x86.h@ 12347

Last change on this file since 12347 was 12225, checked in by vboxsync, 16 years ago
VMM: X86_DR7_ENABLED_MASK should not include GD, because it isn't a breakpoint and including it will break assumptions in CPUMRecalcHyperDRx (DBGFBpGetDR7 always returns GD).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 84.1 KB

Line
1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39
40	/* Workaround for Solaris sys/regset.h defining CS, DS */
41	#if defined(RT_OS_SOLARIS)
42	# undef CS
43	# undef DS
44	#endif
45
46	/** @defgroup grp_x86 x86 Types and Definitions
47	* @{
48	*/
49
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105	/**
106	* EFLAGS.
107	*/
108	typedef union X86EFLAGS
109	{
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	/** The plain unsigned view. */
121	uint32_t u;
122	} X86EFLAGS;
123	/** Pointer to EFLAGS. */
124	typedef X86EFLAGS *PX86EFLAGS;
125	/** Pointer to const EFLAGS. */
126	typedef const X86EFLAGS *PCX86EFLAGS;
127
128	/**
129	* RFLAGS (32 upper bits are reserved).
130	*/
131	typedef union X86RFLAGS
132	{
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	/** The plain unsigned view. */
146	uint64_t u;
147	} X86RFLAGS;
148	/** Pointer to RFLAGS. */
149	typedef X86RFLAGS *PX86RFLAGS;
150	/** Pointer to const RFLAGS. */
151	typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154	/** @name EFLAGS
155	* @{
156	*/
157	/** Bit 0 - CF - Carry flag - Status flag. */
158	#define X86_EFL_CF RT_BIT(0)
159	/** Bit 2 - PF - Parity flag - Status flag. */
160	#define X86_EFL_PF RT_BIT(2)
161	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162	#define X86_EFL_AF RT_BIT(4)
163	/** Bit 6 - ZF - Zero flag - Status flag. */
164	#define X86_EFL_ZF RT_BIT(6)
165	/** Bit 7 - SF - Signed flag - Status flag. */
166	#define X86_EFL_SF RT_BIT(7)
167	/** Bit 8 - TF - Trap flag - System flag. */
168	#define X86_EFL_TF RT_BIT(8)
169	/** Bit 9 - IF - Interrupt flag - System flag. */
170	#define X86_EFL_IF RT_BIT(9)
171	/** Bit 10 - DF - Direction flag - Control flag. */
172	#define X86_EFL_DF RT_BIT(10)
173	/** Bit 11 - OF - Overflow flag - Status flag. */
174	#define X86_EFL_OF RT_BIT(11)
175	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
177	/** Bit 14 - NT - Nested task flag - System flag. */
178	#define X86_EFL_NT RT_BIT(14)
179	/** Bit 16 - RF - Resume flag - System flag. */
180	#define X86_EFL_RF RT_BIT(16)
181	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182	#define X86_EFL_VM RT_BIT(17)
183	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184	#define X86_EFL_AC RT_BIT(18)
185	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186	#define X86_EFL_VIF RT_BIT(19)
187	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188	#define X86_EFL_VIP RT_BIT(20)
189	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190	#define X86_EFL_ID RT_BIT(21)
191	/** IOPL shift. */
192	#define X86_EFL_IOPL_SHIFT 12
193	/** The the IOPL level from the flags. */
194	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chip. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 23 - POPCOUNT instruction. */
353	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
354
355
356	/** Bit 0 - FPU - x87 FPU on Chip. */
357	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
358	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
359	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
360	/** Bit 2 - DE - Debugging extensions. */
361	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
362	/** Bit 3 - PSE - Page Size Extension. */
363	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
364	/** Bit 4 - TSC - Time Stamp Counter. */
365	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
366	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
367	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
368	/** Bit 6 - PAE - Physical Address Extension. */
369	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
370	/** Bit 7 - MCE - Machine Check Exception. */
371	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
372	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
373	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
374	/** Bit 9 - APIC - APIC On-Chip. */
375	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
376	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
377	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
378	/** Bit 12 - MTRR - Memory Type Range Registers. */
379	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
380	/** Bit 13 - PGE - PTE Global Bit. */
381	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
382	/** Bit 14 - MCA - Machine Check Architecture. */
383	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
384	/** Bit 15 - CMOV - Conditional Move Instructions. */
385	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
386	/** Bit 16 - PAT - Page Attribute Table. */
387	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
388	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
389	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
390	/** Bit 18 - PSN - Processor Serial Number. */
391	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
392	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
393	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
394	/** Bit 21 - DS - Debug Store. */
395	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
396	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
397	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
398	/** Bit 23 - MMX - Intel MMX Technology. */
399	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
402	/** Bit 25 - SSE - SSE Support. */
403	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
406	/** Bit 27 - SS - Self Snoop. */
407	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
410	/** Bit 29 - TM - Therm. Monitor. */
411	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
412	/** Bit 31 - PBE - Pending Break Enabled. */
413	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
414	/** @} */
415
416
417	/** @name CPUID AMD Feature information.
418	* CPUID query with EAX=0x80000001.
419	* @{
420	*/
421	/** Bit 0 - FPU - x87 FPU on Chip. */
422	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
423	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
424	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
425	/** Bit 2 - DE - Debugging extensions. */
426	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
427	/** Bit 3 - PSE - Page Size Extension. */
428	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
429	/** Bit 4 - TSC - Time Stamp Counter. */
430	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
431	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
432	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
433	/** Bit 6 - PAE - Physical Address Extension. */
434	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
435	/** Bit 7 - MCE - Machine Check Exception. */
436	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
437	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
438	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
439	/** Bit 9 - APIC - APIC On-Chip. */
440	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
441	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
442	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
443	/** Bit 12 - MTRR - Memory Type Range Registers. */
444	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
445	/** Bit 13 - PGE - PTE Global Bit. */
446	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
447	/** Bit 14 - MCA - Machine Check Architecture. */
448	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
449	/** Bit 15 - CMOV - Conditional Move Instructions. */
450	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
451	/** Bit 16 - PAT - Page Attribute Table. */
452	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
453	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
455	/** Bit 20 - NX - AMD No-Execute Page Protection. */
456	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
457	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
458	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
459	/** Bit 23 - MMX - Intel MMX Technology. */
460	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
461	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
462	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
463	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
465	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
466	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
467	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
468	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
469	/** Bit 29 - LM - AMD Long Mode. */
470	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
471	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
472	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
473	/** Bit 31 - 3DNOW - AMD 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
475
476	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
477	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
478	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
480	/** Bit 2 - SVM - AMD VM extensions. */
481	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
482	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
483	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
484	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
485	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
486	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
487	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
488	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
490	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
491	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
492	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
493	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
494	/** Bit 9 - OSVW - AMD OS visible workaround. */
495	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
496	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
497	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
498	/** Bit 13 - WDT - AMD Watchdog timer support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
500
501	/** @} */
502
503
504	/** @name CPUID AMD Feature information.
505	* CPUID query with EAX=0x80000007.
506	* @{
507	*/
508	/** Bit 0 - TS - Temperature Sensor. */
509	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
510	/** Bit 1 - FID - Frequency ID Control. */
511	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
512	/** Bit 2 - VID - Voltage ID Control. */
513	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
514	/** Bit 3 - TTP - THERMTRIP. */
515	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
516	/** Bit 4 - TM - Hardware Thermal Control. */
517	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
518	/** Bit 5 - STC - Software Thermal Control. */
519	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
520	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
521	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
522	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
523	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
524	/** Bit 8 - TSCINVAR - TSC Invariant. */
525	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
526	/** @} */
527
528
529	/** @name CR0
530	* @{ */
531	/** Bit 0 - PE - Protection Enabled */
532	#define X86_CR0_PE RT_BIT(0)
533	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
534	/** Bit 1 - MP - Monitor Coprocessor */
535	#define X86_CR0_MP RT_BIT(1)
536	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
537	/** Bit 2 - EM - Emulation. */
538	#define X86_CR0_EM RT_BIT(2)
539	#define X86_CR0_EMULATE_FPU RT_BIT(2)
540	/** Bit 3 - TS - Task Switch. */
541	#define X86_CR0_TS RT_BIT(3)
542	#define X86_CR0_TASK_SWITCH RT_BIT(3)
543	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
544	#define X86_CR0_ET RT_BIT(4)
545	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
546	/** Bit 5 - NE - Numeric error. */
547	#define X86_CR0_NE RT_BIT(5)
548	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
549	/** Bit 16 - WP - Write Protect. */
550	#define X86_CR0_WP RT_BIT(16)
551	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
552	/** Bit 18 - AM - Alignment Mask. */
553	#define X86_CR0_AM RT_BIT(18)
554	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
555	/** Bit 29 - NW - Not Write-though. */
556	#define X86_CR0_NW RT_BIT(29)
557	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
558	/** Bit 30 - WP - Cache Disable. */
559	#define X86_CR0_CD RT_BIT(30)
560	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
561	/** Bit 31 - PG - Paging. */
562	#define X86_CR0_PG RT_BIT(31)
563	#define X86_CR0_PAGING RT_BIT(31)
564	/** @} */
565
566
567	/** @name CR3
568	* @{ */
569	/** Bit 3 - PWT - Page-level Writes Transparent. */
570	#define X86_CR3_PWT RT_BIT(3)
571	/** Bit 4 - PCD - Page-level Cache Disable. */
572	#define X86_CR3_PCD RT_BIT(4)
573	/** Bits 12-31 - - Page directory page number. */
574	#define X86_CR3_PAGE_MASK (0xfffff000)
575	/** Bits 5-31 - - PAE Page directory page number. */
576	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
577	/** Bits 12-51 - - AMD64 Page directory page number. */
578	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
579	/** @} */
580
581
582	/** @name CR4
583	* @{ */
584	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
585	#define X86_CR4_VME RT_BIT(0)
586	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
587	#define X86_CR4_PVI RT_BIT(1)
588	/** Bit 2 - TSD - Time Stamp Disable. */
589	#define X86_CR4_TSD RT_BIT(2)
590	/** Bit 3 - DE - Debugging Extensions. */
591	#define X86_CR4_DE RT_BIT(3)
592	/** Bit 4 - PSE - Page Size Extension. */
593	#define X86_CR4_PSE RT_BIT(4)
594	/** Bit 5 - PAE - Physical Address Extension. */
595	#define X86_CR4_PAE RT_BIT(5)
596	/** Bit 6 - MCE - Machine-Check Enable. */
597	#define X86_CR4_MCE RT_BIT(6)
598	/** Bit 7 - PGE - Page Global Enable. */
599	#define X86_CR4_PGE RT_BIT(7)
600	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
601	#define X86_CR4_PCE RT_BIT(8)
602	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
603	#define X86_CR4_OSFSXR RT_BIT(9)
604	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
605	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
606	/** Bit 13 - VMXE - VMX mode is enabled. */
607	#define X86_CR4_VMXE RT_BIT(13)
608	/** @} */
609
610
611	/** @name DR6
612	* @{ */
613	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
614	#define X86_DR6_B0 RT_BIT(0)
615	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
616	#define X86_DR6_B1 RT_BIT(1)
617	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
618	#define X86_DR6_B2 RT_BIT(2)
619	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
620	#define X86_DR6_B3 RT_BIT(3)
621	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
622	#define X86_DR6_BD RT_BIT(13)
623	/** Bit 14 - BS - Single step */
624	#define X86_DR6_BS RT_BIT(14)
625	/** Bit 15 - BT - Task switch. (TSS T bit.) */
626	#define X86_DR6_BT RT_BIT(15)
627	/** Value of DR6 after powerup/reset. */
628	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
629	/** @} */
630
631
632	/** @name DR7
633	* @{ */
634	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
635	#define X86_DR7_L0 RT_BIT(0)
636	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
637	#define X86_DR7_G0 RT_BIT(1)
638	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
639	#define X86_DR7_L1 RT_BIT(2)
640	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
641	#define X86_DR7_G1 RT_BIT(3)
642	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
643	#define X86_DR7_L2 RT_BIT(4)
644	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
645	#define X86_DR7_G2 RT_BIT(5)
646	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
647	#define X86_DR7_L3 RT_BIT(6)
648	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
649	#define X86_DR7_G3 RT_BIT(7)
650	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
651	#define X86_DR7_LE RT_BIT(8)
652	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
653	#define X86_DR7_GE RT_BIT(9)
654
655	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
656	* any DR register is accessed. */
657	#define X86_DR7_GD RT_BIT(13)
658	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
659	#define X86_DR7_RW0_MASK (3 << 16)
660	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
661	#define X86_DR7_LEN0_MASK (3 << 18)
662	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
663	#define X86_DR7_RW1_MASK (3 << 20)
664	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
665	#define X86_DR7_LEN1_MASK (3 << 22)
666	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
667	#define X86_DR7_RW2_MASK (3 << 24)
668	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
669	#define X86_DR7_LEN2_MASK (3 << 26)
670	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
671	#define X86_DR7_RW3_MASK (3 << 28)
672	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
673	#define X86_DR7_LEN3_MASK (3 << 30)
674
675	/** Bits which must be 1s. */
676	#define X86_DR7_MB1_MASK (RT_BIT(10))
677
678	/** Calcs the L bit of Nth breakpoint.
679	* @param iBp The breakpoint number [0..3].
680	*/
681	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
682
683	/** Calcs the G bit of Nth breakpoint.
684	* @param iBp The breakpoint number [0..3].
685	*/
686	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
687
688	/** @name Read/Write values.
689	* @{ */
690	/** Break on instruction fetch only. */
691	#define X86_DR7_RW_EO 0
692	/** Break on write only. */
693	#define X86_DR7_RW_WO 1
694	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
695	#define X86_DR7_RW_IO 2
696	/** Break on read or write (but not instruction fetches). */
697	#define X86_DR7_RW_RW 3
698	/** @} */
699
700	/** Shifts a X86_DR7_RW_* value to its right place.
701	* @param iBp The breakpoint number [0..3].
702	* @param fRw One of the X86_DR7_RW_* value.
703	*/
704	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
705
706	/** @name Length values.
707	* @{ */
708	#define X86_DR7_LEN_BYTE 0
709	#define X86_DR7_LEN_WORD 1
710	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
711	#define X86_DR7_LEN_DWORD 3
712	/** @} */
713
714	/** Shifts a X86_DR7_LEN_* value to its right place.
715	* @param iBp The breakpoint number [0..3].
716	* @param cb One of the X86_DR7_LEN_* values.
717	*/
718	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
719
720	/** Mask used to check if any breakpoints are enabled. */
721	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
722
723	/** @} */
724
725
726	/** @name Machine Specific Registers
727	* @{
728	*/
729
730	/** Time Stamp Counter. */
731	#define MSR_IA32_TSC 0x10
732
733	#define MSR_IA32_PLATFORM_ID 0x17
734
735	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
736	#define MSR_IA32_APICBASE 0x1b
737	#endif
738
739	/** CPU Feature control. */
740	#define MSR_IA32_FEATURE_CONTROL 0x3A
741	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
742	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
743
744	/** BIOS update trigger (microcode update). */
745	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
746
747	/** BIOS update signature (microcode). */
748	#define MSR_IA32_BIOS_SIGN_ID 0x8B
749
750	/** MTRR Capabilities. */
751	#define MSR_IA32_MTRR_CAP 0xFE
752
753
754	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
755	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
756	* R0 SS == CS + 8
757	* R3 CS == CS + 16
758	* R3 SS == CS + 24
759	*/
760	#define MSR_IA32_SYSENTER_CS 0x174
761	/** SYSENTER_ESP - the R0 ESP. */
762	#define MSR_IA32_SYSENTER_ESP 0x175
763	/** SYSENTER_EIP - the R0 EIP. */
764	#define MSR_IA32_SYSENTER_EIP 0x176
765	#endif
766
767	/** Machine Check Global Capabilities Register. */
768	#define MSR_IA32_MCP_CAP 0x179
769	/** Machine Check Global Status Register. */
770	#define MSR_IA32_MCP_STATUS 0x17A
771	/** Machine Check Global Control Register. */
772	#define MSR_IA32_MCP_CTRL 0x17B
773
774	/* Page Attribute Table. */
775	#define MSR_IA32_CR_PAT 0x277
776
777	/** MTRR Default Range. */
778	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
779
780	#define MSR_IA32_MC0_CTL 0x400
781	#define MSR_IA32_MC0_STATUS 0x401
782
783	/** Basic VMX information. */
784	#define MSR_IA32_VMX_BASIC_INFO 0x480
785	/** Allowed settings for pin-based VM execution controls */
786	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
787	/** Allowed settings for proc-based VM execution controls */
788	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
789	/** Allowed settings for the VMX exit controls. */
790	#define MSR_IA32_VMX_EXIT_CTLS 0x483
791	/** Allowed settings for the VMX entry controls. */
792	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
793	/** Misc VMX info. */
794	#define MSR_IA32_VMX_MISC 0x485
795	/** Fixed cleared bits in CR0. */
796	#define MSR_IA32_VMX_CR0_FIXED0 0x486
797	/** Fixed set bits in CR0. */
798	#define MSR_IA32_VMX_CR0_FIXED1 0x487
799	/** Fixed cleared bits in CR4. */
800	#define MSR_IA32_VMX_CR4_FIXED0 0x488
801	/** Fixed set bits in CR4. */
802	#define MSR_IA32_VMX_CR4_FIXED1 0x489
803	/** Information for enumerating fields in the VMCS. */
804	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
805	/** Allowed settings for secondary proc-based VM execution controls */
806	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
807	/** EPT capabilities. */
808	#define MSR_IA32_VMX_EPT_CAPS 0x48C
809
810	/** K6 EFER - Extended Feature Enable Register. */
811	#define MSR_K6_EFER 0xc0000080
812	/** @todo document EFER */
813	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
814	#define MSR_K6_EFER_SCE RT_BIT(0)
815	/** Bit 8 - LME - Long mode enabled. (R/W) */
816	#define MSR_K6_EFER_LME RT_BIT(8)
817	/** Bit 10 - LMA - Long mode active. (R) */
818	#define MSR_K6_EFER_LMA RT_BIT(10)
819	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
820	#define MSR_K6_EFER_NXE RT_BIT(11)
821	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
822	#define MSR_K6_EFER_SVME RT_BIT(12)
823	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
824	#define MSR_K6_EFER_LMSLE RT_BIT(13)
825	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
826	#define MSR_K6_EFER_FFXSR RT_BIT(14)
827	/** K6 STAR - SYSCALL/RET targets. */
828	#define MSR_K6_STAR 0xc0000081
829	/** Shift value for getting the SYSRET CS and SS value. */
830	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
831	/** Shift value for getting the SYSCALL CS and SS value. */
832	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
833	/** Selector mask for use after shifting. */
834	#define MSR_K6_STAR_SEL_MASK 0xffff
835	/** The mask which give the SYSCALL EIP. */
836	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
837	/** K6 WHCR - Write Handling Control Register. */
838	#define MSR_K6_WHCR 0xc0000082
839	/** K6 UWCCR - UC/WC Cacheability Control Register. */
840	#define MSR_K6_UWCCR 0xc0000085
841	/** K6 PSOR - Processor State Observability Register. */
842	#define MSR_K6_PSOR 0xc0000087
843	/** K6 PFIR - Page Flush/Invalidate Register. */
844	#define MSR_K6_PFIR 0xc0000088
845
846	#define MSR_K7_EVNTSEL0 0xc0010000
847	#define MSR_K7_EVNTSEL1 0xc0010001
848	#define MSR_K7_EVNTSEL2 0xc0010002
849	#define MSR_K7_EVNTSEL3 0xc0010003
850	#define MSR_K7_PERFCTR0 0xc0010004
851	#define MSR_K7_PERFCTR1 0xc0010005
852	#define MSR_K7_PERFCTR2 0xc0010006
853	#define MSR_K7_PERFCTR3 0xc0010007
854
855	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
856	#define MSR_K8_LSTAR 0xc0000082
857	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
858	#define MSR_K8_CSTAR 0xc0000083
859	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
860	#define MSR_K8_SF_MASK 0xc0000084
861	/** K8 FS.base - The 64-bit base FS register. */
862	#define MSR_K8_FS_BASE 0xc0000100
863	/** K8 GS.base - The 64-bit base GS register. */
864	#define MSR_K8_GS_BASE 0xc0000101
865	/** K8 KernelGSbase - Used with SWAPGS. */
866	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
867	#define MSR_K8_TSC_AUX 0xc0000103
868	#define MSR_K8_SYSCFG 0xc0010010
869	#define MSR_K8_HWCR 0xc0010015
870	#define MSR_K8_IORRBASE0 0xc0010016
871	#define MSR_K8_IORRMASK0 0xc0010017
872	#define MSR_K8_IORRBASE1 0xc0010018
873	#define MSR_K8_IORRMASK1 0xc0010019
874	#define MSR_K8_TOP_MEM1 0xc001001a
875	#define MSR_K8_TOP_MEM2 0xc001001d
876	#define MSR_K8_VM_CR 0xc0010114
877	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
878
879	#define MSR_K8_IGNNE 0xc0010115
880	#define MSR_K8_SMM_CTL 0xc0010116
881	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
882	* host state during world switch.
883	*/
884	#define MSR_K8_VM_HSAVE_PA 0xc0010117
885
886	/** @} */
887
888
889	/** @name Page Table / Directory / Directory Pointers / L4.
890	* @{
891	*/
892
893	/** Page table/directory entry as an unsigned integer. */
894	typedef uint32_t X86PGUINT;
895	/** Pointer to a page table/directory table entry as an unsigned integer. */
896	typedef X86PGUINT *PX86PGUINT;
897
898	/** Number of entries in a 32-bit PT/PD. */
899	#define X86_PG_ENTRIES 1024
900
901
902	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
903	typedef uint64_t X86PGPAEUINT;
904	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
905	typedef X86PGPAEUINT *PX86PGPAEUINT;
906
907	/** Number of entries in a PAE PT/PD. */
908	#define X86_PG_PAE_ENTRIES 512
909	/** Number of entries in a PAE PDPT. */
910	#define X86_PG_PAE_PDPE_ENTRIES 4
911
912	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
913	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
914	/** Number of entries in an AMD64 PDPT.
915	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
916	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
917
918	/** The size of a 4KB page. */
919	#define X86_PAGE_4K_SIZE _4K
920	/** The page shift of a 4KB page. */
921	#define X86_PAGE_4K_SHIFT 12
922	/** The 4KB page offset mask. */
923	#define X86_PAGE_4K_OFFSET_MASK 0xfff
924	/** The 4KB page base mask for virtual addresses. */
925	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
926	/** The 4KB page base mask for virtual addresses - 32bit version. */
927	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
928
929	/** The size of a 2MB page. */
930	#define X86_PAGE_2M_SIZE _2M
931	/** The page shift of a 2MB page. */
932	#define X86_PAGE_2M_SHIFT 21
933	/** The 2MB page offset mask. */
934	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
935	/** The 2MB page base mask for virtual addresses. */
936	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
937	/** The 2MB page base mask for virtual addresses - 32bit version. */
938	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
939
940	/** The size of a 4MB page. */
941	#define X86_PAGE_4M_SIZE _4M
942	/** The page shift of a 4MB page. */
943	#define X86_PAGE_4M_SHIFT 22
944	/** The 4MB page offset mask. */
945	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
946	/** The 4MB page base mask for virtual addresses. */
947	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
948	/** The 4MB page base mask for virtual addresses - 32bit version. */
949	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
950
951
952
953	/** @name Page Table Entry
954	* @{
955	*/
956	/** Bit 0 - P - Present bit. */
957	#define X86_PTE_P RT_BIT(0)
958	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
959	#define X86_PTE_RW RT_BIT(1)
960	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
961	#define X86_PTE_US RT_BIT(2)
962	/** Bit 3 - PWT - Page level write thru bit. */
963	#define X86_PTE_PWT RT_BIT(3)
964	/** Bit 4 - PCD - Page level cache disable bit. */
965	#define X86_PTE_PCD RT_BIT(4)
966	/** Bit 5 - A - Access bit. */
967	#define X86_PTE_A RT_BIT(5)
968	/** Bit 6 - D - Dirty bit. */
969	#define X86_PTE_D RT_BIT(6)
970	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
971	#define X86_PTE_PAT RT_BIT(7)
972	/** Bit 8 - G - Global flag. */
973	#define X86_PTE_G RT_BIT(8)
974	/** Bits 9-11 - - Available for use to system software. */
975	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
976	/** Bits 12-31 - - Physical Page number of the next level. */
977	#define X86_PTE_PG_MASK ( 0xfffff000 )
978
979	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
980	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
981	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
982	/** @todo Get rid of the above hack; makes code unreadable. */
983	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
984	#else
985	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
986	#endif
987	/** Bits 63 - NX - PAE - No execution flag. */
988	#define X86_PTE_PAE_NX RT_BIT_64(63)
989
990	/**
991	* Page table entry.
992	*/
993	typedef struct X86PTEBITS
994	{
995	/** Flags whether(=1) or not the page is present. */
996	unsigned u1Present : 1;
997	/** Read(=0) / Write(=1) flag. */
998	unsigned u1Write : 1;
999	/** User(=1) / Supervisor (=0) flag. */
1000	unsigned u1User : 1;
1001	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1002	unsigned u1WriteThru : 1;
1003	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1004	unsigned u1CacheDisable : 1;
1005	/** Accessed flag.
1006	* Indicates that the page have been read or written to. */
1007	unsigned u1Accessed : 1;
1008	/** Dirty flag.
1009	* Indicates that the page have been written to. */
1010	unsigned u1Dirty : 1;
1011	/** Reserved / If PAT enabled, bit 2 of the index. */
1012	unsigned u1PAT : 1;
1013	/** Global flag. (Ignored in all but final level.) */
1014	unsigned u1Global : 1;
1015	/** Available for use to system software. */
1016	unsigned u3Available : 3;
1017	/** Physical Page number of the next level. */
1018	unsigned u20PageNo : 20;
1019	} X86PTEBITS;
1020	/** Pointer to a page table entry. */
1021	typedef X86PTEBITS *PX86PTEBITS;
1022	/** Pointer to a const page table entry. */
1023	typedef const X86PTEBITS *PCX86PTEBITS;
1024
1025	/**
1026	* Page table entry.
1027	*/
1028	typedef union X86PTE
1029	{
1030	/** Bit field view. */
1031	X86PTEBITS n;
1032	/** Unsigned integer view */
1033	X86PGUINT u;
1034	/** 32-bit view. */
1035	uint32_t au32[1];
1036	/** 16-bit view. */
1037	uint16_t au16[2];
1038	/** 8-bit view. */
1039	uint8_t au8[4];
1040	} X86PTE;
1041	/** Pointer to a page table entry. */
1042	typedef X86PTE *PX86PTE;
1043	/** Pointer to a const page table entry. */
1044	typedef const X86PTE *PCX86PTE;
1045
1046
1047	/**
1048	* PAE page table entry.
1049	*/
1050	typedef struct X86PTEPAEBITS
1051	{
1052	/** Flags whether(=1) or not the page is present. */
1053	uint32_t u1Present : 1;
1054	/** Read(=0) / Write(=1) flag. */
1055	uint32_t u1Write : 1;
1056	/** User(=1) / Supervisor(=0) flag. */
1057	uint32_t u1User : 1;
1058	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1059	uint32_t u1WriteThru : 1;
1060	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1061	uint32_t u1CacheDisable : 1;
1062	/** Accessed flag.
1063	* Indicates that the page have been read or written to. */
1064	uint32_t u1Accessed : 1;
1065	/** Dirty flag.
1066	* Indicates that the page have been written to. */
1067	uint32_t u1Dirty : 1;
1068	/** Reserved / If PAT enabled, bit 2 of the index. */
1069	uint32_t u1PAT : 1;
1070	/** Global flag. (Ignored in all but final level.) */
1071	uint32_t u1Global : 1;
1072	/** Available for use to system software. */
1073	uint32_t u3Available : 3;
1074	/** Physical Page number of the next level - Low Part. Don't use this. */
1075	uint32_t u20PageNoLow : 20;
1076	/** Physical Page number of the next level - High Part. Don't use this. */
1077	uint32_t u20PageNoHigh : 20;
1078	/** MBZ bits */
1079	uint32_t u11Reserved : 11;
1080	/** No Execute flag. */
1081	uint32_t u1NoExecute : 1;
1082	} X86PTEPAEBITS;
1083	/** Pointer to a page table entry. */
1084	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1085	/** Pointer to a page table entry. */
1086	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1087
1088	/**
1089	* PAE Page table entry.
1090	*/
1091	typedef union X86PTEPAE
1092	{
1093	/** Bit field view. */
1094	X86PTEPAEBITS n;
1095	/** Unsigned integer view */
1096	X86PGPAEUINT u;
1097	/** 32-bit view. */
1098	uint32_t au32[2];
1099	/** 16-bit view. */
1100	uint16_t au16[4];
1101	/** 8-bit view. */
1102	uint8_t au8[8];
1103	} X86PTEPAE;
1104	/** Pointer to a PAE page table entry. */
1105	typedef X86PTEPAE *PX86PTEPAE;
1106	/** Pointer to a const PAE page table entry. */
1107	typedef const X86PTEPAE *PCX86PTEPAE;
1108	/** @} */
1109
1110	/**
1111	* Page table.
1112	*/
1113	typedef struct X86PT
1114	{
1115	/** PTE Array. */
1116	X86PTE a[X86_PG_ENTRIES];
1117	} X86PT;
1118	/** Pointer to a page table. */
1119	typedef X86PT *PX86PT;
1120	/** Pointer to a const page table. */
1121	typedef const X86PT *PCX86PT;
1122
1123	/** The page shift to get the PT index. */
1124	#define X86_PT_SHIFT 12
1125	/** The PT index mask (apply to a shifted page address). */
1126	#define X86_PT_MASK 0x3ff
1127
1128
1129	/**
1130	* Page directory.
1131	*/
1132	typedef struct X86PTPAE
1133	{
1134	/** PTE Array. */
1135	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1136	} X86PTPAE;
1137	/** Pointer to a page table. */
1138	typedef X86PTPAE *PX86PTPAE;
1139	/** Pointer to a const page table. */
1140	typedef const X86PTPAE *PCX86PTPAE;
1141
1142	/** The page shift to get the PA PTE index. */
1143	#define X86_PT_PAE_SHIFT 12
1144	/** The PAE PT index mask (apply to a shifted page address). */
1145	#define X86_PT_PAE_MASK 0x1ff
1146
1147
1148	/** @name 4KB Page Directory Entry
1149	* @{
1150	*/
1151	/** Bit 0 - P - Present bit. */
1152	#define X86_PDE_P RT_BIT(0)
1153	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1154	#define X86_PDE_RW RT_BIT(1)
1155	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1156	#define X86_PDE_US RT_BIT(2)
1157	/** Bit 3 - PWT - Page level write thru bit. */
1158	#define X86_PDE_PWT RT_BIT(3)
1159	/** Bit 4 - PCD - Page level cache disable bit. */
1160	#define X86_PDE_PCD RT_BIT(4)
1161	/** Bit 5 - A - Access bit. */
1162	#define X86_PDE_A RT_BIT(5)
1163	/** Bit 7 - PS - Page size attribute.
1164	* Clear mean 4KB pages, set means large pages (2/4MB). */
1165	#define X86_PDE_PS RT_BIT(7)
1166	/** Bits 9-11 - - Available for use to system software. */
1167	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1168	/** Bits 12-31 - - Physical Page number of the next level. */
1169	#define X86_PDE_PG_MASK ( 0xfffff000 )
1170
1171	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1172	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1173	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1174	* we partly or that part into shadow page table entries. Will be corrected
1175	* soon.
1176	*/
1177	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1178	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1179	#else
1180	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1181	#endif
1182	/** Bits 63 - NX - PAE - No execution flag. */
1183	#define X86_PDE_PAE_NX RT_BIT_64(63)
1184
1185	/**
1186	* Page directory entry.
1187	*/
1188	typedef struct X86PDEBITS
1189	{
1190	/** Flags whether(=1) or not the page is present. */
1191	unsigned u1Present : 1;
1192	/** Read(=0) / Write(=1) flag. */
1193	unsigned u1Write : 1;
1194	/** User(=1) / Supervisor (=0) flag. */
1195	unsigned u1User : 1;
1196	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1197	unsigned u1WriteThru : 1;
1198	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1199	unsigned u1CacheDisable : 1;
1200	/** Accessed flag.
1201	* Indicates that the page have been read or written to. */
1202	unsigned u1Accessed : 1;
1203	/** Reserved / Ignored (dirty bit). */
1204	unsigned u1Reserved0 : 1;
1205	/** Size bit if PSE is enabled - in any event it's 0. */
1206	unsigned u1Size : 1;
1207	/** Reserved / Ignored (global bit). */
1208	unsigned u1Reserved1 : 1;
1209	/** Available for use to system software. */
1210	unsigned u3Available : 3;
1211	/** Physical Page number of the next level. */
1212	unsigned u20PageNo : 20;
1213	} X86PDEBITS;
1214	/** Pointer to a page directory entry. */
1215	typedef X86PDEBITS *PX86PDEBITS;
1216	/** Pointer to a const page directory entry. */
1217	typedef const X86PDEBITS *PCX86PDEBITS;
1218
1219
1220	/**
1221	* PAE page directory entry.
1222	*/
1223	typedef struct X86PDEPAEBITS
1224	{
1225	/** Flags whether(=1) or not the page is present. */
1226	uint32_t u1Present : 1;
1227	/** Read(=0) / Write(=1) flag. */
1228	uint32_t u1Write : 1;
1229	/** User(=1) / Supervisor (=0) flag. */
1230	uint32_t u1User : 1;
1231	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1232	uint32_t u1WriteThru : 1;
1233	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1234	uint32_t u1CacheDisable : 1;
1235	/** Accessed flag.
1236	* Indicates that the page have been read or written to. */
1237	uint32_t u1Accessed : 1;
1238	/** Reserved / Ignored (dirty bit). */
1239	uint32_t u1Reserved0 : 1;
1240	/** Size bit if PSE is enabled - in any event it's 0. */
1241	uint32_t u1Size : 1;
1242	/** Reserved / Ignored (global bit). / */
1243	uint32_t u1Reserved1 : 1;
1244	/** Available for use to system software. */
1245	uint32_t u3Available : 3;
1246	/** Physical Page number of the next level - Low Part. Don't use! */
1247	uint32_t u20PageNoLow : 20;
1248	/** Physical Page number of the next level - High Part. Don't use! */
1249	uint32_t u20PageNoHigh : 20;
1250	/** MBZ bits */
1251	uint32_t u11Reserved : 11;
1252	/** No Execute flag. */
1253	uint32_t u1NoExecute : 1;
1254	} X86PDEPAEBITS;
1255	/** Pointer to a page directory entry. */
1256	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1257	/** Pointer to a const page directory entry. */
1258	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1259
1260	/** @} */
1261
1262
1263	/** @name 2/4MB Page Directory Entry
1264	* @{
1265	*/
1266	/** Bit 0 - P - Present bit. */
1267	#define X86_PDE4M_P RT_BIT(0)
1268	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1269	#define X86_PDE4M_RW RT_BIT(1)
1270	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1271	#define X86_PDE4M_US RT_BIT(2)
1272	/** Bit 3 - PWT - Page level write thru bit. */
1273	#define X86_PDE4M_PWT RT_BIT(3)
1274	/** Bit 4 - PCD - Page level cache disable bit. */
1275	#define X86_PDE4M_PCD RT_BIT(4)
1276	/** Bit 5 - A - Access bit. */
1277	#define X86_PDE4M_A RT_BIT(5)
1278	/** Bit 6 - D - Dirty bit. */
1279	#define X86_PDE4M_D RT_BIT(6)
1280	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1281	#define X86_PDE4M_PS RT_BIT(7)
1282	/** Bit 8 - G - Global flag. */
1283	#define X86_PDE4M_G RT_BIT(8)
1284	/** Bits 9-11 - AVL - Available for use to system software. */
1285	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1286	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1287	#define X86_PDE4M_PAT RT_BIT(12)
1288	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1289	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1290	/** Bits 22-31 - - Physical Page number. */
1291	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1292	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1293	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1294	/** The number of bits to the high part of the page number. */
1295	#define X86_PDE4M_PG_HIGH_SHIFT 19
1296
1297	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1298	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1299	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1300	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1301	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1302
1303	/**
1304	* 4MB page directory entry.
1305	*/
1306	typedef struct X86PDE4MBITS
1307	{
1308	/** Flags whether(=1) or not the page is present. */
1309	unsigned u1Present : 1;
1310	/** Read(=0) / Write(=1) flag. */
1311	unsigned u1Write : 1;
1312	/** User(=1) / Supervisor (=0) flag. */
1313	unsigned u1User : 1;
1314	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1315	unsigned u1WriteThru : 1;
1316	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1317	unsigned u1CacheDisable : 1;
1318	/** Accessed flag.
1319	* Indicates that the page have been read or written to. */
1320	unsigned u1Accessed : 1;
1321	/** Dirty flag.
1322	* Indicates that the page have been written to. */
1323	unsigned u1Dirty : 1;
1324	/** Page size flag - always 1 for 4MB entries. */
1325	unsigned u1Size : 1;
1326	/** Global flag. */
1327	unsigned u1Global : 1;
1328	/** Available for use to system software. */
1329	unsigned u3Available : 3;
1330	/** Reserved / If PAT enabled, bit 2 of the index. */
1331	unsigned u1PAT : 1;
1332	/** Bits 32-39 of the page number on AMD64.
1333	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1334	unsigned u8PageNoHigh : 8;
1335	/** Reserved. */
1336	unsigned u1Reserved : 1;
1337	/** Physical Page number of the page. */
1338	unsigned u10PageNo : 10;
1339	} X86PDE4MBITS;
1340	/** Pointer to a page table entry. */
1341	typedef X86PDE4MBITS *PX86PDE4MBITS;
1342	/** Pointer to a const page table entry. */
1343	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1344
1345
1346	/**
1347	* 2MB PAE page directory entry.
1348	*/
1349	typedef struct X86PDE2MPAEBITS
1350	{
1351	/** Flags whether(=1) or not the page is present. */
1352	uint32_t u1Present : 1;
1353	/** Read(=0) / Write(=1) flag. */
1354	uint32_t u1Write : 1;
1355	/** User(=1) / Supervisor(=0) flag. */
1356	uint32_t u1User : 1;
1357	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1358	uint32_t u1WriteThru : 1;
1359	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1360	uint32_t u1CacheDisable : 1;
1361	/** Accessed flag.
1362	* Indicates that the page have been read or written to. */
1363	uint32_t u1Accessed : 1;
1364	/** Dirty flag.
1365	* Indicates that the page have been written to. */
1366	uint32_t u1Dirty : 1;
1367	/** Page size flag - always 1 for 2MB entries. */
1368	uint32_t u1Size : 1;
1369	/** Global flag. */
1370	uint32_t u1Global : 1;
1371	/** Available for use to system software. */
1372	uint32_t u3Available : 3;
1373	/** Reserved / If PAT enabled, bit 2 of the index. */
1374	uint32_t u1PAT : 1;
1375	/** Reserved. */
1376	uint32_t u9Reserved : 9;
1377	/** Physical Page number of the next level - Low part. Don't use! */
1378	uint32_t u10PageNoLow : 10;
1379	/** Physical Page number of the next level - High part. Don't use! */
1380	uint32_t u20PageNoHigh : 20;
1381	/** MBZ bits */
1382	uint32_t u11Reserved : 11;
1383	/** No Execute flag. */
1384	uint32_t u1NoExecute : 1;
1385	} X86PDE2MPAEBITS;
1386	/** Pointer to a 4MB PAE page table entry. */
1387	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1388	/** Pointer to a 4MB PAE page table entry. */
1389	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1390
1391	/** @} */
1392
1393	/**
1394	* Page directory entry.
1395	*/
1396	typedef union X86PDE
1397	{
1398	/** Normal view. */
1399	X86PDEBITS n;
1400	/** 4MB view (big). */
1401	X86PDE4MBITS b;
1402	/** Unsigned integer view. */
1403	X86PGUINT u;
1404	/** 8 bit unsigned integer view. */
1405	uint8_t au8[4];
1406	/** 16 bit unsigned integer view. */
1407	uint16_t au16[2];
1408	/** 32 bit unsigned integer view. */
1409	uint32_t au32[1];
1410	} X86PDE;
1411	/** Pointer to a page directory entry. */
1412	typedef X86PDE *PX86PDE;
1413	/** Pointer to a const page directory entry. */
1414	typedef const X86PDE *PCX86PDE;
1415
1416	/**
1417	* PAE page directory entry.
1418	*/
1419	typedef union X86PDEPAE
1420	{
1421	/** Normal view. */
1422	X86PDEPAEBITS n;
1423	/** 2MB page view (big). */
1424	X86PDE2MPAEBITS b;
1425	/** Unsigned integer view. */
1426	X86PGPAEUINT u;
1427	/** 8 bit unsigned integer view. */
1428	uint8_t au8[8];
1429	/** 16 bit unsigned integer view. */
1430	uint16_t au16[4];
1431	/** 32 bit unsigned integer view. */
1432	uint32_t au32[2];
1433	} X86PDEPAE;
1434	/** Pointer to a page directory entry. */
1435	typedef X86PDEPAE *PX86PDEPAE;
1436	/** Pointer to a const page directory entry. */
1437	typedef const X86PDEPAE *PCX86PDEPAE;
1438
1439	/**
1440	* Page directory.
1441	*/
1442	typedef struct X86PD
1443	{
1444	/** PDE Array. */
1445	X86PDE a[X86_PG_ENTRIES];
1446	} X86PD;
1447	/** Pointer to a page directory. */
1448	typedef X86PD *PX86PD;
1449	/** Pointer to a const page directory. */
1450	typedef const X86PD *PCX86PD;
1451
1452	/** The page shift to get the PD index. */
1453	#define X86_PD_SHIFT 22
1454	/** The PD index mask (apply to a shifted page address). */
1455	#define X86_PD_MASK 0x3ff
1456
1457
1458	/**
1459	* PAE page directory.
1460	*/
1461	typedef struct X86PDPAE
1462	{
1463	/** PDE Array. */
1464	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1465	} X86PDPAE;
1466	/** Pointer to a PAE page directory. */
1467	typedef X86PDPAE *PX86PDPAE;
1468	/** Pointer to a const PAE page directory. */
1469	typedef const X86PDPAE *PCX86PDPAE;
1470
1471	/** The page shift to get the PAE PD index. */
1472	#define X86_PD_PAE_SHIFT 21
1473	/** The PAE PD index mask (apply to a shifted page address). */
1474	#define X86_PD_PAE_MASK 0x1ff
1475
1476
1477	/** @name Page Directory Pointer Table Entry (PAE)
1478	* @{
1479	*/
1480	/** Bit 0 - P - Present bit. */
1481	#define X86_PDPE_P RT_BIT(0)
1482	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1483	#define X86_PDPE_RW RT_BIT(1)
1484	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1485	#define X86_PDPE_US RT_BIT(2)
1486	/** Bit 3 - PWT - Page level write thru bit. */
1487	#define X86_PDPE_PWT RT_BIT(3)
1488	/** Bit 4 - PCD - Page level cache disable bit. */
1489	#define X86_PDPE_PCD RT_BIT(4)
1490	/** Bit 5 - A - Access bit. Long Mode only. */
1491	#define X86_PDPE_A RT_BIT(5)
1492	/** Bits 9-11 - - Available for use to system software. */
1493	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1494	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1495	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1496	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1497	/** @todo Get rid of the above hack; makes code unreadable. */
1498	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1499	#else
1500	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1501	#endif
1502	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1503	#define X86_PDPE_NX RT_BIT_64(63)
1504
1505	/**
1506	* Page directory pointer table entry.
1507	*/
1508	typedef struct X86PDPEBITS
1509	{
1510	/** Flags whether(=1) or not the page is present. */
1511	uint32_t u1Present : 1;
1512	/** Chunk of reserved bits. */
1513	uint32_t u2Reserved : 2;
1514	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1515	uint32_t u1WriteThru : 1;
1516	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1517	uint32_t u1CacheDisable : 1;
1518	/** Chunk of reserved bits. */
1519	uint32_t u4Reserved : 4;
1520	/** Available for use to system software. */
1521	uint32_t u3Available : 3;
1522	/** Physical Page number of the next level - Low Part. Don't use! */
1523	uint32_t u20PageNoLow : 20;
1524	/** Physical Page number of the next level - High Part. Don't use! */
1525	uint32_t u20PageNoHigh : 20;
1526	/** MBZ bits */
1527	uint32_t u12Reserved : 12;
1528	} X86PDPEBITS;
1529	/** Pointer to a page directory pointer table entry. */
1530	typedef X86PDPEBITS *PX86PTPEBITS;
1531	/** Pointer to a const page directory pointer table entry. */
1532	typedef const X86PDPEBITS *PCX86PTPEBITS;
1533
1534	/**
1535	* Page directory pointer table entry. AMD64 version
1536	*/
1537	typedef struct X86PDPEAMD64BITS
1538	{
1539	/** Flags whether(=1) or not the page is present. */
1540	uint32_t u1Present : 1;
1541	/** Read(=0) / Write(=1) flag. */
1542	uint32_t u1Write : 1;
1543	/** User(=1) / Supervisor (=0) flag. */
1544	uint32_t u1User : 1;
1545	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1546	uint32_t u1WriteThru : 1;
1547	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1548	uint32_t u1CacheDisable : 1;
1549	/** Accessed flag.
1550	* Indicates that the page have been read or written to. */
1551	uint32_t u1Accessed : 1;
1552	/** Chunk of reserved bits. */
1553	uint32_t u3Reserved : 3;
1554	/** Available for use to system software. */
1555	uint32_t u3Available : 3;
1556	/** Physical Page number of the next level - Low Part. Don't use! */
1557	uint32_t u20PageNoLow : 20;
1558	/** Physical Page number of the next level - High Part. Don't use! */
1559	uint32_t u20PageNoHigh : 20;
1560	/** MBZ bits */
1561	uint32_t u11Reserved : 11;
1562	/** No Execute flag. */
1563	uint32_t u1NoExecute : 1;
1564	} X86PDPEAMD64BITS;
1565	/** Pointer to a page directory pointer table entry. */
1566	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1567	/** Pointer to a const page directory pointer table entry. */
1568	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1569
1570	/**
1571	* Page directory pointer table entry.
1572	*/
1573	typedef union X86PDPE
1574	{
1575	/** Normal view. */
1576	X86PDPEBITS n;
1577	/** AMD64 view. */
1578	X86PDPEAMD64BITS lm;
1579	/** Unsigned integer view. */
1580	X86PGPAEUINT u;
1581	/** 8 bit unsigned integer view. */
1582	uint8_t au8[8];
1583	/** 16 bit unsigned integer view. */
1584	uint16_t au16[4];
1585	/** 32 bit unsigned integer view. */
1586	uint32_t au32[2];
1587	} X86PDPE;
1588	/** Pointer to a page directory pointer table entry. */
1589	typedef X86PDPE *PX86PDPE;
1590	/** Pointer to a const page directory pointer table entry. */
1591	typedef const X86PDPE *PCX86PDPE;
1592
1593
1594	/**
1595	* Page directory pointer table.
1596	*/
1597	typedef struct X86PDPT
1598	{
1599	/** PDE Array. */
1600	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1601	} X86PDPT;
1602	/** Pointer to a page directory pointer table. */
1603	typedef X86PDPT *PX86PDPT;
1604	/** Pointer to a const page directory pointer table. */
1605	typedef const X86PDPT *PCX86PDPT;
1606
1607	/** The page shift to get the PDPT index. */
1608	#define X86_PDPT_SHIFT 30
1609	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1610	#define X86_PDPT_MASK_PAE 0x3
1611	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1612	#define X86_PDPT_MASK_AMD64 0x1ff
1613
1614	/** @} */
1615
1616
1617	/** @name Page Map Level-4 Entry (Long Mode PAE)
1618	* @{
1619	*/
1620	/** Bit 0 - P - Present bit. */
1621	#define X86_PML4E_P RT_BIT(0)
1622	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1623	#define X86_PML4E_RW RT_BIT(1)
1624	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1625	#define X86_PML4E_US RT_BIT(2)
1626	/** Bit 3 - PWT - Page level write thru bit. */
1627	#define X86_PML4E_PWT RT_BIT(3)
1628	/** Bit 4 - PCD - Page level cache disable bit. */
1629	#define X86_PML4E_PCD RT_BIT(4)
1630	/** Bit 5 - A - Access bit. */
1631	#define X86_PML4E_A RT_BIT(5)
1632	/** Bits 9-11 - - Available for use to system software. */
1633	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1634	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1635	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1636	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1637	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1638	#else
1639	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1640	#endif
1641	/** Bits 63 - NX - PAE - No execution flag. */
1642	#define X86_PML4E_NX RT_BIT_64(63)
1643
1644	/**
1645	* Page Map Level-4 Entry
1646	*/
1647	typedef struct X86PML4EBITS
1648	{
1649	/** Flags whether(=1) or not the page is present. */
1650	uint32_t u1Present : 1;
1651	/** Read(=0) / Write(=1) flag. */
1652	uint32_t u1Write : 1;
1653	/** User(=1) / Supervisor (=0) flag. */
1654	uint32_t u1User : 1;
1655	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1656	uint32_t u1WriteThru : 1;
1657	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1658	uint32_t u1CacheDisable : 1;
1659	/** Accessed flag.
1660	* Indicates that the page have been read or written to. */
1661	uint32_t u1Accessed : 1;
1662	/** Chunk of reserved bits. */
1663	uint32_t u3Reserved : 3;
1664	/** Available for use to system software. */
1665	uint32_t u3Available : 3;
1666	/** Physical Page number of the next level - Low Part. Don't use! */
1667	uint32_t u20PageNoLow : 20;
1668	/** Physical Page number of the next level - High Part. Don't use! */
1669	uint32_t u20PageNoHigh : 20;
1670	/** MBZ bits */
1671	uint32_t u11Reserved : 11;
1672	/** No Execute flag. */
1673	uint32_t u1NoExecute : 1;
1674	} X86PML4EBITS;
1675	/** Pointer to a page map level-4 entry. */
1676	typedef X86PML4EBITS *PX86PML4EBITS;
1677	/** Pointer to a const page map level-4 entry. */
1678	typedef const X86PML4EBITS *PCX86PML4EBITS;
1679
1680	/**
1681	* Page Map Level-4 Entry.
1682	*/
1683	typedef union X86PML4E
1684	{
1685	/** Normal view. */
1686	X86PML4EBITS n;
1687	/** Unsigned integer view. */
1688	X86PGPAEUINT u;
1689	/** 8 bit unsigned integer view. */
1690	uint8_t au8[8];
1691	/** 16 bit unsigned integer view. */
1692	uint16_t au16[4];
1693	/** 32 bit unsigned integer view. */
1694	uint32_t au32[2];
1695	} X86PML4E;
1696	/** Pointer to a page map level-4 entry. */
1697	typedef X86PML4E *PX86PML4E;
1698	/** Pointer to a const page map level-4 entry. */
1699	typedef const X86PML4E *PCX86PML4E;
1700
1701
1702	/**
1703	* Page Map Level-4.
1704	*/
1705	typedef struct X86PML4
1706	{
1707	/** PDE Array. */
1708	X86PML4E a[X86_PG_PAE_ENTRIES];
1709	} X86PML4;
1710	/** Pointer to a page map level-4. */
1711	typedef X86PML4 *PX86PML4;
1712	/** Pointer to a const page map level-4. */
1713	typedef const X86PML4 *PCX86PML4;
1714
1715	/** The page shift to get the PML4 index. */
1716	#define X86_PML4_SHIFT 39
1717	/** The PML4 index mask (apply to a shifted page address). */
1718	#define X86_PML4_MASK 0x1ff
1719
1720	/** @} */
1721
1722	/** @} */
1723
1724
1725	/**
1726	* 80-bit MMX/FPU register type.
1727	*/
1728	typedef struct X86FPUMMX
1729	{
1730	uint8_t reg[10];
1731	} X86FPUMMX;
1732	/** Pointer to a 80-bit MMX/FPU register type. */
1733	typedef X86FPUMMX *PX86FPUMMX;
1734	/** Pointer to a const 80-bit MMX/FPU register type. */
1735	typedef const X86FPUMMX *PCX86FPUMMX;
1736
1737	/**
1738	* FPU state (aka FSAVE/FRSTOR Memory Region).
1739	*/
1740	#pragma pack(1)
1741	typedef struct X86FPUSTATE
1742	{
1743	/** Control word. */
1744	uint16_t FCW;
1745	/** Alignment word */
1746	uint16_t Dummy1;
1747	/** Status word. */
1748	uint16_t FSW;
1749	/** Alignment word */
1750	uint16_t Dummy2;
1751	/** Tag word */
1752	uint16_t FTW;
1753	/** Alignment word */
1754	uint16_t Dummy3;
1755
1756	/** Instruction pointer. */
1757	uint32_t FPUIP;
1758	/** Code selector. */
1759	uint16_t CS;
1760	/** Opcode. */
1761	uint16_t FOP;
1762	/** FOO. */
1763	uint32_t FPUOO;
1764	/** FOS. */
1765	uint32_t FPUOS;
1766	/** FPU view - todo. */
1767	X86FPUMMX regs[8];
1768	} X86FPUSTATE;
1769	#pragma pack()
1770	/** Pointer to a FPU state. */
1771	typedef X86FPUSTATE *PX86FPUSTATE;
1772	/** Pointer to a const FPU state. */
1773	typedef const X86FPUSTATE *PCX86FPUSTATE;
1774
1775	/**
1776	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1777	*/
1778	#pragma pack(1)
1779	typedef struct X86FXSTATE
1780	{
1781	/** Control word. */
1782	uint16_t FCW;
1783	/** Status word. */
1784	uint16_t FSW;
1785	/** Tag word (it's a byte actually). */
1786	uint8_t FTW;
1787	uint8_t huh1;
1788	/** Opcode. */
1789	uint16_t FOP;
1790	/** Instruction pointer. */
1791	uint32_t FPUIP;
1792	/** Code selector. */
1793	uint16_t CS;
1794	uint16_t Rsvrd1;
1795	/* - offset 16 - */
1796	/** Data pointer. */
1797	uint32_t FPUDP;
1798	/** Data segment */
1799	uint16_t DS;
1800	uint16_t Rsrvd2;
1801	uint32_t MXCSR;
1802	uint32_t MXCSR_MASK;
1803	/* - offset 32 - */
1804	union
1805	{
1806	/** MMX view. */
1807	uint64_t mmx;
1808	/** FPU view - todo. */
1809	X86FPUMMX fpu;
1810	/** 8-bit view. */
1811	uint8_t au8[16];
1812	/** 16-bit view. */
1813	uint16_t au16[8];
1814	/** 32-bit view. */
1815	uint32_t au32[4];
1816	/** 64-bit view. */
1817	uint64_t au64[2];
1818	/** 128-bit view. (yeah, very helpful) */
1819	uint128_t au128[1];
1820	} aRegs[8];
1821	/* - offset 160 - */
1822	union
1823	{
1824	/** XMM Register view . /
1825	uint128_t xmm;
1826	/** 8-bit view. */
1827	uint8_t au8[16];
1828	/** 16-bit view. */
1829	uint16_t au16[8];
1830	/** 32-bit view. */
1831	uint32_t au32[4];
1832	/** 64-bit view. */
1833	uint64_t au64[2];
1834	/** 128-bit view. (yeah, very helpful) */
1835	uint128_t au128[1];
1836	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1837	/* - offset 416 - */
1838	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1839	} X86FXSTATE;
1840	#pragma pack()
1841	/** Pointer to a FPU Extended state. */
1842	typedef X86FXSTATE *PX86FXSTATE;
1843	/** Pointer to a const FPU Extended state. */
1844	typedef const X86FXSTATE *PCX86FXSTATE;
1845
1846
1847	/** @name Selector Descriptor
1848	* @{
1849	*/
1850
1851	/**
1852	* Generic descriptor table entry
1853	*/
1854	#pragma pack(1)
1855	typedef struct X86DESCGENERIC
1856	{
1857	/** Limit - Low word. */
1858	unsigned u16LimitLow : 16;
1859	/** Base address - lowe word.
1860	* Don't try set this to 24 because MSC is doing studing things then. */
1861	unsigned u16BaseLow : 16;
1862	/** Base address - first 8 bits of high word. */
1863	unsigned u8BaseHigh1 : 8;
1864	/** Segment Type. */
1865	unsigned u4Type : 4;
1866	/** Descriptor Type. System(=0) or code/data selector */
1867	unsigned u1DescType : 1;
1868	/** Descriptor Privelege level. */
1869	unsigned u2Dpl : 2;
1870	/** Flags selector present(=1) or not. */
1871	unsigned u1Present : 1;
1872	/** Segment limit 16-19. */
1873	unsigned u4LimitHigh : 4;
1874	/** Available for system software. */
1875	unsigned u1Available : 1;
1876	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1877	unsigned u1Long : 1;
1878	/** This flags meaning depends on the segment type. Try make sense out
1879	* of the intel manual yourself. */
1880	unsigned u1DefBig : 1;
1881	/** Granularity of the limit. If set 4KB granularity is used, if
1882	* clear byte. */
1883	unsigned u1Granularity : 1;
1884	/** Base address - highest 8 bits. */
1885	unsigned u8BaseHigh2 : 8;
1886	} X86DESCGENERIC;
1887	#pragma pack()
1888	/** Pointer to a generic descriptor entry. */
1889	typedef X86DESCGENERIC *PX86DESCGENERIC;
1890	/** Pointer to a const generic descriptor entry. */
1891	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1892
1893
1894	/**
1895	* Descriptor attributes.
1896	*/
1897	typedef struct X86DESCATTRBITS
1898	{
1899	/** Segment Type. */
1900	unsigned u4Type : 4;
1901	/** Descriptor Type. System(=0) or code/data selector */
1902	unsigned u1DescType : 1;
1903	/** Descriptor Privelege level. */
1904	unsigned u2Dpl : 2;
1905	/** Flags selector present(=1) or not. */
1906	unsigned u1Present : 1;
1907	/** Segment limit 16-19. */
1908	unsigned u4LimitHigh : 4;
1909	/** Available for system software. */
1910	unsigned u1Available : 1;
1911	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1912	unsigned u1Long : 1;
1913	/** This flags meaning depends on the segment type. Try make sense out
1914	* of the intel manual yourself. */
1915	unsigned u1DefBig : 1;
1916	/** Granularity of the limit. If set 4KB granularity is used, if
1917	* clear byte. */
1918	unsigned u1Granularity : 1;
1919	} X86DESCATTRBITS;
1920
1921
1922	#pragma pack(1)
1923	typedef union X86DESCATTR
1924	{
1925	/** Normal view. */
1926	X86DESCATTRBITS n;
1927	/** Unsigned integer view. */
1928	uint32_t u;
1929	} X86DESCATTR;
1930	#pragma pack()
1931
1932	/** Pointer to descriptor attributes. */
1933	typedef X86DESCATTR *PX86DESCATTR;
1934	/** Pointer to const descriptor attributes. */
1935	typedef const X86DESCATTR *PCX86DESCATTR;
1936
1937
1938	/**
1939	* Descriptor table entry.
1940	*/
1941	#pragma pack(1)
1942	typedef union X86DESC
1943	{
1944	/** Generic descriptor view. */
1945	X86DESCGENERIC Gen;
1946	#if 0
1947	/** IDT view. */
1948	VBOXIDTE Idt;
1949	#endif
1950
1951	/** 8 bit unsigned interger view. */
1952	uint8_t au8[8];
1953	/** 16 bit unsigned interger view. */
1954	uint16_t au16[4];
1955	/** 32 bit unsigned interger view. */
1956	uint32_t au32[2];
1957	} X86DESC;
1958	#pragma pack()
1959	/** Pointer to descriptor table entry. */
1960	typedef X86DESC *PX86DESC;
1961	/** Pointer to const descriptor table entry. */
1962	typedef const X86DESC *PCX86DESC;
1963
1964
1965	/** @def X86DESC_BASE
1966	* Return the base address of a descriptor.
1967	*/
1968	#define X86DESC_BASE(desc) \
1969	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
1970	\| ( (desc).Gen.u8BaseHigh1 << 16) \
1971	\| ( (desc).Gen.u16BaseLow ) )
1972
1973	/** @def X86DESC_LIMIT
1974	* Return the limit of a descriptor.
1975	*/
1976	#define X86DESC_LIMIT(desc) \
1977	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
1978	\| ( (desc).Gen.u16LimitLow ) )
1979
1980	/**
1981	* 64 bits generic descriptor table entry
1982	* Note: most of these bits have no meaning in long mode.
1983	*/
1984	#pragma pack(1)
1985	typedef struct X86DESC64GENERIC
1986	{
1987	/** Limit - Low word - IGNORED. */
1988	unsigned u16LimitLow : 16;
1989	/** Base address - lowe word. - IGNORED
1990	* Don't try set this to 24 because MSC is doing studing things then. */
1991	unsigned u16BaseLow : 16;
1992	/** Base address - first 8 bits of high word. - IGNORED */
1993	unsigned u8BaseHigh1 : 8;
1994	/** Segment Type. */
1995	unsigned u4Type : 4;
1996	/** Descriptor Type. System(=0) or code/data selector */
1997	unsigned u1DescType : 1;
1998	/** Descriptor Privelege level. */
1999	unsigned u2Dpl : 2;
2000	/** Flags selector present(=1) or not. */
2001	unsigned u1Present : 1;
2002	/** Segment limit 16-19. - IGNORED */
2003	unsigned u4LimitHigh : 4;
2004	/** Available for system software. - IGNORED */
2005	unsigned u1Available : 1;
2006	/** Long mode flag. */
2007	unsigned u1Long : 1;
2008	/** This flags meaning depends on the segment type. Try make sense out
2009	* of the intel manual yourself. */
2010	unsigned u1DefBig : 1;
2011	/** Granularity of the limit. If set 4KB granularity is used, if
2012	* clear byte. - IGNORED */
2013	unsigned u1Granularity : 1;
2014	/** Base address - highest 8 bits. - IGNORED */
2015	unsigned u8BaseHigh2 : 8;
2016	/** Base address - bits 63-32. */
2017	unsigned u32BaseHigh3 : 32;
2018	unsigned u8Reserved : 8;
2019	unsigned u5Zeros : 5;
2020	unsigned u19Reserved : 19;
2021	} X86DESC64GENERIC;
2022	#pragma pack()
2023	/** Pointer to a generic descriptor entry. */
2024	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2025	/** Pointer to a const generic descriptor entry. */
2026	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2027
2028	/**
2029	* System descriptor table entry (64 bits)
2030	*/
2031	#pragma pack(1)
2032	typedef struct X86DESC64SYSTEM
2033	{
2034	/** Limit - Low word. */
2035	unsigned u16LimitLow : 16;
2036	/** Base address - lowe word.
2037	* Don't try set this to 24 because MSC is doing studing things then. */
2038	unsigned u16BaseLow : 16;
2039	/** Base address - first 8 bits of high word. */
2040	unsigned u8BaseHigh1 : 8;
2041	/** Segment Type. */
2042	unsigned u4Type : 4;
2043	/** Descriptor Type. System(=0) or code/data selector */
2044	unsigned u1DescType : 1;
2045	/** Descriptor Privelege level. */
2046	unsigned u2Dpl : 2;
2047	/** Flags selector present(=1) or not. */
2048	unsigned u1Present : 1;
2049	/** Segment limit 16-19. */
2050	unsigned u4LimitHigh : 4;
2051	/** Available for system software. */
2052	unsigned u1Available : 1;
2053	/** Reserved - 0. */
2054	unsigned u1Reserved : 1;
2055	/** This flags meaning depends on the segment type. Try make sense out
2056	* of the intel manual yourself. */
2057	unsigned u1DefBig : 1;
2058	/** Granularity of the limit. If set 4KB granularity is used, if
2059	* clear byte. */
2060	unsigned u1Granularity : 1;
2061	/** Base address - bits 31-24. */
2062	unsigned u8BaseHigh2 : 8;
2063	/** Base address - bits 63-32. */
2064	unsigned u32BaseHigh3 : 32;
2065	unsigned u8Reserved : 8;
2066	unsigned u5Zeros : 5;
2067	unsigned u19Reserved : 19;
2068	} X86DESC64SYSTEM;
2069	#pragma pack()
2070	/** Pointer to a generic descriptor entry. */
2071	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2072	/** Pointer to a const generic descriptor entry. */
2073	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2074
2075
2076	/**
2077	* Descriptor table entry.
2078	*/
2079	#pragma pack(1)
2080	typedef union X86DESC64
2081	{
2082	/** Generic descriptor view. */
2083	X86DESC64GENERIC Gen;
2084	/** System descriptor view. */
2085	X86DESC64SYSTEM System;
2086	#if 0
2087	X86DESC64GATE Gate;
2088	#endif
2089
2090	/** 8 bit unsigned interger view. */
2091	uint8_t au8[16];
2092	/** 16 bit unsigned interger view. */
2093	uint16_t au16[8];
2094	/** 32 bit unsigned interger view. */
2095	uint32_t au32[4];
2096	/** 64 bit unsigned interger view. */
2097	uint64_t au64[2];
2098	} X86DESC64;
2099	#pragma pack()
2100	/** Pointer to descriptor table entry. */
2101	typedef X86DESC64 *PX86DESC64;
2102	/** Pointer to const descriptor table entry. */
2103	typedef const X86DESC64 *PCX86DESC64;
2104
2105	#if HC_ARCH_BITS == 64
2106	typedef X86DESC64 X86DESCHC;
2107	typedef X86DESC64 *PX86DESCHC;
2108	#else
2109	typedef X86DESC X86DESCHC;
2110	typedef X86DESC *PX86DESCHC;
2111	#endif
2112
2113	/** @def X86DESC_LIMIT
2114	* Return the base of a 64-bit descriptor.
2115	*/
2116	#define X86DESC64_BASE(desc) \
2117	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2118	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2119	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2120	\| ( (desc).Gen.u16BaseLow ) )
2121
2122
2123	/** @name Selector Descriptor Types.
2124	* @{
2125	*/
2126
2127	/** @name Non-System Selector Types.
2128	* @{ */
2129	/** Code(=set)/Data(=clear) bit. */
2130	#define X86_SEL_TYPE_CODE 8
2131	/** Memory(=set)/System(=clear) bit. */
2132	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2133	/** Accessed bit. */
2134	#define X86_SEL_TYPE_ACCESSED 1
2135	/** Expand down bit (for data selectors only). */
2136	#define X86_SEL_TYPE_DOWN 4
2137	/** Conforming bit (for code selectors only). */
2138	#define X86_SEL_TYPE_CONF 4
2139	/** Write bit (for data selectors only). */
2140	#define X86_SEL_TYPE_WRITE 2
2141	/** Read bit (for code selectors only). */
2142	#define X86_SEL_TYPE_READ 2
2143
2144	/** Read only selector type. */
2145	#define X86_SEL_TYPE_RO 0
2146	/** Accessed read only selector type. */
2147	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2148	/** Read write selector type. */
2149	#define X86_SEL_TYPE_RW 2
2150	/** Accessed read write selector type. */
2151	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2152	/** Expand down read only selector type. */
2153	#define X86_SEL_TYPE_RO_DOWN 4
2154	/** Accessed expand down read only selector type. */
2155	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2156	/** Expand down read write selector type. */
2157	#define X86_SEL_TYPE_RW_DOWN 6
2158	/** Accessed expand down read write selector type. */
2159	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2160	/** Execute only selector type. */
2161	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2162	/** Accessed execute only selector type. */
2163	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2164	/** Execute and read selector type. */
2165	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2166	/** Accessed execute and read selector type. */
2167	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2168	/** Conforming execute only selector type. */
2169	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2170	/** Accessed Conforming execute only selector type. */
2171	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2172	/** Conforming execute and write selector type. */
2173	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2174	/** Accessed Conforming execute and write selector type. */
2175	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2176	/** @} */
2177
2178
2179	/** @name System Selector Types.
2180	* @{ */
2181	/** Undefined system selector type. */
2182	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2183	/** 286 TSS selector. */
2184	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2185	/** LDT selector. */
2186	#define X86_SEL_TYPE_SYS_LDT 2
2187	/** 286 TSS selector - Busy. */
2188	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2189	/** 286 Callgate selector. */
2190	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2191	/** Taskgate selector. */
2192	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2193	/** 286 Interrupt gate selector. */
2194	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2195	/** 286 Trapgate selector. */
2196	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2197	/** Undefined system selector. */
2198	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2199	/** 386 TSS selector. */
2200	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2201	/** Undefined system selector. */
2202	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2203	/** 386 TSS selector - Busy. */
2204	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2205	/** 386 Callgate selector. */
2206	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2207	/** Undefined system selector. */
2208	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2209	/** 386 Interruptgate selector. */
2210	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2211	/** 386 Trapgate selector. */
2212	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2213	/** @} */
2214
2215	/** @name AMD64 System Selector Types.
2216	* @{ */
2217	#define AMD64_SEL_TYPE_SYS_LDT 2
2218	/** 286 TSS selector - Busy. */
2219	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2220	/** 386 TSS selector - Busy. */
2221	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2222	/** 386 Callgate selector. */
2223	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2224	/** 386 Interruptgate selector. */
2225	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2226	/** 386 Trapgate selector. */
2227	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2228	/** @} */
2229
2230	/** @} */
2231
2232
2233	/** @name Descriptor Table Entry Flag Masks.
2234	* These are for the 2nd 32-bit word of a descriptor.
2235	* @{ */
2236	/** Bits 8-11 - TYPE - Descriptor type mask. */
2237	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2238	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2239	#define X86_DESC_S RT_BIT(12)
2240	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2241	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2242	/** Bit 15 - P - Present. */
2243	#define X86_DESC_P RT_BIT(15)
2244	/** Bit 20 - AVL - Available for system software. */
2245	#define X86_DESC_AVL RT_BIT(20)
2246	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2247	#define X86_DESC_DB RT_BIT(22)
2248	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2249	* used, if clear byte. */
2250	#define X86_DESC_G RT_BIT(23)
2251	/** @} */
2252
2253	/** @} */
2254
2255
2256	/** @name Selectors.
2257	* @{
2258	*/
2259
2260	/**
2261	* The shift used to convert a selector from and to index an index (C).
2262	*/
2263	#define X86_SEL_SHIFT 3
2264
2265	/**
2266	* The shift used to convert a selector from and to index an index (C).
2267	*/
2268	#define AMD64_SEL_SHIFT 4
2269
2270	#if HC_ARCH_BITS == 64
2271	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2272	#else
2273	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2274	#endif
2275
2276	/**
2277	* The mask used to mask off the table indicator and CPL of an selector.
2278	*/
2279	#define X86_SEL_MASK 0xfff8
2280
2281	/**
2282	* The bit indicating that a selector is in the LDT and not in the GDT.
2283	*/
2284	#define X86_SEL_LDT 0x0004
2285	/**
2286	* The bit mask for getting the RPL of a selector.
2287	*/
2288	#define X86_SEL_RPL 0x0003
2289
2290	/** @} */
2291
2292
2293	/**
2294	* x86 Exceptions/Faults/Traps.
2295	*/
2296	typedef enum X86XCPT
2297	{
2298	/** \#DE - Divide error. */
2299	X86_XCPT_DE = 0x00,
2300	/** \#DB - Debug event (single step, DRx, ..) */
2301	X86_XCPT_DB = 0x01,
2302	/** NMI - Non-Maskable Interrupt */
2303	X86_XCPT_NMI = 0x02,
2304	/** \#BP - Breakpoint (INT3). */
2305	X86_XCPT_BP = 0x03,
2306	/** \#OF - Overflow (INTO). */
2307	X86_XCPT_OF = 0x04,
2308	/** \#BR - Bound range exceeded (BOUND). */
2309	X86_XCPT_BR = 0x05,
2310	/** \#UD - Undefined opcode. */
2311	X86_XCPT_UD = 0x06,
2312	/** \#NM - Device not available (math coprocessor device). */
2313	X86_XCPT_NM = 0x07,
2314	/** \#DF - Double fault. */
2315	X86_XCPT_DF = 0x08,
2316	/** ??? - Coprocessor segment overrun (obsolete). */
2317	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2318	/** \#TS - Taskswitch (TSS). */
2319	X86_XCPT_TS = 0x0a,
2320	/** \#NP - Segment no present. */
2321	X86_XCPT_NP = 0x0b,
2322	/** \#SS - Stack segment fault. */
2323	X86_XCPT_SS = 0x0c,
2324	/** \#GP - General protection fault. */
2325	X86_XCPT_GP = 0x0d,
2326	/** \#PF - Page fault. */
2327	X86_XCPT_PF = 0x0e,
2328	/* 0x0f is reserved. */
2329	/** \#MF - Math fault (FPU). */
2330	X86_XCPT_MF = 0x10,
2331	/** \#AC - Alignment check. */
2332	X86_XCPT_AC = 0x11,
2333	/** \#MC - Machine check. */
2334	X86_XCPT_MC = 0x12,
2335	/** \#XF - SIMD Floating-Pointer Exception. */
2336	X86_XCPT_XF = 0x13
2337	} X86XCPT;
2338	/** Pointer to a x86 exception code. */
2339	typedef X86XCPT *PX86XCPT;
2340	/** Pointer to a const x86 exception code. */
2341	typedef const X86XCPT *PCX86XCPT;
2342
2343
2344	/** @name Trap Error Codes
2345	* @{
2346	*/
2347	/** External indicator. */
2348	#define X86_TRAP_ERR_EXTERNAL 1
2349	/** IDT indicator. */
2350	#define X86_TRAP_ERR_IDT 2
2351	/** Descriptor table indicator - If set LDT, if clear GDT. */
2352	#define X86_TRAP_ERR_TI 4
2353	/** Mask for getting the selector. */
2354	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2355	/** Shift for getting the selector table index (C type index). */
2356	#define X86_TRAP_ERR_SEL_SHIFT 3
2357	/** @} */
2358
2359
2360	/** @name \#PF Trap Error Codes
2361	* @{
2362	*/
2363	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2364	#define X86_TRAP_PF_P RT_BIT(0)
2365	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2366	#define X86_TRAP_PF_RW RT_BIT(1)
2367	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2368	#define X86_TRAP_PF_US RT_BIT(2)
2369	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2370	#define X86_TRAP_PF_RSVD RT_BIT(3)
2371	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2372	#define X86_TRAP_PF_ID RT_BIT(4)
2373	/** @} */
2374
2375	#pragma pack(1)
2376	/**
2377	* 32-bit IDTR/GDTR.
2378	*/
2379	typedef struct X86XDTR32
2380	{
2381	/** Size of the descriptor table. */
2382	uint16_t cb;
2383	/** Address of the descriptor table. */
2384	uint32_t uAddr;
2385	} X86XDTR32, *PX86XDTR32;
2386	#pragma pack()
2387
2388	#pragma pack(1)
2389	/**
2390	* 64-bit IDTR/GDTR.
2391	*/
2392	typedef struct X86XDTR64
2393	{
2394	/** Size of the descriptor table. */
2395	uint16_t cb;
2396	/** Address of the descriptor table. */
2397	uint64_t uAddr;
2398	} X86XDTR64, *PX86XDTR64;
2399	#pragma pack()
2400
2401	/** @} */
2402
2403	#endif
2404

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source: vbox/trunk/include/VBox/x86.h@ 12347

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