x86.h@ 21320

Last change on this file since 21320 was 21320, checked in by vboxsync, 16 years ago
Extra CPUID 1 ecx capability bits
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1	/** @file
2	* X86 (and AMD64) Structures and Definitions (VMM,++).
3	*
4	* x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*
27	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
28	* Clara, CA 95054 USA or visit http://www.sun.com if you need
29	* additional information or have any questions.
30	*/
31
32	#ifndef ___VBox_x86_h
33	#define ___VBox_x86_h
34
35	#include <VBox/types.h>
36	#include <iprt/assert.h>
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_x86 x86 Types and Definitions
45	* @{
46	*/
47
48	/**
49	* EFLAGS Bits.
50	*/
51	typedef struct X86EFLAGSBITS
52	{
53	/** Bit 0 - CF - Carry flag - Status flag. */
54	unsigned u1CF : 1;
55	/** Bit 1 - 1 - Reserved flag. */
56	unsigned u1Reserved0 : 1;
57	/** Bit 2 - PF - Parity flag - Status flag. */
58	unsigned u1PF : 1;
59	/** Bit 3 - 0 - Reserved flag. */
60	unsigned u1Reserved1 : 1;
61	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
62	unsigned u1AF : 1;
63	/** Bit 5 - 0 - Reserved flag. */
64	unsigned u1Reserved2 : 1;
65	/** Bit 6 - ZF - Zero flag - Status flag. */
66	unsigned u1ZF : 1;
67	/** Bit 7 - SF - Signed flag - Status flag. */
68	unsigned u1SF : 1;
69	/** Bit 8 - TF - Trap flag - System flag. */
70	unsigned u1TF : 1;
71	/** Bit 9 - IF - Interrupt flag - System flag. */
72	unsigned u1IF : 1;
73	/** Bit 10 - DF - Direction flag - Control flag. */
74	unsigned u1DF : 1;
75	/** Bit 11 - OF - Overflow flag - Status flag. */
76	unsigned u1OF : 1;
77	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
78	unsigned u2IOPL : 2;
79	/** Bit 14 - NT - Nested task flag - System flag. */
80	unsigned u1NT : 1;
81	/** Bit 15 - 0 - Reserved flag. */
82	unsigned u1Reserved3 : 1;
83	/** Bit 16 - RF - Resume flag - System flag. */
84	unsigned u1RF : 1;
85	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
86	unsigned u1VM : 1;
87	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
88	unsigned u1AC : 1;
89	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
90	unsigned u1VIF : 1;
91	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
92	unsigned u1VIP : 1;
93	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
94	unsigned u1ID : 1;
95	/** Bit 22-31 - 0 - Reserved flag. */
96	unsigned u10Reserved4 : 10;
97	} X86EFLAGSBITS;
98	/** Pointer to EFLAGS bits. */
99	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
100	/** Pointer to const EFLAGS bits. */
101	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
102
103	/**
104	* EFLAGS.
105	*/
106	typedef union X86EFLAGS
107	{
108	/** The plain unsigned view. */
109	uint32_t u;
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	} X86EFLAGS;
121	/** Pointer to EFLAGS. */
122	typedef X86EFLAGS *PX86EFLAGS;
123	/** Pointer to const EFLAGS. */
124	typedef const X86EFLAGS *PCX86EFLAGS;
125
126	/**
127	* RFLAGS (32 upper bits are reserved).
128	*/
129	typedef union X86RFLAGS
130	{
131	/** The plain unsigned view. */
132	uint64_t u;
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	} X86RFLAGS;
146	/** Pointer to RFLAGS. */
147	typedef X86RFLAGS *PX86RFLAGS;
148	/** Pointer to const RFLAGS. */
149	typedef const X86RFLAGS *PCX86RFLAGS;
150
151
152	/** @name EFLAGS
153	* @{
154	*/
155	/** Bit 0 - CF - Carry flag - Status flag. */
156	#define X86_EFL_CF RT_BIT(0)
157	/** Bit 2 - PF - Parity flag - Status flag. */
158	#define X86_EFL_PF RT_BIT(2)
159	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
160	#define X86_EFL_AF RT_BIT(4)
161	/** Bit 6 - ZF - Zero flag - Status flag. */
162	#define X86_EFL_ZF RT_BIT(6)
163	/** Bit 7 - SF - Signed flag - Status flag. */
164	#define X86_EFL_SF RT_BIT(7)
165	/** Bit 8 - TF - Trap flag - System flag. */
166	#define X86_EFL_TF RT_BIT(8)
167	/** Bit 9 - IF - Interrupt flag - System flag. */
168	#define X86_EFL_IF RT_BIT(9)
169	/** Bit 10 - DF - Direction flag - Control flag. */
170	#define X86_EFL_DF RT_BIT(10)
171	/** Bit 11 - OF - Overflow flag - Status flag. */
172	#define X86_EFL_OF RT_BIT(11)
173	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
174	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
175	/** Bit 14 - NT - Nested task flag - System flag. */
176	#define X86_EFL_NT RT_BIT(14)
177	/** Bit 16 - RF - Resume flag - System flag. */
178	#define X86_EFL_RF RT_BIT(16)
179	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
180	#define X86_EFL_VM RT_BIT(17)
181	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
182	#define X86_EFL_AC RT_BIT(18)
183	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
184	#define X86_EFL_VIF RT_BIT(19)
185	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
186	#define X86_EFL_VIP RT_BIT(20)
187	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
188	#define X86_EFL_ID RT_BIT(21)
189	/** IOPL shift. */
190	#define X86_EFL_IOPL_SHIFT 12
191	/** The the IOPL level from the flags. */
192	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
193	/** Bits restored by popf */
194	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u1Reserved1 : 1;
207	/** Bit 2 - DS Area 64-bit layout. */
208	unsigned u1DTE64 : 1;
209	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
210	unsigned u1Monitor : 1;
211	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
212	unsigned u1CPLDS : 1;
213	/** Bit 5 - VMX - Virtual Machine Technology. */
214	unsigned u1VMX : 1;
215	/** Bit 6 - SMX: Safer Mode Extensions. */
216	unsigned u1SMX : 1;
217	/** Bit 7 - EST - Enh. SpeedStep Tech. */
218	unsigned u1EST : 1;
219	/** Bit 8 - TM2 - Terminal Monitor 2. */
220	unsigned u1TM2 : 1;
221	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
222	unsigned u1SSSE3 : 1;
223	/** Bit 10 - CNTX-ID - L1 Context ID. */
224	unsigned u1CNTXID : 1;
225	/** Reserved. */
226	unsigned u2Reserved2 : 2;
227	/** Bit 13 - CX16 - CMPXCHG16B. */
228	unsigned u1CX16 : 1;
229	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
230	unsigned u1TPRUpdate : 1;
231	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
232	unsigned u1PDCM : 1;
233	/** Reserved. */
234	unsigned u2Reserved3 : 2;
235	/** Bit 18 - Direct Cache Access. */
236	unsigned u1DCA : 1;
237	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
238	unsigned u1SSE4_1 : 1;
239	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
240	unsigned u1SSE4_2 : 1;
241	/** Bit 21 - x2APIC. */
242	unsigned u1x2APIC : 1;
243	/** Bit 22 - MOVBE - Supports MOVBE. */
244	unsigned u1MOVBE : 1;
245	/** Bit 23 - POPCNT - Supports POPCNT. */
246	unsigned u1POPCNT : 1;
247	/** Reserved. */
248	unsigned u2Reserved4 : 2;
249	/** Bit 26 - XSAVE - Supports XSAVE. */
250	unsigned u1XSAVE : 1;
251	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
252	unsigned u1OSXSAVE : 1;
253	/** Reserved. */
254	unsigned u4Reserved5 : 4;
255	} X86CPUIDFEATECX;
256	/** Pointer to CPUID Feature Information - ECX. */
257	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
258	/** Pointer to const CPUID Feature Information - ECX. */
259	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
260
261
262	/** CPUID Feature Information - EDX.
263	* CPUID query with EAX=1.
264	*/
265	typedef struct X86CPUIDFEATEDX
266	{
267	/** Bit 0 - FPU - x87 FPU on Chip. */
268	unsigned u1FPU : 1;
269	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
270	unsigned u1VME : 1;
271	/** Bit 2 - DE - Debugging extensions. */
272	unsigned u1DE : 1;
273	/** Bit 3 - PSE - Page Size Extension. */
274	unsigned u1PSE : 1;
275	/** Bit 4 - TSC - Time Stamp Counter. */
276	unsigned u1TSC : 1;
277	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
278	unsigned u1MSR : 1;
279	/** Bit 6 - PAE - Physical Address Extension. */
280	unsigned u1PAE : 1;
281	/** Bit 7 - MCE - Machine Check Exception. */
282	unsigned u1MCE : 1;
283	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
284	unsigned u1CX8 : 1;
285	/** Bit 9 - APIC - APIC On-Chip. */
286	unsigned u1APIC : 1;
287	/** Bit 10 - Reserved. */
288	unsigned u1Reserved1 : 1;
289	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
290	unsigned u1SEP : 1;
291	/** Bit 12 - MTRR - Memory Type Range Registers. */
292	unsigned u1MTRR : 1;
293	/** Bit 13 - PGE - PTE Global Bit. */
294	unsigned u1PGE : 1;
295	/** Bit 14 - MCA - Machine Check Architecture. */
296	unsigned u1MCA : 1;
297	/** Bit 15 - CMOV - Conditional Move Instructions. */
298	unsigned u1CMOV : 1;
299	/** Bit 16 - PAT - Page Attribute Table. */
300	unsigned u1PAT : 1;
301	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
302	unsigned u1PSE36 : 1;
303	/** Bit 18 - PSN - Processor Serial Number. */
304	unsigned u1PSN : 1;
305	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
306	unsigned u1CLFSH : 1;
307	/** Bit 20 - Reserved. */
308	unsigned u1Reserved2 : 1;
309	/** Bit 21 - DS - Debug Store. */
310	unsigned u1DS : 1;
311	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
312	unsigned u1ACPI : 1;
313	/** Bit 23 - MMX - Intel MMX 'Technology'. */
314	unsigned u1MMX : 1;
315	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
316	unsigned u1FXSR : 1;
317	/** Bit 25 - SSE - SSE Support. */
318	unsigned u1SSE : 1;
319	/** Bit 26 - SSE2 - SSE2 Support. */
320	unsigned u1SSE2 : 1;
321	/** Bit 27 - SS - Self Snoop. */
322	unsigned u1SS : 1;
323	/** Bit 28 - HTT - Hyper-Threading Technology. */
324	unsigned u1HTT : 1;
325	/** Bit 29 - TM - Thermal Monitor. */
326	unsigned u1TM : 1;
327	/** Bit 30 - Reserved - . */
328	unsigned u1Reserved3 : 1;
329	/** Bit 31 - PBE - Pending Break Enabled. */
330	unsigned u1PBE : 1;
331	} X86CPUIDFEATEDX;
332	/** Pointer to CPUID Feature Information - EDX. */
333	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
334	/** Pointer to const CPUID Feature Information - EDX. */
335	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
336
337	/** @name CPUID Vendor information.
338	* CPUID query with EAX=0.
339	* @{
340	*/
341	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
342	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
343	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
344
345	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
346	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
347	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
348	/** @} */
349
350
351	/** @name CPUID Feature information.
352	* CPUID query with EAX=1.
353	* @{
354	*/
355	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
356	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
357	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
358	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
359	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
360	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
361	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
362	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
363	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
364	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
365	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
366	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
367	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
368	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
369	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
370	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
371	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
372	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
373	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
374	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
375	/** ECX Bit 21 - x2APIC support. */
376	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
377	/** ECX Bit 23 - POPCOUNT instruction. */
378	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
379
380
381	/** Bit 0 - FPU - x87 FPU on Chip. */
382	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
383	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
384	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
385	/** Bit 2 - DE - Debugging extensions. */
386	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
387	/** Bit 3 - PSE - Page Size Extension. */
388	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
389	/** Bit 4 - TSC - Time Stamp Counter. */
390	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
391	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
392	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
393	/** Bit 6 - PAE - Physical Address Extension. */
394	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
395	/** Bit 7 - MCE - Machine Check Exception. */
396	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
397	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
398	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
399	/** Bit 9 - APIC - APIC On-Chip. */
400	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
401	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
402	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
403	/** Bit 12 - MTRR - Memory Type Range Registers. */
404	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
405	/** Bit 13 - PGE - PTE Global Bit. */
406	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
407	/** Bit 14 - MCA - Machine Check Architecture. */
408	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
409	/** Bit 15 - CMOV - Conditional Move Instructions. */
410	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
411	/** Bit 16 - PAT - Page Attribute Table. */
412	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
413	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
414	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
415	/** Bit 18 - PSN - Processor Serial Number. */
416	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
417	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
418	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
419	/** Bit 21 - DS - Debug Store. */
420	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
421	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
422	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
423	/** Bit 23 - MMX - Intel MMX Technology. */
424	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
425	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
426	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
427	/** Bit 25 - SSE - SSE Support. */
428	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
429	/** Bit 26 - SSE2 - SSE2 Support. */
430	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
431	/** Bit 27 - SS - Self Snoop. */
432	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
433	/** Bit 28 - HTT - Hyper-Threading Technology. */
434	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
435	/** Bit 29 - TM - Therm. Monitor. */
436	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
437	/** Bit 31 - PBE - Pending Break Enabled. */
438	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
439	/** @} */
440
441
442	/** @name CPUID AMD Feature information.
443	* CPUID query with EAX=0x80000001.
444	* @{
445	*/
446	/** Bit 0 - FPU - x87 FPU on Chip. */
447	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
448	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
449	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
450	/** Bit 2 - DE - Debugging extensions. */
451	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
452	/** Bit 3 - PSE - Page Size Extension. */
453	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
454	/** Bit 4 - TSC - Time Stamp Counter. */
455	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
456	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
457	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
458	/** Bit 6 - PAE - Physical Address Extension. */
459	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
460	/** Bit 7 - MCE - Machine Check Exception. */
461	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
462	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
463	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
464	/** Bit 9 - APIC - APIC On-Chip. */
465	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
466	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
467	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
468	/** Bit 12 - MTRR - Memory Type Range Registers. */
469	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
470	/** Bit 13 - PGE - PTE Global Bit. */
471	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
472	/** Bit 14 - MCA - Machine Check Architecture. */
473	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
474	/** Bit 15 - CMOV - Conditional Move Instructions. */
475	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
476	/** Bit 16 - PAT - Page Attribute Table. */
477	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
478	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
479	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
480	/** Bit 20 - NX - AMD No-Execute Page Protection. */
481	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
482	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
483	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
484	/** Bit 23 - MMX - Intel MMX Technology. */
485	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
486	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
487	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
488	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
489	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
490	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
491	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
492	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
493	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
494	/** Bit 29 - LM - AMD Long Mode. */
495	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
496	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
497	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
498	/** Bit 31 - 3DNOW - AMD 3DNow. */
499	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
500
501	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
502	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
503	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
504	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
505	/** Bit 2 - SVM - AMD VM extensions. */
506	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
507	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
508	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
509	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
510	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
511	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
512	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
513	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
514	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
515	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
516	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
517	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
518	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
519	/** Bit 9 - OSVW - AMD OS visible workaround. */
520	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
521	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
522	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
523	/** Bit 13 - WDT - AMD Watchdog timer support. */
524	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
525
526	/** @} */
527
528
529	/** @name CPUID AMD Feature information.
530	* CPUID query with EAX=0x80000007.
531	* @{
532	*/
533	/** Bit 0 - TS - Temperature Sensor. */
534	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
535	/** Bit 1 - FID - Frequency ID Control. */
536	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
537	/** Bit 2 - VID - Voltage ID Control. */
538	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
539	/** Bit 3 - TTP - THERMTRIP. */
540	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
541	/** Bit 4 - TM - Hardware Thermal Control. */
542	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
543	/** Bit 5 - STC - Software Thermal Control. */
544	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
545	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
546	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
547	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
548	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
549	/** Bit 8 - TSCINVAR - TSC Invariant. */
550	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
551	/** @} */
552
553
554	/** @name CR0
555	* @{ */
556	/** Bit 0 - PE - Protection Enabled */
557	#define X86_CR0_PE RT_BIT(0)
558	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
559	/** Bit 1 - MP - Monitor Coprocessor */
560	#define X86_CR0_MP RT_BIT(1)
561	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
562	/** Bit 2 - EM - Emulation. */
563	#define X86_CR0_EM RT_BIT(2)
564	#define X86_CR0_EMULATE_FPU RT_BIT(2)
565	/** Bit 3 - TS - Task Switch. */
566	#define X86_CR0_TS RT_BIT(3)
567	#define X86_CR0_TASK_SWITCH RT_BIT(3)
568	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
569	#define X86_CR0_ET RT_BIT(4)
570	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
571	/** Bit 5 - NE - Numeric error. */
572	#define X86_CR0_NE RT_BIT(5)
573	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
574	/** Bit 16 - WP - Write Protect. */
575	#define X86_CR0_WP RT_BIT(16)
576	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
577	/** Bit 18 - AM - Alignment Mask. */
578	#define X86_CR0_AM RT_BIT(18)
579	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
580	/** Bit 29 - NW - Not Write-though. */
581	#define X86_CR0_NW RT_BIT(29)
582	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
583	/** Bit 30 - WP - Cache Disable. */
584	#define X86_CR0_CD RT_BIT(30)
585	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
586	/** Bit 31 - PG - Paging. */
587	#define X86_CR0_PG RT_BIT(31)
588	#define X86_CR0_PAGING RT_BIT(31)
589	/** @} */
590
591
592	/** @name CR3
593	* @{ */
594	/** Bit 3 - PWT - Page-level Writes Transparent. */
595	#define X86_CR3_PWT RT_BIT(3)
596	/** Bit 4 - PCD - Page-level Cache Disable. */
597	#define X86_CR3_PCD RT_BIT(4)
598	/** Bits 12-31 - - Page directory page number. */
599	#define X86_CR3_PAGE_MASK (0xfffff000)
600	/** Bits 5-31 - - PAE Page directory page number. */
601	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
602	/** Bits 12-51 - - AMD64 Page directory page number. */
603	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
604	/** @} */
605
606
607	/** @name CR4
608	* @{ */
609	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
610	#define X86_CR4_VME RT_BIT(0)
611	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
612	#define X86_CR4_PVI RT_BIT(1)
613	/** Bit 2 - TSD - Time Stamp Disable. */
614	#define X86_CR4_TSD RT_BIT(2)
615	/** Bit 3 - DE - Debugging Extensions. */
616	#define X86_CR4_DE RT_BIT(3)
617	/** Bit 4 - PSE - Page Size Extension. */
618	#define X86_CR4_PSE RT_BIT(4)
619	/** Bit 5 - PAE - Physical Address Extension. */
620	#define X86_CR4_PAE RT_BIT(5)
621	/** Bit 6 - MCE - Machine-Check Enable. */
622	#define X86_CR4_MCE RT_BIT(6)
623	/** Bit 7 - PGE - Page Global Enable. */
624	#define X86_CR4_PGE RT_BIT(7)
625	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
626	#define X86_CR4_PCE RT_BIT(8)
627	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
628	#define X86_CR4_OSFSXR RT_BIT(9)
629	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
630	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
631	/** Bit 13 - VMXE - VMX mode is enabled. */
632	#define X86_CR4_VMXE RT_BIT(13)
633	/** @} */
634
635
636	/** @name DR6
637	* @{ */
638	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
639	#define X86_DR6_B0 RT_BIT(0)
640	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
641	#define X86_DR6_B1 RT_BIT(1)
642	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
643	#define X86_DR6_B2 RT_BIT(2)
644	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
645	#define X86_DR6_B3 RT_BIT(3)
646	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
647	#define X86_DR6_BD RT_BIT(13)
648	/** Bit 14 - BS - Single step */
649	#define X86_DR6_BS RT_BIT(14)
650	/** Bit 15 - BT - Task switch. (TSS T bit.) */
651	#define X86_DR6_BT RT_BIT(15)
652	/** Value of DR6 after powerup/reset. */
653	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
654	/** @} */
655
656
657	/** @name DR7
658	* @{ */
659	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
660	#define X86_DR7_L0 RT_BIT(0)
661	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
662	#define X86_DR7_G0 RT_BIT(1)
663	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
664	#define X86_DR7_L1 RT_BIT(2)
665	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
666	#define X86_DR7_G1 RT_BIT(3)
667	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
668	#define X86_DR7_L2 RT_BIT(4)
669	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
670	#define X86_DR7_G2 RT_BIT(5)
671	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
672	#define X86_DR7_L3 RT_BIT(6)
673	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
674	#define X86_DR7_G3 RT_BIT(7)
675	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
676	#define X86_DR7_LE RT_BIT(8)
677	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
678	#define X86_DR7_GE RT_BIT(9)
679
680	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
681	* any DR register is accessed. */
682	#define X86_DR7_GD RT_BIT(13)
683	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
684	#define X86_DR7_RW0_MASK (3 << 16)
685	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
686	#define X86_DR7_LEN0_MASK (3 << 18)
687	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
688	#define X86_DR7_RW1_MASK (3 << 20)
689	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
690	#define X86_DR7_LEN1_MASK (3 << 22)
691	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
692	#define X86_DR7_RW2_MASK (3 << 24)
693	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
694	#define X86_DR7_LEN2_MASK (3 << 26)
695	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
696	#define X86_DR7_RW3_MASK (3 << 28)
697	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
698	#define X86_DR7_LEN3_MASK (3 << 30)
699
700	/** Bits which must be 1s. */
701	#define X86_DR7_MB1_MASK (RT_BIT(10))
702
703	/** Calcs the L bit of Nth breakpoint.
704	* @param iBp The breakpoint number [0..3].
705	*/
706	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
707
708	/** Calcs the G bit of Nth breakpoint.
709	* @param iBp The breakpoint number [0..3].
710	*/
711	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
712
713	/** @name Read/Write values.
714	* @{ */
715	/** Break on instruction fetch only. */
716	#define X86_DR7_RW_EO 0U
717	/** Break on write only. */
718	#define X86_DR7_RW_WO 1U
719	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
720	#define X86_DR7_RW_IO 2U
721	/** Break on read or write (but not instruction fetches). */
722	#define X86_DR7_RW_RW 3U
723	/** @} */
724
725	/** Shifts a X86_DR7_RW_* value to its right place.
726	* @param iBp The breakpoint number [0..3].
727	* @param fRw One of the X86_DR7_RW_* value.
728	*/
729	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
730
731	/** @name Length values.
732	* @{ */
733	#define X86_DR7_LEN_BYTE 0U
734	#define X86_DR7_LEN_WORD 1U
735	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
736	#define X86_DR7_LEN_DWORD 3U
737	/** @} */
738
739	/** Shifts a X86_DR7_LEN_* value to its right place.
740	* @param iBp The breakpoint number [0..3].
741	* @param cb One of the X86_DR7_LEN_* values.
742	*/
743	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
744
745	/** Fetch the breakpoint length bits from the DR7 value.
746	* @param uDR7 DR7 value
747	* @param iBp The breakpoint number [0..3].
748	*/
749	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
750
751	/** Mask used to check if any breakpoints are enabled. */
752	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
753
754	/** Mask used to check if any io breakpoints are set. */
755	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
756
757	/** Value of DR7 after powerup/reset. */
758	#define X86_DR7_INIT_VAL 0x400
759	/** @} */
760
761
762	/** @name Machine Specific Registers
763	* @{
764	*/
765
766	/** Time Stamp Counter. */
767	#define MSR_IA32_TSC 0x10
768
769	#define MSR_IA32_PLATFORM_ID 0x17
770
771	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
772	#define MSR_IA32_APICBASE 0x1b
773	#endif
774
775	/** CPU Feature control. */
776	#define MSR_IA32_FEATURE_CONTROL 0x3A
777	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
778	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
779
780	/** BIOS update trigger (microcode update). */
781	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
782
783	/** BIOS update signature (microcode). */
784	#define MSR_IA32_BIOS_SIGN_ID 0x8B
785
786	/** MTRR Capabilities. */
787	#define MSR_IA32_MTRR_CAP 0xFE
788
789
790	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
791	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
792	* R0 SS == CS + 8
793	* R3 CS == CS + 16
794	* R3 SS == CS + 24
795	*/
796	#define MSR_IA32_SYSENTER_CS 0x174
797	/** SYSENTER_ESP - the R0 ESP. */
798	#define MSR_IA32_SYSENTER_ESP 0x175
799	/** SYSENTER_EIP - the R0 EIP. */
800	#define MSR_IA32_SYSENTER_EIP 0x176
801	#endif
802
803	/** Machine Check Global Capabilities Register. */
804	#define MSR_IA32_MCP_CAP 0x179
805	/** Machine Check Global Status Register. */
806	#define MSR_IA32_MCP_STATUS 0x17A
807	/** Machine Check Global Control Register. */
808	#define MSR_IA32_MCP_CTRL 0x17B
809
810	/* Page Attribute Table. */
811	#define MSR_IA32_CR_PAT 0x277
812
813	/** Performance counter MSRs. (Intel only) */
814	#define MSR_IA32_PERFEVTSEL0 0x186
815	#define MSR_IA32_PERFEVTSEL1 0x187
816	#define MSR_IA32_PERF_STATUS 0x198
817	#define MSR_IA32_PERF_CTL 0x199
818
819	/** MTRR Default Range. */
820	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
821
822	#define MSR_IA32_MC0_CTL 0x400
823	#define MSR_IA32_MC0_STATUS 0x401
824
825	/** Basic VMX information. */
826	#define MSR_IA32_VMX_BASIC_INFO 0x480
827	/** Allowed settings for pin-based VM execution controls */
828	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
829	/** Allowed settings for proc-based VM execution controls */
830	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
831	/** Allowed settings for the VMX exit controls. */
832	#define MSR_IA32_VMX_EXIT_CTLS 0x483
833	/** Allowed settings for the VMX entry controls. */
834	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
835	/** Misc VMX info. */
836	#define MSR_IA32_VMX_MISC 0x485
837	/** Fixed cleared bits in CR0. */
838	#define MSR_IA32_VMX_CR0_FIXED0 0x486
839	/** Fixed set bits in CR0. */
840	#define MSR_IA32_VMX_CR0_FIXED1 0x487
841	/** Fixed cleared bits in CR4. */
842	#define MSR_IA32_VMX_CR4_FIXED0 0x488
843	/** Fixed set bits in CR4. */
844	#define MSR_IA32_VMX_CR4_FIXED1 0x489
845	/** Information for enumerating fields in the VMCS. */
846	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
847	/** Allowed settings for secondary proc-based VM execution controls */
848	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
849	/** EPT capabilities. */
850	#define MSR_IA32_VMX_EPT_CAPS 0x48C
851	/** X2APIC MSR ranges. */
852	#define MSR_IA32_APIC_START 0x800
853	#define MSR_IA32_APIC_END 0x900
854
855	/** K6 EFER - Extended Feature Enable Register. */
856	#define MSR_K6_EFER 0xc0000080
857	/** @todo document EFER */
858	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
859	#define MSR_K6_EFER_SCE RT_BIT(0)
860	/** Bit 8 - LME - Long mode enabled. (R/W) */
861	#define MSR_K6_EFER_LME RT_BIT(8)
862	/** Bit 10 - LMA - Long mode active. (R) */
863	#define MSR_K6_EFER_LMA RT_BIT(10)
864	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
865	#define MSR_K6_EFER_NXE RT_BIT(11)
866	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
867	#define MSR_K6_EFER_SVME RT_BIT(12)
868	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
869	#define MSR_K6_EFER_LMSLE RT_BIT(13)
870	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
871	#define MSR_K6_EFER_FFXSR RT_BIT(14)
872	/** K6 STAR - SYSCALL/RET targets. */
873	#define MSR_K6_STAR 0xc0000081
874	/** Shift value for getting the SYSRET CS and SS value. */
875	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
876	/** Shift value for getting the SYSCALL CS and SS value. */
877	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
878	/** Selector mask for use after shifting. */
879	#define MSR_K6_STAR_SEL_MASK 0xffff
880	/** The mask which give the SYSCALL EIP. */
881	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
882	/** K6 WHCR - Write Handling Control Register. */
883	#define MSR_K6_WHCR 0xc0000082
884	/** K6 UWCCR - UC/WC Cacheability Control Register. */
885	#define MSR_K6_UWCCR 0xc0000085
886	/** K6 PSOR - Processor State Observability Register. */
887	#define MSR_K6_PSOR 0xc0000087
888	/** K6 PFIR - Page Flush/Invalidate Register. */
889	#define MSR_K6_PFIR 0xc0000088
890
891	/** Performance counter MSRs. (AMD only) */
892	#define MSR_K7_EVNTSEL0 0xc0010000
893	#define MSR_K7_EVNTSEL1 0xc0010001
894	#define MSR_K7_EVNTSEL2 0xc0010002
895	#define MSR_K7_EVNTSEL3 0xc0010003
896	#define MSR_K7_PERFCTR0 0xc0010004
897	#define MSR_K7_PERFCTR1 0xc0010005
898	#define MSR_K7_PERFCTR2 0xc0010006
899	#define MSR_K7_PERFCTR3 0xc0010007
900
901	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
902	#define MSR_K8_LSTAR 0xc0000082
903	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
904	#define MSR_K8_CSTAR 0xc0000083
905	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
906	#define MSR_K8_SF_MASK 0xc0000084
907	/** K8 FS.base - The 64-bit base FS register. */
908	#define MSR_K8_FS_BASE 0xc0000100
909	/** K8 GS.base - The 64-bit base GS register. */
910	#define MSR_K8_GS_BASE 0xc0000101
911	/** K8 KernelGSbase - Used with SWAPGS. */
912	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
913	#define MSR_K8_TSC_AUX 0xc0000103
914	#define MSR_K8_SYSCFG 0xc0010010
915	#define MSR_K8_HWCR 0xc0010015
916	#define MSR_K8_IORRBASE0 0xc0010016
917	#define MSR_K8_IORRMASK0 0xc0010017
918	#define MSR_K8_IORRBASE1 0xc0010018
919	#define MSR_K8_IORRMASK1 0xc0010019
920	#define MSR_K8_TOP_MEM1 0xc001001a
921	#define MSR_K8_TOP_MEM2 0xc001001d
922	#define MSR_K8_VM_CR 0xc0010114
923	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
924
925	#define MSR_K8_IGNNE 0xc0010115
926	#define MSR_K8_SMM_CTL 0xc0010116
927	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
928	* host state during world switch.
929	*/
930	#define MSR_K8_VM_HSAVE_PA 0xc0010117
931
932	/** @} */
933
934
935	/** @name Page Table / Directory / Directory Pointers / L4.
936	* @{
937	*/
938
939	/** Page table/directory entry as an unsigned integer. */
940	typedef uint32_t X86PGUINT;
941	/** Pointer to a page table/directory table entry as an unsigned integer. */
942	typedef X86PGUINT *PX86PGUINT;
943	/** Pointer to an const page table/directory table entry as an unsigned integer. */
944	typedef X86PGUINT const *PCX86PGUINT;
945
946	/** Number of entries in a 32-bit PT/PD. */
947	#define X86_PG_ENTRIES 1024
948
949
950	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
951	typedef uint64_t X86PGPAEUINT;
952	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
953	typedef X86PGPAEUINT *PX86PGPAEUINT;
954	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
955	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
956
957	/** Number of entries in a PAE PT/PD. */
958	#define X86_PG_PAE_ENTRIES 512
959	/** Number of entries in a PAE PDPT. */
960	#define X86_PG_PAE_PDPE_ENTRIES 4
961
962	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
963	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
964	/** Number of entries in an AMD64 PDPT.
965	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
966	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
967
968	/** The size of a 4KB page. */
969	#define X86_PAGE_4K_SIZE _4K
970	/** The page shift of a 4KB page. */
971	#define X86_PAGE_4K_SHIFT 12
972	/** The 4KB page offset mask. */
973	#define X86_PAGE_4K_OFFSET_MASK 0xfff
974	/** The 4KB page base mask for virtual addresses. */
975	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
976	/** The 4KB page base mask for virtual addresses - 32bit version. */
977	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
978
979	/** The size of a 2MB page. */
980	#define X86_PAGE_2M_SIZE _2M
981	/** The page shift of a 2MB page. */
982	#define X86_PAGE_2M_SHIFT 21
983	/** The 2MB page offset mask. */
984	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
985	/** The 2MB page base mask for virtual addresses. */
986	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
987	/** The 2MB page base mask for virtual addresses - 32bit version. */
988	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
989
990	/** The size of a 4MB page. */
991	#define X86_PAGE_4M_SIZE _4M
992	/** The page shift of a 4MB page. */
993	#define X86_PAGE_4M_SHIFT 22
994	/** The 4MB page offset mask. */
995	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
996	/** The 4MB page base mask for virtual addresses. */
997	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
998	/** The 4MB page base mask for virtual addresses - 32bit version. */
999	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1000
1001
1002
1003	/** @name Page Table Entry
1004	* @{
1005	*/
1006	/** Bit 0 - P - Present bit. */
1007	#define X86_PTE_BIT_P 0
1008	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1009	#define X86_PTE_BIT_RW 1
1010	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1011	#define X86_PTE_BIT_US 2
1012	/** Bit 3 - PWT - Page level write thru bit. */
1013	#define X86_PTE_BIT_PWT 3
1014	/** Bit 4 - PCD - Page level cache disable bit. */
1015	#define X86_PTE_BIT_PCD 4
1016	/** Bit 5 - A - Access bit. */
1017	#define X86_PTE_BIT_A 5
1018	/** Bit 6 - D - Dirty bit. */
1019	#define X86_PTE_BIT_D 6
1020	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1021	#define X86_PTE_BIT_PAT 7
1022	/** Bit 8 - G - Global flag. */
1023	#define X86_PTE_BIT_G 8
1024
1025	/** Bit 0 - P - Present bit mask. */
1026	#define X86_PTE_P RT_BIT(0)
1027	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1028	#define X86_PTE_RW RT_BIT(1)
1029	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1030	#define X86_PTE_US RT_BIT(2)
1031	/** Bit 3 - PWT - Page level write thru bit mask. */
1032	#define X86_PTE_PWT RT_BIT(3)
1033	/** Bit 4 - PCD - Page level cache disable bit mask. */
1034	#define X86_PTE_PCD RT_BIT(4)
1035	/** Bit 5 - A - Access bit mask. */
1036	#define X86_PTE_A RT_BIT(5)
1037	/** Bit 6 - D - Dirty bit mask. */
1038	#define X86_PTE_D RT_BIT(6)
1039	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1040	#define X86_PTE_PAT RT_BIT(7)
1041	/** Bit 8 - G - Global bit mask. */
1042	#define X86_PTE_G RT_BIT(8)
1043
1044	/** Bits 9-11 - - Available for use to system software. */
1045	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1046	/** Bits 12-31 - - Physical Page number of the next level. */
1047	#define X86_PTE_PG_MASK ( 0xfffff000 )
1048
1049	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1050	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1051	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1052	/** @todo Get rid of the above hack; makes code unreadable. */
1053	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1054	#else
1055	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1056	#endif
1057	/** Bits 63 - NX - PAE - No execution flag. */
1058	#define X86_PTE_PAE_NX RT_BIT_64(63)
1059
1060	/**
1061	* Page table entry.
1062	*/
1063	typedef struct X86PTEBITS
1064	{
1065	/** Flags whether(=1) or not the page is present. */
1066	unsigned u1Present : 1;
1067	/** Read(=0) / Write(=1) flag. */
1068	unsigned u1Write : 1;
1069	/** User(=1) / Supervisor (=0) flag. */
1070	unsigned u1User : 1;
1071	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1072	unsigned u1WriteThru : 1;
1073	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1074	unsigned u1CacheDisable : 1;
1075	/** Accessed flag.
1076	* Indicates that the page have been read or written to. */
1077	unsigned u1Accessed : 1;
1078	/** Dirty flag.
1079	* Indicates that the page have been written to. */
1080	unsigned u1Dirty : 1;
1081	/** Reserved / If PAT enabled, bit 2 of the index. */
1082	unsigned u1PAT : 1;
1083	/** Global flag. (Ignored in all but final level.) */
1084	unsigned u1Global : 1;
1085	/** Available for use to system software. */
1086	unsigned u3Available : 3;
1087	/** Physical Page number of the next level. */
1088	unsigned u20PageNo : 20;
1089	} X86PTEBITS;
1090	/** Pointer to a page table entry. */
1091	typedef X86PTEBITS *PX86PTEBITS;
1092	/** Pointer to a const page table entry. */
1093	typedef const X86PTEBITS *PCX86PTEBITS;
1094
1095	/**
1096	* Page table entry.
1097	*/
1098	typedef union X86PTE
1099	{
1100	/** Unsigned integer view */
1101	X86PGUINT u;
1102	/** Bit field view. */
1103	X86PTEBITS n;
1104	/** 32-bit view. */
1105	uint32_t au32[1];
1106	/** 16-bit view. */
1107	uint16_t au16[2];
1108	/** 8-bit view. */
1109	uint8_t au8[4];
1110	} X86PTE;
1111	/** Pointer to a page table entry. */
1112	typedef X86PTE *PX86PTE;
1113	/** Pointer to a const page table entry. */
1114	typedef const X86PTE *PCX86PTE;
1115
1116
1117	/**
1118	* PAE page table entry.
1119	*/
1120	typedef struct X86PTEPAEBITS
1121	{
1122	/** Flags whether(=1) or not the page is present. */
1123	uint32_t u1Present : 1;
1124	/** Read(=0) / Write(=1) flag. */
1125	uint32_t u1Write : 1;
1126	/** User(=1) / Supervisor(=0) flag. */
1127	uint32_t u1User : 1;
1128	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1129	uint32_t u1WriteThru : 1;
1130	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1131	uint32_t u1CacheDisable : 1;
1132	/** Accessed flag.
1133	* Indicates that the page have been read or written to. */
1134	uint32_t u1Accessed : 1;
1135	/** Dirty flag.
1136	* Indicates that the page have been written to. */
1137	uint32_t u1Dirty : 1;
1138	/** Reserved / If PAT enabled, bit 2 of the index. */
1139	uint32_t u1PAT : 1;
1140	/** Global flag. (Ignored in all but final level.) */
1141	uint32_t u1Global : 1;
1142	/** Available for use to system software. */
1143	uint32_t u3Available : 3;
1144	/** Physical Page number of the next level - Low Part. Don't use this. */
1145	uint32_t u20PageNoLow : 20;
1146	/** Physical Page number of the next level - High Part. Don't use this. */
1147	uint32_t u20PageNoHigh : 20;
1148	/** MBZ bits */
1149	uint32_t u11Reserved : 11;
1150	/** No Execute flag. */
1151	uint32_t u1NoExecute : 1;
1152	} X86PTEPAEBITS;
1153	/** Pointer to a page table entry. */
1154	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1155	/** Pointer to a page table entry. */
1156	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1157
1158	/**
1159	* PAE Page table entry.
1160	*/
1161	typedef union X86PTEPAE
1162	{
1163	/** Unsigned integer view */
1164	X86PGPAEUINT u;
1165	/** Bit field view. */
1166	X86PTEPAEBITS n;
1167	/** 32-bit view. */
1168	uint32_t au32[2];
1169	/** 16-bit view. */
1170	uint16_t au16[4];
1171	/** 8-bit view. */
1172	uint8_t au8[8];
1173	} X86PTEPAE;
1174	/** Pointer to a PAE page table entry. */
1175	typedef X86PTEPAE *PX86PTEPAE;
1176	/** Pointer to a const PAE page table entry. */
1177	typedef const X86PTEPAE *PCX86PTEPAE;
1178	/** @} */
1179
1180	/**
1181	* Page table.
1182	*/
1183	typedef struct X86PT
1184	{
1185	/** PTE Array. */
1186	X86PTE a[X86_PG_ENTRIES];
1187	} X86PT;
1188	/** Pointer to a page table. */
1189	typedef X86PT *PX86PT;
1190	/** Pointer to a const page table. */
1191	typedef const X86PT *PCX86PT;
1192
1193	/** The page shift to get the PT index. */
1194	#define X86_PT_SHIFT 12
1195	/** The PT index mask (apply to a shifted page address). */
1196	#define X86_PT_MASK 0x3ff
1197
1198
1199	/**
1200	* Page directory.
1201	*/
1202	typedef struct X86PTPAE
1203	{
1204	/** PTE Array. */
1205	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1206	} X86PTPAE;
1207	/** Pointer to a page table. */
1208	typedef X86PTPAE *PX86PTPAE;
1209	/** Pointer to a const page table. */
1210	typedef const X86PTPAE *PCX86PTPAE;
1211
1212	/** The page shift to get the PA PTE index. */
1213	#define X86_PT_PAE_SHIFT 12
1214	/** The PAE PT index mask (apply to a shifted page address). */
1215	#define X86_PT_PAE_MASK 0x1ff
1216
1217
1218	/** @name 4KB Page Directory Entry
1219	* @{
1220	*/
1221	/** Bit 0 - P - Present bit. */
1222	#define X86_PDE_P RT_BIT(0)
1223	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1224	#define X86_PDE_RW RT_BIT(1)
1225	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1226	#define X86_PDE_US RT_BIT(2)
1227	/** Bit 3 - PWT - Page level write thru bit. */
1228	#define X86_PDE_PWT RT_BIT(3)
1229	/** Bit 4 - PCD - Page level cache disable bit. */
1230	#define X86_PDE_PCD RT_BIT(4)
1231	/** Bit 5 - A - Access bit. */
1232	#define X86_PDE_A RT_BIT(5)
1233	/** Bit 7 - PS - Page size attribute.
1234	* Clear mean 4KB pages, set means large pages (2/4MB). */
1235	#define X86_PDE_PS RT_BIT(7)
1236	/** Bits 9-11 - - Available for use to system software. */
1237	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1238	/** Bits 12-31 - - Physical Page number of the next level. */
1239	#define X86_PDE_PG_MASK ( 0xfffff000 )
1240
1241	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1242	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1243	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1244	* we partly or that part into shadow page table entries. Will be corrected
1245	* soon.
1246	*/
1247	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1248	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1249	#else
1250	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1251	#endif
1252	/** Bits 63 - NX - PAE - No execution flag. */
1253	#define X86_PDE_PAE_NX RT_BIT_64(63)
1254
1255	/**
1256	* Page directory entry.
1257	*/
1258	typedef struct X86PDEBITS
1259	{
1260	/** Flags whether(=1) or not the page is present. */
1261	unsigned u1Present : 1;
1262	/** Read(=0) / Write(=1) flag. */
1263	unsigned u1Write : 1;
1264	/** User(=1) / Supervisor (=0) flag. */
1265	unsigned u1User : 1;
1266	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1267	unsigned u1WriteThru : 1;
1268	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1269	unsigned u1CacheDisable : 1;
1270	/** Accessed flag.
1271	* Indicates that the page have been read or written to. */
1272	unsigned u1Accessed : 1;
1273	/** Reserved / Ignored (dirty bit). */
1274	unsigned u1Reserved0 : 1;
1275	/** Size bit if PSE is enabled - in any event it's 0. */
1276	unsigned u1Size : 1;
1277	/** Reserved / Ignored (global bit). */
1278	unsigned u1Reserved1 : 1;
1279	/** Available for use to system software. */
1280	unsigned u3Available : 3;
1281	/** Physical Page number of the next level. */
1282	unsigned u20PageNo : 20;
1283	} X86PDEBITS;
1284	/** Pointer to a page directory entry. */
1285	typedef X86PDEBITS *PX86PDEBITS;
1286	/** Pointer to a const page directory entry. */
1287	typedef const X86PDEBITS *PCX86PDEBITS;
1288
1289
1290	/**
1291	* PAE page directory entry.
1292	*/
1293	typedef struct X86PDEPAEBITS
1294	{
1295	/** Flags whether(=1) or not the page is present. */
1296	uint32_t u1Present : 1;
1297	/** Read(=0) / Write(=1) flag. */
1298	uint32_t u1Write : 1;
1299	/** User(=1) / Supervisor (=0) flag. */
1300	uint32_t u1User : 1;
1301	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1302	uint32_t u1WriteThru : 1;
1303	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1304	uint32_t u1CacheDisable : 1;
1305	/** Accessed flag.
1306	* Indicates that the page have been read or written to. */
1307	uint32_t u1Accessed : 1;
1308	/** Reserved / Ignored (dirty bit). */
1309	uint32_t u1Reserved0 : 1;
1310	/** Size bit if PSE is enabled - in any event it's 0. */
1311	uint32_t u1Size : 1;
1312	/** Reserved / Ignored (global bit). / */
1313	uint32_t u1Reserved1 : 1;
1314	/** Available for use to system software. */
1315	uint32_t u3Available : 3;
1316	/** Physical Page number of the next level - Low Part. Don't use! */
1317	uint32_t u20PageNoLow : 20;
1318	/** Physical Page number of the next level - High Part. Don't use! */
1319	uint32_t u20PageNoHigh : 20;
1320	/** MBZ bits */
1321	uint32_t u11Reserved : 11;
1322	/** No Execute flag. */
1323	uint32_t u1NoExecute : 1;
1324	} X86PDEPAEBITS;
1325	/** Pointer to a page directory entry. */
1326	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1327	/** Pointer to a const page directory entry. */
1328	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1329
1330	/** @} */
1331
1332
1333	/** @name 2/4MB Page Directory Entry
1334	* @{
1335	*/
1336	/** Bit 0 - P - Present bit. */
1337	#define X86_PDE4M_P RT_BIT(0)
1338	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1339	#define X86_PDE4M_RW RT_BIT(1)
1340	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1341	#define X86_PDE4M_US RT_BIT(2)
1342	/** Bit 3 - PWT - Page level write thru bit. */
1343	#define X86_PDE4M_PWT RT_BIT(3)
1344	/** Bit 4 - PCD - Page level cache disable bit. */
1345	#define X86_PDE4M_PCD RT_BIT(4)
1346	/** Bit 5 - A - Access bit. */
1347	#define X86_PDE4M_A RT_BIT(5)
1348	/** Bit 6 - D - Dirty bit. */
1349	#define X86_PDE4M_D RT_BIT(6)
1350	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1351	#define X86_PDE4M_PS RT_BIT(7)
1352	/** Bit 8 - G - Global flag. */
1353	#define X86_PDE4M_G RT_BIT(8)
1354	/** Bits 9-11 - AVL - Available for use to system software. */
1355	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1356	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1357	#define X86_PDE4M_PAT RT_BIT(12)
1358	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1359	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1360	/** Bits 22-31 - - Physical Page number. */
1361	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1362	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1363	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1364	/** The number of bits to the high part of the page number. */
1365	#define X86_PDE4M_PG_HIGH_SHIFT 19
1366
1367	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1368	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1369	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1370	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1371	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1372
1373	/**
1374	* 4MB page directory entry.
1375	*/
1376	typedef struct X86PDE4MBITS
1377	{
1378	/** Flags whether(=1) or not the page is present. */
1379	unsigned u1Present : 1;
1380	/** Read(=0) / Write(=1) flag. */
1381	unsigned u1Write : 1;
1382	/** User(=1) / Supervisor (=0) flag. */
1383	unsigned u1User : 1;
1384	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1385	unsigned u1WriteThru : 1;
1386	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1387	unsigned u1CacheDisable : 1;
1388	/** Accessed flag.
1389	* Indicates that the page have been read or written to. */
1390	unsigned u1Accessed : 1;
1391	/** Dirty flag.
1392	* Indicates that the page have been written to. */
1393	unsigned u1Dirty : 1;
1394	/** Page size flag - always 1 for 4MB entries. */
1395	unsigned u1Size : 1;
1396	/** Global flag. */
1397	unsigned u1Global : 1;
1398	/** Available for use to system software. */
1399	unsigned u3Available : 3;
1400	/** Reserved / If PAT enabled, bit 2 of the index. */
1401	unsigned u1PAT : 1;
1402	/** Bits 32-39 of the page number on AMD64.
1403	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1404	unsigned u8PageNoHigh : 8;
1405	/** Reserved. */
1406	unsigned u1Reserved : 1;
1407	/** Physical Page number of the page. */
1408	unsigned u10PageNo : 10;
1409	} X86PDE4MBITS;
1410	/** Pointer to a page table entry. */
1411	typedef X86PDE4MBITS *PX86PDE4MBITS;
1412	/** Pointer to a const page table entry. */
1413	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1414
1415
1416	/**
1417	* 2MB PAE page directory entry.
1418	*/
1419	typedef struct X86PDE2MPAEBITS
1420	{
1421	/** Flags whether(=1) or not the page is present. */
1422	uint32_t u1Present : 1;
1423	/** Read(=0) / Write(=1) flag. */
1424	uint32_t u1Write : 1;
1425	/** User(=1) / Supervisor(=0) flag. */
1426	uint32_t u1User : 1;
1427	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1428	uint32_t u1WriteThru : 1;
1429	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1430	uint32_t u1CacheDisable : 1;
1431	/** Accessed flag.
1432	* Indicates that the page have been read or written to. */
1433	uint32_t u1Accessed : 1;
1434	/** Dirty flag.
1435	* Indicates that the page have been written to. */
1436	uint32_t u1Dirty : 1;
1437	/** Page size flag - always 1 for 2MB entries. */
1438	uint32_t u1Size : 1;
1439	/** Global flag. */
1440	uint32_t u1Global : 1;
1441	/** Available for use to system software. */
1442	uint32_t u3Available : 3;
1443	/** Reserved / If PAT enabled, bit 2 of the index. */
1444	uint32_t u1PAT : 1;
1445	/** Reserved. */
1446	uint32_t u9Reserved : 9;
1447	/** Physical Page number of the next level - Low part. Don't use! */
1448	uint32_t u10PageNoLow : 10;
1449	/** Physical Page number of the next level - High part. Don't use! */
1450	uint32_t u20PageNoHigh : 20;
1451	/** MBZ bits */
1452	uint32_t u11Reserved : 11;
1453	/** No Execute flag. */
1454	uint32_t u1NoExecute : 1;
1455	} X86PDE2MPAEBITS;
1456	/** Pointer to a 4MB PAE page table entry. */
1457	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1458	/** Pointer to a 4MB PAE page table entry. */
1459	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1460
1461	/** @} */
1462
1463	/**
1464	* Page directory entry.
1465	*/
1466	typedef union X86PDE
1467	{
1468	/** Unsigned integer view. */
1469	X86PGUINT u;
1470	/** Normal view. */
1471	X86PDEBITS n;
1472	/** 4MB view (big). */
1473	X86PDE4MBITS b;
1474	/** 8 bit unsigned integer view. */
1475	uint8_t au8[4];
1476	/** 16 bit unsigned integer view. */
1477	uint16_t au16[2];
1478	/** 32 bit unsigned integer view. */
1479	uint32_t au32[1];
1480	} X86PDE;
1481	/** Pointer to a page directory entry. */
1482	typedef X86PDE *PX86PDE;
1483	/** Pointer to a const page directory entry. */
1484	typedef const X86PDE *PCX86PDE;
1485
1486	/**
1487	* PAE page directory entry.
1488	*/
1489	typedef union X86PDEPAE
1490	{
1491	/** Unsigned integer view. */
1492	X86PGPAEUINT u;
1493	/** Normal view. */
1494	X86PDEPAEBITS n;
1495	/** 2MB page view (big). */
1496	X86PDE2MPAEBITS b;
1497	/** 8 bit unsigned integer view. */
1498	uint8_t au8[8];
1499	/** 16 bit unsigned integer view. */
1500	uint16_t au16[4];
1501	/** 32 bit unsigned integer view. */
1502	uint32_t au32[2];
1503	} X86PDEPAE;
1504	/** Pointer to a page directory entry. */
1505	typedef X86PDEPAE *PX86PDEPAE;
1506	/** Pointer to a const page directory entry. */
1507	typedef const X86PDEPAE *PCX86PDEPAE;
1508
1509	/**
1510	* Page directory.
1511	*/
1512	typedef struct X86PD
1513	{
1514	/** PDE Array. */
1515	X86PDE a[X86_PG_ENTRIES];
1516	} X86PD;
1517	/** Pointer to a page directory. */
1518	typedef X86PD *PX86PD;
1519	/** Pointer to a const page directory. */
1520	typedef const X86PD *PCX86PD;
1521
1522	/** The page shift to get the PD index. */
1523	#define X86_PD_SHIFT 22
1524	/** The PD index mask (apply to a shifted page address). */
1525	#define X86_PD_MASK 0x3ff
1526
1527
1528	/**
1529	* PAE page directory.
1530	*/
1531	typedef struct X86PDPAE
1532	{
1533	/** PDE Array. */
1534	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1535	} X86PDPAE;
1536	/** Pointer to a PAE page directory. */
1537	typedef X86PDPAE *PX86PDPAE;
1538	/** Pointer to a const PAE page directory. */
1539	typedef const X86PDPAE *PCX86PDPAE;
1540
1541	/** The page shift to get the PAE PD index. */
1542	#define X86_PD_PAE_SHIFT 21
1543	/** The PAE PD index mask (apply to a shifted page address). */
1544	#define X86_PD_PAE_MASK 0x1ff
1545
1546
1547	/** @name Page Directory Pointer Table Entry (PAE)
1548	* @{
1549	*/
1550	/** Bit 0 - P - Present bit. */
1551	#define X86_PDPE_P RT_BIT(0)
1552	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1553	#define X86_PDPE_RW RT_BIT(1)
1554	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1555	#define X86_PDPE_US RT_BIT(2)
1556	/** Bit 3 - PWT - Page level write thru bit. */
1557	#define X86_PDPE_PWT RT_BIT(3)
1558	/** Bit 4 - PCD - Page level cache disable bit. */
1559	#define X86_PDPE_PCD RT_BIT(4)
1560	/** Bit 5 - A - Access bit. Long Mode only. */
1561	#define X86_PDPE_A RT_BIT(5)
1562	/** Bits 9-11 - - Available for use to system software. */
1563	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1564	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1565	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1566	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1567	/** @todo Get rid of the above hack; makes code unreadable. */
1568	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1569	#else
1570	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1571	#endif
1572	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1573	#define X86_PDPE_NX RT_BIT_64(63)
1574
1575	/**
1576	* Page directory pointer table entry.
1577	*/
1578	typedef struct X86PDPEBITS
1579	{
1580	/** Flags whether(=1) or not the page is present. */
1581	uint32_t u1Present : 1;
1582	/** Chunk of reserved bits. */
1583	uint32_t u2Reserved : 2;
1584	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1585	uint32_t u1WriteThru : 1;
1586	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1587	uint32_t u1CacheDisable : 1;
1588	/** Chunk of reserved bits. */
1589	uint32_t u4Reserved : 4;
1590	/** Available for use to system software. */
1591	uint32_t u3Available : 3;
1592	/** Physical Page number of the next level - Low Part. Don't use! */
1593	uint32_t u20PageNoLow : 20;
1594	/** Physical Page number of the next level - High Part. Don't use! */
1595	uint32_t u20PageNoHigh : 20;
1596	/** MBZ bits */
1597	uint32_t u12Reserved : 12;
1598	} X86PDPEBITS;
1599	/** Pointer to a page directory pointer table entry. */
1600	typedef X86PDPEBITS *PX86PTPEBITS;
1601	/** Pointer to a const page directory pointer table entry. */
1602	typedef const X86PDPEBITS *PCX86PTPEBITS;
1603
1604	/**
1605	* Page directory pointer table entry. AMD64 version
1606	*/
1607	typedef struct X86PDPEAMD64BITS
1608	{
1609	/** Flags whether(=1) or not the page is present. */
1610	uint32_t u1Present : 1;
1611	/** Read(=0) / Write(=1) flag. */
1612	uint32_t u1Write : 1;
1613	/** User(=1) / Supervisor (=0) flag. */
1614	uint32_t u1User : 1;
1615	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1616	uint32_t u1WriteThru : 1;
1617	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1618	uint32_t u1CacheDisable : 1;
1619	/** Accessed flag.
1620	* Indicates that the page have been read or written to. */
1621	uint32_t u1Accessed : 1;
1622	/** Chunk of reserved bits. */
1623	uint32_t u3Reserved : 3;
1624	/** Available for use to system software. */
1625	uint32_t u3Available : 3;
1626	/** Physical Page number of the next level - Low Part. Don't use! */
1627	uint32_t u20PageNoLow : 20;
1628	/** Physical Page number of the next level - High Part. Don't use! */
1629	uint32_t u20PageNoHigh : 20;
1630	/** MBZ bits */
1631	uint32_t u11Reserved : 11;
1632	/** No Execute flag. */
1633	uint32_t u1NoExecute : 1;
1634	} X86PDPEAMD64BITS;
1635	/** Pointer to a page directory pointer table entry. */
1636	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1637	/** Pointer to a const page directory pointer table entry. */
1638	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1639
1640	/**
1641	* Page directory pointer table entry.
1642	*/
1643	typedef union X86PDPE
1644	{
1645	/** Unsigned integer view. */
1646	X86PGPAEUINT u;
1647	/** Normal view. */
1648	X86PDPEBITS n;
1649	/** AMD64 view. */
1650	X86PDPEAMD64BITS lm;
1651	/** 8 bit unsigned integer view. */
1652	uint8_t au8[8];
1653	/** 16 bit unsigned integer view. */
1654	uint16_t au16[4];
1655	/** 32 bit unsigned integer view. */
1656	uint32_t au32[2];
1657	} X86PDPE;
1658	/** Pointer to a page directory pointer table entry. */
1659	typedef X86PDPE *PX86PDPE;
1660	/** Pointer to a const page directory pointer table entry. */
1661	typedef const X86PDPE *PCX86PDPE;
1662
1663
1664	/**
1665	* Page directory pointer table.
1666	*/
1667	typedef struct X86PDPT
1668	{
1669	/** PDE Array. */
1670	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1671	} X86PDPT;
1672	/** Pointer to a page directory pointer table. */
1673	typedef X86PDPT *PX86PDPT;
1674	/** Pointer to a const page directory pointer table. */
1675	typedef const X86PDPT *PCX86PDPT;
1676
1677	/** The page shift to get the PDPT index. */
1678	#define X86_PDPT_SHIFT 30
1679	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1680	#define X86_PDPT_MASK_PAE 0x3
1681	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1682	#define X86_PDPT_MASK_AMD64 0x1ff
1683
1684	/** @} */
1685
1686
1687	/** @name Page Map Level-4 Entry (Long Mode PAE)
1688	* @{
1689	*/
1690	/** Bit 0 - P - Present bit. */
1691	#define X86_PML4E_P RT_BIT(0)
1692	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1693	#define X86_PML4E_RW RT_BIT(1)
1694	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1695	#define X86_PML4E_US RT_BIT(2)
1696	/** Bit 3 - PWT - Page level write thru bit. */
1697	#define X86_PML4E_PWT RT_BIT(3)
1698	/** Bit 4 - PCD - Page level cache disable bit. */
1699	#define X86_PML4E_PCD RT_BIT(4)
1700	/** Bit 5 - A - Access bit. */
1701	#define X86_PML4E_A RT_BIT(5)
1702	/** Bits 9-11 - - Available for use to system software. */
1703	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1704	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1705	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1706	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1707	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1708	#else
1709	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1710	#endif
1711	/** Bits 63 - NX - PAE - No execution flag. */
1712	#define X86_PML4E_NX RT_BIT_64(63)
1713
1714	/**
1715	* Page Map Level-4 Entry
1716	*/
1717	typedef struct X86PML4EBITS
1718	{
1719	/** Flags whether(=1) or not the page is present. */
1720	uint32_t u1Present : 1;
1721	/** Read(=0) / Write(=1) flag. */
1722	uint32_t u1Write : 1;
1723	/** User(=1) / Supervisor (=0) flag. */
1724	uint32_t u1User : 1;
1725	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1726	uint32_t u1WriteThru : 1;
1727	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1728	uint32_t u1CacheDisable : 1;
1729	/** Accessed flag.
1730	* Indicates that the page have been read or written to. */
1731	uint32_t u1Accessed : 1;
1732	/** Chunk of reserved bits. */
1733	uint32_t u3Reserved : 3;
1734	/** Available for use to system software. */
1735	uint32_t u3Available : 3;
1736	/** Physical Page number of the next level - Low Part. Don't use! */
1737	uint32_t u20PageNoLow : 20;
1738	/** Physical Page number of the next level - High Part. Don't use! */
1739	uint32_t u20PageNoHigh : 20;
1740	/** MBZ bits */
1741	uint32_t u11Reserved : 11;
1742	/** No Execute flag. */
1743	uint32_t u1NoExecute : 1;
1744	} X86PML4EBITS;
1745	/** Pointer to a page map level-4 entry. */
1746	typedef X86PML4EBITS *PX86PML4EBITS;
1747	/** Pointer to a const page map level-4 entry. */
1748	typedef const X86PML4EBITS *PCX86PML4EBITS;
1749
1750	/**
1751	* Page Map Level-4 Entry.
1752	*/
1753	typedef union X86PML4E
1754	{
1755	/** Unsigned integer view. */
1756	X86PGPAEUINT u;
1757	/** Normal view. */
1758	X86PML4EBITS n;
1759	/** 8 bit unsigned integer view. */
1760	uint8_t au8[8];
1761	/** 16 bit unsigned integer view. */
1762	uint16_t au16[4];
1763	/** 32 bit unsigned integer view. */
1764	uint32_t au32[2];
1765	} X86PML4E;
1766	/** Pointer to a page map level-4 entry. */
1767	typedef X86PML4E *PX86PML4E;
1768	/** Pointer to a const page map level-4 entry. */
1769	typedef const X86PML4E *PCX86PML4E;
1770
1771
1772	/**
1773	* Page Map Level-4.
1774	*/
1775	typedef struct X86PML4
1776	{
1777	/** PDE Array. */
1778	X86PML4E a[X86_PG_PAE_ENTRIES];
1779	} X86PML4;
1780	/** Pointer to a page map level-4. */
1781	typedef X86PML4 *PX86PML4;
1782	/** Pointer to a const page map level-4. */
1783	typedef const X86PML4 *PCX86PML4;
1784
1785	/** The page shift to get the PML4 index. */
1786	#define X86_PML4_SHIFT 39
1787	/** The PML4 index mask (apply to a shifted page address). */
1788	#define X86_PML4_MASK 0x1ff
1789
1790	/** @} */
1791
1792	/** @} */
1793
1794
1795	/**
1796	* 80-bit MMX/FPU register type.
1797	*/
1798	typedef struct X86FPUMMX
1799	{
1800	uint8_t reg[10];
1801	} X86FPUMMX;
1802	/** Pointer to a 80-bit MMX/FPU register type. */
1803	typedef X86FPUMMX *PX86FPUMMX;
1804	/** Pointer to a const 80-bit MMX/FPU register type. */
1805	typedef const X86FPUMMX *PCX86FPUMMX;
1806
1807	/**
1808	* FPU state (aka FSAVE/FRSTOR Memory Region).
1809	*/
1810	#pragma pack(1)
1811	typedef struct X86FPUSTATE
1812	{
1813	/** Control word. */
1814	uint16_t FCW;
1815	/** Alignment word */
1816	uint16_t Dummy1;
1817	/** Status word. */
1818	uint16_t FSW;
1819	/** Alignment word */
1820	uint16_t Dummy2;
1821	/** Tag word */
1822	uint16_t FTW;
1823	/** Alignment word */
1824	uint16_t Dummy3;
1825
1826	/** Instruction pointer. */
1827	uint32_t FPUIP;
1828	/** Code selector. */
1829	uint16_t CS;
1830	/** Opcode. */
1831	uint16_t FOP;
1832	/** FOO. */
1833	uint32_t FPUOO;
1834	/** FOS. */
1835	uint32_t FPUOS;
1836	/** FPU view - todo. */
1837	X86FPUMMX regs[8];
1838	} X86FPUSTATE;
1839	#pragma pack()
1840	/** Pointer to a FPU state. */
1841	typedef X86FPUSTATE *PX86FPUSTATE;
1842	/** Pointer to a const FPU state. */
1843	typedef const X86FPUSTATE *PCX86FPUSTATE;
1844
1845	/**
1846	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1847	*/
1848	#pragma pack(1)
1849	typedef struct X86FXSTATE
1850	{
1851	/** Control word. */
1852	uint16_t FCW;
1853	/** Status word. */
1854	uint16_t FSW;
1855	/** Tag word (it's a byte actually). */
1856	uint8_t FTW;
1857	uint8_t huh1;
1858	/** Opcode. */
1859	uint16_t FOP;
1860	/** Instruction pointer. */
1861	uint32_t FPUIP;
1862	/** Code selector. */
1863	uint16_t CS;
1864	uint16_t Rsvrd1;
1865	/* - offset 16 - */
1866	/** Data pointer. */
1867	uint32_t FPUDP;
1868	/** Data segment */
1869	uint16_t DS;
1870	uint16_t Rsrvd2;
1871	uint32_t MXCSR;
1872	uint32_t MXCSR_MASK;
1873	/* - offset 32 - */
1874	union
1875	{
1876	/** MMX view. */
1877	uint64_t mmx;
1878	/** FPU view - todo. */
1879	X86FPUMMX fpu;
1880	/** 8-bit view. */
1881	uint8_t au8[16];
1882	/** 16-bit view. */
1883	uint16_t au16[8];
1884	/** 32-bit view. */
1885	uint32_t au32[4];
1886	/** 64-bit view. */
1887	uint64_t au64[2];
1888	/** 128-bit view. (yeah, very helpful) */
1889	uint128_t au128[1];
1890	} aRegs[8];
1891	/* - offset 160 - */
1892	union
1893	{
1894	/** XMM Register view . /
1895	uint128_t xmm;
1896	/** 8-bit view. */
1897	uint8_t au8[16];
1898	/** 16-bit view. */
1899	uint16_t au16[8];
1900	/** 32-bit view. */
1901	uint32_t au32[4];
1902	/** 64-bit view. */
1903	uint64_t au64[2];
1904	/** 128-bit view. (yeah, very helpful) */
1905	uint128_t au128[1];
1906	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1907	/* - offset 416 - */
1908	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1909	} X86FXSTATE;
1910	#pragma pack()
1911	/** Pointer to a FPU Extended state. */
1912	typedef X86FXSTATE *PX86FXSTATE;
1913	/** Pointer to a const FPU Extended state. */
1914	typedef const X86FXSTATE *PCX86FXSTATE;
1915
1916
1917	/** @name Selector Descriptor
1918	* @{
1919	*/
1920
1921	/**
1922	* Descriptor attributes.
1923	*/
1924	typedef struct X86DESCATTRBITS
1925	{
1926	/** Segment Type. */
1927	unsigned u4Type : 4;
1928	/** Descriptor Type. System(=0) or code/data selector */
1929	unsigned u1DescType : 1;
1930	/** Descriptor Privelege level. */
1931	unsigned u2Dpl : 2;
1932	/** Flags selector present(=1) or not. */
1933	unsigned u1Present : 1;
1934	/** Segment limit 16-19. */
1935	unsigned u4LimitHigh : 4;
1936	/** Available for system software. */
1937	unsigned u1Available : 1;
1938	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1939	unsigned u1Long : 1;
1940	/** This flags meaning depends on the segment type. Try make sense out
1941	* of the intel manual yourself. */
1942	unsigned u1DefBig : 1;
1943	/** Granularity of the limit. If set 4KB granularity is used, if
1944	* clear byte. */
1945	unsigned u1Granularity : 1;
1946	} X86DESCATTRBITS;
1947
1948
1949	#pragma pack(1)
1950	typedef union X86DESCATTR
1951	{
1952	/** Unsigned integer view. */
1953	uint32_t u;
1954	/** Normal view. */
1955	X86DESCATTRBITS n;
1956	} X86DESCATTR;
1957	#pragma pack()
1958	/** Pointer to descriptor attributes. */
1959	typedef X86DESCATTR *PX86DESCATTR;
1960	/** Pointer to const descriptor attributes. */
1961	typedef const X86DESCATTR *PCX86DESCATTR;
1962
1963
1964	/**
1965	* Generic descriptor table entry
1966	*/
1967	#pragma pack(1)
1968	typedef struct X86DESCGENERIC
1969	{
1970	/** Limit - Low word. */
1971	unsigned u16LimitLow : 16;
1972	/** Base address - lowe word.
1973	* Don't try set this to 24 because MSC is doing stupid things then. */
1974	unsigned u16BaseLow : 16;
1975	/** Base address - first 8 bits of high word. */
1976	unsigned u8BaseHigh1 : 8;
1977	/** Segment Type. */
1978	unsigned u4Type : 4;
1979	/** Descriptor Type. System(=0) or code/data selector */
1980	unsigned u1DescType : 1;
1981	/** Descriptor Privelege level. */
1982	unsigned u2Dpl : 2;
1983	/** Flags selector present(=1) or not. */
1984	unsigned u1Present : 1;
1985	/** Segment limit 16-19. */
1986	unsigned u4LimitHigh : 4;
1987	/** Available for system software. */
1988	unsigned u1Available : 1;
1989	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1990	unsigned u1Long : 1;
1991	/** This flags meaning depends on the segment type. Try make sense out
1992	* of the intel manual yourself. */
1993	unsigned u1DefBig : 1;
1994	/** Granularity of the limit. If set 4KB granularity is used, if
1995	* clear byte. */
1996	unsigned u1Granularity : 1;
1997	/** Base address - highest 8 bits. */
1998	unsigned u8BaseHigh2 : 8;
1999	} X86DESCGENERIC;
2000	#pragma pack()
2001	/** Pointer to a generic descriptor entry. */
2002	typedef X86DESCGENERIC *PX86DESCGENERIC;
2003	/** Pointer to a const generic descriptor entry. */
2004	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2005
2006	/**
2007	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2008	*/
2009	typedef struct X86DESCGATE
2010	{
2011	/** Target code segment offset - Low word.
2012	* Ignored if task-gate. */
2013	unsigned u16OffsetLow : 16;
2014	/** Target code segment selector for call-, interrupt- and trap-gates,
2015	* TSS selector if task-gate. */
2016	unsigned u16Sel : 16;
2017	/** Number of parameters for a call-gate.
2018	* Ignored if interrupt-, trap- or task-gate. */
2019	unsigned u4ParmCount : 4;
2020	/** Reserved / ignored. */
2021	unsigned u4Reserved : 4;
2022	/** Segment Type. */
2023	unsigned u4Type : 4;
2024	/** Descriptor Type (0 = system). */
2025	unsigned u1DescType : 1;
2026	/** Descriptor Privelege level. */
2027	unsigned u2Dpl : 2;
2028	/** Flags selector present(=1) or not. */
2029	unsigned u1Present : 1;
2030	/** Target code segment offset - High word.
2031	* Ignored if task-gate. */
2032	unsigned u16OffsetHigh : 16;
2033	} X86DESCGATE;
2034	AssertCompileSize(X86DESCGATE, 8);
2035	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2036	typedef X86DESCGATE *PX86DESCGATE;
2037	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2038	typedef const X86DESCGATE *PCX86DESCGATE;
2039
2040	/**
2041	* Descriptor table entry.
2042	*/
2043	#pragma pack(1)
2044	typedef union X86DESC
2045	{
2046	/** Generic descriptor view. */
2047	X86DESCGENERIC Gen;
2048	/** Gate descriptor view. */
2049	X86DESCGATE Gate;
2050
2051	/** 8 bit unsigned interger view. */
2052	uint8_t au8[8];
2053	/** 16 bit unsigned interger view. */
2054	uint16_t au16[4];
2055	/** 32 bit unsigned interger view. */
2056	uint32_t au32[2];
2057	} X86DESC;
2058	AssertCompileSize(X86DESC, 8);
2059	#pragma pack()
2060	/** Pointer to descriptor table entry. */
2061	typedef X86DESC *PX86DESC;
2062	/** Pointer to const descriptor table entry. */
2063	typedef const X86DESC *PCX86DESC;
2064
2065	/** @def X86DESC_BASE
2066	* Return the base address of a descriptor.
2067	*/
2068	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2069	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2070	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2071	\| ( (desc).Gen.u16BaseLow ) )
2072
2073	/** @def X86DESC_LIMIT
2074	* Return the limit of a descriptor.
2075	*/
2076	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2077	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2078	\| ( (desc).Gen.u16LimitLow ) )
2079
2080	/**
2081	* 64 bits generic descriptor table entry
2082	* Note: most of these bits have no meaning in long mode.
2083	*/
2084	#pragma pack(1)
2085	typedef struct X86DESC64GENERIC
2086	{
2087	/** Limit - Low word - IGNORED. */
2088	unsigned u16LimitLow : 16;
2089	/** Base address - lowe word. - IGNORED
2090	* Don't try set this to 24 because MSC is doing stupid things then. */
2091	unsigned u16BaseLow : 16;
2092	/** Base address - first 8 bits of high word. - IGNORED */
2093	unsigned u8BaseHigh1 : 8;
2094	/** Segment Type. */
2095	unsigned u4Type : 4;
2096	/** Descriptor Type. System(=0) or code/data selector */
2097	unsigned u1DescType : 1;
2098	/** Descriptor Privelege level. */
2099	unsigned u2Dpl : 2;
2100	/** Flags selector present(=1) or not. */
2101	unsigned u1Present : 1;
2102	/** Segment limit 16-19. - IGNORED */
2103	unsigned u4LimitHigh : 4;
2104	/** Available for system software. - IGNORED */
2105	unsigned u1Available : 1;
2106	/** Long mode flag. */
2107	unsigned u1Long : 1;
2108	/** This flags meaning depends on the segment type. Try make sense out
2109	* of the intel manual yourself. */
2110	unsigned u1DefBig : 1;
2111	/** Granularity of the limit. If set 4KB granularity is used, if
2112	* clear byte. - IGNORED */
2113	unsigned u1Granularity : 1;
2114	/** Base address - highest 8 bits. - IGNORED */
2115	unsigned u8BaseHigh2 : 8;
2116	/** Base address - bits 63-32. */
2117	unsigned u32BaseHigh3 : 32;
2118	unsigned u8Reserved : 8;
2119	unsigned u5Zeros : 5;
2120	unsigned u19Reserved : 19;
2121	} X86DESC64GENERIC;
2122	#pragma pack()
2123	/** Pointer to a generic descriptor entry. */
2124	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2125	/** Pointer to a const generic descriptor entry. */
2126	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2127
2128	/**
2129	* System descriptor table entry (64 bits)
2130	*
2131	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2132	*/
2133	#pragma pack(1)
2134	typedef struct X86DESC64SYSTEM
2135	{
2136	/** Limit - Low word. */
2137	unsigned u16LimitLow : 16;
2138	/** Base address - lowe word.
2139	* Don't try set this to 24 because MSC is doing stupid things then. */
2140	unsigned u16BaseLow : 16;
2141	/** Base address - first 8 bits of high word. */
2142	unsigned u8BaseHigh1 : 8;
2143	/** Segment Type. */
2144	unsigned u4Type : 4;
2145	/** Descriptor Type. System(=0) or code/data selector */
2146	unsigned u1DescType : 1;
2147	/** Descriptor Privelege level. */
2148	unsigned u2Dpl : 2;
2149	/** Flags selector present(=1) or not. */
2150	unsigned u1Present : 1;
2151	/** Segment limit 16-19. */
2152	unsigned u4LimitHigh : 4;
2153	/** Available for system software. */
2154	unsigned u1Available : 1;
2155	/** Reserved - 0. */
2156	unsigned u1Reserved : 1;
2157	/** This flags meaning depends on the segment type. Try make sense out
2158	* of the intel manual yourself. */
2159	unsigned u1DefBig : 1;
2160	/** Granularity of the limit. If set 4KB granularity is used, if
2161	* clear byte. */
2162	unsigned u1Granularity : 1;
2163	/** Base address - bits 31-24. */
2164	unsigned u8BaseHigh2 : 8;
2165	/** Base address - bits 63-32. */
2166	unsigned u32BaseHigh3 : 32;
2167	unsigned u8Reserved : 8;
2168	unsigned u5Zeros : 5;
2169	unsigned u19Reserved : 19;
2170	} X86DESC64SYSTEM;
2171	#pragma pack()
2172	/** Pointer to a system descriptor entry. */
2173	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2174	/** Pointer to a const system descriptor entry. */
2175	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2176
2177	/**
2178	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2179	*/
2180	typedef struct X86DESC64GATE
2181	{
2182	/** Target code segment offset - Low word. */
2183	unsigned u16OffsetLow : 16;
2184	/** Target code segment selector. */
2185	unsigned u16Sel : 16;
2186	/** Interrupt stack table for interrupt- and trap-gates.
2187	* Ignored by call-gates. */
2188	unsigned u3IST : 3;
2189	/** Reserved / ignored. */
2190	unsigned u5Reserved : 5;
2191	/** Segment Type. */
2192	unsigned u4Type : 4;
2193	/** Descriptor Type (0 = system). */
2194	unsigned u1DescType : 1;
2195	/** Descriptor Privelege level. */
2196	unsigned u2Dpl : 2;
2197	/** Flags selector present(=1) or not. */
2198	unsigned u1Present : 1;
2199	/** Target code segment offset - High word.
2200	* Ignored if task-gate. */
2201	unsigned u16OffsetHigh : 16;
2202	/** Target code segment offset - Top dword.
2203	* Ignored if task-gate. */
2204	unsigned u32OffsetTop : 32;
2205	/** Reserved / ignored / must be zero.
2206	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2207	unsigned u32Reserved : 32;
2208	} X86DESC64GATE;
2209	AssertCompileSize(X86DESC64GATE, 16);
2210	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2211	typedef X86DESC64GATE *PX86DESC64GATE;
2212	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2213	typedef const X86DESC64GATE *PCX86DESC64GATE;
2214
2215
2216	/**
2217	* Descriptor table entry.
2218	*/
2219	#pragma pack(1)
2220	typedef union X86DESC64
2221	{
2222	/** Generic descriptor view. */
2223	X86DESC64GENERIC Gen;
2224	/** System descriptor view. */
2225	X86DESC64SYSTEM System;
2226	/** Gate descriptor view. */
2227	X86DESC64GATE Gate;
2228
2229	/** 8 bit unsigned interger view. */
2230	uint8_t au8[16];
2231	/** 16 bit unsigned interger view. */
2232	uint16_t au16[8];
2233	/** 32 bit unsigned interger view. */
2234	uint32_t au32[4];
2235	/** 64 bit unsigned interger view. */
2236	uint64_t au64[2];
2237	} X86DESC64;
2238	AssertCompileSize(X86DESC64, 16);
2239	#pragma pack()
2240	/** Pointer to descriptor table entry. */
2241	typedef X86DESC64 *PX86DESC64;
2242	/** Pointer to const descriptor table entry. */
2243	typedef const X86DESC64 *PCX86DESC64;
2244
2245	#if HC_ARCH_BITS == 64
2246	typedef X86DESC64 X86DESCHC;
2247	typedef X86DESC64 *PX86DESCHC;
2248	#else
2249	typedef X86DESC X86DESCHC;
2250	typedef X86DESC *PX86DESCHC;
2251	#endif
2252
2253	/** @def X86DESC64_BASE
2254	* Return the base of a 64-bit descriptor.
2255	*/
2256	#define X86DESC64_BASE(desc) \
2257	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2258	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2259	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2260	\| ( (desc).Gen.u16BaseLow ) )
2261
2262
2263	/** @name Selector Descriptor Types.
2264	* @{
2265	*/
2266
2267	/** @name Non-System Selector Types.
2268	* @{ */
2269	/** Code(=set)/Data(=clear) bit. */
2270	#define X86_SEL_TYPE_CODE 8
2271	/** Memory(=set)/System(=clear) bit. */
2272	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2273	/** Accessed bit. */
2274	#define X86_SEL_TYPE_ACCESSED 1
2275	/** Expand down bit (for data selectors only). */
2276	#define X86_SEL_TYPE_DOWN 4
2277	/** Conforming bit (for code selectors only). */
2278	#define X86_SEL_TYPE_CONF 4
2279	/** Write bit (for data selectors only). */
2280	#define X86_SEL_TYPE_WRITE 2
2281	/** Read bit (for code selectors only). */
2282	#define X86_SEL_TYPE_READ 2
2283
2284	/** Read only selector type. */
2285	#define X86_SEL_TYPE_RO 0
2286	/** Accessed read only selector type. */
2287	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2288	/** Read write selector type. */
2289	#define X86_SEL_TYPE_RW 2
2290	/** Accessed read write selector type. */
2291	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2292	/** Expand down read only selector type. */
2293	#define X86_SEL_TYPE_RO_DOWN 4
2294	/** Accessed expand down read only selector type. */
2295	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2296	/** Expand down read write selector type. */
2297	#define X86_SEL_TYPE_RW_DOWN 6
2298	/** Accessed expand down read write selector type. */
2299	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2300	/** Execute only selector type. */
2301	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2302	/** Accessed execute only selector type. */
2303	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2304	/** Execute and read selector type. */
2305	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2306	/** Accessed execute and read selector type. */
2307	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2308	/** Conforming execute only selector type. */
2309	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2310	/** Accessed Conforming execute only selector type. */
2311	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2312	/** Conforming execute and write selector type. */
2313	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2314	/** Accessed Conforming execute and write selector type. */
2315	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2316	/** @} */
2317
2318
2319	/** @name System Selector Types.
2320	* @{ */
2321	/** Undefined system selector type. */
2322	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2323	/** 286 TSS selector. */
2324	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2325	/** LDT selector. */
2326	#define X86_SEL_TYPE_SYS_LDT 2
2327	/** 286 TSS selector - Busy. */
2328	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2329	/** 286 Callgate selector. */
2330	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2331	/** Taskgate selector. */
2332	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2333	/** 286 Interrupt gate selector. */
2334	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2335	/** 286 Trapgate selector. */
2336	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2337	/** Undefined system selector. */
2338	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2339	/** 386 TSS selector. */
2340	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2341	/** Undefined system selector. */
2342	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2343	/** 386 TSS selector - Busy. */
2344	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2345	/** 386 Callgate selector. */
2346	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2347	/** Undefined system selector. */
2348	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2349	/** 386 Interruptgate selector. */
2350	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2351	/** 386 Trapgate selector. */
2352	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2353	/** @} */
2354
2355	/** @name AMD64 System Selector Types.
2356	* @{ */
2357	#define AMD64_SEL_TYPE_SYS_LDT 2
2358	/** 286 TSS selector - Busy. */
2359	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2360	/** 386 TSS selector - Busy. */
2361	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2362	/** 386 Callgate selector. */
2363	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2364	/** 386 Interruptgate selector. */
2365	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2366	/** 386 Trapgate selector. */
2367	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2368	/** @} */
2369
2370	/** @} */
2371
2372
2373	/** @name Descriptor Table Entry Flag Masks.
2374	* These are for the 2nd 32-bit word of a descriptor.
2375	* @{ */
2376	/** Bits 8-11 - TYPE - Descriptor type mask. */
2377	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2378	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2379	#define X86_DESC_S RT_BIT(12)
2380	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2381	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2382	/** Bit 15 - P - Present. */
2383	#define X86_DESC_P RT_BIT(15)
2384	/** Bit 20 - AVL - Available for system software. */
2385	#define X86_DESC_AVL RT_BIT(20)
2386	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2387	#define X86_DESC_DB RT_BIT(22)
2388	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2389	* used, if clear byte. */
2390	#define X86_DESC_G RT_BIT(23)
2391	/** @} */
2392
2393	/** @} */
2394
2395	/** @name Task segment.
2396	* @{
2397	*/
2398	#pragma pack(1)
2399	typedef struct X86TSS32
2400	{
2401	/** Back link to previous task. (static) */
2402	RTSEL selPrev;
2403	uint16_t padding1;
2404	/** Ring-0 stack pointer. (static) */
2405	uint32_t esp0;
2406	/** Ring-0 stack segment. (static) */
2407	RTSEL ss0;
2408	uint16_t padding_ss0;
2409	/** Ring-1 stack pointer. (static) */
2410	uint32_t esp1;
2411	/** Ring-1 stack segment. (static) */
2412	RTSEL ss1;
2413	uint16_t padding_ss1;
2414	/** Ring-2 stack pointer. (static) */
2415	uint32_t esp2;
2416	/** Ring-2 stack segment. (static) */
2417	RTSEL ss2;
2418	uint16_t padding_ss2;
2419	/** Page directory for the task. (static) */
2420	uint32_t cr3;
2421	/** EIP before task switch. */
2422	uint32_t eip;
2423	/** EFLAGS before task switch. */
2424	uint32_t eflags;
2425	/** EAX before task switch. */
2426	uint32_t eax;
2427	/** ECX before task switch. */
2428	uint32_t ecx;
2429	/** EDX before task switch. */
2430	uint32_t edx;
2431	/** EBX before task switch. */
2432	uint32_t ebx;
2433	/** ESP before task switch. */
2434	uint32_t esp;
2435	/** EBP before task switch. */
2436	uint32_t ebp;
2437	/** ESI before task switch. */
2438	uint32_t esi;
2439	/** EDI before task switch. */
2440	uint32_t edi;
2441	/** ES before task switch. */
2442	RTSEL es;
2443	uint16_t padding_es;
2444	/** CS before task switch. */
2445	RTSEL cs;
2446	uint16_t padding_cs;
2447	/** SS before task switch. */
2448	RTSEL ss;
2449	uint16_t padding_ss;
2450	/** DS before task switch. */
2451	RTSEL ds;
2452	uint16_t padding_ds;
2453	/** FS before task switch. */
2454	RTSEL fs;
2455	uint16_t padding_fs;
2456	/** GS before task switch. */
2457	RTSEL gs;
2458	uint16_t padding_gs;
2459	/** LDTR before task switch. */
2460	RTSEL selLdt;
2461	uint16_t padding_ldt;
2462	/** Debug trap flag */
2463	uint16_t fDebugTrap;
2464	/** Offset relative to the TSS of the start of the I/O Bitmap
2465	* and the end of the interrupt redirection bitmap. */
2466	uint16_t offIoBitmap;
2467	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2468	uint8_t IntRedirBitmap[32];
2469	} X86TSS32;
2470	#pragma pack()
2471	/** Pointer to task segment. */
2472	typedef X86TSS32 *PX86TSS32;
2473	/** Pointer to const task segment. */
2474	typedef const X86TSS32 *PCX86TSS32;
2475	/** @} */
2476
2477
2478	/** @name 64 bits Task segment.
2479	* @{
2480	*/
2481	#pragma pack(1)
2482	typedef struct X86TSS64
2483	{
2484	/** Reserved. */
2485	uint32_t u32Reserved;
2486	/** Ring-0 stack pointer. (static) */
2487	uint64_t rsp0;
2488	/** Ring-1 stack pointer. (static) */
2489	uint64_t rsp1;
2490	/** Ring-2 stack pointer. (static) */
2491	uint64_t rsp2;
2492	/** Reserved. */
2493	uint32_t u32Reserved2[2];
2494	/* IST */
2495	uint64_t ist1;
2496	uint64_t ist2;
2497	uint64_t ist3;
2498	uint64_t ist4;
2499	uint64_t ist5;
2500	uint64_t ist6;
2501	uint64_t ist7;
2502	/* Reserved. */
2503	uint16_t u16Reserved[5];
2504	/** Offset relative to the TSS of the start of the I/O Bitmap
2505	* and the end of the interrupt redirection bitmap. */
2506	uint16_t offIoBitmap;
2507	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2508	uint8_t IntRedirBitmap[32];
2509	} X86TSS64;
2510	#pragma pack()
2511	/** Pointer to task segment. */
2512	typedef X86TSS64 *PX86TSS64;
2513	/** Pointer to const task segment. */
2514	typedef const X86TSS64 *PCX86TSS64;
2515	AssertCompileSize(X86TSS64, 136);
2516
2517	/** @} */
2518
2519
2520	/** @name Selectors.
2521	* @{
2522	*/
2523
2524	/**
2525	* The shift used to convert a selector from and to index an index (C).
2526	*/
2527	#define X86_SEL_SHIFT 3
2528
2529	/**
2530	* The shift used to convert a selector from and to index an index (C).
2531	*/
2532	#define AMD64_SEL_SHIFT 4
2533
2534	/** @def X86_SEL_SHIFT_HC
2535	* This is for use with X86DESCHC. */
2536	#if HC_ARCH_BITS == 64
2537	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2538	#else
2539	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2540	#endif
2541
2542	/**
2543	* The mask used to mask off the table indicator and CPL of an selector.
2544	*/
2545	#define X86_SEL_MASK 0xfff8
2546
2547	/**
2548	* The bit indicating that a selector is in the LDT and not in the GDT.
2549	*/
2550	#define X86_SEL_LDT 0x0004
2551	/**
2552	* The bit mask for getting the RPL of a selector.
2553	*/
2554	#define X86_SEL_RPL 0x0003
2555
2556	/** @} */
2557
2558
2559	/**
2560	* x86 Exceptions/Faults/Traps.
2561	*/
2562	typedef enum X86XCPT
2563	{
2564	/** \#DE - Divide error. */
2565	X86_XCPT_DE = 0x00,
2566	/** \#DB - Debug event (single step, DRx, ..) */
2567	X86_XCPT_DB = 0x01,
2568	/** NMI - Non-Maskable Interrupt */
2569	X86_XCPT_NMI = 0x02,
2570	/** \#BP - Breakpoint (INT3). */
2571	X86_XCPT_BP = 0x03,
2572	/** \#OF - Overflow (INTO). */
2573	X86_XCPT_OF = 0x04,
2574	/** \#BR - Bound range exceeded (BOUND). */
2575	X86_XCPT_BR = 0x05,
2576	/** \#UD - Undefined opcode. */
2577	X86_XCPT_UD = 0x06,
2578	/** \#NM - Device not available (math coprocessor device). */
2579	X86_XCPT_NM = 0x07,
2580	/** \#DF - Double fault. */
2581	X86_XCPT_DF = 0x08,
2582	/** ??? - Coprocessor segment overrun (obsolete). */
2583	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2584	/** \#TS - Taskswitch (TSS). */
2585	X86_XCPT_TS = 0x0a,
2586	/** \#NP - Segment no present. */
2587	X86_XCPT_NP = 0x0b,
2588	/** \#SS - Stack segment fault. */
2589	X86_XCPT_SS = 0x0c,
2590	/** \#GP - General protection fault. */
2591	X86_XCPT_GP = 0x0d,
2592	/** \#PF - Page fault. */
2593	X86_XCPT_PF = 0x0e,
2594	/* 0x0f is reserved. */
2595	/** \#MF - Math fault (FPU). */
2596	X86_XCPT_MF = 0x10,
2597	/** \#AC - Alignment check. */
2598	X86_XCPT_AC = 0x11,
2599	/** \#MC - Machine check. */
2600	X86_XCPT_MC = 0x12,
2601	/** \#XF - SIMD Floating-Pointer Exception. */
2602	X86_XCPT_XF = 0x13
2603	} X86XCPT;
2604	/** Pointer to a x86 exception code. */
2605	typedef X86XCPT *PX86XCPT;
2606	/** Pointer to a const x86 exception code. */
2607	typedef const X86XCPT *PCX86XCPT;
2608
2609
2610	/** @name Trap Error Codes
2611	* @{
2612	*/
2613	/** External indicator. */
2614	#define X86_TRAP_ERR_EXTERNAL 1
2615	/** IDT indicator. */
2616	#define X86_TRAP_ERR_IDT 2
2617	/** Descriptor table indicator - If set LDT, if clear GDT. */
2618	#define X86_TRAP_ERR_TI 4
2619	/** Mask for getting the selector. */
2620	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2621	/** Shift for getting the selector table index (C type index). */
2622	#define X86_TRAP_ERR_SEL_SHIFT 3
2623	/** @} */
2624
2625
2626	/** @name \#PF Trap Error Codes
2627	* @{
2628	*/
2629	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2630	#define X86_TRAP_PF_P RT_BIT(0)
2631	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2632	#define X86_TRAP_PF_RW RT_BIT(1)
2633	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2634	#define X86_TRAP_PF_US RT_BIT(2)
2635	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2636	#define X86_TRAP_PF_RSVD RT_BIT(3)
2637	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2638	#define X86_TRAP_PF_ID RT_BIT(4)
2639	/** @} */
2640
2641	#pragma pack(1)
2642	/**
2643	* 32-bit IDTR/GDTR.
2644	*/
2645	typedef struct X86XDTR32
2646	{
2647	/** Size of the descriptor table. */
2648	uint16_t cb;
2649	/** Address of the descriptor table. */
2650	uint32_t uAddr;
2651	} X86XDTR32, *PX86XDTR32;
2652	#pragma pack()
2653
2654	#pragma pack(1)
2655	/**
2656	* 64-bit IDTR/GDTR.
2657	*/
2658	typedef struct X86XDTR64
2659	{
2660	/** Size of the descriptor table. */
2661	uint16_t cb;
2662	/** Address of the descriptor table. */
2663	uint64_t uAddr;
2664	} X86XDTR64, *PX86XDTR64;
2665	#pragma pack()
2666
2667	/** @} */
2668
2669	#endif
2670

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source: vbox/trunk/include/VBox/x86.h@ 21320

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