x86.h@ 23746

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions (VMM,++).
3	*
4	* x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*
27	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
28	* Clara, CA 95054 USA or visit http://www.sun.com if you need
29	* additional information or have any questions.
30	*/
31
32	#ifndef ___VBox_x86_h
33	#define ___VBox_x86_h
34
35	#include <VBox/types.h>
36	#include <iprt/assert.h>
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_x86 x86 Types and Definitions
45	* @{
46	*/
47
48	/**
49	* EFLAGS Bits.
50	*/
51	typedef struct X86EFLAGSBITS
52	{
53	/** Bit 0 - CF - Carry flag - Status flag. */
54	unsigned u1CF : 1;
55	/** Bit 1 - 1 - Reserved flag. */
56	unsigned u1Reserved0 : 1;
57	/** Bit 2 - PF - Parity flag - Status flag. */
58	unsigned u1PF : 1;
59	/** Bit 3 - 0 - Reserved flag. */
60	unsigned u1Reserved1 : 1;
61	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
62	unsigned u1AF : 1;
63	/** Bit 5 - 0 - Reserved flag. */
64	unsigned u1Reserved2 : 1;
65	/** Bit 6 - ZF - Zero flag - Status flag. */
66	unsigned u1ZF : 1;
67	/** Bit 7 - SF - Signed flag - Status flag. */
68	unsigned u1SF : 1;
69	/** Bit 8 - TF - Trap flag - System flag. */
70	unsigned u1TF : 1;
71	/** Bit 9 - IF - Interrupt flag - System flag. */
72	unsigned u1IF : 1;
73	/** Bit 10 - DF - Direction flag - Control flag. */
74	unsigned u1DF : 1;
75	/** Bit 11 - OF - Overflow flag - Status flag. */
76	unsigned u1OF : 1;
77	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
78	unsigned u2IOPL : 2;
79	/** Bit 14 - NT - Nested task flag - System flag. */
80	unsigned u1NT : 1;
81	/** Bit 15 - 0 - Reserved flag. */
82	unsigned u1Reserved3 : 1;
83	/** Bit 16 - RF - Resume flag - System flag. */
84	unsigned u1RF : 1;
85	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
86	unsigned u1VM : 1;
87	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
88	unsigned u1AC : 1;
89	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
90	unsigned u1VIF : 1;
91	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
92	unsigned u1VIP : 1;
93	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
94	unsigned u1ID : 1;
95	/** Bit 22-31 - 0 - Reserved flag. */
96	unsigned u10Reserved4 : 10;
97	} X86EFLAGSBITS;
98	/** Pointer to EFLAGS bits. */
99	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
100	/** Pointer to const EFLAGS bits. */
101	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
102
103	/**
104	* EFLAGS.
105	*/
106	typedef union X86EFLAGS
107	{
108	/** The plain unsigned view. */
109	uint32_t u;
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	} X86EFLAGS;
121	/** Pointer to EFLAGS. */
122	typedef X86EFLAGS *PX86EFLAGS;
123	/** Pointer to const EFLAGS. */
124	typedef const X86EFLAGS *PCX86EFLAGS;
125
126	/**
127	* RFLAGS (32 upper bits are reserved).
128	*/
129	typedef union X86RFLAGS
130	{
131	/** The plain unsigned view. */
132	uint64_t u;
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	} X86RFLAGS;
146	/** Pointer to RFLAGS. */
147	typedef X86RFLAGS *PX86RFLAGS;
148	/** Pointer to const RFLAGS. */
149	typedef const X86RFLAGS *PCX86RFLAGS;
150
151
152	/** @name EFLAGS
153	* @{
154	*/
155	/** Bit 0 - CF - Carry flag - Status flag. */
156	#define X86_EFL_CF RT_BIT(0)
157	/** Bit 2 - PF - Parity flag - Status flag. */
158	#define X86_EFL_PF RT_BIT(2)
159	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
160	#define X86_EFL_AF RT_BIT(4)
161	/** Bit 6 - ZF - Zero flag - Status flag. */
162	#define X86_EFL_ZF RT_BIT(6)
163	/** Bit 7 - SF - Signed flag - Status flag. */
164	#define X86_EFL_SF RT_BIT(7)
165	/** Bit 8 - TF - Trap flag - System flag. */
166	#define X86_EFL_TF RT_BIT(8)
167	/** Bit 9 - IF - Interrupt flag - System flag. */
168	#define X86_EFL_IF RT_BIT(9)
169	/** Bit 10 - DF - Direction flag - Control flag. */
170	#define X86_EFL_DF RT_BIT(10)
171	/** Bit 11 - OF - Overflow flag - Status flag. */
172	#define X86_EFL_OF RT_BIT(11)
173	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
174	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
175	/** Bit 14 - NT - Nested task flag - System flag. */
176	#define X86_EFL_NT RT_BIT(14)
177	/** Bit 16 - RF - Resume flag - System flag. */
178	#define X86_EFL_RF RT_BIT(16)
179	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
180	#define X86_EFL_VM RT_BIT(17)
181	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
182	#define X86_EFL_AC RT_BIT(18)
183	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
184	#define X86_EFL_VIF RT_BIT(19)
185	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
186	#define X86_EFL_VIP RT_BIT(20)
187	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
188	#define X86_EFL_ID RT_BIT(21)
189	/** IOPL shift. */
190	#define X86_EFL_IOPL_SHIFT 12
191	/** The the IOPL level from the flags. */
192	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
193	/** Bits restored by popf */
194	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u1Reserved1 : 1;
207	/** Bit 2 - DS Area 64-bit layout. */
208	unsigned u1DTE64 : 1;
209	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
210	unsigned u1Monitor : 1;
211	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
212	unsigned u1CPLDS : 1;
213	/** Bit 5 - VMX - Virtual Machine Technology. */
214	unsigned u1VMX : 1;
215	/** Bit 6 - SMX: Safer Mode Extensions. */
216	unsigned u1SMX : 1;
217	/** Bit 7 - EST - Enh. SpeedStep Tech. */
218	unsigned u1EST : 1;
219	/** Bit 8 - TM2 - Terminal Monitor 2. */
220	unsigned u1TM2 : 1;
221	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
222	unsigned u1SSSE3 : 1;
223	/** Bit 10 - CNTX-ID - L1 Context ID. */
224	unsigned u1CNTXID : 1;
225	/** Reserved. */
226	unsigned u2Reserved2 : 2;
227	/** Bit 13 - CX16 - CMPXCHG16B. */
228	unsigned u1CX16 : 1;
229	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
230	unsigned u1TPRUpdate : 1;
231	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
232	unsigned u1PDCM : 1;
233	/** Reserved. */
234	unsigned u2Reserved3 : 2;
235	/** Bit 18 - Direct Cache Access. */
236	unsigned u1DCA : 1;
237	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
238	unsigned u1SSE4_1 : 1;
239	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
240	unsigned u1SSE4_2 : 1;
241	/** Bit 21 - x2APIC. */
242	unsigned u1x2APIC : 1;
243	/** Bit 22 - MOVBE - Supports MOVBE. */
244	unsigned u1MOVBE : 1;
245	/** Bit 23 - POPCNT - Supports POPCNT. */
246	unsigned u1POPCNT : 1;
247	/** Reserved. */
248	unsigned u2Reserved4 : 2;
249	/** Bit 26 - XSAVE - Supports XSAVE. */
250	unsigned u1XSAVE : 1;
251	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
252	unsigned u1OSXSAVE : 1;
253	/** Reserved. */
254	unsigned u4Reserved5 : 4;
255	} X86CPUIDFEATECX;
256	/** Pointer to CPUID Feature Information - ECX. */
257	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
258	/** Pointer to const CPUID Feature Information - ECX. */
259	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
260
261
262	/** CPUID Feature Information - EDX.
263	* CPUID query with EAX=1.
264	*/
265	typedef struct X86CPUIDFEATEDX
266	{
267	/** Bit 0 - FPU - x87 FPU on Chip. */
268	unsigned u1FPU : 1;
269	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
270	unsigned u1VME : 1;
271	/** Bit 2 - DE - Debugging extensions. */
272	unsigned u1DE : 1;
273	/** Bit 3 - PSE - Page Size Extension. */
274	unsigned u1PSE : 1;
275	/** Bit 4 - TSC - Time Stamp Counter. */
276	unsigned u1TSC : 1;
277	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
278	unsigned u1MSR : 1;
279	/** Bit 6 - PAE - Physical Address Extension. */
280	unsigned u1PAE : 1;
281	/** Bit 7 - MCE - Machine Check Exception. */
282	unsigned u1MCE : 1;
283	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
284	unsigned u1CX8 : 1;
285	/** Bit 9 - APIC - APIC On-Chip. */
286	unsigned u1APIC : 1;
287	/** Bit 10 - Reserved. */
288	unsigned u1Reserved1 : 1;
289	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
290	unsigned u1SEP : 1;
291	/** Bit 12 - MTRR - Memory Type Range Registers. */
292	unsigned u1MTRR : 1;
293	/** Bit 13 - PGE - PTE Global Bit. */
294	unsigned u1PGE : 1;
295	/** Bit 14 - MCA - Machine Check Architecture. */
296	unsigned u1MCA : 1;
297	/** Bit 15 - CMOV - Conditional Move Instructions. */
298	unsigned u1CMOV : 1;
299	/** Bit 16 - PAT - Page Attribute Table. */
300	unsigned u1PAT : 1;
301	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
302	unsigned u1PSE36 : 1;
303	/** Bit 18 - PSN - Processor Serial Number. */
304	unsigned u1PSN : 1;
305	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
306	unsigned u1CLFSH : 1;
307	/** Bit 20 - Reserved. */
308	unsigned u1Reserved2 : 1;
309	/** Bit 21 - DS - Debug Store. */
310	unsigned u1DS : 1;
311	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
312	unsigned u1ACPI : 1;
313	/** Bit 23 - MMX - Intel MMX 'Technology'. */
314	unsigned u1MMX : 1;
315	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
316	unsigned u1FXSR : 1;
317	/** Bit 25 - SSE - SSE Support. */
318	unsigned u1SSE : 1;
319	/** Bit 26 - SSE2 - SSE2 Support. */
320	unsigned u1SSE2 : 1;
321	/** Bit 27 - SS - Self Snoop. */
322	unsigned u1SS : 1;
323	/** Bit 28 - HTT - Hyper-Threading Technology. */
324	unsigned u1HTT : 1;
325	/** Bit 29 - TM - Thermal Monitor. */
326	unsigned u1TM : 1;
327	/** Bit 30 - Reserved - . */
328	unsigned u1Reserved3 : 1;
329	/** Bit 31 - PBE - Pending Break Enabled. */
330	unsigned u1PBE : 1;
331	} X86CPUIDFEATEDX;
332	/** Pointer to CPUID Feature Information - EDX. */
333	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
334	/** Pointer to const CPUID Feature Information - EDX. */
335	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
336
337	/** @name CPUID Vendor information.
338	* CPUID query with EAX=0.
339	* @{
340	*/
341	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
342	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
343	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
344
345	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
346	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
347	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
348	/** @} */
349
350
351	/** @name CPUID Feature information.
352	* CPUID query with EAX=1.
353	* @{
354	*/
355	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
356	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
357	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
358	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
359	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
360	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
361	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
362	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
363	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
364	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
365	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
366	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
367	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
368	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
369	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
370	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
371	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
372	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
373	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
374	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
375	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
376	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
377	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
378	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
379	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
380	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
381	/** ECX Bit 18 - DCA - Direct Cache Access. */
382	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
383	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
384	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
385	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
386	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
387	/** ECX Bit 21 - x2APIC support. */
388	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
389	/** ECX Bit 22 - MOVBE instruction. */
390	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
391	/** ECX Bit 23 - POPCOUNT instruction. */
392	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
393	/** ECX Bit 26 - XSAVE instruction. */
394	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
395	/** ECX Bit 27 - OSXSAVE instruction. */
396	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
397
398
399	/** Bit 0 - FPU - x87 FPU on Chip. */
400	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
401	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
402	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
403	/** Bit 2 - DE - Debugging extensions. */
404	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
405	/** Bit 3 - PSE - Page Size Extension. */
406	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
407	/** Bit 4 - TSC - Time Stamp Counter. */
408	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
409	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
410	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
411	/** Bit 6 - PAE - Physical Address Extension. */
412	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
413	/** Bit 7 - MCE - Machine Check Exception. */
414	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
415	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
416	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
417	/** Bit 9 - APIC - APIC On-Chip. */
418	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
419	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
420	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
421	/** Bit 12 - MTRR - Memory Type Range Registers. */
422	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
423	/** Bit 13 - PGE - PTE Global Bit. */
424	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
425	/** Bit 14 - MCA - Machine Check Architecture. */
426	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
427	/** Bit 15 - CMOV - Conditional Move Instructions. */
428	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
429	/** Bit 16 - PAT - Page Attribute Table. */
430	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
431	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
432	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
433	/** Bit 18 - PSN - Processor Serial Number. */
434	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
435	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
436	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
437	/** Bit 21 - DS - Debug Store. */
438	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
439	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
440	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
441	/** Bit 23 - MMX - Intel MMX Technology. */
442	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
443	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
444	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
445	/** Bit 25 - SSE - SSE Support. */
446	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
447	/** Bit 26 - SSE2 - SSE2 Support. */
448	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
449	/** Bit 27 - SS - Self Snoop. */
450	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
451	/** Bit 28 - HTT - Hyper-Threading Technology. */
452	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
453	/** Bit 29 - TM - Therm. Monitor. */
454	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
455	/** Bit 31 - PBE - Pending Break Enabled. */
456	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
457	/** @} */
458
459
460	/** @name CPUID AMD Feature information.
461	* CPUID query with EAX=0x80000001.
462	* @{
463	*/
464	/** Bit 0 - FPU - x87 FPU on Chip. */
465	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
466	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
467	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
468	/** Bit 2 - DE - Debugging extensions. */
469	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
470	/** Bit 3 - PSE - Page Size Extension. */
471	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
472	/** Bit 4 - TSC - Time Stamp Counter. */
473	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
474	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
475	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
476	/** Bit 6 - PAE - Physical Address Extension. */
477	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
478	/** Bit 7 - MCE - Machine Check Exception. */
479	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
480	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
481	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
482	/** Bit 9 - APIC - APIC On-Chip. */
483	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
484	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
485	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
486	/** Bit 12 - MTRR - Memory Type Range Registers. */
487	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
488	/** Bit 13 - PGE - PTE Global Bit. */
489	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
490	/** Bit 14 - MCA - Machine Check Architecture. */
491	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
492	/** Bit 15 - CMOV - Conditional Move Instructions. */
493	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
494	/** Bit 16 - PAT - Page Attribute Table. */
495	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
496	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
497	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
498	/** Bit 20 - NX - AMD No-Execute Page Protection. */
499	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
500	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
501	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
502	/** Bit 23 - MMX - Intel MMX Technology. */
503	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
504	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
505	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
506	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
507	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
508	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
509	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
510	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
511	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
512	/** Bit 29 - LM - AMD Long Mode. */
513	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
514	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
515	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
516	/** Bit 31 - 3DNOW - AMD 3DNow. */
517	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
518
519	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
520	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
521	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
522	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
523	/** Bit 2 - SVM - AMD VM extensions. */
524	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
525	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
526	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
527	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
528	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
529	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
530	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
531	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
532	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
533	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
534	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
535	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
536	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
537	/** Bit 9 - OSVW - AMD OS visible workaround. */
538	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
539	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
540	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
541	/** Bit 13 - WDT - AMD Watchdog timer support. */
542	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
543
544	/** @} */
545
546
547	/** @name CPUID AMD Feature information.
548	* CPUID query with EAX=0x80000007.
549	* @{
550	*/
551	/** Bit 0 - TS - Temperature Sensor. */
552	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
553	/** Bit 1 - FID - Frequency ID Control. */
554	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
555	/** Bit 2 - VID - Voltage ID Control. */
556	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
557	/** Bit 3 - TTP - THERMTRIP. */
558	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
559	/** Bit 4 - TM - Hardware Thermal Control. */
560	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
561	/** Bit 5 - STC - Software Thermal Control. */
562	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
563	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
564	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
565	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
566	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
567	/** Bit 8 - TSCINVAR - TSC Invariant. */
568	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
569	/** @} */
570
571
572	/** @name CR0
573	* @{ */
574	/** Bit 0 - PE - Protection Enabled */
575	#define X86_CR0_PE RT_BIT(0)
576	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
577	/** Bit 1 - MP - Monitor Coprocessor */
578	#define X86_CR0_MP RT_BIT(1)
579	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
580	/** Bit 2 - EM - Emulation. */
581	#define X86_CR0_EM RT_BIT(2)
582	#define X86_CR0_EMULATE_FPU RT_BIT(2)
583	/** Bit 3 - TS - Task Switch. */
584	#define X86_CR0_TS RT_BIT(3)
585	#define X86_CR0_TASK_SWITCH RT_BIT(3)
586	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
587	#define X86_CR0_ET RT_BIT(4)
588	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
589	/** Bit 5 - NE - Numeric error. */
590	#define X86_CR0_NE RT_BIT(5)
591	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
592	/** Bit 16 - WP - Write Protect. */
593	#define X86_CR0_WP RT_BIT(16)
594	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
595	/** Bit 18 - AM - Alignment Mask. */
596	#define X86_CR0_AM RT_BIT(18)
597	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
598	/** Bit 29 - NW - Not Write-though. */
599	#define X86_CR0_NW RT_BIT(29)
600	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
601	/** Bit 30 - WP - Cache Disable. */
602	#define X86_CR0_CD RT_BIT(30)
603	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
604	/** Bit 31 - PG - Paging. */
605	#define X86_CR0_PG RT_BIT(31)
606	#define X86_CR0_PAGING RT_BIT(31)
607	/** @} */
608
609
610	/** @name CR3
611	* @{ */
612	/** Bit 3 - PWT - Page-level Writes Transparent. */
613	#define X86_CR3_PWT RT_BIT(3)
614	/** Bit 4 - PCD - Page-level Cache Disable. */
615	#define X86_CR3_PCD RT_BIT(4)
616	/** Bits 12-31 - - Page directory page number. */
617	#define X86_CR3_PAGE_MASK (0xfffff000)
618	/** Bits 5-31 - - PAE Page directory page number. */
619	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
620	/** Bits 12-51 - - AMD64 Page directory page number. */
621	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
622	/** @} */
623
624
625	/** @name CR4
626	* @{ */
627	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
628	#define X86_CR4_VME RT_BIT(0)
629	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
630	#define X86_CR4_PVI RT_BIT(1)
631	/** Bit 2 - TSD - Time Stamp Disable. */
632	#define X86_CR4_TSD RT_BIT(2)
633	/** Bit 3 - DE - Debugging Extensions. */
634	#define X86_CR4_DE RT_BIT(3)
635	/** Bit 4 - PSE - Page Size Extension. */
636	#define X86_CR4_PSE RT_BIT(4)
637	/** Bit 5 - PAE - Physical Address Extension. */
638	#define X86_CR4_PAE RT_BIT(5)
639	/** Bit 6 - MCE - Machine-Check Enable. */
640	#define X86_CR4_MCE RT_BIT(6)
641	/** Bit 7 - PGE - Page Global Enable. */
642	#define X86_CR4_PGE RT_BIT(7)
643	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
644	#define X86_CR4_PCE RT_BIT(8)
645	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
646	#define X86_CR4_OSFSXR RT_BIT(9)
647	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
648	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
649	/** Bit 13 - VMXE - VMX mode is enabled. */
650	#define X86_CR4_VMXE RT_BIT(13)
651	/** @} */
652
653
654	/** @name DR6
655	* @{ */
656	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
657	#define X86_DR6_B0 RT_BIT(0)
658	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
659	#define X86_DR6_B1 RT_BIT(1)
660	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
661	#define X86_DR6_B2 RT_BIT(2)
662	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
663	#define X86_DR6_B3 RT_BIT(3)
664	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
665	#define X86_DR6_BD RT_BIT(13)
666	/** Bit 14 - BS - Single step */
667	#define X86_DR6_BS RT_BIT(14)
668	/** Bit 15 - BT - Task switch. (TSS T bit.) */
669	#define X86_DR6_BT RT_BIT(15)
670	/** Value of DR6 after powerup/reset. */
671	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
672	/** @} */
673
674
675	/** @name DR7
676	* @{ */
677	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
678	#define X86_DR7_L0 RT_BIT(0)
679	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
680	#define X86_DR7_G0 RT_BIT(1)
681	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
682	#define X86_DR7_L1 RT_BIT(2)
683	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
684	#define X86_DR7_G1 RT_BIT(3)
685	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
686	#define X86_DR7_L2 RT_BIT(4)
687	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
688	#define X86_DR7_G2 RT_BIT(5)
689	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
690	#define X86_DR7_L3 RT_BIT(6)
691	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
692	#define X86_DR7_G3 RT_BIT(7)
693	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
694	#define X86_DR7_LE RT_BIT(8)
695	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
696	#define X86_DR7_GE RT_BIT(9)
697
698	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
699	* any DR register is accessed. */
700	#define X86_DR7_GD RT_BIT(13)
701	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
702	#define X86_DR7_RW0_MASK (3 << 16)
703	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
704	#define X86_DR7_LEN0_MASK (3 << 18)
705	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
706	#define X86_DR7_RW1_MASK (3 << 20)
707	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
708	#define X86_DR7_LEN1_MASK (3 << 22)
709	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
710	#define X86_DR7_RW2_MASK (3 << 24)
711	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
712	#define X86_DR7_LEN2_MASK (3 << 26)
713	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
714	#define X86_DR7_RW3_MASK (3 << 28)
715	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
716	#define X86_DR7_LEN3_MASK (3 << 30)
717
718	/** Bits which must be 1s. */
719	#define X86_DR7_MB1_MASK (RT_BIT(10))
720
721	/** Calcs the L bit of Nth breakpoint.
722	* @param iBp The breakpoint number [0..3].
723	*/
724	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
725
726	/** Calcs the G bit of Nth breakpoint.
727	* @param iBp The breakpoint number [0..3].
728	*/
729	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
730
731	/** @name Read/Write values.
732	* @{ */
733	/** Break on instruction fetch only. */
734	#define X86_DR7_RW_EO 0U
735	/** Break on write only. */
736	#define X86_DR7_RW_WO 1U
737	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
738	#define X86_DR7_RW_IO 2U
739	/** Break on read or write (but not instruction fetches). */
740	#define X86_DR7_RW_RW 3U
741	/** @} */
742
743	/** Shifts a X86_DR7_RW_* value to its right place.
744	* @param iBp The breakpoint number [0..3].
745	* @param fRw One of the X86_DR7_RW_* value.
746	*/
747	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
748
749	/** @name Length values.
750	* @{ */
751	#define X86_DR7_LEN_BYTE 0U
752	#define X86_DR7_LEN_WORD 1U
753	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
754	#define X86_DR7_LEN_DWORD 3U
755	/** @} */
756
757	/** Shifts a X86_DR7_LEN_* value to its right place.
758	* @param iBp The breakpoint number [0..3].
759	* @param cb One of the X86_DR7_LEN_* values.
760	*/
761	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
762
763	/** Fetch the breakpoint length bits from the DR7 value.
764	* @param uDR7 DR7 value
765	* @param iBp The breakpoint number [0..3].
766	*/
767	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
768
769	/** Mask used to check if any breakpoints are enabled. */
770	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
771
772	/** Mask used to check if any io breakpoints are set. */
773	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
774
775	/** Value of DR7 after powerup/reset. */
776	#define X86_DR7_INIT_VAL 0x400
777	/** @} */
778
779
780	/** @name Machine Specific Registers
781	* @{
782	*/
783
784	/** Time Stamp Counter. */
785	#define MSR_IA32_TSC 0x10
786
787	#define MSR_IA32_PLATFORM_ID 0x17
788
789	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
790	#define MSR_IA32_APICBASE 0x1b
791	#endif
792
793	/** CPU Feature control. */
794	#define MSR_IA32_FEATURE_CONTROL 0x3A
795	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
796	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
797
798	/** BIOS update trigger (microcode update). */
799	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
800
801	/** BIOS update signature (microcode). */
802	#define MSR_IA32_BIOS_SIGN_ID 0x8B
803
804	/** MTRR Capabilities. */
805	#define MSR_IA32_MTRR_CAP 0xFE
806
807
808	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
809	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
810	* R0 SS == CS + 8
811	* R3 CS == CS + 16
812	* R3 SS == CS + 24
813	*/
814	#define MSR_IA32_SYSENTER_CS 0x174
815	/** SYSENTER_ESP - the R0 ESP. */
816	#define MSR_IA32_SYSENTER_ESP 0x175
817	/** SYSENTER_EIP - the R0 EIP. */
818	#define MSR_IA32_SYSENTER_EIP 0x176
819	#endif
820
821	/** Machine Check Global Capabilities Register. */
822	#define MSR_IA32_MCP_CAP 0x179
823	/** Machine Check Global Status Register. */
824	#define MSR_IA32_MCP_STATUS 0x17A
825	/** Machine Check Global Control Register. */
826	#define MSR_IA32_MCP_CTRL 0x17B
827
828	/* Page Attribute Table. */
829	#define MSR_IA32_CR_PAT 0x277
830
831	/** Performance counter MSRs. (Intel only) */
832	#define MSR_IA32_PERFEVTSEL0 0x186
833	#define MSR_IA32_PERFEVTSEL1 0x187
834	#define MSR_IA32_PERF_STATUS 0x198
835	#define MSR_IA32_PERF_CTL 0x199
836
837	/** MTRR Default Range. */
838	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
839
840	#define MSR_IA32_MC0_CTL 0x400
841	#define MSR_IA32_MC0_STATUS 0x401
842
843	/** Basic VMX information. */
844	#define MSR_IA32_VMX_BASIC_INFO 0x480
845	/** Allowed settings for pin-based VM execution controls */
846	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
847	/** Allowed settings for proc-based VM execution controls */
848	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
849	/** Allowed settings for the VMX exit controls. */
850	#define MSR_IA32_VMX_EXIT_CTLS 0x483
851	/** Allowed settings for the VMX entry controls. */
852	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
853	/** Misc VMX info. */
854	#define MSR_IA32_VMX_MISC 0x485
855	/** Fixed cleared bits in CR0. */
856	#define MSR_IA32_VMX_CR0_FIXED0 0x486
857	/** Fixed set bits in CR0. */
858	#define MSR_IA32_VMX_CR0_FIXED1 0x487
859	/** Fixed cleared bits in CR4. */
860	#define MSR_IA32_VMX_CR4_FIXED0 0x488
861	/** Fixed set bits in CR4. */
862	#define MSR_IA32_VMX_CR4_FIXED1 0x489
863	/** Information for enumerating fields in the VMCS. */
864	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
865	/** Allowed settings for secondary proc-based VM execution controls */
866	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
867	/** EPT capabilities. */
868	#define MSR_IA32_VMX_EPT_CAPS 0x48C
869	/** X2APIC MSR ranges. */
870	#define MSR_IA32_APIC_START 0x800
871	#define MSR_IA32_APIC_END 0x900
872
873	/** K6 EFER - Extended Feature Enable Register. */
874	#define MSR_K6_EFER 0xc0000080
875	/** @todo document EFER */
876	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
877	#define MSR_K6_EFER_SCE RT_BIT(0)
878	/** Bit 8 - LME - Long mode enabled. (R/W) */
879	#define MSR_K6_EFER_LME RT_BIT(8)
880	/** Bit 10 - LMA - Long mode active. (R) */
881	#define MSR_K6_EFER_LMA RT_BIT(10)
882	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
883	#define MSR_K6_EFER_NXE RT_BIT(11)
884	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
885	#define MSR_K6_EFER_SVME RT_BIT(12)
886	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
887	#define MSR_K6_EFER_LMSLE RT_BIT(13)
888	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
889	#define MSR_K6_EFER_FFXSR RT_BIT(14)
890	/** K6 STAR - SYSCALL/RET targets. */
891	#define MSR_K6_STAR 0xc0000081
892	/** Shift value for getting the SYSRET CS and SS value. */
893	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
894	/** Shift value for getting the SYSCALL CS and SS value. */
895	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
896	/** Selector mask for use after shifting. */
897	#define MSR_K6_STAR_SEL_MASK 0xffff
898	/** The mask which give the SYSCALL EIP. */
899	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
900	/** K6 WHCR - Write Handling Control Register. */
901	#define MSR_K6_WHCR 0xc0000082
902	/** K6 UWCCR - UC/WC Cacheability Control Register. */
903	#define MSR_K6_UWCCR 0xc0000085
904	/** K6 PSOR - Processor State Observability Register. */
905	#define MSR_K6_PSOR 0xc0000087
906	/** K6 PFIR - Page Flush/Invalidate Register. */
907	#define MSR_K6_PFIR 0xc0000088
908
909	/** Performance counter MSRs. (AMD only) */
910	#define MSR_K7_EVNTSEL0 0xc0010000
911	#define MSR_K7_EVNTSEL1 0xc0010001
912	#define MSR_K7_EVNTSEL2 0xc0010002
913	#define MSR_K7_EVNTSEL3 0xc0010003
914	#define MSR_K7_PERFCTR0 0xc0010004
915	#define MSR_K7_PERFCTR1 0xc0010005
916	#define MSR_K7_PERFCTR2 0xc0010006
917	#define MSR_K7_PERFCTR3 0xc0010007
918
919	#define MSR_K8_HWCR 0xc0010015
920
921	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
922	#define MSR_K8_LSTAR 0xc0000082
923	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
924	#define MSR_K8_CSTAR 0xc0000083
925	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
926	#define MSR_K8_SF_MASK 0xc0000084
927	/** K8 FS.base - The 64-bit base FS register. */
928	#define MSR_K8_FS_BASE 0xc0000100
929	/** K8 GS.base - The 64-bit base GS register. */
930	#define MSR_K8_GS_BASE 0xc0000101
931	/** K8 KernelGSbase - Used with SWAPGS. */
932	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
933	#define MSR_K8_TSC_AUX 0xc0000103
934	#define MSR_K8_SYSCFG 0xc0010010
935	#define MSR_K8_HWCR 0xc0010015
936	#define MSR_K8_IORRBASE0 0xc0010016
937	#define MSR_K8_IORRMASK0 0xc0010017
938	#define MSR_K8_IORRBASE1 0xc0010018
939	#define MSR_K8_IORRMASK1 0xc0010019
940	#define MSR_K8_TOP_MEM1 0xc001001a
941	#define MSR_K8_TOP_MEM2 0xc001001d
942	#define MSR_K8_VM_CR 0xc0010114
943	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
944
945	#define MSR_K8_IGNNE 0xc0010115
946	#define MSR_K8_SMM_CTL 0xc0010116
947	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
948	* host state during world switch.
949	*/
950	#define MSR_K8_VM_HSAVE_PA 0xc0010117
951
952	/** @} */
953
954
955	/** @name Page Table / Directory / Directory Pointers / L4.
956	* @{
957	*/
958
959	/** Page table/directory entry as an unsigned integer. */
960	typedef uint32_t X86PGUINT;
961	/** Pointer to a page table/directory table entry as an unsigned integer. */
962	typedef X86PGUINT *PX86PGUINT;
963	/** Pointer to an const page table/directory table entry as an unsigned integer. */
964	typedef X86PGUINT const *PCX86PGUINT;
965
966	/** Number of entries in a 32-bit PT/PD. */
967	#define X86_PG_ENTRIES 1024
968
969
970	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
971	typedef uint64_t X86PGPAEUINT;
972	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
973	typedef X86PGPAEUINT *PX86PGPAEUINT;
974	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
975	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
976
977	/** Number of entries in a PAE PT/PD. */
978	#define X86_PG_PAE_ENTRIES 512
979	/** Number of entries in a PAE PDPT. */
980	#define X86_PG_PAE_PDPE_ENTRIES 4
981
982	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
983	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
984	/** Number of entries in an AMD64 PDPT.
985	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
986	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
987
988	/** The size of a 4KB page. */
989	#define X86_PAGE_4K_SIZE _4K
990	/** The page shift of a 4KB page. */
991	#define X86_PAGE_4K_SHIFT 12
992	/** The 4KB page offset mask. */
993	#define X86_PAGE_4K_OFFSET_MASK 0xfff
994	/** The 4KB page base mask for virtual addresses. */
995	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
996	/** The 4KB page base mask for virtual addresses - 32bit version. */
997	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
998
999	/** The size of a 2MB page. */
1000	#define X86_PAGE_2M_SIZE _2M
1001	/** The page shift of a 2MB page. */
1002	#define X86_PAGE_2M_SHIFT 21
1003	/** The 2MB page offset mask. */
1004	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1005	/** The 2MB page base mask for virtual addresses. */
1006	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1007	/** The 2MB page base mask for virtual addresses - 32bit version. */
1008	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1009
1010	/** The size of a 4MB page. */
1011	#define X86_PAGE_4M_SIZE _4M
1012	/** The page shift of a 4MB page. */
1013	#define X86_PAGE_4M_SHIFT 22
1014	/** The 4MB page offset mask. */
1015	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1016	/** The 4MB page base mask for virtual addresses. */
1017	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1018	/** The 4MB page base mask for virtual addresses - 32bit version. */
1019	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1020
1021
1022
1023	/** @name Page Table Entry
1024	* @{
1025	*/
1026	/** Bit 0 - P - Present bit. */
1027	#define X86_PTE_BIT_P 0
1028	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1029	#define X86_PTE_BIT_RW 1
1030	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1031	#define X86_PTE_BIT_US 2
1032	/** Bit 3 - PWT - Page level write thru bit. */
1033	#define X86_PTE_BIT_PWT 3
1034	/** Bit 4 - PCD - Page level cache disable bit. */
1035	#define X86_PTE_BIT_PCD 4
1036	/** Bit 5 - A - Access bit. */
1037	#define X86_PTE_BIT_A 5
1038	/** Bit 6 - D - Dirty bit. */
1039	#define X86_PTE_BIT_D 6
1040	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1041	#define X86_PTE_BIT_PAT 7
1042	/** Bit 8 - G - Global flag. */
1043	#define X86_PTE_BIT_G 8
1044
1045	/** Bit 0 - P - Present bit mask. */
1046	#define X86_PTE_P RT_BIT(0)
1047	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1048	#define X86_PTE_RW RT_BIT(1)
1049	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1050	#define X86_PTE_US RT_BIT(2)
1051	/** Bit 3 - PWT - Page level write thru bit mask. */
1052	#define X86_PTE_PWT RT_BIT(3)
1053	/** Bit 4 - PCD - Page level cache disable bit mask. */
1054	#define X86_PTE_PCD RT_BIT(4)
1055	/** Bit 5 - A - Access bit mask. */
1056	#define X86_PTE_A RT_BIT(5)
1057	/** Bit 6 - D - Dirty bit mask. */
1058	#define X86_PTE_D RT_BIT(6)
1059	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1060	#define X86_PTE_PAT RT_BIT(7)
1061	/** Bit 8 - G - Global bit mask. */
1062	#define X86_PTE_G RT_BIT(8)
1063
1064	/** Bits 9-11 - - Available for use to system software. */
1065	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1066	/** Bits 12-31 - - Physical Page number of the next level. */
1067	#define X86_PTE_PG_MASK ( 0xfffff000 )
1068
1069	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1070	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1071	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1072	/** @todo Get rid of the above hack; makes code unreadable. */
1073	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1074	#else
1075	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1076	#endif
1077	/** Bits 63 - NX - PAE - No execution flag. */
1078	#define X86_PTE_PAE_NX RT_BIT_64(63)
1079
1080	/**
1081	* Page table entry.
1082	*/
1083	typedef struct X86PTEBITS
1084	{
1085	/** Flags whether(=1) or not the page is present. */
1086	unsigned u1Present : 1;
1087	/** Read(=0) / Write(=1) flag. */
1088	unsigned u1Write : 1;
1089	/** User(=1) / Supervisor (=0) flag. */
1090	unsigned u1User : 1;
1091	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1092	unsigned u1WriteThru : 1;
1093	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1094	unsigned u1CacheDisable : 1;
1095	/** Accessed flag.
1096	* Indicates that the page have been read or written to. */
1097	unsigned u1Accessed : 1;
1098	/** Dirty flag.
1099	* Indicates that the page have been written to. */
1100	unsigned u1Dirty : 1;
1101	/** Reserved / If PAT enabled, bit 2 of the index. */
1102	unsigned u1PAT : 1;
1103	/** Global flag. (Ignored in all but final level.) */
1104	unsigned u1Global : 1;
1105	/** Available for use to system software. */
1106	unsigned u3Available : 3;
1107	/** Physical Page number of the next level. */
1108	unsigned u20PageNo : 20;
1109	} X86PTEBITS;
1110	/** Pointer to a page table entry. */
1111	typedef X86PTEBITS *PX86PTEBITS;
1112	/** Pointer to a const page table entry. */
1113	typedef const X86PTEBITS *PCX86PTEBITS;
1114
1115	/**
1116	* Page table entry.
1117	*/
1118	typedef union X86PTE
1119	{
1120	/** Unsigned integer view */
1121	X86PGUINT u;
1122	/** Bit field view. */
1123	X86PTEBITS n;
1124	/** 32-bit view. */
1125	uint32_t au32[1];
1126	/** 16-bit view. */
1127	uint16_t au16[2];
1128	/** 8-bit view. */
1129	uint8_t au8[4];
1130	} X86PTE;
1131	/** Pointer to a page table entry. */
1132	typedef X86PTE *PX86PTE;
1133	/** Pointer to a const page table entry. */
1134	typedef const X86PTE *PCX86PTE;
1135
1136
1137	/**
1138	* PAE page table entry.
1139	*/
1140	typedef struct X86PTEPAEBITS
1141	{
1142	/** Flags whether(=1) or not the page is present. */
1143	uint32_t u1Present : 1;
1144	/** Read(=0) / Write(=1) flag. */
1145	uint32_t u1Write : 1;
1146	/** User(=1) / Supervisor(=0) flag. */
1147	uint32_t u1User : 1;
1148	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1149	uint32_t u1WriteThru : 1;
1150	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1151	uint32_t u1CacheDisable : 1;
1152	/** Accessed flag.
1153	* Indicates that the page have been read or written to. */
1154	uint32_t u1Accessed : 1;
1155	/** Dirty flag.
1156	* Indicates that the page have been written to. */
1157	uint32_t u1Dirty : 1;
1158	/** Reserved / If PAT enabled, bit 2 of the index. */
1159	uint32_t u1PAT : 1;
1160	/** Global flag. (Ignored in all but final level.) */
1161	uint32_t u1Global : 1;
1162	/** Available for use to system software. */
1163	uint32_t u3Available : 3;
1164	/** Physical Page number of the next level - Low Part. Don't use this. */
1165	uint32_t u20PageNoLow : 20;
1166	/** Physical Page number of the next level - High Part. Don't use this. */
1167	uint32_t u20PageNoHigh : 20;
1168	/** MBZ bits */
1169	uint32_t u11Reserved : 11;
1170	/** No Execute flag. */
1171	uint32_t u1NoExecute : 1;
1172	} X86PTEPAEBITS;
1173	/** Pointer to a page table entry. */
1174	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1175	/** Pointer to a page table entry. */
1176	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1177
1178	/**
1179	* PAE Page table entry.
1180	*/
1181	typedef union X86PTEPAE
1182	{
1183	/** Unsigned integer view */
1184	X86PGPAEUINT u;
1185	/** Bit field view. */
1186	X86PTEPAEBITS n;
1187	/** 32-bit view. */
1188	uint32_t au32[2];
1189	/** 16-bit view. */
1190	uint16_t au16[4];
1191	/** 8-bit view. */
1192	uint8_t au8[8];
1193	} X86PTEPAE;
1194	/** Pointer to a PAE page table entry. */
1195	typedef X86PTEPAE *PX86PTEPAE;
1196	/** Pointer to a const PAE page table entry. */
1197	typedef const X86PTEPAE *PCX86PTEPAE;
1198	/** @} */
1199
1200	/**
1201	* Page table.
1202	*/
1203	typedef struct X86PT
1204	{
1205	/** PTE Array. */
1206	X86PTE a[X86_PG_ENTRIES];
1207	} X86PT;
1208	/** Pointer to a page table. */
1209	typedef X86PT *PX86PT;
1210	/** Pointer to a const page table. */
1211	typedef const X86PT *PCX86PT;
1212
1213	/** The page shift to get the PT index. */
1214	#define X86_PT_SHIFT 12
1215	/** The PT index mask (apply to a shifted page address). */
1216	#define X86_PT_MASK 0x3ff
1217
1218
1219	/**
1220	* Page directory.
1221	*/
1222	typedef struct X86PTPAE
1223	{
1224	/** PTE Array. */
1225	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1226	} X86PTPAE;
1227	/** Pointer to a page table. */
1228	typedef X86PTPAE *PX86PTPAE;
1229	/** Pointer to a const page table. */
1230	typedef const X86PTPAE *PCX86PTPAE;
1231
1232	/** The page shift to get the PA PTE index. */
1233	#define X86_PT_PAE_SHIFT 12
1234	/** The PAE PT index mask (apply to a shifted page address). */
1235	#define X86_PT_PAE_MASK 0x1ff
1236
1237
1238	/** @name 4KB Page Directory Entry
1239	* @{
1240	*/
1241	/** Bit 0 - P - Present bit. */
1242	#define X86_PDE_P RT_BIT(0)
1243	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1244	#define X86_PDE_RW RT_BIT(1)
1245	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1246	#define X86_PDE_US RT_BIT(2)
1247	/** Bit 3 - PWT - Page level write thru bit. */
1248	#define X86_PDE_PWT RT_BIT(3)
1249	/** Bit 4 - PCD - Page level cache disable bit. */
1250	#define X86_PDE_PCD RT_BIT(4)
1251	/** Bit 5 - A - Access bit. */
1252	#define X86_PDE_A RT_BIT(5)
1253	/** Bit 7 - PS - Page size attribute.
1254	* Clear mean 4KB pages, set means large pages (2/4MB). */
1255	#define X86_PDE_PS RT_BIT(7)
1256	/** Bits 9-11 - - Available for use to system software. */
1257	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1258	/** Bits 12-31 - - Physical Page number of the next level. */
1259	#define X86_PDE_PG_MASK ( 0xfffff000 )
1260
1261	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1262	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1263	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1264	* we partly or that part into shadow page table entries. Will be corrected
1265	* soon.
1266	*/
1267	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1268	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1269	#else
1270	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1271	#endif
1272	/** Bits 63 - NX - PAE - No execution flag. */
1273	#define X86_PDE_PAE_NX RT_BIT_64(63)
1274
1275	/**
1276	* Page directory entry.
1277	*/
1278	typedef struct X86PDEBITS
1279	{
1280	/** Flags whether(=1) or not the page is present. */
1281	unsigned u1Present : 1;
1282	/** Read(=0) / Write(=1) flag. */
1283	unsigned u1Write : 1;
1284	/** User(=1) / Supervisor (=0) flag. */
1285	unsigned u1User : 1;
1286	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1287	unsigned u1WriteThru : 1;
1288	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1289	unsigned u1CacheDisable : 1;
1290	/** Accessed flag.
1291	* Indicates that the page have been read or written to. */
1292	unsigned u1Accessed : 1;
1293	/** Reserved / Ignored (dirty bit). */
1294	unsigned u1Reserved0 : 1;
1295	/** Size bit if PSE is enabled - in any event it's 0. */
1296	unsigned u1Size : 1;
1297	/** Reserved / Ignored (global bit). */
1298	unsigned u1Reserved1 : 1;
1299	/** Available for use to system software. */
1300	unsigned u3Available : 3;
1301	/** Physical Page number of the next level. */
1302	unsigned u20PageNo : 20;
1303	} X86PDEBITS;
1304	/** Pointer to a page directory entry. */
1305	typedef X86PDEBITS *PX86PDEBITS;
1306	/** Pointer to a const page directory entry. */
1307	typedef const X86PDEBITS *PCX86PDEBITS;
1308
1309
1310	/**
1311	* PAE page directory entry.
1312	*/
1313	typedef struct X86PDEPAEBITS
1314	{
1315	/** Flags whether(=1) or not the page is present. */
1316	uint32_t u1Present : 1;
1317	/** Read(=0) / Write(=1) flag. */
1318	uint32_t u1Write : 1;
1319	/** User(=1) / Supervisor (=0) flag. */
1320	uint32_t u1User : 1;
1321	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1322	uint32_t u1WriteThru : 1;
1323	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1324	uint32_t u1CacheDisable : 1;
1325	/** Accessed flag.
1326	* Indicates that the page have been read or written to. */
1327	uint32_t u1Accessed : 1;
1328	/** Reserved / Ignored (dirty bit). */
1329	uint32_t u1Reserved0 : 1;
1330	/** Size bit if PSE is enabled - in any event it's 0. */
1331	uint32_t u1Size : 1;
1332	/** Reserved / Ignored (global bit). / */
1333	uint32_t u1Reserved1 : 1;
1334	/** Available for use to system software. */
1335	uint32_t u3Available : 3;
1336	/** Physical Page number of the next level - Low Part. Don't use! */
1337	uint32_t u20PageNoLow : 20;
1338	/** Physical Page number of the next level - High Part. Don't use! */
1339	uint32_t u20PageNoHigh : 20;
1340	/** MBZ bits */
1341	uint32_t u11Reserved : 11;
1342	/** No Execute flag. */
1343	uint32_t u1NoExecute : 1;
1344	} X86PDEPAEBITS;
1345	/** Pointer to a page directory entry. */
1346	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1347	/** Pointer to a const page directory entry. */
1348	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1349
1350	/** @} */
1351
1352
1353	/** @name 2/4MB Page Directory Entry
1354	* @{
1355	*/
1356	/** Bit 0 - P - Present bit. */
1357	#define X86_PDE4M_P RT_BIT(0)
1358	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1359	#define X86_PDE4M_RW RT_BIT(1)
1360	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1361	#define X86_PDE4M_US RT_BIT(2)
1362	/** Bit 3 - PWT - Page level write thru bit. */
1363	#define X86_PDE4M_PWT RT_BIT(3)
1364	/** Bit 4 - PCD - Page level cache disable bit. */
1365	#define X86_PDE4M_PCD RT_BIT(4)
1366	/** Bit 5 - A - Access bit. */
1367	#define X86_PDE4M_A RT_BIT(5)
1368	/** Bit 6 - D - Dirty bit. */
1369	#define X86_PDE4M_D RT_BIT(6)
1370	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1371	#define X86_PDE4M_PS RT_BIT(7)
1372	/** Bit 8 - G - Global flag. */
1373	#define X86_PDE4M_G RT_BIT(8)
1374	/** Bits 9-11 - AVL - Available for use to system software. */
1375	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1376	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1377	#define X86_PDE4M_PAT RT_BIT(12)
1378	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1379	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1380	/** Bits 22-31 - - Physical Page number. */
1381	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1382	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1383	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1384	/** The number of bits to the high part of the page number. */
1385	#define X86_PDE4M_PG_HIGH_SHIFT 19
1386
1387	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1388	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1389	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1390	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1391	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1392
1393	/**
1394	* 4MB page directory entry.
1395	*/
1396	typedef struct X86PDE4MBITS
1397	{
1398	/** Flags whether(=1) or not the page is present. */
1399	unsigned u1Present : 1;
1400	/** Read(=0) / Write(=1) flag. */
1401	unsigned u1Write : 1;
1402	/** User(=1) / Supervisor (=0) flag. */
1403	unsigned u1User : 1;
1404	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1405	unsigned u1WriteThru : 1;
1406	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1407	unsigned u1CacheDisable : 1;
1408	/** Accessed flag.
1409	* Indicates that the page have been read or written to. */
1410	unsigned u1Accessed : 1;
1411	/** Dirty flag.
1412	* Indicates that the page have been written to. */
1413	unsigned u1Dirty : 1;
1414	/** Page size flag - always 1 for 4MB entries. */
1415	unsigned u1Size : 1;
1416	/** Global flag. */
1417	unsigned u1Global : 1;
1418	/** Available for use to system software. */
1419	unsigned u3Available : 3;
1420	/** Reserved / If PAT enabled, bit 2 of the index. */
1421	unsigned u1PAT : 1;
1422	/** Bits 32-39 of the page number on AMD64.
1423	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1424	unsigned u8PageNoHigh : 8;
1425	/** Reserved. */
1426	unsigned u1Reserved : 1;
1427	/** Physical Page number of the page. */
1428	unsigned u10PageNo : 10;
1429	} X86PDE4MBITS;
1430	/** Pointer to a page table entry. */
1431	typedef X86PDE4MBITS *PX86PDE4MBITS;
1432	/** Pointer to a const page table entry. */
1433	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1434
1435
1436	/**
1437	* 2MB PAE page directory entry.
1438	*/
1439	typedef struct X86PDE2MPAEBITS
1440	{
1441	/** Flags whether(=1) or not the page is present. */
1442	uint32_t u1Present : 1;
1443	/** Read(=0) / Write(=1) flag. */
1444	uint32_t u1Write : 1;
1445	/** User(=1) / Supervisor(=0) flag. */
1446	uint32_t u1User : 1;
1447	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1448	uint32_t u1WriteThru : 1;
1449	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1450	uint32_t u1CacheDisable : 1;
1451	/** Accessed flag.
1452	* Indicates that the page have been read or written to. */
1453	uint32_t u1Accessed : 1;
1454	/** Dirty flag.
1455	* Indicates that the page have been written to. */
1456	uint32_t u1Dirty : 1;
1457	/** Page size flag - always 1 for 2MB entries. */
1458	uint32_t u1Size : 1;
1459	/** Global flag. */
1460	uint32_t u1Global : 1;
1461	/** Available for use to system software. */
1462	uint32_t u3Available : 3;
1463	/** Reserved / If PAT enabled, bit 2 of the index. */
1464	uint32_t u1PAT : 1;
1465	/** Reserved. */
1466	uint32_t u9Reserved : 9;
1467	/** Physical Page number of the next level - Low part. Don't use! */
1468	uint32_t u10PageNoLow : 10;
1469	/** Physical Page number of the next level - High part. Don't use! */
1470	uint32_t u20PageNoHigh : 20;
1471	/** MBZ bits */
1472	uint32_t u11Reserved : 11;
1473	/** No Execute flag. */
1474	uint32_t u1NoExecute : 1;
1475	} X86PDE2MPAEBITS;
1476	/** Pointer to a 4MB PAE page table entry. */
1477	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1478	/** Pointer to a 4MB PAE page table entry. */
1479	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1480
1481	/** @} */
1482
1483	/**
1484	* Page directory entry.
1485	*/
1486	typedef union X86PDE
1487	{
1488	/** Unsigned integer view. */
1489	X86PGUINT u;
1490	/** Normal view. */
1491	X86PDEBITS n;
1492	/** 4MB view (big). */
1493	X86PDE4MBITS b;
1494	/** 8 bit unsigned integer view. */
1495	uint8_t au8[4];
1496	/** 16 bit unsigned integer view. */
1497	uint16_t au16[2];
1498	/** 32 bit unsigned integer view. */
1499	uint32_t au32[1];
1500	} X86PDE;
1501	/** Pointer to a page directory entry. */
1502	typedef X86PDE *PX86PDE;
1503	/** Pointer to a const page directory entry. */
1504	typedef const X86PDE *PCX86PDE;
1505
1506	/**
1507	* PAE page directory entry.
1508	*/
1509	typedef union X86PDEPAE
1510	{
1511	/** Unsigned integer view. */
1512	X86PGPAEUINT u;
1513	/** Normal view. */
1514	X86PDEPAEBITS n;
1515	/** 2MB page view (big). */
1516	X86PDE2MPAEBITS b;
1517	/** 8 bit unsigned integer view. */
1518	uint8_t au8[8];
1519	/** 16 bit unsigned integer view. */
1520	uint16_t au16[4];
1521	/** 32 bit unsigned integer view. */
1522	uint32_t au32[2];
1523	} X86PDEPAE;
1524	/** Pointer to a page directory entry. */
1525	typedef X86PDEPAE *PX86PDEPAE;
1526	/** Pointer to a const page directory entry. */
1527	typedef const X86PDEPAE *PCX86PDEPAE;
1528
1529	/**
1530	* Page directory.
1531	*/
1532	typedef struct X86PD
1533	{
1534	/** PDE Array. */
1535	X86PDE a[X86_PG_ENTRIES];
1536	} X86PD;
1537	/** Pointer to a page directory. */
1538	typedef X86PD *PX86PD;
1539	/** Pointer to a const page directory. */
1540	typedef const X86PD *PCX86PD;
1541
1542	/** The page shift to get the PD index. */
1543	#define X86_PD_SHIFT 22
1544	/** The PD index mask (apply to a shifted page address). */
1545	#define X86_PD_MASK 0x3ff
1546
1547
1548	/**
1549	* PAE page directory.
1550	*/
1551	typedef struct X86PDPAE
1552	{
1553	/** PDE Array. */
1554	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1555	} X86PDPAE;
1556	/** Pointer to a PAE page directory. */
1557	typedef X86PDPAE *PX86PDPAE;
1558	/** Pointer to a const PAE page directory. */
1559	typedef const X86PDPAE *PCX86PDPAE;
1560
1561	/** The page shift to get the PAE PD index. */
1562	#define X86_PD_PAE_SHIFT 21
1563	/** The PAE PD index mask (apply to a shifted page address). */
1564	#define X86_PD_PAE_MASK 0x1ff
1565
1566
1567	/** @name Page Directory Pointer Table Entry (PAE)
1568	* @{
1569	*/
1570	/** Bit 0 - P - Present bit. */
1571	#define X86_PDPE_P RT_BIT(0)
1572	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1573	#define X86_PDPE_RW RT_BIT(1)
1574	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1575	#define X86_PDPE_US RT_BIT(2)
1576	/** Bit 3 - PWT - Page level write thru bit. */
1577	#define X86_PDPE_PWT RT_BIT(3)
1578	/** Bit 4 - PCD - Page level cache disable bit. */
1579	#define X86_PDPE_PCD RT_BIT(4)
1580	/** Bit 5 - A - Access bit. Long Mode only. */
1581	#define X86_PDPE_A RT_BIT(5)
1582	/** Bits 9-11 - - Available for use to system software. */
1583	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1584	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1585	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1586	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1587	/** @todo Get rid of the above hack; makes code unreadable. */
1588	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1589	#else
1590	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1591	#endif
1592	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1593	#define X86_PDPE_NX RT_BIT_64(63)
1594
1595	/**
1596	* Page directory pointer table entry.
1597	*/
1598	typedef struct X86PDPEBITS
1599	{
1600	/** Flags whether(=1) or not the page is present. */
1601	uint32_t u1Present : 1;
1602	/** Chunk of reserved bits. */
1603	uint32_t u2Reserved : 2;
1604	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1605	uint32_t u1WriteThru : 1;
1606	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1607	uint32_t u1CacheDisable : 1;
1608	/** Chunk of reserved bits. */
1609	uint32_t u4Reserved : 4;
1610	/** Available for use to system software. */
1611	uint32_t u3Available : 3;
1612	/** Physical Page number of the next level - Low Part. Don't use! */
1613	uint32_t u20PageNoLow : 20;
1614	/** Physical Page number of the next level - High Part. Don't use! */
1615	uint32_t u20PageNoHigh : 20;
1616	/** MBZ bits */
1617	uint32_t u12Reserved : 12;
1618	} X86PDPEBITS;
1619	/** Pointer to a page directory pointer table entry. */
1620	typedef X86PDPEBITS *PX86PTPEBITS;
1621	/** Pointer to a const page directory pointer table entry. */
1622	typedef const X86PDPEBITS *PCX86PTPEBITS;
1623
1624	/**
1625	* Page directory pointer table entry. AMD64 version
1626	*/
1627	typedef struct X86PDPEAMD64BITS
1628	{
1629	/** Flags whether(=1) or not the page is present. */
1630	uint32_t u1Present : 1;
1631	/** Read(=0) / Write(=1) flag. */
1632	uint32_t u1Write : 1;
1633	/** User(=1) / Supervisor (=0) flag. */
1634	uint32_t u1User : 1;
1635	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1636	uint32_t u1WriteThru : 1;
1637	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1638	uint32_t u1CacheDisable : 1;
1639	/** Accessed flag.
1640	* Indicates that the page have been read or written to. */
1641	uint32_t u1Accessed : 1;
1642	/** Chunk of reserved bits. */
1643	uint32_t u3Reserved : 3;
1644	/** Available for use to system software. */
1645	uint32_t u3Available : 3;
1646	/** Physical Page number of the next level - Low Part. Don't use! */
1647	uint32_t u20PageNoLow : 20;
1648	/** Physical Page number of the next level - High Part. Don't use! */
1649	uint32_t u20PageNoHigh : 20;
1650	/** MBZ bits */
1651	uint32_t u11Reserved : 11;
1652	/** No Execute flag. */
1653	uint32_t u1NoExecute : 1;
1654	} X86PDPEAMD64BITS;
1655	/** Pointer to a page directory pointer table entry. */
1656	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1657	/** Pointer to a const page directory pointer table entry. */
1658	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1659
1660	/**
1661	* Page directory pointer table entry.
1662	*/
1663	typedef union X86PDPE
1664	{
1665	/** Unsigned integer view. */
1666	X86PGPAEUINT u;
1667	/** Normal view. */
1668	X86PDPEBITS n;
1669	/** AMD64 view. */
1670	X86PDPEAMD64BITS lm;
1671	/** 8 bit unsigned integer view. */
1672	uint8_t au8[8];
1673	/** 16 bit unsigned integer view. */
1674	uint16_t au16[4];
1675	/** 32 bit unsigned integer view. */
1676	uint32_t au32[2];
1677	} X86PDPE;
1678	/** Pointer to a page directory pointer table entry. */
1679	typedef X86PDPE *PX86PDPE;
1680	/** Pointer to a const page directory pointer table entry. */
1681	typedef const X86PDPE *PCX86PDPE;
1682
1683
1684	/**
1685	* Page directory pointer table.
1686	*/
1687	typedef struct X86PDPT
1688	{
1689	/** PDE Array. */
1690	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1691	} X86PDPT;
1692	/** Pointer to a page directory pointer table. */
1693	typedef X86PDPT *PX86PDPT;
1694	/** Pointer to a const page directory pointer table. */
1695	typedef const X86PDPT *PCX86PDPT;
1696
1697	/** The page shift to get the PDPT index. */
1698	#define X86_PDPT_SHIFT 30
1699	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1700	#define X86_PDPT_MASK_PAE 0x3
1701	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1702	#define X86_PDPT_MASK_AMD64 0x1ff
1703
1704	/** @} */
1705
1706
1707	/** @name Page Map Level-4 Entry (Long Mode PAE)
1708	* @{
1709	*/
1710	/** Bit 0 - P - Present bit. */
1711	#define X86_PML4E_P RT_BIT(0)
1712	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1713	#define X86_PML4E_RW RT_BIT(1)
1714	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1715	#define X86_PML4E_US RT_BIT(2)
1716	/** Bit 3 - PWT - Page level write thru bit. */
1717	#define X86_PML4E_PWT RT_BIT(3)
1718	/** Bit 4 - PCD - Page level cache disable bit. */
1719	#define X86_PML4E_PCD RT_BIT(4)
1720	/** Bit 5 - A - Access bit. */
1721	#define X86_PML4E_A RT_BIT(5)
1722	/** Bits 9-11 - - Available for use to system software. */
1723	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1724	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1725	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1726	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1727	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1728	#else
1729	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1730	#endif
1731	/** Bits 63 - NX - PAE - No execution flag. */
1732	#define X86_PML4E_NX RT_BIT_64(63)
1733
1734	/**
1735	* Page Map Level-4 Entry
1736	*/
1737	typedef struct X86PML4EBITS
1738	{
1739	/** Flags whether(=1) or not the page is present. */
1740	uint32_t u1Present : 1;
1741	/** Read(=0) / Write(=1) flag. */
1742	uint32_t u1Write : 1;
1743	/** User(=1) / Supervisor (=0) flag. */
1744	uint32_t u1User : 1;
1745	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1746	uint32_t u1WriteThru : 1;
1747	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1748	uint32_t u1CacheDisable : 1;
1749	/** Accessed flag.
1750	* Indicates that the page have been read or written to. */
1751	uint32_t u1Accessed : 1;
1752	/** Chunk of reserved bits. */
1753	uint32_t u3Reserved : 3;
1754	/** Available for use to system software. */
1755	uint32_t u3Available : 3;
1756	/** Physical Page number of the next level - Low Part. Don't use! */
1757	uint32_t u20PageNoLow : 20;
1758	/** Physical Page number of the next level - High Part. Don't use! */
1759	uint32_t u20PageNoHigh : 20;
1760	/** MBZ bits */
1761	uint32_t u11Reserved : 11;
1762	/** No Execute flag. */
1763	uint32_t u1NoExecute : 1;
1764	} X86PML4EBITS;
1765	/** Pointer to a page map level-4 entry. */
1766	typedef X86PML4EBITS *PX86PML4EBITS;
1767	/** Pointer to a const page map level-4 entry. */
1768	typedef const X86PML4EBITS *PCX86PML4EBITS;
1769
1770	/**
1771	* Page Map Level-4 Entry.
1772	*/
1773	typedef union X86PML4E
1774	{
1775	/** Unsigned integer view. */
1776	X86PGPAEUINT u;
1777	/** Normal view. */
1778	X86PML4EBITS n;
1779	/** 8 bit unsigned integer view. */
1780	uint8_t au8[8];
1781	/** 16 bit unsigned integer view. */
1782	uint16_t au16[4];
1783	/** 32 bit unsigned integer view. */
1784	uint32_t au32[2];
1785	} X86PML4E;
1786	/** Pointer to a page map level-4 entry. */
1787	typedef X86PML4E *PX86PML4E;
1788	/** Pointer to a const page map level-4 entry. */
1789	typedef const X86PML4E *PCX86PML4E;
1790
1791
1792	/**
1793	* Page Map Level-4.
1794	*/
1795	typedef struct X86PML4
1796	{
1797	/** PDE Array. */
1798	X86PML4E a[X86_PG_PAE_ENTRIES];
1799	} X86PML4;
1800	/** Pointer to a page map level-4. */
1801	typedef X86PML4 *PX86PML4;
1802	/** Pointer to a const page map level-4. */
1803	typedef const X86PML4 *PCX86PML4;
1804
1805	/** The page shift to get the PML4 index. */
1806	#define X86_PML4_SHIFT 39
1807	/** The PML4 index mask (apply to a shifted page address). */
1808	#define X86_PML4_MASK 0x1ff
1809
1810	/** @} */
1811
1812	/** @} */
1813
1814
1815	/**
1816	* 80-bit MMX/FPU register type.
1817	*/
1818	typedef struct X86FPUMMX
1819	{
1820	uint8_t reg[10];
1821	} X86FPUMMX;
1822	/** Pointer to a 80-bit MMX/FPU register type. */
1823	typedef X86FPUMMX *PX86FPUMMX;
1824	/** Pointer to a const 80-bit MMX/FPU register type. */
1825	typedef const X86FPUMMX *PCX86FPUMMX;
1826
1827	/**
1828	* FPU state (aka FSAVE/FRSTOR Memory Region).
1829	*/
1830	#pragma pack(1)
1831	typedef struct X86FPUSTATE
1832	{
1833	/** Control word. */
1834	uint16_t FCW;
1835	/** Alignment word */
1836	uint16_t Dummy1;
1837	/** Status word. */
1838	uint16_t FSW;
1839	/** Alignment word */
1840	uint16_t Dummy2;
1841	/** Tag word */
1842	uint16_t FTW;
1843	/** Alignment word */
1844	uint16_t Dummy3;
1845
1846	/** Instruction pointer. */
1847	uint32_t FPUIP;
1848	/** Code selector. */
1849	uint16_t CS;
1850	/** Opcode. */
1851	uint16_t FOP;
1852	/** FOO. */
1853	uint32_t FPUOO;
1854	/** FOS. */
1855	uint32_t FPUOS;
1856	/** FPU view - todo. */
1857	X86FPUMMX regs[8];
1858	} X86FPUSTATE;
1859	#pragma pack()
1860	/** Pointer to a FPU state. */
1861	typedef X86FPUSTATE *PX86FPUSTATE;
1862	/** Pointer to a const FPU state. */
1863	typedef const X86FPUSTATE *PCX86FPUSTATE;
1864
1865	/**
1866	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1867	*/
1868	#pragma pack(1)
1869	typedef struct X86FXSTATE
1870	{
1871	/** Control word. */
1872	uint16_t FCW;
1873	/** Status word. */
1874	uint16_t FSW;
1875	/** Tag word (it's a byte actually). */
1876	uint8_t FTW;
1877	uint8_t huh1;
1878	/** Opcode. */
1879	uint16_t FOP;
1880	/** Instruction pointer. */
1881	uint32_t FPUIP;
1882	/** Code selector. */
1883	uint16_t CS;
1884	uint16_t Rsvrd1;
1885	/* - offset 16 - */
1886	/** Data pointer. */
1887	uint32_t FPUDP;
1888	/** Data segment */
1889	uint16_t DS;
1890	uint16_t Rsrvd2;
1891	uint32_t MXCSR;
1892	uint32_t MXCSR_MASK;
1893	/* - offset 32 - */
1894	union
1895	{
1896	/** MMX view. */
1897	uint64_t mmx;
1898	/** FPU view - todo. */
1899	X86FPUMMX fpu;
1900	/** 8-bit view. */
1901	uint8_t au8[16];
1902	/** 16-bit view. */
1903	uint16_t au16[8];
1904	/** 32-bit view. */
1905	uint32_t au32[4];
1906	/** 64-bit view. */
1907	uint64_t au64[2];
1908	/** 128-bit view. (yeah, very helpful) */
1909	uint128_t au128[1];
1910	} aRegs[8];
1911	/* - offset 160 - */
1912	union
1913	{
1914	/** XMM Register view . /
1915	uint128_t xmm;
1916	/** 8-bit view. */
1917	uint8_t au8[16];
1918	/** 16-bit view. */
1919	uint16_t au16[8];
1920	/** 32-bit view. */
1921	uint32_t au32[4];
1922	/** 64-bit view. */
1923	uint64_t au64[2];
1924	/** 128-bit view. (yeah, very helpful) */
1925	uint128_t au128[1];
1926	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1927	/* - offset 416 - */
1928	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1929	} X86FXSTATE;
1930	#pragma pack()
1931	/** Pointer to a FPU Extended state. */
1932	typedef X86FXSTATE *PX86FXSTATE;
1933	/** Pointer to a const FPU Extended state. */
1934	typedef const X86FXSTATE *PCX86FXSTATE;
1935
1936
1937	/** @name Selector Descriptor
1938	* @{
1939	*/
1940
1941	/**
1942	* Descriptor attributes.
1943	*/
1944	typedef struct X86DESCATTRBITS
1945	{
1946	/** Segment Type. */
1947	unsigned u4Type : 4;
1948	/** Descriptor Type. System(=0) or code/data selector */
1949	unsigned u1DescType : 1;
1950	/** Descriptor Privelege level. */
1951	unsigned u2Dpl : 2;
1952	/** Flags selector present(=1) or not. */
1953	unsigned u1Present : 1;
1954	/** Segment limit 16-19. */
1955	unsigned u4LimitHigh : 4;
1956	/** Available for system software. */
1957	unsigned u1Available : 1;
1958	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1959	unsigned u1Long : 1;
1960	/** This flags meaning depends on the segment type. Try make sense out
1961	* of the intel manual yourself. */
1962	unsigned u1DefBig : 1;
1963	/** Granularity of the limit. If set 4KB granularity is used, if
1964	* clear byte. */
1965	unsigned u1Granularity : 1;
1966	} X86DESCATTRBITS;
1967
1968
1969	#pragma pack(1)
1970	typedef union X86DESCATTR
1971	{
1972	/** Unsigned integer view. */
1973	uint32_t u;
1974	/** Normal view. */
1975	X86DESCATTRBITS n;
1976	} X86DESCATTR;
1977	#pragma pack()
1978	/** Pointer to descriptor attributes. */
1979	typedef X86DESCATTR *PX86DESCATTR;
1980	/** Pointer to const descriptor attributes. */
1981	typedef const X86DESCATTR *PCX86DESCATTR;
1982
1983
1984	/**
1985	* Generic descriptor table entry
1986	*/
1987	#pragma pack(1)
1988	typedef struct X86DESCGENERIC
1989	{
1990	/** Limit - Low word. */
1991	unsigned u16LimitLow : 16;
1992	/** Base address - lowe word.
1993	* Don't try set this to 24 because MSC is doing stupid things then. */
1994	unsigned u16BaseLow : 16;
1995	/** Base address - first 8 bits of high word. */
1996	unsigned u8BaseHigh1 : 8;
1997	/** Segment Type. */
1998	unsigned u4Type : 4;
1999	/** Descriptor Type. System(=0) or code/data selector */
2000	unsigned u1DescType : 1;
2001	/** Descriptor Privelege level. */
2002	unsigned u2Dpl : 2;
2003	/** Flags selector present(=1) or not. */
2004	unsigned u1Present : 1;
2005	/** Segment limit 16-19. */
2006	unsigned u4LimitHigh : 4;
2007	/** Available for system software. */
2008	unsigned u1Available : 1;
2009	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2010	unsigned u1Long : 1;
2011	/** This flags meaning depends on the segment type. Try make sense out
2012	* of the intel manual yourself. */
2013	unsigned u1DefBig : 1;
2014	/** Granularity of the limit. If set 4KB granularity is used, if
2015	* clear byte. */
2016	unsigned u1Granularity : 1;
2017	/** Base address - highest 8 bits. */
2018	unsigned u8BaseHigh2 : 8;
2019	} X86DESCGENERIC;
2020	#pragma pack()
2021	/** Pointer to a generic descriptor entry. */
2022	typedef X86DESCGENERIC *PX86DESCGENERIC;
2023	/** Pointer to a const generic descriptor entry. */
2024	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2025
2026	/**
2027	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2028	*/
2029	typedef struct X86DESCGATE
2030	{
2031	/** Target code segment offset - Low word.
2032	* Ignored if task-gate. */
2033	unsigned u16OffsetLow : 16;
2034	/** Target code segment selector for call-, interrupt- and trap-gates,
2035	* TSS selector if task-gate. */
2036	unsigned u16Sel : 16;
2037	/** Number of parameters for a call-gate.
2038	* Ignored if interrupt-, trap- or task-gate. */
2039	unsigned u4ParmCount : 4;
2040	/** Reserved / ignored. */
2041	unsigned u4Reserved : 4;
2042	/** Segment Type. */
2043	unsigned u4Type : 4;
2044	/** Descriptor Type (0 = system). */
2045	unsigned u1DescType : 1;
2046	/** Descriptor Privelege level. */
2047	unsigned u2Dpl : 2;
2048	/** Flags selector present(=1) or not. */
2049	unsigned u1Present : 1;
2050	/** Target code segment offset - High word.
2051	* Ignored if task-gate. */
2052	unsigned u16OffsetHigh : 16;
2053	} X86DESCGATE;
2054	AssertCompileSize(X86DESCGATE, 8);
2055	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2056	typedef X86DESCGATE *PX86DESCGATE;
2057	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2058	typedef const X86DESCGATE *PCX86DESCGATE;
2059
2060	/**
2061	* Descriptor table entry.
2062	*/
2063	#pragma pack(1)
2064	typedef union X86DESC
2065	{
2066	/** Generic descriptor view. */
2067	X86DESCGENERIC Gen;
2068	/** Gate descriptor view. */
2069	X86DESCGATE Gate;
2070
2071	/** 8 bit unsigned interger view. */
2072	uint8_t au8[8];
2073	/** 16 bit unsigned interger view. */
2074	uint16_t au16[4];
2075	/** 32 bit unsigned interger view. */
2076	uint32_t au32[2];
2077	} X86DESC;
2078	AssertCompileSize(X86DESC, 8);
2079	#pragma pack()
2080	/** Pointer to descriptor table entry. */
2081	typedef X86DESC *PX86DESC;
2082	/** Pointer to const descriptor table entry. */
2083	typedef const X86DESC *PCX86DESC;
2084
2085	/** @def X86DESC_BASE
2086	* Return the base address of a descriptor.
2087	*/
2088	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2089	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2090	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2091	\| ( (desc).Gen.u16BaseLow ) )
2092
2093	/** @def X86DESC_LIMIT
2094	* Return the limit of a descriptor.
2095	*/
2096	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2097	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2098	\| ( (desc).Gen.u16LimitLow ) )
2099
2100	/**
2101	* 64 bits generic descriptor table entry
2102	* Note: most of these bits have no meaning in long mode.
2103	*/
2104	#pragma pack(1)
2105	typedef struct X86DESC64GENERIC
2106	{
2107	/** Limit - Low word - IGNORED. */
2108	unsigned u16LimitLow : 16;
2109	/** Base address - lowe word. - IGNORED
2110	* Don't try set this to 24 because MSC is doing stupid things then. */
2111	unsigned u16BaseLow : 16;
2112	/** Base address - first 8 bits of high word. - IGNORED */
2113	unsigned u8BaseHigh1 : 8;
2114	/** Segment Type. */
2115	unsigned u4Type : 4;
2116	/** Descriptor Type. System(=0) or code/data selector */
2117	unsigned u1DescType : 1;
2118	/** Descriptor Privelege level. */
2119	unsigned u2Dpl : 2;
2120	/** Flags selector present(=1) or not. */
2121	unsigned u1Present : 1;
2122	/** Segment limit 16-19. - IGNORED */
2123	unsigned u4LimitHigh : 4;
2124	/** Available for system software. - IGNORED */
2125	unsigned u1Available : 1;
2126	/** Long mode flag. */
2127	unsigned u1Long : 1;
2128	/** This flags meaning depends on the segment type. Try make sense out
2129	* of the intel manual yourself. */
2130	unsigned u1DefBig : 1;
2131	/** Granularity of the limit. If set 4KB granularity is used, if
2132	* clear byte. - IGNORED */
2133	unsigned u1Granularity : 1;
2134	/** Base address - highest 8 bits. - IGNORED */
2135	unsigned u8BaseHigh2 : 8;
2136	/** Base address - bits 63-32. */
2137	unsigned u32BaseHigh3 : 32;
2138	unsigned u8Reserved : 8;
2139	unsigned u5Zeros : 5;
2140	unsigned u19Reserved : 19;
2141	} X86DESC64GENERIC;
2142	#pragma pack()
2143	/** Pointer to a generic descriptor entry. */
2144	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2145	/** Pointer to a const generic descriptor entry. */
2146	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2147
2148	/**
2149	* System descriptor table entry (64 bits)
2150	*
2151	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2152	*/
2153	#pragma pack(1)
2154	typedef struct X86DESC64SYSTEM
2155	{
2156	/** Limit - Low word. */
2157	unsigned u16LimitLow : 16;
2158	/** Base address - lowe word.
2159	* Don't try set this to 24 because MSC is doing stupid things then. */
2160	unsigned u16BaseLow : 16;
2161	/** Base address - first 8 bits of high word. */
2162	unsigned u8BaseHigh1 : 8;
2163	/** Segment Type. */
2164	unsigned u4Type : 4;
2165	/** Descriptor Type. System(=0) or code/data selector */
2166	unsigned u1DescType : 1;
2167	/** Descriptor Privelege level. */
2168	unsigned u2Dpl : 2;
2169	/** Flags selector present(=1) or not. */
2170	unsigned u1Present : 1;
2171	/** Segment limit 16-19. */
2172	unsigned u4LimitHigh : 4;
2173	/** Available for system software. */
2174	unsigned u1Available : 1;
2175	/** Reserved - 0. */
2176	unsigned u1Reserved : 1;
2177	/** This flags meaning depends on the segment type. Try make sense out
2178	* of the intel manual yourself. */
2179	unsigned u1DefBig : 1;
2180	/** Granularity of the limit. If set 4KB granularity is used, if
2181	* clear byte. */
2182	unsigned u1Granularity : 1;
2183	/** Base address - bits 31-24. */
2184	unsigned u8BaseHigh2 : 8;
2185	/** Base address - bits 63-32. */
2186	unsigned u32BaseHigh3 : 32;
2187	unsigned u8Reserved : 8;
2188	unsigned u5Zeros : 5;
2189	unsigned u19Reserved : 19;
2190	} X86DESC64SYSTEM;
2191	#pragma pack()
2192	/** Pointer to a system descriptor entry. */
2193	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2194	/** Pointer to a const system descriptor entry. */
2195	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2196
2197	/**
2198	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2199	*/
2200	typedef struct X86DESC64GATE
2201	{
2202	/** Target code segment offset - Low word. */
2203	unsigned u16OffsetLow : 16;
2204	/** Target code segment selector. */
2205	unsigned u16Sel : 16;
2206	/** Interrupt stack table for interrupt- and trap-gates.
2207	* Ignored by call-gates. */
2208	unsigned u3IST : 3;
2209	/** Reserved / ignored. */
2210	unsigned u5Reserved : 5;
2211	/** Segment Type. */
2212	unsigned u4Type : 4;
2213	/** Descriptor Type (0 = system). */
2214	unsigned u1DescType : 1;
2215	/** Descriptor Privelege level. */
2216	unsigned u2Dpl : 2;
2217	/** Flags selector present(=1) or not. */
2218	unsigned u1Present : 1;
2219	/** Target code segment offset - High word.
2220	* Ignored if task-gate. */
2221	unsigned u16OffsetHigh : 16;
2222	/** Target code segment offset - Top dword.
2223	* Ignored if task-gate. */
2224	unsigned u32OffsetTop : 32;
2225	/** Reserved / ignored / must be zero.
2226	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2227	unsigned u32Reserved : 32;
2228	} X86DESC64GATE;
2229	AssertCompileSize(X86DESC64GATE, 16);
2230	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2231	typedef X86DESC64GATE *PX86DESC64GATE;
2232	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2233	typedef const X86DESC64GATE *PCX86DESC64GATE;
2234
2235
2236	/**
2237	* Descriptor table entry.
2238	*/
2239	#pragma pack(1)
2240	typedef union X86DESC64
2241	{
2242	/** Generic descriptor view. */
2243	X86DESC64GENERIC Gen;
2244	/** System descriptor view. */
2245	X86DESC64SYSTEM System;
2246	/** Gate descriptor view. */
2247	X86DESC64GATE Gate;
2248
2249	/** 8 bit unsigned interger view. */
2250	uint8_t au8[16];
2251	/** 16 bit unsigned interger view. */
2252	uint16_t au16[8];
2253	/** 32 bit unsigned interger view. */
2254	uint32_t au32[4];
2255	/** 64 bit unsigned interger view. */
2256	uint64_t au64[2];
2257	} X86DESC64;
2258	AssertCompileSize(X86DESC64, 16);
2259	#pragma pack()
2260	/** Pointer to descriptor table entry. */
2261	typedef X86DESC64 *PX86DESC64;
2262	/** Pointer to const descriptor table entry. */
2263	typedef const X86DESC64 *PCX86DESC64;
2264
2265	/** @def X86DESC64_BASE
2266	* Return the base of a 64-bit descriptor.
2267	*/
2268	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2269	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2270	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2271	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2272	\| ( (desc).Gen.u16BaseLow ) )
2273
2274
2275
2276	/** @name Host system descriptor table entry - Use with care!
2277	* @{ */
2278	/** Host system descriptor table entry. */
2279	#if HC_ARCH_BITS == 64
2280	typedef X86DESC64 X86DESCHC;
2281	#else
2282	typedef X86DESC X86DESCHC;
2283	#endif
2284	/** Pointer to a host system descriptor table entry. */
2285	#if HC_ARCH_BITS == 64
2286	typedef PX86DESC64 PX86DESCHC;
2287	#else
2288	typedef PX86DESC PX86DESCHC;
2289	#endif
2290	/** Pointer to a const host system descriptor table entry. */
2291	#if HC_ARCH_BITS == 64
2292	typedef PCX86DESC64 PCX86DESCHC;
2293	#else
2294	typedef PCX86DESC PCX86DESCHC;
2295	#endif
2296	/** @} */
2297
2298
2299	/** @name Selector Descriptor Types.
2300	* @{
2301	*/
2302
2303	/** @name Non-System Selector Types.
2304	* @{ */
2305	/** Code(=set)/Data(=clear) bit. */
2306	#define X86_SEL_TYPE_CODE 8
2307	/** Memory(=set)/System(=clear) bit. */
2308	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2309	/** Accessed bit. */
2310	#define X86_SEL_TYPE_ACCESSED 1
2311	/** Expand down bit (for data selectors only). */
2312	#define X86_SEL_TYPE_DOWN 4
2313	/** Conforming bit (for code selectors only). */
2314	#define X86_SEL_TYPE_CONF 4
2315	/** Write bit (for data selectors only). */
2316	#define X86_SEL_TYPE_WRITE 2
2317	/** Read bit (for code selectors only). */
2318	#define X86_SEL_TYPE_READ 2
2319
2320	/** Read only selector type. */
2321	#define X86_SEL_TYPE_RO 0
2322	/** Accessed read only selector type. */
2323	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2324	/** Read write selector type. */
2325	#define X86_SEL_TYPE_RW 2
2326	/** Accessed read write selector type. */
2327	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2328	/** Expand down read only selector type. */
2329	#define X86_SEL_TYPE_RO_DOWN 4
2330	/** Accessed expand down read only selector type. */
2331	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2332	/** Expand down read write selector type. */
2333	#define X86_SEL_TYPE_RW_DOWN 6
2334	/** Accessed expand down read write selector type. */
2335	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2336	/** Execute only selector type. */
2337	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2338	/** Accessed execute only selector type. */
2339	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2340	/** Execute and read selector type. */
2341	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2342	/** Accessed execute and read selector type. */
2343	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2344	/** Conforming execute only selector type. */
2345	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2346	/** Accessed Conforming execute only selector type. */
2347	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2348	/** Conforming execute and write selector type. */
2349	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2350	/** Accessed Conforming execute and write selector type. */
2351	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2352	/** @} */
2353
2354
2355	/** @name System Selector Types.
2356	* @{ */
2357	/** Undefined system selector type. */
2358	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2359	/** 286 TSS selector. */
2360	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2361	/** LDT selector. */
2362	#define X86_SEL_TYPE_SYS_LDT 2
2363	/** 286 TSS selector - Busy. */
2364	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2365	/** 286 Callgate selector. */
2366	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2367	/** Taskgate selector. */
2368	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2369	/** 286 Interrupt gate selector. */
2370	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2371	/** 286 Trapgate selector. */
2372	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2373	/** Undefined system selector. */
2374	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2375	/** 386 TSS selector. */
2376	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2377	/** Undefined system selector. */
2378	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2379	/** 386 TSS selector - Busy. */
2380	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2381	/** 386 Callgate selector. */
2382	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2383	/** Undefined system selector. */
2384	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2385	/** 386 Interruptgate selector. */
2386	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2387	/** 386 Trapgate selector. */
2388	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2389	/** @} */
2390
2391	/** @name AMD64 System Selector Types.
2392	* @{ */
2393	#define AMD64_SEL_TYPE_SYS_LDT 2
2394	/** 286 TSS selector - Busy. */
2395	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2396	/** 386 TSS selector - Busy. */
2397	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2398	/** 386 Callgate selector. */
2399	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2400	/** 386 Interruptgate selector. */
2401	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2402	/** 386 Trapgate selector. */
2403	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2404	/** @} */
2405
2406	/** @} */
2407
2408
2409	/** @name Descriptor Table Entry Flag Masks.
2410	* These are for the 2nd 32-bit word of a descriptor.
2411	* @{ */
2412	/** Bits 8-11 - TYPE - Descriptor type mask. */
2413	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2414	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2415	#define X86_DESC_S RT_BIT(12)
2416	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2417	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2418	/** Bit 15 - P - Present. */
2419	#define X86_DESC_P RT_BIT(15)
2420	/** Bit 20 - AVL - Available for system software. */
2421	#define X86_DESC_AVL RT_BIT(20)
2422	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2423	#define X86_DESC_DB RT_BIT(22)
2424	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2425	* used, if clear byte. */
2426	#define X86_DESC_G RT_BIT(23)
2427	/** @} */
2428
2429	/** @} */
2430
2431	/** @name Task segment.
2432	* @{
2433	*/
2434	#pragma pack(1)
2435	typedef struct X86TSS32
2436	{
2437	/** Back link to previous task. (static) */
2438	RTSEL selPrev;
2439	uint16_t padding1;
2440	/** Ring-0 stack pointer. (static) */
2441	uint32_t esp0;
2442	/** Ring-0 stack segment. (static) */
2443	RTSEL ss0;
2444	uint16_t padding_ss0;
2445	/** Ring-1 stack pointer. (static) */
2446	uint32_t esp1;
2447	/** Ring-1 stack segment. (static) */
2448	RTSEL ss1;
2449	uint16_t padding_ss1;
2450	/** Ring-2 stack pointer. (static) */
2451	uint32_t esp2;
2452	/** Ring-2 stack segment. (static) */
2453	RTSEL ss2;
2454	uint16_t padding_ss2;
2455	/** Page directory for the task. (static) */
2456	uint32_t cr3;
2457	/** EIP before task switch. */
2458	uint32_t eip;
2459	/** EFLAGS before task switch. */
2460	uint32_t eflags;
2461	/** EAX before task switch. */
2462	uint32_t eax;
2463	/** ECX before task switch. */
2464	uint32_t ecx;
2465	/** EDX before task switch. */
2466	uint32_t edx;
2467	/** EBX before task switch. */
2468	uint32_t ebx;
2469	/** ESP before task switch. */
2470	uint32_t esp;
2471	/** EBP before task switch. */
2472	uint32_t ebp;
2473	/** ESI before task switch. */
2474	uint32_t esi;
2475	/** EDI before task switch. */
2476	uint32_t edi;
2477	/** ES before task switch. */
2478	RTSEL es;
2479	uint16_t padding_es;
2480	/** CS before task switch. */
2481	RTSEL cs;
2482	uint16_t padding_cs;
2483	/** SS before task switch. */
2484	RTSEL ss;
2485	uint16_t padding_ss;
2486	/** DS before task switch. */
2487	RTSEL ds;
2488	uint16_t padding_ds;
2489	/** FS before task switch. */
2490	RTSEL fs;
2491	uint16_t padding_fs;
2492	/** GS before task switch. */
2493	RTSEL gs;
2494	uint16_t padding_gs;
2495	/** LDTR before task switch. */
2496	RTSEL selLdt;
2497	uint16_t padding_ldt;
2498	/** Debug trap flag */
2499	uint16_t fDebugTrap;
2500	/** Offset relative to the TSS of the start of the I/O Bitmap
2501	* and the end of the interrupt redirection bitmap. */
2502	uint16_t offIoBitmap;
2503	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2504	uint8_t IntRedirBitmap[32];
2505	} X86TSS32;
2506	#pragma pack()
2507	/** Pointer to task segment. */
2508	typedef X86TSS32 *PX86TSS32;
2509	/** Pointer to const task segment. */
2510	typedef const X86TSS32 *PCX86TSS32;
2511	/** @} */
2512
2513
2514	/** @name 64 bits Task segment.
2515	* @{
2516	*/
2517	#pragma pack(1)
2518	typedef struct X86TSS64
2519	{
2520	/** Reserved. */
2521	uint32_t u32Reserved;
2522	/** Ring-0 stack pointer. (static) */
2523	uint64_t rsp0;
2524	/** Ring-1 stack pointer. (static) */
2525	uint64_t rsp1;
2526	/** Ring-2 stack pointer. (static) */
2527	uint64_t rsp2;
2528	/** Reserved. */
2529	uint32_t u32Reserved2[2];
2530	/* IST */
2531	uint64_t ist1;
2532	uint64_t ist2;
2533	uint64_t ist3;
2534	uint64_t ist4;
2535	uint64_t ist5;
2536	uint64_t ist6;
2537	uint64_t ist7;
2538	/* Reserved. */
2539	uint16_t u16Reserved[5];
2540	/** Offset relative to the TSS of the start of the I/O Bitmap
2541	* and the end of the interrupt redirection bitmap. */
2542	uint16_t offIoBitmap;
2543	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2544	uint8_t IntRedirBitmap[32];
2545	} X86TSS64;
2546	#pragma pack()
2547	/** Pointer to task segment. */
2548	typedef X86TSS64 *PX86TSS64;
2549	/** Pointer to const task segment. */
2550	typedef const X86TSS64 *PCX86TSS64;
2551	AssertCompileSize(X86TSS64, 136);
2552
2553	/** @} */
2554
2555
2556	/** @name Selectors.
2557	* @{
2558	*/
2559
2560	/**
2561	* The shift used to convert a selector from and to index an index (C).
2562	*/
2563	#define X86_SEL_SHIFT 3
2564
2565	/**
2566	* The mask used to mask off the table indicator and CPL of an selector.
2567	*/
2568	#define X86_SEL_MASK 0xfff8
2569
2570	/**
2571	* The bit indicating that a selector is in the LDT and not in the GDT.
2572	*/
2573	#define X86_SEL_LDT 0x0004
2574	/**
2575	* The bit mask for getting the RPL of a selector.
2576	*/
2577	#define X86_SEL_RPL 0x0003
2578
2579	/** @} */
2580
2581
2582	/**
2583	* x86 Exceptions/Faults/Traps.
2584	*/
2585	typedef enum X86XCPT
2586	{
2587	/** \#DE - Divide error. */
2588	X86_XCPT_DE = 0x00,
2589	/** \#DB - Debug event (single step, DRx, ..) */
2590	X86_XCPT_DB = 0x01,
2591	/** NMI - Non-Maskable Interrupt */
2592	X86_XCPT_NMI = 0x02,
2593	/** \#BP - Breakpoint (INT3). */
2594	X86_XCPT_BP = 0x03,
2595	/** \#OF - Overflow (INTO). */
2596	X86_XCPT_OF = 0x04,
2597	/** \#BR - Bound range exceeded (BOUND). */
2598	X86_XCPT_BR = 0x05,
2599	/** \#UD - Undefined opcode. */
2600	X86_XCPT_UD = 0x06,
2601	/** \#NM - Device not available (math coprocessor device). */
2602	X86_XCPT_NM = 0x07,
2603	/** \#DF - Double fault. */
2604	X86_XCPT_DF = 0x08,
2605	/** ??? - Coprocessor segment overrun (obsolete). */
2606	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2607	/** \#TS - Taskswitch (TSS). */
2608	X86_XCPT_TS = 0x0a,
2609	/** \#NP - Segment no present. */
2610	X86_XCPT_NP = 0x0b,
2611	/** \#SS - Stack segment fault. */
2612	X86_XCPT_SS = 0x0c,
2613	/** \#GP - General protection fault. */
2614	X86_XCPT_GP = 0x0d,
2615	/** \#PF - Page fault. */
2616	X86_XCPT_PF = 0x0e,
2617	/* 0x0f is reserved. */
2618	/** \#MF - Math fault (FPU). */
2619	X86_XCPT_MF = 0x10,
2620	/** \#AC - Alignment check. */
2621	X86_XCPT_AC = 0x11,
2622	/** \#MC - Machine check. */
2623	X86_XCPT_MC = 0x12,
2624	/** \#XF - SIMD Floating-Pointer Exception. */
2625	X86_XCPT_XF = 0x13
2626	} X86XCPT;
2627	/** Pointer to a x86 exception code. */
2628	typedef X86XCPT *PX86XCPT;
2629	/** Pointer to a const x86 exception code. */
2630	typedef const X86XCPT *PCX86XCPT;
2631
2632
2633	/** @name Trap Error Codes
2634	* @{
2635	*/
2636	/** External indicator. */
2637	#define X86_TRAP_ERR_EXTERNAL 1
2638	/** IDT indicator. */
2639	#define X86_TRAP_ERR_IDT 2
2640	/** Descriptor table indicator - If set LDT, if clear GDT. */
2641	#define X86_TRAP_ERR_TI 4
2642	/** Mask for getting the selector. */
2643	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2644	/** Shift for getting the selector table index (C type index). */
2645	#define X86_TRAP_ERR_SEL_SHIFT 3
2646	/** @} */
2647
2648
2649	/** @name \#PF Trap Error Codes
2650	* @{
2651	*/
2652	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2653	#define X86_TRAP_PF_P RT_BIT(0)
2654	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2655	#define X86_TRAP_PF_RW RT_BIT(1)
2656	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2657	#define X86_TRAP_PF_US RT_BIT(2)
2658	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2659	#define X86_TRAP_PF_RSVD RT_BIT(3)
2660	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2661	#define X86_TRAP_PF_ID RT_BIT(4)
2662	/** @} */
2663
2664	#pragma pack(1)
2665	/**
2666	* 32-bit IDTR/GDTR.
2667	*/
2668	typedef struct X86XDTR32
2669	{
2670	/** Size of the descriptor table. */
2671	uint16_t cb;
2672	/** Address of the descriptor table. */
2673	uint32_t uAddr;
2674	} X86XDTR32, *PX86XDTR32;
2675	#pragma pack()
2676
2677	#pragma pack(1)
2678	/**
2679	* 64-bit IDTR/GDTR.
2680	*/
2681	typedef struct X86XDTR64
2682	{
2683	/** Size of the descriptor table. */
2684	uint16_t cb;
2685	/** Address of the descriptor table. */
2686	uint64_t uAddr;
2687	} X86XDTR64, *PX86XDTR64;
2688	#pragma pack()
2689
2690	/** @} */
2691
2692	#endif
2693

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source: vbox/trunk/include/VBox/x86.h@ 23746

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