x86.h@ 24281

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions (VMM,++).
3	*
4	* x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*
27	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
28	* Clara, CA 95054 USA or visit http://www.sun.com if you need
29	* additional information or have any questions.
30	*/
31
32	#ifndef ___VBox_x86_h
33	#define ___VBox_x86_h
34
35	#include <VBox/types.h>
36	#include <iprt/assert.h>
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_x86 x86 Types and Definitions
45	* @{
46	*/
47
48	/**
49	* EFLAGS Bits.
50	*/
51	typedef struct X86EFLAGSBITS
52	{
53	/** Bit 0 - CF - Carry flag - Status flag. */
54	unsigned u1CF : 1;
55	/** Bit 1 - 1 - Reserved flag. */
56	unsigned u1Reserved0 : 1;
57	/** Bit 2 - PF - Parity flag - Status flag. */
58	unsigned u1PF : 1;
59	/** Bit 3 - 0 - Reserved flag. */
60	unsigned u1Reserved1 : 1;
61	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
62	unsigned u1AF : 1;
63	/** Bit 5 - 0 - Reserved flag. */
64	unsigned u1Reserved2 : 1;
65	/** Bit 6 - ZF - Zero flag - Status flag. */
66	unsigned u1ZF : 1;
67	/** Bit 7 - SF - Signed flag - Status flag. */
68	unsigned u1SF : 1;
69	/** Bit 8 - TF - Trap flag - System flag. */
70	unsigned u1TF : 1;
71	/** Bit 9 - IF - Interrupt flag - System flag. */
72	unsigned u1IF : 1;
73	/** Bit 10 - DF - Direction flag - Control flag. */
74	unsigned u1DF : 1;
75	/** Bit 11 - OF - Overflow flag - Status flag. */
76	unsigned u1OF : 1;
77	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
78	unsigned u2IOPL : 2;
79	/** Bit 14 - NT - Nested task flag - System flag. */
80	unsigned u1NT : 1;
81	/** Bit 15 - 0 - Reserved flag. */
82	unsigned u1Reserved3 : 1;
83	/** Bit 16 - RF - Resume flag - System flag. */
84	unsigned u1RF : 1;
85	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
86	unsigned u1VM : 1;
87	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
88	unsigned u1AC : 1;
89	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
90	unsigned u1VIF : 1;
91	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
92	unsigned u1VIP : 1;
93	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
94	unsigned u1ID : 1;
95	/** Bit 22-31 - 0 - Reserved flag. */
96	unsigned u10Reserved4 : 10;
97	} X86EFLAGSBITS;
98	/** Pointer to EFLAGS bits. */
99	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
100	/** Pointer to const EFLAGS bits. */
101	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
102
103	/**
104	* EFLAGS.
105	*/
106	typedef union X86EFLAGS
107	{
108	/** The plain unsigned view. */
109	uint32_t u;
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	} X86EFLAGS;
121	/** Pointer to EFLAGS. */
122	typedef X86EFLAGS *PX86EFLAGS;
123	/** Pointer to const EFLAGS. */
124	typedef const X86EFLAGS *PCX86EFLAGS;
125
126	/**
127	* RFLAGS (32 upper bits are reserved).
128	*/
129	typedef union X86RFLAGS
130	{
131	/** The plain unsigned view. */
132	uint64_t u;
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	} X86RFLAGS;
146	/** Pointer to RFLAGS. */
147	typedef X86RFLAGS *PX86RFLAGS;
148	/** Pointer to const RFLAGS. */
149	typedef const X86RFLAGS *PCX86RFLAGS;
150
151
152	/** @name EFLAGS
153	* @{
154	*/
155	/** Bit 0 - CF - Carry flag - Status flag. */
156	#define X86_EFL_CF RT_BIT(0)
157	/** Bit 2 - PF - Parity flag - Status flag. */
158	#define X86_EFL_PF RT_BIT(2)
159	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
160	#define X86_EFL_AF RT_BIT(4)
161	/** Bit 6 - ZF - Zero flag - Status flag. */
162	#define X86_EFL_ZF RT_BIT(6)
163	/** Bit 7 - SF - Signed flag - Status flag. */
164	#define X86_EFL_SF RT_BIT(7)
165	/** Bit 8 - TF - Trap flag - System flag. */
166	#define X86_EFL_TF RT_BIT(8)
167	/** Bit 9 - IF - Interrupt flag - System flag. */
168	#define X86_EFL_IF RT_BIT(9)
169	/** Bit 10 - DF - Direction flag - Control flag. */
170	#define X86_EFL_DF RT_BIT(10)
171	/** Bit 11 - OF - Overflow flag - Status flag. */
172	#define X86_EFL_OF RT_BIT(11)
173	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
174	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
175	/** Bit 14 - NT - Nested task flag - System flag. */
176	#define X86_EFL_NT RT_BIT(14)
177	/** Bit 16 - RF - Resume flag - System flag. */
178	#define X86_EFL_RF RT_BIT(16)
179	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
180	#define X86_EFL_VM RT_BIT(17)
181	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
182	#define X86_EFL_AC RT_BIT(18)
183	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
184	#define X86_EFL_VIF RT_BIT(19)
185	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
186	#define X86_EFL_VIP RT_BIT(20)
187	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
188	#define X86_EFL_ID RT_BIT(21)
189	/** IOPL shift. */
190	#define X86_EFL_IOPL_SHIFT 12
191	/** The the IOPL level from the flags. */
192	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
193	/** Bits restored by popf */
194	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u1Reserved1 : 1;
207	/** Bit 2 - DS Area 64-bit layout. */
208	unsigned u1DTE64 : 1;
209	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
210	unsigned u1Monitor : 1;
211	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
212	unsigned u1CPLDS : 1;
213	/** Bit 5 - VMX - Virtual Machine Technology. */
214	unsigned u1VMX : 1;
215	/** Bit 6 - SMX: Safer Mode Extensions. */
216	unsigned u1SMX : 1;
217	/** Bit 7 - EST - Enh. SpeedStep Tech. */
218	unsigned u1EST : 1;
219	/** Bit 8 - TM2 - Terminal Monitor 2. */
220	unsigned u1TM2 : 1;
221	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
222	unsigned u1SSSE3 : 1;
223	/** Bit 10 - CNTX-ID - L1 Context ID. */
224	unsigned u1CNTXID : 1;
225	/** Reserved. */
226	unsigned u2Reserved2 : 2;
227	/** Bit 13 - CX16 - CMPXCHG16B. */
228	unsigned u1CX16 : 1;
229	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
230	unsigned u1TPRUpdate : 1;
231	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
232	unsigned u1PDCM : 1;
233	/** Reserved. */
234	unsigned u2Reserved3 : 2;
235	/** Bit 18 - Direct Cache Access. */
236	unsigned u1DCA : 1;
237	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
238	unsigned u1SSE4_1 : 1;
239	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
240	unsigned u1SSE4_2 : 1;
241	/** Bit 21 - x2APIC. */
242	unsigned u1x2APIC : 1;
243	/** Bit 22 - MOVBE - Supports MOVBE. */
244	unsigned u1MOVBE : 1;
245	/** Bit 23 - POPCNT - Supports POPCNT. */
246	unsigned u1POPCNT : 1;
247	/** Reserved. */
248	unsigned u2Reserved4 : 2;
249	/** Bit 26 - XSAVE - Supports XSAVE. */
250	unsigned u1XSAVE : 1;
251	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
252	unsigned u1OSXSAVE : 1;
253	/** Reserved. */
254	unsigned u4Reserved5 : 4;
255	} X86CPUIDFEATECX;
256	/** Pointer to CPUID Feature Information - ECX. */
257	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
258	/** Pointer to const CPUID Feature Information - ECX. */
259	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
260
261
262	/** CPUID Feature Information - EDX.
263	* CPUID query with EAX=1.
264	*/
265	typedef struct X86CPUIDFEATEDX
266	{
267	/** Bit 0 - FPU - x87 FPU on Chip. */
268	unsigned u1FPU : 1;
269	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
270	unsigned u1VME : 1;
271	/** Bit 2 - DE - Debugging extensions. */
272	unsigned u1DE : 1;
273	/** Bit 3 - PSE - Page Size Extension. */
274	unsigned u1PSE : 1;
275	/** Bit 4 - TSC - Time Stamp Counter. */
276	unsigned u1TSC : 1;
277	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
278	unsigned u1MSR : 1;
279	/** Bit 6 - PAE - Physical Address Extension. */
280	unsigned u1PAE : 1;
281	/** Bit 7 - MCE - Machine Check Exception. */
282	unsigned u1MCE : 1;
283	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
284	unsigned u1CX8 : 1;
285	/** Bit 9 - APIC - APIC On-Chip. */
286	unsigned u1APIC : 1;
287	/** Bit 10 - Reserved. */
288	unsigned u1Reserved1 : 1;
289	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
290	unsigned u1SEP : 1;
291	/** Bit 12 - MTRR - Memory Type Range Registers. */
292	unsigned u1MTRR : 1;
293	/** Bit 13 - PGE - PTE Global Bit. */
294	unsigned u1PGE : 1;
295	/** Bit 14 - MCA - Machine Check Architecture. */
296	unsigned u1MCA : 1;
297	/** Bit 15 - CMOV - Conditional Move Instructions. */
298	unsigned u1CMOV : 1;
299	/** Bit 16 - PAT - Page Attribute Table. */
300	unsigned u1PAT : 1;
301	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
302	unsigned u1PSE36 : 1;
303	/** Bit 18 - PSN - Processor Serial Number. */
304	unsigned u1PSN : 1;
305	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
306	unsigned u1CLFSH : 1;
307	/** Bit 20 - Reserved. */
308	unsigned u1Reserved2 : 1;
309	/** Bit 21 - DS - Debug Store. */
310	unsigned u1DS : 1;
311	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
312	unsigned u1ACPI : 1;
313	/** Bit 23 - MMX - Intel MMX 'Technology'. */
314	unsigned u1MMX : 1;
315	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
316	unsigned u1FXSR : 1;
317	/** Bit 25 - SSE - SSE Support. */
318	unsigned u1SSE : 1;
319	/** Bit 26 - SSE2 - SSE2 Support. */
320	unsigned u1SSE2 : 1;
321	/** Bit 27 - SS - Self Snoop. */
322	unsigned u1SS : 1;
323	/** Bit 28 - HTT - Hyper-Threading Technology. */
324	unsigned u1HTT : 1;
325	/** Bit 29 - TM - Thermal Monitor. */
326	unsigned u1TM : 1;
327	/** Bit 30 - Reserved - . */
328	unsigned u1Reserved3 : 1;
329	/** Bit 31 - PBE - Pending Break Enabled. */
330	unsigned u1PBE : 1;
331	} X86CPUIDFEATEDX;
332	/** Pointer to CPUID Feature Information - EDX. */
333	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
334	/** Pointer to const CPUID Feature Information - EDX. */
335	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
336
337	/** @name CPUID Vendor information.
338	* CPUID query with EAX=0.
339	* @{
340	*/
341	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
342	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
343	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
344
345	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
346	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
347	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
348	/** @} */
349
350
351	/** @name CPUID Feature information.
352	* CPUID query with EAX=1.
353	* @{
354	*/
355	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
356	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
357	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
358	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
359	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
360	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
361	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
362	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
363	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
364	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
365	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
366	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
367	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
368	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
369	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
370	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
371	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
372	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
373	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
374	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
375	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
376	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
377	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
378	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
379	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
380	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
381	/** ECX Bit 18 - DCA - Direct Cache Access. */
382	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
383	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
384	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
385	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
386	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
387	/** ECX Bit 21 - x2APIC support. */
388	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
389	/** ECX Bit 22 - MOVBE instruction. */
390	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
391	/** ECX Bit 23 - POPCOUNT instruction. */
392	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
393	/** ECX Bit 26 - XSAVE instruction. */
394	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
395	/** ECX Bit 27 - OSXSAVE instruction. */
396	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
397
398
399	/** Bit 0 - FPU - x87 FPU on Chip. */
400	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
401	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
402	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
403	/** Bit 2 - DE - Debugging extensions. */
404	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
405	/** Bit 3 - PSE - Page Size Extension. */
406	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
407	/** Bit 4 - TSC - Time Stamp Counter. */
408	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
409	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
410	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
411	/** Bit 6 - PAE - Physical Address Extension. */
412	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
413	/** Bit 7 - MCE - Machine Check Exception. */
414	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
415	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
416	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
417	/** Bit 9 - APIC - APIC On-Chip. */
418	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
419	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
420	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
421	/** Bit 12 - MTRR - Memory Type Range Registers. */
422	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
423	/** Bit 13 - PGE - PTE Global Bit. */
424	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
425	/** Bit 14 - MCA - Machine Check Architecture. */
426	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
427	/** Bit 15 - CMOV - Conditional Move Instructions. */
428	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
429	/** Bit 16 - PAT - Page Attribute Table. */
430	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
431	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
432	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
433	/** Bit 18 - PSN - Processor Serial Number. */
434	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
435	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
436	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
437	/** Bit 21 - DS - Debug Store. */
438	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
439	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
440	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
441	/** Bit 23 - MMX - Intel MMX Technology. */
442	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
443	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
444	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
445	/** Bit 25 - SSE - SSE Support. */
446	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
447	/** Bit 26 - SSE2 - SSE2 Support. */
448	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
449	/** Bit 27 - SS - Self Snoop. */
450	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
451	/** Bit 28 - HTT - Hyper-Threading Technology. */
452	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
453	/** Bit 29 - TM - Therm. Monitor. */
454	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
455	/** Bit 31 - PBE - Pending Break Enabled. */
456	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
457	/** @} */
458
459
460	/** @name CPUID AMD Feature information.
461	* CPUID query with EAX=0x80000001.
462	* @{
463	*/
464	/** Bit 0 - FPU - x87 FPU on Chip. */
465	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
466	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
467	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
468	/** Bit 2 - DE - Debugging extensions. */
469	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
470	/** Bit 3 - PSE - Page Size Extension. */
471	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
472	/** Bit 4 - TSC - Time Stamp Counter. */
473	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
474	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
475	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
476	/** Bit 6 - PAE - Physical Address Extension. */
477	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
478	/** Bit 7 - MCE - Machine Check Exception. */
479	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
480	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
481	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
482	/** Bit 9 - APIC - APIC On-Chip. */
483	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
484	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
485	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
486	/** Bit 12 - MTRR - Memory Type Range Registers. */
487	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
488	/** Bit 13 - PGE - PTE Global Bit. */
489	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
490	/** Bit 14 - MCA - Machine Check Architecture. */
491	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
492	/** Bit 15 - CMOV - Conditional Move Instructions. */
493	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
494	/** Bit 16 - PAT - Page Attribute Table. */
495	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
496	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
497	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
498	/** Bit 20 - NX - AMD No-Execute Page Protection. */
499	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
500	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
501	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
502	/** Bit 23 - MMX - Intel MMX Technology. */
503	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
504	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
505	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
506	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
507	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
508	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
509	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
510	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
511	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
512	/** Bit 29 - LM - AMD Long Mode. */
513	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
514	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
515	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
516	/** Bit 31 - 3DNOW - AMD 3DNow. */
517	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
518
519	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
520	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
521	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
522	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
523	/** Bit 2 - SVM - AMD VM extensions. */
524	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
525	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
526	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
527	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
528	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
529	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
530	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
531	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
532	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
533	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
534	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
535	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
536	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
537	/** Bit 9 - OSVW - AMD OS visible workaround. */
538	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
539	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
540	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
541	/** Bit 13 - WDT - AMD Watchdog timer support. */
542	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
543
544	/** @} */
545
546
547	/** @name CPUID AMD Feature information.
548	* CPUID query with EAX=0x80000007.
549	* @{
550	*/
551	/** Bit 0 - TS - Temperature Sensor. */
552	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
553	/** Bit 1 - FID - Frequency ID Control. */
554	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
555	/** Bit 2 - VID - Voltage ID Control. */
556	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
557	/** Bit 3 - TTP - THERMTRIP. */
558	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
559	/** Bit 4 - TM - Hardware Thermal Control. */
560	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
561	/** Bit 5 - STC - Software Thermal Control. */
562	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
563	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
564	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
565	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
566	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
567	/** Bit 8 - TSCINVAR - TSC Invariant. */
568	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
569	/** @} */
570
571
572	/** @name CR0
573	* @{ */
574	/** Bit 0 - PE - Protection Enabled */
575	#define X86_CR0_PE RT_BIT(0)
576	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
577	/** Bit 1 - MP - Monitor Coprocessor */
578	#define X86_CR0_MP RT_BIT(1)
579	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
580	/** Bit 2 - EM - Emulation. */
581	#define X86_CR0_EM RT_BIT(2)
582	#define X86_CR0_EMULATE_FPU RT_BIT(2)
583	/** Bit 3 - TS - Task Switch. */
584	#define X86_CR0_TS RT_BIT(3)
585	#define X86_CR0_TASK_SWITCH RT_BIT(3)
586	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
587	#define X86_CR0_ET RT_BIT(4)
588	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
589	/** Bit 5 - NE - Numeric error. */
590	#define X86_CR0_NE RT_BIT(5)
591	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
592	/** Bit 16 - WP - Write Protect. */
593	#define X86_CR0_WP RT_BIT(16)
594	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
595	/** Bit 18 - AM - Alignment Mask. */
596	#define X86_CR0_AM RT_BIT(18)
597	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
598	/** Bit 29 - NW - Not Write-though. */
599	#define X86_CR0_NW RT_BIT(29)
600	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
601	/** Bit 30 - WP - Cache Disable. */
602	#define X86_CR0_CD RT_BIT(30)
603	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
604	/** Bit 31 - PG - Paging. */
605	#define X86_CR0_PG RT_BIT(31)
606	#define X86_CR0_PAGING RT_BIT(31)
607	/** @} */
608
609
610	/** @name CR3
611	* @{ */
612	/** Bit 3 - PWT - Page-level Writes Transparent. */
613	#define X86_CR3_PWT RT_BIT(3)
614	/** Bit 4 - PCD - Page-level Cache Disable. */
615	#define X86_CR3_PCD RT_BIT(4)
616	/** Bits 12-31 - - Page directory page number. */
617	#define X86_CR3_PAGE_MASK (0xfffff000)
618	/** Bits 5-31 - - PAE Page directory page number. */
619	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
620	/** Bits 12-51 - - AMD64 Page directory page number. */
621	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
622	/** @} */
623
624
625	/** @name CR4
626	* @{ */
627	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
628	#define X86_CR4_VME RT_BIT(0)
629	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
630	#define X86_CR4_PVI RT_BIT(1)
631	/** Bit 2 - TSD - Time Stamp Disable. */
632	#define X86_CR4_TSD RT_BIT(2)
633	/** Bit 3 - DE - Debugging Extensions. */
634	#define X86_CR4_DE RT_BIT(3)
635	/** Bit 4 - PSE - Page Size Extension. */
636	#define X86_CR4_PSE RT_BIT(4)
637	/** Bit 5 - PAE - Physical Address Extension. */
638	#define X86_CR4_PAE RT_BIT(5)
639	/** Bit 6 - MCE - Machine-Check Enable. */
640	#define X86_CR4_MCE RT_BIT(6)
641	/** Bit 7 - PGE - Page Global Enable. */
642	#define X86_CR4_PGE RT_BIT(7)
643	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
644	#define X86_CR4_PCE RT_BIT(8)
645	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
646	#define X86_CR4_OSFSXR RT_BIT(9)
647	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
648	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
649	/** Bit 13 - VMXE - VMX mode is enabled. */
650	#define X86_CR4_VMXE RT_BIT(13)
651	/** @} */
652
653
654	/** @name DR6
655	* @{ */
656	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
657	#define X86_DR6_B0 RT_BIT(0)
658	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
659	#define X86_DR6_B1 RT_BIT(1)
660	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
661	#define X86_DR6_B2 RT_BIT(2)
662	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
663	#define X86_DR6_B3 RT_BIT(3)
664	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
665	#define X86_DR6_BD RT_BIT(13)
666	/** Bit 14 - BS - Single step */
667	#define X86_DR6_BS RT_BIT(14)
668	/** Bit 15 - BT - Task switch. (TSS T bit.) */
669	#define X86_DR6_BT RT_BIT(15)
670	/** Value of DR6 after powerup/reset. */
671	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
672	/** @} */
673
674
675	/** @name DR7
676	* @{ */
677	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
678	#define X86_DR7_L0 RT_BIT(0)
679	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
680	#define X86_DR7_G0 RT_BIT(1)
681	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
682	#define X86_DR7_L1 RT_BIT(2)
683	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
684	#define X86_DR7_G1 RT_BIT(3)
685	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
686	#define X86_DR7_L2 RT_BIT(4)
687	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
688	#define X86_DR7_G2 RT_BIT(5)
689	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
690	#define X86_DR7_L3 RT_BIT(6)
691	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
692	#define X86_DR7_G3 RT_BIT(7)
693	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
694	#define X86_DR7_LE RT_BIT(8)
695	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
696	#define X86_DR7_GE RT_BIT(9)
697
698	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
699	* any DR register is accessed. */
700	#define X86_DR7_GD RT_BIT(13)
701	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
702	#define X86_DR7_RW0_MASK (3 << 16)
703	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
704	#define X86_DR7_LEN0_MASK (3 << 18)
705	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
706	#define X86_DR7_RW1_MASK (3 << 20)
707	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
708	#define X86_DR7_LEN1_MASK (3 << 22)
709	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
710	#define X86_DR7_RW2_MASK (3 << 24)
711	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
712	#define X86_DR7_LEN2_MASK (3 << 26)
713	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
714	#define X86_DR7_RW3_MASK (3 << 28)
715	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
716	#define X86_DR7_LEN3_MASK (3 << 30)
717
718	/** Bits which must be 1s. */
719	#define X86_DR7_MB1_MASK (RT_BIT(10))
720
721	/** Calcs the L bit of Nth breakpoint.
722	* @param iBp The breakpoint number [0..3].
723	*/
724	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
725
726	/** Calcs the G bit of Nth breakpoint.
727	* @param iBp The breakpoint number [0..3].
728	*/
729	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
730
731	/** @name Read/Write values.
732	* @{ */
733	/** Break on instruction fetch only. */
734	#define X86_DR7_RW_EO 0U
735	/** Break on write only. */
736	#define X86_DR7_RW_WO 1U
737	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
738	#define X86_DR7_RW_IO 2U
739	/** Break on read or write (but not instruction fetches). */
740	#define X86_DR7_RW_RW 3U
741	/** @} */
742
743	/** Shifts a X86_DR7_RW_* value to its right place.
744	* @param iBp The breakpoint number [0..3].
745	* @param fRw One of the X86_DR7_RW_* value.
746	*/
747	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
748
749	/** @name Length values.
750	* @{ */
751	#define X86_DR7_LEN_BYTE 0U
752	#define X86_DR7_LEN_WORD 1U
753	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
754	#define X86_DR7_LEN_DWORD 3U
755	/** @} */
756
757	/** Shifts a X86_DR7_LEN_* value to its right place.
758	* @param iBp The breakpoint number [0..3].
759	* @param cb One of the X86_DR7_LEN_* values.
760	*/
761	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
762
763	/** Fetch the breakpoint length bits from the DR7 value.
764	* @param uDR7 DR7 value
765	* @param iBp The breakpoint number [0..3].
766	*/
767	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
768
769	/** Mask used to check if any breakpoints are enabled. */
770	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
771
772	/** Mask used to check if any io breakpoints are set. */
773	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
774
775	/** Value of DR7 after powerup/reset. */
776	#define X86_DR7_INIT_VAL 0x400
777	/** @} */
778
779
780	/** @name Machine Specific Registers
781	* @{
782	*/
783
784	/** Time Stamp Counter. */
785	#define MSR_IA32_TSC 0x10
786
787	#define MSR_IA32_PLATFORM_ID 0x17
788
789	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
790	#define MSR_IA32_APICBASE 0x1b
791	#endif
792
793	/** CPU Feature control. */
794	#define MSR_IA32_FEATURE_CONTROL 0x3A
795	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
796	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
797
798	/** BIOS update trigger (microcode update). */
799	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
800
801	/** BIOS update signature (microcode). */
802	#define MSR_IA32_BIOS_SIGN_ID 0x8B
803
804	/** MTRR Capabilities. */
805	#define MSR_IA32_MTRR_CAP 0xFE
806
807
808	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
809	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
810	* R0 SS == CS + 8
811	* R3 CS == CS + 16
812	* R3 SS == CS + 24
813	*/
814	#define MSR_IA32_SYSENTER_CS 0x174
815	/** SYSENTER_ESP - the R0 ESP. */
816	#define MSR_IA32_SYSENTER_ESP 0x175
817	/** SYSENTER_EIP - the R0 EIP. */
818	#define MSR_IA32_SYSENTER_EIP 0x176
819	#endif
820
821	/** Machine Check Global Capabilities Register. */
822	#define MSR_IA32_MCP_CAP 0x179
823	/** Machine Check Global Status Register. */
824	#define MSR_IA32_MCP_STATUS 0x17A
825	/** Machine Check Global Control Register. */
826	#define MSR_IA32_MCP_CTRL 0x17B
827
828	/** Trace/Profile Resource Control (R/W) */
829	#define MSR_IA32_DEBUGCTL 0x1D9
830
831	/* Page Attribute Table. */
832	#define MSR_IA32_CR_PAT 0x277
833
834	/** Performance counter MSRs. (Intel only) */
835	#define MSR_IA32_PERFEVTSEL0 0x186
836	#define MSR_IA32_PERFEVTSEL1 0x187
837	#define MSR_IA32_PERF_STATUS 0x198
838	#define MSR_IA32_PERF_CTL 0x199
839
840	/** MTRR Default Range. */
841	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
842
843	#define MSR_IA32_MC0_CTL 0x400
844	#define MSR_IA32_MC0_STATUS 0x401
845
846	/** Basic VMX information. */
847	#define MSR_IA32_VMX_BASIC_INFO 0x480
848	/** Allowed settings for pin-based VM execution controls */
849	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
850	/** Allowed settings for proc-based VM execution controls */
851	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
852	/** Allowed settings for the VMX exit controls. */
853	#define MSR_IA32_VMX_EXIT_CTLS 0x483
854	/** Allowed settings for the VMX entry controls. */
855	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
856	/** Misc VMX info. */
857	#define MSR_IA32_VMX_MISC 0x485
858	/** Fixed cleared bits in CR0. */
859	#define MSR_IA32_VMX_CR0_FIXED0 0x486
860	/** Fixed set bits in CR0. */
861	#define MSR_IA32_VMX_CR0_FIXED1 0x487
862	/** Fixed cleared bits in CR4. */
863	#define MSR_IA32_VMX_CR4_FIXED0 0x488
864	/** Fixed set bits in CR4. */
865	#define MSR_IA32_VMX_CR4_FIXED1 0x489
866	/** Information for enumerating fields in the VMCS. */
867	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
868	/** Allowed settings for secondary proc-based VM execution controls */
869	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
870	/** EPT capabilities. */
871	#define MSR_IA32_VMX_EPT_CAPS 0x48C
872	/** DS Save Area (R/W). */
873	#define MSR_IA32_DS_AREA 0x600
874	/** X2APIC MSR ranges. */
875	#define MSR_IA32_APIC_START 0x800
876	#define MSR_IA32_APIC_END 0x900
877
878	/** K6 EFER - Extended Feature Enable Register. */
879	#define MSR_K6_EFER 0xc0000080
880	/** @todo document EFER */
881	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
882	#define MSR_K6_EFER_SCE RT_BIT(0)
883	/** Bit 8 - LME - Long mode enabled. (R/W) */
884	#define MSR_K6_EFER_LME RT_BIT(8)
885	/** Bit 10 - LMA - Long mode active. (R) */
886	#define MSR_K6_EFER_LMA RT_BIT(10)
887	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
888	#define MSR_K6_EFER_NXE RT_BIT(11)
889	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
890	#define MSR_K6_EFER_SVME RT_BIT(12)
891	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
892	#define MSR_K6_EFER_LMSLE RT_BIT(13)
893	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
894	#define MSR_K6_EFER_FFXSR RT_BIT(14)
895	/** K6 STAR - SYSCALL/RET targets. */
896	#define MSR_K6_STAR 0xc0000081
897	/** Shift value for getting the SYSRET CS and SS value. */
898	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
899	/** Shift value for getting the SYSCALL CS and SS value. */
900	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
901	/** Selector mask for use after shifting. */
902	#define MSR_K6_STAR_SEL_MASK 0xffff
903	/** The mask which give the SYSCALL EIP. */
904	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
905	/** K6 WHCR - Write Handling Control Register. */
906	#define MSR_K6_WHCR 0xc0000082
907	/** K6 UWCCR - UC/WC Cacheability Control Register. */
908	#define MSR_K6_UWCCR 0xc0000085
909	/** K6 PSOR - Processor State Observability Register. */
910	#define MSR_K6_PSOR 0xc0000087
911	/** K6 PFIR - Page Flush/Invalidate Register. */
912	#define MSR_K6_PFIR 0xc0000088
913
914	/** Performance counter MSRs. (AMD only) */
915	#define MSR_K7_EVNTSEL0 0xc0010000
916	#define MSR_K7_EVNTSEL1 0xc0010001
917	#define MSR_K7_EVNTSEL2 0xc0010002
918	#define MSR_K7_EVNTSEL3 0xc0010003
919	#define MSR_K7_PERFCTR0 0xc0010004
920	#define MSR_K7_PERFCTR1 0xc0010005
921	#define MSR_K7_PERFCTR2 0xc0010006
922	#define MSR_K7_PERFCTR3 0xc0010007
923
924	#define MSR_K8_HWCR 0xc0010015
925
926	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
927	#define MSR_K8_LSTAR 0xc0000082
928	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
929	#define MSR_K8_CSTAR 0xc0000083
930	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
931	#define MSR_K8_SF_MASK 0xc0000084
932	/** K8 FS.base - The 64-bit base FS register. */
933	#define MSR_K8_FS_BASE 0xc0000100
934	/** K8 GS.base - The 64-bit base GS register. */
935	#define MSR_K8_GS_BASE 0xc0000101
936	/** K8 KernelGSbase - Used with SWAPGS. */
937	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
938	#define MSR_K8_TSC_AUX 0xc0000103
939	#define MSR_K8_SYSCFG 0xc0010010
940	#define MSR_K8_HWCR 0xc0010015
941	#define MSR_K8_IORRBASE0 0xc0010016
942	#define MSR_K8_IORRMASK0 0xc0010017
943	#define MSR_K8_IORRBASE1 0xc0010018
944	#define MSR_K8_IORRMASK1 0xc0010019
945	#define MSR_K8_TOP_MEM1 0xc001001a
946	#define MSR_K8_TOP_MEM2 0xc001001d
947	#define MSR_K8_VM_CR 0xc0010114
948	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
949
950	#define MSR_K8_IGNNE 0xc0010115
951	#define MSR_K8_SMM_CTL 0xc0010116
952	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
953	* host state during world switch.
954	*/
955	#define MSR_K8_VM_HSAVE_PA 0xc0010117
956
957	/** @} */
958
959
960	/** @name Page Table / Directory / Directory Pointers / L4.
961	* @{
962	*/
963
964	/** Page table/directory entry as an unsigned integer. */
965	typedef uint32_t X86PGUINT;
966	/** Pointer to a page table/directory table entry as an unsigned integer. */
967	typedef X86PGUINT *PX86PGUINT;
968	/** Pointer to an const page table/directory table entry as an unsigned integer. */
969	typedef X86PGUINT const *PCX86PGUINT;
970
971	/** Number of entries in a 32-bit PT/PD. */
972	#define X86_PG_ENTRIES 1024
973
974
975	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
976	typedef uint64_t X86PGPAEUINT;
977	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
978	typedef X86PGPAEUINT *PX86PGPAEUINT;
979	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
980	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
981
982	/** Number of entries in a PAE PT/PD. */
983	#define X86_PG_PAE_ENTRIES 512
984	/** Number of entries in a PAE PDPT. */
985	#define X86_PG_PAE_PDPE_ENTRIES 4
986
987	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
988	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
989	/** Number of entries in an AMD64 PDPT.
990	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
991	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
992
993	/** The size of a 4KB page. */
994	#define X86_PAGE_4K_SIZE _4K
995	/** The page shift of a 4KB page. */
996	#define X86_PAGE_4K_SHIFT 12
997	/** The 4KB page offset mask. */
998	#define X86_PAGE_4K_OFFSET_MASK 0xfff
999	/** The 4KB page base mask for virtual addresses. */
1000	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1001	/** The 4KB page base mask for virtual addresses - 32bit version. */
1002	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1003
1004	/** The size of a 2MB page. */
1005	#define X86_PAGE_2M_SIZE _2M
1006	/** The page shift of a 2MB page. */
1007	#define X86_PAGE_2M_SHIFT 21
1008	/** The 2MB page offset mask. */
1009	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1010	/** The 2MB page base mask for virtual addresses. */
1011	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1012	/** The 2MB page base mask for virtual addresses - 32bit version. */
1013	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1014
1015	/** The size of a 4MB page. */
1016	#define X86_PAGE_4M_SIZE _4M
1017	/** The page shift of a 4MB page. */
1018	#define X86_PAGE_4M_SHIFT 22
1019	/** The 4MB page offset mask. */
1020	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1021	/** The 4MB page base mask for virtual addresses. */
1022	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1023	/** The 4MB page base mask for virtual addresses - 32bit version. */
1024	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1025
1026
1027
1028	/** @name Page Table Entry
1029	* @{
1030	*/
1031	/** Bit 0 - P - Present bit. */
1032	#define X86_PTE_BIT_P 0
1033	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1034	#define X86_PTE_BIT_RW 1
1035	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1036	#define X86_PTE_BIT_US 2
1037	/** Bit 3 - PWT - Page level write thru bit. */
1038	#define X86_PTE_BIT_PWT 3
1039	/** Bit 4 - PCD - Page level cache disable bit. */
1040	#define X86_PTE_BIT_PCD 4
1041	/** Bit 5 - A - Access bit. */
1042	#define X86_PTE_BIT_A 5
1043	/** Bit 6 - D - Dirty bit. */
1044	#define X86_PTE_BIT_D 6
1045	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1046	#define X86_PTE_BIT_PAT 7
1047	/** Bit 8 - G - Global flag. */
1048	#define X86_PTE_BIT_G 8
1049
1050	/** Bit 0 - P - Present bit mask. */
1051	#define X86_PTE_P RT_BIT(0)
1052	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1053	#define X86_PTE_RW RT_BIT(1)
1054	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1055	#define X86_PTE_US RT_BIT(2)
1056	/** Bit 3 - PWT - Page level write thru bit mask. */
1057	#define X86_PTE_PWT RT_BIT(3)
1058	/** Bit 4 - PCD - Page level cache disable bit mask. */
1059	#define X86_PTE_PCD RT_BIT(4)
1060	/** Bit 5 - A - Access bit mask. */
1061	#define X86_PTE_A RT_BIT(5)
1062	/** Bit 6 - D - Dirty bit mask. */
1063	#define X86_PTE_D RT_BIT(6)
1064	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1065	#define X86_PTE_PAT RT_BIT(7)
1066	/** Bit 8 - G - Global bit mask. */
1067	#define X86_PTE_G RT_BIT(8)
1068
1069	/** Bits 9-11 - - Available for use to system software. */
1070	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1071	/** Bits 12-31 - - Physical Page number of the next level. */
1072	#define X86_PTE_PG_MASK ( 0xfffff000 )
1073
1074	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1075	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1076	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1077	/** @todo Get rid of the above hack; makes code unreadable. */
1078	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1079	#else
1080	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1081	#endif
1082	/** Bits 63 - NX - PAE - No execution flag. */
1083	#define X86_PTE_PAE_NX RT_BIT_64(63)
1084
1085	/**
1086	* Page table entry.
1087	*/
1088	typedef struct X86PTEBITS
1089	{
1090	/** Flags whether(=1) or not the page is present. */
1091	unsigned u1Present : 1;
1092	/** Read(=0) / Write(=1) flag. */
1093	unsigned u1Write : 1;
1094	/** User(=1) / Supervisor (=0) flag. */
1095	unsigned u1User : 1;
1096	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1097	unsigned u1WriteThru : 1;
1098	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1099	unsigned u1CacheDisable : 1;
1100	/** Accessed flag.
1101	* Indicates that the page have been read or written to. */
1102	unsigned u1Accessed : 1;
1103	/** Dirty flag.
1104	* Indicates that the page have been written to. */
1105	unsigned u1Dirty : 1;
1106	/** Reserved / If PAT enabled, bit 2 of the index. */
1107	unsigned u1PAT : 1;
1108	/** Global flag. (Ignored in all but final level.) */
1109	unsigned u1Global : 1;
1110	/** Available for use to system software. */
1111	unsigned u3Available : 3;
1112	/** Physical Page number of the next level. */
1113	unsigned u20PageNo : 20;
1114	} X86PTEBITS;
1115	/** Pointer to a page table entry. */
1116	typedef X86PTEBITS *PX86PTEBITS;
1117	/** Pointer to a const page table entry. */
1118	typedef const X86PTEBITS *PCX86PTEBITS;
1119
1120	/**
1121	* Page table entry.
1122	*/
1123	typedef union X86PTE
1124	{
1125	/** Unsigned integer view */
1126	X86PGUINT u;
1127	/** Bit field view. */
1128	X86PTEBITS n;
1129	/** 32-bit view. */
1130	uint32_t au32[1];
1131	/** 16-bit view. */
1132	uint16_t au16[2];
1133	/** 8-bit view. */
1134	uint8_t au8[4];
1135	} X86PTE;
1136	/** Pointer to a page table entry. */
1137	typedef X86PTE *PX86PTE;
1138	/** Pointer to a const page table entry. */
1139	typedef const X86PTE *PCX86PTE;
1140
1141
1142	/**
1143	* PAE page table entry.
1144	*/
1145	typedef struct X86PTEPAEBITS
1146	{
1147	/** Flags whether(=1) or not the page is present. */
1148	uint32_t u1Present : 1;
1149	/** Read(=0) / Write(=1) flag. */
1150	uint32_t u1Write : 1;
1151	/** User(=1) / Supervisor(=0) flag. */
1152	uint32_t u1User : 1;
1153	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1154	uint32_t u1WriteThru : 1;
1155	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1156	uint32_t u1CacheDisable : 1;
1157	/** Accessed flag.
1158	* Indicates that the page have been read or written to. */
1159	uint32_t u1Accessed : 1;
1160	/** Dirty flag.
1161	* Indicates that the page have been written to. */
1162	uint32_t u1Dirty : 1;
1163	/** Reserved / If PAT enabled, bit 2 of the index. */
1164	uint32_t u1PAT : 1;
1165	/** Global flag. (Ignored in all but final level.) */
1166	uint32_t u1Global : 1;
1167	/** Available for use to system software. */
1168	uint32_t u3Available : 3;
1169	/** Physical Page number of the next level - Low Part. Don't use this. */
1170	uint32_t u20PageNoLow : 20;
1171	/** Physical Page number of the next level - High Part. Don't use this. */
1172	uint32_t u20PageNoHigh : 20;
1173	/** MBZ bits */
1174	uint32_t u11Reserved : 11;
1175	/** No Execute flag. */
1176	uint32_t u1NoExecute : 1;
1177	} X86PTEPAEBITS;
1178	/** Pointer to a page table entry. */
1179	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1180	/** Pointer to a page table entry. */
1181	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1182
1183	/**
1184	* PAE Page table entry.
1185	*/
1186	typedef union X86PTEPAE
1187	{
1188	/** Unsigned integer view */
1189	X86PGPAEUINT u;
1190	/** Bit field view. */
1191	X86PTEPAEBITS n;
1192	/** 32-bit view. */
1193	uint32_t au32[2];
1194	/** 16-bit view. */
1195	uint16_t au16[4];
1196	/** 8-bit view. */
1197	uint8_t au8[8];
1198	} X86PTEPAE;
1199	/** Pointer to a PAE page table entry. */
1200	typedef X86PTEPAE *PX86PTEPAE;
1201	/** Pointer to a const PAE page table entry. */
1202	typedef const X86PTEPAE *PCX86PTEPAE;
1203	/** @} */
1204
1205	/**
1206	* Page table.
1207	*/
1208	typedef struct X86PT
1209	{
1210	/** PTE Array. */
1211	X86PTE a[X86_PG_ENTRIES];
1212	} X86PT;
1213	/** Pointer to a page table. */
1214	typedef X86PT *PX86PT;
1215	/** Pointer to a const page table. */
1216	typedef const X86PT *PCX86PT;
1217
1218	/** The page shift to get the PT index. */
1219	#define X86_PT_SHIFT 12
1220	/** The PT index mask (apply to a shifted page address). */
1221	#define X86_PT_MASK 0x3ff
1222
1223
1224	/**
1225	* Page directory.
1226	*/
1227	typedef struct X86PTPAE
1228	{
1229	/** PTE Array. */
1230	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1231	} X86PTPAE;
1232	/** Pointer to a page table. */
1233	typedef X86PTPAE *PX86PTPAE;
1234	/** Pointer to a const page table. */
1235	typedef const X86PTPAE *PCX86PTPAE;
1236
1237	/** The page shift to get the PA PTE index. */
1238	#define X86_PT_PAE_SHIFT 12
1239	/** The PAE PT index mask (apply to a shifted page address). */
1240	#define X86_PT_PAE_MASK 0x1ff
1241
1242
1243	/** @name 4KB Page Directory Entry
1244	* @{
1245	*/
1246	/** Bit 0 - P - Present bit. */
1247	#define X86_PDE_P RT_BIT(0)
1248	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1249	#define X86_PDE_RW RT_BIT(1)
1250	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1251	#define X86_PDE_US RT_BIT(2)
1252	/** Bit 3 - PWT - Page level write thru bit. */
1253	#define X86_PDE_PWT RT_BIT(3)
1254	/** Bit 4 - PCD - Page level cache disable bit. */
1255	#define X86_PDE_PCD RT_BIT(4)
1256	/** Bit 5 - A - Access bit. */
1257	#define X86_PDE_A RT_BIT(5)
1258	/** Bit 7 - PS - Page size attribute.
1259	* Clear mean 4KB pages, set means large pages (2/4MB). */
1260	#define X86_PDE_PS RT_BIT(7)
1261	/** Bits 9-11 - - Available for use to system software. */
1262	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1263	/** Bits 12-31 - - Physical Page number of the next level. */
1264	#define X86_PDE_PG_MASK ( 0xfffff000 )
1265
1266	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1267	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1268	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1269	* we partly or that part into shadow page table entries. Will be corrected
1270	* soon.
1271	*/
1272	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1273	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1274	#else
1275	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1276	#endif
1277	/** Bits 63 - NX - PAE - No execution flag. */
1278	#define X86_PDE_PAE_NX RT_BIT_64(63)
1279
1280	/**
1281	* Page directory entry.
1282	*/
1283	typedef struct X86PDEBITS
1284	{
1285	/** Flags whether(=1) or not the page is present. */
1286	unsigned u1Present : 1;
1287	/** Read(=0) / Write(=1) flag. */
1288	unsigned u1Write : 1;
1289	/** User(=1) / Supervisor (=0) flag. */
1290	unsigned u1User : 1;
1291	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1292	unsigned u1WriteThru : 1;
1293	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1294	unsigned u1CacheDisable : 1;
1295	/** Accessed flag.
1296	* Indicates that the page have been read or written to. */
1297	unsigned u1Accessed : 1;
1298	/** Reserved / Ignored (dirty bit). */
1299	unsigned u1Reserved0 : 1;
1300	/** Size bit if PSE is enabled - in any event it's 0. */
1301	unsigned u1Size : 1;
1302	/** Reserved / Ignored (global bit). */
1303	unsigned u1Reserved1 : 1;
1304	/** Available for use to system software. */
1305	unsigned u3Available : 3;
1306	/** Physical Page number of the next level. */
1307	unsigned u20PageNo : 20;
1308	} X86PDEBITS;
1309	/** Pointer to a page directory entry. */
1310	typedef X86PDEBITS *PX86PDEBITS;
1311	/** Pointer to a const page directory entry. */
1312	typedef const X86PDEBITS *PCX86PDEBITS;
1313
1314
1315	/**
1316	* PAE page directory entry.
1317	*/
1318	typedef struct X86PDEPAEBITS
1319	{
1320	/** Flags whether(=1) or not the page is present. */
1321	uint32_t u1Present : 1;
1322	/** Read(=0) / Write(=1) flag. */
1323	uint32_t u1Write : 1;
1324	/** User(=1) / Supervisor (=0) flag. */
1325	uint32_t u1User : 1;
1326	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1327	uint32_t u1WriteThru : 1;
1328	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1329	uint32_t u1CacheDisable : 1;
1330	/** Accessed flag.
1331	* Indicates that the page have been read or written to. */
1332	uint32_t u1Accessed : 1;
1333	/** Reserved / Ignored (dirty bit). */
1334	uint32_t u1Reserved0 : 1;
1335	/** Size bit if PSE is enabled - in any event it's 0. */
1336	uint32_t u1Size : 1;
1337	/** Reserved / Ignored (global bit). / */
1338	uint32_t u1Reserved1 : 1;
1339	/** Available for use to system software. */
1340	uint32_t u3Available : 3;
1341	/** Physical Page number of the next level - Low Part. Don't use! */
1342	uint32_t u20PageNoLow : 20;
1343	/** Physical Page number of the next level - High Part. Don't use! */
1344	uint32_t u20PageNoHigh : 20;
1345	/** MBZ bits */
1346	uint32_t u11Reserved : 11;
1347	/** No Execute flag. */
1348	uint32_t u1NoExecute : 1;
1349	} X86PDEPAEBITS;
1350	/** Pointer to a page directory entry. */
1351	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1352	/** Pointer to a const page directory entry. */
1353	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1354
1355	/** @} */
1356
1357
1358	/** @name 2/4MB Page Directory Entry
1359	* @{
1360	*/
1361	/** Bit 0 - P - Present bit. */
1362	#define X86_PDE4M_P RT_BIT(0)
1363	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1364	#define X86_PDE4M_RW RT_BIT(1)
1365	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1366	#define X86_PDE4M_US RT_BIT(2)
1367	/** Bit 3 - PWT - Page level write thru bit. */
1368	#define X86_PDE4M_PWT RT_BIT(3)
1369	/** Bit 4 - PCD - Page level cache disable bit. */
1370	#define X86_PDE4M_PCD RT_BIT(4)
1371	/** Bit 5 - A - Access bit. */
1372	#define X86_PDE4M_A RT_BIT(5)
1373	/** Bit 6 - D - Dirty bit. */
1374	#define X86_PDE4M_D RT_BIT(6)
1375	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1376	#define X86_PDE4M_PS RT_BIT(7)
1377	/** Bit 8 - G - Global flag. */
1378	#define X86_PDE4M_G RT_BIT(8)
1379	/** Bits 9-11 - AVL - Available for use to system software. */
1380	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1381	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1382	#define X86_PDE4M_PAT RT_BIT(12)
1383	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1384	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1385	/** Bits 22-31 - - Physical Page number. */
1386	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1387	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1388	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1389	/** The number of bits to the high part of the page number. */
1390	#define X86_PDE4M_PG_HIGH_SHIFT 19
1391
1392	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1393	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1394	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1395	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1396	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1397
1398	/**
1399	* 4MB page directory entry.
1400	*/
1401	typedef struct X86PDE4MBITS
1402	{
1403	/** Flags whether(=1) or not the page is present. */
1404	unsigned u1Present : 1;
1405	/** Read(=0) / Write(=1) flag. */
1406	unsigned u1Write : 1;
1407	/** User(=1) / Supervisor (=0) flag. */
1408	unsigned u1User : 1;
1409	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1410	unsigned u1WriteThru : 1;
1411	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1412	unsigned u1CacheDisable : 1;
1413	/** Accessed flag.
1414	* Indicates that the page have been read or written to. */
1415	unsigned u1Accessed : 1;
1416	/** Dirty flag.
1417	* Indicates that the page have been written to. */
1418	unsigned u1Dirty : 1;
1419	/** Page size flag - always 1 for 4MB entries. */
1420	unsigned u1Size : 1;
1421	/** Global flag. */
1422	unsigned u1Global : 1;
1423	/** Available for use to system software. */
1424	unsigned u3Available : 3;
1425	/** Reserved / If PAT enabled, bit 2 of the index. */
1426	unsigned u1PAT : 1;
1427	/** Bits 32-39 of the page number on AMD64.
1428	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1429	unsigned u8PageNoHigh : 8;
1430	/** Reserved. */
1431	unsigned u1Reserved : 1;
1432	/** Physical Page number of the page. */
1433	unsigned u10PageNo : 10;
1434	} X86PDE4MBITS;
1435	/** Pointer to a page table entry. */
1436	typedef X86PDE4MBITS *PX86PDE4MBITS;
1437	/** Pointer to a const page table entry. */
1438	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1439
1440
1441	/**
1442	* 2MB PAE page directory entry.
1443	*/
1444	typedef struct X86PDE2MPAEBITS
1445	{
1446	/** Flags whether(=1) or not the page is present. */
1447	uint32_t u1Present : 1;
1448	/** Read(=0) / Write(=1) flag. */
1449	uint32_t u1Write : 1;
1450	/** User(=1) / Supervisor(=0) flag. */
1451	uint32_t u1User : 1;
1452	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1453	uint32_t u1WriteThru : 1;
1454	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1455	uint32_t u1CacheDisable : 1;
1456	/** Accessed flag.
1457	* Indicates that the page have been read or written to. */
1458	uint32_t u1Accessed : 1;
1459	/** Dirty flag.
1460	* Indicates that the page have been written to. */
1461	uint32_t u1Dirty : 1;
1462	/** Page size flag - always 1 for 2MB entries. */
1463	uint32_t u1Size : 1;
1464	/** Global flag. */
1465	uint32_t u1Global : 1;
1466	/** Available for use to system software. */
1467	uint32_t u3Available : 3;
1468	/** Reserved / If PAT enabled, bit 2 of the index. */
1469	uint32_t u1PAT : 1;
1470	/** Reserved. */
1471	uint32_t u9Reserved : 9;
1472	/** Physical Page number of the next level - Low part. Don't use! */
1473	uint32_t u10PageNoLow : 10;
1474	/** Physical Page number of the next level - High part. Don't use! */
1475	uint32_t u20PageNoHigh : 20;
1476	/** MBZ bits */
1477	uint32_t u11Reserved : 11;
1478	/** No Execute flag. */
1479	uint32_t u1NoExecute : 1;
1480	} X86PDE2MPAEBITS;
1481	/** Pointer to a 4MB PAE page table entry. */
1482	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1483	/** Pointer to a 4MB PAE page table entry. */
1484	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1485
1486	/** @} */
1487
1488	/**
1489	* Page directory entry.
1490	*/
1491	typedef union X86PDE
1492	{
1493	/** Unsigned integer view. */
1494	X86PGUINT u;
1495	/** Normal view. */
1496	X86PDEBITS n;
1497	/** 4MB view (big). */
1498	X86PDE4MBITS b;
1499	/** 8 bit unsigned integer view. */
1500	uint8_t au8[4];
1501	/** 16 bit unsigned integer view. */
1502	uint16_t au16[2];
1503	/** 32 bit unsigned integer view. */
1504	uint32_t au32[1];
1505	} X86PDE;
1506	/** Pointer to a page directory entry. */
1507	typedef X86PDE *PX86PDE;
1508	/** Pointer to a const page directory entry. */
1509	typedef const X86PDE *PCX86PDE;
1510
1511	/**
1512	* PAE page directory entry.
1513	*/
1514	typedef union X86PDEPAE
1515	{
1516	/** Unsigned integer view. */
1517	X86PGPAEUINT u;
1518	/** Normal view. */
1519	X86PDEPAEBITS n;
1520	/** 2MB page view (big). */
1521	X86PDE2MPAEBITS b;
1522	/** 8 bit unsigned integer view. */
1523	uint8_t au8[8];
1524	/** 16 bit unsigned integer view. */
1525	uint16_t au16[4];
1526	/** 32 bit unsigned integer view. */
1527	uint32_t au32[2];
1528	} X86PDEPAE;
1529	/** Pointer to a page directory entry. */
1530	typedef X86PDEPAE *PX86PDEPAE;
1531	/** Pointer to a const page directory entry. */
1532	typedef const X86PDEPAE *PCX86PDEPAE;
1533
1534	/**
1535	* Page directory.
1536	*/
1537	typedef struct X86PD
1538	{
1539	/** PDE Array. */
1540	X86PDE a[X86_PG_ENTRIES];
1541	} X86PD;
1542	/** Pointer to a page directory. */
1543	typedef X86PD *PX86PD;
1544	/** Pointer to a const page directory. */
1545	typedef const X86PD *PCX86PD;
1546
1547	/** The page shift to get the PD index. */
1548	#define X86_PD_SHIFT 22
1549	/** The PD index mask (apply to a shifted page address). */
1550	#define X86_PD_MASK 0x3ff
1551
1552
1553	/**
1554	* PAE page directory.
1555	*/
1556	typedef struct X86PDPAE
1557	{
1558	/** PDE Array. */
1559	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1560	} X86PDPAE;
1561	/** Pointer to a PAE page directory. */
1562	typedef X86PDPAE *PX86PDPAE;
1563	/** Pointer to a const PAE page directory. */
1564	typedef const X86PDPAE *PCX86PDPAE;
1565
1566	/** The page shift to get the PAE PD index. */
1567	#define X86_PD_PAE_SHIFT 21
1568	/** The PAE PD index mask (apply to a shifted page address). */
1569	#define X86_PD_PAE_MASK 0x1ff
1570
1571
1572	/** @name Page Directory Pointer Table Entry (PAE)
1573	* @{
1574	*/
1575	/** Bit 0 - P - Present bit. */
1576	#define X86_PDPE_P RT_BIT(0)
1577	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1578	#define X86_PDPE_RW RT_BIT(1)
1579	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1580	#define X86_PDPE_US RT_BIT(2)
1581	/** Bit 3 - PWT - Page level write thru bit. */
1582	#define X86_PDPE_PWT RT_BIT(3)
1583	/** Bit 4 - PCD - Page level cache disable bit. */
1584	#define X86_PDPE_PCD RT_BIT(4)
1585	/** Bit 5 - A - Access bit. Long Mode only. */
1586	#define X86_PDPE_A RT_BIT(5)
1587	/** Bits 9-11 - - Available for use to system software. */
1588	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1589	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1590	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1591	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1592	/** @todo Get rid of the above hack; makes code unreadable. */
1593	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1594	#else
1595	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1596	#endif
1597	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1598	#define X86_PDPE_NX RT_BIT_64(63)
1599
1600	/**
1601	* Page directory pointer table entry.
1602	*/
1603	typedef struct X86PDPEBITS
1604	{
1605	/** Flags whether(=1) or not the page is present. */
1606	uint32_t u1Present : 1;
1607	/** Chunk of reserved bits. */
1608	uint32_t u2Reserved : 2;
1609	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1610	uint32_t u1WriteThru : 1;
1611	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1612	uint32_t u1CacheDisable : 1;
1613	/** Chunk of reserved bits. */
1614	uint32_t u4Reserved : 4;
1615	/** Available for use to system software. */
1616	uint32_t u3Available : 3;
1617	/** Physical Page number of the next level - Low Part. Don't use! */
1618	uint32_t u20PageNoLow : 20;
1619	/** Physical Page number of the next level - High Part. Don't use! */
1620	uint32_t u20PageNoHigh : 20;
1621	/** MBZ bits */
1622	uint32_t u12Reserved : 12;
1623	} X86PDPEBITS;
1624	/** Pointer to a page directory pointer table entry. */
1625	typedef X86PDPEBITS *PX86PTPEBITS;
1626	/** Pointer to a const page directory pointer table entry. */
1627	typedef const X86PDPEBITS *PCX86PTPEBITS;
1628
1629	/**
1630	* Page directory pointer table entry. AMD64 version
1631	*/
1632	typedef struct X86PDPEAMD64BITS
1633	{
1634	/** Flags whether(=1) or not the page is present. */
1635	uint32_t u1Present : 1;
1636	/** Read(=0) / Write(=1) flag. */
1637	uint32_t u1Write : 1;
1638	/** User(=1) / Supervisor (=0) flag. */
1639	uint32_t u1User : 1;
1640	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1641	uint32_t u1WriteThru : 1;
1642	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1643	uint32_t u1CacheDisable : 1;
1644	/** Accessed flag.
1645	* Indicates that the page have been read or written to. */
1646	uint32_t u1Accessed : 1;
1647	/** Chunk of reserved bits. */
1648	uint32_t u3Reserved : 3;
1649	/** Available for use to system software. */
1650	uint32_t u3Available : 3;
1651	/** Physical Page number of the next level - Low Part. Don't use! */
1652	uint32_t u20PageNoLow : 20;
1653	/** Physical Page number of the next level - High Part. Don't use! */
1654	uint32_t u20PageNoHigh : 20;
1655	/** MBZ bits */
1656	uint32_t u11Reserved : 11;
1657	/** No Execute flag. */
1658	uint32_t u1NoExecute : 1;
1659	} X86PDPEAMD64BITS;
1660	/** Pointer to a page directory pointer table entry. */
1661	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1662	/** Pointer to a const page directory pointer table entry. */
1663	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1664
1665	/**
1666	* Page directory pointer table entry.
1667	*/
1668	typedef union X86PDPE
1669	{
1670	/** Unsigned integer view. */
1671	X86PGPAEUINT u;
1672	/** Normal view. */
1673	X86PDPEBITS n;
1674	/** AMD64 view. */
1675	X86PDPEAMD64BITS lm;
1676	/** 8 bit unsigned integer view. */
1677	uint8_t au8[8];
1678	/** 16 bit unsigned integer view. */
1679	uint16_t au16[4];
1680	/** 32 bit unsigned integer view. */
1681	uint32_t au32[2];
1682	} X86PDPE;
1683	/** Pointer to a page directory pointer table entry. */
1684	typedef X86PDPE *PX86PDPE;
1685	/** Pointer to a const page directory pointer table entry. */
1686	typedef const X86PDPE *PCX86PDPE;
1687
1688
1689	/**
1690	* Page directory pointer table.
1691	*/
1692	typedef struct X86PDPT
1693	{
1694	/** PDE Array. */
1695	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1696	} X86PDPT;
1697	/** Pointer to a page directory pointer table. */
1698	typedef X86PDPT *PX86PDPT;
1699	/** Pointer to a const page directory pointer table. */
1700	typedef const X86PDPT *PCX86PDPT;
1701
1702	/** The page shift to get the PDPT index. */
1703	#define X86_PDPT_SHIFT 30
1704	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1705	#define X86_PDPT_MASK_PAE 0x3
1706	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1707	#define X86_PDPT_MASK_AMD64 0x1ff
1708
1709	/** @} */
1710
1711
1712	/** @name Page Map Level-4 Entry (Long Mode PAE)
1713	* @{
1714	*/
1715	/** Bit 0 - P - Present bit. */
1716	#define X86_PML4E_P RT_BIT(0)
1717	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1718	#define X86_PML4E_RW RT_BIT(1)
1719	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1720	#define X86_PML4E_US RT_BIT(2)
1721	/** Bit 3 - PWT - Page level write thru bit. */
1722	#define X86_PML4E_PWT RT_BIT(3)
1723	/** Bit 4 - PCD - Page level cache disable bit. */
1724	#define X86_PML4E_PCD RT_BIT(4)
1725	/** Bit 5 - A - Access bit. */
1726	#define X86_PML4E_A RT_BIT(5)
1727	/** Bits 9-11 - - Available for use to system software. */
1728	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1729	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1730	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1731	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1732	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1733	#else
1734	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1735	#endif
1736	/** Bits 63 - NX - PAE - No execution flag. */
1737	#define X86_PML4E_NX RT_BIT_64(63)
1738
1739	/**
1740	* Page Map Level-4 Entry
1741	*/
1742	typedef struct X86PML4EBITS
1743	{
1744	/** Flags whether(=1) or not the page is present. */
1745	uint32_t u1Present : 1;
1746	/** Read(=0) / Write(=1) flag. */
1747	uint32_t u1Write : 1;
1748	/** User(=1) / Supervisor (=0) flag. */
1749	uint32_t u1User : 1;
1750	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1751	uint32_t u1WriteThru : 1;
1752	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1753	uint32_t u1CacheDisable : 1;
1754	/** Accessed flag.
1755	* Indicates that the page have been read or written to. */
1756	uint32_t u1Accessed : 1;
1757	/** Chunk of reserved bits. */
1758	uint32_t u3Reserved : 3;
1759	/** Available for use to system software. */
1760	uint32_t u3Available : 3;
1761	/** Physical Page number of the next level - Low Part. Don't use! */
1762	uint32_t u20PageNoLow : 20;
1763	/** Physical Page number of the next level - High Part. Don't use! */
1764	uint32_t u20PageNoHigh : 20;
1765	/** MBZ bits */
1766	uint32_t u11Reserved : 11;
1767	/** No Execute flag. */
1768	uint32_t u1NoExecute : 1;
1769	} X86PML4EBITS;
1770	/** Pointer to a page map level-4 entry. */
1771	typedef X86PML4EBITS *PX86PML4EBITS;
1772	/** Pointer to a const page map level-4 entry. */
1773	typedef const X86PML4EBITS *PCX86PML4EBITS;
1774
1775	/**
1776	* Page Map Level-4 Entry.
1777	*/
1778	typedef union X86PML4E
1779	{
1780	/** Unsigned integer view. */
1781	X86PGPAEUINT u;
1782	/** Normal view. */
1783	X86PML4EBITS n;
1784	/** 8 bit unsigned integer view. */
1785	uint8_t au8[8];
1786	/** 16 bit unsigned integer view. */
1787	uint16_t au16[4];
1788	/** 32 bit unsigned integer view. */
1789	uint32_t au32[2];
1790	} X86PML4E;
1791	/** Pointer to a page map level-4 entry. */
1792	typedef X86PML4E *PX86PML4E;
1793	/** Pointer to a const page map level-4 entry. */
1794	typedef const X86PML4E *PCX86PML4E;
1795
1796
1797	/**
1798	* Page Map Level-4.
1799	*/
1800	typedef struct X86PML4
1801	{
1802	/** PDE Array. */
1803	X86PML4E a[X86_PG_PAE_ENTRIES];
1804	} X86PML4;
1805	/** Pointer to a page map level-4. */
1806	typedef X86PML4 *PX86PML4;
1807	/** Pointer to a const page map level-4. */
1808	typedef const X86PML4 *PCX86PML4;
1809
1810	/** The page shift to get the PML4 index. */
1811	#define X86_PML4_SHIFT 39
1812	/** The PML4 index mask (apply to a shifted page address). */
1813	#define X86_PML4_MASK 0x1ff
1814
1815	/** @} */
1816
1817	/** @} */
1818
1819
1820	/**
1821	* 80-bit MMX/FPU register type.
1822	*/
1823	typedef struct X86FPUMMX
1824	{
1825	uint8_t reg[10];
1826	} X86FPUMMX;
1827	/** Pointer to a 80-bit MMX/FPU register type. */
1828	typedef X86FPUMMX *PX86FPUMMX;
1829	/** Pointer to a const 80-bit MMX/FPU register type. */
1830	typedef const X86FPUMMX *PCX86FPUMMX;
1831
1832	/**
1833	* FPU state (aka FSAVE/FRSTOR Memory Region).
1834	*/
1835	#pragma pack(1)
1836	typedef struct X86FPUSTATE
1837	{
1838	/** Control word. */
1839	uint16_t FCW;
1840	/** Alignment word */
1841	uint16_t Dummy1;
1842	/** Status word. */
1843	uint16_t FSW;
1844	/** Alignment word */
1845	uint16_t Dummy2;
1846	/** Tag word */
1847	uint16_t FTW;
1848	/** Alignment word */
1849	uint16_t Dummy3;
1850
1851	/** Instruction pointer. */
1852	uint32_t FPUIP;
1853	/** Code selector. */
1854	uint16_t CS;
1855	/** Opcode. */
1856	uint16_t FOP;
1857	/** FOO. */
1858	uint32_t FPUOO;
1859	/** FOS. */
1860	uint32_t FPUOS;
1861	/** FPU view - todo. */
1862	X86FPUMMX regs[8];
1863	} X86FPUSTATE;
1864	#pragma pack()
1865	/** Pointer to a FPU state. */
1866	typedef X86FPUSTATE *PX86FPUSTATE;
1867	/** Pointer to a const FPU state. */
1868	typedef const X86FPUSTATE *PCX86FPUSTATE;
1869
1870	/**
1871	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1872	*/
1873	#pragma pack(1)
1874	typedef struct X86FXSTATE
1875	{
1876	/** Control word. */
1877	uint16_t FCW;
1878	/** Status word. */
1879	uint16_t FSW;
1880	/** Tag word (it's a byte actually). */
1881	uint8_t FTW;
1882	uint8_t huh1;
1883	/** Opcode. */
1884	uint16_t FOP;
1885	/** Instruction pointer. */
1886	uint32_t FPUIP;
1887	/** Code selector. */
1888	uint16_t CS;
1889	uint16_t Rsvrd1;
1890	/* - offset 16 - */
1891	/** Data pointer. */
1892	uint32_t FPUDP;
1893	/** Data segment */
1894	uint16_t DS;
1895	uint16_t Rsrvd2;
1896	uint32_t MXCSR;
1897	uint32_t MXCSR_MASK;
1898	/* - offset 32 - */
1899	union
1900	{
1901	/** MMX view. */
1902	uint64_t mmx;
1903	/** FPU view - todo. */
1904	X86FPUMMX fpu;
1905	/** 8-bit view. */
1906	uint8_t au8[16];
1907	/** 16-bit view. */
1908	uint16_t au16[8];
1909	/** 32-bit view. */
1910	uint32_t au32[4];
1911	/** 64-bit view. */
1912	uint64_t au64[2];
1913	/** 128-bit view. (yeah, very helpful) */
1914	uint128_t au128[1];
1915	} aRegs[8];
1916	/* - offset 160 - */
1917	union
1918	{
1919	/** XMM Register view . /
1920	uint128_t xmm;
1921	/** 8-bit view. */
1922	uint8_t au8[16];
1923	/** 16-bit view. */
1924	uint16_t au16[8];
1925	/** 32-bit view. */
1926	uint32_t au32[4];
1927	/** 64-bit view. */
1928	uint64_t au64[2];
1929	/** 128-bit view. (yeah, very helpful) */
1930	uint128_t au128[1];
1931	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1932	/* - offset 416 - */
1933	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1934	} X86FXSTATE;
1935	#pragma pack()
1936	/** Pointer to a FPU Extended state. */
1937	typedef X86FXSTATE *PX86FXSTATE;
1938	/** Pointer to a const FPU Extended state. */
1939	typedef const X86FXSTATE *PCX86FXSTATE;
1940
1941
1942	/** @name Selector Descriptor
1943	* @{
1944	*/
1945
1946	/**
1947	* Descriptor attributes.
1948	*/
1949	typedef struct X86DESCATTRBITS
1950	{
1951	/** Segment Type. */
1952	unsigned u4Type : 4;
1953	/** Descriptor Type. System(=0) or code/data selector */
1954	unsigned u1DescType : 1;
1955	/** Descriptor Privelege level. */
1956	unsigned u2Dpl : 2;
1957	/** Flags selector present(=1) or not. */
1958	unsigned u1Present : 1;
1959	/** Segment limit 16-19. */
1960	unsigned u4LimitHigh : 4;
1961	/** Available for system software. */
1962	unsigned u1Available : 1;
1963	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1964	unsigned u1Long : 1;
1965	/** This flags meaning depends on the segment type. Try make sense out
1966	* of the intel manual yourself. */
1967	unsigned u1DefBig : 1;
1968	/** Granularity of the limit. If set 4KB granularity is used, if
1969	* clear byte. */
1970	unsigned u1Granularity : 1;
1971	} X86DESCATTRBITS;
1972
1973
1974	#pragma pack(1)
1975	typedef union X86DESCATTR
1976	{
1977	/** Unsigned integer view. */
1978	uint32_t u;
1979	/** Normal view. */
1980	X86DESCATTRBITS n;
1981	} X86DESCATTR;
1982	#pragma pack()
1983	/** Pointer to descriptor attributes. */
1984	typedef X86DESCATTR *PX86DESCATTR;
1985	/** Pointer to const descriptor attributes. */
1986	typedef const X86DESCATTR *PCX86DESCATTR;
1987
1988
1989	/**
1990	* Generic descriptor table entry
1991	*/
1992	#pragma pack(1)
1993	typedef struct X86DESCGENERIC
1994	{
1995	/** Limit - Low word. */
1996	unsigned u16LimitLow : 16;
1997	/** Base address - lowe word.
1998	* Don't try set this to 24 because MSC is doing stupid things then. */
1999	unsigned u16BaseLow : 16;
2000	/** Base address - first 8 bits of high word. */
2001	unsigned u8BaseHigh1 : 8;
2002	/** Segment Type. */
2003	unsigned u4Type : 4;
2004	/** Descriptor Type. System(=0) or code/data selector */
2005	unsigned u1DescType : 1;
2006	/** Descriptor Privelege level. */
2007	unsigned u2Dpl : 2;
2008	/** Flags selector present(=1) or not. */
2009	unsigned u1Present : 1;
2010	/** Segment limit 16-19. */
2011	unsigned u4LimitHigh : 4;
2012	/** Available for system software. */
2013	unsigned u1Available : 1;
2014	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2015	unsigned u1Long : 1;
2016	/** This flags meaning depends on the segment type. Try make sense out
2017	* of the intel manual yourself. */
2018	unsigned u1DefBig : 1;
2019	/** Granularity of the limit. If set 4KB granularity is used, if
2020	* clear byte. */
2021	unsigned u1Granularity : 1;
2022	/** Base address - highest 8 bits. */
2023	unsigned u8BaseHigh2 : 8;
2024	} X86DESCGENERIC;
2025	#pragma pack()
2026	/** Pointer to a generic descriptor entry. */
2027	typedef X86DESCGENERIC *PX86DESCGENERIC;
2028	/** Pointer to a const generic descriptor entry. */
2029	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2030
2031	/**
2032	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2033	*/
2034	typedef struct X86DESCGATE
2035	{
2036	/** Target code segment offset - Low word.
2037	* Ignored if task-gate. */
2038	unsigned u16OffsetLow : 16;
2039	/** Target code segment selector for call-, interrupt- and trap-gates,
2040	* TSS selector if task-gate. */
2041	unsigned u16Sel : 16;
2042	/** Number of parameters for a call-gate.
2043	* Ignored if interrupt-, trap- or task-gate. */
2044	unsigned u4ParmCount : 4;
2045	/** Reserved / ignored. */
2046	unsigned u4Reserved : 4;
2047	/** Segment Type. */
2048	unsigned u4Type : 4;
2049	/** Descriptor Type (0 = system). */
2050	unsigned u1DescType : 1;
2051	/** Descriptor Privelege level. */
2052	unsigned u2Dpl : 2;
2053	/** Flags selector present(=1) or not. */
2054	unsigned u1Present : 1;
2055	/** Target code segment offset - High word.
2056	* Ignored if task-gate. */
2057	unsigned u16OffsetHigh : 16;
2058	} X86DESCGATE;
2059	AssertCompileSize(X86DESCGATE, 8);
2060	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2061	typedef X86DESCGATE *PX86DESCGATE;
2062	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2063	typedef const X86DESCGATE *PCX86DESCGATE;
2064
2065	/**
2066	* Descriptor table entry.
2067	*/
2068	#pragma pack(1)
2069	typedef union X86DESC
2070	{
2071	/** Generic descriptor view. */
2072	X86DESCGENERIC Gen;
2073	/** Gate descriptor view. */
2074	X86DESCGATE Gate;
2075
2076	/** 8 bit unsigned interger view. */
2077	uint8_t au8[8];
2078	/** 16 bit unsigned interger view. */
2079	uint16_t au16[4];
2080	/** 32 bit unsigned interger view. */
2081	uint32_t au32[2];
2082	} X86DESC;
2083	AssertCompileSize(X86DESC, 8);
2084	#pragma pack()
2085	/** Pointer to descriptor table entry. */
2086	typedef X86DESC *PX86DESC;
2087	/** Pointer to const descriptor table entry. */
2088	typedef const X86DESC *PCX86DESC;
2089
2090	/** @def X86DESC_BASE
2091	* Return the base address of a descriptor.
2092	*/
2093	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2094	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2095	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2096	\| ( (desc).Gen.u16BaseLow ) )
2097
2098	/** @def X86DESC_LIMIT
2099	* Return the limit of a descriptor.
2100	*/
2101	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2102	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2103	\| ( (desc).Gen.u16LimitLow ) )
2104
2105	/**
2106	* 64 bits generic descriptor table entry
2107	* Note: most of these bits have no meaning in long mode.
2108	*/
2109	#pragma pack(1)
2110	typedef struct X86DESC64GENERIC
2111	{
2112	/** Limit - Low word - IGNORED. */
2113	unsigned u16LimitLow : 16;
2114	/** Base address - lowe word. - IGNORED
2115	* Don't try set this to 24 because MSC is doing stupid things then. */
2116	unsigned u16BaseLow : 16;
2117	/** Base address - first 8 bits of high word. - IGNORED */
2118	unsigned u8BaseHigh1 : 8;
2119	/** Segment Type. */
2120	unsigned u4Type : 4;
2121	/** Descriptor Type. System(=0) or code/data selector */
2122	unsigned u1DescType : 1;
2123	/** Descriptor Privelege level. */
2124	unsigned u2Dpl : 2;
2125	/** Flags selector present(=1) or not. */
2126	unsigned u1Present : 1;
2127	/** Segment limit 16-19. - IGNORED */
2128	unsigned u4LimitHigh : 4;
2129	/** Available for system software. - IGNORED */
2130	unsigned u1Available : 1;
2131	/** Long mode flag. */
2132	unsigned u1Long : 1;
2133	/** This flags meaning depends on the segment type. Try make sense out
2134	* of the intel manual yourself. */
2135	unsigned u1DefBig : 1;
2136	/** Granularity of the limit. If set 4KB granularity is used, if
2137	* clear byte. - IGNORED */
2138	unsigned u1Granularity : 1;
2139	/** Base address - highest 8 bits. - IGNORED */
2140	unsigned u8BaseHigh2 : 8;
2141	/** Base address - bits 63-32. */
2142	unsigned u32BaseHigh3 : 32;
2143	unsigned u8Reserved : 8;
2144	unsigned u5Zeros : 5;
2145	unsigned u19Reserved : 19;
2146	} X86DESC64GENERIC;
2147	#pragma pack()
2148	/** Pointer to a generic descriptor entry. */
2149	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2150	/** Pointer to a const generic descriptor entry. */
2151	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2152
2153	/**
2154	* System descriptor table entry (64 bits)
2155	*
2156	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2157	*/
2158	#pragma pack(1)
2159	typedef struct X86DESC64SYSTEM
2160	{
2161	/** Limit - Low word. */
2162	unsigned u16LimitLow : 16;
2163	/** Base address - lowe word.
2164	* Don't try set this to 24 because MSC is doing stupid things then. */
2165	unsigned u16BaseLow : 16;
2166	/** Base address - first 8 bits of high word. */
2167	unsigned u8BaseHigh1 : 8;
2168	/** Segment Type. */
2169	unsigned u4Type : 4;
2170	/** Descriptor Type. System(=0) or code/data selector */
2171	unsigned u1DescType : 1;
2172	/** Descriptor Privelege level. */
2173	unsigned u2Dpl : 2;
2174	/** Flags selector present(=1) or not. */
2175	unsigned u1Present : 1;
2176	/** Segment limit 16-19. */
2177	unsigned u4LimitHigh : 4;
2178	/** Available for system software. */
2179	unsigned u1Available : 1;
2180	/** Reserved - 0. */
2181	unsigned u1Reserved : 1;
2182	/** This flags meaning depends on the segment type. Try make sense out
2183	* of the intel manual yourself. */
2184	unsigned u1DefBig : 1;
2185	/** Granularity of the limit. If set 4KB granularity is used, if
2186	* clear byte. */
2187	unsigned u1Granularity : 1;
2188	/** Base address - bits 31-24. */
2189	unsigned u8BaseHigh2 : 8;
2190	/** Base address - bits 63-32. */
2191	unsigned u32BaseHigh3 : 32;
2192	unsigned u8Reserved : 8;
2193	unsigned u5Zeros : 5;
2194	unsigned u19Reserved : 19;
2195	} X86DESC64SYSTEM;
2196	#pragma pack()
2197	/** Pointer to a system descriptor entry. */
2198	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2199	/** Pointer to a const system descriptor entry. */
2200	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2201
2202	/**
2203	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2204	*/
2205	typedef struct X86DESC64GATE
2206	{
2207	/** Target code segment offset - Low word. */
2208	unsigned u16OffsetLow : 16;
2209	/** Target code segment selector. */
2210	unsigned u16Sel : 16;
2211	/** Interrupt stack table for interrupt- and trap-gates.
2212	* Ignored by call-gates. */
2213	unsigned u3IST : 3;
2214	/** Reserved / ignored. */
2215	unsigned u5Reserved : 5;
2216	/** Segment Type. */
2217	unsigned u4Type : 4;
2218	/** Descriptor Type (0 = system). */
2219	unsigned u1DescType : 1;
2220	/** Descriptor Privelege level. */
2221	unsigned u2Dpl : 2;
2222	/** Flags selector present(=1) or not. */
2223	unsigned u1Present : 1;
2224	/** Target code segment offset - High word.
2225	* Ignored if task-gate. */
2226	unsigned u16OffsetHigh : 16;
2227	/** Target code segment offset - Top dword.
2228	* Ignored if task-gate. */
2229	unsigned u32OffsetTop : 32;
2230	/** Reserved / ignored / must be zero.
2231	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2232	unsigned u32Reserved : 32;
2233	} X86DESC64GATE;
2234	AssertCompileSize(X86DESC64GATE, 16);
2235	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2236	typedef X86DESC64GATE *PX86DESC64GATE;
2237	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2238	typedef const X86DESC64GATE *PCX86DESC64GATE;
2239
2240
2241	/**
2242	* Descriptor table entry.
2243	*/
2244	#pragma pack(1)
2245	typedef union X86DESC64
2246	{
2247	/** Generic descriptor view. */
2248	X86DESC64GENERIC Gen;
2249	/** System descriptor view. */
2250	X86DESC64SYSTEM System;
2251	/** Gate descriptor view. */
2252	X86DESC64GATE Gate;
2253
2254	/** 8 bit unsigned interger view. */
2255	uint8_t au8[16];
2256	/** 16 bit unsigned interger view. */
2257	uint16_t au16[8];
2258	/** 32 bit unsigned interger view. */
2259	uint32_t au32[4];
2260	/** 64 bit unsigned interger view. */
2261	uint64_t au64[2];
2262	} X86DESC64;
2263	AssertCompileSize(X86DESC64, 16);
2264	#pragma pack()
2265	/** Pointer to descriptor table entry. */
2266	typedef X86DESC64 *PX86DESC64;
2267	/** Pointer to const descriptor table entry. */
2268	typedef const X86DESC64 *PCX86DESC64;
2269
2270	/** @def X86DESC64_BASE
2271	* Return the base of a 64-bit descriptor.
2272	*/
2273	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2274	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2275	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2276	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2277	\| ( (desc).Gen.u16BaseLow ) )
2278
2279
2280
2281	/** @name Host system descriptor table entry - Use with care!
2282	* @{ */
2283	/** Host system descriptor table entry. */
2284	#if HC_ARCH_BITS == 64
2285	typedef X86DESC64 X86DESCHC;
2286	#else
2287	typedef X86DESC X86DESCHC;
2288	#endif
2289	/** Pointer to a host system descriptor table entry. */
2290	#if HC_ARCH_BITS == 64
2291	typedef PX86DESC64 PX86DESCHC;
2292	#else
2293	typedef PX86DESC PX86DESCHC;
2294	#endif
2295	/** Pointer to a const host system descriptor table entry. */
2296	#if HC_ARCH_BITS == 64
2297	typedef PCX86DESC64 PCX86DESCHC;
2298	#else
2299	typedef PCX86DESC PCX86DESCHC;
2300	#endif
2301	/** @} */
2302
2303
2304	/** @name Selector Descriptor Types.
2305	* @{
2306	*/
2307
2308	/** @name Non-System Selector Types.
2309	* @{ */
2310	/** Code(=set)/Data(=clear) bit. */
2311	#define X86_SEL_TYPE_CODE 8
2312	/** Memory(=set)/System(=clear) bit. */
2313	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2314	/** Accessed bit. */
2315	#define X86_SEL_TYPE_ACCESSED 1
2316	/** Expand down bit (for data selectors only). */
2317	#define X86_SEL_TYPE_DOWN 4
2318	/** Conforming bit (for code selectors only). */
2319	#define X86_SEL_TYPE_CONF 4
2320	/** Write bit (for data selectors only). */
2321	#define X86_SEL_TYPE_WRITE 2
2322	/** Read bit (for code selectors only). */
2323	#define X86_SEL_TYPE_READ 2
2324
2325	/** Read only selector type. */
2326	#define X86_SEL_TYPE_RO 0
2327	/** Accessed read only selector type. */
2328	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2329	/** Read write selector type. */
2330	#define X86_SEL_TYPE_RW 2
2331	/** Accessed read write selector type. */
2332	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2333	/** Expand down read only selector type. */
2334	#define X86_SEL_TYPE_RO_DOWN 4
2335	/** Accessed expand down read only selector type. */
2336	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2337	/** Expand down read write selector type. */
2338	#define X86_SEL_TYPE_RW_DOWN 6
2339	/** Accessed expand down read write selector type. */
2340	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2341	/** Execute only selector type. */
2342	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2343	/** Accessed execute only selector type. */
2344	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2345	/** Execute and read selector type. */
2346	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2347	/** Accessed execute and read selector type. */
2348	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2349	/** Conforming execute only selector type. */
2350	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2351	/** Accessed Conforming execute only selector type. */
2352	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2353	/** Conforming execute and write selector type. */
2354	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2355	/** Accessed Conforming execute and write selector type. */
2356	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2357	/** @} */
2358
2359
2360	/** @name System Selector Types.
2361	* @{ */
2362	/** Undefined system selector type. */
2363	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2364	/** 286 TSS selector. */
2365	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2366	/** LDT selector. */
2367	#define X86_SEL_TYPE_SYS_LDT 2
2368	/** 286 TSS selector - Busy. */
2369	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2370	/** 286 Callgate selector. */
2371	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2372	/** Taskgate selector. */
2373	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2374	/** 286 Interrupt gate selector. */
2375	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2376	/** 286 Trapgate selector. */
2377	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2378	/** Undefined system selector. */
2379	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2380	/** 386 TSS selector. */
2381	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2382	/** Undefined system selector. */
2383	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2384	/** 386 TSS selector - Busy. */
2385	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2386	/** 386 Callgate selector. */
2387	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2388	/** Undefined system selector. */
2389	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2390	/** 386 Interruptgate selector. */
2391	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2392	/** 386 Trapgate selector. */
2393	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2394	/** @} */
2395
2396	/** @name AMD64 System Selector Types.
2397	* @{ */
2398	#define AMD64_SEL_TYPE_SYS_LDT 2
2399	/** 286 TSS selector - Busy. */
2400	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2401	/** 386 TSS selector - Busy. */
2402	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2403	/** 386 Callgate selector. */
2404	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2405	/** 386 Interruptgate selector. */
2406	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2407	/** 386 Trapgate selector. */
2408	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2409	/** @} */
2410
2411	/** @} */
2412
2413
2414	/** @name Descriptor Table Entry Flag Masks.
2415	* These are for the 2nd 32-bit word of a descriptor.
2416	* @{ */
2417	/** Bits 8-11 - TYPE - Descriptor type mask. */
2418	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2419	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2420	#define X86_DESC_S RT_BIT(12)
2421	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2422	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2423	/** Bit 15 - P - Present. */
2424	#define X86_DESC_P RT_BIT(15)
2425	/** Bit 20 - AVL - Available for system software. */
2426	#define X86_DESC_AVL RT_BIT(20)
2427	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2428	#define X86_DESC_DB RT_BIT(22)
2429	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2430	* used, if clear byte. */
2431	#define X86_DESC_G RT_BIT(23)
2432	/** @} */
2433
2434	/** @} */
2435
2436	/** @name Task segment.
2437	* @{
2438	*/
2439	#pragma pack(1)
2440	typedef struct X86TSS32
2441	{
2442	/** Back link to previous task. (static) */
2443	RTSEL selPrev;
2444	uint16_t padding1;
2445	/** Ring-0 stack pointer. (static) */
2446	uint32_t esp0;
2447	/** Ring-0 stack segment. (static) */
2448	RTSEL ss0;
2449	uint16_t padding_ss0;
2450	/** Ring-1 stack pointer. (static) */
2451	uint32_t esp1;
2452	/** Ring-1 stack segment. (static) */
2453	RTSEL ss1;
2454	uint16_t padding_ss1;
2455	/** Ring-2 stack pointer. (static) */
2456	uint32_t esp2;
2457	/** Ring-2 stack segment. (static) */
2458	RTSEL ss2;
2459	uint16_t padding_ss2;
2460	/** Page directory for the task. (static) */
2461	uint32_t cr3;
2462	/** EIP before task switch. */
2463	uint32_t eip;
2464	/** EFLAGS before task switch. */
2465	uint32_t eflags;
2466	/** EAX before task switch. */
2467	uint32_t eax;
2468	/** ECX before task switch. */
2469	uint32_t ecx;
2470	/** EDX before task switch. */
2471	uint32_t edx;
2472	/** EBX before task switch. */
2473	uint32_t ebx;
2474	/** ESP before task switch. */
2475	uint32_t esp;
2476	/** EBP before task switch. */
2477	uint32_t ebp;
2478	/** ESI before task switch. */
2479	uint32_t esi;
2480	/** EDI before task switch. */
2481	uint32_t edi;
2482	/** ES before task switch. */
2483	RTSEL es;
2484	uint16_t padding_es;
2485	/** CS before task switch. */
2486	RTSEL cs;
2487	uint16_t padding_cs;
2488	/** SS before task switch. */
2489	RTSEL ss;
2490	uint16_t padding_ss;
2491	/** DS before task switch. */
2492	RTSEL ds;
2493	uint16_t padding_ds;
2494	/** FS before task switch. */
2495	RTSEL fs;
2496	uint16_t padding_fs;
2497	/** GS before task switch. */
2498	RTSEL gs;
2499	uint16_t padding_gs;
2500	/** LDTR before task switch. */
2501	RTSEL selLdt;
2502	uint16_t padding_ldt;
2503	/** Debug trap flag */
2504	uint16_t fDebugTrap;
2505	/** Offset relative to the TSS of the start of the I/O Bitmap
2506	* and the end of the interrupt redirection bitmap. */
2507	uint16_t offIoBitmap;
2508	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2509	uint8_t IntRedirBitmap[32];
2510	} X86TSS32;
2511	#pragma pack()
2512	/** Pointer to task segment. */
2513	typedef X86TSS32 *PX86TSS32;
2514	/** Pointer to const task segment. */
2515	typedef const X86TSS32 *PCX86TSS32;
2516	/** @} */
2517
2518
2519	/** @name 64 bits Task segment.
2520	* @{
2521	*/
2522	#pragma pack(1)
2523	typedef struct X86TSS64
2524	{
2525	/** Reserved. */
2526	uint32_t u32Reserved;
2527	/** Ring-0 stack pointer. (static) */
2528	uint64_t rsp0;
2529	/** Ring-1 stack pointer. (static) */
2530	uint64_t rsp1;
2531	/** Ring-2 stack pointer. (static) */
2532	uint64_t rsp2;
2533	/** Reserved. */
2534	uint32_t u32Reserved2[2];
2535	/* IST */
2536	uint64_t ist1;
2537	uint64_t ist2;
2538	uint64_t ist3;
2539	uint64_t ist4;
2540	uint64_t ist5;
2541	uint64_t ist6;
2542	uint64_t ist7;
2543	/* Reserved. */
2544	uint16_t u16Reserved[5];
2545	/** Offset relative to the TSS of the start of the I/O Bitmap
2546	* and the end of the interrupt redirection bitmap. */
2547	uint16_t offIoBitmap;
2548	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2549	uint8_t IntRedirBitmap[32];
2550	} X86TSS64;
2551	#pragma pack()
2552	/** Pointer to task segment. */
2553	typedef X86TSS64 *PX86TSS64;
2554	/** Pointer to const task segment. */
2555	typedef const X86TSS64 *PCX86TSS64;
2556	AssertCompileSize(X86TSS64, 136);
2557
2558	/** @} */
2559
2560
2561	/** @name Selectors.
2562	* @{
2563	*/
2564
2565	/**
2566	* The shift used to convert a selector from and to index an index (C).
2567	*/
2568	#define X86_SEL_SHIFT 3
2569
2570	/**
2571	* The mask used to mask off the table indicator and CPL of an selector.
2572	*/
2573	#define X86_SEL_MASK 0xfff8
2574
2575	/**
2576	* The bit indicating that a selector is in the LDT and not in the GDT.
2577	*/
2578	#define X86_SEL_LDT 0x0004
2579	/**
2580	* The bit mask for getting the RPL of a selector.
2581	*/
2582	#define X86_SEL_RPL 0x0003
2583
2584	/** @} */
2585
2586
2587	/**
2588	* x86 Exceptions/Faults/Traps.
2589	*/
2590	typedef enum X86XCPT
2591	{
2592	/** \#DE - Divide error. */
2593	X86_XCPT_DE = 0x00,
2594	/** \#DB - Debug event (single step, DRx, ..) */
2595	X86_XCPT_DB = 0x01,
2596	/** NMI - Non-Maskable Interrupt */
2597	X86_XCPT_NMI = 0x02,
2598	/** \#BP - Breakpoint (INT3). */
2599	X86_XCPT_BP = 0x03,
2600	/** \#OF - Overflow (INTO). */
2601	X86_XCPT_OF = 0x04,
2602	/** \#BR - Bound range exceeded (BOUND). */
2603	X86_XCPT_BR = 0x05,
2604	/** \#UD - Undefined opcode. */
2605	X86_XCPT_UD = 0x06,
2606	/** \#NM - Device not available (math coprocessor device). */
2607	X86_XCPT_NM = 0x07,
2608	/** \#DF - Double fault. */
2609	X86_XCPT_DF = 0x08,
2610	/** ??? - Coprocessor segment overrun (obsolete). */
2611	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2612	/** \#TS - Taskswitch (TSS). */
2613	X86_XCPT_TS = 0x0a,
2614	/** \#NP - Segment no present. */
2615	X86_XCPT_NP = 0x0b,
2616	/** \#SS - Stack segment fault. */
2617	X86_XCPT_SS = 0x0c,
2618	/** \#GP - General protection fault. */
2619	X86_XCPT_GP = 0x0d,
2620	/** \#PF - Page fault. */
2621	X86_XCPT_PF = 0x0e,
2622	/* 0x0f is reserved. */
2623	/** \#MF - Math fault (FPU). */
2624	X86_XCPT_MF = 0x10,
2625	/** \#AC - Alignment check. */
2626	X86_XCPT_AC = 0x11,
2627	/** \#MC - Machine check. */
2628	X86_XCPT_MC = 0x12,
2629	/** \#XF - SIMD Floating-Pointer Exception. */
2630	X86_XCPT_XF = 0x13
2631	} X86XCPT;
2632	/** Pointer to a x86 exception code. */
2633	typedef X86XCPT *PX86XCPT;
2634	/** Pointer to a const x86 exception code. */
2635	typedef const X86XCPT *PCX86XCPT;
2636
2637
2638	/** @name Trap Error Codes
2639	* @{
2640	*/
2641	/** External indicator. */
2642	#define X86_TRAP_ERR_EXTERNAL 1
2643	/** IDT indicator. */
2644	#define X86_TRAP_ERR_IDT 2
2645	/** Descriptor table indicator - If set LDT, if clear GDT. */
2646	#define X86_TRAP_ERR_TI 4
2647	/** Mask for getting the selector. */
2648	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2649	/** Shift for getting the selector table index (C type index). */
2650	#define X86_TRAP_ERR_SEL_SHIFT 3
2651	/** @} */
2652
2653
2654	/** @name \#PF Trap Error Codes
2655	* @{
2656	*/
2657	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2658	#define X86_TRAP_PF_P RT_BIT(0)
2659	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2660	#define X86_TRAP_PF_RW RT_BIT(1)
2661	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2662	#define X86_TRAP_PF_US RT_BIT(2)
2663	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2664	#define X86_TRAP_PF_RSVD RT_BIT(3)
2665	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2666	#define X86_TRAP_PF_ID RT_BIT(4)
2667	/** @} */
2668
2669	#pragma pack(1)
2670	/**
2671	* 32-bit IDTR/GDTR.
2672	*/
2673	typedef struct X86XDTR32
2674	{
2675	/** Size of the descriptor table. */
2676	uint16_t cb;
2677	/** Address of the descriptor table. */
2678	uint32_t uAddr;
2679	} X86XDTR32, *PX86XDTR32;
2680	#pragma pack()
2681
2682	#pragma pack(1)
2683	/**
2684	* 64-bit IDTR/GDTR.
2685	*/
2686	typedef struct X86XDTR64
2687	{
2688	/** Size of the descriptor table. */
2689	uint16_t cb;
2690	/** Address of the descriptor table. */
2691	uint64_t uAddr;
2692	} X86XDTR64, *PX86XDTR64;
2693	#pragma pack()
2694
2695	/** @} */
2696
2697	#endif
2698

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source: vbox/trunk/include/VBox/x86.h@ 24281

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