x86.h@ 27459

Last change on this file since 27459 was 27395, checked in by vboxsync, 15 years ago
Added performance counter MSRs
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1	/** @file
2	* X86 (and AMD64) Structures and Definitions (VMM,++).
3	*
4	* x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*
27	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
28	* Clara, CA 95054 USA or visit http://www.sun.com if you need
29	* additional information or have any questions.
30	*/
31
32	#ifndef ___VBox_x86_h
33	#define ___VBox_x86_h
34
35	#include <VBox/types.h>
36	#include <iprt/assert.h>
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_x86 x86 Types and Definitions
45	* @{
46	*/
47
48	/**
49	* EFLAGS Bits.
50	*/
51	typedef struct X86EFLAGSBITS
52	{
53	/** Bit 0 - CF - Carry flag - Status flag. */
54	unsigned u1CF : 1;
55	/** Bit 1 - 1 - Reserved flag. */
56	unsigned u1Reserved0 : 1;
57	/** Bit 2 - PF - Parity flag - Status flag. */
58	unsigned u1PF : 1;
59	/** Bit 3 - 0 - Reserved flag. */
60	unsigned u1Reserved1 : 1;
61	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
62	unsigned u1AF : 1;
63	/** Bit 5 - 0 - Reserved flag. */
64	unsigned u1Reserved2 : 1;
65	/** Bit 6 - ZF - Zero flag - Status flag. */
66	unsigned u1ZF : 1;
67	/** Bit 7 - SF - Signed flag - Status flag. */
68	unsigned u1SF : 1;
69	/** Bit 8 - TF - Trap flag - System flag. */
70	unsigned u1TF : 1;
71	/** Bit 9 - IF - Interrupt flag - System flag. */
72	unsigned u1IF : 1;
73	/** Bit 10 - DF - Direction flag - Control flag. */
74	unsigned u1DF : 1;
75	/** Bit 11 - OF - Overflow flag - Status flag. */
76	unsigned u1OF : 1;
77	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
78	unsigned u2IOPL : 2;
79	/** Bit 14 - NT - Nested task flag - System flag. */
80	unsigned u1NT : 1;
81	/** Bit 15 - 0 - Reserved flag. */
82	unsigned u1Reserved3 : 1;
83	/** Bit 16 - RF - Resume flag - System flag. */
84	unsigned u1RF : 1;
85	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
86	unsigned u1VM : 1;
87	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
88	unsigned u1AC : 1;
89	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
90	unsigned u1VIF : 1;
91	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
92	unsigned u1VIP : 1;
93	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
94	unsigned u1ID : 1;
95	/** Bit 22-31 - 0 - Reserved flag. */
96	unsigned u10Reserved4 : 10;
97	} X86EFLAGSBITS;
98	/** Pointer to EFLAGS bits. */
99	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
100	/** Pointer to const EFLAGS bits. */
101	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
102
103	/**
104	* EFLAGS.
105	*/
106	typedef union X86EFLAGS
107	{
108	/** The plain unsigned view. */
109	uint32_t u;
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	} X86EFLAGS;
121	/** Pointer to EFLAGS. */
122	typedef X86EFLAGS *PX86EFLAGS;
123	/** Pointer to const EFLAGS. */
124	typedef const X86EFLAGS *PCX86EFLAGS;
125
126	/**
127	* RFLAGS (32 upper bits are reserved).
128	*/
129	typedef union X86RFLAGS
130	{
131	/** The plain unsigned view. */
132	uint64_t u;
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	} X86RFLAGS;
146	/** Pointer to RFLAGS. */
147	typedef X86RFLAGS *PX86RFLAGS;
148	/** Pointer to const RFLAGS. */
149	typedef const X86RFLAGS *PCX86RFLAGS;
150
151
152	/** @name EFLAGS
153	* @{
154	*/
155	/** Bit 0 - CF - Carry flag - Status flag. */
156	#define X86_EFL_CF RT_BIT(0)
157	/** Bit 2 - PF - Parity flag - Status flag. */
158	#define X86_EFL_PF RT_BIT(2)
159	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
160	#define X86_EFL_AF RT_BIT(4)
161	/** Bit 6 - ZF - Zero flag - Status flag. */
162	#define X86_EFL_ZF RT_BIT(6)
163	/** Bit 7 - SF - Signed flag - Status flag. */
164	#define X86_EFL_SF RT_BIT(7)
165	/** Bit 8 - TF - Trap flag - System flag. */
166	#define X86_EFL_TF RT_BIT(8)
167	/** Bit 9 - IF - Interrupt flag - System flag. */
168	#define X86_EFL_IF RT_BIT(9)
169	/** Bit 10 - DF - Direction flag - Control flag. */
170	#define X86_EFL_DF RT_BIT(10)
171	/** Bit 11 - OF - Overflow flag - Status flag. */
172	#define X86_EFL_OF RT_BIT(11)
173	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
174	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
175	/** Bit 14 - NT - Nested task flag - System flag. */
176	#define X86_EFL_NT RT_BIT(14)
177	/** Bit 16 - RF - Resume flag - System flag. */
178	#define X86_EFL_RF RT_BIT(16)
179	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
180	#define X86_EFL_VM RT_BIT(17)
181	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
182	#define X86_EFL_AC RT_BIT(18)
183	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
184	#define X86_EFL_VIF RT_BIT(19)
185	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
186	#define X86_EFL_VIP RT_BIT(20)
187	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
188	#define X86_EFL_ID RT_BIT(21)
189	/** IOPL shift. */
190	#define X86_EFL_IOPL_SHIFT 12
191	/** The the IOPL level from the flags. */
192	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
193	/** Bits restored by popf */
194	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u1Reserved1 : 1;
207	/** Bit 2 - DS Area 64-bit layout. */
208	unsigned u1DTE64 : 1;
209	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
210	unsigned u1Monitor : 1;
211	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
212	unsigned u1CPLDS : 1;
213	/** Bit 5 - VMX - Virtual Machine Technology. */
214	unsigned u1VMX : 1;
215	/** Bit 6 - SMX: Safer Mode Extensions. */
216	unsigned u1SMX : 1;
217	/** Bit 7 - EST - Enh. SpeedStep Tech. */
218	unsigned u1EST : 1;
219	/** Bit 8 - TM2 - Terminal Monitor 2. */
220	unsigned u1TM2 : 1;
221	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
222	unsigned u1SSSE3 : 1;
223	/** Bit 10 - CNTX-ID - L1 Context ID. */
224	unsigned u1CNTXID : 1;
225	/** Bit 11 - FMA. */
226	unsigned u1FMA : 1;
227	/** Bit 12 - Reserved. */
228	unsigned u1Reserved2 : 1;
229	/** Bit 13 - CX16 - CMPXCHG16B. */
230	unsigned u1CX16 : 1;
231	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
232	unsigned u1TPRUpdate : 1;
233	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
234	unsigned u1PDCM : 1;
235	/** Reserved. */
236	unsigned u2Reserved3 : 2;
237	/** Bit 18 - Direct Cache Access. */
238	unsigned u1DCA : 1;
239	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
240	unsigned u1SSE4_1 : 1;
241	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
242	unsigned u1SSE4_2 : 1;
243	/** Bit 21 - x2APIC. */
244	unsigned u1x2APIC : 1;
245	/** Bit 22 - MOVBE - Supports MOVBE. */
246	unsigned u1MOVBE : 1;
247	/** Bit 23 - POPCNT - Supports POPCNT. */
248	unsigned u1POPCNT : 1;
249	/** Bit 24 - Reserved. */
250	unsigned u1Reserved4 : 1;
251	/** Bit 25 - AES. */
252	unsigned u1AES : 1;
253	/** Bit 26 - XSAVE - Supports XSAVE. */
254	unsigned u1XSAVE : 1;
255	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
256	unsigned u1OSXSAVE : 1;
257	/** Reserved. */
258	unsigned u4Reserved5 : 4;
259	} X86CPUIDFEATECX;
260	/** Pointer to CPUID Feature Information - ECX. */
261	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
262	/** Pointer to const CPUID Feature Information - ECX. */
263	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
264
265
266	/** CPUID Feature Information - EDX.
267	* CPUID query with EAX=1.
268	*/
269	typedef struct X86CPUIDFEATEDX
270	{
271	/** Bit 0 - FPU - x87 FPU on Chip. */
272	unsigned u1FPU : 1;
273	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
274	unsigned u1VME : 1;
275	/** Bit 2 - DE - Debugging extensions. */
276	unsigned u1DE : 1;
277	/** Bit 3 - PSE - Page Size Extension. */
278	unsigned u1PSE : 1;
279	/** Bit 4 - TSC - Time Stamp Counter. */
280	unsigned u1TSC : 1;
281	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
282	unsigned u1MSR : 1;
283	/** Bit 6 - PAE - Physical Address Extension. */
284	unsigned u1PAE : 1;
285	/** Bit 7 - MCE - Machine Check Exception. */
286	unsigned u1MCE : 1;
287	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
288	unsigned u1CX8 : 1;
289	/** Bit 9 - APIC - APIC On-Chip. */
290	unsigned u1APIC : 1;
291	/** Bit 10 - Reserved. */
292	unsigned u1Reserved1 : 1;
293	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
294	unsigned u1SEP : 1;
295	/** Bit 12 - MTRR - Memory Type Range Registers. */
296	unsigned u1MTRR : 1;
297	/** Bit 13 - PGE - PTE Global Bit. */
298	unsigned u1PGE : 1;
299	/** Bit 14 - MCA - Machine Check Architecture. */
300	unsigned u1MCA : 1;
301	/** Bit 15 - CMOV - Conditional Move Instructions. */
302	unsigned u1CMOV : 1;
303	/** Bit 16 - PAT - Page Attribute Table. */
304	unsigned u1PAT : 1;
305	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
306	unsigned u1PSE36 : 1;
307	/** Bit 18 - PSN - Processor Serial Number. */
308	unsigned u1PSN : 1;
309	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
310	unsigned u1CLFSH : 1;
311	/** Bit 20 - Reserved. */
312	unsigned u1Reserved2 : 1;
313	/** Bit 21 - DS - Debug Store. */
314	unsigned u1DS : 1;
315	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
316	unsigned u1ACPI : 1;
317	/** Bit 23 - MMX - Intel MMX 'Technology'. */
318	unsigned u1MMX : 1;
319	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
320	unsigned u1FXSR : 1;
321	/** Bit 25 - SSE - SSE Support. */
322	unsigned u1SSE : 1;
323	/** Bit 26 - SSE2 - SSE2 Support. */
324	unsigned u1SSE2 : 1;
325	/** Bit 27 - SS - Self Snoop. */
326	unsigned u1SS : 1;
327	/** Bit 28 - HTT - Hyper-Threading Technology. */
328	unsigned u1HTT : 1;
329	/** Bit 29 - TM - Thermal Monitor. */
330	unsigned u1TM : 1;
331	/** Bit 30 - Reserved - . */
332	unsigned u1Reserved3 : 1;
333	/** Bit 31 - PBE - Pending Break Enabled. */
334	unsigned u1PBE : 1;
335	} X86CPUIDFEATEDX;
336	/** Pointer to CPUID Feature Information - EDX. */
337	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
338	/** Pointer to const CPUID Feature Information - EDX. */
339	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
340
341	/** @name CPUID Vendor information.
342	* CPUID query with EAX=0.
343	* @{
344	*/
345	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
346	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
347	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
348
349	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
350	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
351	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
352	/** @} */
353
354
355	/** @name CPUID Feature information.
356	* CPUID query with EAX=1.
357	* @{
358	*/
359	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
360	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
361	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
362	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
363	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
364	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
365	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
366	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
367	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
368	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
369	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
370	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
371	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
372	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
373	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
374	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
375	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
376	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
377	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
378	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
379	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
380	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
381	/** ECX Bit 12 - FMA. */
382	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
383	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
384	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
385	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
386	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
387	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
388	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
389	/** ECX Bit 18 - DCA - Direct Cache Access. */
390	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
391	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
392	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
393	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
394	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
395	/** ECX Bit 21 - x2APIC support. */
396	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
397	/** ECX Bit 22 - MOVBE instruction. */
398	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
399	/** ECX Bit 23 - POPCNT instruction. */
400	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
401	/** ECX Bit 25 - AES instructions. */
402	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
403	/** ECX Bit 26 - XSAVE instruction. */
404	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
405	/** ECX Bit 27 - OSXSAVE instruction. */
406	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
407	/** ECX Bit 28 - AVX. */
408	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
409
410
411	/** Bit 0 - FPU - x87 FPU on Chip. */
412	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
413	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
414	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
415	/** Bit 2 - DE - Debugging extensions. */
416	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
417	/** Bit 3 - PSE - Page Size Extension. */
418	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
419	/** Bit 4 - TSC - Time Stamp Counter. */
420	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
421	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
422	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
423	/** Bit 6 - PAE - Physical Address Extension. */
424	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
425	/** Bit 7 - MCE - Machine Check Exception. */
426	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
427	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
428	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
429	/** Bit 9 - APIC - APIC On-Chip. */
430	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
431	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
432	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
433	/** Bit 12 - MTRR - Memory Type Range Registers. */
434	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
435	/** Bit 13 - PGE - PTE Global Bit. */
436	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
437	/** Bit 14 - MCA - Machine Check Architecture. */
438	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
439	/** Bit 15 - CMOV - Conditional Move Instructions. */
440	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
441	/** Bit 16 - PAT - Page Attribute Table. */
442	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
443	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
444	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
445	/** Bit 18 - PSN - Processor Serial Number. */
446	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
447	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
448	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
449	/** Bit 21 - DS - Debug Store. */
450	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
451	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
452	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
453	/** Bit 23 - MMX - Intel MMX Technology. */
454	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
455	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
456	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
457	/** Bit 25 - SSE - SSE Support. */
458	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
459	/** Bit 26 - SSE2 - SSE2 Support. */
460	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
461	/** Bit 27 - SS - Self Snoop. */
462	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
463	/** Bit 28 - HTT - Hyper-Threading Technology. */
464	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
465	/** Bit 29 - TM - Therm. Monitor. */
466	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
467	/** Bit 31 - PBE - Pending Break Enabled. */
468	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
469	/** @} */
470
471	/** @name CPUID mwait/monitor information.
472	* CPUID query with EAX=5.
473	* @{
474	*/
475	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
476	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
477	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
478	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
479	/** @} */
480
481
482	/** @name CPUID AMD Feature information.
483	* CPUID query with EAX=0x80000001.
484	* @{
485	*/
486	/** Bit 0 - FPU - x87 FPU on Chip. */
487	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
488	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
489	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
490	/** Bit 2 - DE - Debugging extensions. */
491	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
492	/** Bit 3 - PSE - Page Size Extension. */
493	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
494	/** Bit 4 - TSC - Time Stamp Counter. */
495	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
496	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
497	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
498	/** Bit 6 - PAE - Physical Address Extension. */
499	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
500	/** Bit 7 - MCE - Machine Check Exception. */
501	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
502	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
503	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
504	/** Bit 9 - APIC - APIC On-Chip. */
505	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
506	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
507	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
508	/** Bit 12 - MTRR - Memory Type Range Registers. */
509	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
510	/** Bit 13 - PGE - PTE Global Bit. */
511	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
512	/** Bit 14 - MCA - Machine Check Architecture. */
513	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
514	/** Bit 15 - CMOV - Conditional Move Instructions. */
515	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
516	/** Bit 16 - PAT - Page Attribute Table. */
517	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
518	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
519	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
520	/** Bit 20 - NX - AMD No-Execute Page Protection. */
521	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
522	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
523	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
524	/** Bit 23 - MMX - Intel MMX Technology. */
525	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
526	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
527	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
528	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
529	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
530	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
531	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
532	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
533	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
534	/** Bit 29 - LM - AMD Long Mode. */
535	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
536	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
537	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
538	/** Bit 31 - 3DNOW - AMD 3DNow. */
539	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
540
541	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
542	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
543	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
544	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
545	/** Bit 2 - SVM - AMD VM extensions. */
546	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
547	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
548	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
549	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
550	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
551	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
552	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
553	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
554	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
555	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
556	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
557	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
558	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
559	/** Bit 9 - OSVW - AMD OS visible workaround. */
560	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
561	/** Bit 10 - IBS - Instruct based sampling. */
562	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
563	/** Bit 11 - SSE5 - SSE5 instruction support. */
564	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
565	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
566	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
567	/** Bit 13 - WDT - AMD Watchdog timer support. */
568	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
569
570	/** @} */
571
572
573	/** @name CPUID AMD Feature information.
574	* CPUID query with EAX=0x80000007.
575	* @{
576	*/
577	/** Bit 0 - TS - Temperature Sensor. */
578	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
579	/** Bit 1 - FID - Frequency ID Control. */
580	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
581	/** Bit 2 - VID - Voltage ID Control. */
582	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
583	/** Bit 3 - TTP - THERMTRIP. */
584	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
585	/** Bit 4 - TM - Hardware Thermal Control. */
586	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
587	/** Bit 5 - STC - Software Thermal Control. */
588	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
589	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
590	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
591	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
592	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
593	/** Bit 8 - TSCINVAR - TSC Invariant. */
594	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
595	/** @} */
596
597
598	/** @name CR0
599	* @{ */
600	/** Bit 0 - PE - Protection Enabled */
601	#define X86_CR0_PE RT_BIT(0)
602	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
603	/** Bit 1 - MP - Monitor Coprocessor */
604	#define X86_CR0_MP RT_BIT(1)
605	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
606	/** Bit 2 - EM - Emulation. */
607	#define X86_CR0_EM RT_BIT(2)
608	#define X86_CR0_EMULATE_FPU RT_BIT(2)
609	/** Bit 3 - TS - Task Switch. */
610	#define X86_CR0_TS RT_BIT(3)
611	#define X86_CR0_TASK_SWITCH RT_BIT(3)
612	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
613	#define X86_CR0_ET RT_BIT(4)
614	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
615	/** Bit 5 - NE - Numeric error. */
616	#define X86_CR0_NE RT_BIT(5)
617	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
618	/** Bit 16 - WP - Write Protect. */
619	#define X86_CR0_WP RT_BIT(16)
620	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
621	/** Bit 18 - AM - Alignment Mask. */
622	#define X86_CR0_AM RT_BIT(18)
623	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
624	/** Bit 29 - NW - Not Write-though. */
625	#define X86_CR0_NW RT_BIT(29)
626	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
627	/** Bit 30 - WP - Cache Disable. */
628	#define X86_CR0_CD RT_BIT(30)
629	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
630	/** Bit 31 - PG - Paging. */
631	#define X86_CR0_PG RT_BIT(31)
632	#define X86_CR0_PAGING RT_BIT(31)
633	/** @} */
634
635
636	/** @name CR3
637	* @{ */
638	/** Bit 3 - PWT - Page-level Writes Transparent. */
639	#define X86_CR3_PWT RT_BIT(3)
640	/** Bit 4 - PCD - Page-level Cache Disable. */
641	#define X86_CR3_PCD RT_BIT(4)
642	/** Bits 12-31 - - Page directory page number. */
643	#define X86_CR3_PAGE_MASK (0xfffff000)
644	/** Bits 5-31 - - PAE Page directory page number. */
645	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
646	/** Bits 12-51 - - AMD64 Page directory page number. */
647	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
648	/** @} */
649
650
651	/** @name CR4
652	* @{ */
653	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
654	#define X86_CR4_VME RT_BIT(0)
655	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
656	#define X86_CR4_PVI RT_BIT(1)
657	/** Bit 2 - TSD - Time Stamp Disable. */
658	#define X86_CR4_TSD RT_BIT(2)
659	/** Bit 3 - DE - Debugging Extensions. */
660	#define X86_CR4_DE RT_BIT(3)
661	/** Bit 4 - PSE - Page Size Extension. */
662	#define X86_CR4_PSE RT_BIT(4)
663	/** Bit 5 - PAE - Physical Address Extension. */
664	#define X86_CR4_PAE RT_BIT(5)
665	/** Bit 6 - MCE - Machine-Check Enable. */
666	#define X86_CR4_MCE RT_BIT(6)
667	/** Bit 7 - PGE - Page Global Enable. */
668	#define X86_CR4_PGE RT_BIT(7)
669	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
670	#define X86_CR4_PCE RT_BIT(8)
671	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
672	#define X86_CR4_OSFSXR RT_BIT(9)
673	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
674	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
675	/** Bit 13 - VMXE - VMX mode is enabled. */
676	#define X86_CR4_VMXE RT_BIT(13)
677	/** @} */
678
679
680	/** @name DR6
681	* @{ */
682	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
683	#define X86_DR6_B0 RT_BIT(0)
684	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
685	#define X86_DR6_B1 RT_BIT(1)
686	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
687	#define X86_DR6_B2 RT_BIT(2)
688	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
689	#define X86_DR6_B3 RT_BIT(3)
690	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
691	#define X86_DR6_BD RT_BIT(13)
692	/** Bit 14 - BS - Single step */
693	#define X86_DR6_BS RT_BIT(14)
694	/** Bit 15 - BT - Task switch. (TSS T bit.) */
695	#define X86_DR6_BT RT_BIT(15)
696	/** Value of DR6 after powerup/reset. */
697	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
698	/** @} */
699
700
701	/** @name DR7
702	* @{ */
703	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
704	#define X86_DR7_L0 RT_BIT(0)
705	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
706	#define X86_DR7_G0 RT_BIT(1)
707	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
708	#define X86_DR7_L1 RT_BIT(2)
709	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
710	#define X86_DR7_G1 RT_BIT(3)
711	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
712	#define X86_DR7_L2 RT_BIT(4)
713	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
714	#define X86_DR7_G2 RT_BIT(5)
715	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
716	#define X86_DR7_L3 RT_BIT(6)
717	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
718	#define X86_DR7_G3 RT_BIT(7)
719	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
720	#define X86_DR7_LE RT_BIT(8)
721	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
722	#define X86_DR7_GE RT_BIT(9)
723
724	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
725	* any DR register is accessed. */
726	#define X86_DR7_GD RT_BIT(13)
727	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
728	#define X86_DR7_RW0_MASK (3 << 16)
729	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
730	#define X86_DR7_LEN0_MASK (3 << 18)
731	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
732	#define X86_DR7_RW1_MASK (3 << 20)
733	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
734	#define X86_DR7_LEN1_MASK (3 << 22)
735	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
736	#define X86_DR7_RW2_MASK (3 << 24)
737	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
738	#define X86_DR7_LEN2_MASK (3 << 26)
739	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
740	#define X86_DR7_RW3_MASK (3 << 28)
741	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
742	#define X86_DR7_LEN3_MASK (3 << 30)
743
744	/** Bits which must be 1s. */
745	#define X86_DR7_MB1_MASK (RT_BIT(10))
746
747	/** Calcs the L bit of Nth breakpoint.
748	* @param iBp The breakpoint number [0..3].
749	*/
750	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
751
752	/** Calcs the G bit of Nth breakpoint.
753	* @param iBp The breakpoint number [0..3].
754	*/
755	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
756
757	/** @name Read/Write values.
758	* @{ */
759	/** Break on instruction fetch only. */
760	#define X86_DR7_RW_EO 0U
761	/** Break on write only. */
762	#define X86_DR7_RW_WO 1U
763	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
764	#define X86_DR7_RW_IO 2U
765	/** Break on read or write (but not instruction fetches). */
766	#define X86_DR7_RW_RW 3U
767	/** @} */
768
769	/** Shifts a X86_DR7_RW_* value to its right place.
770	* @param iBp The breakpoint number [0..3].
771	* @param fRw One of the X86_DR7_RW_* value.
772	*/
773	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
774
775	/** @name Length values.
776	* @{ */
777	#define X86_DR7_LEN_BYTE 0U
778	#define X86_DR7_LEN_WORD 1U
779	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
780	#define X86_DR7_LEN_DWORD 3U
781	/** @} */
782
783	/** Shifts a X86_DR7_LEN_* value to its right place.
784	* @param iBp The breakpoint number [0..3].
785	* @param cb One of the X86_DR7_LEN_* values.
786	*/
787	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
788
789	/** Fetch the breakpoint length bits from the DR7 value.
790	* @param uDR7 DR7 value
791	* @param iBp The breakpoint number [0..3].
792	*/
793	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
794
795	/** Mask used to check if any breakpoints are enabled. */
796	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
797
798	/** Mask used to check if any io breakpoints are set. */
799	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
800
801	/** Value of DR7 after powerup/reset. */
802	#define X86_DR7_INIT_VAL 0x400
803	/** @} */
804
805
806	/** @name Machine Specific Registers
807	* @{
808	*/
809
810	/** Time Stamp Counter. */
811	#define MSR_IA32_TSC 0x10
812
813	#define MSR_IA32_PLATFORM_ID 0x17
814
815	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
816	#define MSR_IA32_APICBASE 0x1b
817	#endif
818
819	/** CPU Feature control. */
820	#define MSR_IA32_FEATURE_CONTROL 0x3A
821	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
822	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
823
824	/** BIOS update trigger (microcode update). */
825	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
826
827	/** BIOS update signature (microcode). */
828	#define MSR_IA32_BIOS_SIGN_ID 0x8B
829
830	/** General performance counters. */
831	#define MSR_IA32_PMC0 0xC1
832	#define MSR_IA32_PMC1 0xC2
833	#define MSR_IA32_PMC2 0xC3
834	#define MSR_IA32_PMC3 0xC4
835
836	/** Nehalem power control. */
837	#define MSR_IA32_PLATFORM_INFO 0xCE
838
839	/** MTRR Capabilities. */
840	#define MSR_IA32_MTRR_CAP 0xFE
841
842
843	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
844	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
845	* R0 SS == CS + 8
846	* R3 CS == CS + 16
847	* R3 SS == CS + 24
848	*/
849	#define MSR_IA32_SYSENTER_CS 0x174
850	/** SYSENTER_ESP - the R0 ESP. */
851	#define MSR_IA32_SYSENTER_ESP 0x175
852	/** SYSENTER_EIP - the R0 EIP. */
853	#define MSR_IA32_SYSENTER_EIP 0x176
854	#endif
855
856	/** Machine Check Global Capabilities Register. */
857	#define MSR_IA32_MCP_CAP 0x179
858	/** Machine Check Global Status Register. */
859	#define MSR_IA32_MCP_STATUS 0x17A
860	/** Machine Check Global Control Register. */
861	#define MSR_IA32_MCP_CTRL 0x17B
862
863	/** Trace/Profile Resource Control (R/W) */
864	#define MSR_IA32_DEBUGCTL 0x1D9
865
866	/* Page Attribute Table. */
867	#define MSR_IA32_CR_PAT 0x277
868
869	/** Performance counter MSRs. (Intel only) */
870	#define MSR_IA32_PERFEVTSEL0 0x186
871	#define MSR_IA32_PERFEVTSEL1 0x187
872	#define MSR_IA32_FLEX_RATIO 0x194
873	#define MSR_IA32_PERF_STATUS 0x198
874	#define MSR_IA32_PERF_CTL 0x199
875
876	/** Enable misc. processor features (R/W). */
877	#define MSR_IA32_MISC_ENABLE 0x1A0
878
879	/** MTRR Default Range. */
880	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
881
882	#define MSR_IA32_MC0_CTL 0x400
883	#define MSR_IA32_MC0_STATUS 0x401
884
885	/** Basic VMX information. */
886	#define MSR_IA32_VMX_BASIC_INFO 0x480
887	/** Allowed settings for pin-based VM execution controls */
888	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
889	/** Allowed settings for proc-based VM execution controls */
890	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
891	/** Allowed settings for the VMX exit controls. */
892	#define MSR_IA32_VMX_EXIT_CTLS 0x483
893	/** Allowed settings for the VMX entry controls. */
894	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
895	/** Misc VMX info. */
896	#define MSR_IA32_VMX_MISC 0x485
897	/** Fixed cleared bits in CR0. */
898	#define MSR_IA32_VMX_CR0_FIXED0 0x486
899	/** Fixed set bits in CR0. */
900	#define MSR_IA32_VMX_CR0_FIXED1 0x487
901	/** Fixed cleared bits in CR4. */
902	#define MSR_IA32_VMX_CR4_FIXED0 0x488
903	/** Fixed set bits in CR4. */
904	#define MSR_IA32_VMX_CR4_FIXED1 0x489
905	/** Information for enumerating fields in the VMCS. */
906	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
907	/** Allowed settings for secondary proc-based VM execution controls */
908	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
909	/** EPT capabilities. */
910	#define MSR_IA32_VMX_EPT_CAPS 0x48C
911	/** DS Save Area (R/W). */
912	#define MSR_IA32_DS_AREA 0x600
913	/** X2APIC MSR ranges. */
914	#define MSR_IA32_APIC_START 0x800
915	#define MSR_IA32_APIC_END 0x900
916
917	/** K6 EFER - Extended Feature Enable Register. */
918	#define MSR_K6_EFER 0xc0000080
919	/** @todo document EFER */
920	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
921	#define MSR_K6_EFER_SCE RT_BIT(0)
922	/** Bit 8 - LME - Long mode enabled. (R/W) */
923	#define MSR_K6_EFER_LME RT_BIT(8)
924	/** Bit 10 - LMA - Long mode active. (R) */
925	#define MSR_K6_EFER_LMA RT_BIT(10)
926	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
927	#define MSR_K6_EFER_NXE RT_BIT(11)
928	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
929	#define MSR_K6_EFER_SVME RT_BIT(12)
930	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
931	#define MSR_K6_EFER_LMSLE RT_BIT(13)
932	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
933	#define MSR_K6_EFER_FFXSR RT_BIT(14)
934	/** K6 STAR - SYSCALL/RET targets. */
935	#define MSR_K6_STAR 0xc0000081
936	/** Shift value for getting the SYSRET CS and SS value. */
937	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
938	/** Shift value for getting the SYSCALL CS and SS value. */
939	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
940	/** Selector mask for use after shifting. */
941	#define MSR_K6_STAR_SEL_MASK 0xffff
942	/** The mask which give the SYSCALL EIP. */
943	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
944	/** K6 WHCR - Write Handling Control Register. */
945	#define MSR_K6_WHCR 0xc0000082
946	/** K6 UWCCR - UC/WC Cacheability Control Register. */
947	#define MSR_K6_UWCCR 0xc0000085
948	/** K6 PSOR - Processor State Observability Register. */
949	#define MSR_K6_PSOR 0xc0000087
950	/** K6 PFIR - Page Flush/Invalidate Register. */
951	#define MSR_K6_PFIR 0xc0000088
952
953	/** Performance counter MSRs. (AMD only) */
954	#define MSR_K7_EVNTSEL0 0xc0010000
955	#define MSR_K7_EVNTSEL1 0xc0010001
956	#define MSR_K7_EVNTSEL2 0xc0010002
957	#define MSR_K7_EVNTSEL3 0xc0010003
958	#define MSR_K7_PERFCTR0 0xc0010004
959	#define MSR_K7_PERFCTR1 0xc0010005
960	#define MSR_K7_PERFCTR2 0xc0010006
961	#define MSR_K7_PERFCTR3 0xc0010007
962
963	#define MSR_K8_HWCR 0xc0010015
964
965	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
966	#define MSR_K8_LSTAR 0xc0000082
967	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
968	#define MSR_K8_CSTAR 0xc0000083
969	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
970	#define MSR_K8_SF_MASK 0xc0000084
971	/** K8 FS.base - The 64-bit base FS register. */
972	#define MSR_K8_FS_BASE 0xc0000100
973	/** K8 GS.base - The 64-bit base GS register. */
974	#define MSR_K8_GS_BASE 0xc0000101
975	/** K8 KernelGSbase - Used with SWAPGS. */
976	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
977	#define MSR_K8_TSC_AUX 0xc0000103
978	#define MSR_K8_SYSCFG 0xc0010010
979	#define MSR_K8_HWCR 0xc0010015
980	#define MSR_K8_IORRBASE0 0xc0010016
981	#define MSR_K8_IORRMASK0 0xc0010017
982	#define MSR_K8_IORRBASE1 0xc0010018
983	#define MSR_K8_IORRMASK1 0xc0010019
984	#define MSR_K8_TOP_MEM1 0xc001001a
985	#define MSR_K8_TOP_MEM2 0xc001001d
986	#define MSR_K8_VM_CR 0xc0010114
987	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
988
989	#define MSR_K8_IGNNE 0xc0010115
990	#define MSR_K8_SMM_CTL 0xc0010116
991	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
992	* host state during world switch.
993	*/
994	#define MSR_K8_VM_HSAVE_PA 0xc0010117
995
996	/** @} */
997
998
999	/** @name Page Table / Directory / Directory Pointers / L4.
1000	* @{
1001	*/
1002
1003	/** Page table/directory entry as an unsigned integer. */
1004	typedef uint32_t X86PGUINT;
1005	/** Pointer to a page table/directory table entry as an unsigned integer. */
1006	typedef X86PGUINT *PX86PGUINT;
1007	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1008	typedef X86PGUINT const *PCX86PGUINT;
1009
1010	/** Number of entries in a 32-bit PT/PD. */
1011	#define X86_PG_ENTRIES 1024
1012
1013
1014	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1015	typedef uint64_t X86PGPAEUINT;
1016	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1017	typedef X86PGPAEUINT *PX86PGPAEUINT;
1018	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1019	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1020
1021	/** Number of entries in a PAE PT/PD. */
1022	#define X86_PG_PAE_ENTRIES 512
1023	/** Number of entries in a PAE PDPT. */
1024	#define X86_PG_PAE_PDPE_ENTRIES 4
1025
1026	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1027	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1028	/** Number of entries in an AMD64 PDPT.
1029	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1030	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1031
1032	/** The size of a 4KB page. */
1033	#define X86_PAGE_4K_SIZE _4K
1034	/** The page shift of a 4KB page. */
1035	#define X86_PAGE_4K_SHIFT 12
1036	/** The 4KB page offset mask. */
1037	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1038	/** The 4KB page base mask for virtual addresses. */
1039	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1040	/** The 4KB page base mask for virtual addresses - 32bit version. */
1041	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1042
1043	/** The size of a 2MB page. */
1044	#define X86_PAGE_2M_SIZE _2M
1045	/** The page shift of a 2MB page. */
1046	#define X86_PAGE_2M_SHIFT 21
1047	/** The 2MB page offset mask. */
1048	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1049	/** The 2MB page base mask for virtual addresses. */
1050	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1051	/** The 2MB page base mask for virtual addresses - 32bit version. */
1052	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1053
1054	/** The size of a 4MB page. */
1055	#define X86_PAGE_4M_SIZE _4M
1056	/** The page shift of a 4MB page. */
1057	#define X86_PAGE_4M_SHIFT 22
1058	/** The 4MB page offset mask. */
1059	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1060	/** The 4MB page base mask for virtual addresses. */
1061	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1062	/** The 4MB page base mask for virtual addresses - 32bit version. */
1063	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1064
1065
1066
1067	/** @name Page Table Entry
1068	* @{
1069	*/
1070	/** Bit 0 - P - Present bit. */
1071	#define X86_PTE_BIT_P 0
1072	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1073	#define X86_PTE_BIT_RW 1
1074	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1075	#define X86_PTE_BIT_US 2
1076	/** Bit 3 - PWT - Page level write thru bit. */
1077	#define X86_PTE_BIT_PWT 3
1078	/** Bit 4 - PCD - Page level cache disable bit. */
1079	#define X86_PTE_BIT_PCD 4
1080	/** Bit 5 - A - Access bit. */
1081	#define X86_PTE_BIT_A 5
1082	/** Bit 6 - D - Dirty bit. */
1083	#define X86_PTE_BIT_D 6
1084	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1085	#define X86_PTE_BIT_PAT 7
1086	/** Bit 8 - G - Global flag. */
1087	#define X86_PTE_BIT_G 8
1088
1089	/** Bit 0 - P - Present bit mask. */
1090	#define X86_PTE_P RT_BIT(0)
1091	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1092	#define X86_PTE_RW RT_BIT(1)
1093	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1094	#define X86_PTE_US RT_BIT(2)
1095	/** Bit 3 - PWT - Page level write thru bit mask. */
1096	#define X86_PTE_PWT RT_BIT(3)
1097	/** Bit 4 - PCD - Page level cache disable bit mask. */
1098	#define X86_PTE_PCD RT_BIT(4)
1099	/** Bit 5 - A - Access bit mask. */
1100	#define X86_PTE_A RT_BIT(5)
1101	/** Bit 6 - D - Dirty bit mask. */
1102	#define X86_PTE_D RT_BIT(6)
1103	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1104	#define X86_PTE_PAT RT_BIT(7)
1105	/** Bit 8 - G - Global bit mask. */
1106	#define X86_PTE_G RT_BIT(8)
1107
1108	/** Bits 9-11 - - Available for use to system software. */
1109	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1110	/** Bits 12-31 - - Physical Page number of the next level. */
1111	#define X86_PTE_PG_MASK ( 0xfffff000 )
1112
1113	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1114	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1115	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1116	/** @todo Get rid of the above hack; makes code unreadable. */
1117	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1118	#else
1119	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1120	#endif
1121	/** Bits 63 - NX - PAE - No execution flag. */
1122	#define X86_PTE_PAE_NX RT_BIT_64(63)
1123
1124	/**
1125	* Page table entry.
1126	*/
1127	typedef struct X86PTEBITS
1128	{
1129	/** Flags whether(=1) or not the page is present. */
1130	unsigned u1Present : 1;
1131	/** Read(=0) / Write(=1) flag. */
1132	unsigned u1Write : 1;
1133	/** User(=1) / Supervisor (=0) flag. */
1134	unsigned u1User : 1;
1135	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1136	unsigned u1WriteThru : 1;
1137	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1138	unsigned u1CacheDisable : 1;
1139	/** Accessed flag.
1140	* Indicates that the page have been read or written to. */
1141	unsigned u1Accessed : 1;
1142	/** Dirty flag.
1143	* Indicates that the page has been written to. */
1144	unsigned u1Dirty : 1;
1145	/** Reserved / If PAT enabled, bit 2 of the index. */
1146	unsigned u1PAT : 1;
1147	/** Global flag. (Ignored in all but final level.) */
1148	unsigned u1Global : 1;
1149	/** Available for use to system software. */
1150	unsigned u3Available : 3;
1151	/** Physical Page number of the next level. */
1152	unsigned u20PageNo : 20;
1153	} X86PTEBITS;
1154	/** Pointer to a page table entry. */
1155	typedef X86PTEBITS *PX86PTEBITS;
1156	/** Pointer to a const page table entry. */
1157	typedef const X86PTEBITS *PCX86PTEBITS;
1158
1159	/**
1160	* Page table entry.
1161	*/
1162	typedef union X86PTE
1163	{
1164	/** Unsigned integer view */
1165	X86PGUINT u;
1166	/** Bit field view. */
1167	X86PTEBITS n;
1168	/** 32-bit view. */
1169	uint32_t au32[1];
1170	/** 16-bit view. */
1171	uint16_t au16[2];
1172	/** 8-bit view. */
1173	uint8_t au8[4];
1174	} X86PTE;
1175	/** Pointer to a page table entry. */
1176	typedef X86PTE *PX86PTE;
1177	/** Pointer to a const page table entry. */
1178	typedef const X86PTE *PCX86PTE;
1179
1180
1181	/**
1182	* PAE page table entry.
1183	*/
1184	typedef struct X86PTEPAEBITS
1185	{
1186	/** Flags whether(=1) or not the page is present. */
1187	uint32_t u1Present : 1;
1188	/** Read(=0) / Write(=1) flag. */
1189	uint32_t u1Write : 1;
1190	/** User(=1) / Supervisor(=0) flag. */
1191	uint32_t u1User : 1;
1192	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1193	uint32_t u1WriteThru : 1;
1194	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1195	uint32_t u1CacheDisable : 1;
1196	/** Accessed flag.
1197	* Indicates that the page have been read or written to. */
1198	uint32_t u1Accessed : 1;
1199	/** Dirty flag.
1200	* Indicates that the page has been written to. */
1201	uint32_t u1Dirty : 1;
1202	/** Reserved / If PAT enabled, bit 2 of the index. */
1203	uint32_t u1PAT : 1;
1204	/** Global flag. (Ignored in all but final level.) */
1205	uint32_t u1Global : 1;
1206	/** Available for use to system software. */
1207	uint32_t u3Available : 3;
1208	/** Physical Page number of the next level - Low Part. Don't use this. */
1209	uint32_t u20PageNoLow : 20;
1210	/** Physical Page number of the next level - High Part. Don't use this. */
1211	uint32_t u20PageNoHigh : 20;
1212	/** MBZ bits */
1213	uint32_t u11Reserved : 11;
1214	/** No Execute flag. */
1215	uint32_t u1NoExecute : 1;
1216	} X86PTEPAEBITS;
1217	/** Pointer to a page table entry. */
1218	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1219	/** Pointer to a page table entry. */
1220	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1221
1222	/**
1223	* PAE Page table entry.
1224	*/
1225	typedef union X86PTEPAE
1226	{
1227	/** Unsigned integer view */
1228	X86PGPAEUINT u;
1229	/** Bit field view. */
1230	X86PTEPAEBITS n;
1231	/** 32-bit view. */
1232	uint32_t au32[2];
1233	/** 16-bit view. */
1234	uint16_t au16[4];
1235	/** 8-bit view. */
1236	uint8_t au8[8];
1237	} X86PTEPAE;
1238	/** Pointer to a PAE page table entry. */
1239	typedef X86PTEPAE *PX86PTEPAE;
1240	/** Pointer to a const PAE page table entry. */
1241	typedef const X86PTEPAE *PCX86PTEPAE;
1242	/** @} */
1243
1244	/**
1245	* Page table.
1246	*/
1247	typedef struct X86PT
1248	{
1249	/** PTE Array. */
1250	X86PTE a[X86_PG_ENTRIES];
1251	} X86PT;
1252	/** Pointer to a page table. */
1253	typedef X86PT *PX86PT;
1254	/** Pointer to a const page table. */
1255	typedef const X86PT *PCX86PT;
1256
1257	/** The page shift to get the PT index. */
1258	#define X86_PT_SHIFT 12
1259	/** The PT index mask (apply to a shifted page address). */
1260	#define X86_PT_MASK 0x3ff
1261
1262
1263	/**
1264	* Page directory.
1265	*/
1266	typedef struct X86PTPAE
1267	{
1268	/** PTE Array. */
1269	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1270	} X86PTPAE;
1271	/** Pointer to a page table. */
1272	typedef X86PTPAE *PX86PTPAE;
1273	/** Pointer to a const page table. */
1274	typedef const X86PTPAE *PCX86PTPAE;
1275
1276	/** The page shift to get the PA PTE index. */
1277	#define X86_PT_PAE_SHIFT 12
1278	/** The PAE PT index mask (apply to a shifted page address). */
1279	#define X86_PT_PAE_MASK 0x1ff
1280
1281
1282	/** @name 4KB Page Directory Entry
1283	* @{
1284	*/
1285	/** Bit 0 - P - Present bit. */
1286	#define X86_PDE_P RT_BIT(0)
1287	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1288	#define X86_PDE_RW RT_BIT(1)
1289	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1290	#define X86_PDE_US RT_BIT(2)
1291	/** Bit 3 - PWT - Page level write thru bit. */
1292	#define X86_PDE_PWT RT_BIT(3)
1293	/** Bit 4 - PCD - Page level cache disable bit. */
1294	#define X86_PDE_PCD RT_BIT(4)
1295	/** Bit 5 - A - Access bit. */
1296	#define X86_PDE_A RT_BIT(5)
1297	/** Bit 7 - PS - Page size attribute.
1298	* Clear mean 4KB pages, set means large pages (2/4MB). */
1299	#define X86_PDE_PS RT_BIT(7)
1300	/** Bits 9-11 - - Available for use to system software. */
1301	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1302	/** Bits 12-31 - - Physical Page number of the next level. */
1303	#define X86_PDE_PG_MASK ( 0xfffff000 )
1304
1305	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1306	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1307	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1308	* we partly or that part into shadow page table entries. Will be corrected
1309	* soon.
1310	*/
1311	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1312	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1313	#else
1314	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1315	#endif
1316	/** Bits 63 - NX - PAE - No execution flag. */
1317	#define X86_PDE_PAE_NX RT_BIT_64(63)
1318
1319	/**
1320	* Page directory entry.
1321	*/
1322	typedef struct X86PDEBITS
1323	{
1324	/** Flags whether(=1) or not the page is present. */
1325	unsigned u1Present : 1;
1326	/** Read(=0) / Write(=1) flag. */
1327	unsigned u1Write : 1;
1328	/** User(=1) / Supervisor (=0) flag. */
1329	unsigned u1User : 1;
1330	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1331	unsigned u1WriteThru : 1;
1332	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1333	unsigned u1CacheDisable : 1;
1334	/** Accessed flag.
1335	* Indicates that the page has been read or written to. */
1336	unsigned u1Accessed : 1;
1337	/** Reserved / Ignored (dirty bit). */
1338	unsigned u1Reserved0 : 1;
1339	/** Size bit if PSE is enabled - in any event it's 0. */
1340	unsigned u1Size : 1;
1341	/** Reserved / Ignored (global bit). */
1342	unsigned u1Reserved1 : 1;
1343	/** Available for use to system software. */
1344	unsigned u3Available : 3;
1345	/** Physical Page number of the next level. */
1346	unsigned u20PageNo : 20;
1347	} X86PDEBITS;
1348	/** Pointer to a page directory entry. */
1349	typedef X86PDEBITS *PX86PDEBITS;
1350	/** Pointer to a const page directory entry. */
1351	typedef const X86PDEBITS *PCX86PDEBITS;
1352
1353
1354	/**
1355	* PAE page directory entry.
1356	*/
1357	typedef struct X86PDEPAEBITS
1358	{
1359	/** Flags whether(=1) or not the page is present. */
1360	uint32_t u1Present : 1;
1361	/** Read(=0) / Write(=1) flag. */
1362	uint32_t u1Write : 1;
1363	/** User(=1) / Supervisor (=0) flag. */
1364	uint32_t u1User : 1;
1365	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1366	uint32_t u1WriteThru : 1;
1367	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1368	uint32_t u1CacheDisable : 1;
1369	/** Accessed flag.
1370	* Indicates that the page has been read or written to. */
1371	uint32_t u1Accessed : 1;
1372	/** Reserved / Ignored (dirty bit). */
1373	uint32_t u1Reserved0 : 1;
1374	/** Size bit if PSE is enabled - in any event it's 0. */
1375	uint32_t u1Size : 1;
1376	/** Reserved / Ignored (global bit). / */
1377	uint32_t u1Reserved1 : 1;
1378	/** Available for use to system software. */
1379	uint32_t u3Available : 3;
1380	/** Physical Page number of the next level - Low Part. Don't use! */
1381	uint32_t u20PageNoLow : 20;
1382	/** Physical Page number of the next level - High Part. Don't use! */
1383	uint32_t u20PageNoHigh : 20;
1384	/** MBZ bits */
1385	uint32_t u11Reserved : 11;
1386	/** No Execute flag. */
1387	uint32_t u1NoExecute : 1;
1388	} X86PDEPAEBITS;
1389	/** Pointer to a page directory entry. */
1390	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1391	/** Pointer to a const page directory entry. */
1392	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1393
1394	/** @} */
1395
1396
1397	/** @name 2/4MB Page Directory Entry
1398	* @{
1399	*/
1400	/** Bit 0 - P - Present bit. */
1401	#define X86_PDE4M_P RT_BIT(0)
1402	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1403	#define X86_PDE4M_RW RT_BIT(1)
1404	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1405	#define X86_PDE4M_US RT_BIT(2)
1406	/** Bit 3 - PWT - Page level write thru bit. */
1407	#define X86_PDE4M_PWT RT_BIT(3)
1408	/** Bit 4 - PCD - Page level cache disable bit. */
1409	#define X86_PDE4M_PCD RT_BIT(4)
1410	/** Bit 5 - A - Access bit. */
1411	#define X86_PDE4M_A RT_BIT(5)
1412	/** Bit 6 - D - Dirty bit. */
1413	#define X86_PDE4M_D RT_BIT(6)
1414	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1415	#define X86_PDE4M_PS RT_BIT(7)
1416	/** Bit 8 - G - Global flag. */
1417	#define X86_PDE4M_G RT_BIT(8)
1418	/** Bits 9-11 - AVL - Available for use to system software. */
1419	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1420	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1421	#define X86_PDE4M_PAT RT_BIT(12)
1422	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1423	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1424	/** Bits 22-31 - - Physical Page number. */
1425	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1426	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1427	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1428	/** The number of bits to the high part of the page number. */
1429	#define X86_PDE4M_PG_HIGH_SHIFT 19
1430
1431	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1432	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1433	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1434	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1435	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1436
1437	/**
1438	* 4MB page directory entry.
1439	*/
1440	typedef struct X86PDE4MBITS
1441	{
1442	/** Flags whether(=1) or not the page is present. */
1443	unsigned u1Present : 1;
1444	/** Read(=0) / Write(=1) flag. */
1445	unsigned u1Write : 1;
1446	/** User(=1) / Supervisor (=0) flag. */
1447	unsigned u1User : 1;
1448	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1449	unsigned u1WriteThru : 1;
1450	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1451	unsigned u1CacheDisable : 1;
1452	/** Accessed flag.
1453	* Indicates that the page have been read or written to. */
1454	unsigned u1Accessed : 1;
1455	/** Dirty flag.
1456	* Indicates that the page has been written to. */
1457	unsigned u1Dirty : 1;
1458	/** Page size flag - always 1 for 4MB entries. */
1459	unsigned u1Size : 1;
1460	/** Global flag. */
1461	unsigned u1Global : 1;
1462	/** Available for use to system software. */
1463	unsigned u3Available : 3;
1464	/** Reserved / If PAT enabled, bit 2 of the index. */
1465	unsigned u1PAT : 1;
1466	/** Bits 32-39 of the page number on AMD64.
1467	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1468	unsigned u8PageNoHigh : 8;
1469	/** Reserved. */
1470	unsigned u1Reserved : 1;
1471	/** Physical Page number of the page. */
1472	unsigned u10PageNo : 10;
1473	} X86PDE4MBITS;
1474	/** Pointer to a page table entry. */
1475	typedef X86PDE4MBITS *PX86PDE4MBITS;
1476	/** Pointer to a const page table entry. */
1477	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1478
1479
1480	/**
1481	* 2MB PAE page directory entry.
1482	*/
1483	typedef struct X86PDE2MPAEBITS
1484	{
1485	/** Flags whether(=1) or not the page is present. */
1486	uint32_t u1Present : 1;
1487	/** Read(=0) / Write(=1) flag. */
1488	uint32_t u1Write : 1;
1489	/** User(=1) / Supervisor(=0) flag. */
1490	uint32_t u1User : 1;
1491	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1492	uint32_t u1WriteThru : 1;
1493	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1494	uint32_t u1CacheDisable : 1;
1495	/** Accessed flag.
1496	* Indicates that the page have been read or written to. */
1497	uint32_t u1Accessed : 1;
1498	/** Dirty flag.
1499	* Indicates that the page has been written to. */
1500	uint32_t u1Dirty : 1;
1501	/** Page size flag - always 1 for 2MB entries. */
1502	uint32_t u1Size : 1;
1503	/** Global flag. */
1504	uint32_t u1Global : 1;
1505	/** Available for use to system software. */
1506	uint32_t u3Available : 3;
1507	/** Reserved / If PAT enabled, bit 2 of the index. */
1508	uint32_t u1PAT : 1;
1509	/** Reserved. */
1510	uint32_t u9Reserved : 9;
1511	/** Physical Page number of the next level - Low part. Don't use! */
1512	uint32_t u10PageNoLow : 10;
1513	/** Physical Page number of the next level - High part. Don't use! */
1514	uint32_t u20PageNoHigh : 20;
1515	/** MBZ bits */
1516	uint32_t u11Reserved : 11;
1517	/** No Execute flag. */
1518	uint32_t u1NoExecute : 1;
1519	} X86PDE2MPAEBITS;
1520	/** Pointer to a 2MB PAE page table entry. */
1521	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1522	/** Pointer to a 2MB PAE page table entry. */
1523	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1524
1525	/** @} */
1526
1527	/**
1528	* Page directory entry.
1529	*/
1530	typedef union X86PDE
1531	{
1532	/** Unsigned integer view. */
1533	X86PGUINT u;
1534	/** Normal view. */
1535	X86PDEBITS n;
1536	/** 4MB view (big). */
1537	X86PDE4MBITS b;
1538	/** 8 bit unsigned integer view. */
1539	uint8_t au8[4];
1540	/** 16 bit unsigned integer view. */
1541	uint16_t au16[2];
1542	/** 32 bit unsigned integer view. */
1543	uint32_t au32[1];
1544	} X86PDE;
1545	/** Pointer to a page directory entry. */
1546	typedef X86PDE *PX86PDE;
1547	/** Pointer to a const page directory entry. */
1548	typedef const X86PDE *PCX86PDE;
1549
1550	/**
1551	* PAE page directory entry.
1552	*/
1553	typedef union X86PDEPAE
1554	{
1555	/** Unsigned integer view. */
1556	X86PGPAEUINT u;
1557	/** Normal view. */
1558	X86PDEPAEBITS n;
1559	/** 2MB page view (big). */
1560	X86PDE2MPAEBITS b;
1561	/** 8 bit unsigned integer view. */
1562	uint8_t au8[8];
1563	/** 16 bit unsigned integer view. */
1564	uint16_t au16[4];
1565	/** 32 bit unsigned integer view. */
1566	uint32_t au32[2];
1567	} X86PDEPAE;
1568	/** Pointer to a page directory entry. */
1569	typedef X86PDEPAE *PX86PDEPAE;
1570	/** Pointer to a const page directory entry. */
1571	typedef const X86PDEPAE *PCX86PDEPAE;
1572
1573	/**
1574	* Page directory.
1575	*/
1576	typedef struct X86PD
1577	{
1578	/** PDE Array. */
1579	X86PDE a[X86_PG_ENTRIES];
1580	} X86PD;
1581	/** Pointer to a page directory. */
1582	typedef X86PD *PX86PD;
1583	/** Pointer to a const page directory. */
1584	typedef const X86PD *PCX86PD;
1585
1586	/** The page shift to get the PD index. */
1587	#define X86_PD_SHIFT 22
1588	/** The PD index mask (apply to a shifted page address). */
1589	#define X86_PD_MASK 0x3ff
1590
1591
1592	/**
1593	* PAE page directory.
1594	*/
1595	typedef struct X86PDPAE
1596	{
1597	/** PDE Array. */
1598	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1599	} X86PDPAE;
1600	/** Pointer to a PAE page directory. */
1601	typedef X86PDPAE *PX86PDPAE;
1602	/** Pointer to a const PAE page directory. */
1603	typedef const X86PDPAE *PCX86PDPAE;
1604
1605	/** The page shift to get the PAE PD index. */
1606	#define X86_PD_PAE_SHIFT 21
1607	/** The PAE PD index mask (apply to a shifted page address). */
1608	#define X86_PD_PAE_MASK 0x1ff
1609
1610
1611	/** @name Page Directory Pointer Table Entry (PAE)
1612	* @{
1613	*/
1614	/** Bit 0 - P - Present bit. */
1615	#define X86_PDPE_P RT_BIT(0)
1616	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1617	#define X86_PDPE_RW RT_BIT(1)
1618	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1619	#define X86_PDPE_US RT_BIT(2)
1620	/** Bit 3 - PWT - Page level write thru bit. */
1621	#define X86_PDPE_PWT RT_BIT(3)
1622	/** Bit 4 - PCD - Page level cache disable bit. */
1623	#define X86_PDPE_PCD RT_BIT(4)
1624	/** Bit 5 - A - Access bit. Long Mode only. */
1625	#define X86_PDPE_A RT_BIT(5)
1626	/** Bits 9-11 - - Available for use to system software. */
1627	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1628	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1629	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1630	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1631	/** @todo Get rid of the above hack; makes code unreadable. */
1632	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1633	#else
1634	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1635	#endif
1636	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1637	#define X86_PDPE_NX RT_BIT_64(63)
1638
1639	/**
1640	* Page directory pointer table entry.
1641	*/
1642	typedef struct X86PDPEBITS
1643	{
1644	/** Flags whether(=1) or not the page is present. */
1645	uint32_t u1Present : 1;
1646	/** Chunk of reserved bits. */
1647	uint32_t u2Reserved : 2;
1648	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1649	uint32_t u1WriteThru : 1;
1650	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1651	uint32_t u1CacheDisable : 1;
1652	/** Chunk of reserved bits. */
1653	uint32_t u4Reserved : 4;
1654	/** Available for use to system software. */
1655	uint32_t u3Available : 3;
1656	/** Physical Page number of the next level - Low Part. Don't use! */
1657	uint32_t u20PageNoLow : 20;
1658	/** Physical Page number of the next level - High Part. Don't use! */
1659	uint32_t u20PageNoHigh : 20;
1660	/** MBZ bits */
1661	uint32_t u12Reserved : 12;
1662	} X86PDPEBITS;
1663	/** Pointer to a page directory pointer table entry. */
1664	typedef X86PDPEBITS *PX86PTPEBITS;
1665	/** Pointer to a const page directory pointer table entry. */
1666	typedef const X86PDPEBITS *PCX86PTPEBITS;
1667
1668	/**
1669	* Page directory pointer table entry. AMD64 version
1670	*/
1671	typedef struct X86PDPEAMD64BITS
1672	{
1673	/** Flags whether(=1) or not the page is present. */
1674	uint32_t u1Present : 1;
1675	/** Read(=0) / Write(=1) flag. */
1676	uint32_t u1Write : 1;
1677	/** User(=1) / Supervisor (=0) flag. */
1678	uint32_t u1User : 1;
1679	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1680	uint32_t u1WriteThru : 1;
1681	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1682	uint32_t u1CacheDisable : 1;
1683	/** Accessed flag.
1684	* Indicates that the page have been read or written to. */
1685	uint32_t u1Accessed : 1;
1686	/** Chunk of reserved bits. */
1687	uint32_t u3Reserved : 3;
1688	/** Available for use to system software. */
1689	uint32_t u3Available : 3;
1690	/** Physical Page number of the next level - Low Part. Don't use! */
1691	uint32_t u20PageNoLow : 20;
1692	/** Physical Page number of the next level - High Part. Don't use! */
1693	uint32_t u20PageNoHigh : 20;
1694	/** MBZ bits */
1695	uint32_t u11Reserved : 11;
1696	/** No Execute flag. */
1697	uint32_t u1NoExecute : 1;
1698	} X86PDPEAMD64BITS;
1699	/** Pointer to a page directory pointer table entry. */
1700	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1701	/** Pointer to a const page directory pointer table entry. */
1702	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1703
1704	/**
1705	* Page directory pointer table entry.
1706	*/
1707	typedef union X86PDPE
1708	{
1709	/** Unsigned integer view. */
1710	X86PGPAEUINT u;
1711	/** Normal view. */
1712	X86PDPEBITS n;
1713	/** AMD64 view. */
1714	X86PDPEAMD64BITS lm;
1715	/** 8 bit unsigned integer view. */
1716	uint8_t au8[8];
1717	/** 16 bit unsigned integer view. */
1718	uint16_t au16[4];
1719	/** 32 bit unsigned integer view. */
1720	uint32_t au32[2];
1721	} X86PDPE;
1722	/** Pointer to a page directory pointer table entry. */
1723	typedef X86PDPE *PX86PDPE;
1724	/** Pointer to a const page directory pointer table entry. */
1725	typedef const X86PDPE *PCX86PDPE;
1726
1727
1728	/**
1729	* Page directory pointer table.
1730	*/
1731	typedef struct X86PDPT
1732	{
1733	/** PDE Array. */
1734	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1735	} X86PDPT;
1736	/** Pointer to a page directory pointer table. */
1737	typedef X86PDPT *PX86PDPT;
1738	/** Pointer to a const page directory pointer table. */
1739	typedef const X86PDPT *PCX86PDPT;
1740
1741	/** The page shift to get the PDPT index. */
1742	#define X86_PDPT_SHIFT 30
1743	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1744	#define X86_PDPT_MASK_PAE 0x3
1745	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1746	#define X86_PDPT_MASK_AMD64 0x1ff
1747
1748	/** @} */
1749
1750
1751	/** @name Page Map Level-4 Entry (Long Mode PAE)
1752	* @{
1753	*/
1754	/** Bit 0 - P - Present bit. */
1755	#define X86_PML4E_P RT_BIT(0)
1756	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1757	#define X86_PML4E_RW RT_BIT(1)
1758	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1759	#define X86_PML4E_US RT_BIT(2)
1760	/** Bit 3 - PWT - Page level write thru bit. */
1761	#define X86_PML4E_PWT RT_BIT(3)
1762	/** Bit 4 - PCD - Page level cache disable bit. */
1763	#define X86_PML4E_PCD RT_BIT(4)
1764	/** Bit 5 - A - Access bit. */
1765	#define X86_PML4E_A RT_BIT(5)
1766	/** Bits 9-11 - - Available for use to system software. */
1767	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1768	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1769	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1770	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1771	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1772	#else
1773	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1774	#endif
1775	/** Bits 63 - NX - PAE - No execution flag. */
1776	#define X86_PML4E_NX RT_BIT_64(63)
1777
1778	/**
1779	* Page Map Level-4 Entry
1780	*/
1781	typedef struct X86PML4EBITS
1782	{
1783	/** Flags whether(=1) or not the page is present. */
1784	uint32_t u1Present : 1;
1785	/** Read(=0) / Write(=1) flag. */
1786	uint32_t u1Write : 1;
1787	/** User(=1) / Supervisor (=0) flag. */
1788	uint32_t u1User : 1;
1789	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1790	uint32_t u1WriteThru : 1;
1791	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1792	uint32_t u1CacheDisable : 1;
1793	/** Accessed flag.
1794	* Indicates that the page have been read or written to. */
1795	uint32_t u1Accessed : 1;
1796	/** Chunk of reserved bits. */
1797	uint32_t u3Reserved : 3;
1798	/** Available for use to system software. */
1799	uint32_t u3Available : 3;
1800	/** Physical Page number of the next level - Low Part. Don't use! */
1801	uint32_t u20PageNoLow : 20;
1802	/** Physical Page number of the next level - High Part. Don't use! */
1803	uint32_t u20PageNoHigh : 20;
1804	/** MBZ bits */
1805	uint32_t u11Reserved : 11;
1806	/** No Execute flag. */
1807	uint32_t u1NoExecute : 1;
1808	} X86PML4EBITS;
1809	/** Pointer to a page map level-4 entry. */
1810	typedef X86PML4EBITS *PX86PML4EBITS;
1811	/** Pointer to a const page map level-4 entry. */
1812	typedef const X86PML4EBITS *PCX86PML4EBITS;
1813
1814	/**
1815	* Page Map Level-4 Entry.
1816	*/
1817	typedef union X86PML4E
1818	{
1819	/** Unsigned integer view. */
1820	X86PGPAEUINT u;
1821	/** Normal view. */
1822	X86PML4EBITS n;
1823	/** 8 bit unsigned integer view. */
1824	uint8_t au8[8];
1825	/** 16 bit unsigned integer view. */
1826	uint16_t au16[4];
1827	/** 32 bit unsigned integer view. */
1828	uint32_t au32[2];
1829	} X86PML4E;
1830	/** Pointer to a page map level-4 entry. */
1831	typedef X86PML4E *PX86PML4E;
1832	/** Pointer to a const page map level-4 entry. */
1833	typedef const X86PML4E *PCX86PML4E;
1834
1835
1836	/**
1837	* Page Map Level-4.
1838	*/
1839	typedef struct X86PML4
1840	{
1841	/** PDE Array. */
1842	X86PML4E a[X86_PG_PAE_ENTRIES];
1843	} X86PML4;
1844	/** Pointer to a page map level-4. */
1845	typedef X86PML4 *PX86PML4;
1846	/** Pointer to a const page map level-4. */
1847	typedef const X86PML4 *PCX86PML4;
1848
1849	/** The page shift to get the PML4 index. */
1850	#define X86_PML4_SHIFT 39
1851	/** The PML4 index mask (apply to a shifted page address). */
1852	#define X86_PML4_MASK 0x1ff
1853
1854	/** @} */
1855
1856	/** @} */
1857
1858
1859	/**
1860	* 80-bit MMX/FPU register type.
1861	*/
1862	typedef struct X86FPUMMX
1863	{
1864	uint8_t reg[10];
1865	} X86FPUMMX;
1866	/** Pointer to a 80-bit MMX/FPU register type. */
1867	typedef X86FPUMMX *PX86FPUMMX;
1868	/** Pointer to a const 80-bit MMX/FPU register type. */
1869	typedef const X86FPUMMX *PCX86FPUMMX;
1870
1871	/**
1872	* FPU state (aka FSAVE/FRSTOR Memory Region).
1873	*/
1874	#pragma pack(1)
1875	typedef struct X86FPUSTATE
1876	{
1877	/** Control word. */
1878	uint16_t FCW;
1879	/** Alignment word */
1880	uint16_t Dummy1;
1881	/** Status word. */
1882	uint16_t FSW;
1883	/** Alignment word */
1884	uint16_t Dummy2;
1885	/** Tag word */
1886	uint16_t FTW;
1887	/** Alignment word */
1888	uint16_t Dummy3;
1889
1890	/** Instruction pointer. */
1891	uint32_t FPUIP;
1892	/** Code selector. */
1893	uint16_t CS;
1894	/** Opcode. */
1895	uint16_t FOP;
1896	/** FOO. */
1897	uint32_t FPUOO;
1898	/** FOS. */
1899	uint32_t FPUOS;
1900	/** FPU view - todo. */
1901	X86FPUMMX regs[8];
1902	} X86FPUSTATE;
1903	#pragma pack()
1904	/** Pointer to a FPU state. */
1905	typedef X86FPUSTATE *PX86FPUSTATE;
1906	/** Pointer to a const FPU state. */
1907	typedef const X86FPUSTATE *PCX86FPUSTATE;
1908
1909	/**
1910	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1911	*/
1912	#pragma pack(1)
1913	typedef struct X86FXSTATE
1914	{
1915	/** Control word. */
1916	uint16_t FCW;
1917	/** Status word. */
1918	uint16_t FSW;
1919	/** Tag word. (The upper byte is always zero.) */
1920	uint16_t FTW;
1921	/** Opcode. */
1922	uint16_t FOP;
1923	/** Instruction pointer. */
1924	uint32_t FPUIP;
1925	/** Code selector. */
1926	uint16_t CS;
1927	uint16_t Rsvrd1;
1928	/* - offset 16 - */
1929	/** Data pointer. */
1930	uint32_t FPUDP;
1931	/** Data segment */
1932	uint16_t DS;
1933	uint16_t Rsrvd2;
1934	uint32_t MXCSR;
1935	uint32_t MXCSR_MASK;
1936	/* - offset 32 - */
1937	union
1938	{
1939	/** MMX view. */
1940	uint64_t mmx;
1941	/** FPU view - todo. */
1942	X86FPUMMX fpu;
1943	/** 8-bit view. */
1944	uint8_t au8[16];
1945	/** 16-bit view. */
1946	uint16_t au16[8];
1947	/** 32-bit view. */
1948	uint32_t au32[4];
1949	/** 64-bit view. */
1950	uint64_t au64[2];
1951	/** 128-bit view. (yeah, very helpful) */
1952	uint128_t au128[1];
1953	} aRegs[8];
1954	/* - offset 160 - */
1955	union
1956	{
1957	/** XMM Register view . /
1958	uint128_t xmm;
1959	/** 8-bit view. */
1960	uint8_t au8[16];
1961	/** 16-bit view. */
1962	uint16_t au16[8];
1963	/** 32-bit view. */
1964	uint32_t au32[4];
1965	/** 64-bit view. */
1966	uint64_t au64[2];
1967	/** 128-bit view. (yeah, very helpful) */
1968	uint128_t au128[1];
1969	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1970	/* - offset 416 - */
1971	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1972	} X86FXSTATE;
1973	#pragma pack()
1974	/** Pointer to a FPU Extended state. */
1975	typedef X86FXSTATE *PX86FXSTATE;
1976	/** Pointer to a const FPU Extended state. */
1977	typedef const X86FXSTATE *PCX86FXSTATE;
1978
1979
1980	/** @name Selector Descriptor
1981	* @{
1982	*/
1983
1984	/**
1985	* Descriptor attributes.
1986	*/
1987	typedef struct X86DESCATTRBITS
1988	{
1989	/** 00 - Segment Type. */
1990	unsigned u4Type : 4;
1991	/** 04 - Descriptor Type. System(=0) or code/data selector */
1992	unsigned u1DescType : 1;
1993	/** 05 - Descriptor Privelege level. */
1994	unsigned u2Dpl : 2;
1995	/** 07 - Flags selector present(=1) or not. */
1996	unsigned u1Present : 1;
1997	/** 08 - Segment limit 16-19. */
1998	unsigned u4LimitHigh : 4;
1999	/** 0c - Available for system software. */
2000	unsigned u1Available : 1;
2001	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2002	unsigned u1Long : 1;
2003	/** 0e - This flags meaning depends on the segment type. Try make sense out
2004	* of the intel manual yourself. */
2005	unsigned u1DefBig : 1;
2006	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2007	* clear byte. */
2008	unsigned u1Granularity : 1;
2009	} X86DESCATTRBITS;
2010
2011
2012	#pragma pack(1)
2013	typedef union X86DESCATTR
2014	{
2015	/** Unsigned integer view. */
2016	uint32_t u;
2017	/** Normal view. */
2018	X86DESCATTRBITS n;
2019	} X86DESCATTR;
2020	#pragma pack()
2021	/** Pointer to descriptor attributes. */
2022	typedef X86DESCATTR *PX86DESCATTR;
2023	/** Pointer to const descriptor attributes. */
2024	typedef const X86DESCATTR *PCX86DESCATTR;
2025
2026
2027	/**
2028	* Generic descriptor table entry
2029	*/
2030	#pragma pack(1)
2031	typedef struct X86DESCGENERIC
2032	{
2033	/** Limit - Low word. */
2034	unsigned u16LimitLow : 16;
2035	/** Base address - lowe word.
2036	* Don't try set this to 24 because MSC is doing stupid things then. */
2037	unsigned u16BaseLow : 16;
2038	/** Base address - first 8 bits of high word. */
2039	unsigned u8BaseHigh1 : 8;
2040	/** Segment Type. */
2041	unsigned u4Type : 4;
2042	/** Descriptor Type. System(=0) or code/data selector */
2043	unsigned u1DescType : 1;
2044	/** Descriptor Privelege level. */
2045	unsigned u2Dpl : 2;
2046	/** Flags selector present(=1) or not. */
2047	unsigned u1Present : 1;
2048	/** Segment limit 16-19. */
2049	unsigned u4LimitHigh : 4;
2050	/** Available for system software. */
2051	unsigned u1Available : 1;
2052	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2053	unsigned u1Long : 1;
2054	/** This flags meaning depends on the segment type. Try make sense out
2055	* of the intel manual yourself. */
2056	unsigned u1DefBig : 1;
2057	/** Granularity of the limit. If set 4KB granularity is used, if
2058	* clear byte. */
2059	unsigned u1Granularity : 1;
2060	/** Base address - highest 8 bits. */
2061	unsigned u8BaseHigh2 : 8;
2062	} X86DESCGENERIC;
2063	#pragma pack()
2064	/** Pointer to a generic descriptor entry. */
2065	typedef X86DESCGENERIC *PX86DESCGENERIC;
2066	/** Pointer to a const generic descriptor entry. */
2067	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2068
2069	/**
2070	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2071	*/
2072	typedef struct X86DESCGATE
2073	{
2074	/** Target code segment offset - Low word.
2075	* Ignored if task-gate. */
2076	unsigned u16OffsetLow : 16;
2077	/** Target code segment selector for call-, interrupt- and trap-gates,
2078	* TSS selector if task-gate. */
2079	unsigned u16Sel : 16;
2080	/** Number of parameters for a call-gate.
2081	* Ignored if interrupt-, trap- or task-gate. */
2082	unsigned u4ParmCount : 4;
2083	/** Reserved / ignored. */
2084	unsigned u4Reserved : 4;
2085	/** Segment Type. */
2086	unsigned u4Type : 4;
2087	/** Descriptor Type (0 = system). */
2088	unsigned u1DescType : 1;
2089	/** Descriptor Privelege level. */
2090	unsigned u2Dpl : 2;
2091	/** Flags selector present(=1) or not. */
2092	unsigned u1Present : 1;
2093	/** Target code segment offset - High word.
2094	* Ignored if task-gate. */
2095	unsigned u16OffsetHigh : 16;
2096	} X86DESCGATE;
2097	AssertCompileSize(X86DESCGATE, 8);
2098	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2099	typedef X86DESCGATE *PX86DESCGATE;
2100	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2101	typedef const X86DESCGATE *PCX86DESCGATE;
2102
2103	/**
2104	* Descriptor table entry.
2105	*/
2106	#pragma pack(1)
2107	typedef union X86DESC
2108	{
2109	/** Generic descriptor view. */
2110	X86DESCGENERIC Gen;
2111	/** Gate descriptor view. */
2112	X86DESCGATE Gate;
2113
2114	/** 8 bit unsigned interger view. */
2115	uint8_t au8[8];
2116	/** 16 bit unsigned interger view. */
2117	uint16_t au16[4];
2118	/** 32 bit unsigned interger view. */
2119	uint32_t au32[2];
2120	} X86DESC;
2121	AssertCompileSize(X86DESC, 8);
2122	#pragma pack()
2123	/** Pointer to descriptor table entry. */
2124	typedef X86DESC *PX86DESC;
2125	/** Pointer to const descriptor table entry. */
2126	typedef const X86DESC *PCX86DESC;
2127
2128	/** @def X86DESC_BASE
2129	* Return the base address of a descriptor.
2130	*/
2131	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2132	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2133	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2134	\| ( (desc).Gen.u16BaseLow ) )
2135
2136	/** @def X86DESC_LIMIT
2137	* Return the limit of a descriptor.
2138	*/
2139	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2140	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2141	\| ( (desc).Gen.u16LimitLow ) )
2142
2143	/**
2144	* 64 bits generic descriptor table entry
2145	* Note: most of these bits have no meaning in long mode.
2146	*/
2147	#pragma pack(1)
2148	typedef struct X86DESC64GENERIC
2149	{
2150	/** Limit - Low word - IGNORED. */
2151	unsigned u16LimitLow : 16;
2152	/** Base address - lowe word. - IGNORED
2153	* Don't try set this to 24 because MSC is doing stupid things then. */
2154	unsigned u16BaseLow : 16;
2155	/** Base address - first 8 bits of high word. - IGNORED */
2156	unsigned u8BaseHigh1 : 8;
2157	/** Segment Type. */
2158	unsigned u4Type : 4;
2159	/** Descriptor Type. System(=0) or code/data selector */
2160	unsigned u1DescType : 1;
2161	/** Descriptor Privelege level. */
2162	unsigned u2Dpl : 2;
2163	/** Flags selector present(=1) or not. */
2164	unsigned u1Present : 1;
2165	/** Segment limit 16-19. - IGNORED */
2166	unsigned u4LimitHigh : 4;
2167	/** Available for system software. - IGNORED */
2168	unsigned u1Available : 1;
2169	/** Long mode flag. */
2170	unsigned u1Long : 1;
2171	/** This flags meaning depends on the segment type. Try make sense out
2172	* of the intel manual yourself. */
2173	unsigned u1DefBig : 1;
2174	/** Granularity of the limit. If set 4KB granularity is used, if
2175	* clear byte. - IGNORED */
2176	unsigned u1Granularity : 1;
2177	/** Base address - highest 8 bits. - IGNORED */
2178	unsigned u8BaseHigh2 : 8;
2179	/** Base address - bits 63-32. */
2180	unsigned u32BaseHigh3 : 32;
2181	unsigned u8Reserved : 8;
2182	unsigned u5Zeros : 5;
2183	unsigned u19Reserved : 19;
2184	} X86DESC64GENERIC;
2185	#pragma pack()
2186	/** Pointer to a generic descriptor entry. */
2187	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2188	/** Pointer to a const generic descriptor entry. */
2189	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2190
2191	/**
2192	* System descriptor table entry (64 bits)
2193	*
2194	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2195	*/
2196	#pragma pack(1)
2197	typedef struct X86DESC64SYSTEM
2198	{
2199	/** Limit - Low word. */
2200	unsigned u16LimitLow : 16;
2201	/** Base address - lowe word.
2202	* Don't try set this to 24 because MSC is doing stupid things then. */
2203	unsigned u16BaseLow : 16;
2204	/** Base address - first 8 bits of high word. */
2205	unsigned u8BaseHigh1 : 8;
2206	/** Segment Type. */
2207	unsigned u4Type : 4;
2208	/** Descriptor Type. System(=0) or code/data selector */
2209	unsigned u1DescType : 1;
2210	/** Descriptor Privelege level. */
2211	unsigned u2Dpl : 2;
2212	/** Flags selector present(=1) or not. */
2213	unsigned u1Present : 1;
2214	/** Segment limit 16-19. */
2215	unsigned u4LimitHigh : 4;
2216	/** Available for system software. */
2217	unsigned u1Available : 1;
2218	/** Reserved - 0. */
2219	unsigned u1Reserved : 1;
2220	/** This flags meaning depends on the segment type. Try make sense out
2221	* of the intel manual yourself. */
2222	unsigned u1DefBig : 1;
2223	/** Granularity of the limit. If set 4KB granularity is used, if
2224	* clear byte. */
2225	unsigned u1Granularity : 1;
2226	/** Base address - bits 31-24. */
2227	unsigned u8BaseHigh2 : 8;
2228	/** Base address - bits 63-32. */
2229	unsigned u32BaseHigh3 : 32;
2230	unsigned u8Reserved : 8;
2231	unsigned u5Zeros : 5;
2232	unsigned u19Reserved : 19;
2233	} X86DESC64SYSTEM;
2234	#pragma pack()
2235	/** Pointer to a system descriptor entry. */
2236	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2237	/** Pointer to a const system descriptor entry. */
2238	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2239
2240	/**
2241	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2242	*/
2243	typedef struct X86DESC64GATE
2244	{
2245	/** Target code segment offset - Low word. */
2246	unsigned u16OffsetLow : 16;
2247	/** Target code segment selector. */
2248	unsigned u16Sel : 16;
2249	/** Interrupt stack table for interrupt- and trap-gates.
2250	* Ignored by call-gates. */
2251	unsigned u3IST : 3;
2252	/** Reserved / ignored. */
2253	unsigned u5Reserved : 5;
2254	/** Segment Type. */
2255	unsigned u4Type : 4;
2256	/** Descriptor Type (0 = system). */
2257	unsigned u1DescType : 1;
2258	/** Descriptor Privelege level. */
2259	unsigned u2Dpl : 2;
2260	/** Flags selector present(=1) or not. */
2261	unsigned u1Present : 1;
2262	/** Target code segment offset - High word.
2263	* Ignored if task-gate. */
2264	unsigned u16OffsetHigh : 16;
2265	/** Target code segment offset - Top dword.
2266	* Ignored if task-gate. */
2267	unsigned u32OffsetTop : 32;
2268	/** Reserved / ignored / must be zero.
2269	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2270	unsigned u32Reserved : 32;
2271	} X86DESC64GATE;
2272	AssertCompileSize(X86DESC64GATE, 16);
2273	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2274	typedef X86DESC64GATE *PX86DESC64GATE;
2275	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2276	typedef const X86DESC64GATE *PCX86DESC64GATE;
2277
2278
2279	/**
2280	* Descriptor table entry.
2281	*/
2282	#pragma pack(1)
2283	typedef union X86DESC64
2284	{
2285	/** Generic descriptor view. */
2286	X86DESC64GENERIC Gen;
2287	/** System descriptor view. */
2288	X86DESC64SYSTEM System;
2289	/** Gate descriptor view. */
2290	X86DESC64GATE Gate;
2291
2292	/** 8 bit unsigned interger view. */
2293	uint8_t au8[16];
2294	/** 16 bit unsigned interger view. */
2295	uint16_t au16[8];
2296	/** 32 bit unsigned interger view. */
2297	uint32_t au32[4];
2298	/** 64 bit unsigned interger view. */
2299	uint64_t au64[2];
2300	} X86DESC64;
2301	AssertCompileSize(X86DESC64, 16);
2302	#pragma pack()
2303	/** Pointer to descriptor table entry. */
2304	typedef X86DESC64 *PX86DESC64;
2305	/** Pointer to const descriptor table entry. */
2306	typedef const X86DESC64 *PCX86DESC64;
2307
2308	/** @def X86DESC64_BASE
2309	* Return the base of a 64-bit descriptor.
2310	*/
2311	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2312	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2313	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2314	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2315	\| ( (desc).Gen.u16BaseLow ) )
2316
2317
2318
2319	/** @name Host system descriptor table entry - Use with care!
2320	* @{ */
2321	/** Host system descriptor table entry. */
2322	#if HC_ARCH_BITS == 64
2323	typedef X86DESC64 X86DESCHC;
2324	#else
2325	typedef X86DESC X86DESCHC;
2326	#endif
2327	/** Pointer to a host system descriptor table entry. */
2328	#if HC_ARCH_BITS == 64
2329	typedef PX86DESC64 PX86DESCHC;
2330	#else
2331	typedef PX86DESC PX86DESCHC;
2332	#endif
2333	/** Pointer to a const host system descriptor table entry. */
2334	#if HC_ARCH_BITS == 64
2335	typedef PCX86DESC64 PCX86DESCHC;
2336	#else
2337	typedef PCX86DESC PCX86DESCHC;
2338	#endif
2339	/** @} */
2340
2341
2342	/** @name Selector Descriptor Types.
2343	* @{
2344	*/
2345
2346	/** @name Non-System Selector Types.
2347	* @{ */
2348	/** Code(=set)/Data(=clear) bit. */
2349	#define X86_SEL_TYPE_CODE 8
2350	/** Memory(=set)/System(=clear) bit. */
2351	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2352	/** Accessed bit. */
2353	#define X86_SEL_TYPE_ACCESSED 1
2354	/** Expand down bit (for data selectors only). */
2355	#define X86_SEL_TYPE_DOWN 4
2356	/** Conforming bit (for code selectors only). */
2357	#define X86_SEL_TYPE_CONF 4
2358	/** Write bit (for data selectors only). */
2359	#define X86_SEL_TYPE_WRITE 2
2360	/** Read bit (for code selectors only). */
2361	#define X86_SEL_TYPE_READ 2
2362
2363	/** Read only selector type. */
2364	#define X86_SEL_TYPE_RO 0
2365	/** Accessed read only selector type. */
2366	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2367	/** Read write selector type. */
2368	#define X86_SEL_TYPE_RW 2
2369	/** Accessed read write selector type. */
2370	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2371	/** Expand down read only selector type. */
2372	#define X86_SEL_TYPE_RO_DOWN 4
2373	/** Accessed expand down read only selector type. */
2374	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2375	/** Expand down read write selector type. */
2376	#define X86_SEL_TYPE_RW_DOWN 6
2377	/** Accessed expand down read write selector type. */
2378	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2379	/** Execute only selector type. */
2380	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2381	/** Accessed execute only selector type. */
2382	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2383	/** Execute and read selector type. */
2384	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2385	/** Accessed execute and read selector type. */
2386	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2387	/** Conforming execute only selector type. */
2388	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2389	/** Accessed Conforming execute only selector type. */
2390	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2391	/** Conforming execute and write selector type. */
2392	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2393	/** Accessed Conforming execute and write selector type. */
2394	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2395	/** @} */
2396
2397
2398	/** @name System Selector Types.
2399	* @{ */
2400	/** Undefined system selector type. */
2401	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2402	/** 286 TSS selector. */
2403	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2404	/** LDT selector. */
2405	#define X86_SEL_TYPE_SYS_LDT 2
2406	/** 286 TSS selector - Busy. */
2407	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2408	/** 286 Callgate selector. */
2409	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2410	/** Taskgate selector. */
2411	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2412	/** 286 Interrupt gate selector. */
2413	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2414	/** 286 Trapgate selector. */
2415	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2416	/** Undefined system selector. */
2417	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2418	/** 386 TSS selector. */
2419	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2420	/** Undefined system selector. */
2421	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2422	/** 386 TSS selector - Busy. */
2423	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2424	/** 386 Callgate selector. */
2425	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2426	/** Undefined system selector. */
2427	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2428	/** 386 Interruptgate selector. */
2429	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2430	/** 386 Trapgate selector. */
2431	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2432	/** @} */
2433
2434	/** @name AMD64 System Selector Types.
2435	* @{ */
2436	#define AMD64_SEL_TYPE_SYS_LDT 2
2437	/** 286 TSS selector - Busy. */
2438	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2439	/** 386 TSS selector - Busy. */
2440	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2441	/** 386 Callgate selector. */
2442	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2443	/** 386 Interruptgate selector. */
2444	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2445	/** 386 Trapgate selector. */
2446	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2447	/** @} */
2448
2449	/** @} */
2450
2451
2452	/** @name Descriptor Table Entry Flag Masks.
2453	* These are for the 2nd 32-bit word of a descriptor.
2454	* @{ */
2455	/** Bits 8-11 - TYPE - Descriptor type mask. */
2456	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2457	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2458	#define X86_DESC_S RT_BIT(12)
2459	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2460	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2461	/** Bit 15 - P - Present. */
2462	#define X86_DESC_P RT_BIT(15)
2463	/** Bit 20 - AVL - Available for system software. */
2464	#define X86_DESC_AVL RT_BIT(20)
2465	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2466	#define X86_DESC_DB RT_BIT(22)
2467	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2468	* used, if clear byte. */
2469	#define X86_DESC_G RT_BIT(23)
2470	/** @} */
2471
2472	/** @} */
2473
2474	/** @name Task segment.
2475	* @{
2476	*/
2477	#pragma pack(1)
2478	typedef struct X86TSS32
2479	{
2480	/** Back link to previous task. (static) */
2481	RTSEL selPrev;
2482	uint16_t padding1;
2483	/** Ring-0 stack pointer. (static) */
2484	uint32_t esp0;
2485	/** Ring-0 stack segment. (static) */
2486	RTSEL ss0;
2487	uint16_t padding_ss0;
2488	/** Ring-1 stack pointer. (static) */
2489	uint32_t esp1;
2490	/** Ring-1 stack segment. (static) */
2491	RTSEL ss1;
2492	uint16_t padding_ss1;
2493	/** Ring-2 stack pointer. (static) */
2494	uint32_t esp2;
2495	/** Ring-2 stack segment. (static) */
2496	RTSEL ss2;
2497	uint16_t padding_ss2;
2498	/** Page directory for the task. (static) */
2499	uint32_t cr3;
2500	/** EIP before task switch. */
2501	uint32_t eip;
2502	/** EFLAGS before task switch. */
2503	uint32_t eflags;
2504	/** EAX before task switch. */
2505	uint32_t eax;
2506	/** ECX before task switch. */
2507	uint32_t ecx;
2508	/** EDX before task switch. */
2509	uint32_t edx;
2510	/** EBX before task switch. */
2511	uint32_t ebx;
2512	/** ESP before task switch. */
2513	uint32_t esp;
2514	/** EBP before task switch. */
2515	uint32_t ebp;
2516	/** ESI before task switch. */
2517	uint32_t esi;
2518	/** EDI before task switch. */
2519	uint32_t edi;
2520	/** ES before task switch. */
2521	RTSEL es;
2522	uint16_t padding_es;
2523	/** CS before task switch. */
2524	RTSEL cs;
2525	uint16_t padding_cs;
2526	/** SS before task switch. */
2527	RTSEL ss;
2528	uint16_t padding_ss;
2529	/** DS before task switch. */
2530	RTSEL ds;
2531	uint16_t padding_ds;
2532	/** FS before task switch. */
2533	RTSEL fs;
2534	uint16_t padding_fs;
2535	/** GS before task switch. */
2536	RTSEL gs;
2537	uint16_t padding_gs;
2538	/** LDTR before task switch. */
2539	RTSEL selLdt;
2540	uint16_t padding_ldt;
2541	/** Debug trap flag */
2542	uint16_t fDebugTrap;
2543	/** Offset relative to the TSS of the start of the I/O Bitmap
2544	* and the end of the interrupt redirection bitmap. */
2545	uint16_t offIoBitmap;
2546	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2547	uint8_t IntRedirBitmap[32];
2548	} X86TSS32;
2549	#pragma pack()
2550	/** Pointer to task segment. */
2551	typedef X86TSS32 *PX86TSS32;
2552	/** Pointer to const task segment. */
2553	typedef const X86TSS32 *PCX86TSS32;
2554	/** @} */
2555
2556
2557	/** @name 64 bits Task segment.
2558	* @{
2559	*/
2560	#pragma pack(1)
2561	typedef struct X86TSS64
2562	{
2563	/** Reserved. */
2564	uint32_t u32Reserved;
2565	/** Ring-0 stack pointer. (static) */
2566	uint64_t rsp0;
2567	/** Ring-1 stack pointer. (static) */
2568	uint64_t rsp1;
2569	/** Ring-2 stack pointer. (static) */
2570	uint64_t rsp2;
2571	/** Reserved. */
2572	uint32_t u32Reserved2[2];
2573	/* IST */
2574	uint64_t ist1;
2575	uint64_t ist2;
2576	uint64_t ist3;
2577	uint64_t ist4;
2578	uint64_t ist5;
2579	uint64_t ist6;
2580	uint64_t ist7;
2581	/* Reserved. */
2582	uint16_t u16Reserved[5];
2583	/** Offset relative to the TSS of the start of the I/O Bitmap
2584	* and the end of the interrupt redirection bitmap. */
2585	uint16_t offIoBitmap;
2586	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2587	uint8_t IntRedirBitmap[32];
2588	} X86TSS64;
2589	#pragma pack()
2590	/** Pointer to task segment. */
2591	typedef X86TSS64 *PX86TSS64;
2592	/** Pointer to const task segment. */
2593	typedef const X86TSS64 *PCX86TSS64;
2594	AssertCompileSize(X86TSS64, 136);
2595
2596	/** @} */
2597
2598
2599	/** @name Selectors.
2600	* @{
2601	*/
2602
2603	/**
2604	* The shift used to convert a selector from and to index an index (C).
2605	*/
2606	#define X86_SEL_SHIFT 3
2607
2608	/**
2609	* The mask used to mask off the table indicator and CPL of an selector.
2610	*/
2611	#define X86_SEL_MASK 0xfff8
2612
2613	/**
2614	* The bit indicating that a selector is in the LDT and not in the GDT.
2615	*/
2616	#define X86_SEL_LDT 0x0004
2617	/**
2618	* The bit mask for getting the RPL of a selector.
2619	*/
2620	#define X86_SEL_RPL 0x0003
2621
2622	/** @} */
2623
2624
2625	/**
2626	* x86 Exceptions/Faults/Traps.
2627	*/
2628	typedef enum X86XCPT
2629	{
2630	/** \#DE - Divide error. */
2631	X86_XCPT_DE = 0x00,
2632	/** \#DB - Debug event (single step, DRx, ..) */
2633	X86_XCPT_DB = 0x01,
2634	/** NMI - Non-Maskable Interrupt */
2635	X86_XCPT_NMI = 0x02,
2636	/** \#BP - Breakpoint (INT3). */
2637	X86_XCPT_BP = 0x03,
2638	/** \#OF - Overflow (INTO). */
2639	X86_XCPT_OF = 0x04,
2640	/** \#BR - Bound range exceeded (BOUND). */
2641	X86_XCPT_BR = 0x05,
2642	/** \#UD - Undefined opcode. */
2643	X86_XCPT_UD = 0x06,
2644	/** \#NM - Device not available (math coprocessor device). */
2645	X86_XCPT_NM = 0x07,
2646	/** \#DF - Double fault. */
2647	X86_XCPT_DF = 0x08,
2648	/** ??? - Coprocessor segment overrun (obsolete). */
2649	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2650	/** \#TS - Taskswitch (TSS). */
2651	X86_XCPT_TS = 0x0a,
2652	/** \#NP - Segment no present. */
2653	X86_XCPT_NP = 0x0b,
2654	/** \#SS - Stack segment fault. */
2655	X86_XCPT_SS = 0x0c,
2656	/** \#GP - General protection fault. */
2657	X86_XCPT_GP = 0x0d,
2658	/** \#PF - Page fault. */
2659	X86_XCPT_PF = 0x0e,
2660	/* 0x0f is reserved. */
2661	/** \#MF - Math fault (FPU). */
2662	X86_XCPT_MF = 0x10,
2663	/** \#AC - Alignment check. */
2664	X86_XCPT_AC = 0x11,
2665	/** \#MC - Machine check. */
2666	X86_XCPT_MC = 0x12,
2667	/** \#XF - SIMD Floating-Pointer Exception. */
2668	X86_XCPT_XF = 0x13
2669	} X86XCPT;
2670	/** Pointer to a x86 exception code. */
2671	typedef X86XCPT *PX86XCPT;
2672	/** Pointer to a const x86 exception code. */
2673	typedef const X86XCPT *PCX86XCPT;
2674
2675
2676	/** @name Trap Error Codes
2677	* @{
2678	*/
2679	/** External indicator. */
2680	#define X86_TRAP_ERR_EXTERNAL 1
2681	/** IDT indicator. */
2682	#define X86_TRAP_ERR_IDT 2
2683	/** Descriptor table indicator - If set LDT, if clear GDT. */
2684	#define X86_TRAP_ERR_TI 4
2685	/** Mask for getting the selector. */
2686	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2687	/** Shift for getting the selector table index (C type index). */
2688	#define X86_TRAP_ERR_SEL_SHIFT 3
2689	/** @} */
2690
2691
2692	/** @name \#PF Trap Error Codes
2693	* @{
2694	*/
2695	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2696	#define X86_TRAP_PF_P RT_BIT(0)
2697	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2698	#define X86_TRAP_PF_RW RT_BIT(1)
2699	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2700	#define X86_TRAP_PF_US RT_BIT(2)
2701	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2702	#define X86_TRAP_PF_RSVD RT_BIT(3)
2703	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2704	#define X86_TRAP_PF_ID RT_BIT(4)
2705	/** @} */
2706
2707	#pragma pack(1)
2708	/**
2709	* 32-bit IDTR/GDTR.
2710	*/
2711	typedef struct X86XDTR32
2712	{
2713	/** Size of the descriptor table. */
2714	uint16_t cb;
2715	/** Address of the descriptor table. */
2716	uint32_t uAddr;
2717	} X86XDTR32, *PX86XDTR32;
2718	#pragma pack()
2719
2720	#pragma pack(1)
2721	/**
2722	* 64-bit IDTR/GDTR.
2723	*/
2724	typedef struct X86XDTR64
2725	{
2726	/** Size of the descriptor table. */
2727	uint16_t cb;
2728	/** Address of the descriptor table. */
2729	uint64_t uAddr;
2730	} X86XDTR64, *PX86XDTR64;
2731	#pragma pack()
2732
2733	/** @} */
2734
2735	#endif
2736

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source: vbox/trunk/include/VBox/x86.h@ 27459

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