x86.h@ 28065

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions (VMM,++).
3	*
4	* x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*
27	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
28	* Clara, CA 95054 USA or visit http://www.sun.com if you need
29	* additional information or have any questions.
30	*/
31
32	#ifndef ___VBox_x86_h
33	#define ___VBox_x86_h
34
35	#include <VBox/types.h>
36	#include <iprt/assert.h>
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_x86 x86 Types and Definitions
45	* @{
46	*/
47
48	/**
49	* EFLAGS Bits.
50	*/
51	typedef struct X86EFLAGSBITS
52	{
53	/** Bit 0 - CF - Carry flag - Status flag. */
54	unsigned u1CF : 1;
55	/** Bit 1 - 1 - Reserved flag. */
56	unsigned u1Reserved0 : 1;
57	/** Bit 2 - PF - Parity flag - Status flag. */
58	unsigned u1PF : 1;
59	/** Bit 3 - 0 - Reserved flag. */
60	unsigned u1Reserved1 : 1;
61	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
62	unsigned u1AF : 1;
63	/** Bit 5 - 0 - Reserved flag. */
64	unsigned u1Reserved2 : 1;
65	/** Bit 6 - ZF - Zero flag - Status flag. */
66	unsigned u1ZF : 1;
67	/** Bit 7 - SF - Signed flag - Status flag. */
68	unsigned u1SF : 1;
69	/** Bit 8 - TF - Trap flag - System flag. */
70	unsigned u1TF : 1;
71	/** Bit 9 - IF - Interrupt flag - System flag. */
72	unsigned u1IF : 1;
73	/** Bit 10 - DF - Direction flag - Control flag. */
74	unsigned u1DF : 1;
75	/** Bit 11 - OF - Overflow flag - Status flag. */
76	unsigned u1OF : 1;
77	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
78	unsigned u2IOPL : 2;
79	/** Bit 14 - NT - Nested task flag - System flag. */
80	unsigned u1NT : 1;
81	/** Bit 15 - 0 - Reserved flag. */
82	unsigned u1Reserved3 : 1;
83	/** Bit 16 - RF - Resume flag - System flag. */
84	unsigned u1RF : 1;
85	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
86	unsigned u1VM : 1;
87	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
88	unsigned u1AC : 1;
89	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
90	unsigned u1VIF : 1;
91	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
92	unsigned u1VIP : 1;
93	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
94	unsigned u1ID : 1;
95	/** Bit 22-31 - 0 - Reserved flag. */
96	unsigned u10Reserved4 : 10;
97	} X86EFLAGSBITS;
98	/** Pointer to EFLAGS bits. */
99	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
100	/** Pointer to const EFLAGS bits. */
101	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
102
103	/**
104	* EFLAGS.
105	*/
106	typedef union X86EFLAGS
107	{
108	/** The plain unsigned view. */
109	uint32_t u;
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	} X86EFLAGS;
121	/** Pointer to EFLAGS. */
122	typedef X86EFLAGS *PX86EFLAGS;
123	/** Pointer to const EFLAGS. */
124	typedef const X86EFLAGS *PCX86EFLAGS;
125
126	/**
127	* RFLAGS (32 upper bits are reserved).
128	*/
129	typedef union X86RFLAGS
130	{
131	/** The plain unsigned view. */
132	uint64_t u;
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	} X86RFLAGS;
146	/** Pointer to RFLAGS. */
147	typedef X86RFLAGS *PX86RFLAGS;
148	/** Pointer to const RFLAGS. */
149	typedef const X86RFLAGS *PCX86RFLAGS;
150
151
152	/** @name EFLAGS
153	* @{
154	*/
155	/** Bit 0 - CF - Carry flag - Status flag. */
156	#define X86_EFL_CF RT_BIT(0)
157	/** Bit 2 - PF - Parity flag - Status flag. */
158	#define X86_EFL_PF RT_BIT(2)
159	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
160	#define X86_EFL_AF RT_BIT(4)
161	/** Bit 6 - ZF - Zero flag - Status flag. */
162	#define X86_EFL_ZF RT_BIT(6)
163	/** Bit 7 - SF - Signed flag - Status flag. */
164	#define X86_EFL_SF RT_BIT(7)
165	/** Bit 8 - TF - Trap flag - System flag. */
166	#define X86_EFL_TF RT_BIT(8)
167	/** Bit 9 - IF - Interrupt flag - System flag. */
168	#define X86_EFL_IF RT_BIT(9)
169	/** Bit 10 - DF - Direction flag - Control flag. */
170	#define X86_EFL_DF RT_BIT(10)
171	/** Bit 11 - OF - Overflow flag - Status flag. */
172	#define X86_EFL_OF RT_BIT(11)
173	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
174	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
175	/** Bit 14 - NT - Nested task flag - System flag. */
176	#define X86_EFL_NT RT_BIT(14)
177	/** Bit 16 - RF - Resume flag - System flag. */
178	#define X86_EFL_RF RT_BIT(16)
179	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
180	#define X86_EFL_VM RT_BIT(17)
181	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
182	#define X86_EFL_AC RT_BIT(18)
183	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
184	#define X86_EFL_VIF RT_BIT(19)
185	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
186	#define X86_EFL_VIP RT_BIT(20)
187	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
188	#define X86_EFL_ID RT_BIT(21)
189	/** IOPL shift. */
190	#define X86_EFL_IOPL_SHIFT 12
191	/** The the IOPL level from the flags. */
192	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
193	/** Bits restored by popf */
194	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u1Reserved1 : 1;
207	/** Bit 2 - DS Area 64-bit layout. */
208	unsigned u1DTE64 : 1;
209	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
210	unsigned u1Monitor : 1;
211	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
212	unsigned u1CPLDS : 1;
213	/** Bit 5 - VMX - Virtual Machine Technology. */
214	unsigned u1VMX : 1;
215	/** Bit 6 - SMX: Safer Mode Extensions. */
216	unsigned u1SMX : 1;
217	/** Bit 7 - EST - Enh. SpeedStep Tech. */
218	unsigned u1EST : 1;
219	/** Bit 8 - TM2 - Terminal Monitor 2. */
220	unsigned u1TM2 : 1;
221	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
222	unsigned u1SSSE3 : 1;
223	/** Bit 10 - CNTX-ID - L1 Context ID. */
224	unsigned u1CNTXID : 1;
225	/** Bit 11 - FMA. */
226	unsigned u1FMA : 1;
227	/** Bit 12 - Reserved. */
228	unsigned u1Reserved2 : 1;
229	/** Bit 13 - CX16 - CMPXCHG16B. */
230	unsigned u1CX16 : 1;
231	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
232	unsigned u1TPRUpdate : 1;
233	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
234	unsigned u1PDCM : 1;
235	/** Reserved. */
236	unsigned u2Reserved3 : 2;
237	/** Bit 18 - Direct Cache Access. */
238	unsigned u1DCA : 1;
239	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
240	unsigned u1SSE4_1 : 1;
241	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
242	unsigned u1SSE4_2 : 1;
243	/** Bit 21 - x2APIC. */
244	unsigned u1x2APIC : 1;
245	/** Bit 22 - MOVBE - Supports MOVBE. */
246	unsigned u1MOVBE : 1;
247	/** Bit 23 - POPCNT - Supports POPCNT. */
248	unsigned u1POPCNT : 1;
249	/** Bit 24 - Reserved. */
250	unsigned u1Reserved4 : 1;
251	/** Bit 25 - AES. */
252	unsigned u1AES : 1;
253	/** Bit 26 - XSAVE - Supports XSAVE. */
254	unsigned u1XSAVE : 1;
255	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
256	unsigned u1OSXSAVE : 1;
257	/** Reserved. */
258	unsigned u4Reserved5 : 4;
259	} X86CPUIDFEATECX;
260	/** Pointer to CPUID Feature Information - ECX. */
261	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
262	/** Pointer to const CPUID Feature Information - ECX. */
263	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
264
265
266	/** CPUID Feature Information - EDX.
267	* CPUID query with EAX=1.
268	*/
269	typedef struct X86CPUIDFEATEDX
270	{
271	/** Bit 0 - FPU - x87 FPU on Chip. */
272	unsigned u1FPU : 1;
273	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
274	unsigned u1VME : 1;
275	/** Bit 2 - DE - Debugging extensions. */
276	unsigned u1DE : 1;
277	/** Bit 3 - PSE - Page Size Extension. */
278	unsigned u1PSE : 1;
279	/** Bit 4 - TSC - Time Stamp Counter. */
280	unsigned u1TSC : 1;
281	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
282	unsigned u1MSR : 1;
283	/** Bit 6 - PAE - Physical Address Extension. */
284	unsigned u1PAE : 1;
285	/** Bit 7 - MCE - Machine Check Exception. */
286	unsigned u1MCE : 1;
287	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
288	unsigned u1CX8 : 1;
289	/** Bit 9 - APIC - APIC On-Chip. */
290	unsigned u1APIC : 1;
291	/** Bit 10 - Reserved. */
292	unsigned u1Reserved1 : 1;
293	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
294	unsigned u1SEP : 1;
295	/** Bit 12 - MTRR - Memory Type Range Registers. */
296	unsigned u1MTRR : 1;
297	/** Bit 13 - PGE - PTE Global Bit. */
298	unsigned u1PGE : 1;
299	/** Bit 14 - MCA - Machine Check Architecture. */
300	unsigned u1MCA : 1;
301	/** Bit 15 - CMOV - Conditional Move Instructions. */
302	unsigned u1CMOV : 1;
303	/** Bit 16 - PAT - Page Attribute Table. */
304	unsigned u1PAT : 1;
305	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
306	unsigned u1PSE36 : 1;
307	/** Bit 18 - PSN - Processor Serial Number. */
308	unsigned u1PSN : 1;
309	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
310	unsigned u1CLFSH : 1;
311	/** Bit 20 - Reserved. */
312	unsigned u1Reserved2 : 1;
313	/** Bit 21 - DS - Debug Store. */
314	unsigned u1DS : 1;
315	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
316	unsigned u1ACPI : 1;
317	/** Bit 23 - MMX - Intel MMX 'Technology'. */
318	unsigned u1MMX : 1;
319	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
320	unsigned u1FXSR : 1;
321	/** Bit 25 - SSE - SSE Support. */
322	unsigned u1SSE : 1;
323	/** Bit 26 - SSE2 - SSE2 Support. */
324	unsigned u1SSE2 : 1;
325	/** Bit 27 - SS - Self Snoop. */
326	unsigned u1SS : 1;
327	/** Bit 28 - HTT - Hyper-Threading Technology. */
328	unsigned u1HTT : 1;
329	/** Bit 29 - TM - Thermal Monitor. */
330	unsigned u1TM : 1;
331	/** Bit 30 - Reserved - . */
332	unsigned u1Reserved3 : 1;
333	/** Bit 31 - PBE - Pending Break Enabled. */
334	unsigned u1PBE : 1;
335	} X86CPUIDFEATEDX;
336	/** Pointer to CPUID Feature Information - EDX. */
337	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
338	/** Pointer to const CPUID Feature Information - EDX. */
339	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
340
341	/** @name CPUID Vendor information.
342	* CPUID query with EAX=0.
343	* @{
344	*/
345	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
346	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
347	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
348
349	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
350	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
351	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
352	/** @} */
353
354
355	/** @name CPUID Feature information.
356	* CPUID query with EAX=1.
357	* @{
358	*/
359	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
360	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
361	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
362	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
363	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
364	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
365	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
366	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
367	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
368	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
369	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
370	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
371	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
372	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
373	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
374	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
375	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
376	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
377	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
378	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
379	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
380	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
381	/** ECX Bit 12 - FMA. */
382	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
383	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
384	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
385	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
386	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
387	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
388	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
389	/** ECX Bit 18 - DCA - Direct Cache Access. */
390	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
391	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
392	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
393	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
394	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
395	/** ECX Bit 21 - x2APIC support. */
396	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
397	/** ECX Bit 22 - MOVBE instruction. */
398	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
399	/** ECX Bit 23 - POPCNT instruction. */
400	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
401	/** ECX Bit 25 - AES instructions. */
402	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
403	/** ECX Bit 26 - XSAVE instruction. */
404	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
405	/** ECX Bit 27 - OSXSAVE instruction. */
406	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
407	/** ECX Bit 28 - AVX. */
408	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
409
410
411	/** Bit 0 - FPU - x87 FPU on Chip. */
412	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
413	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
414	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
415	/** Bit 2 - DE - Debugging extensions. */
416	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
417	/** Bit 3 - PSE - Page Size Extension. */
418	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
419	/** Bit 4 - TSC - Time Stamp Counter. */
420	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
421	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
422	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
423	/** Bit 6 - PAE - Physical Address Extension. */
424	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
425	/** Bit 7 - MCE - Machine Check Exception. */
426	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
427	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
428	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
429	/** Bit 9 - APIC - APIC On-Chip. */
430	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
431	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
432	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
433	/** Bit 12 - MTRR - Memory Type Range Registers. */
434	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
435	/** Bit 13 - PGE - PTE Global Bit. */
436	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
437	/** Bit 14 - MCA - Machine Check Architecture. */
438	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
439	/** Bit 15 - CMOV - Conditional Move Instructions. */
440	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
441	/** Bit 16 - PAT - Page Attribute Table. */
442	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
443	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
444	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
445	/** Bit 18 - PSN - Processor Serial Number. */
446	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
447	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
448	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
449	/** Bit 21 - DS - Debug Store. */
450	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
451	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
452	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
453	/** Bit 23 - MMX - Intel MMX Technology. */
454	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
455	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
456	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
457	/** Bit 25 - SSE - SSE Support. */
458	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
459	/** Bit 26 - SSE2 - SSE2 Support. */
460	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
461	/** Bit 27 - SS - Self Snoop. */
462	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
463	/** Bit 28 - HTT - Hyper-Threading Technology. */
464	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
465	/** Bit 29 - TM - Therm. Monitor. */
466	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
467	/** Bit 31 - PBE - Pending Break Enabled. */
468	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
469	/** @} */
470
471	/** @name CPUID mwait/monitor information.
472	* CPUID query with EAX=5.
473	* @{
474	*/
475	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
476	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
477	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
478	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
479	/** @} */
480
481
482	/** @name CPUID AMD Feature information.
483	* CPUID query with EAX=0x80000001.
484	* @{
485	*/
486	/** Bit 0 - FPU - x87 FPU on Chip. */
487	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
488	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
489	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
490	/** Bit 2 - DE - Debugging extensions. */
491	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
492	/** Bit 3 - PSE - Page Size Extension. */
493	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
494	/** Bit 4 - TSC - Time Stamp Counter. */
495	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
496	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
497	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
498	/** Bit 6 - PAE - Physical Address Extension. */
499	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
500	/** Bit 7 - MCE - Machine Check Exception. */
501	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
502	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
503	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
504	/** Bit 9 - APIC - APIC On-Chip. */
505	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
506	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
507	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
508	/** Bit 12 - MTRR - Memory Type Range Registers. */
509	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
510	/** Bit 13 - PGE - PTE Global Bit. */
511	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
512	/** Bit 14 - MCA - Machine Check Architecture. */
513	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
514	/** Bit 15 - CMOV - Conditional Move Instructions. */
515	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
516	/** Bit 16 - PAT - Page Attribute Table. */
517	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
518	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
519	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
520	/** Bit 20 - NX - AMD No-Execute Page Protection. */
521	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
522	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
523	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
524	/** Bit 23 - MMX - Intel MMX Technology. */
525	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
526	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
527	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
528	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
529	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
530	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
531	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
532	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
533	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
534	/** Bit 29 - LM - AMD Long Mode. */
535	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
536	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
537	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
538	/** Bit 31 - 3DNOW - AMD 3DNow. */
539	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
540
541	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
542	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
543	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
544	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
545	/** Bit 2 - SVM - AMD VM extensions. */
546	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
547	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
548	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
549	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
550	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
551	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
552	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
553	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
554	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
555	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
556	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
557	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
558	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
559	/** Bit 9 - OSVW - AMD OS visible workaround. */
560	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
561	/** Bit 10 - IBS - Instruct based sampling. */
562	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
563	/** Bit 11 - SSE5 - SSE5 instruction support. */
564	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
565	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
566	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
567	/** Bit 13 - WDT - AMD Watchdog timer support. */
568	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
569
570	/** @} */
571
572
573	/** @name CPUID AMD Feature information.
574	* CPUID query with EAX=0x80000007.
575	* @{
576	*/
577	/** Bit 0 - TS - Temperature Sensor. */
578	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
579	/** Bit 1 - FID - Frequency ID Control. */
580	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
581	/** Bit 2 - VID - Voltage ID Control. */
582	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
583	/** Bit 3 - TTP - THERMTRIP. */
584	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
585	/** Bit 4 - TM - Hardware Thermal Control. */
586	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
587	/** Bit 5 - STC - Software Thermal Control. */
588	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
589	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
590	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
591	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
592	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
593	/** Bit 8 - TSCINVAR - TSC Invariant. */
594	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
595	/** @} */
596
597
598	/** @name CR0
599	* @{ */
600	/** Bit 0 - PE - Protection Enabled */
601	#define X86_CR0_PE RT_BIT(0)
602	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
603	/** Bit 1 - MP - Monitor Coprocessor */
604	#define X86_CR0_MP RT_BIT(1)
605	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
606	/** Bit 2 - EM - Emulation. */
607	#define X86_CR0_EM RT_BIT(2)
608	#define X86_CR0_EMULATE_FPU RT_BIT(2)
609	/** Bit 3 - TS - Task Switch. */
610	#define X86_CR0_TS RT_BIT(3)
611	#define X86_CR0_TASK_SWITCH RT_BIT(3)
612	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
613	#define X86_CR0_ET RT_BIT(4)
614	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
615	/** Bit 5 - NE - Numeric error. */
616	#define X86_CR0_NE RT_BIT(5)
617	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
618	/** Bit 16 - WP - Write Protect. */
619	#define X86_CR0_WP RT_BIT(16)
620	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
621	/** Bit 18 - AM - Alignment Mask. */
622	#define X86_CR0_AM RT_BIT(18)
623	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
624	/** Bit 29 - NW - Not Write-though. */
625	#define X86_CR0_NW RT_BIT(29)
626	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
627	/** Bit 30 - WP - Cache Disable. */
628	#define X86_CR0_CD RT_BIT(30)
629	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
630	/** Bit 31 - PG - Paging. */
631	#define X86_CR0_PG RT_BIT(31)
632	#define X86_CR0_PAGING RT_BIT(31)
633	/** @} */
634
635
636	/** @name CR3
637	* @{ */
638	/** Bit 3 - PWT - Page-level Writes Transparent. */
639	#define X86_CR3_PWT RT_BIT(3)
640	/** Bit 4 - PCD - Page-level Cache Disable. */
641	#define X86_CR3_PCD RT_BIT(4)
642	/** Bits 12-31 - - Page directory page number. */
643	#define X86_CR3_PAGE_MASK (0xfffff000)
644	/** Bits 5-31 - - PAE Page directory page number. */
645	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
646	/** Bits 12-51 - - AMD64 Page directory page number. */
647	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
648	/** @} */
649
650
651	/** @name CR4
652	* @{ */
653	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
654	#define X86_CR4_VME RT_BIT(0)
655	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
656	#define X86_CR4_PVI RT_BIT(1)
657	/** Bit 2 - TSD - Time Stamp Disable. */
658	#define X86_CR4_TSD RT_BIT(2)
659	/** Bit 3 - DE - Debugging Extensions. */
660	#define X86_CR4_DE RT_BIT(3)
661	/** Bit 4 - PSE - Page Size Extension. */
662	#define X86_CR4_PSE RT_BIT(4)
663	/** Bit 5 - PAE - Physical Address Extension. */
664	#define X86_CR4_PAE RT_BIT(5)
665	/** Bit 6 - MCE - Machine-Check Enable. */
666	#define X86_CR4_MCE RT_BIT(6)
667	/** Bit 7 - PGE - Page Global Enable. */
668	#define X86_CR4_PGE RT_BIT(7)
669	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
670	#define X86_CR4_PCE RT_BIT(8)
671	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
672	#define X86_CR4_OSFSXR RT_BIT(9)
673	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
674	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
675	/** Bit 13 - VMXE - VMX mode is enabled. */
676	#define X86_CR4_VMXE RT_BIT(13)
677	/** @} */
678
679
680	/** @name DR6
681	* @{ */
682	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
683	#define X86_DR6_B0 RT_BIT(0)
684	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
685	#define X86_DR6_B1 RT_BIT(1)
686	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
687	#define X86_DR6_B2 RT_BIT(2)
688	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
689	#define X86_DR6_B3 RT_BIT(3)
690	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
691	#define X86_DR6_BD RT_BIT(13)
692	/** Bit 14 - BS - Single step */
693	#define X86_DR6_BS RT_BIT(14)
694	/** Bit 15 - BT - Task switch. (TSS T bit.) */
695	#define X86_DR6_BT RT_BIT(15)
696	/** Value of DR6 after powerup/reset. */
697	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
698	/** @} */
699
700
701	/** @name DR7
702	* @{ */
703	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
704	#define X86_DR7_L0 RT_BIT(0)
705	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
706	#define X86_DR7_G0 RT_BIT(1)
707	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
708	#define X86_DR7_L1 RT_BIT(2)
709	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
710	#define X86_DR7_G1 RT_BIT(3)
711	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
712	#define X86_DR7_L2 RT_BIT(4)
713	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
714	#define X86_DR7_G2 RT_BIT(5)
715	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
716	#define X86_DR7_L3 RT_BIT(6)
717	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
718	#define X86_DR7_G3 RT_BIT(7)
719	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
720	#define X86_DR7_LE RT_BIT(8)
721	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
722	#define X86_DR7_GE RT_BIT(9)
723
724	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
725	* any DR register is accessed. */
726	#define X86_DR7_GD RT_BIT(13)
727	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
728	#define X86_DR7_RW0_MASK (3 << 16)
729	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
730	#define X86_DR7_LEN0_MASK (3 << 18)
731	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
732	#define X86_DR7_RW1_MASK (3 << 20)
733	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
734	#define X86_DR7_LEN1_MASK (3 << 22)
735	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
736	#define X86_DR7_RW2_MASK (3 << 24)
737	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
738	#define X86_DR7_LEN2_MASK (3 << 26)
739	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
740	#define X86_DR7_RW3_MASK (3 << 28)
741	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
742	#define X86_DR7_LEN3_MASK (3 << 30)
743
744	/** Bits which must be 1s. */
745	#define X86_DR7_MB1_MASK (RT_BIT(10))
746
747	/** Calcs the L bit of Nth breakpoint.
748	* @param iBp The breakpoint number [0..3].
749	*/
750	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
751
752	/** Calcs the G bit of Nth breakpoint.
753	* @param iBp The breakpoint number [0..3].
754	*/
755	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
756
757	/** @name Read/Write values.
758	* @{ */
759	/** Break on instruction fetch only. */
760	#define X86_DR7_RW_EO 0U
761	/** Break on write only. */
762	#define X86_DR7_RW_WO 1U
763	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
764	#define X86_DR7_RW_IO 2U
765	/** Break on read or write (but not instruction fetches). */
766	#define X86_DR7_RW_RW 3U
767	/** @} */
768
769	/** Shifts a X86_DR7_RW_* value to its right place.
770	* @param iBp The breakpoint number [0..3].
771	* @param fRw One of the X86_DR7_RW_* value.
772	*/
773	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
774
775	/** @name Length values.
776	* @{ */
777	#define X86_DR7_LEN_BYTE 0U
778	#define X86_DR7_LEN_WORD 1U
779	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
780	#define X86_DR7_LEN_DWORD 3U
781	/** @} */
782
783	/** Shifts a X86_DR7_LEN_* value to its right place.
784	* @param iBp The breakpoint number [0..3].
785	* @param cb One of the X86_DR7_LEN_* values.
786	*/
787	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
788
789	/** Fetch the breakpoint length bits from the DR7 value.
790	* @param uDR7 DR7 value
791	* @param iBp The breakpoint number [0..3].
792	*/
793	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
794
795	/** Mask used to check if any breakpoints are enabled. */
796	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
797
798	/** Mask used to check if any io breakpoints are set. */
799	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
800
801	/** Value of DR7 after powerup/reset. */
802	#define X86_DR7_INIT_VAL 0x400
803	/** @} */
804
805
806	/** @name Machine Specific Registers
807	* @{
808	*/
809
810	/** Time Stamp Counter. */
811	#define MSR_IA32_TSC 0x10
812
813	#define MSR_IA32_PLATFORM_ID 0x17
814
815	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
816	#define MSR_IA32_APICBASE 0x1b
817	#endif
818
819	/** CPU Feature control. */
820	#define MSR_IA32_FEATURE_CONTROL 0x3A
821	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
822	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
823
824	/** BIOS update trigger (microcode update). */
825	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
826
827	/** BIOS update signature (microcode). */
828	#define MSR_IA32_BIOS_SIGN_ID 0x8B
829
830	/** General performance counter no. 0. */
831	#define MSR_IA32_PMC0 0xC1
832	/** General performance counter no. 1. */
833	#define MSR_IA32_PMC1 0xC2
834	/** General performance counter no. 2. */
835	#define MSR_IA32_PMC2 0xC3
836	/** General performance counter no. 3. */
837	#define MSR_IA32_PMC3 0xC4
838
839	/** Nehalem power control. */
840	#define MSR_IA32_PLATFORM_INFO 0xCE
841
842	/** Get FSB clock status (Intel-specific). */
843	#define MSR_IA32_FSB_CLOCK_STS 0xCD
844
845	/** MTRR Capabilities. */
846	#define MSR_IA32_MTRR_CAP 0xFE
847
848
849	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
850	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
851	* R0 SS == CS + 8
852	* R3 CS == CS + 16
853	* R3 SS == CS + 24
854	*/
855	#define MSR_IA32_SYSENTER_CS 0x174
856	/** SYSENTER_ESP - the R0 ESP. */
857	#define MSR_IA32_SYSENTER_ESP 0x175
858	/** SYSENTER_EIP - the R0 EIP. */
859	#define MSR_IA32_SYSENTER_EIP 0x176
860	#endif
861
862	/** Machine Check Global Capabilities Register. */
863	#define MSR_IA32_MCP_CAP 0x179
864	/** Machine Check Global Status Register. */
865	#define MSR_IA32_MCP_STATUS 0x17A
866	/** Machine Check Global Control Register. */
867	#define MSR_IA32_MCP_CTRL 0x17B
868
869	/** Trace/Profile Resource Control (R/W) */
870	#define MSR_IA32_DEBUGCTL 0x1D9
871
872	/* Page Attribute Table. */
873	#define MSR_IA32_CR_PAT 0x277
874
875	/** Performance counter MSRs. (Intel only) */
876	#define MSR_IA32_PERFEVTSEL0 0x186
877	#define MSR_IA32_PERFEVTSEL1 0x187
878	#define MSR_IA32_FLEX_RATIO 0x194
879	#define MSR_IA32_PERF_STATUS 0x198
880	#define MSR_IA32_PERF_CTL 0x199
881	#define MSR_IA32_THERM_STATUS 0x19c
882
883	/** Enable misc. processor features (R/W). */
884	#define MSR_IA32_MISC_ENABLE 0x1A0
885
886	/** MTRR Default Range. */
887	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
888
889	#define MSR_IA32_MC0_CTL 0x400
890	#define MSR_IA32_MC0_STATUS 0x401
891
892	/** Basic VMX information. */
893	#define MSR_IA32_VMX_BASIC_INFO 0x480
894	/** Allowed settings for pin-based VM execution controls */
895	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
896	/** Allowed settings for proc-based VM execution controls */
897	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
898	/** Allowed settings for the VMX exit controls. */
899	#define MSR_IA32_VMX_EXIT_CTLS 0x483
900	/** Allowed settings for the VMX entry controls. */
901	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
902	/** Misc VMX info. */
903	#define MSR_IA32_VMX_MISC 0x485
904	/** Fixed cleared bits in CR0. */
905	#define MSR_IA32_VMX_CR0_FIXED0 0x486
906	/** Fixed set bits in CR0. */
907	#define MSR_IA32_VMX_CR0_FIXED1 0x487
908	/** Fixed cleared bits in CR4. */
909	#define MSR_IA32_VMX_CR4_FIXED0 0x488
910	/** Fixed set bits in CR4. */
911	#define MSR_IA32_VMX_CR4_FIXED1 0x489
912	/** Information for enumerating fields in the VMCS. */
913	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
914	/** Allowed settings for secondary proc-based VM execution controls */
915	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
916	/** EPT capabilities. */
917	#define MSR_IA32_VMX_EPT_CAPS 0x48C
918	/** DS Save Area (R/W). */
919	#define MSR_IA32_DS_AREA 0x600
920	/** X2APIC MSR ranges. */
921	#define MSR_IA32_APIC_START 0x800
922	#define MSR_IA32_APIC_END 0x900
923
924	/** K6 EFER - Extended Feature Enable Register. */
925	#define MSR_K6_EFER 0xc0000080
926	/** @todo document EFER */
927	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
928	#define MSR_K6_EFER_SCE RT_BIT(0)
929	/** Bit 8 - LME - Long mode enabled. (R/W) */
930	#define MSR_K6_EFER_LME RT_BIT(8)
931	/** Bit 10 - LMA - Long mode active. (R) */
932	#define MSR_K6_EFER_LMA RT_BIT(10)
933	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
934	#define MSR_K6_EFER_NXE RT_BIT(11)
935	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
936	#define MSR_K6_EFER_SVME RT_BIT(12)
937	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
938	#define MSR_K6_EFER_LMSLE RT_BIT(13)
939	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
940	#define MSR_K6_EFER_FFXSR RT_BIT(14)
941	/** K6 STAR - SYSCALL/RET targets. */
942	#define MSR_K6_STAR 0xc0000081
943	/** Shift value for getting the SYSRET CS and SS value. */
944	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
945	/** Shift value for getting the SYSCALL CS and SS value. */
946	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
947	/** Selector mask for use after shifting. */
948	#define MSR_K6_STAR_SEL_MASK 0xffff
949	/** The mask which give the SYSCALL EIP. */
950	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
951	/** K6 WHCR - Write Handling Control Register. */
952	#define MSR_K6_WHCR 0xc0000082
953	/** K6 UWCCR - UC/WC Cacheability Control Register. */
954	#define MSR_K6_UWCCR 0xc0000085
955	/** K6 PSOR - Processor State Observability Register. */
956	#define MSR_K6_PSOR 0xc0000087
957	/** K6 PFIR - Page Flush/Invalidate Register. */
958	#define MSR_K6_PFIR 0xc0000088
959
960	/** Performance counter MSRs. (AMD only) */
961	#define MSR_K7_EVNTSEL0 0xc0010000
962	#define MSR_K7_EVNTSEL1 0xc0010001
963	#define MSR_K7_EVNTSEL2 0xc0010002
964	#define MSR_K7_EVNTSEL3 0xc0010003
965	#define MSR_K7_PERFCTR0 0xc0010004
966	#define MSR_K7_PERFCTR1 0xc0010005
967	#define MSR_K7_PERFCTR2 0xc0010006
968	#define MSR_K7_PERFCTR3 0xc0010007
969
970	#define MSR_K8_HWCR 0xc0010015
971
972	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
973	#define MSR_K8_LSTAR 0xc0000082
974	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
975	#define MSR_K8_CSTAR 0xc0000083
976	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
977	#define MSR_K8_SF_MASK 0xc0000084
978	/** K8 FS.base - The 64-bit base FS register. */
979	#define MSR_K8_FS_BASE 0xc0000100
980	/** K8 GS.base - The 64-bit base GS register. */
981	#define MSR_K8_GS_BASE 0xc0000101
982	/** K8 KernelGSbase - Used with SWAPGS. */
983	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
984	#define MSR_K8_TSC_AUX 0xc0000103
985	#define MSR_K8_SYSCFG 0xc0010010
986	#define MSR_K8_HWCR 0xc0010015
987	#define MSR_K8_IORRBASE0 0xc0010016
988	#define MSR_K8_IORRMASK0 0xc0010017
989	#define MSR_K8_IORRBASE1 0xc0010018
990	#define MSR_K8_IORRMASK1 0xc0010019
991	#define MSR_K8_TOP_MEM1 0xc001001a
992	#define MSR_K8_TOP_MEM2 0xc001001d
993	#define MSR_K8_VM_CR 0xc0010114
994	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
995
996	#define MSR_K8_IGNNE 0xc0010115
997	#define MSR_K8_SMM_CTL 0xc0010116
998	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
999	* host state during world switch.
1000	*/
1001	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1002
1003	/** @} */
1004
1005
1006	/** @name Page Table / Directory / Directory Pointers / L4.
1007	* @{
1008	*/
1009
1010	/** Page table/directory entry as an unsigned integer. */
1011	typedef uint32_t X86PGUINT;
1012	/** Pointer to a page table/directory table entry as an unsigned integer. */
1013	typedef X86PGUINT *PX86PGUINT;
1014	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1015	typedef X86PGUINT const *PCX86PGUINT;
1016
1017	/** Number of entries in a 32-bit PT/PD. */
1018	#define X86_PG_ENTRIES 1024
1019
1020
1021	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1022	typedef uint64_t X86PGPAEUINT;
1023	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1024	typedef X86PGPAEUINT *PX86PGPAEUINT;
1025	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1026	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1027
1028	/** Number of entries in a PAE PT/PD. */
1029	#define X86_PG_PAE_ENTRIES 512
1030	/** Number of entries in a PAE PDPT. */
1031	#define X86_PG_PAE_PDPE_ENTRIES 4
1032
1033	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1034	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1035	/** Number of entries in an AMD64 PDPT.
1036	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1037	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1038
1039	/** The size of a 4KB page. */
1040	#define X86_PAGE_4K_SIZE _4K
1041	/** The page shift of a 4KB page. */
1042	#define X86_PAGE_4K_SHIFT 12
1043	/** The 4KB page offset mask. */
1044	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1045	/** The 4KB page base mask for virtual addresses. */
1046	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1047	/** The 4KB page base mask for virtual addresses - 32bit version. */
1048	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1049
1050	/** The size of a 2MB page. */
1051	#define X86_PAGE_2M_SIZE _2M
1052	/** The page shift of a 2MB page. */
1053	#define X86_PAGE_2M_SHIFT 21
1054	/** The 2MB page offset mask. */
1055	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1056	/** The 2MB page base mask for virtual addresses. */
1057	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1058	/** The 2MB page base mask for virtual addresses - 32bit version. */
1059	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1060
1061	/** The size of a 4MB page. */
1062	#define X86_PAGE_4M_SIZE _4M
1063	/** The page shift of a 4MB page. */
1064	#define X86_PAGE_4M_SHIFT 22
1065	/** The 4MB page offset mask. */
1066	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1067	/** The 4MB page base mask for virtual addresses. */
1068	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1069	/** The 4MB page base mask for virtual addresses - 32bit version. */
1070	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1071
1072
1073
1074	/** @name Page Table Entry
1075	* @{
1076	*/
1077	/** Bit 0 - P - Present bit. */
1078	#define X86_PTE_BIT_P 0
1079	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1080	#define X86_PTE_BIT_RW 1
1081	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1082	#define X86_PTE_BIT_US 2
1083	/** Bit 3 - PWT - Page level write thru bit. */
1084	#define X86_PTE_BIT_PWT 3
1085	/** Bit 4 - PCD - Page level cache disable bit. */
1086	#define X86_PTE_BIT_PCD 4
1087	/** Bit 5 - A - Access bit. */
1088	#define X86_PTE_BIT_A 5
1089	/** Bit 6 - D - Dirty bit. */
1090	#define X86_PTE_BIT_D 6
1091	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1092	#define X86_PTE_BIT_PAT 7
1093	/** Bit 8 - G - Global flag. */
1094	#define X86_PTE_BIT_G 8
1095
1096	/** Bit 0 - P - Present bit mask. */
1097	#define X86_PTE_P RT_BIT(0)
1098	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1099	#define X86_PTE_RW RT_BIT(1)
1100	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1101	#define X86_PTE_US RT_BIT(2)
1102	/** Bit 3 - PWT - Page level write thru bit mask. */
1103	#define X86_PTE_PWT RT_BIT(3)
1104	/** Bit 4 - PCD - Page level cache disable bit mask. */
1105	#define X86_PTE_PCD RT_BIT(4)
1106	/** Bit 5 - A - Access bit mask. */
1107	#define X86_PTE_A RT_BIT(5)
1108	/** Bit 6 - D - Dirty bit mask. */
1109	#define X86_PTE_D RT_BIT(6)
1110	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1111	#define X86_PTE_PAT RT_BIT(7)
1112	/** Bit 8 - G - Global bit mask. */
1113	#define X86_PTE_G RT_BIT(8)
1114
1115	/** Bits 9-11 - - Available for use to system software. */
1116	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1117	/** Bits 12-31 - - Physical Page number of the next level. */
1118	#define X86_PTE_PG_MASK ( 0xfffff000 )
1119
1120	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1121	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1122	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1123	/** @todo Get rid of the above hack; makes code unreadable. */
1124	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1125	#else
1126	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1127	#endif
1128	/** Bits 63 - NX - PAE - No execution flag. */
1129	#define X86_PTE_PAE_NX RT_BIT_64(63)
1130
1131	/**
1132	* Page table entry.
1133	*/
1134	typedef struct X86PTEBITS
1135	{
1136	/** Flags whether(=1) or not the page is present. */
1137	unsigned u1Present : 1;
1138	/** Read(=0) / Write(=1) flag. */
1139	unsigned u1Write : 1;
1140	/** User(=1) / Supervisor (=0) flag. */
1141	unsigned u1User : 1;
1142	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1143	unsigned u1WriteThru : 1;
1144	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1145	unsigned u1CacheDisable : 1;
1146	/** Accessed flag.
1147	* Indicates that the page have been read or written to. */
1148	unsigned u1Accessed : 1;
1149	/** Dirty flag.
1150	* Indicates that the page has been written to. */
1151	unsigned u1Dirty : 1;
1152	/** Reserved / If PAT enabled, bit 2 of the index. */
1153	unsigned u1PAT : 1;
1154	/** Global flag. (Ignored in all but final level.) */
1155	unsigned u1Global : 1;
1156	/** Available for use to system software. */
1157	unsigned u3Available : 3;
1158	/** Physical Page number of the next level. */
1159	unsigned u20PageNo : 20;
1160	} X86PTEBITS;
1161	/** Pointer to a page table entry. */
1162	typedef X86PTEBITS *PX86PTEBITS;
1163	/** Pointer to a const page table entry. */
1164	typedef const X86PTEBITS *PCX86PTEBITS;
1165
1166	/**
1167	* Page table entry.
1168	*/
1169	typedef union X86PTE
1170	{
1171	/** Unsigned integer view */
1172	X86PGUINT u;
1173	/** Bit field view. */
1174	X86PTEBITS n;
1175	/** 32-bit view. */
1176	uint32_t au32[1];
1177	/** 16-bit view. */
1178	uint16_t au16[2];
1179	/** 8-bit view. */
1180	uint8_t au8[4];
1181	} X86PTE;
1182	/** Pointer to a page table entry. */
1183	typedef X86PTE *PX86PTE;
1184	/** Pointer to a const page table entry. */
1185	typedef const X86PTE *PCX86PTE;
1186
1187
1188	/**
1189	* PAE page table entry.
1190	*/
1191	typedef struct X86PTEPAEBITS
1192	{
1193	/** Flags whether(=1) or not the page is present. */
1194	uint32_t u1Present : 1;
1195	/** Read(=0) / Write(=1) flag. */
1196	uint32_t u1Write : 1;
1197	/** User(=1) / Supervisor(=0) flag. */
1198	uint32_t u1User : 1;
1199	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1200	uint32_t u1WriteThru : 1;
1201	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1202	uint32_t u1CacheDisable : 1;
1203	/** Accessed flag.
1204	* Indicates that the page have been read or written to. */
1205	uint32_t u1Accessed : 1;
1206	/** Dirty flag.
1207	* Indicates that the page has been written to. */
1208	uint32_t u1Dirty : 1;
1209	/** Reserved / If PAT enabled, bit 2 of the index. */
1210	uint32_t u1PAT : 1;
1211	/** Global flag. (Ignored in all but final level.) */
1212	uint32_t u1Global : 1;
1213	/** Available for use to system software. */
1214	uint32_t u3Available : 3;
1215	/** Physical Page number of the next level - Low Part. Don't use this. */
1216	uint32_t u20PageNoLow : 20;
1217	/** Physical Page number of the next level - High Part. Don't use this. */
1218	uint32_t u20PageNoHigh : 20;
1219	/** MBZ bits */
1220	uint32_t u11Reserved : 11;
1221	/** No Execute flag. */
1222	uint32_t u1NoExecute : 1;
1223	} X86PTEPAEBITS;
1224	/** Pointer to a page table entry. */
1225	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1226	/** Pointer to a page table entry. */
1227	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1228
1229	/**
1230	* PAE Page table entry.
1231	*/
1232	typedef union X86PTEPAE
1233	{
1234	/** Unsigned integer view */
1235	X86PGPAEUINT u;
1236	/** Bit field view. */
1237	X86PTEPAEBITS n;
1238	/** 32-bit view. */
1239	uint32_t au32[2];
1240	/** 16-bit view. */
1241	uint16_t au16[4];
1242	/** 8-bit view. */
1243	uint8_t au8[8];
1244	} X86PTEPAE;
1245	/** Pointer to a PAE page table entry. */
1246	typedef X86PTEPAE *PX86PTEPAE;
1247	/** Pointer to a const PAE page table entry. */
1248	typedef const X86PTEPAE *PCX86PTEPAE;
1249	/** @} */
1250
1251	/**
1252	* Page table.
1253	*/
1254	typedef struct X86PT
1255	{
1256	/** PTE Array. */
1257	X86PTE a[X86_PG_ENTRIES];
1258	} X86PT;
1259	/** Pointer to a page table. */
1260	typedef X86PT *PX86PT;
1261	/** Pointer to a const page table. */
1262	typedef const X86PT *PCX86PT;
1263
1264	/** The page shift to get the PT index. */
1265	#define X86_PT_SHIFT 12
1266	/** The PT index mask (apply to a shifted page address). */
1267	#define X86_PT_MASK 0x3ff
1268
1269
1270	/**
1271	* Page directory.
1272	*/
1273	typedef struct X86PTPAE
1274	{
1275	/** PTE Array. */
1276	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1277	} X86PTPAE;
1278	/** Pointer to a page table. */
1279	typedef X86PTPAE *PX86PTPAE;
1280	/** Pointer to a const page table. */
1281	typedef const X86PTPAE *PCX86PTPAE;
1282
1283	/** The page shift to get the PA PTE index. */
1284	#define X86_PT_PAE_SHIFT 12
1285	/** The PAE PT index mask (apply to a shifted page address). */
1286	#define X86_PT_PAE_MASK 0x1ff
1287
1288
1289	/** @name 4KB Page Directory Entry
1290	* @{
1291	*/
1292	/** Bit 0 - P - Present bit. */
1293	#define X86_PDE_P RT_BIT(0)
1294	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1295	#define X86_PDE_RW RT_BIT(1)
1296	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1297	#define X86_PDE_US RT_BIT(2)
1298	/** Bit 3 - PWT - Page level write thru bit. */
1299	#define X86_PDE_PWT RT_BIT(3)
1300	/** Bit 4 - PCD - Page level cache disable bit. */
1301	#define X86_PDE_PCD RT_BIT(4)
1302	/** Bit 5 - A - Access bit. */
1303	#define X86_PDE_A RT_BIT(5)
1304	/** Bit 7 - PS - Page size attribute.
1305	* Clear mean 4KB pages, set means large pages (2/4MB). */
1306	#define X86_PDE_PS RT_BIT(7)
1307	/** Bits 9-11 - - Available for use to system software. */
1308	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1309	/** Bits 12-31 - - Physical Page number of the next level. */
1310	#define X86_PDE_PG_MASK ( 0xfffff000 )
1311
1312	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1313	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1314	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1315	* we partly or that part into shadow page table entries. Will be corrected
1316	* soon.
1317	*/
1318	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1319	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1320	#else
1321	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1322	#endif
1323	/** Bits 63 - NX - PAE - No execution flag. */
1324	#define X86_PDE_PAE_NX RT_BIT_64(63)
1325
1326	/**
1327	* Page directory entry.
1328	*/
1329	typedef struct X86PDEBITS
1330	{
1331	/** Flags whether(=1) or not the page is present. */
1332	unsigned u1Present : 1;
1333	/** Read(=0) / Write(=1) flag. */
1334	unsigned u1Write : 1;
1335	/** User(=1) / Supervisor (=0) flag. */
1336	unsigned u1User : 1;
1337	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1338	unsigned u1WriteThru : 1;
1339	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1340	unsigned u1CacheDisable : 1;
1341	/** Accessed flag.
1342	* Indicates that the page has been read or written to. */
1343	unsigned u1Accessed : 1;
1344	/** Reserved / Ignored (dirty bit). */
1345	unsigned u1Reserved0 : 1;
1346	/** Size bit if PSE is enabled - in any event it's 0. */
1347	unsigned u1Size : 1;
1348	/** Reserved / Ignored (global bit). */
1349	unsigned u1Reserved1 : 1;
1350	/** Available for use to system software. */
1351	unsigned u3Available : 3;
1352	/** Physical Page number of the next level. */
1353	unsigned u20PageNo : 20;
1354	} X86PDEBITS;
1355	/** Pointer to a page directory entry. */
1356	typedef X86PDEBITS *PX86PDEBITS;
1357	/** Pointer to a const page directory entry. */
1358	typedef const X86PDEBITS *PCX86PDEBITS;
1359
1360
1361	/**
1362	* PAE page directory entry.
1363	*/
1364	typedef struct X86PDEPAEBITS
1365	{
1366	/** Flags whether(=1) or not the page is present. */
1367	uint32_t u1Present : 1;
1368	/** Read(=0) / Write(=1) flag. */
1369	uint32_t u1Write : 1;
1370	/** User(=1) / Supervisor (=0) flag. */
1371	uint32_t u1User : 1;
1372	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1373	uint32_t u1WriteThru : 1;
1374	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1375	uint32_t u1CacheDisable : 1;
1376	/** Accessed flag.
1377	* Indicates that the page has been read or written to. */
1378	uint32_t u1Accessed : 1;
1379	/** Reserved / Ignored (dirty bit). */
1380	uint32_t u1Reserved0 : 1;
1381	/** Size bit if PSE is enabled - in any event it's 0. */
1382	uint32_t u1Size : 1;
1383	/** Reserved / Ignored (global bit). / */
1384	uint32_t u1Reserved1 : 1;
1385	/** Available for use to system software. */
1386	uint32_t u3Available : 3;
1387	/** Physical Page number of the next level - Low Part. Don't use! */
1388	uint32_t u20PageNoLow : 20;
1389	/** Physical Page number of the next level - High Part. Don't use! */
1390	uint32_t u20PageNoHigh : 20;
1391	/** MBZ bits */
1392	uint32_t u11Reserved : 11;
1393	/** No Execute flag. */
1394	uint32_t u1NoExecute : 1;
1395	} X86PDEPAEBITS;
1396	/** Pointer to a page directory entry. */
1397	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1398	/** Pointer to a const page directory entry. */
1399	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1400
1401	/** @} */
1402
1403
1404	/** @name 2/4MB Page Directory Entry
1405	* @{
1406	*/
1407	/** Bit 0 - P - Present bit. */
1408	#define X86_PDE4M_P RT_BIT(0)
1409	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1410	#define X86_PDE4M_RW RT_BIT(1)
1411	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1412	#define X86_PDE4M_US RT_BIT(2)
1413	/** Bit 3 - PWT - Page level write thru bit. */
1414	#define X86_PDE4M_PWT RT_BIT(3)
1415	/** Bit 4 - PCD - Page level cache disable bit. */
1416	#define X86_PDE4M_PCD RT_BIT(4)
1417	/** Bit 5 - A - Access bit. */
1418	#define X86_PDE4M_A RT_BIT(5)
1419	/** Bit 6 - D - Dirty bit. */
1420	#define X86_PDE4M_D RT_BIT(6)
1421	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1422	#define X86_PDE4M_PS RT_BIT(7)
1423	/** Bit 8 - G - Global flag. */
1424	#define X86_PDE4M_G RT_BIT(8)
1425	/** Bits 9-11 - AVL - Available for use to system software. */
1426	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1427	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1428	#define X86_PDE4M_PAT RT_BIT(12)
1429	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1430	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1431	/** Bits 22-31 - - Physical Page number. */
1432	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1433	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1434	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1435	/** The number of bits to the high part of the page number. */
1436	#define X86_PDE4M_PG_HIGH_SHIFT 19
1437
1438	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1439	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1440	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1441	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1442	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1443
1444	/**
1445	* 4MB page directory entry.
1446	*/
1447	typedef struct X86PDE4MBITS
1448	{
1449	/** Flags whether(=1) or not the page is present. */
1450	unsigned u1Present : 1;
1451	/** Read(=0) / Write(=1) flag. */
1452	unsigned u1Write : 1;
1453	/** User(=1) / Supervisor (=0) flag. */
1454	unsigned u1User : 1;
1455	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1456	unsigned u1WriteThru : 1;
1457	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1458	unsigned u1CacheDisable : 1;
1459	/** Accessed flag.
1460	* Indicates that the page have been read or written to. */
1461	unsigned u1Accessed : 1;
1462	/** Dirty flag.
1463	* Indicates that the page has been written to. */
1464	unsigned u1Dirty : 1;
1465	/** Page size flag - always 1 for 4MB entries. */
1466	unsigned u1Size : 1;
1467	/** Global flag. */
1468	unsigned u1Global : 1;
1469	/** Available for use to system software. */
1470	unsigned u3Available : 3;
1471	/** Reserved / If PAT enabled, bit 2 of the index. */
1472	unsigned u1PAT : 1;
1473	/** Bits 32-39 of the page number on AMD64.
1474	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1475	unsigned u8PageNoHigh : 8;
1476	/** Reserved. */
1477	unsigned u1Reserved : 1;
1478	/** Physical Page number of the page. */
1479	unsigned u10PageNo : 10;
1480	} X86PDE4MBITS;
1481	/** Pointer to a page table entry. */
1482	typedef X86PDE4MBITS *PX86PDE4MBITS;
1483	/** Pointer to a const page table entry. */
1484	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1485
1486
1487	/**
1488	* 2MB PAE page directory entry.
1489	*/
1490	typedef struct X86PDE2MPAEBITS
1491	{
1492	/** Flags whether(=1) or not the page is present. */
1493	uint32_t u1Present : 1;
1494	/** Read(=0) / Write(=1) flag. */
1495	uint32_t u1Write : 1;
1496	/** User(=1) / Supervisor(=0) flag. */
1497	uint32_t u1User : 1;
1498	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1499	uint32_t u1WriteThru : 1;
1500	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1501	uint32_t u1CacheDisable : 1;
1502	/** Accessed flag.
1503	* Indicates that the page have been read or written to. */
1504	uint32_t u1Accessed : 1;
1505	/** Dirty flag.
1506	* Indicates that the page has been written to. */
1507	uint32_t u1Dirty : 1;
1508	/** Page size flag - always 1 for 2MB entries. */
1509	uint32_t u1Size : 1;
1510	/** Global flag. */
1511	uint32_t u1Global : 1;
1512	/** Available for use to system software. */
1513	uint32_t u3Available : 3;
1514	/** Reserved / If PAT enabled, bit 2 of the index. */
1515	uint32_t u1PAT : 1;
1516	/** Reserved. */
1517	uint32_t u9Reserved : 9;
1518	/** Physical Page number of the next level - Low part. Don't use! */
1519	uint32_t u10PageNoLow : 10;
1520	/** Physical Page number of the next level - High part. Don't use! */
1521	uint32_t u20PageNoHigh : 20;
1522	/** MBZ bits */
1523	uint32_t u11Reserved : 11;
1524	/** No Execute flag. */
1525	uint32_t u1NoExecute : 1;
1526	} X86PDE2MPAEBITS;
1527	/** Pointer to a 2MB PAE page table entry. */
1528	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1529	/** Pointer to a 2MB PAE page table entry. */
1530	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1531
1532	/** @} */
1533
1534	/**
1535	* Page directory entry.
1536	*/
1537	typedef union X86PDE
1538	{
1539	/** Unsigned integer view. */
1540	X86PGUINT u;
1541	/** Normal view. */
1542	X86PDEBITS n;
1543	/** 4MB view (big). */
1544	X86PDE4MBITS b;
1545	/** 8 bit unsigned integer view. */
1546	uint8_t au8[4];
1547	/** 16 bit unsigned integer view. */
1548	uint16_t au16[2];
1549	/** 32 bit unsigned integer view. */
1550	uint32_t au32[1];
1551	} X86PDE;
1552	/** Pointer to a page directory entry. */
1553	typedef X86PDE *PX86PDE;
1554	/** Pointer to a const page directory entry. */
1555	typedef const X86PDE *PCX86PDE;
1556
1557	/**
1558	* PAE page directory entry.
1559	*/
1560	typedef union X86PDEPAE
1561	{
1562	/** Unsigned integer view. */
1563	X86PGPAEUINT u;
1564	/** Normal view. */
1565	X86PDEPAEBITS n;
1566	/** 2MB page view (big). */
1567	X86PDE2MPAEBITS b;
1568	/** 8 bit unsigned integer view. */
1569	uint8_t au8[8];
1570	/** 16 bit unsigned integer view. */
1571	uint16_t au16[4];
1572	/** 32 bit unsigned integer view. */
1573	uint32_t au32[2];
1574	} X86PDEPAE;
1575	/** Pointer to a page directory entry. */
1576	typedef X86PDEPAE *PX86PDEPAE;
1577	/** Pointer to a const page directory entry. */
1578	typedef const X86PDEPAE *PCX86PDEPAE;
1579
1580	/**
1581	* Page directory.
1582	*/
1583	typedef struct X86PD
1584	{
1585	/** PDE Array. */
1586	X86PDE a[X86_PG_ENTRIES];
1587	} X86PD;
1588	/** Pointer to a page directory. */
1589	typedef X86PD *PX86PD;
1590	/** Pointer to a const page directory. */
1591	typedef const X86PD *PCX86PD;
1592
1593	/** The page shift to get the PD index. */
1594	#define X86_PD_SHIFT 22
1595	/** The PD index mask (apply to a shifted page address). */
1596	#define X86_PD_MASK 0x3ff
1597
1598
1599	/**
1600	* PAE page directory.
1601	*/
1602	typedef struct X86PDPAE
1603	{
1604	/** PDE Array. */
1605	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1606	} X86PDPAE;
1607	/** Pointer to a PAE page directory. */
1608	typedef X86PDPAE *PX86PDPAE;
1609	/** Pointer to a const PAE page directory. */
1610	typedef const X86PDPAE *PCX86PDPAE;
1611
1612	/** The page shift to get the PAE PD index. */
1613	#define X86_PD_PAE_SHIFT 21
1614	/** The PAE PD index mask (apply to a shifted page address). */
1615	#define X86_PD_PAE_MASK 0x1ff
1616
1617
1618	/** @name Page Directory Pointer Table Entry (PAE)
1619	* @{
1620	*/
1621	/** Bit 0 - P - Present bit. */
1622	#define X86_PDPE_P RT_BIT(0)
1623	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1624	#define X86_PDPE_RW RT_BIT(1)
1625	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1626	#define X86_PDPE_US RT_BIT(2)
1627	/** Bit 3 - PWT - Page level write thru bit. */
1628	#define X86_PDPE_PWT RT_BIT(3)
1629	/** Bit 4 - PCD - Page level cache disable bit. */
1630	#define X86_PDPE_PCD RT_BIT(4)
1631	/** Bit 5 - A - Access bit. Long Mode only. */
1632	#define X86_PDPE_A RT_BIT(5)
1633	/** Bits 9-11 - - Available for use to system software. */
1634	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1635	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1636	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1637	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1638	/** @todo Get rid of the above hack; makes code unreadable. */
1639	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1640	#else
1641	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1642	#endif
1643	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1644	#define X86_PDPE_NX RT_BIT_64(63)
1645
1646	/**
1647	* Page directory pointer table entry.
1648	*/
1649	typedef struct X86PDPEBITS
1650	{
1651	/** Flags whether(=1) or not the page is present. */
1652	uint32_t u1Present : 1;
1653	/** Chunk of reserved bits. */
1654	uint32_t u2Reserved : 2;
1655	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1656	uint32_t u1WriteThru : 1;
1657	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1658	uint32_t u1CacheDisable : 1;
1659	/** Chunk of reserved bits. */
1660	uint32_t u4Reserved : 4;
1661	/** Available for use to system software. */
1662	uint32_t u3Available : 3;
1663	/** Physical Page number of the next level - Low Part. Don't use! */
1664	uint32_t u20PageNoLow : 20;
1665	/** Physical Page number of the next level - High Part. Don't use! */
1666	uint32_t u20PageNoHigh : 20;
1667	/** MBZ bits */
1668	uint32_t u12Reserved : 12;
1669	} X86PDPEBITS;
1670	/** Pointer to a page directory pointer table entry. */
1671	typedef X86PDPEBITS *PX86PTPEBITS;
1672	/** Pointer to a const page directory pointer table entry. */
1673	typedef const X86PDPEBITS *PCX86PTPEBITS;
1674
1675	/**
1676	* Page directory pointer table entry. AMD64 version
1677	*/
1678	typedef struct X86PDPEAMD64BITS
1679	{
1680	/** Flags whether(=1) or not the page is present. */
1681	uint32_t u1Present : 1;
1682	/** Read(=0) / Write(=1) flag. */
1683	uint32_t u1Write : 1;
1684	/** User(=1) / Supervisor (=0) flag. */
1685	uint32_t u1User : 1;
1686	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1687	uint32_t u1WriteThru : 1;
1688	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1689	uint32_t u1CacheDisable : 1;
1690	/** Accessed flag.
1691	* Indicates that the page have been read or written to. */
1692	uint32_t u1Accessed : 1;
1693	/** Chunk of reserved bits. */
1694	uint32_t u3Reserved : 3;
1695	/** Available for use to system software. */
1696	uint32_t u3Available : 3;
1697	/** Physical Page number of the next level - Low Part. Don't use! */
1698	uint32_t u20PageNoLow : 20;
1699	/** Physical Page number of the next level - High Part. Don't use! */
1700	uint32_t u20PageNoHigh : 20;
1701	/** MBZ bits */
1702	uint32_t u11Reserved : 11;
1703	/** No Execute flag. */
1704	uint32_t u1NoExecute : 1;
1705	} X86PDPEAMD64BITS;
1706	/** Pointer to a page directory pointer table entry. */
1707	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1708	/** Pointer to a const page directory pointer table entry. */
1709	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1710
1711	/**
1712	* Page directory pointer table entry.
1713	*/
1714	typedef union X86PDPE
1715	{
1716	/** Unsigned integer view. */
1717	X86PGPAEUINT u;
1718	/** Normal view. */
1719	X86PDPEBITS n;
1720	/** AMD64 view. */
1721	X86PDPEAMD64BITS lm;
1722	/** 8 bit unsigned integer view. */
1723	uint8_t au8[8];
1724	/** 16 bit unsigned integer view. */
1725	uint16_t au16[4];
1726	/** 32 bit unsigned integer view. */
1727	uint32_t au32[2];
1728	} X86PDPE;
1729	/** Pointer to a page directory pointer table entry. */
1730	typedef X86PDPE *PX86PDPE;
1731	/** Pointer to a const page directory pointer table entry. */
1732	typedef const X86PDPE *PCX86PDPE;
1733
1734
1735	/**
1736	* Page directory pointer table.
1737	*/
1738	typedef struct X86PDPT
1739	{
1740	/** PDE Array. */
1741	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1742	} X86PDPT;
1743	/** Pointer to a page directory pointer table. */
1744	typedef X86PDPT *PX86PDPT;
1745	/** Pointer to a const page directory pointer table. */
1746	typedef const X86PDPT *PCX86PDPT;
1747
1748	/** The page shift to get the PDPT index. */
1749	#define X86_PDPT_SHIFT 30
1750	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1751	#define X86_PDPT_MASK_PAE 0x3
1752	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1753	#define X86_PDPT_MASK_AMD64 0x1ff
1754
1755	/** @} */
1756
1757
1758	/** @name Page Map Level-4 Entry (Long Mode PAE)
1759	* @{
1760	*/
1761	/** Bit 0 - P - Present bit. */
1762	#define X86_PML4E_P RT_BIT(0)
1763	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1764	#define X86_PML4E_RW RT_BIT(1)
1765	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1766	#define X86_PML4E_US RT_BIT(2)
1767	/** Bit 3 - PWT - Page level write thru bit. */
1768	#define X86_PML4E_PWT RT_BIT(3)
1769	/** Bit 4 - PCD - Page level cache disable bit. */
1770	#define X86_PML4E_PCD RT_BIT(4)
1771	/** Bit 5 - A - Access bit. */
1772	#define X86_PML4E_A RT_BIT(5)
1773	/** Bits 9-11 - - Available for use to system software. */
1774	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1775	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1776	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1777	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1778	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1779	#else
1780	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1781	#endif
1782	/** Bits 63 - NX - PAE - No execution flag. */
1783	#define X86_PML4E_NX RT_BIT_64(63)
1784
1785	/**
1786	* Page Map Level-4 Entry
1787	*/
1788	typedef struct X86PML4EBITS
1789	{
1790	/** Flags whether(=1) or not the page is present. */
1791	uint32_t u1Present : 1;
1792	/** Read(=0) / Write(=1) flag. */
1793	uint32_t u1Write : 1;
1794	/** User(=1) / Supervisor (=0) flag. */
1795	uint32_t u1User : 1;
1796	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1797	uint32_t u1WriteThru : 1;
1798	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1799	uint32_t u1CacheDisable : 1;
1800	/** Accessed flag.
1801	* Indicates that the page have been read or written to. */
1802	uint32_t u1Accessed : 1;
1803	/** Chunk of reserved bits. */
1804	uint32_t u3Reserved : 3;
1805	/** Available for use to system software. */
1806	uint32_t u3Available : 3;
1807	/** Physical Page number of the next level - Low Part. Don't use! */
1808	uint32_t u20PageNoLow : 20;
1809	/** Physical Page number of the next level - High Part. Don't use! */
1810	uint32_t u20PageNoHigh : 20;
1811	/** MBZ bits */
1812	uint32_t u11Reserved : 11;
1813	/** No Execute flag. */
1814	uint32_t u1NoExecute : 1;
1815	} X86PML4EBITS;
1816	/** Pointer to a page map level-4 entry. */
1817	typedef X86PML4EBITS *PX86PML4EBITS;
1818	/** Pointer to a const page map level-4 entry. */
1819	typedef const X86PML4EBITS *PCX86PML4EBITS;
1820
1821	/**
1822	* Page Map Level-4 Entry.
1823	*/
1824	typedef union X86PML4E
1825	{
1826	/** Unsigned integer view. */
1827	X86PGPAEUINT u;
1828	/** Normal view. */
1829	X86PML4EBITS n;
1830	/** 8 bit unsigned integer view. */
1831	uint8_t au8[8];
1832	/** 16 bit unsigned integer view. */
1833	uint16_t au16[4];
1834	/** 32 bit unsigned integer view. */
1835	uint32_t au32[2];
1836	} X86PML4E;
1837	/** Pointer to a page map level-4 entry. */
1838	typedef X86PML4E *PX86PML4E;
1839	/** Pointer to a const page map level-4 entry. */
1840	typedef const X86PML4E *PCX86PML4E;
1841
1842
1843	/**
1844	* Page Map Level-4.
1845	*/
1846	typedef struct X86PML4
1847	{
1848	/** PDE Array. */
1849	X86PML4E a[X86_PG_PAE_ENTRIES];
1850	} X86PML4;
1851	/** Pointer to a page map level-4. */
1852	typedef X86PML4 *PX86PML4;
1853	/** Pointer to a const page map level-4. */
1854	typedef const X86PML4 *PCX86PML4;
1855
1856	/** The page shift to get the PML4 index. */
1857	#define X86_PML4_SHIFT 39
1858	/** The PML4 index mask (apply to a shifted page address). */
1859	#define X86_PML4_MASK 0x1ff
1860
1861	/** @} */
1862
1863	/** @} */
1864
1865
1866	/**
1867	* 80-bit MMX/FPU register type.
1868	*/
1869	typedef struct X86FPUMMX
1870	{
1871	uint8_t reg[10];
1872	} X86FPUMMX;
1873	/** Pointer to a 80-bit MMX/FPU register type. */
1874	typedef X86FPUMMX *PX86FPUMMX;
1875	/** Pointer to a const 80-bit MMX/FPU register type. */
1876	typedef const X86FPUMMX *PCX86FPUMMX;
1877
1878	/**
1879	* FPU state (aka FSAVE/FRSTOR Memory Region).
1880	*/
1881	#pragma pack(1)
1882	typedef struct X86FPUSTATE
1883	{
1884	/** Control word. */
1885	uint16_t FCW;
1886	/** Alignment word */
1887	uint16_t Dummy1;
1888	/** Status word. */
1889	uint16_t FSW;
1890	/** Alignment word */
1891	uint16_t Dummy2;
1892	/** Tag word */
1893	uint16_t FTW;
1894	/** Alignment word */
1895	uint16_t Dummy3;
1896
1897	/** Instruction pointer. */
1898	uint32_t FPUIP;
1899	/** Code selector. */
1900	uint16_t CS;
1901	/** Opcode. */
1902	uint16_t FOP;
1903	/** FOO. */
1904	uint32_t FPUOO;
1905	/** FOS. */
1906	uint32_t FPUOS;
1907	/** FPU view - todo. */
1908	X86FPUMMX regs[8];
1909	} X86FPUSTATE;
1910	#pragma pack()
1911	/** Pointer to a FPU state. */
1912	typedef X86FPUSTATE *PX86FPUSTATE;
1913	/** Pointer to a const FPU state. */
1914	typedef const X86FPUSTATE *PCX86FPUSTATE;
1915
1916	/**
1917	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1918	*/
1919	#pragma pack(1)
1920	typedef struct X86FXSTATE
1921	{
1922	/** Control word. */
1923	uint16_t FCW;
1924	/** Status word. */
1925	uint16_t FSW;
1926	/** Tag word. (The upper byte is always zero.) */
1927	uint16_t FTW;
1928	/** Opcode. */
1929	uint16_t FOP;
1930	/** Instruction pointer. */
1931	uint32_t FPUIP;
1932	/** Code selector. */
1933	uint16_t CS;
1934	uint16_t Rsvrd1;
1935	/* - offset 16 - */
1936	/** Data pointer. */
1937	uint32_t FPUDP;
1938	/** Data segment */
1939	uint16_t DS;
1940	uint16_t Rsrvd2;
1941	uint32_t MXCSR;
1942	uint32_t MXCSR_MASK;
1943	/* - offset 32 - */
1944	union
1945	{
1946	/** MMX view. */
1947	uint64_t mmx;
1948	/** FPU view - todo. */
1949	X86FPUMMX fpu;
1950	/** 8-bit view. */
1951	uint8_t au8[16];
1952	/** 16-bit view. */
1953	uint16_t au16[8];
1954	/** 32-bit view. */
1955	uint32_t au32[4];
1956	/** 64-bit view. */
1957	uint64_t au64[2];
1958	/** 128-bit view. (yeah, very helpful) */
1959	uint128_t au128[1];
1960	} aRegs[8];
1961	/* - offset 160 - */
1962	union
1963	{
1964	/** XMM Register view . /
1965	uint128_t xmm;
1966	/** 8-bit view. */
1967	uint8_t au8[16];
1968	/** 16-bit view. */
1969	uint16_t au16[8];
1970	/** 32-bit view. */
1971	uint32_t au32[4];
1972	/** 64-bit view. */
1973	uint64_t au64[2];
1974	/** 128-bit view. (yeah, very helpful) */
1975	uint128_t au128[1];
1976	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1977	/* - offset 416 - */
1978	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1979	} X86FXSTATE;
1980	#pragma pack()
1981	/** Pointer to a FPU Extended state. */
1982	typedef X86FXSTATE *PX86FXSTATE;
1983	/** Pointer to a const FPU Extended state. */
1984	typedef const X86FXSTATE *PCX86FXSTATE;
1985
1986
1987	/** @name Selector Descriptor
1988	* @{
1989	*/
1990
1991	/**
1992	* Descriptor attributes.
1993	*/
1994	typedef struct X86DESCATTRBITS
1995	{
1996	/** 00 - Segment Type. */
1997	unsigned u4Type : 4;
1998	/** 04 - Descriptor Type. System(=0) or code/data selector */
1999	unsigned u1DescType : 1;
2000	/** 05 - Descriptor Privelege level. */
2001	unsigned u2Dpl : 2;
2002	/** 07 - Flags selector present(=1) or not. */
2003	unsigned u1Present : 1;
2004	/** 08 - Segment limit 16-19. */
2005	unsigned u4LimitHigh : 4;
2006	/** 0c - Available for system software. */
2007	unsigned u1Available : 1;
2008	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2009	unsigned u1Long : 1;
2010	/** 0e - This flags meaning depends on the segment type. Try make sense out
2011	* of the intel manual yourself. */
2012	unsigned u1DefBig : 1;
2013	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2014	* clear byte. */
2015	unsigned u1Granularity : 1;
2016	} X86DESCATTRBITS;
2017
2018
2019	#pragma pack(1)
2020	typedef union X86DESCATTR
2021	{
2022	/** Unsigned integer view. */
2023	uint32_t u;
2024	/** Normal view. */
2025	X86DESCATTRBITS n;
2026	} X86DESCATTR;
2027	#pragma pack()
2028	/** Pointer to descriptor attributes. */
2029	typedef X86DESCATTR *PX86DESCATTR;
2030	/** Pointer to const descriptor attributes. */
2031	typedef const X86DESCATTR *PCX86DESCATTR;
2032
2033
2034	/**
2035	* Generic descriptor table entry
2036	*/
2037	#pragma pack(1)
2038	typedef struct X86DESCGENERIC
2039	{
2040	/** Limit - Low word. */
2041	unsigned u16LimitLow : 16;
2042	/** Base address - lowe word.
2043	* Don't try set this to 24 because MSC is doing stupid things then. */
2044	unsigned u16BaseLow : 16;
2045	/** Base address - first 8 bits of high word. */
2046	unsigned u8BaseHigh1 : 8;
2047	/** Segment Type. */
2048	unsigned u4Type : 4;
2049	/** Descriptor Type. System(=0) or code/data selector */
2050	unsigned u1DescType : 1;
2051	/** Descriptor Privelege level. */
2052	unsigned u2Dpl : 2;
2053	/** Flags selector present(=1) or not. */
2054	unsigned u1Present : 1;
2055	/** Segment limit 16-19. */
2056	unsigned u4LimitHigh : 4;
2057	/** Available for system software. */
2058	unsigned u1Available : 1;
2059	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2060	unsigned u1Long : 1;
2061	/** This flags meaning depends on the segment type. Try make sense out
2062	* of the intel manual yourself. */
2063	unsigned u1DefBig : 1;
2064	/** Granularity of the limit. If set 4KB granularity is used, if
2065	* clear byte. */
2066	unsigned u1Granularity : 1;
2067	/** Base address - highest 8 bits. */
2068	unsigned u8BaseHigh2 : 8;
2069	} X86DESCGENERIC;
2070	#pragma pack()
2071	/** Pointer to a generic descriptor entry. */
2072	typedef X86DESCGENERIC *PX86DESCGENERIC;
2073	/** Pointer to a const generic descriptor entry. */
2074	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2075
2076	/**
2077	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2078	*/
2079	typedef struct X86DESCGATE
2080	{
2081	/** Target code segment offset - Low word.
2082	* Ignored if task-gate. */
2083	unsigned u16OffsetLow : 16;
2084	/** Target code segment selector for call-, interrupt- and trap-gates,
2085	* TSS selector if task-gate. */
2086	unsigned u16Sel : 16;
2087	/** Number of parameters for a call-gate.
2088	* Ignored if interrupt-, trap- or task-gate. */
2089	unsigned u4ParmCount : 4;
2090	/** Reserved / ignored. */
2091	unsigned u4Reserved : 4;
2092	/** Segment Type. */
2093	unsigned u4Type : 4;
2094	/** Descriptor Type (0 = system). */
2095	unsigned u1DescType : 1;
2096	/** Descriptor Privelege level. */
2097	unsigned u2Dpl : 2;
2098	/** Flags selector present(=1) or not. */
2099	unsigned u1Present : 1;
2100	/** Target code segment offset - High word.
2101	* Ignored if task-gate. */
2102	unsigned u16OffsetHigh : 16;
2103	} X86DESCGATE;
2104	AssertCompileSize(X86DESCGATE, 8);
2105	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2106	typedef X86DESCGATE *PX86DESCGATE;
2107	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2108	typedef const X86DESCGATE *PCX86DESCGATE;
2109
2110	/**
2111	* Descriptor table entry.
2112	*/
2113	#pragma pack(1)
2114	typedef union X86DESC
2115	{
2116	/** Generic descriptor view. */
2117	X86DESCGENERIC Gen;
2118	/** Gate descriptor view. */
2119	X86DESCGATE Gate;
2120
2121	/** 8 bit unsigned interger view. */
2122	uint8_t au8[8];
2123	/** 16 bit unsigned interger view. */
2124	uint16_t au16[4];
2125	/** 32 bit unsigned interger view. */
2126	uint32_t au32[2];
2127	} X86DESC;
2128	AssertCompileSize(X86DESC, 8);
2129	#pragma pack()
2130	/** Pointer to descriptor table entry. */
2131	typedef X86DESC *PX86DESC;
2132	/** Pointer to const descriptor table entry. */
2133	typedef const X86DESC *PCX86DESC;
2134
2135	/** @def X86DESC_BASE
2136	* Return the base address of a descriptor.
2137	*/
2138	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2139	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2140	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2141	\| ( (desc).Gen.u16BaseLow ) )
2142
2143	/** @def X86DESC_LIMIT
2144	* Return the limit of a descriptor.
2145	*/
2146	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2147	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2148	\| ( (desc).Gen.u16LimitLow ) )
2149
2150	/**
2151	* 64 bits generic descriptor table entry
2152	* Note: most of these bits have no meaning in long mode.
2153	*/
2154	#pragma pack(1)
2155	typedef struct X86DESC64GENERIC
2156	{
2157	/** Limit - Low word - IGNORED. */
2158	unsigned u16LimitLow : 16;
2159	/** Base address - lowe word. - IGNORED
2160	* Don't try set this to 24 because MSC is doing stupid things then. */
2161	unsigned u16BaseLow : 16;
2162	/** Base address - first 8 bits of high word. - IGNORED */
2163	unsigned u8BaseHigh1 : 8;
2164	/** Segment Type. */
2165	unsigned u4Type : 4;
2166	/** Descriptor Type. System(=0) or code/data selector */
2167	unsigned u1DescType : 1;
2168	/** Descriptor Privelege level. */
2169	unsigned u2Dpl : 2;
2170	/** Flags selector present(=1) or not. */
2171	unsigned u1Present : 1;
2172	/** Segment limit 16-19. - IGNORED */
2173	unsigned u4LimitHigh : 4;
2174	/** Available for system software. - IGNORED */
2175	unsigned u1Available : 1;
2176	/** Long mode flag. */
2177	unsigned u1Long : 1;
2178	/** This flags meaning depends on the segment type. Try make sense out
2179	* of the intel manual yourself. */
2180	unsigned u1DefBig : 1;
2181	/** Granularity of the limit. If set 4KB granularity is used, if
2182	* clear byte. - IGNORED */
2183	unsigned u1Granularity : 1;
2184	/** Base address - highest 8 bits. - IGNORED */
2185	unsigned u8BaseHigh2 : 8;
2186	/** Base address - bits 63-32. */
2187	unsigned u32BaseHigh3 : 32;
2188	unsigned u8Reserved : 8;
2189	unsigned u5Zeros : 5;
2190	unsigned u19Reserved : 19;
2191	} X86DESC64GENERIC;
2192	#pragma pack()
2193	/** Pointer to a generic descriptor entry. */
2194	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2195	/** Pointer to a const generic descriptor entry. */
2196	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2197
2198	/**
2199	* System descriptor table entry (64 bits)
2200	*
2201	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2202	*/
2203	#pragma pack(1)
2204	typedef struct X86DESC64SYSTEM
2205	{
2206	/** Limit - Low word. */
2207	unsigned u16LimitLow : 16;
2208	/** Base address - lowe word.
2209	* Don't try set this to 24 because MSC is doing stupid things then. */
2210	unsigned u16BaseLow : 16;
2211	/** Base address - first 8 bits of high word. */
2212	unsigned u8BaseHigh1 : 8;
2213	/** Segment Type. */
2214	unsigned u4Type : 4;
2215	/** Descriptor Type. System(=0) or code/data selector */
2216	unsigned u1DescType : 1;
2217	/** Descriptor Privelege level. */
2218	unsigned u2Dpl : 2;
2219	/** Flags selector present(=1) or not. */
2220	unsigned u1Present : 1;
2221	/** Segment limit 16-19. */
2222	unsigned u4LimitHigh : 4;
2223	/** Available for system software. */
2224	unsigned u1Available : 1;
2225	/** Reserved - 0. */
2226	unsigned u1Reserved : 1;
2227	/** This flags meaning depends on the segment type. Try make sense out
2228	* of the intel manual yourself. */
2229	unsigned u1DefBig : 1;
2230	/** Granularity of the limit. If set 4KB granularity is used, if
2231	* clear byte. */
2232	unsigned u1Granularity : 1;
2233	/** Base address - bits 31-24. */
2234	unsigned u8BaseHigh2 : 8;
2235	/** Base address - bits 63-32. */
2236	unsigned u32BaseHigh3 : 32;
2237	unsigned u8Reserved : 8;
2238	unsigned u5Zeros : 5;
2239	unsigned u19Reserved : 19;
2240	} X86DESC64SYSTEM;
2241	#pragma pack()
2242	/** Pointer to a system descriptor entry. */
2243	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2244	/** Pointer to a const system descriptor entry. */
2245	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2246
2247	/**
2248	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2249	*/
2250	typedef struct X86DESC64GATE
2251	{
2252	/** Target code segment offset - Low word. */
2253	unsigned u16OffsetLow : 16;
2254	/** Target code segment selector. */
2255	unsigned u16Sel : 16;
2256	/** Interrupt stack table for interrupt- and trap-gates.
2257	* Ignored by call-gates. */
2258	unsigned u3IST : 3;
2259	/** Reserved / ignored. */
2260	unsigned u5Reserved : 5;
2261	/** Segment Type. */
2262	unsigned u4Type : 4;
2263	/** Descriptor Type (0 = system). */
2264	unsigned u1DescType : 1;
2265	/** Descriptor Privelege level. */
2266	unsigned u2Dpl : 2;
2267	/** Flags selector present(=1) or not. */
2268	unsigned u1Present : 1;
2269	/** Target code segment offset - High word.
2270	* Ignored if task-gate. */
2271	unsigned u16OffsetHigh : 16;
2272	/** Target code segment offset - Top dword.
2273	* Ignored if task-gate. */
2274	unsigned u32OffsetTop : 32;
2275	/** Reserved / ignored / must be zero.
2276	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2277	unsigned u32Reserved : 32;
2278	} X86DESC64GATE;
2279	AssertCompileSize(X86DESC64GATE, 16);
2280	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2281	typedef X86DESC64GATE *PX86DESC64GATE;
2282	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2283	typedef const X86DESC64GATE *PCX86DESC64GATE;
2284
2285
2286	/**
2287	* Descriptor table entry.
2288	*/
2289	#pragma pack(1)
2290	typedef union X86DESC64
2291	{
2292	/** Generic descriptor view. */
2293	X86DESC64GENERIC Gen;
2294	/** System descriptor view. */
2295	X86DESC64SYSTEM System;
2296	/** Gate descriptor view. */
2297	X86DESC64GATE Gate;
2298
2299	/** 8 bit unsigned interger view. */
2300	uint8_t au8[16];
2301	/** 16 bit unsigned interger view. */
2302	uint16_t au16[8];
2303	/** 32 bit unsigned interger view. */
2304	uint32_t au32[4];
2305	/** 64 bit unsigned interger view. */
2306	uint64_t au64[2];
2307	} X86DESC64;
2308	AssertCompileSize(X86DESC64, 16);
2309	#pragma pack()
2310	/** Pointer to descriptor table entry. */
2311	typedef X86DESC64 *PX86DESC64;
2312	/** Pointer to const descriptor table entry. */
2313	typedef const X86DESC64 *PCX86DESC64;
2314
2315	/** @def X86DESC64_BASE
2316	* Return the base of a 64-bit descriptor.
2317	*/
2318	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2319	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2320	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2321	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2322	\| ( (desc).Gen.u16BaseLow ) )
2323
2324
2325
2326	/** @name Host system descriptor table entry - Use with care!
2327	* @{ */
2328	/** Host system descriptor table entry. */
2329	#if HC_ARCH_BITS == 64
2330	typedef X86DESC64 X86DESCHC;
2331	#else
2332	typedef X86DESC X86DESCHC;
2333	#endif
2334	/** Pointer to a host system descriptor table entry. */
2335	#if HC_ARCH_BITS == 64
2336	typedef PX86DESC64 PX86DESCHC;
2337	#else
2338	typedef PX86DESC PX86DESCHC;
2339	#endif
2340	/** Pointer to a const host system descriptor table entry. */
2341	#if HC_ARCH_BITS == 64
2342	typedef PCX86DESC64 PCX86DESCHC;
2343	#else
2344	typedef PCX86DESC PCX86DESCHC;
2345	#endif
2346	/** @} */
2347
2348
2349	/** @name Selector Descriptor Types.
2350	* @{
2351	*/
2352
2353	/** @name Non-System Selector Types.
2354	* @{ */
2355	/** Code(=set)/Data(=clear) bit. */
2356	#define X86_SEL_TYPE_CODE 8
2357	/** Memory(=set)/System(=clear) bit. */
2358	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2359	/** Accessed bit. */
2360	#define X86_SEL_TYPE_ACCESSED 1
2361	/** Expand down bit (for data selectors only). */
2362	#define X86_SEL_TYPE_DOWN 4
2363	/** Conforming bit (for code selectors only). */
2364	#define X86_SEL_TYPE_CONF 4
2365	/** Write bit (for data selectors only). */
2366	#define X86_SEL_TYPE_WRITE 2
2367	/** Read bit (for code selectors only). */
2368	#define X86_SEL_TYPE_READ 2
2369
2370	/** Read only selector type. */
2371	#define X86_SEL_TYPE_RO 0
2372	/** Accessed read only selector type. */
2373	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2374	/** Read write selector type. */
2375	#define X86_SEL_TYPE_RW 2
2376	/** Accessed read write selector type. */
2377	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2378	/** Expand down read only selector type. */
2379	#define X86_SEL_TYPE_RO_DOWN 4
2380	/** Accessed expand down read only selector type. */
2381	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2382	/** Expand down read write selector type. */
2383	#define X86_SEL_TYPE_RW_DOWN 6
2384	/** Accessed expand down read write selector type. */
2385	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2386	/** Execute only selector type. */
2387	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2388	/** Accessed execute only selector type. */
2389	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2390	/** Execute and read selector type. */
2391	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2392	/** Accessed execute and read selector type. */
2393	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2394	/** Conforming execute only selector type. */
2395	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2396	/** Accessed Conforming execute only selector type. */
2397	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2398	/** Conforming execute and write selector type. */
2399	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2400	/** Accessed Conforming execute and write selector type. */
2401	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2402	/** @} */
2403
2404
2405	/** @name System Selector Types.
2406	* @{ */
2407	/** Undefined system selector type. */
2408	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2409	/** 286 TSS selector. */
2410	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2411	/** LDT selector. */
2412	#define X86_SEL_TYPE_SYS_LDT 2
2413	/** 286 TSS selector - Busy. */
2414	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2415	/** 286 Callgate selector. */
2416	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2417	/** Taskgate selector. */
2418	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2419	/** 286 Interrupt gate selector. */
2420	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2421	/** 286 Trapgate selector. */
2422	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2423	/** Undefined system selector. */
2424	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2425	/** 386 TSS selector. */
2426	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2427	/** Undefined system selector. */
2428	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2429	/** 386 TSS selector - Busy. */
2430	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2431	/** 386 Callgate selector. */
2432	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2433	/** Undefined system selector. */
2434	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2435	/** 386 Interruptgate selector. */
2436	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2437	/** 386 Trapgate selector. */
2438	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2439	/** @} */
2440
2441	/** @name AMD64 System Selector Types.
2442	* @{ */
2443	#define AMD64_SEL_TYPE_SYS_LDT 2
2444	/** 286 TSS selector - Busy. */
2445	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2446	/** 386 TSS selector - Busy. */
2447	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2448	/** 386 Callgate selector. */
2449	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2450	/** 386 Interruptgate selector. */
2451	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2452	/** 386 Trapgate selector. */
2453	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2454	/** @} */
2455
2456	/** @} */
2457
2458
2459	/** @name Descriptor Table Entry Flag Masks.
2460	* These are for the 2nd 32-bit word of a descriptor.
2461	* @{ */
2462	/** Bits 8-11 - TYPE - Descriptor type mask. */
2463	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2464	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2465	#define X86_DESC_S RT_BIT(12)
2466	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2467	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2468	/** Bit 15 - P - Present. */
2469	#define X86_DESC_P RT_BIT(15)
2470	/** Bit 20 - AVL - Available for system software. */
2471	#define X86_DESC_AVL RT_BIT(20)
2472	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2473	#define X86_DESC_DB RT_BIT(22)
2474	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2475	* used, if clear byte. */
2476	#define X86_DESC_G RT_BIT(23)
2477	/** @} */
2478
2479	/** @} */
2480
2481	/** @name Task segment.
2482	* @{
2483	*/
2484	#pragma pack(1)
2485	typedef struct X86TSS32
2486	{
2487	/** Back link to previous task. (static) */
2488	RTSEL selPrev;
2489	uint16_t padding1;
2490	/** Ring-0 stack pointer. (static) */
2491	uint32_t esp0;
2492	/** Ring-0 stack segment. (static) */
2493	RTSEL ss0;
2494	uint16_t padding_ss0;
2495	/** Ring-1 stack pointer. (static) */
2496	uint32_t esp1;
2497	/** Ring-1 stack segment. (static) */
2498	RTSEL ss1;
2499	uint16_t padding_ss1;
2500	/** Ring-2 stack pointer. (static) */
2501	uint32_t esp2;
2502	/** Ring-2 stack segment. (static) */
2503	RTSEL ss2;
2504	uint16_t padding_ss2;
2505	/** Page directory for the task. (static) */
2506	uint32_t cr3;
2507	/** EIP before task switch. */
2508	uint32_t eip;
2509	/** EFLAGS before task switch. */
2510	uint32_t eflags;
2511	/** EAX before task switch. */
2512	uint32_t eax;
2513	/** ECX before task switch. */
2514	uint32_t ecx;
2515	/** EDX before task switch. */
2516	uint32_t edx;
2517	/** EBX before task switch. */
2518	uint32_t ebx;
2519	/** ESP before task switch. */
2520	uint32_t esp;
2521	/** EBP before task switch. */
2522	uint32_t ebp;
2523	/** ESI before task switch. */
2524	uint32_t esi;
2525	/** EDI before task switch. */
2526	uint32_t edi;
2527	/** ES before task switch. */
2528	RTSEL es;
2529	uint16_t padding_es;
2530	/** CS before task switch. */
2531	RTSEL cs;
2532	uint16_t padding_cs;
2533	/** SS before task switch. */
2534	RTSEL ss;
2535	uint16_t padding_ss;
2536	/** DS before task switch. */
2537	RTSEL ds;
2538	uint16_t padding_ds;
2539	/** FS before task switch. */
2540	RTSEL fs;
2541	uint16_t padding_fs;
2542	/** GS before task switch. */
2543	RTSEL gs;
2544	uint16_t padding_gs;
2545	/** LDTR before task switch. */
2546	RTSEL selLdt;
2547	uint16_t padding_ldt;
2548	/** Debug trap flag */
2549	uint16_t fDebugTrap;
2550	/** Offset relative to the TSS of the start of the I/O Bitmap
2551	* and the end of the interrupt redirection bitmap. */
2552	uint16_t offIoBitmap;
2553	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2554	uint8_t IntRedirBitmap[32];
2555	} X86TSS32;
2556	#pragma pack()
2557	/** Pointer to task segment. */
2558	typedef X86TSS32 *PX86TSS32;
2559	/** Pointer to const task segment. */
2560	typedef const X86TSS32 *PCX86TSS32;
2561	/** @} */
2562
2563
2564	/** @name 64 bits Task segment.
2565	* @{
2566	*/
2567	#pragma pack(1)
2568	typedef struct X86TSS64
2569	{
2570	/** Reserved. */
2571	uint32_t u32Reserved;
2572	/** Ring-0 stack pointer. (static) */
2573	uint64_t rsp0;
2574	/** Ring-1 stack pointer. (static) */
2575	uint64_t rsp1;
2576	/** Ring-2 stack pointer. (static) */
2577	uint64_t rsp2;
2578	/** Reserved. */
2579	uint32_t u32Reserved2[2];
2580	/* IST */
2581	uint64_t ist1;
2582	uint64_t ist2;
2583	uint64_t ist3;
2584	uint64_t ist4;
2585	uint64_t ist5;
2586	uint64_t ist6;
2587	uint64_t ist7;
2588	/* Reserved. */
2589	uint16_t u16Reserved[5];
2590	/** Offset relative to the TSS of the start of the I/O Bitmap
2591	* and the end of the interrupt redirection bitmap. */
2592	uint16_t offIoBitmap;
2593	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2594	uint8_t IntRedirBitmap[32];
2595	} X86TSS64;
2596	#pragma pack()
2597	/** Pointer to task segment. */
2598	typedef X86TSS64 *PX86TSS64;
2599	/** Pointer to const task segment. */
2600	typedef const X86TSS64 *PCX86TSS64;
2601	AssertCompileSize(X86TSS64, 136);
2602
2603	/** @} */
2604
2605
2606	/** @name Selectors.
2607	* @{
2608	*/
2609
2610	/**
2611	* The shift used to convert a selector from and to index an index (C).
2612	*/
2613	#define X86_SEL_SHIFT 3
2614
2615	/**
2616	* The mask used to mask off the table indicator and CPL of an selector.
2617	*/
2618	#define X86_SEL_MASK 0xfff8
2619
2620	/**
2621	* The bit indicating that a selector is in the LDT and not in the GDT.
2622	*/
2623	#define X86_SEL_LDT 0x0004
2624	/**
2625	* The bit mask for getting the RPL of a selector.
2626	*/
2627	#define X86_SEL_RPL 0x0003
2628
2629	/** @} */
2630
2631
2632	/**
2633	* x86 Exceptions/Faults/Traps.
2634	*/
2635	typedef enum X86XCPT
2636	{
2637	/** \#DE - Divide error. */
2638	X86_XCPT_DE = 0x00,
2639	/** \#DB - Debug event (single step, DRx, ..) */
2640	X86_XCPT_DB = 0x01,
2641	/** NMI - Non-Maskable Interrupt */
2642	X86_XCPT_NMI = 0x02,
2643	/** \#BP - Breakpoint (INT3). */
2644	X86_XCPT_BP = 0x03,
2645	/** \#OF - Overflow (INTO). */
2646	X86_XCPT_OF = 0x04,
2647	/** \#BR - Bound range exceeded (BOUND). */
2648	X86_XCPT_BR = 0x05,
2649	/** \#UD - Undefined opcode. */
2650	X86_XCPT_UD = 0x06,
2651	/** \#NM - Device not available (math coprocessor device). */
2652	X86_XCPT_NM = 0x07,
2653	/** \#DF - Double fault. */
2654	X86_XCPT_DF = 0x08,
2655	/** ??? - Coprocessor segment overrun (obsolete). */
2656	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2657	/** \#TS - Taskswitch (TSS). */
2658	X86_XCPT_TS = 0x0a,
2659	/** \#NP - Segment no present. */
2660	X86_XCPT_NP = 0x0b,
2661	/** \#SS - Stack segment fault. */
2662	X86_XCPT_SS = 0x0c,
2663	/** \#GP - General protection fault. */
2664	X86_XCPT_GP = 0x0d,
2665	/** \#PF - Page fault. */
2666	X86_XCPT_PF = 0x0e,
2667	/* 0x0f is reserved. */
2668	/** \#MF - Math fault (FPU). */
2669	X86_XCPT_MF = 0x10,
2670	/** \#AC - Alignment check. */
2671	X86_XCPT_AC = 0x11,
2672	/** \#MC - Machine check. */
2673	X86_XCPT_MC = 0x12,
2674	/** \#XF - SIMD Floating-Pointer Exception. */
2675	X86_XCPT_XF = 0x13
2676	} X86XCPT;
2677	/** Pointer to a x86 exception code. */
2678	typedef X86XCPT *PX86XCPT;
2679	/** Pointer to a const x86 exception code. */
2680	typedef const X86XCPT *PCX86XCPT;
2681
2682
2683	/** @name Trap Error Codes
2684	* @{
2685	*/
2686	/** External indicator. */
2687	#define X86_TRAP_ERR_EXTERNAL 1
2688	/** IDT indicator. */
2689	#define X86_TRAP_ERR_IDT 2
2690	/** Descriptor table indicator - If set LDT, if clear GDT. */
2691	#define X86_TRAP_ERR_TI 4
2692	/** Mask for getting the selector. */
2693	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2694	/** Shift for getting the selector table index (C type index). */
2695	#define X86_TRAP_ERR_SEL_SHIFT 3
2696	/** @} */
2697
2698
2699	/** @name \#PF Trap Error Codes
2700	* @{
2701	*/
2702	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2703	#define X86_TRAP_PF_P RT_BIT(0)
2704	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2705	#define X86_TRAP_PF_RW RT_BIT(1)
2706	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2707	#define X86_TRAP_PF_US RT_BIT(2)
2708	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2709	#define X86_TRAP_PF_RSVD RT_BIT(3)
2710	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2711	#define X86_TRAP_PF_ID RT_BIT(4)
2712	/** @} */
2713
2714	#pragma pack(1)
2715	/**
2716	* 32-bit IDTR/GDTR.
2717	*/
2718	typedef struct X86XDTR32
2719	{
2720	/** Size of the descriptor table. */
2721	uint16_t cb;
2722	/** Address of the descriptor table. */
2723	uint32_t uAddr;
2724	} X86XDTR32, *PX86XDTR32;
2725	#pragma pack()
2726
2727	#pragma pack(1)
2728	/**
2729	* 64-bit IDTR/GDTR.
2730	*/
2731	typedef struct X86XDTR64
2732	{
2733	/** Size of the descriptor table. */
2734	uint16_t cb;
2735	/** Address of the descriptor table. */
2736	uint64_t uAddr;
2737	} X86XDTR64, *PX86XDTR64;
2738	#pragma pack()
2739
2740	/** @} */
2741
2742	#endif
2743

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source: vbox/trunk/include/VBox/x86.h@ 28065

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