VirtualBox

source: vbox/trunk/include/VBox/x86.h@ 480

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1/** @file
2 * X86 (and AMD64) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006 InnoTek Systemberatung GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License as published by the Free Software Foundation,
12 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13 * distribution. VirtualBox OSE is distributed in the hope that it will
14 * be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * If you received this file as part of a commercial VirtualBox
17 * distribution, then only the terms of your commercial VirtualBox
18 * license agreement apply instead of the previous paragraph.
19 */
20
21/*
22 * x86.mac is generated from this file using:
23 * sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
24 */
25
26
27#ifndef __VBox_x86_h__
28#define __VBox_x86_h__
29
30#include <VBox/types.h>
31
32/** @defgroup grp_x86 x86 Types and Definitions
33 * @{
34 */
35
36/**
37 * EFLAGS Bits.
38 */
39typedef struct X86EFLAGSBITS
40{
41 /** Bit 0 - CF - Carry flag - Status flag. */
42 unsigned u1CF : 1;
43 /** Bit 1 - 1 - Reserved flag. */
44 unsigned u1Reserved0 : 1;
45 /** Bit 2 - PF - Parity flag - Status flag. */
46 unsigned u1PF : 1;
47 /** Bit 3 - 0 - Reserved flag. */
48 unsigned u1Reserved1 : 1;
49 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
50 unsigned u1AF : 1;
51 /** Bit 5 - 0 - Reserved flag. */
52 unsigned u1Reserved2 : 1;
53 /** Bit 6 - ZF - Zero flag - Status flag. */
54 unsigned u1ZF : 1;
55 /** Bit 7 - SF - Signed flag - Status flag. */
56 unsigned u1SF : 1;
57 /** Bit 8 - TF - Trap flag - System flag. */
58 unsigned u1TF : 1;
59 /** Bit 9 - IF - Interrupt flag - System flag. */
60 unsigned u1IF : 1;
61 /** Bit 10 - DF - Direction flag - Control flag. */
62 unsigned u1DF : 1;
63 /** Bit 11 - OF - Overflow flag - Status flag. */
64 unsigned u1OF : 1;
65 /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
66 unsigned u2IOPL : 2;
67 /** Bit 14 - NT - Nested task flag - System flag. */
68 unsigned u1NT : 1;
69 /** Bit 15 - 0 - Reserved flag. */
70 unsigned u1Reserved3 : 1;
71 /** Bit 16 - RF - Resume flag - System flag. */
72 unsigned u1RF : 1;
73 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
74 unsigned u1VM : 1;
75 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
76 unsigned u1AC : 1;
77 /** Bit 19 - VIF - Virtual interupt flag - System flag. */
78 unsigned u1VIF : 1;
79 /** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
80 unsigned u1VIP : 1;
81 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
82 unsigned u1ID : 1;
83 /** Bit 22-31 - 0 - Reserved flag. */
84 unsigned u10Reserved4 : 10;
85} X86EFLAGSBITS;
86/** Pointer to EFLAGS bits. */
87typedef X86EFLAGSBITS *PX86EFLAGSBITS;
88/** Pointer to const EFLAGS bits. */
89typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
90
91/**
92 * EFLAGS.
93 */
94typedef union X86EFLAGS
95{
96 /** The bitfield view. */
97 X86EFLAGSBITS Bits;
98 /** The 8-bit view. */
99 uint8_t au8[4];
100 /** The 16-bit view. */
101 uint16_t au16[2];
102 /** The 32-bit view. */
103 uint32_t au32[1];
104 /** The 32-bit view. */
105 uint32_t u32;
106} X86EFLAGS;
107/** Pointer to EFLAGS. */
108typedef X86EFLAGS *PX86EFLAGS;
109/** Pointer to const EFLAGS. */
110typedef const X86EFLAGS *PCX86EFLAGS;
111
112
113/** @name EFLAGS
114 * @{
115 */
116/** Bit 0 - CF - Carry flag - Status flag. */
117#define X86_EFL_CF BIT(0)
118/** Bit 2 - PF - Parity flag - Status flag. */
119#define X86_EFL_PF BIT(2)
120/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
121#define X86_EFL_AF BIT(4)
122/** Bit 6 - ZF - Zero flag - Status flag. */
123#define X86_EFL_ZF BIT(6)
124/** Bit 7 - SF - Signed flag - Status flag. */
125#define X86_EFL_SF BIT(7)
126/** Bit 8 - TF - Trap flag - System flag. */
127#define X86_EFL_TF BIT(8)
128/** Bit 9 - IF - Interrupt flag - System flag. */
129#define X86_EFL_IF BIT(9)
130/** Bit 10 - DF - Direction flag - Control flag. */
131#define X86_EFL_DF BIT(10)
132/** Bit 11 - OF - Overflow flag - Status flag. */
133#define X86_EFL_OF BIT(11)
134/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
135#define X86_EFL_IOPL (BIT(12) | BIT(13))
136/** Bit 14 - NT - Nested task flag - System flag. */
137#define X86_EFL_NT BIT(14)
138/** Bit 16 - RF - Resume flag - System flag. */
139#define X86_EFL_RF BIT(16)
140/** Bit 17 - VM - Virtual 8086 mode - System flag. */
141#define X86_EFL_VM BIT(17)
142/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
143#define X86_EFL_AC BIT(18)
144/** Bit 19 - VIF - Virtual interupt flag - System flag. */
145#define X86_EFL_VIF BIT(19)
146/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
147#define X86_EFL_VIP BIT(20)
148/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
149#define X86_EFL_ID BIT(21)
150/** IOPL shift. */
151#define X86_EFL_IOPL_SHIFT 12
152/** The the IOPL level from the flags. */
153#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
154/** @} */
155
156
157/** CPUID Feature information - ECX.
158 * CPUID query with EAX=1.
159 */
160typedef struct X86CPUIDFEATECX
161{
162 /** Bit 0 - SSE3 - Supports SSE3 or not. */
163 unsigned u1SSE3 : 1;
164 /** Reserved. */
165 unsigned u2Reserved1 : 2;
166 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
167 unsigned u1Monitor : 1;
168 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
169 unsigned u1CPLDS : 1;
170 /** Bit 5 - VMX - Virtual Machine Technology. */
171 unsigned u1VMX : 1;
172 /** Reserved. */
173 unsigned u1Reserved2 : 1;
174 /** Bit 7 - EST - Enh. SpeedStep Tech. */
175 unsigned u1EST : 1;
176 /** Bit 8 - TM2 - Terminal Monitor 2. */
177 unsigned u1TM2 : 1;
178 /** Reserved. */
179 unsigned u1Reserved3 : 1;
180 /** Bit 10 - CNTX-ID - L1 Context ID. */
181 unsigned u1CNTXID : 1;
182 /** Reserved. */
183 unsigned u2Reserved4 : 2;
184 /** Bit 13 - CX16 - CMPXCHG16B. */
185 unsigned u1CX16 : 1;
186 /** Reserved. */
187 unsigned u18Reserved5 : 18;
188
189} X86CPUIDFEATECX;
190/** Pointer to CPUID Feature Information - ECX. */
191typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
192/** Pointer to const CPUID Feature Information - ECX. */
193typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
194
195
196/** CPUID Feature Information - EDX.
197 * CPUID query with EAX=1.
198 */
199typedef struct X86CPUIDFEATEDX
200{
201 /** Bit 0 - FPU - x87 FPU on Chip. */
202 unsigned u1FPU : 1;
203 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
204 unsigned u1VME : 1;
205 /** Bit 2 - DE - Debugging extensions. */
206 unsigned u1DE : 1;
207 /** Bit 3 - PSE - Page Size Extension. */
208 unsigned u1PSE : 1;
209 /** Bit 4 - TSC - Tiem Stamp Counter. */
210 unsigned u1TSC : 1;
211 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
212 unsigned u1MSR : 1;
213 /** Bit 6 - PAE - Physical Address Extension. */
214 unsigned u1PAE : 1;
215 /** Bit 7 - MCE - Machine Check Exception. */
216 unsigned u1MCE : 1;
217 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
218 unsigned u1CX8 : 1;
219 /** Bit 9 - APIC - APIC On-Chick. */
220 unsigned u1APIC : 1;
221 /** Bit 10 - Reserved. */
222 unsigned u1Reserved1 : 1;
223 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
224 unsigned u1SEP : 1;
225 /** Bit 12 - MTRR - Memory Type Range Registers. */
226 unsigned u1MTRR : 1;
227 /** Bit 13 - PGE - PTE Global Bit. */
228 unsigned u1PGE : 1;
229 /** Bit 14 - MCA - Machine Check Architecture. */
230 unsigned u1MCA : 1;
231 /** Bit 15 - CMOV - Conditional Move Instructions. */
232 unsigned u1CMOV : 1;
233 /** Bit 16 - PAT - Page Attribute Table. */
234 unsigned u1PAT : 1;
235 /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
236 unsigned u1PSE36 : 1;
237 /** Bit 18 - PSN - Processor Serial Number. */
238 unsigned u1PSN : 1;
239 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
240 unsigned u1CLFSH : 1;
241 /** Bit 20 - Reserved. */
242 unsigned u1Reserved2 : 1;
243 /** Bit 21 - DS - Debug Store. */
244 unsigned u1DS : 1;
245 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
246 unsigned u1ACPI : 1;
247 /** Bit 23 - MMX - Intel MMX 'Technology'. */
248 unsigned u1MMX : 1;
249 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
250 unsigned u1FXSR : 1;
251 /** Bit 25 - SSE - SSE Support. */
252 unsigned u1SSE : 1;
253 /** Bit 26 - SSE2 - SSE2 Support. */
254 unsigned u1SSE2 : 1;
255 /** Bit 27 - SS - Self Snoop. */
256 unsigned u1SS : 1;
257 /** Bit 28 - HTT - Hyper-Threading Technology. */
258 unsigned u1HTT : 1;
259 /** Bit 29 - TM - Thermal Monitor. */
260 unsigned u1TM : 1;
261 /** Bit 30 - Reserved - . */
262 unsigned u1Reserved3 : 1;
263 /** Bit 31 - PBE - Pending Break Enabled. */
264 unsigned u1PBE : 1;
265} X86CPUIDFEATEDX;
266/** Pointer to CPUID Feature Information - EDX. */
267typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
268/** Pointer to const CPUID Feature Information - EDX. */
269typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
270
271
272/** @name CPUID Feature information.
273 * CPUID query with EAX=1.
274 * @{
275 */
276/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
277#define X86_CPUID_FEATURE_ECX_SSE3 BIT(0)
278/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
279#define X86_CPUID_FEATURE_ECX_MONITOR BIT(3)
280/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
281#define X86_CPUID_FEATURE_ECX_CPLDS BIT(4)
282/** ECX Bit 5 - VMX - Virtual Machine Technology. */
283#define X86_CPUID_FEATURE_ECX_VMX BIT(5)
284/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
285#define X86_CPUID_FEATURE_ECX_EST BIT(7)
286/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
287#define X86_CPUID_FEATURE_ECX_TM2 BIT(8)
288/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
289#define X86_CPUID_FEATURE_ECX_CNTXID BIT(10)
290/** ECX Bit 13 - CX16 - L1 Context ID. */
291#define X86_CPUID_FEATURE_ECX_CX16 BIT(13)
292
293
294/** Bit 0 - FPU - x87 FPU on Chip. */
295#define X86_CPUID_FEATURE_EDX_FPU BIT(0)
296/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
297#define X86_CPUID_FEATURE_EDX_VME BIT(1)
298/** Bit 2 - DE - Debugging extensions. */
299#define X86_CPUID_FEATURE_EDX_DE BIT(2)
300/** Bit 3 - PSE - Page Size Extension. */
301#define X86_CPUID_FEATURE_EDX_PSE BIT(3)
302/** Bit 4 - TSC - Time Stamp Counter. */
303#define X86_CPUID_FEATURE_EDX_TSC BIT(4)
304/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
305#define X86_CPUID_FEATURE_EDX_MSR BIT(5)
306/** Bit 6 - PAE - Physical Address Extension. */
307#define X86_CPUID_FEATURE_EDX_PAE BIT(6)
308/** Bit 7 - MCE - Machine Check Exception. */
309#define X86_CPUID_FEATURE_EDX_MCE BIT(7)
310/** Bit 8 - CX8 - CMPXCHG8B instruction. */
311#define X86_CPUID_FEATURE_EDX_CX8 BIT(8)
312/** Bit 9 - APIC - APIC On-Chip. */
313#define X86_CPUID_FEATURE_EDX_APIC BIT(9)
314/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
315#define X86_CPUID_FEATURE_EDX_SEP BIT(11)
316/** Bit 12 - MTRR - Memory Type Range Registers. */
317#define X86_CPUID_FEATURE_EDX_MTRR BIT(12)
318/** Bit 13 - PGE - PTE Global Bit. */
319#define X86_CPUID_FEATURE_EDX_PGE BIT(13)
320/** Bit 14 - MCA - Machine Check Architecture. */
321#define X86_CPUID_FEATURE_EDX_MCA BIT(14)
322/** Bit 15 - CMOV - Conditional Move Instructions. */
323#define X86_CPUID_FEATURE_EDX_CMOV BIT(15)
324/** Bit 16 - PAT - Page Attribute Table. */
325#define X86_CPUID_FEATURE_EDX_PAT BIT(16)
326/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
327#define X86_CPUID_FEATURE_EDX_PSE36 BIT(17)
328/** Bit 18 - PSN - Processor Serial Number. */
329#define X86_CPUID_FEATURE_EDX_PSN BIT(18)
330/** Bit 19 - CLFSH - CLFLUSH Instruction. */
331#define X86_CPUID_FEATURE_EDX_CLFSH BIT(19)
332/** Bit 21 - DS - Debug Store. */
333#define X86_CPUID_FEATURE_EDX_DS BIT(21)
334/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
335#define X86_CPUID_FEATURE_EDX_ACPI BIT(22)
336/** Bit 23 - MMX - Intel MMX Technology. */
337#define X86_CPUID_FEATURE_EDX_MMX BIT(23)
338/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
339#define X86_CPUID_FEATURE_EDX_FXSR BIT(24)
340/** Bit 25 - SSE - SSE Support. */
341#define X86_CPUID_FEATURE_EDX_SSE BIT(25)
342/** Bit 26 - SSE2 - SSE2 Support. */
343#define X86_CPUID_FEATURE_EDX_SSE2 BIT(26)
344/** Bit 27 - SS - Self Snoop. */
345#define X86_CPUID_FEATURE_EDX_SS BIT(27)
346/** Bit 28 - HTT - Hyper-Threading Technology. */
347#define X86_CPUID_FEATURE_EDX_HTT BIT(28)
348/** Bit 29 - TM - Therm. Monitor. */
349#define X86_CPUID_FEATURE_EDX_TM BIT(29)
350/** Bit 31 - PBE - Pending Break Enabled. */
351#define X86_CPUID_FEATURE_EDX_PBE BIT(31)
352/** @} */
353
354
355/** @name CPUID AMD Feature information.
356 * CPUID query with EAX=0x80000001.
357 * @{
358 */
359/** Bit 0 - FPU - x87 FPU on Chip. */
360#define X86_CPUID_AMD_FEATURE_EDX_FPU BIT(0)
361/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
362#define X86_CPUID_AMD_FEATURE_EDX_VME BIT(1)
363/** Bit 2 - DE - Debugging extensions. */
364#define X86_CPUID_AMD_FEATURE_EDX_DE BIT(2)
365/** Bit 3 - PSE - Page Size Extension. */
366#define X86_CPUID_AMD_FEATURE_EDX_PSE BIT(3)
367/** Bit 4 - TSC - Time Stamp Counter. */
368#define X86_CPUID_AMD_FEATURE_EDX_TSC BIT(4)
369/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
370#define X86_CPUID_AMD_FEATURE_EDX_MSR BIT(5)
371/** Bit 6 - PAE - Physical Address Extension. */
372#define X86_CPUID_AMD_FEATURE_EDX_PAE BIT(6)
373/** Bit 7 - MCE - Machine Check Exception. */
374#define X86_CPUID_AMD_FEATURE_EDX_MCE BIT(7)
375/** Bit 8 - CX8 - CMPXCHG8B instruction. */
376#define X86_CPUID_AMD_FEATURE_EDX_CX8 BIT(8)
377/** Bit 9 - APIC - APIC On-Chip. */
378#define X86_CPUID_AMD_FEATURE_EDX_APIC BIT(9)
379/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
380#define X86_CPUID_AMD_FEATURE_EDX_SEP BIT(11)
381/** Bit 12 - MTRR - Memory Type Range Registers. */
382#define X86_CPUID_AMD_FEATURE_EDX_MTRR BIT(12)
383/** Bit 13 - PGE - PTE Global Bit. */
384#define X86_CPUID_AMD_FEATURE_EDX_PGE BIT(13)
385/** Bit 14 - MCA - Machine Check Architecture. */
386#define X86_CPUID_AMD_FEATURE_EDX_MCA BIT(14)
387/** Bit 15 - CMOV - Conditional Move Instructions. */
388#define X86_CPUID_AMD_FEATURE_EDX_CMOV BIT(15)
389/** Bit 16 - PAT - Page Attribute Table. */
390#define X86_CPUID_AMD_FEATURE_EDX_PAT BIT(16)
391/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
392#define X86_CPUID_AMD_FEATURE_EDX_PSE36 BIT(17)
393/** Bit 20 - NX - AMD No-Execute Page Protection. */
394#define X86_CPUID_AMD_FEATURE_EDX_NX BIT(20)
395/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
396#define X86_CPUID_AMD_FEATURE_EDX_AXMMX BIT(22)
397/** Bit 23 - MMX - Intel MMX Technology. */
398#define X86_CPUID_AMD_FEATURE_EDX_MMX BIT(23)
399/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
400#define X86_CPUID_AMD_FEATURE_EDX_FXSR BIT(24)
401/** Bit 25 - ???? - AMD fast FXSAVE and FXRSTOR Instructions. */
402#define X86_CPUID_AMD_FEATURE_EDX_FFXSR BIT(25)
403/** Bit 29 - ???? - AMD Long Mode. */
404#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE BIT(29)
405/** Bit 30 - ???? - AMD Extensions to 3DNow. */
406#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX BIT(30)
407/** Bit 31 - ???? - AMD 3DNow. */
408#define X86_CPUID_AMD_FEATURE_EDX_3DNOW BIT(31)
409
410/** Bit 1 - LAHF/SAHF - ???. */
411/*define X86_CPUID_AMD_FEATURE_ECX_TODO BIT(0)*/
412/** Bit 1 - CMPL - ???. */
413#define X86_CPUID_AMD_FEATURE_ECX_CMPL BIT(1)
414/** Bit 2 - SVM - AMD VM extensions. */
415#define X86_CPUID_AMD_FEATURE_ECX_SVM BIT(2)
416/** Bit 4 - CR8L - ???. */
417#define X86_CPUID_AMD_FEATURE_ECX_CR8L BIT(4)
418
419/** @} */
420
421
422/** @name CR0
423 * @{ */
424/** Bit 0 - PE - Protection Enabled */
425#define X86_CR0_PE BIT(0)
426#define X86_CR0_PROTECTION_ENABLE BIT(0)
427/** Bit 1 - MP - Monitor Coprocessor */
428#define X86_CR0_MP BIT(1)
429#define X86_CR0_MONITOR_COPROCESSOR BIT(1)
430/** Bit 2 - EM - Emulation. */
431#define X86_CR0_EM BIT(2)
432#define X86_CR0_EMULATE_FPU BIT(2)
433/** Bit 3 - TS - Task Switch. */
434#define X86_CR0_TS BIT(3)
435#define X86_CR0_TASK_SWITCH BIT(3)
436/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
437#define X86_CR0_ET BIT(4)
438#define X86_CR0_EXTENSION_TYPE BIT(4)
439/** Bit 5 - NE - Numeric error. */
440#define X86_CR0_NE BIT(5)
441#define X86_CR0_NUMERIC_ERROR BIT(5)
442/** Bit 16 - WP - Write Protect. */
443#define X86_CR0_WP BIT(16)
444#define X86_CR0_WRITE_PROTECT BIT(16)
445/** Bit 18 - AM - Alignment Mask. */
446#define X86_CR0_AM BIT(18)
447#define X86_CR0_ALIGMENT_MASK BIT(18)
448/** Bit 29 - NW - Not Write-though. */
449#define X86_CR0_NW BIT(29)
450#define X86_CR0_NOT_WRITE_THROUGH BIT(29)
451/** Bit 30 - WP - Cache Disable. */
452#define X86_CR0_CD BIT(30)
453#define X86_CR0_CACHE_DISABLE BIT(30)
454/** Bit 31 - PG - Paging. */
455#define X86_CR0_PG BIT(31)
456#define X86_CR0_PAGING BIT(31)
457/** @} */
458
459
460/** @name CR3
461 * @{ */
462/** Bit 3 - PWT - Page-level Writes Transparent. */
463#define X86_CR3_PWT BIT(3)
464/** Bit 4 - PCD - Page-level Cache Disable. */
465#define X86_CR3_PCD BIT(4)
466/** Bits 12-31 - - Page directory page number. */
467#define X86_CR3_PAGE_MASK (0xfffff000)
468/** Bits 5-31 - - PAE Page directory page number. */
469#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
470/** @} */
471
472
473/** @name CR4
474 * @{ */
475/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
476#define X86_CR4_VME BIT(0)
477/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
478#define X86_CR4_PVI BIT(1)
479/** Bit 2 - TSD - Time Stamp Disable. */
480#define X86_CR4_TSD BIT(2)
481/** Bit 3 - DE - Debugging Extensions. */
482#define X86_CR4_DE BIT(3)
483/** Bit 4 - PSE - Page Size Extension. */
484#define X86_CR4_PSE BIT(4)
485/** Bit 5 - PAE - Physical Address Extension. */
486#define X86_CR4_PAE BIT(5)
487/** Bit 6 - MCE - Machine-Check Enable. */
488#define X86_CR4_MCE BIT(6)
489/** Bit 7 - PGE - Page Global Enable. */
490#define X86_CR4_PGE BIT(7)
491/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
492#define X86_CR4_PCE BIT(8)
493/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
494#define X86_CR4_OSFSXR BIT(9)
495/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
496#define X86_CR4_OSXMMEEXCPT BIT(10)
497/** Bit 13 - VMXE - VMX mode is enabled. */
498#define X86_CR4_VMXE BIT(13)
499/** @} */
500
501
502/** @name DR6
503 * @{ */
504/** Bit 0 - B0 - Breakpoint 0 condition detected. */
505#define X86_DR6_B0 BIT(0)
506/** Bit 1 - B1 - Breakpoint 1 condition detected. */
507#define X86_DR6_B1 BIT(1)
508/** Bit 2 - B2 - Breakpoint 2 condition detected. */
509#define X86_DR6_B2 BIT(2)
510/** Bit 3 - B3 - Breakpoint 3 condition detected. */
511#define X86_DR6_B3 BIT(3)
512/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
513#define X86_DR6_BD BIT(13)
514/** Bit 14 - BS - Single step */
515#define X86_DR6_BS BIT(14)
516/** Bit 15 - BT - Task switch. (TSS T bit.) */
517#define X86_DR6_BT BIT(15)
518/** @} */
519
520
521/** @name DR7
522 * @{ */
523/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
524#define X86_DR7_L0 BIT(0)
525/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
526#define X86_DR7_G0 BIT(1)
527/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
528#define X86_DR7_L1 BIT(2)
529/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
530#define X86_DR7_G1 BIT(3)
531/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
532#define X86_DR7_L2 BIT(4)
533/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
534#define X86_DR7_G2 BIT(5)
535/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
536#define X86_DR7_L3 BIT(6)
537/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
538#define X86_DR7_G3 BIT(7)
539/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
540#define X86_DR7_LE BIT(8)
541/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
542#define X86_DR7_GE BIT(9)
543
544/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
545 * any DR register is accessed. */
546#define X86_DR7_GD BIT(13)
547/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
548#define X86_DR7_RW0_MASK (3 << 16)
549/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
550#define X86_DR7_LEN0_MASK (3 << 18)
551/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
552#define X86_DR7_RW1_MASK (3 << 20)
553/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
554#define X86_DR7_LEN1_MASK (3 << 22)
555/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
556#define X86_DR7_RW2_MASK (3 << 24)
557/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
558#define X86_DR7_LEN2_MASK (3 << 26)
559/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
560#define X86_DR7_RW3_MASK (3 << 28)
561/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
562#define X86_DR7_LEN3_MASK (3 << 30)
563
564/** Bits which must be 1s. */
565#define X86_DR7_MB1_MASK (BIT(10))
566
567/** Calcs the L bit of Nth breakpoint.
568 * @param iBp The breakpoint number [0..3].
569 */
570#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
571
572/** Calcs the G bit of Nth breakpoint.
573 * @param iBp The breakpoint number [0..3].
574 */
575#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
576
577/** @name Read/Write values.
578 * @{ */
579/** Break on instruction fetch only. */
580#define X86_DR7_RW_EO 0
581/** Break on write only. */
582#define X86_DR7_RW_WO 1
583/** Break on I/O read/write. This is only defined if CR4.DE is set. */
584#define X86_DR7_RW_IO 2
585/** Break on read or write (but not instruction fetches). */
586#define X86_DR7_RW_RW 3
587/** @} */
588
589/** Shifts a X86_DR7_RW_* value to its right place.
590 * @param iBp The breakpoint number [0..3].
591 * @param fRw One of the X86_DR7_RW_* value.
592 */
593#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
594
595/** @name Length values.
596 * @{ */
597#define X86_DR7_LEN_BYTE 0
598#define X86_DR7_LEN_WORD 1
599#define X86_DR7_LEN_QWORD 2 /**< AMD64 long mode only. */
600#define X86_DR7_LEN_DWORD 3
601/** @} */
602
603/** Shifts a X86_DR7_LEN_* value to its right place.
604 * @param iBp The breakpoint number [0..3].
605 * @param cb One of the X86_DR7_LEN_* values.
606 */
607#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
608
609/** Mask used to check if any breakpoints are enabled. */
610#define X86_DR7_ENABLED_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(7))
611
612/** @} */
613
614
615/** @name Machine Specific Registers
616 * @{
617 */
618/** CPU Feature control. */
619#define MSR_IA32_FEATURE_CONTROL 0x3A
620#define MSR_IA32_FEATURE_CONTROL_LOCK BIT(0)
621#define MSR_IA32_FEATURE_CONTROL_VMXON BIT(2)
622
623
624#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
625/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
626 * R0 SS == CS + 8
627 * R3 CS == CS + 16
628 * R3 SS == CS + 24
629 */
630#define MSR_IA32_SYSENTER_CS 0x174
631/** SYSENTER_ESP - the R0 ESP. */
632#define MSR_IA32_SYSENTER_ESP 0x175
633/** SYSENTER_EIP - the R0 EIP. */
634#define MSR_IA32_SYSENTER_EIP 0x176
635#endif
636
637/** Basic VMX information. */
638#define MSR_IA32_VMX_BASIC_INFO 0x480
639/** Allowed settings for pin-based VM execution controls */
640#define MSR_IA32_VMX_PINBASED_CTLS 0x481
641/** Allowed settings for proc-based VM execution controls */
642#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
643/** Allowed settings for the VMX exit controls. */
644#define MSR_IA32_VMX_EXIT_CTLS 0x483
645/** Allowed settings for the VMX entry controls. */
646#define MSR_IA32_VMX_ENTRY_CTLS 0x484
647/** Misc VMX info. */
648#define MSR_IA32_VMX_MISC 0x485
649/** Fixed cleared bits in CR0. */
650#define MSR_IA32_VMX_CR0_FIXED0 0x486
651/** Fixed set bits in CR0. */
652#define MSR_IA32_VMX_CR0_FIXED1 0x487
653/** Fixed cleared bits in CR4. */
654#define MSR_IA32_VMX_CR4_FIXED0 0x488
655/** Fixed set bits in CR4. */
656#define MSR_IA32_VMX_CR4_FIXED1 0x489
657/** Information for enumerating fields in the VMCS. */
658#define MSR_IA32_VMX_VMCS_ENUM 0x48A
659
660
661/** K6 EFER - Extended Feature Enable Register. */
662#define MSR_K6_EFER 0xc0000080
663/** @todo document EFER */
664/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
665#define MSR_K6_EFER_SCE BIT(0)
666/** Bit 8 - LME - Long mode enabled. (R/W) */
667#define MSR_K6_EFER_LME BIT(8)
668/** Bit 10 - LMA - Long mode active. (R) */
669#define MSR_K6_EFER_LMA BIT(10)
670/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
671#define MSR_K6_EFER_NXE BIT(11)
672/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
673#define MSR_K6_EFER_SVME BIT(12)
674/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
675#define MSR_K6_EFER_LMSLE BIT(13)
676/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
677#define MSR_K6_EFER_FFXSR BIT(14)
678/** K6 STAR - SYSCALL/RET targets. */
679#define MSR_K6_STAR 0xc0000081
680/** Shift value for getting the SYSRET CS and SS value. */
681#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
682/** Shift value for getting the SYSCALL CS and SS value. */
683#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
684/** Selector mask for use after shifting. */
685#define MSR_K6_STAR_SEL_MASK 0xffff
686/** The mask which give the SYSCALL EIP. */
687#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
688/** K6 WHCR - Write Handling Control Register. */
689#define MSR_K6_WHCR 0xc0000082
690/** K6 UWCCR - UC/WC Cacheability Control Register. */
691#define MSR_K6_UWCCR 0xc0000085
692/** K6 PSOR - Processor State Observability Register. */
693#define MSR_K6_PSOR 0xc0000087
694/** K6 PFIR - Page Flush/Invalidate Register. */
695#define MSR_K6_PFIR 0xc0000088
696
697#define MSR_K7_EVNTSEL0 0xc0010000
698#define MSR_K7_EVNTSEL1 0xc0010001
699#define MSR_K7_EVNTSEL2 0xc0010002
700#define MSR_K7_EVNTSEL3 0xc0010003
701#define MSR_K7_PERFCTR0 0xc0010004
702#define MSR_K7_PERFCTR1 0xc0010005
703#define MSR_K7_PERFCTR2 0xc0010006
704#define MSR_K7_PERFCTR3 0xc0010007
705
706/** K8 LSTAR - Long mode SYSCALL target (RIP). */
707#define MSR_K8_LSTAR 0xc0000082
708/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
709#define MSR_K8_CSTAR 0xc0000083
710/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
711#define MSR_K8_SF_MASK 0xc0000084
712/** K8 FS.base - The 64-bit base FS register. */
713#define MSR_K8_FS_BASE 0xc0000100
714/** K8 GS.base - The 64-bit base GS register. */
715#define MSR_K8_GS_BASE 0xc0000101
716/** K8 KernelGSbase - Used with SWAPGS. */
717#define MSR_K8_KERNEL_GS_BASE 0xc0000102
718#define MSR_K8_TSC_AUX 0xc0000103
719#define MSR_K8_SYSCFG 0xc0010010
720#define MSR_K8_HWCR 0xc0010015
721#define MSR_K8_IORRBASE0 0xc0010016
722#define MSR_K8_IORRMASK0 0xc0010017
723#define MSR_K8_IORRBASE1 0xc0010018
724#define MSR_K8_IORRMASK1 0xc0010019
725#define MSR_K8_TOP_MEM1 0xc001001a
726#define MSR_K8_TOP_MEM2 0xc001001d
727#define MSR_K8_VM_CR 0xc0010114
728#define MSR_K8_IGNNE 0xc0010115
729#define MSR_K8_SMM_CTL 0xc0010116
730/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
731 * host state during world switch.
732 */
733#define MSR_K8_VM_HSAVE_PA 0xc0010117
734
735/** @} */
736
737
738/** @name Page Table / Directory / Directory Pointers / L4.
739 * @{
740 */
741
742/** Page table/directory entry as an unsigned integer. */
743typedef uint32_t X86PGUINT;
744/** Pointer to a page table/directory table entry as an unsigned integer. */
745typedef X86PGUINT *PX86PGUINT;
746
747/** Number of entries in a 32-bit PT/PD. */
748#define X86_PG_ENTRIES 1024
749
750
751/** PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
752typedef uint64_t X86PGPAEUINT;
753/** Pointer to a PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
754typedef X86PGPAEUINT *PX86PGPAEUINT;
755
756/** Number of entries in a PAE PT/PD/PDPTR/L4/L5. */
757#define X86_PG_PAE_ENTRIES 512
758
759
760/** The size of a 4KB page. */
761#define X86_PAGE_4K_SIZE _4K
762/** The page shift of a 4KB page. */
763#define X86_PAGE_4K_SHIFT 12
764/** The 4KB page offset mask. */
765#define X86_PAGE_4K_OFFSET_MASK 0xfff
766/** The 4KB page base mask for virtual addresses. */
767#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
768/** The 4KB page base mask for virtual addresses - 32bit version. */
769#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
770
771/** The size of a 2MB page. */
772#define X86_PAGE_2M_SIZE _2M
773/** The page shift of a 2MB page. */
774#define X86_PAGE_2M_SHIFT 21
775/** The 2MB page offset mask. */
776#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
777/** The 2MB page base mask for virtual addresses. */
778#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
779/** The 2MB page base mask for virtual addresses - 32bit version. */
780#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
781
782/** The size of a 4MB page. */
783#define X86_PAGE_4M_SIZE _4M
784/** The page shift of a 4MB page. */
785#define X86_PAGE_4M_SHIFT 22
786/** The 4MB page offset mask. */
787#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
788/** The 4MB page base mask for virtual addresses. */
789#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
790/** The 4MB page base mask for virtual addresses - 32bit version. */
791#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
792
793
794
795/** @name Page Table Entry
796 * @{
797 */
798/** Bit 0 - P - Present bit. */
799#define X86_PTE_P BIT(0)
800/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
801#define X86_PTE_RW BIT(1)
802/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
803#define X86_PTE_US BIT(2)
804/** Bit 3 - PWT - Page level write thru bit. */
805#define X86_PTE_PWT BIT(3)
806/** Bit 4 - PCD - Page level cache disable bit. */
807#define X86_PTE_PCD BIT(4)
808/** Bit 5 - A - Access bit. */
809#define X86_PTE_A BIT(5)
810/** Bit 6 - D - Dirty bit. */
811#define X86_PTE_D BIT(6)
812/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
813#define X86_PTE_PAT BIT(7)
814/** Bit 8 - G - Global flag. */
815#define X86_PTE_G BIT(8)
816/** Bits 9-11 - - Available for use to system software. */
817#define X86_PTE_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
818/** Bits 12-31 - - Physical Page number of the next level. */
819#define X86_PTE_PG_MASK ( 0xfffff000 )
820
821/** Bits 12-51 - - PAE - Physical Page number of the next level. */
822#if 1 /* we're using this internally and have to mask of the top 16-bit. */
823#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
824#else
825#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
826#endif
827/** Bits 63 - NX - PAE - No execution flag. */
828#define X86_PTE_PAE_NX BIT64(63)
829
830/**
831 * Page table entry.
832 */
833typedef struct X86PTEBITS
834{
835 /** Flags whether(=1) or not the page is present. */
836 unsigned u1Present : 1;
837 /** Read(=0) / Write(=1) flag. */
838 unsigned u1Write : 1;
839 /** User(=1) / Supervisor (=0) flag. */
840 unsigned u1User : 1;
841 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
842 unsigned u1WriteThru : 1;
843 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
844 unsigned u1CacheDisable : 1;
845 /** Accessed flag.
846 * Indicates that the page have been read or written to. */
847 unsigned u1Accessed : 1;
848 /** Dirty flag.
849 * Indicates that the page have been written to. */
850 unsigned u1Dirty : 1;
851 /** Reserved / If PAT enabled, bit 2 of the index. */
852 unsigned u1PAT : 1;
853 /** Global flag. (Ignored in all but final level.) */
854 unsigned u1Global : 1;
855 /** Available for use to system software. */
856 unsigned u3Available : 3;
857 /** Physical Page number of the next level. */
858 unsigned u20PageNo : 20;
859} X86PTEBITS;
860/** Pointer to a page table entry. */
861typedef X86PTEBITS *PX86PTEBITS;
862/** Pointer to a const page table entry. */
863typedef const X86PTEBITS *PCX86PTEBITS;
864
865/**
866 * Page table entry.
867 */
868typedef union X86PTE
869{
870 /** Bit field view. */
871 X86PTEBITS n;
872 /** Unsigned integer view */
873 X86PGUINT u;
874 /** 32-bit view. */
875 uint32_t au32[1];
876 /** 16-bit view. */
877 uint16_t au16[2];
878 /** 8-bit view. */
879 uint8_t au8[4];
880} X86PTE;
881/** Pointer to a page table entry. */
882typedef X86PTE *PX86PTE;
883/** Pointer to a const page table entry. */
884typedef const X86PTE *PCX86PTE;
885
886
887/**
888 * PAE page table entry.
889 */
890typedef struct X86PTEPAEBITS
891{
892 /** Flags whether(=1) or not the page is present. */
893 uint32_t u1Present : 1;
894 /** Read(=0) / Write(=1) flag. */
895 uint32_t u1Write : 1;
896 /** User(=1) / Supervisor(=0) flag. */
897 uint32_t u1User : 1;
898 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
899 uint32_t u1WriteThru : 1;
900 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
901 uint32_t u1CacheDisable : 1;
902 /** Accessed flag.
903 * Indicates that the page have been read or written to. */
904 uint32_t u1Accessed : 1;
905 /** Dirty flag.
906 * Indicates that the page have been written to. */
907 uint32_t u1Dirty : 1;
908 /** Reserved / If PAT enabled, bit 2 of the index. */
909 uint32_t u1PAT : 1;
910 /** Global flag. (Ignored in all but final level.) */
911 uint32_t u1Global : 1;
912 /** Available for use to system software. */
913 uint32_t u3Available : 3;
914 /** Physical Page number of the next level - Low Part. Don't use this. */
915 uint32_t u20PageNoLow : 20;
916 /** Physical Page number of the next level - High Part. Don't use this. */
917 uint32_t u20PageNoHigh : 20;
918 /** MBZ bits */
919 uint32_t u11Reserved : 11;
920 /** No Execute flag. */
921 uint32_t u1NoExecute : 1;
922} X86PTEPAEBITS;
923/** Pointer to a page table entry. */
924typedef X86PTEPAEBITS *PX86PTEPAEBITS;
925/** Pointer to a page table entry. */
926typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
927
928/**
929 * PAE Page table entry.
930 */
931typedef union X86PTEPAE
932{
933 /** Bit field view. */
934 X86PTEPAEBITS n;
935 /** Unsigned integer view */
936 X86PGPAEUINT u;
937 /** 32-bit view. */
938 uint32_t au32[2];
939 /** 16-bit view. */
940 uint16_t au16[4];
941 /** 8-bit view. */
942 uint8_t au8[8];
943} X86PTEPAE;
944/** Pointer to a PAE page table entry. */
945typedef X86PTEPAE *PX86PTEPAE;
946/** Pointer to a const PAE page table entry. */
947typedef const X86PTEPAE *PCX86PTEPAE;
948/** @} */
949
950/**
951 * Page table.
952 */
953typedef struct X86PT
954{
955 /** PTE Array. */
956 X86PTE a[X86_PG_ENTRIES];
957} X86PT;
958/** Pointer to a page table. */
959typedef X86PT *PX86PT;
960/** Pointer to a const page table. */
961typedef const X86PT *PCX86PT;
962
963/** The page shift to get the PT index. */
964#define X86_PT_SHIFT 12
965/** The PT index mask (apply to a shifted page address). */
966#define X86_PT_MASK 0x3ff
967
968
969/**
970 * Page directory.
971 */
972typedef struct X86PTPAE
973{
974 /** PTE Array. */
975 X86PTEPAE a[X86_PG_PAE_ENTRIES];
976} X86PTPAE;
977/** Pointer to a page table. */
978typedef X86PTPAE *PX86PTPAE;
979/** Pointer to a const page table. */
980typedef const X86PTPAE *PCX86PTPAE;
981
982/** The page shift to get the PA PTE index. */
983#define X86_PT_PAE_SHIFT 12
984/** The PAE PT index mask (apply to a shifted page address). */
985#define X86_PT_PAE_MASK 0x1ff
986
987
988/** @name 4KB Page Directory Entry
989 * @{
990 */
991/** Bit 0 - P - Present bit. */
992#define X86_PDE_P BIT(0)
993/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
994#define X86_PDE_RW BIT(1)
995/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
996#define X86_PDE_US BIT(2)
997/** Bit 3 - PWT - Page level write thru bit. */
998#define X86_PDE_PWT BIT(3)
999/** Bit 4 - PCD - Page level cache disable bit. */
1000#define X86_PDE_PCD BIT(4)
1001/** Bit 5 - A - Access bit. */
1002#define X86_PDE_A BIT(5)
1003/** Bit 7 - PS - Page size attribute.
1004 * Clear mean 4KB pages, set means large pages (2/4MB). */
1005#define X86_PDE_PS BIT(7)
1006/** Bits 9-11 - - Available for use to system software. */
1007#define X86_PDE_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
1008/** Bits 12-31 - - Physical Page number of the next level. */
1009#define X86_PDE_PG_MASK ( 0xfffff000 )
1010
1011/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1012#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1013#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1014#else
1015#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1016#endif
1017/** Bits 63 - NX - PAE - No execution flag. */
1018#define X86_PDE_PAE_NX BIT64(63)
1019
1020/**
1021 * Page directory entry.
1022 */
1023typedef struct X86PDEBITS
1024{
1025 /** Flags whether(=1) or not the page is present. */
1026 unsigned u1Present : 1;
1027 /** Read(=0) / Write(=1) flag. */
1028 unsigned u1Write : 1;
1029 /** User(=1) / Supervisor (=0) flag. */
1030 unsigned u1User : 1;
1031 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1032 unsigned u1WriteThru : 1;
1033 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1034 unsigned u1CacheDisable : 1;
1035 /** Accessed flag.
1036 * Indicates that the page have been read or written to. */
1037 unsigned u1Accessed : 1;
1038 /** Reserved / Ignored (dirty bit). */
1039 unsigned u1Reserved0 : 1;
1040 /** Size bit if PSE is enabled - in any event it's 0. */
1041 unsigned u1Size : 1;
1042 /** Reserved / Ignored (global bit). */
1043 unsigned u1Reserved1 : 1;
1044 /** Available for use to system software. */
1045 unsigned u3Available : 3;
1046 /** Physical Page number of the next level. */
1047 unsigned u20PageNo : 20;
1048} X86PDEBITS;
1049/** Pointer to a page directory entry. */
1050typedef X86PDEBITS *PX86PDEBITS;
1051/** Pointer to a const page directory entry. */
1052typedef const X86PDEBITS *PCX86PDEBITS;
1053
1054
1055/**
1056 * PAE page directory entry.
1057 */
1058typedef struct X86PDEPAEBITS
1059{
1060 /** Flags whether(=1) or not the page is present. */
1061 uint32_t u1Present : 1;
1062 /** Read(=0) / Write(=1) flag. */
1063 uint32_t u1Write : 1;
1064 /** User(=1) / Supervisor (=0) flag. */
1065 uint32_t u1User : 1;
1066 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1067 uint32_t u1WriteThru : 1;
1068 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1069 uint32_t u1CacheDisable : 1;
1070 /** Accessed flag.
1071 * Indicates that the page have been read or written to. */
1072 uint32_t u1Accessed : 1;
1073 /** Reserved / Ignored (dirty bit). */
1074 uint32_t u1Reserved0 : 1;
1075 /** Size bit if PSE is enabled - in any event it's 0. */
1076 uint32_t u1Size : 1;
1077 /** Reserved / Ignored (global bit). / */
1078 uint32_t u1Reserved1 : 1;
1079 /** Available for use to system software. */
1080 uint32_t u3Available : 3;
1081 /** Physical Page number of the next level - Low Part. Don't use! */
1082 uint32_t u20PageNoLow : 20;
1083 /** Physical Page number of the next level - High Part. Don't use! */
1084 uint32_t u20PageNoHigh : 20;
1085 /** MBZ bits */
1086 uint32_t u11Reserved : 11;
1087 /** No Execute flag. */
1088 uint32_t u1NoExecute : 1;
1089} X86PDEPAEBITS;
1090/** Pointer to a page directory entry. */
1091typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1092/** Pointer to a const page directory entry. */
1093typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1094
1095/** @} */
1096
1097
1098/** @name 2/4MB Page Directory Entry
1099 * @{
1100 */
1101/** Bit 0 - P - Present bit. */
1102#define X86_PDE4M_P BIT(0)
1103/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1104#define X86_PDE4M_RW BIT(1)
1105/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1106#define X86_PDE4M_US BIT(2)
1107/** Bit 3 - PWT - Page level write thru bit. */
1108#define X86_PDE4M_PWT BIT(3)
1109/** Bit 4 - PCD - Page level cache disable bit. */
1110#define X86_PDE4M_PCD BIT(4)
1111/** Bit 5 - A - Access bit. */
1112#define X86_PDE4M_A BIT(5)
1113/** Bit 6 - D - Dirty bit. */
1114#define X86_PDE4M_D BIT(6)
1115/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1116#define X86_PDE4M_PS BIT(7)
1117/** Bit 8 - G - Global flag. */
1118#define X86_PDE4M_G BIT(8)
1119/** Bits 9-11 - AVL - Available for use to system software. */
1120#define X86_PDE4M_AVL (BIT(9) | BIT(10) | BIT(11))
1121/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1122#define X86_PDE4M_PAT BIT(12)
1123/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1124#define X86_PDE4M_PAT_SHIFT (12 - 7)
1125/** Bits 22-31 - - Physical Page number. */
1126#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1127/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1128#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1129/** The number of bits to the high part of the page number. */
1130#define X86_PDE4M_PG_HIGH_SHIFT 19
1131
1132/** Bits 12-51 - - PAE - Physical Page number. */
1133#define X86_PDE4M_PAE_PG_MASK ( 0x000fffffffc00000ULL )
1134/** Bits 63 - NX - PAE - No execution flag. */
1135#define X86_PDE4M_PAE_NX BIT64(63)
1136
1137/**
1138 * 4MB page directory entry.
1139 */
1140typedef struct X86PDE4MBITS
1141{
1142 /** Flags whether(=1) or not the page is present. */
1143 unsigned u1Present : 1;
1144 /** Read(=0) / Write(=1) flag. */
1145 unsigned u1Write : 1;
1146 /** User(=1) / Supervisor (=0) flag. */
1147 unsigned u1User : 1;
1148 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1149 unsigned u1WriteThru : 1;
1150 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1151 unsigned u1CacheDisable : 1;
1152 /** Accessed flag.
1153 * Indicates that the page have been read or written to. */
1154 unsigned u1Accessed : 1;
1155 /** Dirty flag.
1156 * Indicates that the page have been written to. */
1157 unsigned u1Dirty : 1;
1158 /** Page size flag - always 1 for 4MB entries. */
1159 unsigned u1Size : 1;
1160 /** Global flag. */
1161 unsigned u1Global : 1;
1162 /** Available for use to system software. */
1163 unsigned u3Available : 3;
1164 /** Reserved / If PAT enabled, bit 2 of the index. */
1165 unsigned u1PAT : 1;
1166 /** Bits 32-39 of the page number on AMD64.
1167 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1168 unsigned u8PageNoHigh : 8;
1169 /** Reserved. */
1170 unsigned u1Reserved : 1;
1171 /** Physical Page number of the page. */
1172 unsigned u10PageNo : 10;
1173} X86PDE4MBITS;
1174/** Pointer to a page table entry. */
1175typedef X86PDE4MBITS *PX86PDE4MBITS;
1176/** Pointer to a const page table entry. */
1177typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1178
1179
1180/**
1181 * 2MB PAE page directory entry.
1182 */
1183typedef struct X86PDE2MPAEBITS
1184{
1185 /** Flags whether(=1) or not the page is present. */
1186 uint32_t u1Present : 1;
1187 /** Read(=0) / Write(=1) flag. */
1188 uint32_t u1Write : 1;
1189 /** User(=1) / Supervisor(=0) flag. */
1190 uint32_t u1User : 1;
1191 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1192 uint32_t u1WriteThru : 1;
1193 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1194 uint32_t u1CacheDisable : 1;
1195 /** Accessed flag.
1196 * Indicates that the page have been read or written to. */
1197 uint32_t u1Accessed : 1;
1198 /** Dirty flag.
1199 * Indicates that the page have been written to. */
1200 uint32_t u1Dirty : 1;
1201 /** Page size flag - always 1 for 2MB entries. */
1202 uint32_t u1Size : 1;
1203 /** Global flag. */
1204 uint32_t u1Global : 1;
1205 /** Available for use to system software. */
1206 uint32_t u3Available : 3;
1207 /** Reserved / If PAT enabled, bit 2 of the index. */
1208 uint32_t u1PAT : 1;
1209 /** Reserved. */
1210 uint32_t u9Reserved : 9;
1211 /** Physical Page number of the next level - Low part. Don't use! */
1212 uint32_t u10PageNoLow : 10;
1213 /** Physical Page number of the next level - High part. Don't use! */
1214 uint32_t u20PageNoHigh : 20;
1215 /** MBZ bits */
1216 uint32_t u11Reserved : 11;
1217 /** No Execute flag. */
1218 uint32_t u1NoExecute : 1;
1219} X86PDE2MPAEBITS;
1220/** Pointer to a 4MB PAE page table entry. */
1221typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1222/** Pointer to a 4MB PAE page table entry. */
1223typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1224
1225/** @} */
1226
1227/**
1228 * Page directory entry.
1229 */
1230typedef union X86PDE
1231{
1232 /** Normal view. */
1233 X86PDEBITS n;
1234 /** 4MB view (big). */
1235 X86PDE4MBITS b;
1236 /** Unsigned integer view. */
1237 X86PGUINT u;
1238 /** 8 bit unsigned integer view. */
1239 uint8_t au8[4];
1240 /** 16 bit unsigned integer view. */
1241 uint16_t au16[2];
1242 /** 32 bit unsigned integer view. */
1243 uint32_t au32[1];
1244} X86PDE;
1245/** Pointer to a page directory entry. */
1246typedef X86PDE *PX86PDE;
1247/** Pointer to a const page directory entry. */
1248typedef const X86PDE *PCX86PDE;
1249
1250/**
1251 * PAE page directory entry.
1252 */
1253typedef union X86PDEPAE
1254{
1255 /** Normal view. */
1256 X86PDEPAEBITS n;
1257 /** 2MB page view (big). */
1258 X86PDE2MPAEBITS b;
1259 /** Unsigned integer view. */
1260 X86PGPAEUINT u;
1261 /** 8 bit unsigned integer view. */
1262 uint8_t au8[8];
1263 /** 16 bit unsigned integer view. */
1264 uint16_t au16[4];
1265 /** 32 bit unsigned integer view. */
1266 uint32_t au32[2];
1267} X86PDEPAE;
1268/** Pointer to a page directory entry. */
1269typedef X86PDEPAE *PX86PDEPAE;
1270/** Pointer to a const page directory entry. */
1271typedef const X86PDEPAE *PCX86PDEPAE;
1272
1273/**
1274 * Page directory.
1275 */
1276typedef struct X86PD
1277{
1278 /** PDE Array. */
1279 X86PDE a[X86_PG_ENTRIES];
1280} X86PD;
1281/** Pointer to a page directory. */
1282typedef X86PD *PX86PD;
1283/** Pointer to a const page directory. */
1284typedef const X86PD *PCX86PD;
1285
1286/** The page shift to get the PD index. */
1287#define X86_PD_SHIFT 22
1288/** The PD index mask (apply to a shifted page address). */
1289#define X86_PD_MASK 0x3ff
1290
1291
1292/**
1293 * PAE page directory.
1294 */
1295typedef struct X86PDPAE
1296{
1297 /** PDE Array. */
1298 X86PDEPAE a[X86_PG_PAE_ENTRIES];
1299} X86PDPAE;
1300/** Pointer to a PAE page directory. */
1301typedef X86PDPAE *PX86PDPAE;
1302/** Pointer to a const PAE page directory. */
1303typedef const X86PDPAE *PCX86PDPAE;
1304
1305/** The page shift to get the PAE PD index. */
1306#define X86_PD_PAE_SHIFT 21
1307/** The PAE PD index mask (apply to a shifted page address). */
1308#define X86_PD_PAE_MASK 0x1ff
1309
1310
1311/** @name Page Directory Pointer Table Entry (PAE)
1312 * @{
1313 */
1314/** Bit 0 - P - Present bit. */
1315#define X86_PDPE_P BIT(0)
1316/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1317#define X86_PDPE_RW BIT(1)
1318/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1319#define X86_PDPE_US BIT(2)
1320/** Bit 3 - PWT - Page level write thru bit. */
1321#define X86_PDPE_PWT BIT(3)
1322/** Bit 4 - PCD - Page level cache disable bit. */
1323#define X86_PDPE_PCD BIT(4)
1324/** Bit 5 - A - Access bit. Long Mode only. */
1325#define X86_PDPE_A BIT(5)
1326/** Bits 9-11 - - Available for use to system software. */
1327#define X86_PDPE_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
1328/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1329#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1330#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1331#else
1332#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1333#endif
1334/** Bits 63 - NX - PAE - No execution flag. */
1335#define X86_PDPE_NX BIT64(63)
1336
1337/**
1338 * Page directory pointer table entry.
1339 */
1340typedef struct X86PDPEBITS
1341{
1342 /** Flags whether(=1) or not the page is present. */
1343 uint32_t u1Present : 1;
1344 /** Read(=0) / Write(=1) flag. */
1345 uint32_t u1Write : 1;
1346 /** User(=1) / Supervisor (=0) flag. */
1347 uint32_t u1User : 1;
1348 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1349 uint32_t u1WriteThru : 1;
1350 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1351 uint32_t u1CacheDisable : 1;
1352 /** Accessed flag.
1353 * Indicates that the page have been read or written to. */
1354 uint32_t u1Accessed : 1;
1355 /** Chunk of reserved bits. */
1356 uint32_t u3Reserved : 3;
1357 /** Available for use to system software. */
1358 uint32_t u3Available : 3;
1359 /** Physical Page number of the next level - Low Part. Don't use! */
1360 uint32_t u20PageNoLow : 20;
1361 /** Physical Page number of the next level - High Part. Don't use! */
1362 uint32_t u20PageNoHigh : 20;
1363 /** MBZ bits */
1364 uint32_t u11Reserved : 11;
1365 /** No Execute flag. */
1366 uint32_t u1NoExecute : 1;
1367} X86PDPEBITS;
1368/** Pointer to a page directory pointer table entry. */
1369typedef X86PDPEBITS *PX86PTPEBITS;
1370/** Pointer to a const page directory pointer table entry. */
1371typedef const X86PDPEBITS *PCX86PTPEBITS;
1372
1373/**
1374 * Page directory pointer table entry.
1375 */
1376typedef union X86PDPE
1377{
1378 /** Normal view. */
1379 X86PDPEBITS n;
1380 /** Unsigned integer view. */
1381 X86PGPAEUINT u;
1382 /** 8 bit unsigned integer view. */
1383 uint8_t au8[8];
1384 /** 16 bit unsigned integer view. */
1385 uint16_t au16[4];
1386 /** 32 bit unsigned integer view. */
1387 uint32_t au32[2];
1388} X86PDPE;
1389/** Pointer to a page directory pointer table entry. */
1390typedef X86PDPE *PX86PDPE;
1391/** Pointer to a const page directory pointer table entry. */
1392typedef const X86PDPE *PCX86PDPE;
1393
1394
1395/**
1396 * Page directory pointer table.
1397 */
1398typedef struct X86PDPTR
1399{
1400 /** PDE Array. */
1401 X86PDPE a[X86_PG_PAE_ENTRIES];
1402} X86PDPTR;
1403/** Pointer to a page directory pointer table. */
1404typedef X86PDPTR *PX86PDPTR;
1405/** Pointer to a const page directory pointer table. */
1406typedef const X86PDPTR *PCX86PDPTR;
1407
1408/** The page shift to get the PDPTR index. */
1409#define X86_PDPTR_SHIFT 30
1410/** The PDPTR index mask (apply to a shifted page address). (32 bits PAE) */
1411#define X86_PDPTR_MASK_32 0x3
1412/** The PDPTR index mask (apply to a shifted page address). (64 bits PAE)*/
1413#define X86_PDPTR_MASK 0x1ff
1414
1415/** @} */
1416
1417
1418/** @name Page Map Level-4 Entry (Long Mode PAE)
1419 * @{
1420 */
1421/** Bit 0 - P - Present bit. */
1422#define X86_PML4E_P BIT(0)
1423/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1424#define X86_PML4E_RW BIT(1)
1425/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1426#define X86_PML4E_US BIT(2)
1427/** Bit 3 - PWT - Page level write thru bit. */
1428#define X86_PML4E_PWT BIT(3)
1429/** Bit 4 - PCD - Page level cache disable bit. */
1430#define X86_PML4E_PCD BIT(4)
1431/** Bit 5 - A - Access bit. */
1432#define X86_PML4E_A BIT(5)
1433/** Bits 9-11 - - Available for use to system software. */
1434#define X86_PML4E_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
1435/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1436#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1437#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1438#else
1439#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1440#endif
1441/** Bits 63 - NX - PAE - No execution flag. */
1442#define X86_PML4E_NX BIT64(63)
1443
1444/**
1445 * Page Map Level-4 Entry
1446 */
1447typedef struct X86PML4EBITS
1448{
1449 /** Flags whether(=1) or not the page is present. */
1450 uint32_t u1Present : 1;
1451 /** Read(=0) / Write(=1) flag. */
1452 uint32_t u1Write : 1;
1453 /** User(=1) / Supervisor (=0) flag. */
1454 uint32_t u1User : 1;
1455 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1456 uint32_t u1WriteThru : 1;
1457 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1458 uint32_t u1CacheDisable : 1;
1459 /** Accessed flag.
1460 * Indicates that the page have been read or written to. */
1461 uint32_t u1Accessed : 1;
1462 /** Chunk of reserved bits. */
1463 uint32_t u3Reserved : 3;
1464 /** Available for use to system software. */
1465 uint32_t u3Available : 3;
1466 /** Physical Page number of the next level - Low Part. Don't use! */
1467 uint32_t u20PageNoLow : 20;
1468 /** Physical Page number of the next level - High Part. Don't use! */
1469 uint32_t u20PageNoHigh : 20;
1470 /** MBZ bits */
1471 uint32_t u11Reserved : 11;
1472 /** No Execute flag. */
1473 uint32_t u1NoExecute : 1;
1474} X86PML4EBITS;
1475/** Pointer to a page map level-4 entry. */
1476typedef X86PML4EBITS *PX86PML4EBITS;
1477/** Pointer to a const page map level-4 entry. */
1478typedef const X86PML4EBITS *PCX86PML4EBITS;
1479
1480/**
1481 * Page Map Level-4 Entry.
1482 */
1483typedef union X86PML4E
1484{
1485 /** Normal view. */
1486 X86PML4EBITS n;
1487 /** Unsigned integer view. */
1488 X86PGPAEUINT u;
1489 /** 8 bit unsigned integer view. */
1490 uint8_t au8[8];
1491 /** 16 bit unsigned integer view. */
1492 uint16_t au16[4];
1493 /** 32 bit unsigned integer view. */
1494 uint32_t au32[2];
1495} X86PML4E;
1496/** Pointer to a page map level-4 entry. */
1497typedef X86PML4E *PX86PML4E;
1498/** Pointer to a const page map level-4 entry. */
1499typedef const X86PML4E *PCX86PML4E;
1500
1501
1502/**
1503 * Page Map Level-4.
1504 */
1505typedef struct X86PML4
1506{
1507 /** PDE Array. */
1508 X86PML4E a[X86_PG_PAE_ENTRIES];
1509} X86PML4;
1510/** Pointer to a page map level-4. */
1511typedef X86PML4 *PX86PML4;
1512/** Pointer to a const page map level-4. */
1513typedef const X86PML4 *PCX86PML4;
1514
1515/** The page shift to get the PML4 index. */
1516#define X86_PML4_SHIFT 39
1517/** The PML4 index mask (apply to a shifted page address). */
1518#define X86_PML4_MASK 0x1ff
1519
1520/** @} */
1521
1522/** @} */
1523
1524
1525/**
1526 * 80-bit MMX/FPU register type.
1527 */
1528typedef struct X86FPUMMX
1529{
1530 uint8_t reg[10];
1531} X86FPUMMX;
1532/** Pointer to a 80-bit MMX/FPU register type. */
1533typedef X86FPUMMX *PX86FPUMMX;
1534/** Pointer to a const 80-bit MMX/FPU register type. */
1535typedef const X86FPUMMX *PCX86FPUMMX;
1536
1537/**
1538 * FPU state (aka FSAVE/FRSTOR Memory Region).
1539 */
1540#pragma pack(1)
1541typedef struct X86FPUSTATE
1542{
1543 /** Control word. */
1544 uint16_t FCW;
1545 /** Alignment word */
1546 uint16_t Dummy1;
1547 /** Status word. */
1548 uint16_t FSW;
1549 /** Alignment word */
1550 uint16_t Dummy2;
1551 /** Tag word */
1552 uint16_t FTW;
1553 /** Alignment word */
1554 uint16_t Dummy3;
1555
1556 /** Instruction pointer. */
1557 uint32_t FPUIP;
1558 /** Code selector. */
1559 uint16_t CS;
1560 /** Opcode. */
1561 uint16_t FOP;
1562 /** FOO. */
1563 uint32_t FPUOO;
1564 /** FOS. */
1565 uint32_t FPUOS;
1566 /** FPU view - todo. */
1567 X86FPUMMX regs[8];
1568} X86FPUSTATE;
1569#pragma pack()
1570/** Pointer to a FPU state. */
1571typedef X86FPUSTATE *PX86FPUSTATE;
1572/** Pointer to a const FPU state. */
1573typedef const X86FPUSTATE *PCX86FPUSTATE;
1574
1575/**
1576 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1577 */
1578#pragma pack(1)
1579typedef struct X86FXSTATE
1580{
1581 /** Control word. */
1582 uint16_t FCW;
1583 /** Status word. */
1584 uint16_t FSW;
1585 /** Tag word (it's a byte actually). */
1586 uint8_t FTW;
1587 uint8_t huh1;
1588 /** Opcode. */
1589 uint16_t FOP;
1590 /** Instruction pointer. */
1591 uint32_t FPUIP;
1592 /** Code selector. */
1593 uint16_t CS;
1594 uint16_t Rsvrd1;
1595 /* - offset 16 - */
1596 /** Data pointer. */
1597 uint32_t FPUDP;
1598 /** Data segment */
1599 uint16_t DS;
1600 uint16_t Rsrvd2;
1601 uint32_t MXCSR;
1602 uint32_t MXCSR_MASK;
1603 /* - offset 32 - */
1604 union
1605 {
1606 /** MMX view. */
1607 uint64_t mmx;
1608 /** FPU view - todo. */
1609 X86FPUMMX fpu;
1610 /** 8-bit view. */
1611 uint8_t au8[16];
1612 /** 16-bit view. */
1613 uint16_t au16[8];
1614 /** 32-bit view. */
1615 uint32_t au32[4];
1616 /** 64-bit view. */
1617 uint64_t au64[2];
1618 /** 128-bit view. (yeah, very helpful) */
1619 uint128_t au128[1];
1620 } aRegs[8];
1621 /* - offset 160 - */
1622 union
1623 {
1624 /** XMM Register view *. */
1625 uint128_t xmm;
1626 /** 8-bit view. */
1627 uint8_t au8[16];
1628 /** 16-bit view. */
1629 uint16_t au16[8];
1630 /** 32-bit view. */
1631 uint32_t au32[4];
1632 /** 64-bit view. */
1633 uint64_t au64[2];
1634 /** 128-bit view. (yeah, very helpful) */
1635 uint128_t au128[1];
1636 } aXMM[8];
1637 /* - offset 288 - */
1638 uint32_t au32RsrvdRest[(512 - 288) / sizeof(uint32_t)];
1639} X86FXSTATE;
1640#pragma pack()
1641/** Pointer to a FPU Extended state. */
1642typedef X86FXSTATE *PX86FXSTATE;
1643/** Pointer to a const FPU Extended state. */
1644typedef const X86FXSTATE *PCX86FXSTATE;
1645
1646
1647/** @name Selector Descriptor
1648 * @{
1649 */
1650
1651/**
1652 * Generic descriptor table entry
1653 */
1654#pragma pack(1)
1655typedef struct X86DESCGENERIC
1656{
1657 /** Limit - Low word. */
1658 unsigned u16LimitLow : 16;
1659 /** Base address - lowe word.
1660 * Don't try set this to 24 because MSC is doing studing things then. */
1661 unsigned u16BaseLow : 16;
1662 /** Base address - first 8 bits of high word. */
1663 unsigned u8BaseHigh1 : 8;
1664 /** Segment Type. */
1665 unsigned u4Type : 4;
1666 /** Descriptor Type. System(=0) or code/data selector */
1667 unsigned u1DescType : 1;
1668 /** Descriptor Privelege level. */
1669 unsigned u2Dpl : 2;
1670 /** Flags selector present(=1) or not. */
1671 unsigned u1Present : 1;
1672 /** Segment limit 16-19. */
1673 unsigned u4LimitHigh : 4;
1674 /** Available for system software. */
1675 unsigned u1Available : 1;
1676 /** Reserved - 0. */
1677 unsigned u1Reserved : 1;
1678 /** This flags meaning depends on the segment type. Try make sense out
1679 * of the intel manual yourself. */
1680 unsigned u1DefBig : 1;
1681 /** Granularity of the limit. If set 4KB granularity is used, if
1682 * clear byte. */
1683 unsigned u1Granularity : 1;
1684 /** Base address - highest 8 bits. */
1685 unsigned u8BaseHigh2 : 8;
1686} X86DESCGENERIC;
1687#pragma pack()
1688/** Pointer to a generic descriptor entry. */
1689typedef X86DESCGENERIC *PX86DESCGENERIC;
1690/** Pointer to a const generic descriptor entry. */
1691typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1692
1693
1694/**
1695 * Descriptor attributes.
1696 */
1697typedef struct X86DESCATTRBITS
1698{
1699 /** Segment Type. */
1700 unsigned u4Type : 4;
1701 /** Descriptor Type. System(=0) or code/data selector */
1702 unsigned u1DescType : 1;
1703 /** Descriptor Privelege level. */
1704 unsigned u2Dpl : 2;
1705 /** Flags selector present(=1) or not. */
1706 unsigned u1Present : 1;
1707 /** Segment limit 16-19. */
1708 unsigned u4LimitHigh : 4;
1709 /** Available for system software. */
1710 unsigned u1Available : 1;
1711 /** Reserved - 0. */
1712 unsigned u1Reserved : 1;
1713 /** This flags meaning depends on the segment type. Try make sense out
1714 * of the intel manual yourself. */
1715 unsigned u1DefBig : 1;
1716 /** Granularity of the limit. If set 4KB granularity is used, if
1717 * clear byte. */
1718 unsigned u1Granularity : 1;
1719} X86DESCATTRBITS;
1720
1721
1722#pragma pack(1)
1723typedef union X86DESCATTR
1724{
1725 /** Normal view. */
1726 X86DESCATTRBITS n;
1727 /** Unsigned integer view. */
1728 uint32_t u;
1729} X86DESCATTR;
1730#pragma pack()
1731
1732/** Pointer to descriptor attributes. */
1733typedef X86DESCATTR *PX86DESCATTR;
1734/** Pointer to const descriptor attributes. */
1735typedef const X86DESCATTR *PCX86DESCATTR;
1736
1737
1738/**
1739 * Descriptor table entry.
1740 */
1741#pragma pack(1)
1742typedef union X86DESC
1743{
1744 /** Generic descriptor view. */
1745 X86DESCGENERIC Gen;
1746#if 0
1747 /** IDT view. */
1748 VBOXIDTE Idt;
1749#endif
1750
1751 /** 8 bit unsigned interger view. */
1752 uint8_t au8[8];
1753 /** 16 bit unsigned interger view. */
1754 uint16_t au16[4];
1755 /** 32 bit unsigned interger view. */
1756 uint32_t au32[2];
1757} X86DESC;
1758#pragma pack()
1759/** Pointer to descriptor table entry. */
1760typedef X86DESC *PX86DESC;
1761/** Pointer to const descriptor table entry. */
1762typedef const X86DESC *PCX86DESC;
1763
1764
1765/** @name Selector Descriptor Types.
1766 * @{
1767 */
1768
1769/** @name Non-System Selector Types.
1770 * @{ */
1771/** Code(=set)/Data(=clear) bit. */
1772#define X86_SEL_TYPE_CODE 8
1773/** Accessed bit. */
1774#define X86_SEL_TYPE_ACCESSED 1
1775/** Expand down bit (for data selectors only). */
1776#define X86_SEL_TYPE_DOWN 4
1777/** Conforming bit (for code selectors only). */
1778#define X86_SEL_TYPE_CONF 4
1779/** Write bit (for data selectors only). */
1780#define X86_SEL_TYPE_WRITE 2
1781/** Read bit (for code selectors only). */
1782#define X86_SEL_TYPE_READ 2
1783
1784/** Read only selector type. */
1785#define X86_SEL_TYPE_RO 0
1786/** Accessed read only selector type. */
1787#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
1788/** Read write selector type. */
1789#define X86_SEL_TYPE_RW 2
1790/** Accessed read write selector type. */
1791#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
1792/** Expand down read only selector type. */
1793#define X86_SEL_TYPE_RO_DOWN 4
1794/** Accessed expand down read only selector type. */
1795#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
1796/** Expand down read write selector type. */
1797#define X86_SEL_TYPE_RW_DOWN 6
1798/** Accessed expand down read write selector type. */
1799#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
1800/** Execute only selector type. */
1801#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
1802/** Accessed execute only selector type. */
1803#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1804/** Execute and read selector type. */
1805#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
1806/** Accessed execute and read selector type. */
1807#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1808/** Conforming execute only selector type. */
1809#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
1810/** Accessed Conforming execute only selector type. */
1811#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1812/** Conforming execute and write selector type. */
1813#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
1814/** Accessed Conforming execute and write selector type. */
1815#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1816/** @} */
1817
1818
1819/** @name System Selector Types.
1820 * @{ */
1821/** Undefined system selector type. */
1822#define X86_SEL_TYPE_SYS_UNDEFINED 0
1823/** 286 TSS selector. */
1824#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
1825/** LDT selector. */
1826#define X86_SEL_TYPE_SYS_LDT 2
1827/** 286 TSS selector - Busy. */
1828#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
1829/** 286 Callgate selector. */
1830#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
1831/** Taskgate selector. */
1832#define X86_SEL_TYPE_SYS_TASK_GATE 5
1833/** 286 Interrupt gate selector. */
1834#define X86_SEL_TYPE_SYS_286_INT_GATE 6
1835/** 286 Trapgate selector. */
1836#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
1837/** Undefined system selector. */
1838#define X86_SEL_TYPE_SYS_UNDEFINED2 8
1839/** 386 TSS selector. */
1840#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
1841/** Undefined system selector. */
1842#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
1843/** 386 TSS selector - Busy. */
1844#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
1845/** 386 Callgate selector. */
1846#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
1847/** Undefined system selector. */
1848#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
1849/** 386 Interruptgate selector. */
1850#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
1851/** 386 Trapgate selector. */
1852#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
1853/** @} */
1854
1855/** @} */
1856
1857
1858/** @name Descriptor Table Entry Flag Masks.
1859 * These are for the 2nd 32-bit word of a descriptor.
1860 * @{ */
1861/** Bits 8-11 - TYPE - Descriptor type mask. */
1862#define X86_DESC_TYPE_MASK (BIT(8) | BIT(9) | BIT(10) | BIT(11))
1863/** Bit 12 - S - System (=0) or Code/Data (=1). */
1864#define X86_DESC_S BIT(12)
1865/** Bits 13-14 - DPL - Descriptor Privilege Level. */
1866#define X86_DESC_DPL (BIT(13) | BIT(14))
1867/** Bit 15 - P - Present. */
1868#define X86_DESC_P BIT(15)
1869/** Bit 20 - AVL - Available for system software. */
1870#define X86_DESC_AVL BIT(20)
1871/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
1872#define X86_DESC_DB BIT(22)
1873/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
1874 * used, if clear byte. */
1875#define X86_DESC_G BIT(23)
1876/** @} */
1877
1878/** @} */
1879
1880
1881/** @name Selectors.
1882 * @{
1883 */
1884
1885/**
1886 * The shift used to convert a selector from and to index an index (C).
1887 */
1888#define X86_SEL_SHIFT 3
1889
1890/**
1891 * The mask used to mask off the table indicator and CPL of an selector.
1892 */
1893#define X86_SEL_MASK 0xfff8
1894
1895/**
1896 * The bit indicating that a selector is in the LDT and not in the GDT.
1897 */
1898#define X86_SEL_LDT 0x0004
1899/**
1900 * The bit mask for getting the RPL of a selector.
1901 */
1902#define X86_SEL_RPL 0x0003
1903
1904/** @} */
1905
1906
1907/**
1908 * x86 Exceptions/Faults/Traps.
1909 */
1910typedef enum X86XCPT
1911{
1912 /** \#DE - Divide error. */
1913 X86_XCPT_DE = 0x00,
1914 /** \#DB - Debug event (single step, DRx, ..) */
1915 X86_XCPT_DB = 0x01,
1916 /** NMI - Non-Maskable Interrupt */
1917 X86_XCPT_NMI = 0x02,
1918 /** \#BP - Breakpoint (INT3). */
1919 X86_XCPT_BP = 0x03,
1920 /** \#OF - Overflow (INTO). */
1921 X86_XCPT_OF = 0x04,
1922 /** \#BR - Bound range exceeded (BOUND). */
1923 X86_XCPT_BR = 0x05,
1924 /** \#UD - Undefined opcode. */
1925 X86_XCPT_UD = 0x06,
1926 /** \#NM - Device not available (math coprocessor device). */
1927 X86_XCPT_NM = 0x07,
1928 /** \#DF - Double fault. */
1929 X86_XCPT_DF = 0x08,
1930 /** ??? - Coprocessor segment overrun (obsolete). */
1931 X86_XCPT_CO_SEG_OVERRUN = 0x09,
1932 /** \#TS - Taskswitch (TSS). */
1933 X86_XCPT_TS = 0x0a,
1934 /** \#NP - Segment no present. */
1935 X86_XCPT_NP = 0x0b,
1936 /** \#SS - Stack segment fault. */
1937 X86_XCPT_SS = 0x0c,
1938 /** \#GP - General protection fault. */
1939 X86_XCPT_GP = 0x0d,
1940 /** \#PF - Page fault. */
1941 X86_XCPT_PF = 0x0e,
1942 /* 0x0f is reserved. */
1943 /** \#MF - Math fault (FPU). */
1944 X86_XCPT_MF = 0x10,
1945 /** \#AC - Alignment check. */
1946 X86_XCPT_AC = 0x11,
1947 /** \#MC - Machine check. */
1948 X86_XCPT_MC = 0x12,
1949 /** \#XF - SIMD Floating-Pointer Exception. */
1950 X86_XCPT_XF = 0x13
1951} X86XCPT;
1952/** Pointer to a x86 exception code. */
1953typedef X86XCPT *PX86XCPT;
1954/** Pointer to a const x86 exception code. */
1955typedef const X86XCPT *PCX86XCPT;
1956
1957
1958/** @name Trap Error Codes
1959 * @{
1960 */
1961/** External indicator. */
1962#define X86_TRAP_ERR_EXTERNAL 1
1963/** IDT indicator. */
1964#define X86_TRAP_ERR_IDT 2
1965/** Descriptor table indicator - If set LDT, if clear GDT. */
1966#define X86_TRAP_ERR_TI 4
1967/** Mask for getting the selector. */
1968#define X86_TRAP_ERR_SEL_MASK 0xfff8
1969/** Shift for getting the selector table index (C type index). */
1970#define X86_TRAP_ERR_SEL_SHIFT 3
1971/** @} */
1972
1973
1974/** @name \#PF Trap Error Codes
1975 * @{
1976 */
1977/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
1978#define X86_TRAP_PF_P BIT(0)
1979/** Bit 1 - R/W - Read (clear) or write (set) access. */
1980#define X86_TRAP_PF_RW BIT(1)
1981/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
1982#define X86_TRAP_PF_US BIT(2)
1983/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
1984#define X86_TRAP_PF_RSVD BIT(3)
1985/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
1986#define X86_TRAP_PF_ID BIT(4)
1987/** @} */
1988
1989
1990
1991/** @} */
1992
1993#endif
1994
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