VirtualBox

source: vbox/trunk/include/VBox/x86.mac@ 17676

Last change on this file since 17676 was 13702, checked in by vboxsync, 16 years ago

VMM++: new EM status code VINF_EM_DBG_RING0_ASSERTION for distinguishing ring-0 and hyper assertions. Resynched the .mac files, hacking the x86.h sed transformations in the process.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 23.5 KB
Line 
1%define ___VBox_x86_h
2%define X86_EFL_CF RT_BIT(0)
3%define X86_EFL_PF RT_BIT(2)
4%define X86_EFL_AF RT_BIT(4)
5%define X86_EFL_ZF RT_BIT(6)
6%define X86_EFL_SF RT_BIT(7)
7%define X86_EFL_TF RT_BIT(8)
8%define X86_EFL_IF RT_BIT(9)
9%define X86_EFL_DF RT_BIT(10)
10%define X86_EFL_OF RT_BIT(11)
11%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
12%define X86_EFL_NT RT_BIT(14)
13%define X86_EFL_RF RT_BIT(16)
14%define X86_EFL_VM RT_BIT(17)
15%define X86_EFL_AC RT_BIT(18)
16%define X86_EFL_VIF RT_BIT(19)
17%define X86_EFL_VIP RT_BIT(20)
18%define X86_EFL_ID RT_BIT(21)
19%define X86_EFL_IOPL_SHIFT 12
20%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
21%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
22%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
23%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
24%define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
25%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
26%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
27%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
28%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
29%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
30%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
31%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
32%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
33%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
34%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
35%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
36%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
37%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
38%define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
39%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
40%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
41%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
42%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
43%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
44%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
45%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
46%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
47%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
48%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
49%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
50%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
51%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
52%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
53%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
54%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
55%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
56%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
57%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
58%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
59%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
60%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
61%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
62%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
63%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
64%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
65%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
66%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
67%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
68%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
69%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
70%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
71%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
72%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
73%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
74%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
75%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
76%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
77%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
78%define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
79%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
80%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
81%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
82%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
83%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
84%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
85%define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
86%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
87%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
88%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
89%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
90%define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
91%define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
92%define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
93%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
94%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
95%define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
96%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
97%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
98%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
99%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
100%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
101%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
102%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
103%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
104%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
105%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
106%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
107%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
108%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
109%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
110%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
111%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
112%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
113%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
114%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
115%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
116%define X86_CR0_PE RT_BIT(0)
117%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
118%define X86_CR0_MP RT_BIT(1)
119%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
120%define X86_CR0_EM RT_BIT(2)
121%define X86_CR0_EMULATE_FPU RT_BIT(2)
122%define X86_CR0_TS RT_BIT(3)
123%define X86_CR0_TASK_SWITCH RT_BIT(3)
124%define X86_CR0_ET RT_BIT(4)
125%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
126%define X86_CR0_NE RT_BIT(5)
127%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
128%define X86_CR0_WP RT_BIT(16)
129%define X86_CR0_WRITE_PROTECT RT_BIT(16)
130%define X86_CR0_AM RT_BIT(18)
131%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
132%define X86_CR0_NW RT_BIT(29)
133%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
134%define X86_CR0_CD RT_BIT(30)
135%define X86_CR0_CACHE_DISABLE RT_BIT(30)
136%define X86_CR0_PG RT_BIT(31)
137%define X86_CR0_PAGING RT_BIT(31)
138%define X86_CR3_PWT RT_BIT(3)
139%define X86_CR3_PCD RT_BIT(4)
140%define X86_CR3_PAGE_MASK (0xfffff000)
141%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
142%define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
143%define X86_CR4_VME RT_BIT(0)
144%define X86_CR4_PVI RT_BIT(1)
145%define X86_CR4_TSD RT_BIT(2)
146%define X86_CR4_DE RT_BIT(3)
147%define X86_CR4_PSE RT_BIT(4)
148%define X86_CR4_PAE RT_BIT(5)
149%define X86_CR4_MCE RT_BIT(6)
150%define X86_CR4_PGE RT_BIT(7)
151%define X86_CR4_PCE RT_BIT(8)
152%define X86_CR4_OSFSXR RT_BIT(9)
153%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
154%define X86_CR4_VMXE RT_BIT(13)
155%define X86_DR6_B0 RT_BIT(0)
156%define X86_DR6_B1 RT_BIT(1)
157%define X86_DR6_B2 RT_BIT(2)
158%define X86_DR6_B3 RT_BIT(3)
159%define X86_DR6_BD RT_BIT(13)
160%define X86_DR6_BS RT_BIT(14)
161%define X86_DR6_BT RT_BIT(15)
162%define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
163%define X86_DR7_L0 RT_BIT(0)
164%define X86_DR7_G0 RT_BIT(1)
165%define X86_DR7_L1 RT_BIT(2)
166%define X86_DR7_G1 RT_BIT(3)
167%define X86_DR7_L2 RT_BIT(4)
168%define X86_DR7_G2 RT_BIT(5)
169%define X86_DR7_L3 RT_BIT(6)
170%define X86_DR7_G3 RT_BIT(7)
171%define X86_DR7_LE RT_BIT(8)
172%define X86_DR7_GE RT_BIT(9)
173%define X86_DR7_GD RT_BIT(13)
174%define X86_DR7_RW0_MASK (3 << 16)
175%define X86_DR7_LEN0_MASK (3 << 18)
176%define X86_DR7_RW1_MASK (3 << 20)
177%define X86_DR7_LEN1_MASK (3 << 22)
178%define X86_DR7_RW2_MASK (3 << 24)
179%define X86_DR7_LEN2_MASK (3 << 26)
180%define X86_DR7_RW3_MASK (3 << 28)
181%define X86_DR7_LEN3_MASK (3 << 30)
182%define X86_DR7_MB1_MASK (RT_BIT(10))
183%define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
184%define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
185%define X86_DR7_RW_EO 0
186%define X86_DR7_RW_WO 1
187%define X86_DR7_RW_IO 2
188%define X86_DR7_RW_RW 3
189%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
190%define X86_DR7_LEN_BYTE 0
191%define X86_DR7_LEN_WORD 1
192%define X86_DR7_LEN_QWORD 2
193%define X86_DR7_LEN_DWORD 3
194%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
195%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
196%define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
197%define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
198%define X86_DR7_INIT_VAL 0x400
199%define MSR_IA32_TSC 0x10
200%define MSR_IA32_PLATFORM_ID 0x17
201%define MSR_IA32_APICBASE 0x1b
202%define MSR_IA32_FEATURE_CONTROL 0x3A
203%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
204%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
205%define MSR_IA32_BIOS_UPDT_TRIG 0x79
206%define MSR_IA32_BIOS_SIGN_ID 0x8B
207%define MSR_IA32_MTRR_CAP 0xFE
208%define MSR_IA32_SYSENTER_CS 0x174
209%define MSR_IA32_SYSENTER_ESP 0x175
210%define MSR_IA32_SYSENTER_EIP 0x176
211%define MSR_IA32_MCP_CAP 0x179
212%define MSR_IA32_MCP_STATUS 0x17A
213%define MSR_IA32_MCP_CTRL 0x17B
214%define MSR_IA32_CR_PAT 0x277
215%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
216%define MSR_IA32_MC0_CTL 0x400
217%define MSR_IA32_MC0_STATUS 0x401
218%define MSR_IA32_VMX_BASIC_INFO 0x480
219%define MSR_IA32_VMX_PINBASED_CTLS 0x481
220%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
221%define MSR_IA32_VMX_EXIT_CTLS 0x483
222%define MSR_IA32_VMX_ENTRY_CTLS 0x484
223%define MSR_IA32_VMX_MISC 0x485
224%define MSR_IA32_VMX_CR0_FIXED0 0x486
225%define MSR_IA32_VMX_CR0_FIXED1 0x487
226%define MSR_IA32_VMX_CR4_FIXED0 0x488
227%define MSR_IA32_VMX_CR4_FIXED1 0x489
228%define MSR_IA32_VMX_VMCS_ENUM 0x48A
229%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
230%define MSR_IA32_VMX_EPT_CAPS 0x48C
231%define MSR_IA32_APIC_START 0x800
232%define MSR_IA32_APIC_END 0x900
233%define MSR_K6_EFER 0xc0000080
234%define MSR_K6_EFER_SCE RT_BIT(0)
235%define MSR_K6_EFER_LME RT_BIT(8)
236%define MSR_K6_EFER_LMA RT_BIT(10)
237%define MSR_K6_EFER_NXE RT_BIT(11)
238%define MSR_K6_EFER_SVME RT_BIT(12)
239%define MSR_K6_EFER_LMSLE RT_BIT(13)
240%define MSR_K6_EFER_FFXSR RT_BIT(14)
241%define MSR_K6_STAR 0xc0000081
242%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
243%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
244%define MSR_K6_STAR_SEL_MASK 0xffff
245%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
246%define MSR_K6_WHCR 0xc0000082
247%define MSR_K6_UWCCR 0xc0000085
248%define MSR_K6_PSOR 0xc0000087
249%define MSR_K6_PFIR 0xc0000088
250%define MSR_K7_EVNTSEL0 0xc0010000
251%define MSR_K7_EVNTSEL1 0xc0010001
252%define MSR_K7_EVNTSEL2 0xc0010002
253%define MSR_K7_EVNTSEL3 0xc0010003
254%define MSR_K7_PERFCTR0 0xc0010004
255%define MSR_K7_PERFCTR1 0xc0010005
256%define MSR_K7_PERFCTR2 0xc0010006
257%define MSR_K7_PERFCTR3 0xc0010007
258%define MSR_K8_LSTAR 0xc0000082
259%define MSR_K8_CSTAR 0xc0000083
260%define MSR_K8_SF_MASK 0xc0000084
261%define MSR_K8_FS_BASE 0xc0000100
262%define MSR_K8_GS_BASE 0xc0000101
263%define MSR_K8_KERNEL_GS_BASE 0xc0000102
264%define MSR_K8_TSC_AUX 0xc0000103
265%define MSR_K8_SYSCFG 0xc0010010
266%define MSR_K8_HWCR 0xc0010015
267%define MSR_K8_IORRBASE0 0xc0010016
268%define MSR_K8_IORRMASK0 0xc0010017
269%define MSR_K8_IORRBASE1 0xc0010018
270%define MSR_K8_IORRMASK1 0xc0010019
271%define MSR_K8_TOP_MEM1 0xc001001a
272%define MSR_K8_TOP_MEM2 0xc001001d
273%define MSR_K8_VM_CR 0xc0010114
274%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
275%define MSR_K8_IGNNE 0xc0010115
276%define MSR_K8_SMM_CTL 0xc0010116
277%define MSR_K8_VM_HSAVE_PA 0xc0010117
278%define X86_PG_ENTRIES 1024
279%define X86_PG_PAE_ENTRIES 512
280%define X86_PG_PAE_PDPE_ENTRIES 4
281%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
282%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
283%define X86_PAGE_4K_SIZE _4K
284%define X86_PAGE_4K_SHIFT 12
285%define X86_PAGE_4K_OFFSET_MASK 0xfff
286%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
287%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
288%define X86_PAGE_2M_SIZE _2M
289%define X86_PAGE_2M_SHIFT 21
290%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
291%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
292%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
293%define X86_PAGE_4M_SIZE _4M
294%define X86_PAGE_4M_SHIFT 22
295%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
296%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
297%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
298%define X86_PTE_P RT_BIT(0)
299%define X86_PTE_RW RT_BIT(1)
300%define X86_PTE_US RT_BIT(2)
301%define X86_PTE_PWT RT_BIT(3)
302%define X86_PTE_PCD RT_BIT(4)
303%define X86_PTE_A RT_BIT(5)
304%define X86_PTE_D RT_BIT(6)
305%define X86_PTE_PAT RT_BIT(7)
306%define X86_PTE_G RT_BIT(8)
307%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
308%define X86_PTE_PG_MASK ( 0xfffff000 )
309%define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
310%define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
311%define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
312%define X86_PTE_PAE_NX RT_BIT_64(63)
313%define X86_PT_SHIFT 12
314%define X86_PT_MASK 0x3ff
315%define X86_PT_PAE_SHIFT 12
316%define X86_PT_PAE_MASK 0x1ff
317%define X86_PDE_P RT_BIT(0)
318%define X86_PDE_RW RT_BIT(1)
319%define X86_PDE_US RT_BIT(2)
320%define X86_PDE_PWT RT_BIT(3)
321%define X86_PDE_PCD RT_BIT(4)
322%define X86_PDE_A RT_BIT(5)
323%define X86_PDE_PS RT_BIT(7)
324%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
325%define X86_PDE_PG_MASK ( 0xfffff000 )
326%define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
327%define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
328%define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
329%define X86_PDE_PAE_NX RT_BIT_64(63)
330%define X86_PDE4M_P RT_BIT(0)
331%define X86_PDE4M_RW RT_BIT(1)
332%define X86_PDE4M_US RT_BIT(2)
333%define X86_PDE4M_PWT RT_BIT(3)
334%define X86_PDE4M_PCD RT_BIT(4)
335%define X86_PDE4M_A RT_BIT(5)
336%define X86_PDE4M_D RT_BIT(6)
337%define X86_PDE4M_PS RT_BIT(7)
338%define X86_PDE4M_G RT_BIT(8)
339%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
340%define X86_PDE4M_PAT RT_BIT(12)
341%define X86_PDE4M_PAT_SHIFT (12 - 7)
342%define X86_PDE4M_PG_MASK ( 0xffc00000 )
343%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
344%define X86_PDE4M_PG_HIGH_SHIFT 19
345%define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
346%define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
347%define X86_PD_SHIFT 22
348%define X86_PD_MASK 0x3ff
349%define X86_PD_PAE_SHIFT 21
350%define X86_PD_PAE_MASK 0x1ff
351%define X86_PDPE_P RT_BIT(0)
352%define X86_PDPE_RW RT_BIT(1)
353%define X86_PDPE_US RT_BIT(2)
354%define X86_PDPE_PWT RT_BIT(3)
355%define X86_PDPE_PCD RT_BIT(4)
356%define X86_PDPE_A RT_BIT(5)
357%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
358%define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
359%define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
360%define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
361%define X86_PDPE_NX RT_BIT_64(63)
362%define X86_PDPT_SHIFT 30
363%define X86_PDPT_MASK_PAE 0x3
364%define X86_PDPT_MASK_AMD64 0x1ff
365%define X86_PML4E_P RT_BIT(0)
366%define X86_PML4E_RW RT_BIT(1)
367%define X86_PML4E_US RT_BIT(2)
368%define X86_PML4E_PWT RT_BIT(3)
369%define X86_PML4E_PCD RT_BIT(4)
370%define X86_PML4E_A RT_BIT(5)
371%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
372%define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
373%define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
374%define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
375%define X86_PML4E_NX RT_BIT_64(63)
376%define X86_PML4_SHIFT 39
377%define X86_PML4_MASK 0x1ff
378%define X86_SEL_TYPE_CODE 8
379%define X86_SEL_TYPE_MEMORY RT_BIT(4)
380%define X86_SEL_TYPE_ACCESSED 1
381%define X86_SEL_TYPE_DOWN 4
382%define X86_SEL_TYPE_CONF 4
383%define X86_SEL_TYPE_WRITE 2
384%define X86_SEL_TYPE_READ 2
385%define X86_SEL_TYPE_RO 0
386%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
387%define X86_SEL_TYPE_RW 2
388%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
389%define X86_SEL_TYPE_RO_DOWN 4
390%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
391%define X86_SEL_TYPE_RW_DOWN 6
392%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
393%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
394%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
395%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
396%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
397%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
398%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
399%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
400%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
401%define X86_SEL_TYPE_SYS_UNDEFINED 0
402%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
403%define X86_SEL_TYPE_SYS_LDT 2
404%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
405%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
406%define X86_SEL_TYPE_SYS_TASK_GATE 5
407%define X86_SEL_TYPE_SYS_286_INT_GATE 6
408%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
409%define X86_SEL_TYPE_SYS_UNDEFINED2 8
410%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
411%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
412%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
413%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
414%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
415%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
416%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
417%define AMD64_SEL_TYPE_SYS_LDT 2
418%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
419%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
420%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
421%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
422%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
423%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
424%define X86_DESC_S RT_BIT(12)
425%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
426%define X86_DESC_P RT_BIT(15)
427%define X86_DESC_AVL RT_BIT(20)
428%define X86_DESC_DB RT_BIT(22)
429%define X86_DESC_G RT_BIT(23)
430%define X86_SEL_SHIFT 3
431%define AMD64_SEL_SHIFT 4
432%define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
433%define X86_SEL_SHIFT_HC X86_SEL_SHIFT
434%define X86_SEL_MASK 0xfff8
435%define X86_SEL_LDT 0x0004
436%define X86_SEL_RPL 0x0003
437%define X86_TRAP_ERR_EXTERNAL 1
438%define X86_TRAP_ERR_IDT 2
439%define X86_TRAP_ERR_TI 4
440%define X86_TRAP_ERR_SEL_MASK 0xfff8
441%define X86_TRAP_ERR_SEL_SHIFT 3
442%define X86_TRAP_PF_P RT_BIT(0)
443%define X86_TRAP_PF_RW RT_BIT(1)
444%define X86_TRAP_PF_US RT_BIT(2)
445%define X86_TRAP_PF_RSVD RT_BIT(3)
446%define X86_TRAP_PF_ID RT_BIT(4)
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette