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source: vbox/trunk/include/iprt/armv8.h@ 106430

Last change on this file since 106430 was 106363, checked in by vboxsync, 6 months ago

include/iprt/armv8.h: Add more definitions and some bug fixing, bugref:10393 bugref:10388 bugref:10732
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/cdefs.h>
44# ifndef RT_IN_ASSEMBLER
45# include <iprt/types.h>
46# include <iprt/assert.h>
47# endif
48# include <iprt/assertcompile.h>
49#else
50# pragma D depends_on library vbox-types.d
51#endif
52
53/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
54 * @ingroup grp_rt
55 * @{
56 */
57
58/** @name The AArch64 register encoding - deprecated.
59 * @deprecated Use ARMV8_A64_REG_XXX instead.
60 * @todo correct code and drop these remaining ones.
61 * @{ */
62#define ARMV8_AARCH64_REG_X0 0
63#define ARMV8_AARCH64_REG_X1 1
64#define ARMV8_AARCH64_REG_X2 2
65#define ARMV8_AARCH64_REG_X3 3
66#define ARMV8_AARCH64_REG_ZR 31
67/** @} */
68
69/** @name The AArch64 general purpose register encoding.
70 * @{ */
71#define ARMV8_A64_REG_X0 0
72#define ARMV8_A64_REG_X1 1
73#define ARMV8_A64_REG_X2 2
74#define ARMV8_A64_REG_X3 3
75#define ARMV8_A64_REG_X4 4
76#define ARMV8_A64_REG_X5 5
77#define ARMV8_A64_REG_X6 6
78#define ARMV8_A64_REG_X7 7
79#define ARMV8_A64_REG_X8 8
80#define ARMV8_A64_REG_X9 9
81#define ARMV8_A64_REG_X10 10
82#define ARMV8_A64_REG_X11 11
83#define ARMV8_A64_REG_X12 12
84#define ARMV8_A64_REG_X13 13
85#define ARMV8_A64_REG_X14 14
86#define ARMV8_A64_REG_X15 15
87#define ARMV8_A64_REG_X16 16
88#define ARMV8_A64_REG_X17 17
89#define ARMV8_A64_REG_X18 18
90#define ARMV8_A64_REG_X19 19
91#define ARMV8_A64_REG_X20 20
92#define ARMV8_A64_REG_X21 21
93#define ARMV8_A64_REG_X22 22
94#define ARMV8_A64_REG_X23 23
95#define ARMV8_A64_REG_X24 24
96#define ARMV8_A64_REG_X25 25
97#define ARMV8_A64_REG_X26 26
98#define ARMV8_A64_REG_X27 27
99#define ARMV8_A64_REG_X28 28
100#define ARMV8_A64_REG_X29 29
101#define ARMV8_A64_REG_X30 30
102/** @} */
103
104/** @name The AArch64 32-bit general purpose register names.
105 * @{ */
106#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
107#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
108#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
109#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
110#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
111#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
112#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
113#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
114#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
115#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
116#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
117#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
118#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
119#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
120#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
121#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
122#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
123#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
124#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
125#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
126#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
127#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
128#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
129#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
130#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
131#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
132#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
133#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
134#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
135#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
136#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
137/** @} */
138
139/** @name The AArch64 NEON scalar register encoding.
140 * @{ */
141#define ARMV8_A64_REG_Q0 0
142#define ARMV8_A64_REG_Q1 1
143#define ARMV8_A64_REG_Q2 2
144#define ARMV8_A64_REG_Q3 3
145#define ARMV8_A64_REG_Q4 4
146#define ARMV8_A64_REG_Q5 5
147#define ARMV8_A64_REG_Q6 6
148#define ARMV8_A64_REG_Q7 7
149#define ARMV8_A64_REG_Q8 8
150#define ARMV8_A64_REG_Q9 9
151#define ARMV8_A64_REG_Q10 10
152#define ARMV8_A64_REG_Q11 11
153#define ARMV8_A64_REG_Q12 12
154#define ARMV8_A64_REG_Q13 13
155#define ARMV8_A64_REG_Q14 14
156#define ARMV8_A64_REG_Q15 15
157#define ARMV8_A64_REG_Q16 16
158#define ARMV8_A64_REG_Q17 17
159#define ARMV8_A64_REG_Q18 18
160#define ARMV8_A64_REG_Q19 19
161#define ARMV8_A64_REG_Q20 20
162#define ARMV8_A64_REG_Q21 21
163#define ARMV8_A64_REG_Q22 22
164#define ARMV8_A64_REG_Q23 23
165#define ARMV8_A64_REG_Q24 24
166#define ARMV8_A64_REG_Q25 25
167#define ARMV8_A64_REG_Q26 26
168#define ARMV8_A64_REG_Q27 27
169#define ARMV8_A64_REG_Q28 28
170#define ARMV8_A64_REG_Q29 29
171#define ARMV8_A64_REG_Q30 30
172#define ARMV8_A64_REG_Q31 31
173/** @} */
174
175/** @name The AArch64 NEON vector register encoding.
176 * @{ */
177#define ARMV8_A64_REG_V0 ARMV8_A64_REG_Q0
178#define ARMV8_A64_REG_V1 ARMV8_A64_REG_Q1
179#define ARMV8_A64_REG_V2 ARMV8_A64_REG_Q2
180#define ARMV8_A64_REG_V3 ARMV8_A64_REG_Q3
181#define ARMV8_A64_REG_V4 ARMV8_A64_REG_Q4
182#define ARMV8_A64_REG_V5 ARMV8_A64_REG_Q5
183#define ARMV8_A64_REG_V6 ARMV8_A64_REG_Q6
184#define ARMV8_A64_REG_V7 ARMV8_A64_REG_Q7
185#define ARMV8_A64_REG_V8 ARMV8_A64_REG_Q8
186#define ARMV8_A64_REG_V9 ARMV8_A64_REG_Q9
187#define ARMV8_A64_REG_V10 ARMV8_A64_REG_Q10
188#define ARMV8_A64_REG_V11 ARMV8_A64_REG_Q11
189#define ARMV8_A64_REG_V12 ARMV8_A64_REG_Q12
190#define ARMV8_A64_REG_V13 ARMV8_A64_REG_Q13
191#define ARMV8_A64_REG_V14 ARMV8_A64_REG_Q14
192#define ARMV8_A64_REG_V15 ARMV8_A64_REG_Q15
193#define ARMV8_A64_REG_V16 ARMV8_A64_REG_Q16
194#define ARMV8_A64_REG_V17 ARMV8_A64_REG_Q17
195#define ARMV8_A64_REG_V18 ARMV8_A64_REG_Q18
196#define ARMV8_A64_REG_V19 ARMV8_A64_REG_Q19
197#define ARMV8_A64_REG_V20 ARMV8_A64_REG_Q20
198#define ARMV8_A64_REG_V21 ARMV8_A64_REG_Q21
199#define ARMV8_A64_REG_V22 ARMV8_A64_REG_Q22
200#define ARMV8_A64_REG_V23 ARMV8_A64_REG_Q23
201#define ARMV8_A64_REG_V24 ARMV8_A64_REG_Q24
202#define ARMV8_A64_REG_V25 ARMV8_A64_REG_Q25
203#define ARMV8_A64_REG_V26 ARMV8_A64_REG_Q26
204#define ARMV8_A64_REG_V27 ARMV8_A64_REG_Q27
205#define ARMV8_A64_REG_V28 ARMV8_A64_REG_Q28
206#define ARMV8_A64_REG_V29 ARMV8_A64_REG_Q29
207#define ARMV8_A64_REG_V30 ARMV8_A64_REG_Q30
208#define ARMV8_A64_REG_V31 ARMV8_A64_REG_Q31
209/** @} */
210
211/** @name The AArch64 register 31.
212 * @note Register 31 typically refers to the zero register, but can also in
213 * select case (by instruction and opecode field) refer the to stack
214 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
215 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
216 * 31 will be the zero register.
217 * @{ */
218/** The stack pointer. */
219#define ARMV8_A64_REG_SP 31
220/** The zero register. Reads as zero, writes ignored. */
221#define ARMV8_A64_REG_XZR 31
222/** The zero register, the 32-bit register name. */
223#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
224/** @} */
225
226/** @name AArch64 register aliases
227 * @{ */
228/** The link register is typically mapped to x30 as that's the default pick of
229 * the RET instruction. */
230#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
231/** Frame base pointer is typically mapped to x29. */
232#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
233/** @} */
234
235
236/** @name System register encoding.
237 * @{
238 */
239/** Mask for the op0 part of an MSR/MRS instruction */
240#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
241/** Shift for the op0 part of an MSR/MRS instruction */
242#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
243/** Returns the op0 part of the given MRS/MSR instruction. */
244#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
245/** Mask for the op1 part of an MSR/MRS instruction */
246#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
247/** Shift for the op1 part of an MSR/MRS instruction */
248#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
249/** Returns the op1 part of the given MRS/MSR instruction. */
250#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
251/** Mask for the CRn part of an MSR/MRS instruction */
252#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
253 | RT_BIT_32(15) )
254/** Shift for the CRn part of an MSR/MRS instruction */
255#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
256/** Returns the CRn part of the given MRS/MSR instruction. */
257#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
258/** Mask for the CRm part of an MSR/MRS instruction */
259#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
260 | RT_BIT_32(11) )
261/** Shift for the CRm part of an MSR/MRS instruction */
262#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
263/** Returns the CRn part of the given MRS/MSR instruction. */
264#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
265/** Mask for the op2 part of an MSR/MRS instruction */
266#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
267/** Shift for the op2 part of an MSR/MRS instruction */
268#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
269/** Returns the op2 part of the given MRS/MSR instruction. */
270#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
271/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
272#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
273 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
274 | ARMV8_AARCH64_SYSREG_OP2_MASK)
275/** @} */
276
277/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
278 * IPRT specific and not part of the ARMv8 specification.
279 * @{ */
280#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
281 (uint16_t)( (((a_Op0) & 0x3) << 14) \
282 | (((a_Op1) & 0x7) << 11) \
283 | (((a_CRn) & 0xf) << 7) \
284 | (((a_CRm) & 0xf) << 3) \
285 | ((a_Op2) & 0x7))
286/** Returns the internal system register ID from the given MRS/MSR instruction. */
287#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
288 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
289 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
290 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
291 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
292 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
293/** Encodes the given system register ID in the given MSR/MRS instruction. */
294#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
295 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
296/** @} */
297
298
299/** @name System register IDs.
300 * @{ */
301/** OSDTRRX_EL1 register - RW. */
302#define ARMV8_AARCH64_SYSREG_OSDTRRX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 0, 2)
303/** MDSCR_EL1 - RW. */
304#define ARMV8_AARCH64_SYSREG_MDSCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 2)
305/** DBGBVR<0..15>_EL1 register - RW. */
306#define ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 4)
307/** DBGBCR<0..15>_EL1 register - RW. */
308#define ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 5)
309/** DBGWVR<0..15>_EL1 register - RW. */
310#define ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 6)
311/** DBGWCR<0..15>_EL1 register - RW. */
312#define ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 7)
313/** MDCCINT_EL1 register - RW. */
314#define ARMV8_AARCH64_SYSREG_MDCCINT_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 0)
315/** OSDTRTX_EL1 register - RW. */
316#define ARMV8_AARCH64_SYSREG_OSDTRTX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 3, 2)
317/** OSECCR_EL1 register - RW. */
318#define ARMV8_AARCH64_SYSREG_OSECCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 6, 2)
319/** MDRAR_EL1 register - RO. */
320#define ARMV8_AARCH64_SYSREG_MDRAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 0)
321/** OSLAR_EL1 register - WO. */
322#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
323/** OSLSR_EL1 register - RO. */
324#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
325/** OSDLR_EL1 register - RW. */
326#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
327
328/** MIDR_EL1 register - RO. */
329#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
330/** MIPDR_EL1 register - RO. */
331#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
332/** REVIDR_EL1 register - RO. */
333#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
334/** ID_PFR0_EL1 register - RO. */
335#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
336/** ID_PFR1_EL1 register - RO. */
337#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
338/** ID_DFR0_EL1 register - RO. */
339#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
340/** ID_AFR0_EL1 register - RO. */
341#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
342/** ID_MMFR0_EL1 register - RO. */
343#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
344/** ID_MMFR1_EL1 register - RO. */
345#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
346/** ID_MMFR2_EL1 register - RO. */
347#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
348/** ID_MMFR3_EL1 register - RO. */
349#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
350
351/** ID_ISAR0_EL1 register - RO. */
352#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
353/** ID_ISAR1_EL1 register - RO. */
354#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
355/** ID_ISAR2_EL1 register - RO. */
356#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
357/** ID_ISAR3_EL1 register - RO. */
358#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
359/** ID_ISAR4_EL1 register - RO. */
360#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
361/** ID_ISAR5_EL1 register - RO. */
362#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
363/** ID_MMFR4_EL1 register - RO. */
364#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
365/** ID_ISAR6_EL1 register - RO. */
366#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
367
368/** MVFR0_EL1 register - RO. */
369#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
370/** MVFR1_EL1 register - RO. */
371#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
372/** MVFR2_EL1 register - RO. */
373#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
374/** ID_PFR2_EL1 register - RO. */
375#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
376/** ID_DFR1_EL1 register - RO. */
377#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
378/** ID_MMFR5_EL1 register - RO. */
379#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
380
381/** ID_AA64PFR0_EL1 register - RO. */
382#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
383/** ID_AA64PFR0_EL1 register - RO. */
384#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
385/** ID_AA64ZFR0_EL1 register - RO. */
386#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
387/** ID_AA64SMFR0_EL1 register - RO. */
388#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
389
390/** ID_AA64DFR0_EL1 register - RO. */
391#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
392/** ID_AA64DFR0_EL1 register - RO. */
393#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
394/** ID_AA64AFR0_EL1 register - RO. */
395#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
396/** ID_AA64AFR1_EL1 register - RO. */
397#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
398
399/** ID_AA64ISAR0_EL1 register - RO. */
400#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
401/** ID_AA64ISAR1_EL1 register - RO. */
402#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
403/** ID_AA64ISAR2_EL1 register - RO. */
404#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
405
406/** ID_AA64MMFR0_EL1 register - RO. */
407#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
408/** ID_AA64MMFR1_EL1 register - RO. */
409#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
410/** ID_AA64MMFR2_EL1 register - RO. */
411#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
412
413/** SCTRL_EL1 register - RW. */
414#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
415/** ACTRL_EL1 register - RW. */
416#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
417/** CPACR_EL1 register - RW. */
418#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
419/** RGSR_EL1 register - RW. */
420#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
421/** GCR_EL1 register - RW. */
422#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
423
424/** ZCR_EL1 register - RW. */
425#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
426/** TRFCR_EL1 register - RW. */
427#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
428/** SMPRI_EL1 register - RW. */
429#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
430/** SMCR_EL1 register - RW. */
431#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
432
433/** TTBR0_EL1 register - RW. */
434#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
435/** TTBR1_EL1 register - RW. */
436#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
437/** TCR_EL1 register - RW. */
438#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
439
440/** APIAKeyLo_EL1 register - RW. */
441#define ARMV8_AARCH64_SYSREG_APIAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 0)
442/** APIAKeyHi_EL1 register - RW. */
443#define ARMV8_AARCH64_SYSREG_APIAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 1)
444/** APIBKeyLo_EL1 register - RW. */
445#define ARMV8_AARCH64_SYSREG_APIBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 2)
446/** APIBKeyHi_EL1 register - RW. */
447#define ARMV8_AARCH64_SYSREG_APIBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 3)
448
449/** APDAKeyLo_EL1 register - RW. */
450#define ARMV8_AARCH64_SYSREG_APDAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 0)
451/** APDAKeyHi_EL1 register - RW. */
452#define ARMV8_AARCH64_SYSREG_APDAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 1)
453/** APDBKeyLo_EL1 register - RW. */
454#define ARMV8_AARCH64_SYSREG_APDBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 2)
455/** APDBKeyHi_EL1 register - RW. */
456#define ARMV8_AARCH64_SYSREG_APDBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 3)
457
458/** APGAKeyLo_EL1 register - RW. */
459#define ARMV8_AARCH64_SYSREG_APGAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 0)
460/** APGAKeyHi_EL1 register - RW. */
461#define ARMV8_AARCH64_SYSREG_APGAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 1)
462
463/** SPSR_EL1 register - RW. */
464#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
465/** ELR_EL1 register - RW. */
466#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
467
468/** SP_EL0 register - RW. */
469#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
470
471/** PSTATE.SPSel value. */
472#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
473/** PSTATE.CurrentEL value. */
474#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
475/** PSTATE.PAN value. */
476#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
477/** PSTATE.UAO value. */
478#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
479
480/** PSTATE.ALLINT value. */
481#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
482
483/** ICC_PMR_EL1 register - RW. */
484#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
485
486/** AFSR0_EL1 register - RW. */
487#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
488/** AFSR1_EL1 register - RW. */
489#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
490
491/** ESR_EL1 register - RW. */
492#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
493
494/** ERRIDR_EL1 register - RO. */
495#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
496/** ERRSELR_EL1 register - RW. */
497#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
498
499/** FAR_EL1 register - RW. */
500#define ARMV8_AARCH64_SYSREG_FAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 6, 0, 0)
501
502/** PAR_EL1 register - RW. */
503#define ARMV8_AARCH64_SYSREG_PAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 7, 4, 0)
504
505/** MAIR_EL1 register - RW. */
506#define ARMV8_AARCH64_SYSREG_MAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 2, 0)
507
508/** AMAIR_EL1 register - RW. */
509#define ARMV8_AARCH64_SYSREG_AMAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 3, 0)
510
511/** VBAR_EL1 register - RW. */
512#define ARMV8_AARCH64_SYSREG_VBAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 0, 0)
513
514/** ICC_IAR0_EL1 register - RO. */
515#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
516/** ICC_EOIR0_EL1 register - WO. */
517#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
518/** ICC_HPPIR0_EL1 register - WO. */
519#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
520/** ICC_BPR0_EL1 register - RW. */
521#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
522/** ICC_AP0R0_EL1 register - RW. */
523#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
524/** ICC_AP0R1_EL1 register - RW. */
525#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
526/** ICC_AP0R2_EL1 register - RW. */
527#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
528/** ICC_AP0R3_EL1 register - RW. */
529#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
530
531/** ICC_AP1R0_EL1 register - RW. */
532#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
533/** ICC_AP1R1_EL1 register - RW. */
534#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
535/** ICC_AP1R2_EL1 register - RW. */
536#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
537/** ICC_AP1R3_EL1 register - RW. */
538#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
539/** ICC_NMIAR1_EL1 register - RO. */
540#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
541
542/** ICC_DIR_EL1 register - WO. */
543#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
544/** ICC_RPR_EL1 register - RO. */
545#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
546/** ICC_SGI1R_EL1 register - WO. */
547#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
548/** ICC_ASGI1R_EL1 register - WO. */
549#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
550/** ICC_SGI0R_EL1 register - WO. */
551#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
552
553/** ICC_IAR1_EL1 register - RO. */
554#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
555/** ICC_EOIR1_EL1 register - WO. */
556#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
557/** ICC_HPPIR1_EL1 register - RO. */
558#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
559/** ICC_BPR1_EL1 register - RW. */
560#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
561/** ICC_CTLR_EL1 register - RW. */
562#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
563/** ICC_SRE_EL1 register - RW. */
564#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
565/** ICC_IGRPEN0_EL1 register - RW. */
566#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
567/** ICC_IGRPEN1_EL1 register - RW. */
568#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
569
570/** CONTEXTIDR_EL1 register - RW. */
571#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 1)
572/** TPIDR_EL1 register - RW. */
573#define ARMV8_AARCH64_SYSREG_TPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 4)
574
575/** CNTKCTL_EL1 register - RW. */
576#define ARMV8_AARCH64_SYSREG_CNTKCTL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 14, 1, 0)
577
578/** CSSELR_EL1 register - RW. */
579#define ARMV8_AARCH64_SYSREG_CSSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 2, 0, 0, 0)
580
581/** NZCV - Status Flags - ??. */
582#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
583/** DAIF - Interrupt Mask Bits - ??. */
584#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
585/** SVCR - Streaming Vector Control Register - ??. */
586#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
587/** DIT - Data Independent Timing - ??. */
588#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
589/** SSBS - Speculative Store Bypass Safe - ??. */
590#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
591/** TCO - Tag Check Override - ??. */
592#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
593
594/** FPCR register - RW. */
595#define ARMV8_AARCH64_SYSREG_FPCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 0)
596/** FPSR register - RW. */
597#define ARMV8_AARCH64_SYSREG_FPSR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 1)
598
599/** PMCR_EL0 register - RW. */
600#define ARMV8_AARCH64_SYSREG_PMCR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 0)
601
602/** PMCCNTR_EL0 register - RW. */
603#define ARMV8_AARCH64_SYSREG_PMCCNTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 13, 0)
604
605/** ICC_SRE_EL2 register - RW. */
606#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 9, 5)
607
608/** TPIDR_EL0 register - RW. */
609#define ARMV8_AARCH64_SYSREG_TPIDR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 2)
610/** TPIDRRO_EL0 register - RO. */
611#define ARMV8_AARCH64_SYSREG_TPIDRRO_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 3)
612
613/** CNTFRQ_EL0 register - RW. */
614#define ARMV8_AARCH64_SYSREG_CNTFRQ_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 0)
615/** CNTVCT_EL0 register - RW. */
616#define ARMV8_AARCH64_SYSREG_CNTVCT_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 2)
617
618/** CNTP_TVAL_EL0 register - RW. */
619#define ARMV8_AARCH64_SYSREG_CNTP_TVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 0)
620/** CNTP_CTL_EL0 register - RW. */
621#define ARMV8_AARCH64_SYSREG_CNTP_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 1)
622/** CNTP_CVAL_EL0 register - RW. */
623#define ARMV8_AARCH64_SYSREG_CNTP_CVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 2)
624
625/** CNTV_CTL_EL0 register - RW. */
626#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
627
628/** VPIDR_EL2 register - RW. */
629#define ARMV8_AARCH64_SYSREG_VPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 0)
630/** VMPIDR_EL2 register - RW. */
631#define ARMV8_AARCH64_SYSREG_VMPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 5)
632
633/** SCTLR_EL2 register - RW. */
634#define ARMV8_AARCH64_SYSREG_SCTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 0)
635/** ACTLR_EL2 register - RW. */
636#define ARMV8_AARCH64_SYSREG_ACTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 1)
637
638/** HCR_EL2 register - RW. */
639#define ARMV8_AARCH64_SYSREG_HCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 0)
640/** MDCR_EL2 register - RW. */
641#define ARMV8_AARCH64_SYSREG_MDCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 1)
642/** CPTR_EL2 register - RW. */
643#define ARMV8_AARCH64_SYSREG_CPTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 2)
644/** HSTR_EL2 register - RW. */
645#define ARMV8_AARCH64_SYSREG_HSTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 3)
646/** HFGRTR_EL2 register - RW. */
647#define ARMV8_AARCH64_SYSREG_HFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 4)
648/** HFGWTR_EL2 register - RW. */
649#define ARMV8_AARCH64_SYSREG_HFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 5)
650/** HFGITR_EL2 register - RW. */
651#define ARMV8_AARCH64_SYSREG_HFGITR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 6)
652/** HACR_EL2 register - RW. */
653#define ARMV8_AARCH64_SYSREG_HACR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 7)
654
655/** ZCR_EL2 register - RW. */
656#define ARMV8_AARCH64_SYSREG_ZCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 0)
657/** TRFCR_EL2 register - RW. */
658#define ARMV8_AARCH64_SYSREG_TRFCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 1)
659/** HCRX_EL2 register - RW. */
660#define ARMV8_AARCH64_SYSREG_HCRX_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 2)
661
662/** SDER32_EL2 register - RW. */
663#define ARMV8_AARCH64_SYSREG_SDER32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 3, 0)
664
665/** TTBR0_EL2 register - RW. */
666#define ARMV8_AARCH64_SYSREG_TTBR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 0)
667/** TTBR1_EL2 register - RW. */
668#define ARMV8_AARCH64_SYSREG_TTBR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 1)
669/** TCR_EL2 register - RW. */
670#define ARMV8_AARCH64_SYSREG_TCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 2)
671
672/** VTTBR_EL2 register - RW. */
673#define ARMV8_AARCH64_SYSREG_VTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 0)
674/** VTCR_EL2 register - RW. */
675#define ARMV8_AARCH64_SYSREG_VTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 2)
676
677/** VNCR_EL2 register - RW. */
678#define ARMV8_AARCH64_SYSREG_VNCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 2, 0)
679
680/** VSTTBR_EL2 register - RW. */
681#define ARMV8_AARCH64_SYSREG_VSTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 0)
682/** VSTCR_EL2 register - RW. */
683#define ARMV8_AARCH64_SYSREG_VSTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 2)
684
685/** DACR32_EL2 register - RW. */
686#define ARMV8_AARCH64_SYSREG_DACR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 0, 0)
687
688/** HDFGRTR_EL2 register - RW. */
689#define ARMV8_AARCH64_SYSREG_HDFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 4)
690/** HDFGWTR_EL2 register - RW. */
691#define ARMV8_AARCH64_SYSREG_HDFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 5)
692/** HAFGRTR_EL2 register - RW. */
693#define ARMV8_AARCH64_SYSREG_HAFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 6)
694
695/** SPSR_EL2 register - RW. */
696#define ARMV8_AARCH64_SYSREG_SPSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 0)
697/** ELR_EL2 register - RW. */
698#define ARMV8_AARCH64_SYSREG_ELR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 1)
699
700/** SP_EL1 register - RW. */
701#define ARMV8_AARCH64_SYSREG_SP_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 1, 0)
702
703/** IFSR32_EL2 register - RW. */
704#define ARMV8_AARCH64_SYSREG_IFSR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 0, 1)
705
706/** AFSR0_EL2 register - RW. */
707#define ARMV8_AARCH64_SYSREG_AFSR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 0)
708/** AFSR1_EL2 register - RW. */
709#define ARMV8_AARCH64_SYSREG_AFSR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 1)
710
711/** ESR_EL2 register - RW. */
712#define ARMV8_AARCH64_SYSREG_ESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 0)
713/** VSESR_EL2 register - RW. */
714#define ARMV8_AARCH64_SYSREG_VSESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 3)
715
716/** FPEXC32_EL2 register - RW. */
717#define ARMV8_AARCH64_SYSREG_FPEXC32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 3, 0)
718
719/** TFSR_EL2 register - RW. */
720#define ARMV8_AARCH64_SYSREG_TFSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 6, 0)
721
722/** FAR_EL2 register - RW. */
723#define ARMV8_AARCH64_SYSREG_FAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 0)
724/** HPFAR_EL2 register - RW. */
725#define ARMV8_AARCH64_SYSREG_HPFAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 4)
726
727/** PMSCR_EL2 register - RW. */
728#define ARMV8_AARCH64_SYSREG_PMSCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 9, 9, 0)
729
730/** MAIR_EL2 register - RW. */
731#define ARMV8_AARCH64_SYSREG_MAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 2, 0)
732
733/** AMAIR_EL2 register - RW. */
734#define ARMV8_AARCH64_SYSREG_AMAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 3, 0)
735
736/** MPAMHCR_EL2 register - RW. */
737#define ARMV8_AARCH64_SYSREG_MPAMHCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 0)
738/** MPAMVPMV_EL2 register - RW. */
739#define ARMV8_AARCH64_SYSREG_MPAMVPMV_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 1)
740
741/** MPAM2_EL2 register - RW. */
742#define ARMV8_AARCH64_SYSREG_MPAM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 5, 0)
743
744/** MPAMVPM0_EL2 register - RW. */
745#define ARMV8_AARCH64_SYSREG_MPAMVPM0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 0)
746/** MPAMVPM1_EL2 register - RW. */
747#define ARMV8_AARCH64_SYSREG_MPAMVPM1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 1)
748/** MPAMVPM2_EL2 register - RW. */
749#define ARMV8_AARCH64_SYSREG_MPAMVPM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 2)
750/** MPAMVPM3_EL2 register - RW. */
751#define ARMV8_AARCH64_SYSREG_MPAMVPM3_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 3)
752/** MPAMVPM4_EL2 register - RW. */
753#define ARMV8_AARCH64_SYSREG_MPAMVPM4_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 4)
754/** MPAMVPM5_EL2 register - RW. */
755#define ARMV8_AARCH64_SYSREG_MPAMVPM5_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 5)
756/** MPAMVPM6_EL2 register - RW. */
757#define ARMV8_AARCH64_SYSREG_MPAMVPM6_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 6)
758/** MPAMVPM7_EL2 register - RW. */
759#define ARMV8_AARCH64_SYSREG_MPAMVPM7_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 7)
760
761/** VBAR_EL2 register - RW. */
762#define ARMV8_AARCH64_SYSREG_VBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 0)
763/** RVBAR_EL2 register - RW. */
764#define ARMV8_AARCH64_SYSREG_RVBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 1)
765/** RMR_EL2 register - RW. */
766#define ARMV8_AARCH64_SYSREG_RMR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 2)
767
768/** VDISR_EL2 register - RW. */
769#define ARMV8_AARCH64_SYSREG_VDISR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 1, 1)
770
771/** CONTEXTIDR_EL2 register - RW. */
772#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 1)
773/** TPIDR_EL2 register - RW. */
774#define ARMV8_AARCH64_SYSREG_TPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 2)
775/** SCXTNUM_EL2 register - RW. */
776#define ARMV8_AARCH64_SYSREG_SCXTNUM_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 7)
777
778/** CNTVOFF_EL2 register - RW. */
779#define ARMV8_AARCH64_SYSREG_CNTVOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 3)
780/** CNTPOFF_EL2 register - RW. */
781#define ARMV8_AARCH64_SYSREG_CNTPOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 6)
782
783/** CNTHCTL_EL2 register - RW. */
784#define ARMV8_AARCH64_SYSREG_CNTHCTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 1, 0)
785
786/** CNTHP_TVAL_EL2 register - RW. */
787#define ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 0)
788/** CNTHP_CTL_EL2 register - RW. */
789#define ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 1)
790/** CNTHP_CVAL_EL2 register - RW. */
791#define ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 2)
792
793/** CNTHV_TVAL_EL2 register - RW. */
794#define ARMV8_AARCH64_SYSREG_CNTHV_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 0)
795/** CNTHV_CTL_EL2 register - RW. */
796#define ARMV8_AARCH64_SYSREG_CNTHV_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 1)
797/** CNTHV_CVAL_EL2 register - RW. */
798#define ARMV8_AARCH64_SYSREG_CNTHV_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 2)
799
800/** CNTHVS_TVAL_EL2 register - RW. */
801#define ARMV8_AARCH64_SYSREG_CNTHVS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 0)
802/** CNTHVS_CTL_EL2 register - RW. */
803#define ARMV8_AARCH64_SYSREG_CNTHVS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 1)
804/** CNTHVS_CVAL_EL2 register - RW. */
805#define ARMV8_AARCH64_SYSREG_CNTHVS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 2)
806
807/** CNTHPS_TVAL_EL2 register - RW. */
808#define ARMV8_AARCH64_SYSREG_CNTHPS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 0)
809/** CNTHPS_CTL_EL2 register - RW. */
810#define ARMV8_AARCH64_SYSREG_CNTHPS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 1)
811/** CNTHPS_CVAL_EL2 register - RW. */
812#define ARMV8_AARCH64_SYSREG_CNTHPS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 2)
813
814/** SP_EL2 register - RW. */
815#define ARMV8_AARCH64_SYSREG_SP_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 6, 4, 1, 0)
816/** @} */
817
818
819#ifndef RT_IN_ASSEMBLER
820/**
821 * SPSR_EL2 (according to chapter C5.2.19)
822 */
823typedef union ARMV8SPSREL2
824{
825 /** The plain unsigned view. */
826 uint64_t u;
827 /** The 8-bit view. */
828 uint8_t au8[8];
829 /** The 16-bit view. */
830 uint16_t au16[4];
831 /** The 32-bit view. */
832 uint32_t au32[2];
833 /** The 64-bit view. */
834 uint64_t u64;
835} ARMV8SPSREL2;
836/** Pointer to SPSR_EL2. */
837typedef ARMV8SPSREL2 *PARMV8SPSREL2;
838/** Pointer to const SPSR_EL2. */
839typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
840#endif /* !RT_IN_ASSEMBLER */
841
842
843/** @name SPSR_EL2 (When exception is taken from AArch64 state)
844 * @{
845 */
846/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
847#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
848#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
849/** Bit 0 - SP - Selected stack pointer. */
850#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
851#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
852/** Bit 1 - Reserved (read as zero). */
853#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
854/** Bit 2 - 3 - EL - Exception level. */
855#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
856#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
857#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
858#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
859/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
860#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
861#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
862/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
863#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
864#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
865/** Bit 6 - I - FIQ interrupt mask. */
866#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
867#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
868/** Bit 7 - I - IRQ interrupt mask. */
869#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
870#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
871/** Bit 8 - A - SError interrupt mask. */
872#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
873#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
874/** Bit 9 - D - Debug Exception mask. */
875#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
876#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
877/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
878#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
879#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
880#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
881/** Bit 12 - SSBS - Speculative Store Bypass. */
882#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
883#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
884/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
885#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
886#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
887/** Bit 14 - 19 - Reserved (read as zero). */
888#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
889 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
890/** Bit 20 - IL - Illegal Execution State flag. */
891#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
892#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
893/** Bit 21 - SS - Software Step flag. */
894#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
895#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
896/** Bit 22 - PAN - Privileged Access Never flag. */
897#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
898#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
899/** Bit 23 - UAO - User Access Override flag. */
900#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
901#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
902/** Bit 24 - DIT - Data Independent Timing flag. */
903#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
904#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
905/** Bit 25 - TCO - Tag Check Override flag. */
906#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
907#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
908/** Bit 26 - 27 - Reserved (read as zero). */
909#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
910/** Bit 28 - V - Overflow condition flag. */
911#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
912#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
913/** Bit 29 - C - Carry condition flag. */
914#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
915#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
916/** Bit 30 - Z - Zero condition flag. */
917#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
918#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
919/** Bit 31 - N - Negative condition flag. */
920#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
921#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
922/** Bit 32 - 63 - Reserved (read as zero). */
923#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
924/** Checks whether the given SPSR value contains a AARCH64 execution state. */
925#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
926/** @} */
927
928/** @name Aarch64 Exception levels
929 * @{ */
930/** Exception Level 0 - User mode. */
931#define ARMV8_AARCH64_EL_0 0
932/** Exception Level 1 - Supervisor mode. */
933#define ARMV8_AARCH64_EL_1 1
934/** Exception Level 2 - Hypervisor mode. */
935#define ARMV8_AARCH64_EL_2 2
936/** @} */
937
938
939/** @name ESR_EL2 (Exception Syndrome Register, EL2)
940 * @{
941 */
942/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
943#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
944#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
945/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
946#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
947#define ARMV8_ESR_EL2_IL_BIT 25
948#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
949#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
950/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
951#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
952 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
953#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
954/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
955#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
956 | RT_BIT_64(35) | RT_BIT_64(36))
957#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
958/** @} */
959
960
961/** @name ESR_EL2 Exception Classes (EC)
962 * @{ */
963/** Unknown exception reason. */
964#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
965/** Trapped WF* instruction. */
966#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
967/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
968#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
969/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
970#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
971/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
972#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
973/** AArch32 - Trapped LDC or STC access. */
974#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
975/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
976#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
977/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
978#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
979/** AArch32 - Trapped pointer authentication instruction. */
980#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
981/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
982#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
983/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
984#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
985/** FEAT_BTI - Branch Target Exception. */
986#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
987/** Illegal Execution State. */
988#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
989/** AArch32 - SVC instruction execution. */
990#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
991/** AArch32 - HVC instruction execution. */
992#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
993/** AArch32 - SMC instruction execution. */
994#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
995/** AArch64 - SVC instruction execution. */
996#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
997/** AArch64 - HVC instruction execution. */
998#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
999/** AArch64 - SMC instruction execution. */
1000#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
1001/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
1002#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
1003/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
1004#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
1005/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
1006#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
1007/** FEAT_TME - Exception from TSTART instruction. */
1008#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
1009/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
1010#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
1011/** FEAT_SME - Access to SME functionality trapped. */
1012#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
1013/** FEAT_RME - Exception from Granule Protection Check. */
1014#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
1015/** Instruction Abort from a lower Exception level. */
1016#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
1017/** Instruction Abort from the same Exception level. */
1018#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
1019/** PC alignment fault exception. */
1020#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
1021/** Data Abort from a lower Exception level. */
1022#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
1023/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
1024#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
1025/** SP alignment fault exception. */
1026#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
1027/** FEAT_MOPS - Memory Operation Exception. */
1028#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
1029/** AArch32 - Trapped floating point exception. */
1030#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
1031/** AArch64 - Trapped floating point exception. */
1032#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
1033/** SError interrupt. */
1034#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
1035/** Breakpoint Exception from a lower Exception level. */
1036#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
1037/** Breakpoint Exception from the same Exception level. */
1038#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
1039/** Software Step Exception from a lower Exception level. */
1040#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
1041/** Software Step Exception from the same Exception level. */
1042#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
1043/** Watchpoint Exception from a lower Exception level. */
1044#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
1045/** Watchpoint Exception from the same Exception level. */
1046#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
1047/** AArch32 - BKPT instruction execution. */
1048#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
1049/** AArch32 - Vector Catch exception. */
1050#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
1051/** AArch64 - BRK instruction execution. */
1052#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
1053/** @} */
1054
1055
1056/** @name ISS encoding for Data Abort exceptions.
1057 * @{ */
1058/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
1059#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
1060 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
1061#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
1062/** Bit 6 - WnR - Write not Read. */
1063#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
1064#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
1065/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
1066#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
1067#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
1068/** Bit 8 - CM - Cache maintenance instruction. */
1069#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
1070#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
1071/** Bit 9 - EA - External abort type. */
1072#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
1073#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
1074/** Bit 10 - FnV - FAR not Valid. */
1075#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
1076#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
1077/** Bit 11 - 12 - LST - Load/Store Type. */
1078#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
1079#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
1080/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
1081#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
1082#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
1083/** Bit 14 - AR - Acquire/Release semantics. */
1084#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
1085#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
1086/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
1087#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
1088#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
1089/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
1090#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
1091 | RT_BIT_32(19) | RT_BIT_32(20))
1092#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
1093/** Bit 21 - SSE - Syndrome Sign Extend. */
1094#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
1095#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
1096/** Bit 22 - 23 - SAS - Syndrome Access Size. */
1097#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
1098#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
1099/** Bit 24 - ISV - Instruction Syndrome Valid. */
1100#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
1101#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
1102/** @} */
1103
1104
1105/** @name Data Fault Status Code (DFSC).
1106 * @{ */
1107/** Address size fault, level 0 of translation or translation table base register. */
1108#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
1109/** Address size fault, level 1. */
1110#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
1111/** Address size fault, level 2. */
1112#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
1113/** Address size fault, level 3. */
1114#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
1115/** Translation fault, level 0. */
1116#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
1117/** Translation fault, level 1. */
1118#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
1119/** Translation fault, level 2. */
1120#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
1121/** Translation fault, level 3. */
1122#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
1123/** FEAT_LPA2 - Access flag fault, level 0. */
1124#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
1125/** Access flag fault, level 1. */
1126#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
1127/** Access flag fault, level 2. */
1128#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
1129/** Access flag fault, level 3. */
1130#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
1131/** FEAT_LPA2 - Permission fault, level 0. */
1132#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
1133/** Permission fault, level 1. */
1134#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
1135/** Permission fault, level 2. */
1136#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
1137/** Permission fault, level 3. */
1138#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
1139/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
1140#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
1141/** FEAT_MTE2 - Synchronous Tag Check Fault. */
1142#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
1143/** @todo Do the rest (lazy developer). */
1144/** @} */
1145
1146
1147/** @name SAS encoding.
1148 * @{ */
1149/** Byte access. */
1150#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
1151/** Halfword access (uint16_t). */
1152#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
1153/** Word access (uint32_t). */
1154#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
1155/** Doubleword access (uint64_t). */
1156#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
1157/** @} */
1158
1159
1160/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
1161 * @{ */
1162/** Bit 0 - Direction flag. */
1163#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
1164#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
1165/** Bit 1 - 4 - CRm value from the instruction. */
1166#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
1167 | RT_BIT_32(4))
1168#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
1169/** Bit 5 - 9 - Rt value from the instruction. */
1170#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
1171 | RT_BIT_32(8) | RT_BIT_32(9))
1172#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
1173/** Bit 10 - 13 - CRn value from the instruction. */
1174#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
1175 | RT_BIT_32(13))
1176#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
1177/** Bit 14 - 16 - Op2 value from the instruction. */
1178#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
1179#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
1180/** Bit 17 - 19 - Op2 value from the instruction. */
1181#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
1182#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
1183/** Bit 20 - 21 - Op0 value from the instruction. */
1184#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
1185#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
1186/** Bit 22 - 24 - Reserved. */
1187#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
1188/** @} */
1189
1190
1191/** @name ISS encoding for trapped HVC instruction exceptions.
1192 * @{ */
1193/** Bit 0 - 15 - imm16 value of the instruction. */
1194#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
1195#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
1196/** @} */
1197
1198
1199/** @name TCR_EL1 - Translation Control Register (EL1)
1200 * @{
1201 */
1202/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
1203#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
1204 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
1205#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
1206/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
1207#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
1208#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
1209/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1210#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
1211#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
1212/** Non cacheable. */
1213# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
1214/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1215# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
1216/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1217# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
1218/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1219# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
1220/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1221#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
1222#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
1223/** Non cacheable. */
1224# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
1225/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1226# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
1227/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1228# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
1229/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1230# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
1231/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
1232#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
1233#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
1234/** Non shareable. */
1235# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
1236/** Invalid value. */
1237# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
1238/** Outer Shareable. */
1239# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
1240/** Inner Shareable. */
1241# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
1242/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
1243#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15))
1244#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
1245/** Invalid granule size. */
1246# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
1247/** 16KiB granule size. */
1248# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
1249/** 4KiB granule size. */
1250# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
1251/** 64KiB granule size. */
1252# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
1253/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
1254#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
1255 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
1256#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
1257/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
1258#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
1259#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
1260/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
1261#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
1262#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
1263/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1264#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
1265#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
1266/** Non cacheable. */
1267# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
1268/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1269# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
1270/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1271# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
1272/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1273# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
1274/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1275#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
1276#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
1277/** Non cacheable. */
1278# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
1279/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1280# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
1281/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1282# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
1283/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1284# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
1285/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
1286#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
1287#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
1288/** Non shareable. */
1289# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
1290/** Invalid value. */
1291# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
1292/** Outer Shareable. */
1293# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
1294/** Inner Shareable. */
1295# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
1296/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
1297#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
1298#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
1299/** Invalid granule size. */
1300# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
1301/** 16KiB granule size. */
1302# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
1303/** 4KiB granule size. */
1304# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
1305/** 64KiB granule size. */
1306# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
1307/** Bit 32 - 34 - Intermediate Physical Address Size. */
1308#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
1309#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
1310/** IPA - 32 bits, 4GiB. */
1311# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
1312/** IPA - 36 bits, 64GiB. */
1313# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
1314/** IPA - 40 bits, 1TiB. */
1315# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
1316/** IPA - 42 bits, 4TiB. */
1317# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
1318/** IPA - 44 bits, 16TiB. */
1319# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
1320/** IPA - 48 bits, 256TiB. */
1321# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
1322/** IPA - 52 bits, 4PiB. */
1323# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
1324/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
1325#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
1326#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
1327/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
1328#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
1329#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
1330/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
1331#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
1332#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
1333/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
1334#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
1335#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
1336/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
1337#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
1338#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
1339/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
1340#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
1341#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
1342/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
1343#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
1344#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
1345/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
1346#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
1347#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
1348/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
1349#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
1350#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
1351/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
1352#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
1353#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
1354/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
1355#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
1356#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
1357/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
1358#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
1359#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
1360/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
1361#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
1362#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
1363/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
1364#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1365#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1366/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1367#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1368#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1369/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1370#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1371#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1372/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1373#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1374#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1375/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1376#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1377#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1378/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1379#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1380#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1381/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1382#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1383#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1384/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1385#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1386#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1387/** Bit 57 - TCMA0 */
1388#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1389#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1390/** Bit 58 - TCMA1 */
1391#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1392#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1393/** Bit 59 - Data Sharing(?). */
1394#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1395#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1396/** @} */
1397
1398
1399/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1400 * @{
1401 */
1402/** Bit 0 - Common not Private (FEAT_TTCNP). */
1403#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1404#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1405/** Bit 1 - 47 - Translation table base address. */
1406#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1407#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) ((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR)
1408/** Bit 48 - 63 - ASID. */
1409#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1410#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1411/** @} */
1412
1413
1414/** @name MDSCR_EL1 - MOnitor Debug System Control Register (EL1).
1415 * @{ */
1416/** Bit 0 - SS - Software step control bit. */
1417#define ARMV8_MDSCR_EL1_AARCH64_SS RT_BIT_64(0)
1418#define ARMV8_MDSCR_EL1_AARCH64_SS_BIT 0
1419/** @} */
1420
1421
1422/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1423 * @{ */
1424/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1425#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1426#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1427#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1428/** @} */
1429
1430
1431/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1432 * @{ */
1433/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1434#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1435#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1436#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1437/** @} */
1438
1439
1440/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1441 * @{ */
1442/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1443#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1444#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1445#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1446/** @} */
1447
1448
1449/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1450 * @{ */
1451/** Bit 0 - Common Binary Pointer Register - RW. */
1452#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1453#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1454/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1455#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1456#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1457/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1458#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1459#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1460/** Bit 8 - 10 - Priority bits - RO. */
1461#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1462#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1463/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1464#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1465#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1466/** INTIDS are 16-bit wide. */
1467# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1468/** INTIDS are 24-bit wide. */
1469# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1470/** Bit 14 - SEI Supported - RO. */
1471#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1472#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1473/** Bit 15 - Affinity 3 Valid - RO. */
1474#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1475#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1476/** Bit 18 - Range Selector Support - RO. */
1477#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1478#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1479/** Bit 19 - Extended INTID range supported - RO. */
1480#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1481#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1482/** All RW bits. */
1483#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1484/** All RO bits (including Res0). */
1485#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1486/** @} */
1487
1488
1489/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1490 * @{ */
1491/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1492#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1493#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1494/** @} */
1495
1496
1497/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1498 * @{ */
1499/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1500#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1501#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1502/** @} */
1503
1504
1505/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1506 * @{ */
1507/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1508#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1509#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1510/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1511#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1512#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1513/** Bit 24 - 27 - The INTID of the SGI. */
1514#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1515#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1516/* Bit 28 - 31 - Reserved. */
1517/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1518#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1519#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1520/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1521#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1522#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1523/* Bit 41 - 43 - Reserved. */
1524/** Bit 44 - 47 - Range selector. */
1525#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1526#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1527/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1528#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1529#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1530/* Bit 56 - 63 - Reserved. */
1531/** @} */
1532
1533
1534/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1535 * @{ */
1536/** Bit 0 - Enables the timer. */
1537#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1538#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1539/** Bit 1 - Timer interrupt mask bit. */
1540#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1541#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1542/** Bit 2 - Timer status bit. */
1543#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1544#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1545/** @} */
1546
1547
1548/** @name OSLAR_EL1 - OS Lock Access Register.
1549 * @{ */
1550/** Bit 0 - The OS Lock status bit. */
1551#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1552#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1553/** @} */
1554
1555
1556/** @name OSLSR_EL1 - OS Lock Status Register.
1557 * @{ */
1558/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1559#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1560#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1561/** Bit 1 - The OS Lock status bit. */
1562#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1563#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1564/** Bit 2 - Not 32-bit access. */
1565#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1566#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1567/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1568#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1569#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1570/** @} */
1571
1572
1573/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1574 * @{ */
1575/* Bit 0 - 3 - Reserved. */
1576/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1577#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1578#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1579/** No AES instructions implemented. */
1580# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1581/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1582# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1583/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1584# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1585/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1586#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1587#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1588/** No SHA1 instructions implemented. */
1589# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1590/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1591# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1592/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1593#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1594#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1595/** No SHA2 instructions implemented. */
1596# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1597/** SHA256 instructions implemented (FEAT_SHA256). */
1598# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1599/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1600# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1601/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1602#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1603#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1604/** No CRC32 instructions implemented. */
1605# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1606/** CRC32 instructions implemented (FEAT_CRC32). */
1607# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1608/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1609#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1610#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1611/** No Atomic instructions implemented. */
1612# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1613/** Atomic instructions implemented (FEAT_LSE). */
1614# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1615/** Bit 24 - 27 - Indicates support for TME instructions. */
1616#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1617#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1618/** TME instructions are not implemented. */
1619# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1620/** TME instructions are implemented. */
1621# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1622/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1623#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1624#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1625/** No RDMA instructions implemented. */
1626# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1627/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1628# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1629/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1630#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1631#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1632/** No SHA3 instructions implemented. */
1633# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1634/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1635# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1636/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1637#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1638#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1639/** No SM3 instructions implemented. */
1640# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1641/** SM3 instructions implemented (FEAT_SM3). */
1642# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1643/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1644#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1645#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1646/** No SM4 instructions implemented. */
1647# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1648/** SM4 instructions implemented (FEAT_SM4). */
1649# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1650/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1651#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1652#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1653/** No Dot Product instructions implemented. */
1654# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1655/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1656# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1657/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1658#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1659#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1660/** FMLAL and FMLSL instructions are not implemented. */
1661# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1662/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1663# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1664/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1665#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1666#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1667/** No flag manipulation instructions implemented. */
1668# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1669/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1670# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1671/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1672# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1673/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1674#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1675#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1676/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1677# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1678/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1679# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1680/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1681# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1682/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1683#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1684#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1685/** No Random Number instructions implemented. */
1686# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1687/** RNDR and RDNRRS registers are implemented . */
1688# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1689/** @} */
1690
1691
1692/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1693 * @{ */
1694/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1695#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1696#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1697/** DC CVAP not supported. */
1698# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1699/** DC CVAP supported (FEAT_DPB). */
1700# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1701/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1702# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1703/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1704#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1705#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1706/** Address Authentication using the QARMA5 algorithm is not implemented. */
1707# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1708/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1709# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1710/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1711# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1712/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1713# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1714/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1715# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1716/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1717# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1718/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1719#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1720#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1721/** Address Authentication using the QARMA5 algorithm is not implemented. */
1722# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1723/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1724# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1725/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1726# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1727/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1728# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1729/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1730# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1731/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1732# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1733/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1734#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1735#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1736/** No FJCVTZS instruction implemented. */
1737# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1738/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1739# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1740/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1741#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1742#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1743/** No FCMLA and FCADD instructions implemented. */
1744# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1745/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1746# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1747/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1748#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1749#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1750/** No RCpc instructions implemented. */
1751# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1752/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1753# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1754/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1755# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1756/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1757#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1758#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1759/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1760# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1761/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1762# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1763/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1764#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1765#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1766/** Generic Authentication using an implementation defined algorithm is not implemented. */
1767# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1768/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1769# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1770/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1771#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1772#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1773/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1774# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1775/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1776# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1777/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1778#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1779#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1780/** No SB instructions implemented. */
1781# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1782/** SB instructions implemented (FEAT_SB). */
1783# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1784/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1785#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1786#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1787/** Prediction invalidation instructions are not implemented. */
1788# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1789/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1790# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1791/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1792#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1793#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1794/** BFloat16 instructions are not implemented. */
1795# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1796/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1797# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1798/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1799# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1800/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1801#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1802#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1803/** Data Gathering Hint instructions are not implemented. */
1804# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1805/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1806# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1807/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1808#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1809#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1810/** No Int8 matrix multiplication instructions implemented. */
1811# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1812/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1813# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1814/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1815#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1816#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1817/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1818# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1819/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1820# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1821/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1822#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1823#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1824/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1825# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1826/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1827# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1828/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1829# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1830/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1831# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1832/** @} */
1833
1834
1835/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1836 * @{ */
1837/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1838#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1839#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1840/** WFET and WFIT are not supported. */
1841# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1842/** WFET and WFIT are supported (FEAT_WFxT). */
1843# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1844/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1845#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1846#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1847/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1848# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1849/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1850# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1851/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1852#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1853#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1854/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1855# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1856/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1857# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1858/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1859#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1860#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1861/** Address Authentication using the QARMA3 algorithm is not implemented. */
1862# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1863/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1864# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1865/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1866# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1867/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1868# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1869/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1870# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1871/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1872# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1873/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1874#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1875#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1876/** No Memory Copy and Memory Set instructions implemented. */
1877# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1878/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1879# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1880/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1881#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1882#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1883/** BC instruction is not implemented. */
1884# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1885/** BC instruction is implemented (FEAT_HBC). */
1886# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1887/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1888#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1889#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1890/** ConstPACField() returns FALSE. */
1891# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1892/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1893# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1894/* Bit 28 - 63 - Reserved. */
1895/** @} */
1896
1897
1898/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1899 * @{ */
1900/** Bit 0 - 3 - EL0 Exception level handling. */
1901#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1902#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1903/** EL0 can be executed in AArch64 state only. */
1904# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1905/** EL0 can be executed in AArch64 and AArch32 state. */
1906# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1907/** Bit 4 - 7 - EL1 Exception level handling. */
1908#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1909#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1910/** EL1 can be executed in AArch64 state only. */
1911# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1912/** EL1 can be executed in AArch64 and AArch32 state. */
1913# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1914/** Bit 8 - 11 - EL2 Exception level handling. */
1915#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1916#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1917/** EL2 is not implemented. */
1918# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1919/** EL2 can be executed in AArch64 state only. */
1920# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1921/** EL2 can be executed in AArch64 and AArch32 state. */
1922# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1923/** Bit 12 - 15 - EL3 Exception level handling. */
1924#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1925#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1926/** EL3 is not implemented. */
1927# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1928/** EL3 can be executed in AArch64 state only. */
1929# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1930/** EL3 can be executed in AArch64 and AArch32 state. */
1931# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1932/** Bit 16 - 19 - Floating-point support. */
1933#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1934#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1935/** Floating-point is implemented and support single and double precision. */
1936# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1937/** Floating-point is implemented and support single, double and half precision. */
1938# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1939/** Floating-point is not implemented. */
1940# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1941/** Bit 20 - 23 - Advanced SIMD support. */
1942#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1943#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1944/** Advanced SIMD is implemented and support single and double precision. */
1945# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1946/** Advanced SIMD is implemented and support single, double and half precision. */
1947# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1948/** Advanced SIMD is not implemented. */
1949# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1950/** Bit 24 - 27 - System register GIC CPU interface support. */
1951#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1952#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1953/** GIC CPU interface system registers are not implemented. */
1954# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1955/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1956# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1957/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1958# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1959/** Bit 28 - 31 - RAS Extension version. */
1960#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1961#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1962/** No RAS extension. */
1963# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1964/** RAS Extension implemented. */
1965# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1966/** FEAT_RASv1p1 implemented. */
1967# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1968/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1969#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1970#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1971/** SVE is not supported. */
1972# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1973/** SVE is supported. */
1974# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1975/** Bit 36 - 39 - Secure EL2 support. */
1976#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1977#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1978/** Secure EL2 is not supported. */
1979# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1980/** Secure EL2 is implemented. */
1981# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1982/** Bit 40 - 43 - MPAM support. */
1983#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1984#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
1985/** MPAM extension major version number is 0. */
1986# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
1987/** MPAM extension major version number is 1. */
1988# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
1989/** Bit 44 - 47 - Activity Monitor Extension support. */
1990#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1991#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
1992/** Activity Monitor extension is not implemented. */
1993# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
1994/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
1995# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
1996/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
1997# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
1998/** Bit 48 - 51 - Data Independent Timing support. */
1999#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2000#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
2001/** AArch64 does not guarantee constant execution time of any instructions. */
2002# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
2003/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
2004# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
2005/** Bit 52 - 55 - Realm Management Extension support. */
2006#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2007#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
2008/** Realm Management Extension not implemented. */
2009# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
2010/** RMEv1 is implemented (FEAT_RME). */
2011# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
2012/** Bit 56 - 59 - Speculative use out of context branch targets support. */
2013#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2014#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
2015/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
2016# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
2017/** FEAT_CSV2 is implemented. */
2018# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
2019/** FEAT_CSV2_2 is implemented. */
2020# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
2021/** FEAT_CSV2_3 is implemented. */
2022# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
2023/** Bit 60 - 63 - Speculative use of faulting data support. */
2024#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2025#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
2026/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
2027# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
2028/** FEAT_CSV3 is supported . */
2029# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
2030/** @} */
2031
2032
2033/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
2034 * @{ */
2035/** Bit 0 - 3 - Branch Target Identification support. */
2036#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2037#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
2038/** The Branch Target Identification mechanism is not implemented. */
2039# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
2040/** The Branch Target Identifcation mechanism is implemented. */
2041# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
2042/** Bit 4 - 7 - Speculative Store Bypassing control support. */
2043#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2044#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
2045/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
2046# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
2047/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
2048# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
2049/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
2050 * to directly read and write the PSTATE.SSBS field. */
2051# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
2052/** Bit 8 - 11 - Memory Tagging Extension support. */
2053#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2054#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
2055/** MTE is not implemented. */
2056# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
2057/** Instruction only Memory Tagging Extensions implemented. */
2058# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
2059/** Full Memory Tagging Extension implemented. */
2060# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
2061/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
2062# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
2063/** Bit 12 - 15 - RAS Extension fractional field. */
2064#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2065#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
2066/** RAS Extension is implemented. */
2067# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
2068/** FEAT_RASv1p1 is implemented. */
2069# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
2070/** Bit 16 - 19 - MPAM minor version number. */
2071#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2072#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
2073/** The minor version of number of the MPAM extension is 0. */
2074# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
2075/** The minor version of number of the MPAM extension is 1. */
2076# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
2077/* Bit 20 - 23 - Reserved. */
2078/** Bit 24 - 27 - Scalable Matrix Extension support. */
2079#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2080#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
2081/** Scalable Matrix Extensions are not implemented. */
2082# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
2083/** Scalable Matrix Extensions are implemented (FEAT_SME). */
2084# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
2085/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
2086# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
2087/** Bit 28 - 31 - Random Number trap to EL3 support. */
2088#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2089#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
2090/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
2091# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
2092/** Trapping of RNDR and RDNRRS to EL3 is supported. */
2093# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
2094/** Bit 32 - 35 - CSV2 fractional field. */
2095#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2096#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
2097/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
2098# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
2099/** FEAT_CSV2_1p1 is implemented. */
2100# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
2101/** FEAT_CSV2_1p2 is implemented. */
2102# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
2103/** Bit 36 - 39 - Non-maskable Interrupt support. */
2104#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2105#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
2106/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
2107# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
2108/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
2109# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
2110/** @} */
2111
2112
2113/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
2114 * @{ */
2115/** Bit 0 - 3 - Physical Address range supported. */
2116#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2117#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
2118/** Physical Address range is 32 bits, 4GiB. */
2119# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
2120/** Physical Address range is 36 bits, 64GiB. */
2121# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
2122/** Physical Address range is 40 bits, 1TiB. */
2123# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
2124/** Physical Address range is 42 bits, 4TiB. */
2125# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
2126/** Physical Address range is 44 bits, 16TiB. */
2127# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
2128/** Physical Address range is 48 bits, 256TiB. */
2129# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
2130/** Physical Address range is 52 bits, 4PiB. */
2131# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
2132/** Bit 4 - 7 - Number of ASID bits. */
2133#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2134#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
2135/** ASID bits is 8. */
2136# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
2137/** ASID bits is 16. */
2138# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
2139/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
2140#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2141#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
2142/** No mixed-endian support. */
2143# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
2144/** Mixed-endian supported. */
2145# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
2146/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
2147#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2148#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
2149/** No distinction between Secure and Non-secure Memory supported. */
2150# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
2151/** Distinction between Secure and Non-secure Memory supported. */
2152# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
2153/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
2154#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2155#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
2156/** No mixed-endian support at EL0. */
2157# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
2158/** Mixed-endian support at EL0. */
2159# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
2160/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
2161#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2162#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
2163/** 16KiB granule size not supported. */
2164# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
2165/** 16KiB granule size is supported. */
2166# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
2167/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2168# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
2169/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
2170#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2171#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
2172/** 64KiB granule supported. */
2173# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
2174/** 64KiB granule not supported. */
2175# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
2176/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
2177#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2178#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
2179/** 4KiB granule supported. */
2180# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
2181/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2182# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
2183/** 4KiB granule not supported. */
2184# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
2185/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
2186#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2187#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
2188/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
2189# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
2190/** 16KiB granule not supported at stage 2. */
2191# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
2192/** 16KiB granule supported at stage 2. */
2193# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
2194/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2195# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
2196/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
2197#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2198#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
2199/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
2200# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
2201/** 64KiB granule not supported at stage 2. */
2202# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
2203/** 64KiB granule supported at stage 2. */
2204# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
2205/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2206#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2207#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
2208/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
2209# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
2210/** 4KiB granule not supported at stage 2. */
2211# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
2212/** 4KiB granule supported at stage 2. */
2213# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
2214/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2215# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
2216/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
2217#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2218#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
2219/** All exception entries and exits are context synchronization events. */
2220# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
2221/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
2222# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
2223/* Bit 48 - 55 - Reserved. */
2224/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
2225#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2226#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
2227/** Fine-grained trap controls are not implemented. */
2228# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
2229/** Fine-grained trap controls are implemented (FEAT_FGT). */
2230# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
2231/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
2232#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2233#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
2234/** Enhanced Counter Virtualization is not implemented. */
2235# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
2236/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
2237# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
2238/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
2239# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
2240/** @} */
2241
2242
2243/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
2244 * @{ */
2245/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
2246#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2247#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
2248/** Hardware update of the Access flag and dirty state are not supported. */
2249# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
2250/** Support for hardware update of the Access flag for Block and Page descriptors. */
2251# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
2252/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
2253# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
2254/** Bit 4 - 7 - EL1 Exception level handling. */
2255#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2256#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
2257/** VMID bits is 8. */
2258# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
2259/** VMID bits is 16 (FEAT_VMID16). */
2260# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
2261/** Bit 8 - 11 - Virtualization Host Extensions support. */
2262#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2263#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
2264/** Virtualization Host Extensions are not supported. */
2265# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
2266/** Virtualization Host Extensions are supported. */
2267# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
2268/** Bit 12 - 15 - Hierarchical Permission Disables. */
2269#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2270#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
2271/** Disabling of hierarchical controls not supported. */
2272# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
2273/** Disabling of hierarchical controls supported (FEAT_HPDS). */
2274# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
2275/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
2276# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
2277/** Bit 16 - 19 - LORegions support. */
2278#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2279#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
2280/** LORegions not supported. */
2281# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
2282/** LORegions supported. */
2283# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
2284/** Bit 20 - 23 - Privileged Access Never support. */
2285#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2286#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
2287/** PAN not supported. */
2288# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
2289/** PAN supported (FEAT_PAN). */
2290# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
2291/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
2292# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
2293/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
2294# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
2295/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
2296#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2297#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
2298/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
2299# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
2300/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
2301# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
2302/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
2303#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2304#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
2305/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
2306# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
2307/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
2308# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
2309/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
2310#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2311#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
2312/** Configurable delayed trapping of WFE is not supported. */
2313# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
2314/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
2315# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
2316/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
2317#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2318#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
2319/** Enhanced Translation Synchronization is not supported. */
2320# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
2321/** Enhanced Translation Synchronization is implemented. */
2322# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
2323/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2324#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2325#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
2326/** HCRX_EL2 and its associated EL3 trap are not supported. */
2327# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
2328/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
2329# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
2330/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
2331#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2332#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
2333/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
2334# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
2335/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
2336# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
2337/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
2338#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2339#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
2340/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
2341# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
2342/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
2343# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
2344/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
2345#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2346#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
2347/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
2348# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
2349/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
2350# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
2351/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
2352#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2353#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
2354/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
2355# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
2356/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
2357# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
2358/* Bit 60 - 63 - Reserved. */
2359/** @} */
2360
2361
2362/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
2363 * @{ */
2364/** Bit 0 - 3 - Indicates support for Common not Private translations. */
2365#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2366#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
2367/** Common not Private translations are not supported. */
2368# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
2369/** Support for Common not Private translations (FEAT_TTNCP). */
2370# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
2371/** Bit 4 - 7 - Indicates support for User Access Override. */
2372#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2373#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2374/** User Access Override is not supported. */
2375# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2376/** User Access Override is supported (FEAT_UAO). */
2377# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2378/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2379#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2380#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2381/** LSMAOE and nTLSMD bits are not supported. */
2382# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2383/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2384# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2385/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2386#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2387#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2388/** IESB bit is not supported. */
2389# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2390/** IESB bit is supported (FEAT_IESB). */
2391# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2392/** Bit 16 - 19 - Indicates support for larger virtual address. */
2393#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2394#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2395/** Virtual address range is 48 bits. */
2396# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2397/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2398# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2399/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2400#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2401#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2402/** CCSIDR_EL1 register format is 32-bit. */
2403# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2404/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2405# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2406/** Bit 24 - 27 - Indicates support for nested virtualization. */
2407#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2408#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2409/** Nested virtualization is not supported. */
2410# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2411/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2412# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2413/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2414# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2415/** Bit 28 - 31 - Indicates support for small translation tables. */
2416#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2417#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2418/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2419# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2420/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2421# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2422/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2423#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2424#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2425/** Unaligned single-copy atomicity and atomic functions are not supported. */
2426# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2427/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2428# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2429/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2430#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2431#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2432/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2433# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2434/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2435# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2436/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2437#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2438#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2439/** HCR_EL2.FWB bit is not supported. */
2440# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2441/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2442# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2443/* Bit 44 - 47 - Reserved. */
2444/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2445#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2446#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2447/** TLB maintenance instructions by address have bits [47:44] Res0. */
2448# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2449/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2450# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2451/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2452 * changing block size for a translation. */
2453#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2454#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2455/** Level 0 support for changing block size is supported (FEAT_BBM). */
2456# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2457/** Level 1 support for changing block size is supported (FEAT_BBM). */
2458# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2459/** Level 2 support for changing block size is supported (FEAT_BBM). */
2460# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2461/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2462#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2463#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2464/** Enhanced Virtualization Traps are not supported. */
2465# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2466/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2467# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2468/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2469# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2470/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2471#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2472#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2473/** E0PDx mechanism is not supported. */
2474# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2475/** E0PDx mechanism is supported (FEAT_E0PD). */
2476# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2477/** @} */
2478
2479
2480/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2481 * @{ */
2482/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2483#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2484#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2485/** Armv8 debug architecture version. */
2486# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2487/** Armv8 debug architecture version with virtualization host extensions. */
2488# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2489/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2490# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2491/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2492# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2493/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2494# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2495/** Bit 4 - 7 - Indicates trace support. */
2496#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2497#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2498/** Trace unit System registers not implemented. */
2499# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2500/** Trace unit System registers supported. */
2501# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2502/** Bit 8 - 11 - Performance Monitors Extension version. */
2503#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2504#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2505/** Performance Monitors Extension not supported. */
2506# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2507/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2508# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2509/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2510# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2511/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2512# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2513/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2514# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2515/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2516# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2517/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2518# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2519/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2520#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2521#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2522/* Bit 16 - 19 - Reserved 0. */
2523/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2524#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2525#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2526/* Bit 24 - 27 - Reserved 0. */
2527/** Bit 28 - 31 - Number of context-aware breakpoints. */
2528#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2529#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2530/** Bit 32 - 35 - Statistical Profiling Extension version. */
2531#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2532#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2533/** Statistical Profiling Extension not implemented. */
2534# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2535/** Statistical Profiling Extension supported (FEAT_SPE). */
2536# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2537/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2538# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2539/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2540# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2541/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2542# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2543/** Bit 36 - 39 - OS Double Lock implemented. */
2544#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2545#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2546/** OS Double Lock is not implemented. */
2547# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2548/** OS Double Lock is supported (FEAT_DoubleLock). */
2549# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2550/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2551#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2552#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2553/** Armv8.4 self-hosted Trace Extension not implemented. */
2554# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2555/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2556# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2557/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2558#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2559#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2560/** Trace Buffer Extension is not implemented. */
2561# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2562/** Trace Buffer Extension is supported (FEAT_TRBE). */
2563# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2564/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2565#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2566#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2567/** Multi-threaded PMU extension is not implemented. */
2568# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2569/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2570# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2571/** Multi-threaded PMU extension is not implemented. */
2572# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2573/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2574#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2575#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2576/** Branch Record Buffer extension is not implemented. */
2577# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2578/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2579# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2580/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2581# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2582/* Bit 56 - 59 - Reserved. */
2583/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2584#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2585#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2586/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2587# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2588/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2589# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2590/** @} */
2591
2592
2593/** @name FPCR - AArch64 Floating Point Control Register.
2594 * @{ */
2595/** Bit 0 - Flush Inputs to Zero when FEAT_AFP is supported. */
2596#define ARMV8_FPCR_FIZ RT_BIT_64(0)
2597#define ARMV8_FPCR_FIZ_BIT 0
2598/** Bit 1 - Alternate Handling of floating-point numbers when FEAT_AFP is supported. */
2599#define ARMV8_FPCR_AH RT_BIT_64(1)
2600#define ARMV8_FPCR_AH_BIT 1
2601/** Bit 2 - Controls how the output elements other than the lowest element of the vector are determined for
2602 * Advanced SIMD scalar instructions, when FEAT_AFP is supported. */
2603#define ARMV8_FPCR_NEP RT_BIT_64(2)
2604#define ARMV8_FPCR_NEP_BIT 2
2605/* Bit 3 - 7 - Reserved.*/
2606/** Bit 8 - Invalid Operation floating-point exception trap enable. */
2607#define ARMV8_FPCR_IOE RT_BIT_64(8)
2608#define ARMV8_FPCR_IOE_BIT 8
2609/** Bit 9 - Divide by Zero floating-point exception trap enable. */
2610#define ARMV8_FPCR_DZE RT_BIT_64(9)
2611#define ARMV8_FPCR_DZE_BIT 9
2612/** Bit 10 - Overflow floating-point exception trap enable. */
2613#define ARMV8_FPCR_OFE RT_BIT_64(10)
2614#define ARMV8_FPCR_OFE_BIT 10
2615/** Bit 11 - Underflow floating-point exception trap enable. */
2616#define ARMV8_FPCR_UFE RT_BIT_64(11)
2617#define ARMV8_FPCR_UFE_BIT 11
2618/** Bit 12 - Inexact floating-point exception trap enable. */
2619#define ARMV8_FPCR_IXE RT_BIT_64(12)
2620#define ARMV8_FPCR_IXE_BIT 12
2621/** Bit 13 - Controls numeric behavior of BFloat16 dot productions calculations performed,
2622 * supported when FEAT_EBF16 is supported. */
2623#define ARMV8_FPCR_EBF RT_BIT_64(13)
2624#define ARMV8_FPCR_EBF_BIT 13
2625/* Bit 14 - Reserved */
2626/** Bit 15 - Input Denormal floating-point exception trap enable. */
2627#define ARMV8_FPCR_IDE RT_BIT_64(15)
2628#define ARMV8_FPCR_IDE_BIT 15
2629/* Bit 16 - 18 - Reserved for AArch64 (Len field for AArch32). */
2630/** Bit 19 - Flushing denormalized numbers to zero control bit on half-precision data-processing instructions,
2631 * available when FEAT_FP16 is supported. */
2632#define ARMV8_FPCR_FZ16 RT_BIT_64(19)
2633#define ARMV8_FPCR_FZ16_BIT 19
2634/* Bit 20 - 21 - Reserved for AArch64 (Stride field dor AArch32). */
2635/** Bit 22 - 23 - Rounding Mode control field. */
2636#define ARMV8_FPCR_RMODE_MASK (RT_BIT_64(22) | RT_BIT_64(23))
2637#define ARMV8_FPCR_RMODE_SHIFT 22
2638/** Round to Nearest (RN) mode. */
2639# define ARMV8_FPCR_RMODE_RN 0
2640/** Round towards Plus Infinity (RP) mode. */
2641# define ARMV8_FPCR_RMODE_RP 1
2642/** Round towards Minus Infinity (RM) mode. */
2643# define ARMV8_FPCR_RMODE_RM 2
2644/** Round towards Zero (RZ) mode. */
2645# define ARMV8_FPCR_RMODE_RZ 3
2646/** Bit 24 - Flushing denormalized numbers to zero control bit. */
2647#define ARMV8_FPCR_FZ RT_BIT_64(24)
2648#define ARMV8_FPCR_FZ_BIT 24
2649/** Bit 25 - Default NaN use for NaN propagation. */
2650#define ARMV8_FPCR_DN RT_BIT_64(25)
2651#define ARMV8_FPCR_DN_BIT 25
2652/** Bit 26 - Alternative half-precision control bit. */
2653#define ARMV8_FPCR_AHP RT_BIT_64(26)
2654#define ARMV8_FPCR_AHP_BIT 26
2655/* Bit 27 - 63 - Reserved. */
2656/** @} */
2657
2658
2659/** @name FPSR - AArch64 Floating Point Status Register.
2660 * @{ */
2661/** Bit 0 - Invalid Operation cumulative floating-point exception bit. */
2662#define ARMV8_FPSR_IOC RT_BIT_64(0)
2663/** Bit 1 - Divide by Zero cumulative floating-point exception bit. */
2664#define ARMV8_FPSR_DZC RT_BIT_64(1)
2665/** Bit 2 - Overflow cumulative floating-point exception bit. */
2666#define ARMV8_FPSR_OFC RT_BIT_64(2)
2667/** Bit 3 - Underflow cumulative floating-point exception bit. */
2668#define ARMV8_FPSR_UFC RT_BIT_64(3)
2669/** Bit 4 - Inexact cumulative floating-point exception bit. */
2670#define ARMV8_FPSR_IXC RT_BIT_64(4)
2671/* Bit 5 - 6 - Reserved. */
2672/** Bit 7 - Input Denormal cumulative floating-point exception bit. */
2673#define ARMV8_FPSR_IDC RT_BIT_64(7)
2674/* Bit 8 - 26 - Reserved. */
2675/** Bit 27 - Cumulative saturation bit, Advanced SIMD only. */
2676#define ARMV8_FPSR_QC RT_BIT_64(27)
2677/* Bit 28 - 31 - NZCV bits for AArch32 floating point operations. */
2678/* Bit 32 - 63 - Reserved. */
2679/** @} */
2680
2681
2682
2683/** @name SCTLR_EL1 - AArch64 System Control Register (EL1).
2684 * @{ */
2685/** Bit 0 - MMU enable for EL1 and EL0 stage 1 address translation. */
2686#define ARMV8_SCTLR_EL1_M RT_BIT_64(0)
2687/** Bit 1 - Alignment check enable for EL1 and EL0. */
2688#define ARMV8_SCTLR_EL1_A RT_BIT_64(1)
2689/** Bit 2 - Stage 1 cacheability control, for data accesses. */
2690#define ARMV8_SCTLR_EL1_C RT_BIT_64(2)
2691/** Bit 3 - SP alignment check enable. */
2692#define ARMV8_SCTLR_EL1_SA RT_BIT_64(3)
2693/** Bit 4 - SP alignment check enable for EL0. */
2694#define ARMV8_SCTLR_EL1_SA0 RT_BIT_64(4)
2695/** Bit 5 - System instruction memory barrier enable from AArch32 EL0. */
2696#define ARMV8_SCTLR_EL1_CP15BEN RT_BIT_64(5)
2697/** Bit 6 - Non-aligned access enable. */
2698#define ARMV8_SCTLR_EL1_nAA RT_BIT_64(6)
2699/** Bit 7 - IT disable, disables some uses of IT instructions at EL0 using AArch32. */
2700#define ARMV8_SCTLR_EL1_ITD RT_BIT_64(7)
2701/** Bit 8 - SETEND instruction disable, disables SETEND instructions at EL0 using AArch32. */
2702#define ARMV8_SCTLR_EL1_SED RT_BIT_64(8)
2703/** Bit 9 - User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D,A,I,F} masks to EL1. */
2704#define ARMV8_SCTLR_EL1_UMA RT_BIT_64(9)
2705/** Bit 10 - Enable EL0 acccess to the CFP*, DVP* and CPP* instructions if FEAT_SPECRES is supported. */
2706#define ARMV8_SCTLR_EL1_EnRCTX RT_BIT_64(10)
2707/** Bit 11 - Exception Exit is Context Synchronizing (FEAT_ExS required). */
2708#define ARMV8_SCTLR_EL1_EOS RT_BIT_64(11)
2709/** Bit 12 - Stage 1 instruction access cacheability control, for access at EL0 and EL1. */
2710#define ARMV8_SCTLR_EL1_I RT_BIT_64(12)
2711/** @todo Finish (lazy developer). */
2712/** @} */
2713
2714
2715/** @name SCTLR_EL2 - AArch64 System Control Register (EL2) - 32-bit.
2716 * @{ */
2717/** Bit 0 - MMU enable for EL2. */
2718#define ARMV8_SCTLR_EL2_M RT_BIT_64(0)
2719/** Bit 1 - Alignment check enable. */
2720#define ARMV8_SCTLR_EL2_A RT_BIT_64(1)
2721/** Bit 2 - Global enable for data and unified caches. */
2722#define ARMV8_SCTLR_EL2_C RT_BIT_64(2)
2723/** Bit 3 - SP alignment check enable. */
2724#define ARMV8_SCTLR_EL2_SA RT_BIT_64(3)
2725/* Bit 4 - 11 - Reserved. */
2726/** Bit 12 - Instruction cache enable. */
2727#define ARMV8_SCTLR_EL2_I RT_BIT_64(12)
2728/* Bit 13 - 18 - Reserved. */
2729/** Bit 19 - Force treatment of all memory regions with write permissions as XN. */
2730#define ARMV8_SCTLR_EL2_WXN RT_BIT_64(19)
2731/* Bit 20 - 24 - Reserved. */
2732/** Bit 25 - Exception endianess - set means big endian, clear little endian. */
2733#define ARMV8_SCTLR_EL2_EE RT_BIT_64(25)
2734/* Bit 26 - 31 - Reserved. */
2735/** @} */
2736
2737
2738#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
2739/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2740 * @ingroup grp_rt_armv8
2741 *
2742 * A few inlined functions and macros for assiting in encoding common ARMv8
2743 * instructions.
2744 *
2745 * @{ */
2746
2747/** A64: Official NOP instruction. */
2748#define ARMV8_A64_INSTR_NOP UINT32_C(0xd503201f)
2749/** A64: Return instruction. */
2750#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2751/** A64: Return instruction with LR pointer authentication using SP and key A. */
2752#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2753/** A64: Return instruction with LR pointer authentication using SP and key B. */
2754#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2755/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2756#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2757/** A64: Insert pointer authentication code into LR using SP and key B. */
2758#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2759/** A64: Insert pointer authentication code into LR using XZR and key B. */
2760#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2761/** A64: Invert the carry flag (PSTATE.C). */
2762#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
2763
2764
2765/** Memory barrier: Shareability domain. */
2766typedef enum
2767{
2768 kArm64InstMbReqDomain_OuterShareable = 0,
2769 kArm64InstMbReqDomain_Nonshareable,
2770 kArm64InstMbReqDomain_InnerShareable,
2771 kArm64InstMbReqDomain_FullSystem
2772} ARM64INSTRMBREQDOMAIN;
2773
2774/** Memory barrier: Access type. */
2775typedef enum
2776{
2777 kArm64InstMbReqType_All0 = 0, /**< Special. Only used with PSSBB and SSBB. */
2778 kArm64InstMbReqType_Reads,
2779 kArm64InstMbReqType_Writes,
2780 kArm64InstMbReqType_All
2781} ARM64INSTRMBREQTYPE;
2782
2783/**
2784 * A64: DMB option
2785 */
2786DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDmb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
2787 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
2788{
2789 return UINT32_C(0xd50330bf)
2790 | ((uint32_t)enmDomain << 8)
2791 | ((uint32_t)enmType << 10);
2792}
2793
2794
2795/**
2796 * A64: DSB option
2797 */
2798DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
2799 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
2800{
2801 return UINT32_C(0xd503309f)
2802 | ((uint32_t)enmDomain << 8)
2803 | ((uint32_t)enmType << 10);
2804}
2805
2806
2807/**
2808 * A64: SSBB
2809 */
2810DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSsbb(void)
2811{
2812 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_OuterShareable, kArm64InstMbReqType_All0);
2813}
2814
2815
2816/**
2817 * A64: PSSBB
2818 */
2819DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPSsbb(void)
2820{
2821 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_Nonshareable, kArm64InstMbReqType_All0);
2822}
2823
2824
2825/**
2826 * A64: ISB option
2827 *
2828 * @note Only the default option selection is supported, all others are
2829 * currently reserved.
2830 */
2831DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
2832 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
2833{
2834 return UINT32_C(0xd50330df)
2835 | ((uint32_t)enmDomain << 8)
2836 | ((uint32_t)enmType << 10);
2837}
2838
2839
2840typedef enum
2841{
2842 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
2843 * and update the register. */
2844 kArm64InstrStLdPairType_PostIndex = 1,
2845 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2846 * but don't update the register. */
2847 kArm64InstrStLdPairType_Signed = 2,
2848 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2849 * and update the register. */
2850 kArm64InstrStLdPairType_PreIndex = 3
2851} ARM64INSTRSTLDPAIRTYPE;
2852
2853/**
2854 * A64: Encodes either stp (store register pair) or ldp (load register pair).
2855 *
2856 * @returns The encoded instruction.
2857 * @param fLoad true for ldp, false of stp.
2858 * @param u2Opc When @a fSimdFp is @c false:
2859 * - 0 for 32-bit GPRs (Wt).
2860 * - 1 for encoding stgp or ldpsw.
2861 * - 2 for 64-bit GRPs (Xt).
2862 * - 3 illegal.
2863 * When @a fSimdFp is @c true:
2864 * - 0 for 32-bit SIMD&FP registers (St).
2865 * - 1 for 64-bit SIMD&FP registers (Dt).
2866 * - 2 for 128-bit SIMD&FP regsiters (Qt).
2867 * @param enmType The instruction variant wrt addressing and updating of the
2868 * addressing register.
2869 * @param iReg1 The first register to store/load.
2870 * @param iReg2 The second register to store/load.
2871 * @param iBaseReg The base register to use when addressing. SP is allowed.
2872 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
2873 * will be multiplied by the register size.
2874 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
2875 * stgp/ldpsw instructions.
2876 */
2877DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
2878 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2879 bool fSimdFp = false)
2880{
2881 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
2882 return (u2Opc << 30)
2883 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
2884 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
2885 | ((uint32_t)enmType << 23)
2886 | ((uint32_t)fLoad << 22)
2887 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
2888 | (iReg2 << 10)
2889 | (iBaseReg << 5)
2890 | iReg1;
2891}
2892
2893
2894/** A64: ldp x1, x2, [x3] */
2895DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2896 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2897 bool f64Bit = true)
2898{
2899 return Armv8A64MkInstrStLdPair(true /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2900}
2901
2902
2903/** A64: stp x1, x2, [x3] */
2904DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2905 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2906 bool f64Bit = true)
2907{
2908 return Armv8A64MkInstrStLdPair(false /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2909}
2910
2911
2912typedef enum /* Size VR Opc */
2913{ /* \ | / */
2914 kArmv8A64InstrLdStType_Mask_Size = 0x300,
2915 kArmv8A64InstrLdStType_Mask_VR = 0x010,
2916 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
2917 kArmv8A64InstrLdStType_Shift_Size = 8,
2918 kArmv8A64InstrLdStType_Shift_VR = 4,
2919 kArmv8A64InstrLdStType_Shift_Opc = 0,
2920
2921 kArmv8A64InstrLdStType_St_Byte = 0x000,
2922 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
2923 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
2924 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
2925
2926 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
2927 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
2928 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
2929 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
2930
2931 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
2932 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
2933 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
2934
2935 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
2936 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
2937
2938 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
2939
2940 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
2941 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
2942 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
2943 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
2944
2945 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
2946 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
2947
2948 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
2949 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
2950
2951 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
2952 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
2953
2954} ARMV8A64INSTRLDSTTYPE;
2955/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
2956#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
2957
2958
2959/**
2960 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2961 *
2962 * @returns The encoded instruction.
2963 * @param u32Opcode The base opcode value.
2964 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2965 * @param iReg The register to load into / store.
2966 * @param iBaseReg The base register to use when addressing. SP is allowed.
2967 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2968 */
2969DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
2970 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2971{
2972 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
2973 return u32Opcode
2974 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2975 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2976 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2977 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
2978 | (iBaseReg << 5)
2979 | iReg;
2980}
2981
2982
2983/**
2984 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2985 *
2986 * @returns The encoded instruction.
2987 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2988 * @param iReg The register to load into / store.
2989 * @param iBaseReg The base register to use when addressing. SP is allowed.
2990 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2991 */
2992DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
2993 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2994{
2995 /* 3 2 1 0 */
2996 /* 10987654321098765432109876543210 */
2997 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
2998 enmType, iReg, iBaseReg, i9ImmDisp);
2999}
3000
3001/**
3002 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
3003 *
3004 * @returns The encoded instruction.
3005 * @param enmType The load/store instruction type. Prefech not valid.
3006 * @param iReg The register to load into / store.
3007 * @param iBaseReg The base register to use when addressing. SP is allowed.
3008 * Written back.
3009 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3010 */
3011DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3012 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3013{
3014 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3015 /* 10987654321098765432109876543210 */
3016 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
3017 enmType, iReg, iBaseReg, i9ImmDisp);
3018}
3019
3020/**
3021 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
3022 *
3023 * @returns The encoded instruction.
3024 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3025 * @param iReg The register to load into / store.
3026 * @param iBaseReg The base register to use when addressing. SP is allowed.
3027 * Written back.
3028 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3029 */
3030DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3031 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3032{
3033 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3034 /* 10987654321098765432109876543210 */
3035 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
3036 enmType, iReg, iBaseReg, i9ImmDisp);
3037}
3038
3039/**
3040 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
3041 *
3042 * @returns The encoded instruction.
3043 * @param enmType The load/store instruction type. Prefech not valid,
3044 * nor any SIMD&FP variants.
3045 * @param iReg The register to load into / store.
3046 * @param iBaseReg The base register to use when addressing. SP is allowed.
3047 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3048 */
3049DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
3050 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3051{
3052 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
3053 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
3054 /* 3 2 1 0 */
3055 /* 10987654321098765432109876543210 */
3056 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
3057 enmType, iReg, iBaseReg, i9ImmDisp);
3058}
3059
3060
3061/**
3062 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
3063 *
3064 * @returns The encoded instruction.
3065 * @param enmType The load/store instruction type. Prefech not valid,
3066 * nor any SIMD&FP variants.
3067 * @param iReg The register to load into / store.
3068 * @param iBaseReg The base register to use when addressing. SP is allowed.
3069 * @param u12ImmDisp Addressing displacement, scaled by size.
3070 */
3071DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
3072 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
3073{
3074 Assert(u12ImmDisp < 4096U);
3075 Assert(iReg < 32); /* 3 2 1 0 */
3076 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3077 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
3078 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3079 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3080 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3081 | (u12ImmDisp << 10)
3082 | (iBaseReg << 5)
3083 | iReg;
3084}
3085
3086typedef enum
3087{
3088 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
3089 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
3090 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
3091 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
3092} ARMV8A64INSTRLDSTEXTEND;
3093
3094/**
3095 * A64: Encodes load/store w/ index register.
3096 *
3097 * @returns The encoded instruction.
3098 * @param enmType The load/store instruction type.
3099 * @param iReg The register to load into / store.
3100 * @param iBaseReg The base register to use when addressing. SP is allowed.
3101 * @param iRegIndex The index register.
3102 * @param enmExtend The extending to apply to @a iRegIndex.
3103 * @param fShifted Whether to shift the index. The shift amount corresponds
3104 * to the access size (thus irrelevant for byte accesses).
3105 */
3106DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
3107 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
3108 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
3109 bool fShifted = false)
3110{
3111 Assert(iRegIndex < 32);
3112 Assert(iReg < 32); /* 3 2 1 0 */
3113 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3114 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
3115 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3116 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3117 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3118 | (iRegIndex << 16)
3119 | ((uint32_t)enmExtend << 13)
3120 | ((uint32_t)fShifted << 12)
3121 | (iBaseReg << 5)
3122 | iReg;
3123}
3124
3125typedef enum /* VR Opc */
3126{ /* \ | */
3127 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
3128 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
3129 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
3130 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
3131
3132 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
3133 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
3134 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
3135 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
3136
3137 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
3138 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
3139 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
3140} ARMV8A64INSTRLDRLITTERAL;
3141
3142
3143/**
3144 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
3145 *
3146 * @returns The encoded instruction.
3147 * @param enmType The load instruction type.
3148 * @param iReg The register to load into.
3149 * @param i19Imm The signed immediate value, multiplied by 4 regardless
3150 * of access size.
3151 */
3152DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
3153{
3154 Assert(i19Imm >= -262144 && i19Imm < 262144);
3155 Assert(iReg < 32); /* 3 2 1 0 */
3156 /* 10987654321098765432109876543210 */
3157 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
3158 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
3159 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
3160 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
3161 | iReg;
3162}
3163
3164
3165typedef enum
3166{
3167 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
3168 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
3169 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
3170} ARMV8A64INSTRMOVWIDE;
3171
3172/**
3173 * A64: Encode a move wide immediate instruction.
3174 *
3175 * @returns The encoded instruction.
3176 * @param enmType The load instruction type.
3177 * @param iRegDst The register to mov the immediate into.
3178 * @param uImm16 The immediate value.
3179 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
3180 * half-words to target:
3181 * - 0 for bits 15:00,
3182 * - 1 for bits 31:16,
3183 * - 2 for bits 47:32 (f64Bit=true only),
3184 * - 3 for bits 63:48 (f64Bit=true only).
3185 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
3186 */
3187DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
3188 uint32_t iHalfWord = 0, bool f64Bit = true)
3189{
3190 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
3191 return ((uint32_t)f64Bit << 31)
3192 | ((uint32_t)enmType << 29)
3193 | UINT32_C(0x12800000)
3194 | (iHalfWord << 21)
3195 | (uImm16 << 5)
3196 | iRegDst;
3197}
3198
3199/** A64: Encodes a MOVN instruction.
3200 * @see Armv8A64MkInstrMovWide for parameter details. */
3201DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3202{
3203 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
3204}
3205
3206/** A64: Encodes a MOVZ instruction.
3207 * @see Armv8A64MkInstrMovWide for parameter details. */
3208DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3209{
3210 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
3211}
3212
3213/** A64: Encodes a MOVK instruction.
3214 * @see Armv8A64MkInstrMovWide for parameter details. */
3215DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3216{
3217 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
3218}
3219
3220
3221typedef enum
3222{
3223 kArmv8A64InstrShift_Lsl = 0,
3224 kArmv8A64InstrShift_Lsr,
3225 kArmv8A64InstrShift_Asr,
3226 kArmv8A64InstrShift_Ror
3227} ARMV8A64INSTRSHIFT;
3228
3229
3230/**
3231 * A64: Encodes a logical instruction with a shifted 2nd register operand.
3232 *
3233 * @returns The encoded instruction.
3234 * @param u2Opc The logical operation to perform.
3235 * @param fNot Whether to complement the 2nd operand.
3236 * @param iRegResult The output register.
3237 * @param iReg1 The 1st register operand.
3238 * @param iReg2Shifted The 2nd register operand, to which the optional
3239 * shifting is applied.
3240 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
3241 * GPRs.
3242 * @param offShift6 The shift amount (default: none).
3243 * @param enmShift The shift operation (default: LSL).
3244 */
3245DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
3246 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
3247 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
3248{
3249 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
3250 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
3251 return ((uint32_t)f64Bit << 31)
3252 | (u2Opc << 29)
3253 | UINT32_C(0x0a000000)
3254 | ((uint32_t)enmShift << 22)
3255 | ((uint32_t)fNot << 21)
3256 | (iReg2Shifted << 16)
3257 | (offShift6 << 10)
3258 | (iReg1 << 5)
3259 | iRegResult;
3260}
3261
3262
3263/** A64: Encodes an AND instruction.
3264 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3265DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3266 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3267{
3268 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3269}
3270
3271
3272/** A64: Encodes an BIC instruction.
3273 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3274DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3275 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3276{
3277 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3278}
3279
3280
3281/** A64: Encodes an ORR instruction.
3282 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3283DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3284 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3285{
3286 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3287}
3288
3289
3290/** A64: Encodes an MOV instruction.
3291 * This is an alias for "orr dst, xzr, src". */
3292DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
3293{
3294 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
3295}
3296
3297
3298/** A64: Encodes an ORN instruction.
3299 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3300DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3301 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3302{
3303 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3304}
3305
3306
3307/** A64: Encodes an EOR instruction.
3308 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3309DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3310 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3311{
3312 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3313}
3314
3315
3316/** A64: Encodes an EON instruction.
3317 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3318DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3319 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3320{
3321 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3322}
3323
3324
3325/** A64: Encodes an ANDS instruction.
3326 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3327DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3328 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3329{
3330 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3331}
3332
3333
3334/** A64: Encodes an BICS instruction.
3335 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3336DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3337 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3338{
3339 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3340}
3341
3342
3343
3344/*
3345 * Data processing instructions with two source register operands.
3346 */
3347
3348
3349/** A64: Encodes an SUBP instruction. */
3350DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3351{
3352 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3353 return UINT32_C(0x80000000)
3354 | UINT32_C(0x1ac00000)
3355 | (UINT32_C(0) << 10)
3356 | (iRegSubtrahend << 16)
3357 | (iRegMinuend << 5)
3358 | iRegResult;
3359}
3360
3361
3362/** A64: Encodes an SUBPS instruction. */
3363DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3364{
3365 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3366 return UINT32_C(0x80000000)
3367 | UINT32_C(0x20000000)
3368 | UINT32_C(0x1ac00000)
3369 | (UINT32_C(0) << 10)
3370 | (iRegSubtrahend << 16)
3371 | (iRegMinuend << 5)
3372 | iRegResult;
3373}
3374
3375
3376/** A64: Encodes an UDIV instruction. */
3377DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3378{
3379 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3380 return ((uint32_t)f64Bit << 31)
3381 | UINT32_C(0x1ac00000)
3382 | (UINT32_C(2) << 10)
3383 | (iRegDivisor << 16)
3384 | (iRegDividend << 5)
3385 | iRegResult;
3386}
3387
3388
3389/** A64: Encodes an SDIV instruction. */
3390DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3391{
3392 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3393 return ((uint32_t)f64Bit << 31)
3394 | UINT32_C(0x1ac00000)
3395 | (UINT32_C(3) << 10)
3396 | (iRegDivisor << 16)
3397 | (iRegDividend << 5)
3398 | iRegResult;
3399}
3400
3401
3402/** A64: Encodes an IRG instruction. */
3403DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3404{
3405 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3406 return UINT32_C(0x80000000)
3407 | UINT32_C(0x1ac00000)
3408 | (UINT32_C(4) << 10)
3409 | (iRegSrc2 << 16)
3410 | (iRegSrc1 << 5)
3411 | iRegResult;
3412}
3413
3414
3415/** A64: Encodes a GMI instruction. */
3416DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3417{
3418 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3419 return UINT32_C(0x80000000)
3420 | UINT32_C(0x1ac00000)
3421 | (UINT32_C(5) << 10)
3422 | (iRegSrc2 << 16)
3423 | (iRegSrc1 << 5)
3424 | iRegResult;
3425}
3426
3427
3428/** A64: Encodes an LSLV instruction. */
3429DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3430{
3431 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3432 return ((uint32_t)f64Bit << 31)
3433 | UINT32_C(0x1ac00000)
3434 | (UINT32_C(8) << 10)
3435 | (iRegCount << 16)
3436 | (iRegSrc << 5)
3437 | iRegResult;
3438}
3439
3440
3441/** A64: Encodes an LSRV instruction. */
3442DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3443{
3444 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3445 return ((uint32_t)f64Bit << 31)
3446 | UINT32_C(0x1ac00000)
3447 | (UINT32_C(9) << 10)
3448 | (iRegCount << 16)
3449 | (iRegSrc << 5)
3450 | iRegResult;
3451}
3452
3453
3454/** A64: Encodes an ASRV instruction. */
3455DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3456{
3457 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3458 return ((uint32_t)f64Bit << 31)
3459 | UINT32_C(0x1ac00000)
3460 | (UINT32_C(10) << 10)
3461 | (iRegCount << 16)
3462 | (iRegSrc << 5)
3463 | iRegResult;
3464}
3465
3466
3467/** A64: Encodes a RORV instruction. */
3468DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3469{
3470 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3471 return ((uint32_t)f64Bit << 31)
3472 | UINT32_C(0x1ac00000)
3473 | (UINT32_C(11) << 10)
3474 | (iRegCount << 16)
3475 | (iRegSrc << 5)
3476 | iRegResult;
3477}
3478
3479
3480/** A64: Encodes a PACGA instruction. */
3481DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3482{
3483 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3484 return UINT32_C(0x80000000)
3485 | UINT32_C(0x1ac00000)
3486 | (UINT32_C(12) << 10)
3487 | (iRegSrc2 << 16)
3488 | (iRegSrc1 << 5)
3489 | iRegResult;
3490}
3491
3492
3493/** A64: Encodes a CRC32* instruction. */
3494DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3495{
3496 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3497 return ((uint32_t)(uSize == 3) << 31)
3498 | UINT32_C(0x1ac00000)
3499 | (UINT32_C(16) << 10)
3500 | (uSize << 10)
3501 | (iRegValue << 16)
3502 | (iRegCrc << 5)
3503 | iRegResult;
3504}
3505
3506
3507/** A64: Encodes a CRC32B instruction. */
3508DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3509{
3510 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
3511}
3512
3513
3514/** A64: Encodes a CRC32H instruction. */
3515DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3516{
3517 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
3518}
3519
3520
3521/** A64: Encodes a CRC32W instruction. */
3522DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3523{
3524 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
3525}
3526
3527
3528/** A64: Encodes a CRC32X instruction. */
3529DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3530{
3531 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
3532}
3533
3534
3535/** A64: Encodes a CRC32C* instruction. */
3536DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3537{
3538 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3539 return ((uint32_t)(uSize == 3) << 31)
3540 | UINT32_C(0x1ac00000)
3541 | (UINT32_C(20) << 10)
3542 | (uSize << 10)
3543 | (iRegValue << 16)
3544 | (iRegCrc << 5)
3545 | iRegResult;
3546}
3547
3548
3549/** A64: Encodes a CRC32B instruction. */
3550DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3551{
3552 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
3553}
3554
3555
3556/** A64: Encodes a CRC32CH instruction. */
3557DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3558{
3559 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
3560}
3561
3562
3563/** A64: Encodes a CRC32CW instruction. */
3564DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3565{
3566 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
3567}
3568
3569
3570/** A64: Encodes a CRC32CX instruction. */
3571DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3572{
3573 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
3574}
3575
3576
3577/** A64: Encodes an SMAX instruction. */
3578DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3579{
3580 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3581 return ((uint32_t)f64Bit << 31)
3582 | UINT32_C(0x1ac00000)
3583 | (UINT32_C(24) << 10)
3584 | (iRegSrc2 << 16)
3585 | (iRegSrc1 << 5)
3586 | iRegResult;
3587}
3588
3589
3590/** A64: Encodes an UMAX instruction. */
3591DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3592{
3593 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3594 return ((uint32_t)f64Bit << 31)
3595 | UINT32_C(0x1ac00000)
3596 | (UINT32_C(25) << 10)
3597 | (iRegSrc2 << 16)
3598 | (iRegSrc1 << 5)
3599 | iRegResult;
3600}
3601
3602
3603/** A64: Encodes an SMIN instruction. */
3604DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3605{
3606 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3607 return ((uint32_t)f64Bit << 31)
3608 | UINT32_C(0x1ac00000)
3609 | (UINT32_C(26) << 10)
3610 | (iRegSrc2 << 16)
3611 | (iRegSrc1 << 5)
3612 | iRegResult;
3613}
3614
3615
3616/** A64: Encodes an UMIN instruction. */
3617DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3618{
3619 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3620 return ((uint32_t)f64Bit << 31)
3621 | UINT32_C(0x1ac00000)
3622 | (UINT32_C(27) << 10)
3623 | (iRegSrc2 << 16)
3624 | (iRegSrc1 << 5)
3625 | iRegResult;
3626}
3627
3628
3629# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
3630
3631/**
3632 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
3633 *
3634 * @returns The decoded mask.
3635 * @param uImm6SizeLen The immS value from the instruction. (No N part
3636 * here, as that must be zero for instructions
3637 * operating on 32-bit wide registers.)
3638 * @param uImm6Rotations The immR value from the instruction.
3639 */
3640DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3641{
3642 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
3643
3644 /* Determine the element size. */
3645 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
3646 Assert(cBitsElementLog2 + 1U != 0U);
3647
3648 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3649 Assert(uImm6Rotations < cBitsElement);
3650
3651 /* Extract the number of bits set to 1: */
3652 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
3653 Assert(cBitsSetTo1 < cBitsElement);
3654 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
3655
3656 /* Produce the unrotated pattern. */
3657 static const uint32_t s_auReplicate[]
3658 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3659 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3660
3661 /* Rotate it and return. */
3662 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
3663}
3664
3665
3666/**
3667 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
3668 *
3669 * @returns The decoded mask.
3670 * @param uImm7SizeLen The N:immS value from the instruction.
3671 * @param uImm6Rotations The immR value from the instruction.
3672 */
3673DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
3674{
3675 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
3676
3677 /* Determine the element size. */
3678 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
3679 Assert(cBitsElementLog2 + 1U != 0U);
3680
3681 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3682 Assert(uImm6Rotations < cBitsElement);
3683
3684 /* Extract the number of bits set to 1: */
3685 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
3686 Assert(cBitsSetTo1 < cBitsElement);
3687 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
3688
3689 /* Produce the unrotated pattern. */
3690 static const uint64_t s_auReplicate[]
3691 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3692 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3693
3694 /* Rotate it and return. */
3695 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
3696}
3697
3698
3699/**
3700 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
3701 * the immS value.
3702 */
3703DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3704{
3705 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
3706}
3707
3708
3709/**
3710 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3711 * 32-bit bitmask to a set of immediates for those instructions.
3712 *
3713 * @returns true if successful, false if not.
3714 * @param fMask The mask value to convert.
3715 * @param puImm6SizeLen Where to return the immS part (N is always zero for
3716 * 32-bit wide masks).
3717 * @param puImm6Rotations Where to return the immR.
3718 */
3719DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
3720{
3721 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
3722 if ((uint32_t)(fMask + 1U) <= 1)
3723 return false;
3724
3725 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3726 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
3727 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
3728 if (cRor)
3729 fMask = ASMRotateRightU32(fMask, cRor);
3730 else
3731 fMask = ASMRotateLeftU32(fMask, cRol);
3732 Assert(fMask & RT_BIT_32(0));
3733 Assert(!(fMask & RT_BIT_32(31)));
3734
3735 /* Count the trailing ones and leading zeros. */
3736 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
3737 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
3738
3739 /* The potential element length is then the sum of the two above. */
3740 unsigned const cBitsElement = cOnes + cZeros;
3741 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3742 return false;
3743
3744 /* Special case: 32 bits element size. Since we're done here. */
3745 if (cBitsElement == 32)
3746 *puImm6SizeLen = cOnes - 1;
3747 else
3748 {
3749 /* Extract the element bits and check that these are replicated in the whole pattern. */
3750 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
3751 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
3752
3753 static const uint32_t s_auReplicate[]
3754 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3755 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3756 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3757 else
3758 return false;
3759 }
3760 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3761
3762 return true;
3763}
3764
3765
3766/**
3767 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3768 * 64-bit bitmask to a set of immediates for those instructions.
3769 *
3770 * @returns true if successful, false if not.
3771 * @param fMask The mask value to convert.
3772 * @param puImm7SizeLen Where to return the N:immS part.
3773 * @param puImm6Rotations Where to return the immR.
3774 */
3775DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
3776{
3777 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
3778 if ((uint64_t)(fMask + 1U) <= 1)
3779 return false;
3780
3781 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3782 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
3783 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
3784 if (cRor)
3785 fMask = ASMRotateRightU64(fMask, cRor);
3786 else
3787 fMask = ASMRotateLeftU64(fMask, cRol);
3788 Assert(fMask & RT_BIT_64(0));
3789 Assert(!(fMask & RT_BIT_64(63)));
3790
3791 /* Count the trailing ones and leading zeros. */
3792 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
3793 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
3794
3795 /* The potential element length is then the sum of the two above. */
3796 unsigned const cBitsElement = cOnes + cZeros;
3797 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3798 return false;
3799
3800 /* Special case: 64 bits element size. Since we're done here. */
3801 if (cBitsElement == 64)
3802 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
3803 else
3804 {
3805 /* Extract the element bits and check that these are replicated in the whole pattern. */
3806 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
3807 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
3808
3809 static const uint64_t s_auReplicate[]
3810 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3811 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3812 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3813 else
3814 return false;
3815 }
3816 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3817
3818 return true;
3819}
3820
3821# endif /* IPRT_INCLUDED_asm_h */
3822
3823/**
3824 * A64: Encodes a logical instruction with an complicated immediate mask.
3825 *
3826 * The @a uImm7SizeLen parameter specifies two things:
3827 * 1. the element size and
3828 * 2. the number of bits set to 1 in the pattern.
3829 *
3830 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
3831 * top) and using the position of the first bit set as a power of two.
3832 *
3833 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
3834 * |---|---|---|---|---|---|---|--------------|
3835 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
3836 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
3837 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
3838 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
3839 * | 0 | 0 | x | x | x | x | x | 32 bits |
3840 * | 1 | x | x | x | x | x | x | 64 bits |
3841 *
3842 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
3843 * there is always one zero bit in the pattern).
3844 *
3845 * The @a uImm6Rotations parameter specifies how many bits to the right,
3846 * the element pattern is rotated. The rotation count must be less than the
3847 * element bit count (size).
3848 *
3849 * @returns The encoded instruction.
3850 * @param u2Opc The logical operation to perform.
3851 * @param iRegResult The output register.
3852 * @param iRegSrc The 1st register operand.
3853 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
3854 * field at the top of the 6-bit 'imms' field.
3855 *
3856 * @param uImm6Rotations The rotation count.
3857 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3858 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3859 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3860 */
3861DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3862 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
3863{
3864 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x3f)));
3865 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
3866 return ((uint32_t)f64Bit << 31)
3867 | (u2Opc << 29)
3868 | UINT32_C(0x12000000)
3869 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
3870 | (uImm6Rotations << 16)
3871 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
3872 | (iRegSrc << 5)
3873 | iRegResult;
3874}
3875
3876
3877/** A64: Encodes an AND instruction w/ complicated immediate mask.
3878 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3879DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
3880 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3881{
3882 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3883}
3884
3885
3886/** A64: Encodes an ORR instruction w/ complicated immediate mask.
3887 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3888DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
3889 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3890{
3891 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3892}
3893
3894
3895/** A64: Encodes an EOR instruction w/ complicated immediate mask.
3896 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3897DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
3898 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3899{
3900 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3901}
3902
3903
3904/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
3905 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3906DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
3907 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3908{
3909 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3910}
3911
3912
3913/** A64: Encodes an TST instruction w/ complicated immediate mask.
3914 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3915DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
3916 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3917{
3918 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3919}
3920
3921
3922/**
3923 * A64: Encodes a bitfield instruction.
3924 *
3925 * @returns The encoded instruction.
3926 * @param u2Opc The bitfield operation to perform.
3927 * @param iRegResult The output register.
3928 * @param iRegSrc The 1st register operand.
3929 * @param cImm6Ror The right rotation count.
3930 * @param uImm6S The leftmost bit to be moved.
3931 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3932 * @param uN1 This must match @a f64Bit for all instructions
3933 * currently specified.
3934 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3935 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3936 */
3937DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3938 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
3939{
3940 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
3941 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
3942 return ((uint32_t)f64Bit << 31)
3943 | (u2Opc << 29)
3944 | UINT32_C(0x13000000)
3945 | (uN1 << 22)
3946 | (cImm6Ror << 16)
3947 | (uImm6S << 10)
3948 | (iRegSrc << 5)
3949 | iRegResult;
3950}
3951
3952
3953/** A64: Encodes a SBFM instruction.
3954 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3955DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3956 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3957{
3958 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3959}
3960
3961
3962/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
3963 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3964DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3965{
3966 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
3967}
3968
3969
3970/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
3971 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3972DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3973{
3974 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
3975}
3976
3977
3978/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
3979 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3980DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
3981{
3982 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
3983}
3984
3985
3986/** A64: Encodes an ASR instruction w/ immediate shift value.
3987 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3988DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3989{
3990 uint32_t const cWidth = f64Bit ? 63 : 31;
3991 Assert(cShift > 0); Assert(cShift <= cWidth);
3992 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
3993}
3994
3995
3996/** A64: Encodes a BFM instruction.
3997 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3998DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3999 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4000{
4001 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4002}
4003
4004
4005/** A64: Encodes a BFI instruction (insert).
4006 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4007DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
4008 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4009{
4010 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4011 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
4012 cBitsWidth - 1, f64Bit);
4013}
4014
4015
4016/** A64: Encodes a BFC instruction (clear).
4017 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4018DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfc(uint32_t iRegResult,
4019 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4020{
4021 return Armv8A64MkInstrBfi(iRegResult, ARMV8_A64_REG_XZR, offFirstBit, cBitsWidth, f64Bit);
4022}
4023
4024
4025/** A64: Encodes a BFXIL instruction (insert low).
4026 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4027DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfxil(uint32_t iRegResult, uint32_t iRegSrc,
4028 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4029{
4030 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4031 Assert(offFirstBit + cBitsWidth <= (f64Bit ? 64U : 32U));
4032 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4033}
4034
4035
4036/** A64: Encodes an UBFM instruction.
4037 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4038DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4039 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4040{
4041 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4042}
4043
4044
4045/** A64: Encodes an UBFX instruction (zero extending extract).
4046 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4047DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
4048 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4049{
4050 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4051}
4052
4053
4054/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
4055 * shifted into destination).
4056 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4057DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
4058 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
4059{
4060 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
4061 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
4062}
4063
4064
4065/** A64: Encodes an LSL instruction w/ immediate shift value.
4066 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4067DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4068{
4069 uint32_t const cWidth = f64Bit ? 63 : 31;
4070 Assert(cShift > 0); Assert(cShift <= cWidth);
4071 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
4072 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
4073}
4074
4075
4076/** A64: Encodes an LSR instruction w/ immediate shift value.
4077 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4078DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4079{
4080 uint32_t const cWidth = f64Bit ? 63 : 31;
4081 Assert(cShift > 0); Assert(cShift <= cWidth);
4082 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
4083}
4084
4085
4086/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
4087 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4088DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4089{
4090 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
4091}
4092
4093
4094/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
4095 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4096DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4097{
4098 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
4099}
4100
4101
4102/**
4103 * A64: Encodes an EXTR instruction with an immediate.
4104 *
4105 * @returns The encoded instruction.
4106 * @param iRegResult The register to store the result in. ZR is valid.
4107 * @param iRegLow The register holding the least significant bits in the
4108 * extraction. ZR is valid.
4109 * @param iRegHigh The register holding the most significant bits in the
4110 * extraction. ZR is valid.
4111 * @param uLsb The bit number of the least significant bit, or where in
4112 * @a iRegLow to start the
4113 * extraction.
4114 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4115 */
4116DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
4117 bool f64Bit = true)
4118{
4119 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
4120 return ((uint32_t)f64Bit << 31)
4121 | UINT32_C(0x13800000)
4122 | ((uint32_t)f64Bit << 22) /*N*/
4123 | (iRegHigh << 16)
4124 | (uLsb << 10)
4125 | (iRegLow << 5)
4126 | iRegResult;
4127}
4128
4129
4130/** A64: Rotates the value of a register (alias for EXTR). */
4131DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4132{
4133 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
4134}
4135
4136
4137/**
4138 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
4139 *
4140 * @returns The encoded instruction.
4141 * @param fSub true for sub and subs, false for add and
4142 * adds.
4143 * @param iRegResult The register to store the result in.
4144 * SP is valid when @a fSetFlags = false,
4145 * and ZR is valid otherwise.
4146 * @param iRegSrc The register containing the augend (@a fSub
4147 * = false) or minuend (@a fSub = true). SP is
4148 * a valid registers for all variations.
4149 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
4150 * (@a fSub = true).
4151 * @param f64Bit true for 64-bit GRPs (default), false for
4152 * 32-bit GPRs.
4153 * @param fSetFlags Whether to set flags (adds / subs) or not
4154 * (add / sub - default).
4155 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
4156 * bits to the left, or not (default).
4157 */
4158DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
4159 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
4160 bool fSetFlags = false, bool fShift12 = false)
4161{
4162 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
4163 return ((uint32_t)f64Bit << 31)
4164 | ((uint32_t)fSub << 30)
4165 | ((uint32_t)fSetFlags << 29)
4166 | UINT32_C(0x11000000)
4167 | ((uint32_t)fShift12 << 22)
4168 | (uImm12AddendSubtrahend << 10)
4169 | (iRegSrc << 5)
4170 | iRegResult;
4171}
4172
4173
4174/** Alias for sub zxr, reg, \#uimm12. */
4175DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
4176 bool f64Bit = true, bool fShift12 = false)
4177{
4178 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
4179 f64Bit, true /*fSetFlags*/, fShift12);
4180}
4181
4182
4183/** ADD dst, src, \#uimm12 */
4184DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
4185 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4186{
4187 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
4188}
4189
4190
4191/** SUB dst, src, \#uimm12 */
4192DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
4193 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4194{
4195 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
4196}
4197
4198
4199/**
4200 * A64: Encodes either add, adds, sub or subs with shifted register.
4201 *
4202 * @returns The encoded instruction.
4203 * @param fSub true for sub and subs, false for add and
4204 * adds.
4205 * @param iRegResult The register to store the result in.
4206 * SP is NOT valid, but ZR is.
4207 * @param iRegSrc1 The register containing the augend (@a fSub
4208 * = false) or minuend (@a fSub = true).
4209 * SP is NOT valid, but ZR is.
4210 * @param iRegSrc2 The register containing the addened (@a fSub
4211 * = false) or subtrahend (@a fSub = true).
4212 * SP is NOT valid, but ZR is.
4213 * @param f64Bit true for 64-bit GRPs (default), false for
4214 * 32-bit GPRs.
4215 * @param fSetFlags Whether to set flags (adds / subs) or not
4216 * (add / sub - default).
4217 * @param cShift The shift count to apply to @a iRegSrc2.
4218 * @param enmShift The shift type to apply to the @a iRegSrc2
4219 * register. kArmv8A64InstrShift_Ror is
4220 * reserved.
4221 */
4222DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4223 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4224 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4225{
4226 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4227 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
4228
4229 return ((uint32_t)f64Bit << 31)
4230 | ((uint32_t)fSub << 30)
4231 | ((uint32_t)fSetFlags << 29)
4232 | UINT32_C(0x0b000000)
4233 | ((uint32_t)enmShift << 22)
4234 | (iRegSrc2 << 16)
4235 | (cShift << 10)
4236 | (iRegSrc1 << 5)
4237 | iRegResult;
4238}
4239
4240
4241/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
4242DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
4243 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4244{
4245 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
4246 f64Bit, true /*fSetFlags*/, cShift, enmShift);
4247}
4248
4249
4250/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4251DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4252 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4253 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4254{
4255 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4256}
4257
4258
4259/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4260DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4261 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4262 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4263{
4264 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4265}
4266
4267
4268/** NEG dst */
4269DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
4270{
4271 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
4272}
4273
4274
4275/** Extension option for 'extended register' instructions. */
4276typedef enum ARMV8A64INSTREXTEND
4277{
4278 kArmv8A64InstrExtend_UxtB = 0,
4279 kArmv8A64InstrExtend_UxtH,
4280 kArmv8A64InstrExtend_UxtW,
4281 kArmv8A64InstrExtend_UxtX,
4282 kArmv8A64InstrExtend_SxtB,
4283 kArmv8A64InstrExtend_SxtH,
4284 kArmv8A64InstrExtend_SxtW,
4285 kArmv8A64InstrExtend_SxtX,
4286 /** The default is either UXTW or UXTX depending on whether the instruction
4287 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
4288 * to the f64Bit value. */
4289 kArmv8A64InstrExtend_Default
4290} ARMV8A64INSTREXTEND;
4291
4292
4293/**
4294 * A64: Encodes either add, adds, sub or subs with extended register encoding.
4295 *
4296 * @returns The encoded instruction.
4297 * @param fSub true for sub and subs, false for add and
4298 * adds.
4299 * @param iRegResult The register to store the result in.
4300 * SP is NOT valid, but ZR is.
4301 * @param iRegSrc1 The register containing the augend (@a fSub
4302 * = false) or minuend (@a fSub = true).
4303 * SP is valid, but ZR is NOT.
4304 * @param iRegSrc2 The register containing the addened (@a fSub
4305 * = false) or subtrahend (@a fSub = true).
4306 * SP is NOT valid, but ZR is.
4307 * @param f64Bit true for 64-bit GRPs (default), false for
4308 * 32-bit GPRs.
4309 * @param fSetFlags Whether to set flags (adds / subs) or not
4310 * (add / sub - default).
4311 * @param enmExtend The type of extension to apply to @a
4312 * iRegSrc2.
4313 * @param cShift The left shift count to apply to @a iRegSrc2
4314 * after enmExtend processing is done.
4315 * Max shift is 4 for some reason.
4316 */
4317DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4318 bool f64Bit = true, bool fSetFlags = false,
4319 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
4320 uint32_t cShift = 0)
4321{
4322 if (enmExtend == kArmv8A64InstrExtend_Default)
4323 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
4324 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
4325
4326 return ((uint32_t)f64Bit << 31)
4327 | ((uint32_t)fSub << 30)
4328 | ((uint32_t)fSetFlags << 29)
4329 | UINT32_C(0x0b200000)
4330 | (iRegSrc2 << 16)
4331 | ((uint32_t)enmExtend << 13)
4332 | (cShift << 10)
4333 | (iRegSrc1 << 5)
4334 | iRegResult;
4335}
4336
4337
4338/**
4339 * A64: Encodes either adc, adcs, sbc or sbcs with two source registers.
4340 *
4341 * @returns The encoded instruction.
4342 * @param fSub true for sbc and sbcs, false for adc and
4343 * adcs.
4344 * @param iRegResult The register to store the result in. SP is
4345 * NOT valid, but ZR is.
4346 * @param iRegSrc1 The register containing the augend (@a fSub
4347 * = false) or minuend (@a fSub = true).
4348 * SP is NOT valid, but ZR is.
4349 * @param iRegSrc2 The register containing the addened (@a fSub
4350 * = false) or subtrahend (@a fSub = true).
4351 * SP is NOT valid, but ZR is.
4352 * @param f64Bit true for 64-bit GRPs (default), false for
4353 * 32-bit GPRs.
4354 * @param fSetFlags Whether to set flags (adds / subs) or not
4355 * (add / sub - default).
4356 */
4357DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcSbc(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4358 bool f64Bit = true, bool fSetFlags = false)
4359{
4360 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4361
4362 return ((uint32_t)f64Bit << 31)
4363 | ((uint32_t)fSub << 30)
4364 | ((uint32_t)fSetFlags << 29)
4365 | UINT32_C(0x1a000000)
4366 | (iRegSrc2 << 16)
4367 | (iRegSrc1 << 5)
4368 | iRegResult;
4369}
4370
4371
4372/** ADC dst, reg1, reg2 */
4373DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4374 bool f64Bit = true, bool fSetFlags = false)
4375{
4376 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4377}
4378
4379
4380/** ADCS dst, reg1, reg2 */
4381DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4382{
4383 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4384}
4385
4386
4387/** SBC dst, reg1, reg2 */
4388DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4389 bool f64Bit = true, bool fSetFlags = false)
4390{
4391 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4392}
4393
4394
4395/** SBCS dst, reg1, reg2 */
4396DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4397{
4398 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4399}
4400
4401
4402/**
4403 * A64: Encodes a B (unconditional branch w/ imm) instruction.
4404 *
4405 * @returns The encoded instruction.
4406 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4407 */
4408DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
4409{
4410 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
4411 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
4412}
4413
4414
4415/**
4416 * A64: Encodes a BL (unconditional call w/ imm) instruction.
4417 *
4418 * @returns The encoded instruction.
4419 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4420 */
4421DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
4422{
4423 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
4424}
4425
4426
4427/**
4428 * A64: Encodes a BR (unconditional branch w/ register) instruction.
4429 *
4430 * @returns The encoded instruction.
4431 * @param iReg The register containing the target address.
4432 */
4433DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
4434{
4435 Assert(iReg < 32);
4436 return UINT32_C(0xd61f0000) | (iReg << 5);
4437}
4438
4439
4440/**
4441 * A64: Encodes a BLR instruction.
4442 *
4443 * @returns The encoded instruction.
4444 * @param iReg The register containing the target address.
4445 */
4446DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
4447{
4448 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
4449}
4450
4451
4452/**
4453 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
4454 *
4455 * @returns The encoded instruction.
4456 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4457 * its not zero.
4458 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4459 * @param iReg The GPR to check for zero / non-zero value.
4460 * @param f64Bit true for 64-bit register, false for 32-bit.
4461 */
4462DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4463{
4464 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
4465 return ((uint32_t)f64Bit << 31)
4466 | UINT32_C(0x34000000)
4467 | ((uint32_t)fJmpIfNotZero << 24)
4468 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4469 | iReg;
4470}
4471
4472
4473/** A64: Encodes the CBZ instructions. */
4474DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4475{
4476 return Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4477}
4478
4479
4480/** A64: Encodes the CBNZ instructions. */
4481DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbnz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4482{
4483 return Armv8A64MkInstrCbzCbnz(true /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4484}
4485
4486
4487/**
4488 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
4489 *
4490 * @returns The encoded instruction.
4491 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4492 * its not zero.
4493 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4494 * @param iReg The GPR to check for zero / non-zero value.
4495 * @param iBitNo The bit to test for.
4496 */
4497DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4498{
4499 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
4500 return ((uint32_t)(iBitNo & 0x20) << (31-5))
4501 | UINT32_C(0x36000000)
4502 | ((uint32_t)fJmpIfNotZero << 24)
4503 | ((iBitNo & 0x1f) << 19)
4504 | (((uint32_t)iImm14 & 0x3fff) << 5)
4505 | iReg;
4506}
4507
4508
4509/**
4510 * A64: Encodes TBZ (conditional branch w/ immediate) instructions.
4511 *
4512 * @returns The encoded instruction.
4513 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4514 * @param iReg The GPR to check for zero / non-zero value.
4515 * @param iBitNo The bit to test for.
4516 */
4517DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4518{
4519 return Armv8A64MkInstrTbzTbnz(false /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4520}
4521
4522
4523/**
4524 * A64: Encodes TBNZ (conditional branch w/ immediate) instructions.
4525 *
4526 * @returns The encoded instruction.
4527 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4528 * @param iReg The GPR to check for zero / non-zero value.
4529 * @param iBitNo The bit to test for.
4530 */
4531DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbnz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4532{
4533 return Armv8A64MkInstrTbzTbnz(true /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4534}
4535
4536
4537
4538/** Armv8 Condition codes. */
4539typedef enum ARMV8INSTRCOND
4540{
4541 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
4542 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
4543
4544 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
4545 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
4546 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
4547 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
4548
4549 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
4550 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
4551
4552 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
4553 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
4554
4555 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
4556 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
4557
4558 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
4559 kArmv8InstrCond_Lt, /**< b - Signed less than. */
4560
4561 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
4562 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
4563
4564 kArmv8InstrCond_Al, /**< e - Condition is always true. */
4565 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
4566} ARMV8INSTRCOND;
4567
4568/**
4569 * A64: Encodes conditional branch instruction w/ immediate target.
4570 *
4571 * @returns The encoded instruction.
4572 * @param enmCond The branch condition.
4573 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4574 */
4575DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
4576{
4577 Assert((unsigned)enmCond < 16);
4578 return UINT32_C(0x54000000)
4579 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4580 | (uint32_t)enmCond;
4581}
4582
4583
4584/**
4585 * A64: Encodes the BRK instruction.
4586 *
4587 * @returns The encoded instruction.
4588 * @param uImm16 Unsigned immediate value.
4589 */
4590DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
4591{
4592 Assert(uImm16 < _64K);
4593 return UINT32_C(0xd4200000)
4594 | (uImm16 << 5);
4595}
4596
4597/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
4598 * @{ */
4599#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
4600#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
4601#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
4602#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
4603#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
4604#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
4605#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
4606#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
4607
4608#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
4609#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
4610#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
4611#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
4612#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
4613#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
4614#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
4615#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
4616/** @} */
4617
4618/**
4619 * A64: Encodes CCMP or CCMN with two register operands.
4620 *
4621 * @returns The encoded instruction.
4622 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
4623 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
4624 * @param fNzcv The N, Z, C & V flags values to load if the condition
4625 * does not match. See RMA64_NZCV_F_XXX.
4626 * @param enmCond The condition guarding the compare.
4627 * @param fCCmp Set for CCMP (default), clear for CCMN.
4628 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4629 */
4630DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4631 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
4632{
4633 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
4634
4635 return ((uint32_t)f64Bit << 31)
4636 | ((uint32_t)fCCmp << 30)
4637 | UINT32_C(0x3a400000)
4638 | (iRegSrc2 << 16)
4639 | ((uint32_t)enmCond << 12)
4640 | (iRegSrc1 << 5)
4641 | fNzcv;
4642}
4643
4644/** CCMP w/ reg. */
4645DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4646 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4647{
4648 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4649}
4650
4651
4652/** CCMN w/ reg. */
4653DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4654 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4655{
4656 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4657}
4658
4659
4660/**
4661 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
4662 *
4663 * @returns The encoded instruction.
4664 * @param iRegSrc The register. SP is NOT valid, but ZR is.
4665 * @param uImm5 The immediate, to compare iRegSrc with.
4666 * @param fNzcv The N, Z, C & V flags values to load if the condition
4667 * does not match. See RMA64_NZCV_F_XXX.
4668 * @param enmCond The condition guarding the compare.
4669 * @param fCCmp Set for CCMP (default), clear for CCMN.
4670 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4671 */
4672DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
4673 bool fCCmp = true, bool f64Bit = true)
4674{
4675 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
4676
4677 return ((uint32_t)f64Bit << 31)
4678 | ((uint32_t)fCCmp << 30)
4679 | UINT32_C(0x3a400800)
4680 | (uImm5 << 16)
4681 | ((uint32_t)enmCond << 12)
4682 | (iRegSrc << 5)
4683 | fNzcv;
4684}
4685
4686/** CCMP w/ immediate. */
4687DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4688 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4689{
4690 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4691}
4692
4693
4694/** CCMN w/ immediate. */
4695DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4696 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4697{
4698 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4699}
4700
4701
4702/**
4703 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
4704 *
4705 * @returns The encoded instruction.
4706 * @param uOp Opcode bit 30.
4707 * @param uOp2 Opcode bits 11:10.
4708 * @param iRegResult The result register. SP is NOT valid, but ZR is.
4709 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
4710 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
4711 * @param enmCond The condition guarding the compare.
4712 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4713 */
4714DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
4715 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4716{
4717 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4718
4719 return ((uint32_t)f64Bit << 31)
4720 | (uOp << 30)
4721 | UINT32_C(0x1a800000)
4722 | (iRegSrc2 << 16)
4723 | ((uint32_t)enmCond << 12)
4724 | (uOp2 << 10)
4725 | (iRegSrc1 << 5)
4726 | iRegResult;
4727}
4728
4729
4730/** A64: Encodes CSEL.
4731 * @see Armv8A64MkInstrCondSelect for details. */
4732DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4733 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4734{
4735 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4736}
4737
4738
4739/** A64: Encodes CSINC.
4740 * @see Armv8A64MkInstrCondSelect for details. */
4741DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4742 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4743{
4744 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4745}
4746
4747
4748/** A64: Encodes CSET.
4749 * @see Armv8A64MkInstrCondSelect for details. */
4750DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4751{
4752 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4753 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4754 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4755}
4756
4757
4758/** A64: Encodes CSINV.
4759 * @see Armv8A64MkInstrCondSelect for details. */
4760DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4761 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4762{
4763 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4764}
4765
4766/** A64: Encodes CSETM.
4767 * @see Armv8A64MkInstrCondSelect for details. */
4768DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4769{
4770 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4771 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4772 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4773}
4774
4775
4776/** A64: Encodes CSNEG.
4777 * @see Armv8A64MkInstrCondSelect for details. */
4778DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4779 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4780{
4781 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4782}
4783
4784
4785/**
4786 * A64: Encodes REV instruction.
4787 *
4788 * @returns The encoded instruction.
4789 * @param iRegDst The destination register. SP is NOT valid.
4790 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4791 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4792 */
4793DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4794{
4795 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4796
4797 return ((uint32_t)f64Bit << 31)
4798 | UINT32_C(0x5ac00800)
4799 | ((uint32_t)f64Bit << 10)
4800 | (iRegSrc << 5)
4801 | iRegDst;
4802}
4803
4804
4805/**
4806 * A64: Encodes REV16 instruction.
4807 *
4808 * @returns The encoded instruction.
4809 * @param iRegDst The destination register. SP is NOT valid.
4810 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4811 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4812 */
4813DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4814{
4815 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4816
4817 return ((uint32_t)f64Bit << 31)
4818 | UINT32_C(0x5ac00400)
4819 | (iRegSrc << 5)
4820 | iRegDst;
4821}
4822
4823
4824/**
4825 * A64: Encodes SETF8 & SETF16.
4826 *
4827 * @returns The encoded instruction.
4828 * @param iRegResult The register holding the result. SP is NOT valid.
4829 * @param f16Bit Set for SETF16, clear for SETF8.
4830 */
4831DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
4832{
4833 Assert(iRegResult < 32);
4834
4835 return UINT32_C(0x3a00080d)
4836 | ((uint32_t)f16Bit << 14)
4837 | (iRegResult << 5);
4838}
4839
4840
4841/**
4842 * A64: Encodes RMIF.
4843 *
4844 * @returns The encoded instruction.
4845 * @param iRegSrc The source register to get flags from.
4846 * @param cRotateRight The right rotate count (LSB bit offset).
4847 * @param fMask Mask of which flag bits to set:
4848 * - bit 0: V
4849 * - bit 1: C
4850 * - bit 2: Z
4851 * - bit 3: N
4852 */
4853DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRmif(uint32_t iRegSrc, uint32_t cRotateRight, uint32_t fMask)
4854{
4855 Assert(iRegSrc < 32); Assert(cRotateRight < 64); Assert(fMask <= 0xf);
4856
4857 return UINT32_C(0xba000400)
4858 | (cRotateRight << 15)
4859 | (iRegSrc << 5)
4860 | fMask;
4861}
4862
4863
4864/**
4865 * A64: Encodes MRS (for reading a system register into a GPR).
4866 *
4867 * @returns The encoded instruction.
4868 * @param iRegDst The register to put the result into. SP is NOT valid.
4869 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4870 * IPRT specific format, of the register to read.
4871 */
4872DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
4873{
4874 Assert(iRegDst < 32);
4875 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4876
4877 /* Note. The top bit of idSysReg must always be set and is also set in
4878 0xd5300000, otherwise we'll be encoding a different instruction. */
4879 return UINT32_C(0xd5300000)
4880 | (idSysReg << 5)
4881 | iRegDst;
4882}
4883
4884
4885/**
4886 * A64: Encodes MSR (for writing a GPR to a system register).
4887 *
4888 * @returns The encoded instruction.
4889 * @param iRegSrc The register which value to write. SP is NOT valid.
4890 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4891 * IPRT specific format, of the register to write.
4892 */
4893DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
4894{
4895 Assert(iRegSrc < 32);
4896 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4897
4898 /* Note. The top bit of idSysReg must always be set and is also set in
4899 0xd5100000, otherwise we'll be encoding a different instruction. */
4900 return UINT32_C(0xd5100000)
4901 | (idSysReg << 5)
4902 | iRegSrc;
4903}
4904
4905
4906/** @} */
4907
4908
4909/** @defgroup grp_rt_armv8_mkinstr_vec Vector Instruction Encoding Helpers
4910 * @ingroup grp_rt_armv8_mkinstr
4911 *
4912 * A few inlined functions and macros for assisting in encoding common ARMv8
4913 * Neon/SIMD instructions.
4914 *
4915 * @{ */
4916
4917/** Armv8 vector logical operation. */
4918typedef enum
4919{
4920 kArmv8VecInstrLogicOp_And = 0, /**< AND */
4921 kArmv8VecInstrLogicOp_Bic = RT_BIT_32(22), /**< BIC */
4922 kArmv8VecInstrLogicOp_Orr = RT_BIT_32(23), /**< ORR */
4923 kArmv8VecInstrLogicOp_Orn = RT_BIT_32(23) | RT_BIT_32(22), /**< ORN */
4924 kArmv8VecInstrLogicOp_Eor = RT_BIT_32(29), /**< EOR */
4925 kArmv8VecInstrLogicOp_Bsl = RT_BIT_32(29) | RT_BIT_32(22), /**< BSL */
4926 kArmv8VecInstrLogicOp_Bit = RT_BIT_32(29) | RT_BIT_32(23), /**< BIT */
4927 kArmv8VecInstrLogicOp_Bif = RT_BIT_32(29) | RT_BIT_32(23) | RT_BIT_32(22) /**< BIF */
4928} ARMV8INSTRVECLOGICOP;
4929
4930
4931/**
4932 * A64: Encodes logical instruction (vector, register).
4933 *
4934 * @returns The encoded instruction.
4935 * @param enmOp The operation to encode.
4936 * @param iVecRegDst The vector register to put the result into.
4937 * @param iVecRegSrc1 The 1st source register.
4938 * @param iVecRegSrc2 The 2nd source register.
4939 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4940 * or just the low 64-bit (false).
4941 */
4942DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrLogical(ARMV8INSTRVECLOGICOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4943 bool f128Bit = true)
4944{
4945 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4946
4947 return UINT32_C(0x0e201c00)
4948 | (uint32_t)enmOp
4949 | ((uint32_t)f128Bit << 30)
4950 | (iVecRegSrc2 << 16)
4951 | (iVecRegSrc1 << 5)
4952 | iVecRegDst;
4953}
4954
4955
4956/**
4957 * A64: Encodes ORR (vector, register).
4958 *
4959 * @returns The encoded instruction.
4960 * @param iVecRegDst The vector register to put the result into.
4961 * @param iVecRegSrc1 The 1st source register.
4962 * @param iVecRegSrc2 The 2nd source register.
4963 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4964 * or just the low 64-bit (false).
4965 */
4966DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrOrr(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4967 bool f128Bit = true)
4968{
4969 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Orr, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
4970}
4971
4972
4973/**
4974 * A64: Encodes EOR (vector, register).
4975 *
4976 * @returns The encoded instruction.
4977 * @param iVecRegDst The vector register to put the result into.
4978 * @param iVecRegSrc1 The 1st source register.
4979 * @param iVecRegSrc2 The 2nd source register.
4980 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4981 * or just the low 64-bit (false).
4982 */
4983DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrEor(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4984 bool f128Bit = true)
4985{
4986 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Eor, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
4987}
4988
4989
4990/**
4991 * A64: Encodes AND (vector, register).
4992 *
4993 * @returns The encoded instruction.
4994 * @param iVecRegDst The vector register to put the result into.
4995 * @param iVecRegSrc1 The 1st source register.
4996 * @param iVecRegSrc2 The 2nd source register.
4997 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4998 * or just the low 64-bit (false).
4999 */
5000DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAnd(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5001 bool f128Bit = true)
5002{
5003 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_And, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5004}
5005
5006
5007/** Armv8 UMOV/INS vector element size. */
5008typedef enum ARMV8INSTRUMOVINSSZ
5009{
5010 kArmv8InstrUmovInsSz_U8 = 0, /**< Byte. */
5011 kArmv8InstrUmovInsSz_U16 = 1, /**< Halfword. */
5012 kArmv8InstrUmovInsSz_U32 = 2, /**< 32-bit. */
5013 kArmv8InstrUmovInsSz_U64 = 3 /**< 64-bit (only valid when the destination is a 64-bit register. */
5014} ARMV8INSTRUMOVINSSZ;
5015
5016
5017/**
5018 * A64: Encodes UMOV (vector, register).
5019 *
5020 * @returns The encoded instruction.
5021 * @param iRegDst The register to put the result into.
5022 * @param iVecRegSrc The vector source register.
5023 * @param idxElem The element index.
5024 * @param enmSz Element size of the source vector register.
5025 * @param fDst64Bit Flag whether the destination register is 64-bit (true) or 32-bit (false).
5026 */
5027DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUmov(uint32_t iRegDst, uint32_t iVecRegSrc, uint8_t idxElem,
5028 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64, bool fDst64Bit = true)
5029{
5030 Assert(iRegDst < 32); Assert(iVecRegSrc < 32);
5031 Assert((fDst64Bit && enmSz == kArmv8InstrUmovInsSz_U64) || (!fDst64Bit && enmSz != kArmv8InstrUmovInsSz_U64));
5032 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5033 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5034 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5035 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5036
5037 return UINT32_C(0x0e003c00)
5038 | ((uint32_t)fDst64Bit << 30)
5039 | ((uint32_t)idxElem << (16 + enmSz + 1))
5040 | (RT_BIT_32(enmSz) << 16)
5041 | (iVecRegSrc << 5)
5042 | iRegDst;
5043}
5044
5045
5046/**
5047 * A64: Encodes INS (vector, register).
5048 *
5049 * @returns The encoded instruction.
5050 * @param iVecRegDst The vector register to put the result into.
5051 * @param iRegSrc The source register.
5052 * @param idxElem The element index for the destination.
5053 * @param enmSz Element size of the source vector register.
5054 *
5055 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5056 */
5057DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrIns(uint32_t iVecRegDst, uint32_t iRegSrc, uint8_t idxElem,
5058 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64)
5059{
5060 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5061 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5062 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5063 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5064 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5065
5066 return UINT32_C(0x4e001c00)
5067 | ((uint32_t)idxElem << (16 + enmSz + 1))
5068 | (RT_BIT_32(enmSz) << 16)
5069 | (iRegSrc << 5)
5070 | iVecRegDst;
5071}
5072
5073
5074/**
5075 * A64: Encodes DUP (vector, register).
5076 *
5077 * @returns The encoded instruction.
5078 * @param iVecRegDst The vector register to put the result into.
5079 * @param iRegSrc The source register (ZR is valid).
5080 * @param enmSz Element size of the source vector register.
5081 * @param f128Bit Flag whether the instruction operates on the whole 128-bit of the vector register (true) or
5082 * just the low 64-bit (false).
5083 *
5084 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5085 */
5086DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrDup(uint32_t iVecRegDst, uint32_t iRegSrc, ARMV8INSTRUMOVINSSZ enmSz,
5087 bool f128Bit = true)
5088{
5089 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5090 Assert( (enmSz == kArmv8InstrUmovInsSz_U8)
5091 || (enmSz == kArmv8InstrUmovInsSz_U16)
5092 || (enmSz == kArmv8InstrUmovInsSz_U32)
5093 || (enmSz == kArmv8InstrUmovInsSz_U64));
5094
5095 return UINT32_C(0x0e000c00)
5096 | ((uint32_t)f128Bit << 30)
5097 | (RT_BIT_32(enmSz) << 16)
5098 | (iRegSrc << 5)
5099 | iVecRegDst;
5100}
5101
5102
5103/** Armv8 vector compare to zero vector element size. */
5104typedef enum ARMV8INSTRVECCMPZEROSZ
5105{
5106 kArmv8InstrCmpZeroSz_S8 = 0, /**< Byte. */
5107 kArmv8InstrCmpZeroSz_S16 = 1, /**< Halfword. */
5108 kArmv8InstrCmpZeroSz_S32 = 2, /**< 32-bit. */
5109 kArmv8InstrCmpZeroSz_S64 = 3 /**< 64-bit. */
5110} ARMV8INSTRVECCMPZEROSZ;
5111
5112
5113/** Armv8 vector compare to zero vector operation. */
5114typedef enum ARMV8INSTRVECCMPZEROOP
5115{
5116 kArmv8InstrCmpZeroOp_Gt = 0, /**< Greater than. */
5117 kArmv8InstrCmpZeroOp_Ge = RT_BIT_32(29), /**< Greater than or equal to. */
5118 kArmv8InstrCmpZeroOp_Eq = RT_BIT_32(12), /**< Equal to. */
5119 kArmv8InstrCmpZeroOp_Le = RT_BIT_32(29) | RT_BIT_32(12) /**< Lower than or equal to. */
5120} ARMV8INSTRVECCMPZEROOP;
5121
5122
5123/**
5124 * A64: Encodes CMGT, CMGE, CMEQ or CMLE against zero (vector, register).
5125 *
5126 * @returns The encoded instruction.
5127 * @param iVecRegDst The vector register to put the result into.
5128 * @param iVecRegSrc The vector source register.
5129 * @param enmSz Vector element size.
5130 * @param enmOp The compare operation against to encode.
5131 */
5132DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpToZero(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECCMPZEROSZ enmSz,
5133 ARMV8INSTRVECCMPZEROOP enmOp)
5134{
5135 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5136
5137 return UINT32_C(0x5e208800)
5138 | ((uint32_t)enmSz << 22)
5139 | (RT_BIT_32(enmSz) << 16)
5140 | (iVecRegSrc << 5)
5141 | iVecRegDst
5142 | (uint32_t)enmOp;
5143}
5144
5145
5146/**
5147 * A64: Encodes CNT (vector, register).
5148 *
5149 * @returns The encoded instruction.
5150 * @param iVecRegDst The vector register to put the result into.
5151 * @param iVecRegSrc The vector source register.
5152 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5153 * or just the low 64-bit (false).
5154 */
5155DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCnt(uint32_t iVecRegDst, uint32_t iVecRegSrc, bool f128Bit = true)
5156{
5157 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5158
5159 return UINT32_C(0x0e205800)
5160 | ((uint32_t)f128Bit << 30)
5161 | (iVecRegSrc << 5)
5162 | iVecRegDst;
5163}
5164
5165
5166/** Armv8 vector unsigned sum long across vector element size. */
5167typedef enum ARMV8INSTRVECUADDLVSZ
5168{
5169 kArmv8InstrUAddLVSz_8B = 0, /**< 8 x 8-bit. */
5170 kArmv8InstrUAddLVSz_16B = RT_BIT_32(30), /**< 16 x 8-bit. */
5171 kArmv8InstrUAddLVSz_4H = 1, /**< 4 x 16-bit. */
5172 kArmv8InstrUAddLVSz_8H = RT_BIT_32(30) | 1, /**< 8 x 16-bit. */
5173 kArmv8InstrUAddLVSz_4S = RT_BIT_32(30) | 2 /**< 4 x 32-bit. */
5174} ARMV8INSTRVECUADDLVSZ;
5175
5176
5177/**
5178 * A64: Encodes UADDLV (vector, register).
5179 *
5180 * @returns The encoded instruction.
5181 * @param iVecRegDst The vector register to put the result into.
5182 * @param iVecRegSrc The vector source register.
5183 * @param enmSz Element size.
5184 */
5185DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUAddLV(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECUADDLVSZ enmSz)
5186{
5187 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5188
5189 return UINT32_C(0x2e303800)
5190 | ((uint32_t)enmSz)
5191 | (iVecRegSrc << 5)
5192 | iVecRegDst;
5193}
5194
5195
5196/** Armv8 USHR/USRA/URSRA/SSHR/SRSA/SSHR vector element size. */
5197typedef enum ARMV8INSTRUSHIFTSZ
5198{
5199 kArmv8InstrShiftSz_U8 = 8, /**< Byte. */
5200 kArmv8InstrShiftSz_U16 = 16, /**< Halfword. */
5201 kArmv8InstrShiftSz_U32 = 32, /**< 32-bit. */
5202 kArmv8InstrShiftSz_U64 = 64 /**< 64-bit. */
5203} ARMV8INSTRUSHIFTSZ;
5204
5205/**
5206 * A64: Encodes USHR/USRA/URSRA/SSHR/SRSA/SSHR (vector, register).
5207 *
5208 * @returns The encoded instruction.
5209 * @param iVecRegDst The vector register to put the result into.
5210 * @param iVecRegSrc The vector source register.
5211 * @param cShift Number of bits to shift.
5212 * @param enmSz Element size.
5213 * @param fUnsigned Flag whether this a signed or unsigned shift,
5214 * @param fRound Flag whether this is the rounding shift variant.
5215 * @param fAccum Flag whether this is the accumulate shift variant.
5216 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5217 * or just the low 64-bit (false).
5218 */
5219DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShrImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5220 bool fUnsigned = true, bool fRound = false, bool fAccum = false, bool f128Bit = true)
5221{
5222 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5223 Assert( cShift >= 1
5224 && ( (enmSz == kArmv8InstrShiftSz_U8 && cShift <= 8)
5225 || (enmSz == kArmv8InstrShiftSz_U16 && cShift <= 16)
5226 || (enmSz == kArmv8InstrShiftSz_U32 && cShift <= 32)
5227 || (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
5228
5229 return UINT32_C(0x0f000400)
5230 | ((uint32_t)f128Bit << 30)
5231 | ((uint32_t)fUnsigned << 29)
5232 | ((((uint32_t)enmSz << 1) - cShift) << 16)
5233 | ((uint32_t)fRound << 13)
5234 | ((uint32_t)fAccum << 12)
5235 | (iVecRegSrc << 5)
5236 | iVecRegDst;
5237}
5238
5239
5240/**
5241 * A64: Encodes SHL (vector, register).
5242 *
5243 * @returns The encoded instruction.
5244 * @param iVecRegDst The vector register to put the result into.
5245 * @param iVecRegSrc The vector source register.
5246 * @param cShift Number of bits to shift.
5247 * @param enmSz Element size.
5248 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5249 * or just the low 64-bit (false).
5250 */
5251DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5252 bool f128Bit = true)
5253{
5254 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5255 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5256 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5257 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
5258 || (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
5259
5260 return UINT32_C(0x0f005400)
5261 | ((uint32_t)f128Bit << 30)
5262 | (((uint32_t)enmSz | cShift) << 16)
5263 | (iVecRegSrc << 5)
5264 | iVecRegDst;
5265}
5266
5267
5268/**
5269 * A64: Encodes SHLL/SHLL2/USHLL/USHLL2 (vector, register).
5270 *
5271 * @returns The encoded instruction.
5272 * @param iVecRegDst The vector register to put the result into.
5273 * @param iVecRegSrc The vector source register.
5274 * @param cShift Number of bits to shift.
5275 * @param enmSz Element size of the source vector register, the destination vector register
5276 * element size is twice as large, kArmv8InstrShiftSz_U64 is invalid.
5277 * @param fUnsigned Flag whether this is an unsigned shift left (true, default) or signed (false).
5278 * @param fUpper Flag whether this operates on the lower half (false, default) of the source vector register
5279 * or the upper half (true).
5280 */
5281DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUShll(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5282 bool fUnsigned = true, bool fUpper = false)
5283{
5284 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5285 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5286 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5287 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32));
5288
5289 return UINT32_C(0x0f00a400)
5290 | ((uint32_t)fUpper << 30)
5291 | ((uint32_t)fUnsigned << 29)
5292 | (((uint32_t)enmSz | cShift) << 16)
5293 | (iVecRegSrc << 5)
5294 | iVecRegDst;
5295}
5296
5297
5298/** Armv8 vector arith ops element size. */
5299typedef enum ARMV8INSTRVECARITHSZ
5300{
5301 kArmv8VecInstrArithSz_8 = 0, /**< 8-bit. */
5302 kArmv8VecInstrArithSz_16 = 1, /**< 16-bit. */
5303 kArmv8VecInstrArithSz_32 = 2, /**< 32-bit. */
5304 kArmv8VecInstrArithSz_64 = 3 /**< 64-bit. */
5305} ARMV8INSTRVECARITHSZ;
5306
5307
5308/** Armv8 vector arithmetic operation. */
5309typedef enum
5310{
5311 kArmv8VecInstrArithOp_Add = RT_BIT_32(15), /**< ADD */
5312 kArmv8VecInstrArithOp_Sub = RT_BIT_32(29) | RT_BIT_32(15), /**< SUB */
5313 kArmv8VecInstrArithOp_UnsignSat_Add = RT_BIT_32(29) | RT_BIT_32(11), /**< UQADD */
5314 kArmv8VecInstrArithOp_UnsignSat_Sub = RT_BIT_32(29) | RT_BIT_32(13) | RT_BIT_32(11), /**< UQSUB */
5315 kArmv8VecInstrArithOp_SignSat_Add = RT_BIT_32(11), /**< SQADD */
5316 kArmv8VecInstrArithOp_SignSat_Sub = RT_BIT_32(13) | RT_BIT_32(11), /**< SQSUB */
5317 kArmv8VecInstrArithOp_Mul = RT_BIT_32(15) | RT_BIT_32(12) | RT_BIT_32(11) /**< MUL */
5318} ARMV8INSTRVECARITHOP;
5319
5320
5321/**
5322 * A64: Encodes an arithmetic operation (vector, register).
5323 *
5324 * @returns The encoded instruction.
5325 * @param enmOp The operation to encode.
5326 * @param iVecRegDst The vector register to put the result into.
5327 * @param iVecRegSrc1 The first vector source register.
5328 * @param iVecRegSrc2 The second vector source register.
5329 * @param enmSz Element size.
5330 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5331 * or just the low 64-bit (false).
5332 */
5333DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrArithOp(ARMV8INSTRVECARITHOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5334 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5335{
5336 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5337
5338 return UINT32_C(0x0e200400)
5339 | (uint32_t)enmOp
5340 | ((uint32_t)f128Bit << 30)
5341 | ((uint32_t)enmSz << 22)
5342 | (iVecRegSrc2 << 16)
5343 | (iVecRegSrc1 << 5)
5344 | iVecRegDst;
5345}
5346
5347
5348/** Armv8 vector compare operation. */
5349typedef enum ARMV8VECINSTRCMPOP
5350{
5351 /* U insn[15:10] */
5352 kArmv8VecInstrCmpOp_Gt = UINT32_C(0x3400), /**< Greater than (>) (signed) */
5353 kArmv8VecInstrCmpOp_Ge = UINT32_C(0x3c00), /**< Greater or equal (>=) (signed) */
5354 kArmv8VecInstrCmpOp_Hi = RT_BIT_32(29) | UINT32_C(0x3400), /**< Greater than (>) (unsigned) */
5355 kArmv8VecInstrCmpOp_Hs = RT_BIT_32(29) | UINT32_C(0x3c00), /**< Greater or equal (>=) (unsigned) */
5356 kArmv8VecInstrCmpOp_Eq = RT_BIT_32(29) | UINT32_C(0x8c00) /**< Equal (==) (unsigned) */
5357} ARMV8VECINSTRCMPOP;
5358
5359/**
5360 * A64: Encodes CMEQ/CMGE/CMGT/CMHI/CMHS (register variant) (vector, register).
5361 *
5362 * @returns The encoded instruction.
5363 * @param enmOp The operation to perform.
5364 * @param iVecRegDst The vector register to put the result into.
5365 * @param iVecRegSrc1 The first vector source register.
5366 * @param iVecRegSrc2 The second vector source register.
5367 * @param enmSz Element size.
5368 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5369 * or just the low 64-bit (false).
5370 */
5371DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmp(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5372 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5373{
5374 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5375
5376 return UINT32_C(0x0e200000)
5377 | ((uint32_t)f128Bit << 30)
5378 | ((uint32_t)enmSz << 22)
5379 | (iVecRegSrc2 << 16)
5380 | ((uint32_t)enmOp)
5381 | (iVecRegSrc1 << 5)
5382 | iVecRegDst;
5383}
5384
5385
5386/** Armv8 vector compare against zero operation. */
5387typedef enum ARMV8VECINSTRCMPZEROOP
5388{
5389 /* U insn[15:10] */
5390 kArmv8VecInstrCmpZeroOp_Gt = UINT32_C(0x8800), /**< Greater than zero (>) (signed) */
5391 kArmv8VecInstrCmpZeroOp_Eq = UINT32_C(0x9800), /**< Equal to zero (==) */
5392 kArmv8VecInstrCmpZeroOp_Lt = UINT32_C(0xa800), /**< Lower than zero (>=) (signed) */
5393 kArmv8VecInstrCmpZeroOp_Ge = RT_BIT_32(29) | UINT32_C(0x8800), /**< Greater or equal to zero (>=) (signed) */
5394 kArmv8VecInstrCmpZeroOp_Le = RT_BIT_32(29) | UINT32_C(0x9800) /**< Lower or equal to zero (<=) (signed) */
5395} ARMV8VECINSTRCMPZEROOP;
5396
5397/**
5398 * A64: Encodes CMEQ/CMGE/CMGT/CMLE/CMLT (zero variant) (vector, register).
5399 *
5400 * @returns The encoded instruction.
5401 * @param enmOp The operation to perform.
5402 * @param iVecRegDst The vector register to put the result into.
5403 * @param iVecRegSrc The first vector source register.
5404 * @param enmSz Element size.
5405 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5406 * or just the low 64-bit (false).
5407 */
5408DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpAgainstZero(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc,
5409 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5410{
5411 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5412
5413 return UINT32_C(0x0e200000)
5414 | ((uint32_t)f128Bit << 30)
5415 | ((uint32_t)enmSz << 22)
5416 | ((uint32_t)enmOp)
5417 | (iVecRegSrc << 5)
5418 | iVecRegDst;
5419}
5420
5421
5422/** Armv8 [Signed,Unsigned] Extract {Unsigned} operation. */
5423typedef enum
5424{
5425 kArmv8VecInstrQxtnOp_Sqxtn = RT_BIT_32(14), /**< SQXTN */
5426 kArmv8VecInstrQxtnOp_Sqxtun = RT_BIT_32(29) | RT_BIT_32(13), /**< SQXTUN */
5427 kArmv8VecInstrQxtnOp_Uqxtn = RT_BIT_32(29) | RT_BIT_32(14) /**< UQXTN */
5428} ARMV8INSTRVECQXTNOP;
5429
5430/**
5431 * A64: Encodes SQXTN/SQXTN2/UQXTN/UQXTN2/SQXTUN/SQXTUN2 (vector, register).
5432 *
5433 * @returns The encoded instruction.
5434 * @param enmOp The operation to perform.
5435 * @param fUpper Flag whether to write the result to the lower (false) or upper (true) half of the destinatiom register.
5436 * @param iVecRegDst The vector register to put the result into.
5437 * @param iVecRegSrc The first vector source register.
5438 * @param enmSz Element size.
5439 */
5440DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrQxtn(ARMV8INSTRVECQXTNOP enmOp, bool fUpper, uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECARITHSZ enmSz)
5441{
5442 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5443
5444 return UINT32_C(0x0e210800)
5445 | ((uint32_t)enmOp)
5446 | ((uint32_t)fUpper << 30)
5447 | ((uint32_t)enmSz << 22)
5448 | (iVecRegSrc << 5)
5449 | iVecRegDst;
5450}
5451
5452
5453/** Armv8 floating point size. */
5454typedef enum
5455{
5456 kArmv8VecInstrFpSz_2x_Single = 0, /**< 2x single precision values in the low 64-bit of the 128-bit register. */
5457 kArmv8VecInstrFpSz_4x_Single = RT_BIT_32(30), /**< 4x single precision values in the 128-bit register. */
5458 kArmv8VecInstrFpSz_2x_Double = RT_BIT_32(30) | RT_BIT_32(22) /**< 2x double precision values in the 128-bit register. */
5459} ARMV8INSTRVECFPSZ;
5460
5461
5462/** Armv8 3 operand floating point operation. */
5463typedef enum
5464{
5465 /* insn[29] insn[23] insn[15:11] */
5466 kArmv8VecInstrFpOp_Add = UINT32_C(0xd000), /**< FADD */
5467 kArmv8VecInstrFpOp_Sub = RT_BIT_32(23) | UINT32_C(0xd000), /**< FADD */
5468 kArmv8VecInstrFpOp_AddPairwise = RT_BIT_32(29) | UINT32_C(0xd000), /**< FADDP */
5469 kArmv8VecInstrFpOp_Mul = RT_BIT_32(29) | UINT32_C(0xd800), /**< FMUL */
5470 kArmv8VecInstrFpOp_Div = RT_BIT_32(29) | UINT32_C(0xf800), /**< FDIV */
5471
5472 kArmv8VecInstrFpOp_Max = UINT32_C(0xf000), /**< FMAX */
5473 kArmv8VecInstrFpOp_MaxNumber = UINT32_C(0xc000), /**< FMAXNM */
5474 kArmv8VecInstrFpOp_MaxNumberPairwise = RT_BIT_32(29) | UINT32_C(0xc000), /**< FMAXNMP */
5475 kArmv8VecInstrFpOp_MaxPairwise = RT_BIT_32(29) | UINT32_C(0xf000), /**< FMAXP */
5476
5477 kArmv8VecInstrFpOp_Min = RT_BIT_32(23) | UINT32_C(0xf000), /**< FMIN */
5478 kArmv8VecInstrFpOp_MinNumber = RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNM */
5479 kArmv8VecInstrFpOp_MinNumberPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNMP */
5480 kArmv8VecInstrFpOp_MinPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xf000), /**< FMINP */
5481
5482 kArmv8VecInstrFpOp_Fmla = UINT32_C(0xc800), /**< FMLA */
5483 kArmv8VecInstrFpOp_Fmls = RT_BIT_32(23) | UINT32_C(0xc800) /**< FMLS */
5484} ARMV8INSTRVECFPOP;
5485
5486/**
5487 * A64: Encodes a 3 operand floating point operation (vector, register).
5488 *
5489 * @returns The encoded instruction.
5490 * @param enmOp The operation to perform.
5491 * @param enmSz The size to operate on.
5492 * @param iVecRegDst The vector register to put the result into.
5493 * @param iVecRegSrc1 The first vector source register.
5494 * @param iVecRegSrc2 The second vector source register.
5495 */
5496DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrFp3Op(ARMV8INSTRVECFPOP enmOp, ARMV8INSTRVECFPSZ enmSz, uint32_t iVecRegDst,
5497 uint32_t iVecRegSrc1, uint32_t iVecRegSrc2)
5498{
5499 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5500
5501 return UINT32_C(0x0e200400)
5502 | ((uint32_t)enmOp)
5503 | ((uint32_t)enmSz)
5504 | (iVecRegSrc2 << 16)
5505 | (iVecRegSrc1 << 5)
5506 | iVecRegDst;
5507}
5508
5509
5510/** @} */
5511
5512#endif /* !dtrace && __cplusplus */
5513
5514/** @} */
5515
5516#endif /* !IPRT_INCLUDED_armv8_h */
5517
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