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source: vbox/trunk/include/iprt/armv8.h@ 103606

Last change on this file since 103606 was 103606, checked in by vboxsync, 9 months ago

iprt/armv8.h: CSEL and friends. bugref:10376
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/types.h>
44# include <iprt/assert.h>
45#else
46# pragma D depends_on library vbox-types.d
47#endif
48
49/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
50 * @ingroup grp_rt
51 * @{
52 */
53
54/** @name The AArch64 register encoding - deprecated.
55 * @deprecated Use ARMV8_A64_REG_XXX instead.
56 * @todo correct code and drop these remaining ones.
57 * @{ */
58#define ARMV8_AARCH64_REG_X0 0
59#define ARMV8_AARCH64_REG_X1 1
60#define ARMV8_AARCH64_REG_X2 2
61#define ARMV8_AARCH64_REG_X3 3
62#define ARMV8_AARCH64_REG_ZR 31
63/** @} */
64
65/** @name The AArch64 general purpose register encoding.
66 * @{ */
67#define ARMV8_A64_REG_X0 0
68#define ARMV8_A64_REG_X1 1
69#define ARMV8_A64_REG_X2 2
70#define ARMV8_A64_REG_X3 3
71#define ARMV8_A64_REG_X4 4
72#define ARMV8_A64_REG_X5 5
73#define ARMV8_A64_REG_X6 6
74#define ARMV8_A64_REG_X7 7
75#define ARMV8_A64_REG_X8 8
76#define ARMV8_A64_REG_X9 9
77#define ARMV8_A64_REG_X10 10
78#define ARMV8_A64_REG_X11 11
79#define ARMV8_A64_REG_X12 12
80#define ARMV8_A64_REG_X13 13
81#define ARMV8_A64_REG_X14 14
82#define ARMV8_A64_REG_X15 15
83#define ARMV8_A64_REG_X16 16
84#define ARMV8_A64_REG_X17 17
85#define ARMV8_A64_REG_X18 18
86#define ARMV8_A64_REG_X19 19
87#define ARMV8_A64_REG_X20 20
88#define ARMV8_A64_REG_X21 21
89#define ARMV8_A64_REG_X22 22
90#define ARMV8_A64_REG_X23 23
91#define ARMV8_A64_REG_X24 24
92#define ARMV8_A64_REG_X25 25
93#define ARMV8_A64_REG_X26 26
94#define ARMV8_A64_REG_X27 27
95#define ARMV8_A64_REG_X28 28
96#define ARMV8_A64_REG_X29 29
97#define ARMV8_A64_REG_X30 30
98/** @} */
99
100/** @name The AArch64 32-bit general purpose register names.
101 * @{ */
102#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
103#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
104#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
105#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
106#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
107#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
108#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
109#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
110#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
111#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
112#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
113#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
114#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
115#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
116#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
117#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
118#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
119#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
120#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
121#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
122#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
123#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
124#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
125#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
126#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
127#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
128#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
129#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
130#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
131#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
132#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
133/** @} */
134
135/** @name The AArch64 register 31.
136 * @note Register 31 typically refers to the zero register, but can also in
137 * select case (by instruction and opecode field) refer the to stack
138 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
139 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
140 * 31 will be the zero register.
141 * @{ */
142/** The stack pointer. */
143#define ARMV8_A64_REG_SP 31
144/** The zero register. Reads as zero, writes ignored. */
145#define ARMV8_A64_REG_XZR 31
146/** The zero register, the 32-bit register name. */
147#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
148/** @} */
149
150/** @name AArch64 register aliases
151 * @{ */
152/** The link register is typically mapped to x30 as that's the default pick of
153 * the RET instruction. */
154#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
155/** Frame base pointer is typically mapped to x29. */
156#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
157/** @} */
158
159
160/** @name System register encoding.
161 * @{
162 */
163/** Mask for the op0 part of an MSR/MRS instruction */
164#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
165/** Shift for the op0 part of an MSR/MRS instruction */
166#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
167/** Returns the op0 part of the given MRS/MSR instruction. */
168#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
169/** Mask for the op1 part of an MSR/MRS instruction */
170#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
171/** Shift for the op1 part of an MSR/MRS instruction */
172#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
173/** Returns the op1 part of the given MRS/MSR instruction. */
174#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
175/** Mask for the CRn part of an MSR/MRS instruction */
176#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
177 | RT_BIT_32(15) )
178/** Shift for the CRn part of an MSR/MRS instruction */
179#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
180/** Returns the CRn part of the given MRS/MSR instruction. */
181#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
182/** Mask for the CRm part of an MSR/MRS instruction */
183#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
184 | RT_BIT_32(11) )
185/** Shift for the CRm part of an MSR/MRS instruction */
186#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
187/** Returns the CRn part of the given MRS/MSR instruction. */
188#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
189/** Mask for the op2 part of an MSR/MRS instruction */
190#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
191/** Shift for the op2 part of an MSR/MRS instruction */
192#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
193/** Returns the op2 part of the given MRS/MSR instruction. */
194#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
195/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
196#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
197 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
198 | ARMV8_AARCH64_SYSREG_OP2_MASK)
199/** @} */
200
201/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
202 * IPRT specific and not part of the ARMv8 specification.
203 * @{ */
204#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
205 UINT16_C( (((a_Op0) & 0x3) << 14) \
206 | (((a_Op1) & 0x7) << 11) \
207 | (((a_CRn) & 0xf) << 7) \
208 | (((a_CRm) & 0xf) << 3) \
209 | ((a_Op2) & 0x7))
210/** Returns the internal system register ID from the given MRS/MSR instruction. */
211#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
212 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
213 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
214 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
215 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
216 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
217/** Encodes the given system register ID in the given MSR/MRS instruction. */
218#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
219 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
220/** @} */
221
222
223/** @name System register IDs.
224 * @{ */
225/** OSLAR_EL1 register - WO. */
226#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
227/** OSLSR_EL1 register - RO. */
228#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
229/** OSDLR_EL1 register - RW. */
230#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
231
232/** MIDR_EL1 register - RO. */
233#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
234/** MIPDR_EL1 register - RO. */
235#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
236/** REVIDR_EL1 register - RO. */
237#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
238/** ID_PFR0_EL1 register - RO. */
239#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
240/** ID_PFR1_EL1 register - RO. */
241#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
242/** ID_DFR0_EL1 register - RO. */
243#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
244/** ID_AFR0_EL1 register - RO. */
245#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
246/** ID_MMFR0_EL1 register - RO. */
247#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
248/** ID_MMFR1_EL1 register - RO. */
249#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
250/** ID_MMFR2_EL1 register - RO. */
251#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
252/** ID_MMFR3_EL1 register - RO. */
253#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
254
255/** ID_ISAR0_EL1 register - RO. */
256#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
257/** ID_ISAR1_EL1 register - RO. */
258#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
259/** ID_ISAR2_EL1 register - RO. */
260#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
261/** ID_ISAR3_EL1 register - RO. */
262#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
263/** ID_ISAR4_EL1 register - RO. */
264#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
265/** ID_ISAR5_EL1 register - RO. */
266#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
267/** ID_MMFR4_EL1 register - RO. */
268#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
269/** ID_ISAR6_EL1 register - RO. */
270#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
271
272/** MVFR0_EL1 register - RO. */
273#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
274/** MVFR1_EL1 register - RO. */
275#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
276/** MVFR2_EL1 register - RO. */
277#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
278/** ID_PFR2_EL1 register - RO. */
279#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
280/** ID_DFR1_EL1 register - RO. */
281#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
282/** ID_MMFR5_EL1 register - RO. */
283#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
284
285/** ID_AA64PFR0_EL1 register - RO. */
286#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
287/** ID_AA64PFR0_EL1 register - RO. */
288#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
289/** ID_AA64ZFR0_EL1 register - RO. */
290#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
291/** ID_AA64SMFR0_EL1 register - RO. */
292#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
293
294/** ID_AA64DFR0_EL1 register - RO. */
295#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
296/** ID_AA64DFR0_EL1 register - RO. */
297#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
298/** ID_AA64AFR0_EL1 register - RO. */
299#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
300/** ID_AA64AFR1_EL1 register - RO. */
301#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
302
303/** ID_AA64ISAR0_EL1 register - RO. */
304#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
305/** ID_AA64ISAR1_EL1 register - RO. */
306#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
307/** ID_AA64ISAR2_EL1 register - RO. */
308#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
309
310/** ID_AA64MMFR0_EL1 register - RO. */
311#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
312/** ID_AA64MMFR1_EL1 register - RO. */
313#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
314/** ID_AA64MMFR2_EL1 register - RO. */
315#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
316
317/** SCTRL_EL1 register - RW. */
318#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
319/** ACTRL_EL1 register - RW. */
320#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
321/** CPACR_EL1 register - RW. */
322#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
323/** RGSR_EL1 register - RW. */
324#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
325/** GCR_EL1 register - RW. */
326#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
327
328/** ZCR_EL1 register - RW. */
329#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
330/** TRFCR_EL1 register - RW. */
331#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
332/** SMPRI_EL1 register - RW. */
333#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
334/** SMCR_EL1 register - RW. */
335#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
336
337/** TTBR0_EL1 register - RW. */
338#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
339/** TTBR1_EL1 register - RW. */
340#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
341/** TCR_EL1 register - RW. */
342#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
343
344/** @todo APIA,APIB,APDA,APDB,APGA registers. */
345
346/** SPSR_EL1 register - RW. */
347#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
348/** ELR_EL1 register - RW. */
349#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
350
351/** SP_EL0 register - RW. */
352#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
353
354/** PSTATE.SPSel value. */
355#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
356/** PSTATE.CurrentEL value. */
357#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
358/** PSTATE.PAN value. */
359#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
360/** PSTATE.UAO value. */
361#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
362
363/** PSTATE.ALLINT value. */
364#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
365
366/** ICC_PMR_EL1 register - RW. */
367#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
368
369/** AFSR0_EL1 register - RW. */
370#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
371/** AFSR1_EL1 register - RW. */
372#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
373
374/** ESR_EL1 register - RW. */
375#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
376
377/** ERRIDR_EL1 register - RO. */
378#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
379/** ERRSELR_EL1 register - RW. */
380#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
381
382/** ICC_IAR0_EL1 register - RO. */
383#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
384/** ICC_EOIR0_EL1 register - WO. */
385#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
386/** ICC_HPPIR0_EL1 register - WO. */
387#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
388/** ICC_BPR0_EL1 register - RW. */
389#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
390/** ICC_AP0R0_EL1 register - RW. */
391#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
392/** ICC_AP0R1_EL1 register - RW. */
393#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
394/** ICC_AP0R2_EL1 register - RW. */
395#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
396/** ICC_AP0R3_EL1 register - RW. */
397#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
398
399/** ICC_AP1R0_EL1 register - RW. */
400#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
401/** ICC_AP1R1_EL1 register - RW. */
402#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
403/** ICC_AP1R2_EL1 register - RW. */
404#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
405/** ICC_AP1R3_EL1 register - RW. */
406#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
407/** ICC_NMIAR1_EL1 register - RO. */
408#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
409
410/** ICC_DIR_EL1 register - WO. */
411#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
412/** ICC_RPR_EL1 register - RO. */
413#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
414/** ICC_SGI1R_EL1 register - WO. */
415#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
416/** ICC_ASGI1R_EL1 register - WO. */
417#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
418/** ICC_SGI0R_EL1 register - WO. */
419#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
420
421/** ICC_IAR1_EL1 register - RO. */
422#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
423/** ICC_EOIR1_EL1 register - WO. */
424#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
425/** ICC_HPPIR1_EL1 register - RO. */
426#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
427/** ICC_BPR1_EL1 register - RW. */
428#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
429/** ICC_CTLR_EL1 register - RW. */
430#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
431/** ICC_SRE_EL1 register - RW. */
432#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
433/** ICC_IGRPEN0_EL1 register - RW. */
434#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
435/** ICC_IGRPEN1_EL1 register - RW. */
436#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
437
438/** CNTV_CTL_EL0 register - RW. */
439#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
440/** @} */
441
442
443/**
444 * SPSR_EL2 (according to chapter C5.2.19)
445 */
446typedef union ARMV8SPSREL2
447{
448 /** The plain unsigned view. */
449 uint64_t u;
450 /** The 8-bit view. */
451 uint8_t au8[8];
452 /** The 16-bit view. */
453 uint16_t au16[4];
454 /** The 32-bit view. */
455 uint32_t au32[2];
456 /** The 64-bit view. */
457 uint64_t u64;
458} ARMV8SPSREL2;
459/** Pointer to SPSR_EL2. */
460typedef ARMV8SPSREL2 *PARMV8SPSREL2;
461/** Pointer to const SPSR_EL2. */
462typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
463
464
465/** @name SPSR_EL2 (When exception is taken from AArch64 state)
466 * @{
467 */
468/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
469#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
470#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
471/** Bit 0 - SP - Selected stack pointer. */
472#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
473#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
474/** Bit 1 - Reserved (read as zero). */
475#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
476/** Bit 2 - 3 - EL - Exception level. */
477#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
478#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
479#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
480#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
481/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
482#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
483#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
484/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
485#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
486#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
487/** Bit 6 - I - FIQ interrupt mask. */
488#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
489#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
490/** Bit 7 - I - IRQ interrupt mask. */
491#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
492#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
493/** Bit 8 - A - SError interrupt mask. */
494#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
495#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
496/** Bit 9 - D - Debug Exception mask. */
497#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
498#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
499/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
500#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
501#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
502#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
503/** Bit 12 - SSBS - Speculative Store Bypass. */
504#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
505#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
506/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
507#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
508#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
509/** Bit 14 - 19 - Reserved (read as zero). */
510#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
511 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
512/** Bit 20 - IL - Illegal Execution State flag. */
513#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
514#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
515/** Bit 21 - SS - Software Step flag. */
516#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
517#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
518/** Bit 22 - PAN - Privileged Access Never flag. */
519#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
520#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
521/** Bit 23 - UAO - User Access Override flag. */
522#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
523#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
524/** Bit 24 - DIT - Data Independent Timing flag. */
525#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
526#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
527/** Bit 25 - TCO - Tag Check Override flag. */
528#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
529#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
530/** Bit 26 - 27 - Reserved (read as zero). */
531#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
532/** Bit 28 - V - Overflow condition flag. */
533#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
534#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
535/** Bit 29 - C - Carry condition flag. */
536#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
537#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
538/** Bit 30 - Z - Zero condition flag. */
539#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
540#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
541/** Bit 31 - N - Negative condition flag. */
542#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
543#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
544/** Bit 32 - 63 - Reserved (read as zero). */
545#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
546/** Checks whether the given SPSR value contains a AARCH64 execution state. */
547#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
548/** @} */
549
550/** @name Aarch64 Exception levels
551 * @{ */
552/** Exception Level 0 - User mode. */
553#define ARMV8_AARCH64_EL_0 0
554/** Exception Level 1 - Supervisor mode. */
555#define ARMV8_AARCH64_EL_1 1
556/** Exception Level 2 - Hypervisor mode. */
557#define ARMV8_AARCH64_EL_2 2
558/** @} */
559
560
561/** @name ESR_EL2 (Exception Syndrome Register, EL2)
562 * @{
563 */
564/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
565#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
566#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
567/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
568#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
569#define ARMV8_ESR_EL2_IL_BIT 25
570#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
571#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
572/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
573#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
574 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
575#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
576/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
577#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
578 | RT_BIT_64(35) | RT_BIT_64(36))
579#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
580/** @} */
581
582
583/** @name ESR_EL2 Exception Classes (EC)
584 * @{ */
585/** Unknown exception reason. */
586#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
587/** Trapped WF* instruction. */
588#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
589/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
590#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
591/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
592#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
593/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
594#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
595/** AArch32 - Trapped LDC or STC access. */
596#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
597/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
598#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
599/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
600#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
601/** AArch32 - Trapped pointer authentication instruction. */
602#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
603/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
604#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
605/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
606#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
607/** FEAT_BTI - Branch Target Exception. */
608#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
609/** Illegal Execution State. */
610#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
611/** AArch32 - SVC instruction execution. */
612#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
613/** AArch32 - HVC instruction execution. */
614#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
615/** AArch32 - SMC instruction execution. */
616#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
617/** AArch64 - SVC instruction execution. */
618#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
619/** AArch64 - HVC instruction execution. */
620#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
621/** AArch64 - SMC instruction execution. */
622#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
623/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
624#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
625/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
626#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
627/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
628#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
629/** FEAT_TME - Exception from TSTART instruction. */
630#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
631/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
632#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
633/** FEAT_SME - Access to SME functionality trapped. */
634#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
635/** FEAT_RME - Exception from Granule Protection Check. */
636#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
637/** Instruction Abort from a lower Exception level. */
638#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
639/** Instruction Abort from the same Exception level. */
640#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
641/** PC alignment fault exception. */
642#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
643/** Data Abort from a lower Exception level. */
644#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
645/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
646#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
647/** SP alignment fault exception. */
648#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
649/** FEAT_MOPS - Memory Operation Exception. */
650#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
651/** AArch32 - Trapped floating point exception. */
652#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
653/** AArch64 - Trapped floating point exception. */
654#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
655/** SError interrupt. */
656#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
657/** Breakpoint Exception from a lower Exception level. */
658#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
659/** Breakpoint Exception from the same Exception level. */
660#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
661/** Software Step Exception from a lower Exception level. */
662#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
663/** Software Step Exception from the same Exception level. */
664#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
665/** Watchpoint Exception from a lower Exception level. */
666#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
667/** Watchpoint Exception from the same Exception level. */
668#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
669/** AArch32 - BKPT instruction execution. */
670#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
671/** AArch32 - Vector Catch exception. */
672#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
673/** AArch64 - BRK instruction execution. */
674#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
675/** @} */
676
677
678/** @name ISS encoding for Data Abort exceptions.
679 * @{ */
680/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
681#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
682 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
683#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
684/** Bit 6 - WnR - Write not Read. */
685#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
686#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
687/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
688#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
689#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
690/** Bit 8 - CM - Cache maintenance instruction. */
691#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
692#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
693/** Bit 9 - EA - External abort type. */
694#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
695#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
696/** Bit 10 - FnV - FAR not Valid. */
697#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
698#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
699/** Bit 11 - 12 - LST - Load/Store Type. */
700#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
701#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
702/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
703#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
704#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
705/** Bit 14 - AR - Acquire/Release semantics. */
706#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
707#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
708/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
709#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
710#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
711/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
712#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
713 | RT_BIT_32(19) | RT_BIT_32(20))
714#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
715/** Bit 21 - SSE - Syndrome Sign Extend. */
716#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
717#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
718/** Bit 22 - 23 - SAS - Syndrome Access Size. */
719#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
720#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
721/** Bit 24 - ISV - Instruction Syndrome Valid. */
722#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
723#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
724/** @} */
725
726
727/** @name Data Fault Status Code (DFSC).
728 * @{ */
729/** Address size fault, level 0 of translation or translation table base register. */
730#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
731/** Address size fault, level 1. */
732#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
733/** Address size fault, level 2. */
734#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
735/** Address size fault, level 3. */
736#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
737/** Translation fault, level 0. */
738#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
739/** Translation fault, level 1. */
740#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
741/** Translation fault, level 2. */
742#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
743/** Translation fault, level 3. */
744#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
745/** FEAT_LPA2 - Access flag fault, level 0. */
746#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
747/** Access flag fault, level 1. */
748#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
749/** Access flag fault, level 2. */
750#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
751/** Access flag fault, level 3. */
752#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
753/** FEAT_LPA2 - Permission fault, level 0. */
754#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
755/** Permission fault, level 1. */
756#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
757/** Permission fault, level 2. */
758#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
759/** Permission fault, level 3. */
760#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
761/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
762#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
763/** FEAT_MTE2 - Synchronous Tag Check Fault. */
764#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
765/** @todo Do the rest (lazy developer). */
766/** @} */
767
768
769/** @name SAS encoding.
770 * @{ */
771/** Byte access. */
772#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
773/** Halfword access (uint16_t). */
774#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
775/** Word access (uint32_t). */
776#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
777/** Doubleword access (uint64_t). */
778#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
779/** @} */
780
781
782/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
783 * @{ */
784/** Bit 0 - Direction flag. */
785#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
786#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
787/** Bit 1 - 4 - CRm value from the instruction. */
788#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
789 | RT_BIT_32(4))
790#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
791/** Bit 5 - 9 - Rt value from the instruction. */
792#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
793 | RT_BIT_32(8) | RT_BIT_32(9))
794#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
795/** Bit 10 - 13 - CRn value from the instruction. */
796#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
797 | RT_BIT_32(13))
798#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
799/** Bit 14 - 16 - Op2 value from the instruction. */
800#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
801#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
802/** Bit 17 - 19 - Op2 value from the instruction. */
803#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
804#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
805/** Bit 20 - 21 - Op0 value from the instruction. */
806#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
807#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
808/** Bit 22 - 24 - Reserved. */
809#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
810/** @} */
811
812
813/** @name ISS encoding for trapped HVC instruction exceptions.
814 * @{ */
815/** Bit 0 - 15 - imm16 value of the instruction. */
816#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
817#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
818/** @} */
819
820
821/** @name TCR_EL1 - Translation Control Register (EL1)
822 * @{
823 */
824/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
825#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
826 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
827#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
828/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
829#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
830#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
831/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
832#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
833#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
834/** Non cacheable. */
835# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
836/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
837# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
838/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
839# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
840/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
841# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
842/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
843#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
844#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
845/** Non cacheable. */
846# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
847/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
848# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
849/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
850# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
851/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
852# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
853/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
854#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
855#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
856/** Non shareable. */
857# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
858/** Invalid value. */
859# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
860/** Outer Shareable. */
861# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
862/** Inner Shareable. */
863# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
864/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
865#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15))
866#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
867/** Invalid granule size. */
868# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
869/** 16KiB granule size. */
870# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
871/** 4KiB granule size. */
872# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
873/** 64KiB granule size. */
874# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
875/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
876#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
877 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
878#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
879/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
880#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
881#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
882/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
883#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
884#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
885/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
886#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
887#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
888/** Non cacheable. */
889# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
890/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
891# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
892/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
893# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
894/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
895# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
896/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
897#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
898#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
899/** Non cacheable. */
900# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
901/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
902# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
903/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
904# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
905/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
906# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
907/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
908#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
909#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
910/** Non shareable. */
911# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
912/** Invalid value. */
913# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
914/** Outer Shareable. */
915# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
916/** Inner Shareable. */
917# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
918/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
919#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
920#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
921/** Invalid granule size. */
922# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
923/** 16KiB granule size. */
924# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
925/** 4KiB granule size. */
926# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
927/** 64KiB granule size. */
928# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
929/** Bit 32 - 34 - Intermediate Physical Address Size. */
930#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
931#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
932/** IPA - 32 bits, 4GiB. */
933# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
934/** IPA - 36 bits, 64GiB. */
935# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
936/** IPA - 40 bits, 1TiB. */
937# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
938/** IPA - 42 bits, 4TiB. */
939# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
940/** IPA - 44 bits, 16TiB. */
941# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
942/** IPA - 48 bits, 256TiB. */
943# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
944/** IPA - 52 bits, 4PiB. */
945# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
946/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
947#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
948#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
949/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
950#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
951#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
952/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
953#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
954#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
955/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
956#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
957#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
958/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
959#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
960#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
961/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
962#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
963#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
964/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
965#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
966#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
967/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
968#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
969#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
970/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
971#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
972#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
973/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
974#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
975#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
976/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
977#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
978#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
979/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
980#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
981#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
982/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
983#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
984#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
985/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
986#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
987#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
988/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
989#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
990#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
991/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
992#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
993#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
994/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
995#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
996#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
997/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
998#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
999#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1000/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1001#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1002#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1003/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1004#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1005#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1006/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1007#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1008#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1009/** Bit 57 - TCMA0 */
1010#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1011#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1012/** Bit 58 - TCMA1 */
1013#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1014#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1015/** Bit 59 - Data Sharing(?). */
1016#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1017#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1018/** @} */
1019
1020
1021/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1022 * @{
1023 */
1024/** Bit 0 - Common not Private (FEAT_TTCNP). */
1025#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1026#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1027/** Bit 1 - 47 - Translation table base address. */
1028#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1029#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1)
1030/** Bit 48 - 63 - ASID. */
1031#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1032#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1033/** @} */
1034
1035
1036/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1037 * @{ */
1038/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1039#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1040#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1041#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1042/** @} */
1043
1044
1045/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1046 * @{ */
1047/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1048#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1049#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1050#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1051/** @} */
1052
1053
1054/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1055 * @{ */
1056/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1057#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1058#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1059#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1060/** @} */
1061
1062
1063/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1064 * @{ */
1065/** Bit 0 - Common Binary Pointer Register - RW. */
1066#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1067#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1068/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1069#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1070#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1071/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1072#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1073#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1074/** Bit 8 - 10 - Priority bits - RO. */
1075#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1076#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1077/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1078#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1079#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1080/** INTIDS are 16-bit wide. */
1081# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1082/** INTIDS are 24-bit wide. */
1083# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1084/** Bit 14 - SEI Supported - RO. */
1085#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1086#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1087/** Bit 15 - Affinity 3 Valid - RO. */
1088#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1089#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1090/** Bit 18 - Range Selector Support - RO. */
1091#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1092#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1093/** Bit 19 - Extended INTID range supported - RO. */
1094#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1095#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1096/** All RW bits. */
1097#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1098/** All RO bits (including Res0). */
1099#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1100/** @} */
1101
1102
1103/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1104 * @{ */
1105/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1106#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1107#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1108/** @} */
1109
1110
1111/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1112 * @{ */
1113/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1114#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1115#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1116/** @} */
1117
1118
1119/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1120 * @{ */
1121/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1122#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1123#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1124/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1125#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1126#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1127/** Bit 24 - 27 - The INTID of the SGI. */
1128#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1129#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1130/* Bit 28 - 31 - Reserved. */
1131/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1132#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1133#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1134/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1135#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1136#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1137/* Bit 41 - 43 - Reserved. */
1138/** Bit 44 - 47 - Range selector. */
1139#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1140#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1141/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1142#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1143#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1144/* Bit 56 - 63 - Reserved. */
1145/** @} */
1146
1147
1148/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1149 * @{ */
1150/** Bit 0 - Enables the timer. */
1151#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1152#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1153/** Bit 1 - Timer interrupt mask bit. */
1154#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1155#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1156/** Bit 2 - Timer status bit. */
1157#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1158#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1159/** @} */
1160
1161
1162/** @name OSLAR_EL1 - OS Lock Access Register.
1163 * @{ */
1164/** Bit 0 - The OS Lock status bit. */
1165#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1166#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1167/** @} */
1168
1169
1170/** @name OSLSR_EL1 - OS Lock Status Register.
1171 * @{ */
1172/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1173#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1174#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1175/** Bit 1 - The OS Lock status bit. */
1176#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1177#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1178/** Bit 2 - Not 32-bit access. */
1179#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1180#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1181/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1182#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1183#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1184/** @} */
1185
1186
1187/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1188 * @{ */
1189/* Bit 0 - 3 - Reserved. */
1190/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1191#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1192#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1193/** No AES instructions implemented. */
1194# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1195/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1196# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1197/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1198# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1199/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1200#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1201#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1202/** No SHA1 instructions implemented. */
1203# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1204/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1205# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1206/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1207#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1208#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1209/** No SHA2 instructions implemented. */
1210# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1211/** SHA256 instructions implemented (FEAT_SHA256). */
1212# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1213/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1214# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1215/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1216#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1217#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1218/** No CRC32 instructions implemented. */
1219# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1220/** CRC32 instructions implemented (FEAT_CRC32). */
1221# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1222/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1223#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1224#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1225/** No Atomic instructions implemented. */
1226# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1227/** Atomic instructions implemented (FEAT_LSE). */
1228# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1229/** Bit 24 - 27 - Indicates support for TME instructions. */
1230#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1231#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1232/** TME instructions are not implemented. */
1233# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1234/** TME instructions are implemented. */
1235# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1236/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1237#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1238#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1239/** No RDMA instructions implemented. */
1240# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1241/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1242# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1243/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1244#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1245#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1246/** No SHA3 instructions implemented. */
1247# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1248/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1249# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1250/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1251#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1252#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1253/** No SM3 instructions implemented. */
1254# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1255/** SM3 instructions implemented (FEAT_SM3). */
1256# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1257/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1258#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1259#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1260/** No SM4 instructions implemented. */
1261# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1262/** SM4 instructions implemented (FEAT_SM4). */
1263# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1264/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1265#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1266#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1267/** No Dot Product instructions implemented. */
1268# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1269/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1270# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1271/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1272#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1273#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1274/** FMLAL and FMLSL instructions are not implemented. */
1275# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1276/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1277# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1278/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1279#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1280#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1281/** No flag manipulation instructions implemented. */
1282# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1283/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1284# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1285/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1286# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1287/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1288#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1289#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1290/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1291# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1292/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1293# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1294/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1295# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1296/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1297#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1298#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1299/** No Random Number instructions implemented. */
1300# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1301/** RNDR and RDNRRS registers are implemented . */
1302# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1303/** @} */
1304
1305
1306/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1307 * @{ */
1308/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1309#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1310#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1311/** DC CVAP not supported. */
1312# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1313/** DC CVAP supported (FEAT_DPB). */
1314# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1315/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1316# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1317/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1318#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1319#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1320/** Address Authentication using the QARMA5 algorithm is not implemented. */
1321# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1322/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1323# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1324/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1325# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1326/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1327# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1328/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1329# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1330/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1331# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1332/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1333#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1334#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1335/** Address Authentication using the QARMA5 algorithm is not implemented. */
1336# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1337/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1338# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1339/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1340# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1341/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1342# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1343/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1344# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1345/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1346# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1347/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1348#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1349#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1350/** No FJCVTZS instruction implemented. */
1351# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1352/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1353# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1354/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1355#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1356#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1357/** No FCMLA and FCADD instructions implemented. */
1358# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1359/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1360# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1361/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1362#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1363#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1364/** No RCpc instructions implemented. */
1365# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1366/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1367# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1368/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1369# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1370/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1371#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1372#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1373/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1374# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1375/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1376# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1377/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1378#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1379#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1380/** Generic Authentication using an implementation defined algorithm is not implemented. */
1381# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1382/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1383# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1384/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1385#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1386#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1387/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1388# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1389/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1390# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1391/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1392#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1393#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1394/** No SB instructions implemented. */
1395# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1396/** SB instructions implemented (FEAT_SB). */
1397# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1398/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1399#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1400#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1401/** Prediction invalidation instructions are not implemented. */
1402# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1403/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1404# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1405/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1406#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1407#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1408/** BFloat16 instructions are not implemented. */
1409# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1410/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1411# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1412/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1413# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1414/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1415#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1416#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1417/** Data Gathering Hint instructions are not implemented. */
1418# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1419/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1420# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1421/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1422#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1423#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1424/** No Int8 matrix multiplication instructions implemented. */
1425# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1426/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1427# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1428/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1429#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1430#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1431/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1432# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1433/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1434# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1435/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1436#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1437#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1438/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1439# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1440/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1441# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1442/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1443# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1444/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1445# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1446/** @} */
1447
1448
1449/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1450 * @{ */
1451/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1452#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1453#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1454/** WFET and WFIT are not supported. */
1455# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1456/** WFET and WFIT are supported (FEAT_WFxT). */
1457# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1458/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1459#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1460#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1461/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1462# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1463/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1464# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1465/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1466#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1467#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1468/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1469# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1470/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1471# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1472/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1473#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1474#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1475/** Address Authentication using the QARMA3 algorithm is not implemented. */
1476# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1477/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1478# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1479/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1480# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1481/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1482# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1483/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1484# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1485/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1486# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1487/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1488#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1489#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1490/** No Memory Copy and Memory Set instructions implemented. */
1491# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1492/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1493# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1494/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1495#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1496#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1497/** BC instruction is not implemented. */
1498# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1499/** BC instruction is implemented (FEAT_HBC). */
1500# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1501/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1502#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1503#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1504/** ConstPACField() returns FALSE. */
1505# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1506/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1507# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1508/* Bit 28 - 63 - Reserved. */
1509/** @} */
1510
1511
1512/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1513 * @{ */
1514/** Bit 0 - 3 - EL0 Exception level handling. */
1515#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1516#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1517/** EL0 can be executed in AArch64 state only. */
1518# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1519/** EL0 can be executed in AArch64 and AArch32 state. */
1520# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1521/** Bit 4 - 7 - EL1 Exception level handling. */
1522#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1523#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1524/** EL1 can be executed in AArch64 state only. */
1525# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1526/** EL1 can be executed in AArch64 and AArch32 state. */
1527# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1528/** Bit 8 - 11 - EL2 Exception level handling. */
1529#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1530#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1531/** EL2 is not implemented. */
1532# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1533/** EL2 can be executed in AArch64 state only. */
1534# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1535/** EL2 can be executed in AArch64 and AArch32 state. */
1536# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1537/** Bit 12 - 15 - EL3 Exception level handling. */
1538#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1539#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1540/** EL3 is not implemented. */
1541# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1542/** EL3 can be executed in AArch64 state only. */
1543# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1544/** EL3 can be executed in AArch64 and AArch32 state. */
1545# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1546/** Bit 16 - 19 - Floating-point support. */
1547#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1548#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1549/** Floating-point is implemented and support single and double precision. */
1550# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1551/** Floating-point is implemented and support single, double and half precision. */
1552# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1553/** Floating-point is not implemented. */
1554# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1555/** Bit 20 - 23 - Advanced SIMD support. */
1556#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1557#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1558/** Advanced SIMD is implemented and support single and double precision. */
1559# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1560/** Advanced SIMD is implemented and support single, double and half precision. */
1561# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1562/** Advanced SIMD is not implemented. */
1563# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1564/** Bit 24 - 27 - System register GIC CPU interface support. */
1565#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1566#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1567/** GIC CPU interface system registers are not implemented. */
1568# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1569/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1570# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1571/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1572# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1573/** Bit 28 - 31 - RAS Extension version. */
1574#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1575#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1576/** No RAS extension. */
1577# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1578/** RAS Extension implemented. */
1579# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1580/** FEAT_RASv1p1 implemented. */
1581# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1582/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1583#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1584#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1585/** SVE is not supported. */
1586# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1587/** SVE is supported. */
1588# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1589/** Bit 36 - 39 - Secure EL2 support. */
1590#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1591#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1592/** Secure EL2 is not supported. */
1593# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1594/** Secure EL2 is implemented. */
1595# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1596/** Bit 40 - 43 - MPAM support. */
1597#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1598#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
1599/** MPAM extension major version number is 0. */
1600# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
1601/** MPAM extension major version number is 1. */
1602# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
1603/** Bit 44 - 47 - Activity Monitor Extension support. */
1604#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1605#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
1606/** Activity Monitor extension is not implemented. */
1607# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
1608/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
1609# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
1610/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
1611# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
1612/** Bit 48 - 51 - Data Independent Timing support. */
1613#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1614#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
1615/** AArch64 does not guarantee constant execution time of any instructions. */
1616# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
1617/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
1618# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
1619/** Bit 52 - 55 - Realm Management Extension support. */
1620#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1621#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
1622/** Realm Management Extension not implemented. */
1623# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
1624/** RMEv1 is implemented (FEAT_RME). */
1625# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
1626/** Bit 56 - 59 - Speculative use out of context branch targets support. */
1627#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1628#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
1629/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
1630# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
1631/** FEAT_CSV2 is implemented. */
1632# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
1633/** FEAT_CSV2_2 is implemented. */
1634# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
1635/** FEAT_CSV2_3 is implemented. */
1636# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
1637/** Bit 60 - 63 - Speculative use of faulting data support. */
1638#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1639#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
1640/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
1641# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
1642/** FEAT_CSV3 is supported . */
1643# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
1644/** @} */
1645
1646
1647/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
1648 * @{ */
1649/** Bit 0 - 3 - Branch Target Identification support. */
1650#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1651#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
1652/** The Branch Target Identification mechanism is not implemented. */
1653# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
1654/** The Branch Target Identifcation mechanism is implemented. */
1655# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
1656/** Bit 4 - 7 - Speculative Store Bypassing control support. */
1657#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1658#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
1659/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
1660# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
1661/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
1662# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
1663/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
1664 * to directly read and write the PSTATE.SSBS field. */
1665# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
1666/** Bit 8 - 11 - Memory Tagging Extension support. */
1667#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1668#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
1669/** MTE is not implemented. */
1670# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
1671/** Instruction only Memory Tagging Extensions implemented. */
1672# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
1673/** Full Memory Tagging Extension implemented. */
1674# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
1675/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
1676# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
1677/** Bit 12 - 15 - RAS Extension fractional field. */
1678#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1679#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
1680/** RAS Extension is implemented. */
1681# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
1682/** FEAT_RASv1p1 is implemented. */
1683# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
1684/** Bit 16 - 19 - MPAM minor version number. */
1685#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1686#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
1687/** The minor version of number of the MPAM extension is 0. */
1688# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
1689/** The minor version of number of the MPAM extension is 1. */
1690# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
1691/* Bit 20 - 23 - Reserved. */
1692/** Bit 24 - 27 - Scalable Matrix Extension support. */
1693#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1694#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
1695/** Scalable Matrix Extensions are not implemented. */
1696# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
1697/** Scalable Matrix Extensions are implemented (FEAT_SME). */
1698# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
1699/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
1700# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
1701/** Bit 28 - 31 - Random Number trap to EL3 support. */
1702#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1703#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
1704/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
1705# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
1706/** Trapping of RNDR and RDNRRS to EL3 is supported. */
1707# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
1708/** Bit 32 - 35 - CSV2 fractional field. */
1709#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1710#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
1711/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
1712# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
1713/** FEAT_CSV2_1p1 is implemented. */
1714# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
1715/** FEAT_CSV2_1p2 is implemented. */
1716# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
1717/** Bit 36 - 39 - Non-maskable Interrupt support. */
1718#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1719#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
1720/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
1721# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
1722/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
1723# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
1724/** @} */
1725
1726
1727/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
1728 * @{ */
1729/** Bit 0 - 3 - Physical Address range supported. */
1730#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1731#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
1732/** Physical Address range is 32 bits, 4GiB. */
1733# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
1734/** Physical Address range is 36 bits, 64GiB. */
1735# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
1736/** Physical Address range is 40 bits, 1TiB. */
1737# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
1738/** Physical Address range is 42 bits, 4TiB. */
1739# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
1740/** Physical Address range is 44 bits, 16TiB. */
1741# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
1742/** Physical Address range is 48 bits, 256TiB. */
1743# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
1744/** Physical Address range is 52 bits, 4PiB. */
1745# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
1746/** Bit 4 - 7 - Number of ASID bits. */
1747#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1748#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
1749/** ASID bits is 8. */
1750# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
1751/** ASID bits is 16. */
1752# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
1753/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
1754#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1755#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
1756/** No mixed-endian support. */
1757# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
1758/** Mixed-endian supported. */
1759# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
1760/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
1761#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1762#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
1763/** No distinction between Secure and Non-secure Memory supported. */
1764# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
1765/** Distinction between Secure and Non-secure Memory supported. */
1766# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
1767/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
1768#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1769#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
1770/** No mixed-endian support at EL0. */
1771# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
1772/** Mixed-endian support at EL0. */
1773# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
1774/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
1775#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1776#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
1777/** 16KiB granule size not supported. */
1778# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
1779/** 16KiB granule size is supported. */
1780# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
1781/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1782# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
1783/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
1784#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1785#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
1786/** 64KiB granule supported. */
1787# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
1788/** 64KiB granule not supported. */
1789# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
1790/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
1791#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1792#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
1793/** 4KiB granule supported. */
1794# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
1795/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1796# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
1797/** 4KiB granule not supported. */
1798# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
1799/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
1800#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1801#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
1802/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
1803# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
1804/** 16KiB granule not supported at stage 2. */
1805# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
1806/** 16KiB granule supported at stage 2. */
1807# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
1808/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1809# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
1810/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
1811#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1812#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
1813/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
1814# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
1815/** 64KiB granule not supported at stage 2. */
1816# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
1817/** 64KiB granule supported at stage 2. */
1818# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
1819/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1820#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1821#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
1822/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
1823# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
1824/** 4KiB granule not supported at stage 2. */
1825# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
1826/** 4KiB granule supported at stage 2. */
1827# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
1828/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1829# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
1830/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
1831#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1832#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
1833/** All exception entries and exits are context synchronization events. */
1834# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
1835/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
1836# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
1837/* Bit 48 - 55 - Reserved. */
1838/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
1839#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1840#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
1841/** Fine-grained trap controls are not implemented. */
1842# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
1843/** Fine-grained trap controls are implemented (FEAT_FGT). */
1844# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
1845/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
1846#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1847#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
1848/** Enhanced Counter Virtualization is not implemented. */
1849# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
1850/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
1851# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
1852/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
1853# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
1854/** @} */
1855
1856
1857/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
1858 * @{ */
1859/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
1860#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1861#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
1862/** Hardware update of the Access flag and dirty state are not supported. */
1863# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
1864/** Support for hardware update of the Access flag for Block and Page descriptors. */
1865# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
1866/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
1867# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
1868/** Bit 4 - 7 - EL1 Exception level handling. */
1869#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1870#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
1871/** VMID bits is 8. */
1872# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
1873/** VMID bits is 16 (FEAT_VMID16). */
1874# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
1875/** Bit 8 - 11 - Virtualization Host Extensions support. */
1876#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1877#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
1878/** Virtualization Host Extensions are not supported. */
1879# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
1880/** Virtualization Host Extensions are supported. */
1881# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
1882/** Bit 12 - 15 - Hierarchical Permission Disables. */
1883#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1884#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
1885/** Disabling of hierarchical controls not supported. */
1886# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
1887/** Disabling of hierarchical controls supported (FEAT_HPDS). */
1888# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
1889/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
1890# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
1891/** Bit 16 - 19 - LORegions support. */
1892#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1893#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
1894/** LORegions not supported. */
1895# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
1896/** LORegions supported. */
1897# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
1898/** Bit 20 - 23 - Privileged Access Never support. */
1899#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1900#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
1901/** PAN not supported. */
1902# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
1903/** PAN supported (FEAT_PAN). */
1904# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
1905/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
1906# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
1907/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
1908# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
1909/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
1910#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1911#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
1912/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
1913# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
1914/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
1915# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
1916/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
1917#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1918#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
1919/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
1920# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
1921/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
1922# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
1923/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
1924#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1925#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
1926/** Configurable delayed trapping of WFE is not supported. */
1927# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
1928/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
1929# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
1930/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
1931#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1932#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
1933/** Enhanced Translation Synchronization is not supported. */
1934# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
1935/** Enhanced Translation Synchronization is implemented. */
1936# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
1937/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1938#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1939#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
1940/** HCRX_EL2 and its associated EL3 trap are not supported. */
1941# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
1942/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
1943# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
1944/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
1945#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1946#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
1947/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
1948# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
1949/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
1950# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
1951/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
1952#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1953#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
1954/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
1955# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
1956/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
1957# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
1958/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
1959#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1960#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
1961/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
1962# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
1963/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
1964# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
1965/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
1966#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1967#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
1968/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
1969# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
1970/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
1971# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
1972/* Bit 60 - 63 - Reserved. */
1973/** @} */
1974
1975
1976/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
1977 * @{ */
1978/** Bit 0 - 3 - Indicates support for Common not Private translations. */
1979#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1980#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
1981/** Common not Private translations are not supported. */
1982# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
1983/** Support for Common not Private translations (FEAT_TTNCP). */
1984# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
1985/** Bit 4 - 7 - Indicates support for User Access Override. */
1986#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1987#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
1988/** User Access Override is not supported. */
1989# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
1990/** User Access Override is supported (FEAT_UAO). */
1991# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
1992/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
1993#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1994#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
1995/** LSMAOE and nTLSMD bits are not supported. */
1996# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
1997/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
1998# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
1999/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2000#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2001#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2002/** IESB bit is not supported. */
2003# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2004/** IESB bit is supported (FEAT_IESB). */
2005# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2006/** Bit 16 - 19 - Indicates support for larger virtual address. */
2007#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2008#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2009/** Virtual address range is 48 bits. */
2010# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2011/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2012# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2013/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2014#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2015#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2016/** CCSIDR_EL1 register format is 32-bit. */
2017# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2018/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2019# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2020/** Bit 24 - 27 - Indicates support for nested virtualization. */
2021#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2022#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2023/** Nested virtualization is not supported. */
2024# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2025/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2026# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2027/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2028# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2029/** Bit 28 - 31 - Indicates support for small translation tables. */
2030#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2031#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2032/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2033# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2034/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2035# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2036/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2037#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2038#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2039/** Unaligned single-copy atomicity and atomic functions are not supported. */
2040# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2041/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2042# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2043/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2044#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2045#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2046/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2047# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2048/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2049# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2050/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2051#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2052#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2053/** HCR_EL2.FWB bit is not supported. */
2054# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2055/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2056# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2057/* Bit 44 - 47 - Reserved. */
2058/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2059#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2060#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2061/** TLB maintenance instructions by address have bits [47:44] Res0. */
2062# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2063/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2064# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2065/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2066 * changing block size for a translation. */
2067#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2068#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2069/** Level 0 support for changing block size is supported (FEAT_BBM). */
2070# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2071/** Level 1 support for changing block size is supported (FEAT_BBM). */
2072# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2073/** Level 2 support for changing block size is supported (FEAT_BBM). */
2074# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2075/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2076#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2077#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2078/** Enhanced Virtualization Traps are not supported. */
2079# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2080/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2081# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2082/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2083# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2084/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2085#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2086#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2087/** E0PDx mechanism is not supported. */
2088# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2089/** E0PDx mechanism is supported (FEAT_E0PD). */
2090# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2091/** @} */
2092
2093
2094/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2095 * @{ */
2096/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2097#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2098#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2099/** Armv8 debug architecture version. */
2100# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2101/** Armv8 debug architecture version with virtualization host extensions. */
2102# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2103/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2104# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2105/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2106# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2107/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2108# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2109/** Bit 4 - 7 - Indicates trace support. */
2110#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2111#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2112/** Trace unit System registers not implemented. */
2113# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2114/** Trace unit System registers supported. */
2115# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2116/** Bit 8 - 11 - Performance Monitors Extension version. */
2117#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2118#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2119/** Performance Monitors Extension not supported. */
2120# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2121/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2122# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2123/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2124# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2125/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2126# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2127/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2128# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2129/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2130# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2131/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2132# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2133/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2134#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2135#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2136/* Bit 16 - 19 - Reserved 0. */
2137/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2138#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2139#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2140/* Bit 24 - 27 - Reserved 0. */
2141/** Bit 28 - 31 - Number of context-aware breakpoints. */
2142#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2143#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2144/** Bit 32 - 35 - Statistical Profiling Extension version. */
2145#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2146#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2147/** Statistical Profiling Extension not implemented. */
2148# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2149/** Statistical Profiling Extension supported (FEAT_SPE). */
2150# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2151/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2152# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2153/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2154# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2155/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2156# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2157/** Bit 36 - 39 - OS Double Lock implemented. */
2158#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2159#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2160/** OS Double Lock is not implemented. */
2161# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2162/** OS Double Lock is supported (FEAT_DoubleLock). */
2163# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2164/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2165#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2166#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2167/** Armv8.4 self-hosted Trace Extension not implemented. */
2168# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2169/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2170# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2171/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2172#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2173#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2174/** Trace Buffer Extension is not implemented. */
2175# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2176/** Trace Buffer Extension is supported (FEAT_TRBE). */
2177# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2178/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2179#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2180#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2181/** Multi-threaded PMU extension is not implemented. */
2182# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2183/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2184# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2185/** Multi-threaded PMU extension is not implemented. */
2186# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2187/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2188#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2189#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2190/** Branch Record Buffer extension is not implemented. */
2191# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2192/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2193# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2194/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2195# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2196/* Bit 56 - 59 - Reserved. */
2197/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2198#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2199#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2200/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2201# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2202/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2203# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2204/** @} */
2205
2206
2207#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
2208/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2209 * @ingroup grp_rt_armv8
2210 *
2211 * A few inlined functions and macros for assiting in encoding common ARMv8
2212 * instructions.
2213 *
2214 * @{ */
2215
2216/** A64: Return instruction. */
2217#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2218/** A64: Return instruction with LR pointer authentication using SP and key A. */
2219#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2220/** A64: Return instruction with LR pointer authentication using SP and key B. */
2221#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2222/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2223#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2224/** A64: Insert pointer authentication code into LR using SP and key B. */
2225#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2226/** A64: Insert pointer authentication code into LR using XZR and key B. */
2227#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2228
2229
2230typedef enum
2231{
2232 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
2233 * and update the register. */
2234 kArm64InstrStLdPairType_PostIndex = 1,
2235 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2236 * but don't update the register. */
2237 kArm64InstrStLdPairType_Signed = 2,
2238 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2239 * and update the register. */
2240 kArm64InstrStLdPairType_PreIndex = 3
2241} ARM64INSTRSTLDPAIRTYPE;
2242
2243/**
2244 * A64: Encodes either stp (store register pair) or ldp (load register pair).
2245 *
2246 * @returns The encoded instruction.
2247 * @param fLoad true for ldp, false of stp.
2248 * @param u2Opc When @a fSimdFp is @c false:
2249 * - 0 for 32-bit GPRs (Wt).
2250 * - 1 for encoding stgp or ldpsw.
2251 * - 2 for 64-bit GRPs (Xt).
2252 * - 3 illegal.
2253 * When @a fSimdFp is @c true:
2254 * - 0 for 32-bit SIMD&FP registers (St).
2255 * - 1 for 64-bit SIMD&FP registers (Dt).
2256 * - 2 for 128-bit SIMD&FP regsiters (Qt).
2257 * @param enmType The instruction variant wrt addressing and updating of the
2258 * addressing register.
2259 * @param iReg1 The first register to store/load.
2260 * @param iReg2 The second register to store/load.
2261 * @param iBaseReg The base register to use when addressing. SP is allowed.
2262 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
2263 * will be multiplied by the register size.
2264 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
2265 * stgp/ldpsw instructions.
2266 */
2267DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
2268 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2269 bool fSimdFp = false)
2270{
2271 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
2272 return (u2Opc << 30)
2273 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
2274 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
2275 | ((uint32_t)enmType << 23)
2276 | ((uint32_t)fLoad << 22)
2277 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
2278 | (iReg2 << 10)
2279 | (iBaseReg << 5)
2280 | iReg1;
2281}
2282
2283typedef enum /* Size VR Opc */
2284{ /* \ | / */
2285 kArmv8A64InstrLdStType_Mask_Size = 0x300,
2286 kArmv8A64InstrLdStType_Mask_VR = 0x010,
2287 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
2288 kArmv8A64InstrLdStType_Shift_Size = 8,
2289 kArmv8A64InstrLdStType_Shift_VR = 4,
2290 kArmv8A64InstrLdStType_Shift_Opc = 0,
2291
2292 kArmv8A64InstrLdStType_St_Byte = 0x000,
2293 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
2294 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
2295 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
2296
2297 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
2298 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
2299 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
2300 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
2301
2302 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
2303 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
2304 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
2305
2306 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
2307 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
2308
2309 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
2310
2311 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
2312 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
2313 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
2314 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
2315
2316 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
2317 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
2318
2319 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
2320 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
2321
2322 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
2323 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
2324
2325} ARMV8A64INSTRLDSTTYPE;
2326/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
2327#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
2328
2329
2330/**
2331 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2332 *
2333 * @returns The encoded instruction.
2334 * @param u32Opcode The base opcode value.
2335 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2336 * @param iReg The register to load into / store.
2337 * @param iBaseReg The base register to use when addressing. SP is allowed.
2338 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2339 */
2340DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
2341 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2342{
2343 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
2344 return u32Opcode
2345 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2346 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2347 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2348 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
2349 | (iBaseReg << 5)
2350 | iReg;
2351}
2352
2353
2354/**
2355 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2356 *
2357 * @returns The encoded instruction.
2358 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2359 * @param iReg The register to load into / store.
2360 * @param iBaseReg The base register to use when addressing. SP is allowed.
2361 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2362 */
2363DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
2364 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2365{
2366 /* 3 2 1 0 */
2367 /* 10987654321098765432109876543210 */
2368 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
2369 enmType, iReg, iBaseReg, i9ImmDisp);
2370}
2371
2372/**
2373 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
2374 *
2375 * @returns The encoded instruction.
2376 * @param enmType The load/store instruction type. Prefech not valid.
2377 * @param iReg The register to load into / store.
2378 * @param iBaseReg The base register to use when addressing. SP is allowed.
2379 * Written back.
2380 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2381 */
2382DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2383 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2384{
2385 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2386 /* 10987654321098765432109876543210 */
2387 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
2388 enmType, iReg, iBaseReg, i9ImmDisp);
2389}
2390
2391/**
2392 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
2393 *
2394 * @returns The encoded instruction.
2395 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2396 * @param iReg The register to load into / store.
2397 * @param iBaseReg The base register to use when addressing. SP is allowed.
2398 * Written back.
2399 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2400 */
2401DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2402 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2403{
2404 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2405 /* 10987654321098765432109876543210 */
2406 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
2407 enmType, iReg, iBaseReg, i9ImmDisp);
2408}
2409
2410/**
2411 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
2412 *
2413 * @returns The encoded instruction.
2414 * @param enmType The load/store instruction type. Prefech not valid,
2415 * nor any SIMD&FP variants.
2416 * @param iReg The register to load into / store.
2417 * @param iBaseReg The base register to use when addressing. SP is allowed.
2418 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2419 */
2420DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
2421 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2422{
2423 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
2424 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
2425 /* 3 2 1 0 */
2426 /* 10987654321098765432109876543210 */
2427 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
2428 enmType, iReg, iBaseReg, i9ImmDisp);
2429}
2430
2431
2432/**
2433 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
2434 *
2435 * @returns The encoded instruction.
2436 * @param enmType The load/store instruction type. Prefech not valid,
2437 * nor any SIMD&FP variants.
2438 * @param iReg The register to load into / store.
2439 * @param iBaseReg The base register to use when addressing. SP is allowed.
2440 * @param u12ImmDisp Addressing displacement, scaled by size.
2441 */
2442DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
2443 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
2444{
2445 Assert(u12ImmDisp < 4096U);
2446 Assert(iReg < 32); /* 3 2 1 0 */
2447 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2448 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
2449 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2450 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2451 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2452 | (u12ImmDisp << 10)
2453 | (iBaseReg << 5)
2454 | iReg;
2455}
2456
2457typedef enum
2458{
2459 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
2460 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
2461 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
2462 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
2463} ARMV8A64INSTRLDSTEXTEND;
2464
2465/**
2466 * A64: Encodes load/store w/ index register.
2467 *
2468 * @returns The encoded instruction.
2469 * @param enmType The load/store instruction type.
2470 * @param iReg The register to load into / store.
2471 * @param iBaseReg The base register to use when addressing. SP is allowed.
2472 * @param iRegIndex The index register.
2473 * @param enmExtend The extending to apply to @a iRegIndex.
2474 * @param fShifted Whether to shift the index. The shift amount corresponds
2475 * to the access size (thus irrelevant for byte accesses).
2476 */
2477DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
2478 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
2479 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
2480 bool fShifted = false)
2481{
2482 Assert(iRegIndex < 32);
2483 Assert(iReg < 32); /* 3 2 1 0 */
2484 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2485 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
2486 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2487 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2488 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2489 | (iRegIndex << 16)
2490 | ((uint32_t)enmExtend << 13)
2491 | ((uint32_t)fShifted << 12)
2492 | (iBaseReg << 5)
2493 | iReg;
2494}
2495
2496typedef enum /* VR Opc */
2497{ /* \ | */
2498 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
2499 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
2500 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
2501 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
2502
2503 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
2504 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
2505 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
2506 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
2507
2508 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
2509 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
2510 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
2511} ARMV8A64INSTRLDRLITTERAL;
2512
2513
2514/**
2515 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
2516 *
2517 * @returns The encoded instruction.
2518 * @param enmType The load instruction type.
2519 * @param iReg The register to load into.
2520 * @param i19Imm The signed immediate value, multiplied by 4 regardless
2521 * of access size.
2522 */
2523DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
2524{
2525 Assert(i19Imm >= -262144 && i19Imm < 262144);
2526 Assert(iReg < 32); /* 3 2 1 0 */
2527 /* 10987654321098765432109876543210 */
2528 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
2529 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
2530 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
2531 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
2532 | iReg;
2533}
2534
2535
2536typedef enum
2537{
2538 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
2539 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
2540 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
2541} ARMV8A64INSTRMOVWIDE;
2542
2543/**
2544 * A64: Encode a move wide immediate instruction.
2545 *
2546 * @returns The encoded instruction.
2547 * @param enmType The load instruction type.
2548 * @param iRegDst The register to mov the immediate into.
2549 * @param uImm16 The immediate value.
2550 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
2551 * half-words to target:
2552 * - 0 for bits 15:00,
2553 * - 1 for bits 31:16,
2554 * - 2 for bits 47:32 (f64Bit=true only),
2555 * - 3 for bits 63:48 (f64Bit=true only).
2556 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
2557 */
2558DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
2559 uint32_t iHalfWord = 0, bool f64Bit = true)
2560{
2561 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
2562 return ((uint32_t)f64Bit << 31)
2563 | ((uint32_t)enmType << 29)
2564 | UINT32_C(0x12800000)
2565 | (iHalfWord << 21)
2566 | (uImm16 << 5)
2567 | iRegDst;
2568}
2569
2570/** A64: Encodes a MOVN instruction.
2571 * @see Armv8A64MkInstrMovWide for parameter details. */
2572DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2573{
2574 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
2575}
2576
2577/** A64: Encodes a MOVZ instruction.
2578 * @see Armv8A64MkInstrMovWide for parameter details. */
2579DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2580{
2581 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
2582}
2583
2584/** A64: Encodes a MOVK instruction.
2585 * @see Armv8A64MkInstrMovWide for parameter details. */
2586DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2587{
2588 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
2589}
2590
2591
2592typedef enum
2593{
2594 kArmv8A64InstrShift_Lsl = 0,
2595 kArmv8A64InstrShift_Lsr,
2596 kArmv8A64InstrShift_Asr,
2597 kArmv8A64InstrShift_Ror
2598} ARMV8A64INSTRSHIFT;
2599
2600
2601/**
2602 * A64: Encodes a logical instruction with a shifted 2nd register operand.
2603 *
2604 * @returns The encoded instruction.
2605 * @param u2Opc The logical operation to perform.
2606 * @param fNot Whether to complement the 2nd operand.
2607 * @param iRegResult The output register.
2608 * @param iReg1 The 1st register operand.
2609 * @param iReg2Shifted The 2nd register operand, to which the optional
2610 * shifting is applied.
2611 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
2612 * GPRs.
2613 * @param offShift6 The shift amount (default: none).
2614 * @param enmShift The shift operation (default: LSL).
2615 */
2616DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
2617 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
2618 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
2619{
2620 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
2621 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
2622 return ((uint32_t)f64Bit << 31)
2623 | (u2Opc << 29)
2624 | UINT32_C(0x0a000000)
2625 | ((uint32_t)enmShift << 22)
2626 | ((uint32_t)fNot << 21)
2627 | (iReg2Shifted << 16)
2628 | (offShift6 << 10)
2629 | (iReg1 << 5)
2630 | iRegResult;
2631}
2632
2633
2634/** A64: Encodes an AND instruction.
2635 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2636DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2637 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2638{
2639 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2640}
2641
2642
2643/** A64: Encodes an BIC instruction.
2644 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2645DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2646 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2647{
2648 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2649}
2650
2651
2652/** A64: Encodes an ORR instruction.
2653 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2654DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2655 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2656{
2657 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2658}
2659
2660
2661/** A64: Encodes an MOV instruction.
2662 * This is an alias for "orr dst, xzr, src". */
2663DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
2664{
2665 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
2666}
2667
2668
2669/** A64: Encodes an ORN instruction.
2670 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2671DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2672 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2673{
2674 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2675}
2676
2677
2678/** A64: Encodes an EOR instruction.
2679 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2680DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2681 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2682{
2683 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2684}
2685
2686
2687/** A64: Encodes an EON instruction.
2688 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2689DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2690 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2691{
2692 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2693}
2694
2695
2696/** A64: Encodes an ANDS instruction.
2697 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2698DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2699 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2700{
2701 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2702}
2703
2704
2705/** A64: Encodes an BICS instruction.
2706 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2707DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2708 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2709{
2710 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2711}
2712
2713# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
2714
2715/**
2716 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
2717 *
2718 * @returns The decoded mask.
2719 * @param uImm6SizeLen The immS value from the instruction. (No N part
2720 * here, as that must be zero for instructions
2721 * operating on 32-bit wide registers.)
2722 * @param uImm6Rotations The immR value from the instruction.
2723 */
2724DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
2725{
2726 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
2727
2728 /* Determine the element size. */
2729 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
2730 Assert(cBitsElementLog2 + 1U != 0U);
2731
2732 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
2733 Assert(uImm6Rotations < cBitsElement);
2734
2735 /* Extract the number of bits set to 1: */
2736 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
2737 Assert(cBitsSetTo1 < cBitsElement);
2738 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
2739
2740 /* Produce the unrotated pattern. */
2741 static const uint32_t s_auReplicate[]
2742 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
2743 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
2744
2745 /* Rotate it and return. */
2746 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
2747}
2748
2749
2750/**
2751 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
2752 *
2753 * @returns The decoded mask.
2754 * @param uImm7SizeLen The N:immS value from the instruction.
2755 * @param uImm6Rotations The immR value from the instruction.
2756 */
2757DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
2758{
2759 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
2760
2761 /* Determine the element size. */
2762 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
2763 Assert(cBitsElementLog2 + 1U != 0U);
2764
2765 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
2766 Assert(uImm6Rotations < cBitsElement);
2767
2768 /* Extract the number of bits set to 1: */
2769 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
2770 Assert(cBitsSetTo1 < cBitsElement);
2771 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
2772
2773 /* Produce the unrotated pattern. */
2774 static const uint64_t s_auReplicate[]
2775 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
2776 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
2777
2778 /* Rotate it and return. */
2779 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
2780}
2781
2782
2783/**
2784 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
2785 * the immS value.
2786 */
2787DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
2788{
2789 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
2790}
2791
2792
2793/**
2794 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
2795 * 32-bit bitmask to a set of immediates for those instructions.
2796 *
2797 * @returns true if successful, false if not.
2798 * @param fMask The mask value to convert.
2799 * @param puImm6SizeLen Where to return the immS part (N is always zero for
2800 * 32-bit wide masks).
2801 * @param puImm6Rotations Where to return the immR.
2802 */
2803DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
2804{
2805 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
2806 if ((uint32_t)(fMask + 1U) <= 1)
2807 return false;
2808
2809 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
2810 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
2811 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
2812 if (cRor)
2813 fMask = ASMRotateRightU32(fMask, cRor);
2814 else
2815 fMask = ASMRotateLeftU32(fMask, cRol);
2816 Assert(fMask & RT_BIT_32(0));
2817 Assert(!(fMask & RT_BIT_32(31)));
2818
2819 /* Count the trailing ones and leading zeros. */
2820 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
2821 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
2822
2823 /* The potential element length is then the sum of the two above. */
2824 unsigned const cBitsElement = cOnes + cZeros;
2825 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
2826 return false;
2827
2828 /* Special case: 32 bits element size. Since we're done here. */
2829 if (cBitsElement == 32)
2830 *puImm6SizeLen = cOnes - 1;
2831 else
2832 {
2833 /* Extract the element bits and check that these are replicated in the whole pattern. */
2834 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
2835 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
2836
2837 static const uint32_t s_auReplicate[]
2838 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
2839 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
2840 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
2841 else
2842 return false;
2843 }
2844 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
2845
2846 return true;
2847}
2848
2849
2850/**
2851 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
2852 * 64-bit bitmask to a set of immediates for those instructions.
2853 *
2854 * @returns true if successful, false if not.
2855 * @param fMask The mask value to convert.
2856 * @param puImm7SizeLen Where to return the N:immS part.
2857 * @param puImm6Rotations Where to return the immR.
2858 */
2859DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
2860{
2861 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
2862 if ((uint64_t)(fMask + 1U) <= 1)
2863 return false;
2864
2865 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
2866 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
2867 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
2868 if (cRor)
2869 fMask = ASMRotateRightU64(fMask, cRor);
2870 else
2871 fMask = ASMRotateLeftU64(fMask, cRol);
2872 Assert(fMask & RT_BIT_64(0));
2873 Assert(!(fMask & RT_BIT_64(63)));
2874
2875 /* Count the trailing ones and leading zeros. */
2876 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
2877 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
2878
2879 /* The potential element length is then the sum of the two above. */
2880 unsigned const cBitsElement = cOnes + cZeros;
2881 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
2882 return false;
2883
2884 /* Special case: 64 bits element size. Since we're done here. */
2885 if (cBitsElement == 64)
2886 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
2887 else
2888 {
2889 /* Extract the element bits and check that these are replicated in the whole pattern. */
2890 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
2891 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
2892
2893 static const uint64_t s_auReplicate[]
2894 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
2895 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
2896 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
2897 else
2898 return false;
2899 }
2900 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
2901
2902 return true;
2903}
2904
2905# endif /* IPRT_INCLUDED_asm_h */
2906
2907/**
2908 * A64: Encodes a logical instruction with an complicated immediate mask.
2909 *
2910 * The @a uImm7SizeLen parameter specifies two things:
2911 * 1. the element size and
2912 * 2. the number of bits set to 1 in the pattern.
2913 *
2914 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
2915 * top) and using the position of the first bit set as a power of two.
2916 *
2917 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
2918 * |---|---|---|---|---|---|---|--------------|
2919 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
2920 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
2921 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
2922 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
2923 * | 0 | 0 | x | x | x | x | x | 32 bits |
2924 * | 1 | x | x | x | x | x | x | 64 bits |
2925 *
2926 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
2927 * there is always one zero bit in the pattern).
2928 *
2929 * The @a uImm6Rotations parameter specifies how many bits to the right,
2930 * the element pattern is rotated. The rotation count must be less than the
2931 * element bit count (size).
2932 *
2933 * @returns The encoded instruction.
2934 * @param u2Opc The logical operation to perform.
2935 * @param iRegResult The output register.
2936 * @param iRegSrc The 1st register operand.
2937 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
2938 * field at the top of the 6-bit 'imms' field.
2939 *
2940 * @param uImm6Rotations The rotation count.
2941 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
2942 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
2943 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
2944 */
2945DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
2946 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
2947{
2948 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x1f)));
2949 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
2950 return ((uint32_t)f64Bit << 31)
2951 | (u2Opc << 29)
2952 | UINT32_C(0x12000000)
2953 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
2954 | (uImm6Rotations << 16)
2955 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
2956 | (iRegSrc << 5)
2957 | iRegResult;
2958}
2959
2960
2961/** A64: Encodes an AND instruction w/ complicated immediate mask.
2962 * @see Armv8A64MkInstrLogicalImm for parameter details. */
2963DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
2964 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
2965{
2966 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
2967}
2968
2969
2970/** A64: Encodes an ORR instruction w/ complicated immediate mask.
2971 * @see Armv8A64MkInstrLogicalImm for parameter details. */
2972DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
2973 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
2974{
2975 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
2976}
2977
2978
2979/** A64: Encodes an EOR instruction w/ complicated immediate mask.
2980 * @see Armv8A64MkInstrLogicalImm for parameter details. */
2981DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
2982 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
2983{
2984 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
2985}
2986
2987
2988/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
2989 * @see Armv8A64MkInstrLogicalImm for parameter details. */
2990DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
2991 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
2992{
2993 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
2994}
2995
2996
2997/** A64: Encodes an TST instruction w/ complicated immediate mask.
2998 * @see Armv8A64MkInstrLogicalImm for parameter details. */
2999DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
3000 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3001{
3002 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3003}
3004
3005
3006/**
3007 * A64: Encodes a bitfield instruction.
3008 *
3009 * @returns The encoded instruction.
3010 * @param u2Opc The bitfield operation to perform.
3011 * @param iRegResult The output register.
3012 * @param iRegSrc The 1st register operand.
3013 * @param cImm6Ror The right rotation count.
3014 * @param uImm6S The leftmost bit to be moved.
3015 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3016 * @param uN1 This must match @a f64Bit for all instructions
3017 * currently specified.
3018 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3019 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3020 */
3021DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3022 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
3023{
3024 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
3025 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
3026 return ((uint32_t)f64Bit << 31)
3027 | (u2Opc << 29)
3028 | UINT32_C(0x13000000)
3029 | (uN1 << 22)
3030 | (cImm6Ror << 16)
3031 | (uImm6S << 10)
3032 | (iRegSrc << 5)
3033 | iRegResult;
3034}
3035
3036
3037/** A64: Encodes a SBFM instruction.
3038 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3039DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3040 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3041{
3042 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3043}
3044
3045
3046/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
3047 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3048DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3049{
3050 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
3051}
3052
3053
3054/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
3055 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3056DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3057{
3058 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
3059}
3060
3061
3062/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
3063 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3064DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
3065{
3066 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
3067}
3068
3069
3070/** A64: Encodes a BFM instruction.
3071 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3072DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3073 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3074{
3075 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3076}
3077
3078
3079/** A64: Encodes a BFI instruction (insert).
3080 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3081DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
3082 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3083{
3084 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3085 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
3086 cBitsWidth - 1, f64Bit);
3087}
3088
3089
3090/** A64: Encodes an UBFM instruction.
3091 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3092DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3093 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3094{
3095 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3096}
3097
3098
3099/** A64: Encodes an UBFX instruction (zero extending extract).
3100 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3101DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
3102 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3103{
3104 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3105}
3106
3107
3108/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
3109 * shifted into destination).
3110 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3111DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
3112 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
3113{
3114 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
3115 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
3116}
3117
3118
3119/** A64: Encodes an LSL instruction w/ immediate shift value.
3120 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3121DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3122{
3123 uint32_t const cWidth = f64Bit ? 63 : 31;
3124 Assert(cShift > 0); Assert(cShift <= cWidth);
3125 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
3126 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
3127}
3128
3129
3130/** A64: Encodes an LSR instruction w/ immediate shift value.
3131 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3132DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3133{
3134 uint32_t const cWidth = f64Bit ? 63 : 31;
3135 Assert(cShift > 0); Assert(cShift <= cWidth);
3136 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
3137}
3138
3139
3140/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
3141 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3142DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3143{
3144 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
3145}
3146
3147
3148/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
3149 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3150DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3151{
3152 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
3153}
3154
3155
3156/**
3157 * A64: Encodes an EXTR instruction with an immediate.
3158 *
3159 * @returns The encoded instruction.
3160 * @param iRegResult The register to store the result in. ZR is valid.
3161 * @param iRegLow The register holding the least significant bits in the
3162 * extraction. ZR is valid.
3163 * @param iRegHigh The register holding the most significant bits in the
3164 * extraction. ZR is valid.
3165 * @param uLsb The bit number of the least significant bit, or where in
3166 * @a iRegLow to start the
3167 * extraction.
3168 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3169 */
3170DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
3171 bool f64Bit = true)
3172{
3173 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
3174 return ((uint32_t)f64Bit << 31)
3175 | UINT32_C(0x13800000)
3176 | ((uint32_t)f64Bit << 22) /*N*/
3177 | (iRegHigh << 16)
3178 | (uLsb << 10)
3179 | (iRegLow << 5)
3180 | iRegResult;
3181}
3182
3183
3184/** A64: Rotates the value of a register (alias for EXTR). */
3185DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3186{
3187 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
3188}
3189
3190
3191/**
3192 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
3193 *
3194 * @returns The encoded instruction.
3195 * @param fSub true for sub and subs, false for add and
3196 * adds.
3197 * @param iRegResult The register to store the result in.
3198 * SP is valid when @a fSetFlags = false,
3199 * and ZR is valid otherwise.
3200 * @param iRegSrc The register containing the augend (@a fSub
3201 * = false) or minuend (@a fSub = true). SP is
3202 * a valid registers for all variations.
3203 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
3204 * (@a fSub = true).
3205 * @param f64Bit true for 64-bit GRPs (default), false for
3206 * 32-bit GPRs.
3207 * @param fSetFlags Whether to set flags (adds / subs) or not
3208 * (add / sub - default).
3209 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
3210 * bits to the left, or not (default).
3211 */
3212DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
3213 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
3214 bool fSetFlags = false, bool fShift12 = false)
3215{
3216 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
3217 return ((uint32_t)f64Bit << 31)
3218 | ((uint32_t)fSub << 30)
3219 | ((uint32_t)fSetFlags << 29)
3220 | UINT32_C(0x11000000)
3221 | ((uint32_t)fShift12 << 22)
3222 | (uImm12AddendSubtrahend << 10)
3223 | (iRegSrc << 5)
3224 | iRegResult;
3225}
3226
3227
3228/** Alias for sub zxr, reg, \#uimm12. */
3229DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
3230 bool f64Bit = true, bool fShift12 = false)
3231{
3232 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
3233 f64Bit, true /*fSetFlags*/, fShift12);
3234}
3235
3236
3237/** ADD dst, src, \#uimm12 */
3238DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
3239 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3240{
3241 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
3242}
3243
3244
3245/** SUB dst, src, \#uimm12 */
3246DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
3247 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3248{
3249 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
3250}
3251
3252
3253/**
3254 * A64: Encodes either add, adds, sub or subs with shifted register.
3255 *
3256 * @returns The encoded instruction.
3257 * @param fSub true for sub and subs, false for add and
3258 * adds.
3259 * @param iRegResult The register to store the result in.
3260 * SP is NOT valid, but ZR is.
3261 * @param iRegSrc1 The register containing the augend (@a fSub
3262 * = false) or minuend (@a fSub = true).
3263 * SP is NOT valid, but ZR is.
3264 * @param iRegSrc2 The register containing the addened (@a fSub
3265 * = false) or subtrahend (@a fSub = true).
3266 * SP is NOT valid, but ZR is.
3267 * @param f64Bit true for 64-bit GRPs (default), false for
3268 * 32-bit GPRs.
3269 * @param fSetFlags Whether to set flags (adds / subs) or not
3270 * (add / sub - default).
3271 * @param cShift The shift count to apply to @a iRegSrc2.
3272 * @param enmShift The shift type to apply to the @a iRegSrc2
3273 * register. kArmv8A64InstrShift_Ror is
3274 * reserved.
3275 */
3276DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3277 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3278 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3279{
3280 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3281 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
3282
3283 return ((uint32_t)f64Bit << 31)
3284 | ((uint32_t)fSub << 30)
3285 | ((uint32_t)fSetFlags << 29)
3286 | UINT32_C(0x0b000000)
3287 | ((uint32_t)enmShift << 22)
3288 | (iRegSrc2 << 16)
3289 | (cShift << 10)
3290 | (iRegSrc1 << 5)
3291 | iRegResult;
3292}
3293
3294
3295/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
3296DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
3297 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3298{
3299 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
3300 f64Bit, true /*fSetFlags*/, cShift, enmShift);
3301}
3302
3303
3304/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3305DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3306 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3307 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3308{
3309 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3310}
3311
3312
3313/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3314DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3315 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3316 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3317{
3318 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3319}
3320
3321
3322/** NEG dst */
3323DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
3324{
3325 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
3326}
3327
3328
3329/** Extension option for 'extended register' instructions. */
3330typedef enum ARMV8A64INSTREXTEND
3331{
3332 kArmv8A64InstrExtend_UxtB = 0,
3333 kArmv8A64InstrExtend_UxtH,
3334 kArmv8A64InstrExtend_UxtW,
3335 kArmv8A64InstrExtend_UxtX,
3336 kArmv8A64InstrExtend_SxtB,
3337 kArmv8A64InstrExtend_SxtH,
3338 kArmv8A64InstrExtend_SxtW,
3339 kArmv8A64InstrExtend_SxtX,
3340 /** The default is either UXTW or UXTX depending on whether the instruction
3341 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
3342 * to the f64Bit value. */
3343 kArmv8A64InstrExtend_Default
3344} ARMV8A64INSTREXTEND;
3345
3346
3347/**
3348 * A64: Encodes either add, adds, sub or subs with extended register encoding.
3349 *
3350 * @returns The encoded instruction.
3351 * @param fSub true for sub and subs, false for add and
3352 * adds.
3353 * @param iRegResult The register to store the result in.
3354 * SP is NOT valid, but ZR is.
3355 * @param iRegSrc1 The register containing the augend (@a fSub
3356 * = false) or minuend (@a fSub = true).
3357 * SP is valid, but ZR is NOT.
3358 * @param iRegSrc2 The register containing the addened (@a fSub
3359 * = false) or subtrahend (@a fSub = true).
3360 * SP is NOT valid, but ZR is.
3361 * @param f64Bit true for 64-bit GRPs (default), false for
3362 * 32-bit GPRs.
3363 * @param fSetFlags Whether to set flags (adds / subs) or not
3364 * (add / sub - default).
3365 * @param enmExtend The type of extension to apply to @a
3366 * iRegSrc2.
3367 * @param cShift The left shift count to apply to @a iRegSrc2
3368 * after enmExtend processing is done.
3369 * Max shift is 4 for some reason.
3370 */
3371DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3372 bool f64Bit = true, bool fSetFlags = false,
3373 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
3374 uint32_t cShift = 0)
3375{
3376 if (enmExtend == kArmv8A64InstrExtend_Default)
3377 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
3378 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
3379
3380 return ((uint32_t)f64Bit << 31)
3381 | ((uint32_t)fSub << 30)
3382 | ((uint32_t)fSetFlags << 29)
3383 | UINT32_C(0x0b200000)
3384 | (iRegSrc2 << 16)
3385 | ((uint32_t)enmExtend << 13)
3386 | (cShift << 10)
3387 | (iRegSrc1 << 5)
3388 | iRegResult;
3389}
3390
3391
3392/**
3393 * A64: Encodes a B (unconditional branch w/ imm) instruction.
3394 *
3395 * @returns The encoded instruction.
3396 * @param iImm26 Signed number of instruction to jump (i.e. *4).
3397 */
3398DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
3399{
3400 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
3401 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
3402}
3403
3404
3405/**
3406 * A64: Encodes a BL (unconditional call w/ imm) instruction.
3407 *
3408 * @returns The encoded instruction.
3409 * @param iImm26 Signed number of instruction to jump (i.e. *4).
3410 */
3411DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
3412{
3413 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
3414}
3415
3416
3417/**
3418 * A64: Encodes a BR (unconditional branch w/ register) instruction.
3419 *
3420 * @returns The encoded instruction.
3421 * @param iReg The register containing the target address.
3422 */
3423DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
3424{
3425 Assert(iReg < 32);
3426 return UINT32_C(0xd61f0000) | (iReg << 5);
3427}
3428
3429
3430/**
3431 * A64: Encodes a BLR instruction.
3432 *
3433 * @returns The encoded instruction.
3434 * @param iReg The register containing the target address.
3435 */
3436DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
3437{
3438 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
3439}
3440
3441
3442/**
3443 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
3444 *
3445 * @returns The encoded instruction.
3446 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
3447 * its not zero.
3448 * @param iImm19 Signed number of instruction to jump (i.e. *4).
3449 * @param iReg The GPR to check for zero / non-zero value.
3450 * @param f64Bit true for 64-bit register, false for 32-bit.
3451 */
3452DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
3453{
3454 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
3455 return ((uint32_t)f64Bit << 31)
3456 | UINT32_C(0x34000000)
3457 | ((uint32_t)fJmpIfNotZero << 24)
3458 | (((uint32_t)iImm19 & 0x7ffff) << 5)
3459 | iReg;
3460}
3461
3462
3463/**
3464 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
3465 *
3466 * @returns The encoded instruction.
3467 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
3468 * its not zero.
3469 * @param iImm14 Signed number of instruction to jump (i.e. *4).
3470 * @param iReg The GPR to check for zero / non-zero value.
3471 * @param iBitNo The bit to test for.
3472 */
3473DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
3474{
3475 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
3476 return ((uint32_t)(iBitNo & 0x20) << (31-5))
3477 | UINT32_C(0x36000000)
3478 | ((uint32_t)fJmpIfNotZero << 24)
3479 | ((iBitNo & 0x1f) << 19)
3480 | (((uint32_t)iImm14 & 0x3fff) << 5)
3481 | iReg;
3482}
3483
3484
3485
3486/** Armv8 Condition codes. */
3487typedef enum ARMV8INSTRCOND
3488{
3489 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
3490 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
3491
3492 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
3493 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
3494 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
3495 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
3496
3497 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
3498 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
3499
3500 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
3501 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
3502
3503 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
3504 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
3505
3506 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
3507 kArmv8InstrCond_Lt, /**< b - Signed less than. */
3508
3509 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
3510 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
3511
3512 kArmv8InstrCond_Al, /**< e - Condition is always true. */
3513 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
3514} ARMV8INSTRCOND;
3515
3516/**
3517 * A64: Encodes conditional branch instruction w/ immediate target.
3518 *
3519 * @returns The encoded instruction.
3520 * @param enmCond The branch condition.
3521 * @param iImm19 Signed number of instruction to jump (i.e. *4).
3522 */
3523DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
3524{
3525 Assert((unsigned)enmCond < 16);
3526 return UINT32_C(0x54000000)
3527 | (((uint32_t)iImm19 & 0x7ffff) << 5)
3528 | (uint32_t)enmCond;
3529}
3530
3531
3532/**
3533 * A64: Encodes the BRK instruction.
3534 *
3535 * @returns The encoded instruction.
3536 * @param uImm16 Unsigned immediate value.
3537 */
3538DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
3539{
3540 Assert(uImm16 < _64K);
3541 return UINT32_C(0xd4200000)
3542 | (uImm16 << 5);
3543}
3544
3545/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
3546 * @{ */
3547#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
3548#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
3549#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
3550#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
3551#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
3552#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
3553#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
3554#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
3555
3556#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
3557#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
3558#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
3559#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
3560#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
3561#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
3562#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
3563#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
3564/** @} */
3565
3566/**
3567 * A64: Encodes CCMP or CCMN with two register operands.
3568 *
3569 * @returns The encoded instruction.
3570 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
3571 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
3572 * @param fNzcv The N, Z, C & V flags values to load if the condition
3573 * does not match. See RMA64_NZCV_F_XXX.
3574 * @param enmCond The condition guarding the compare.
3575 * @param fCCmp Set for CCMP (default), clear for CCMN.
3576 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3577 */
3578DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
3579 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
3580{
3581 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
3582
3583 return ((uint32_t)f64Bit << 31)
3584 | ((uint32_t)fCCmp << 30)
3585 | UINT32_C(0x3a400000)
3586 | (iRegSrc2 << 16)
3587 | ((uint32_t)enmCond << 12)
3588 | (iRegSrc1 << 5)
3589 | fNzcv;
3590}
3591
3592/** CCMP w/ reg. */
3593DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
3594 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3595{
3596 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
3597}
3598
3599
3600/** CCMN w/ reg. */
3601DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
3602 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3603{
3604 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
3605}
3606
3607
3608/**
3609 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
3610 *
3611 * @returns The encoded instruction.
3612 * @param iRegSrc The register. SP is NOT valid, but ZR is.
3613 * @param uImm5 The immediate, to compare iRegSrc with.
3614 * @param fNzcv The N, Z, C & V flags values to load if the condition
3615 * does not match. See RMA64_NZCV_F_XXX.
3616 * @param enmCond The condition guarding the compare.
3617 * @param fCCmp Set for CCMP (default), clear for CCMN.
3618 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3619 */
3620DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
3621 bool fCCmp = true, bool f64Bit = true)
3622{
3623 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
3624
3625 return ((uint32_t)f64Bit << 31)
3626 | ((uint32_t)fCCmp << 30)
3627 | UINT32_C(0x3a400800)
3628 | (uImm5 << 16)
3629 | ((uint32_t)enmCond << 12)
3630 | (iRegSrc << 5)
3631 | fNzcv;
3632}
3633
3634/** CCMP w/ immediate. */
3635DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
3636 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3637{
3638 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
3639}
3640
3641
3642/** CCMN w/ immediate. */
3643DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
3644 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3645{
3646 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
3647}
3648
3649
3650/**
3651 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
3652 *
3653 * @returns The encoded instruction.
3654 * @param uOp Opcode bit 30.
3655 * @param uOp2 Opcode bits 11:10.
3656 * @param iRegResult The result register. SP is NOT valid, but ZR is.
3657 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
3658 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
3659 * @param enmCond The condition guarding the compare.
3660 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3661 */
3662DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
3663 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
3664{
3665 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3666
3667 return ((uint32_t)f64Bit << 31)
3668 | (uOp << 30)
3669 | UINT32_C(0x1a800000)
3670 | (iRegSrc2 << 16)
3671 | ((uint32_t)enmCond << 12)
3672 | (uOp2 << 10)
3673 | (iRegSrc1 << 5)
3674 | iRegResult;
3675}
3676
3677
3678/** A64: Encodes CSEL.
3679 * @see Armv8A64MkInstrCondSelect for details. */
3680DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3681 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3682{
3683 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
3684}
3685
3686
3687/** A64: Encodes CSINC.
3688 * @see Armv8A64MkInstrCondSelect for details. */
3689DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3690 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3691{
3692 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
3693}
3694
3695
3696/** A64: Encodes CSET.
3697 * @see Armv8A64MkInstrCondSelect for details. */
3698DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
3699{
3700 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
3701 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
3702 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
3703}
3704
3705
3706/** A64: Encodes CSINV.
3707 * @see Armv8A64MkInstrCondSelect for details. */
3708DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3709 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3710{
3711 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
3712}
3713
3714/** A64: Encodes CSETM.
3715 * @see Armv8A64MkInstrCondSelect for details. */
3716DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
3717{
3718 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
3719 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
3720 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
3721}
3722
3723
3724/** A64: Encodes CSNEG.
3725 * @see Armv8A64MkInstrCondSelect for details. */
3726DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3727 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3728{
3729 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
3730}
3731
3732
3733/**
3734 * A64: Encodes REV instruction.
3735 *
3736 * @returns The encoded instruction.
3737 * @param iRegDst The destination register. SP is NOT valid.
3738 * @param iRegSrc The source register. SP is NOT valid, but ZR is
3739 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3740 */
3741DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
3742{
3743 Assert(iRegDst < 32); Assert(iRegSrc < 32);
3744
3745 return ((uint32_t)f64Bit << 31)
3746 | (UINT32_C(0x5ac00800))
3747 | ((uint32_t)f64Bit << 10)
3748 | (iRegSrc << 5)
3749 | iRegDst;
3750}
3751
3752
3753/**
3754 * A64: Encodes REV16 instruction.
3755 *
3756 * @returns The encoded instruction.
3757 * @param iRegDst The destination register. SP is NOT valid.
3758 * @param iRegSrc The source register. SP is NOT valid, but ZR is
3759 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3760 */
3761DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
3762{
3763 Assert(iRegDst < 32); Assert(iRegSrc < 32);
3764
3765 return ((uint32_t)f64Bit << 31)
3766 | (UINT32_C(0x5ac00400))
3767 | (iRegSrc << 5)
3768 | iRegDst;
3769}
3770
3771
3772/** @} */
3773
3774#endif /* !dtrace && __cplusplus */
3775
3776/** @} */
3777
3778#endif /* !IPRT_INCLUDED_armv8_h */
3779
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