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source: vbox/trunk/include/iprt/armv8.h@ 103675

Last change on this file since 103675 was 103675, checked in by vboxsync, 9 months ago

VMM/IEM: Implemented iemNativeEmit_sub_r_r_efl and enabled it for both hosts. bugref:10376
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/types.h>
44# include <iprt/assert.h>
45#else
46# pragma D depends_on library vbox-types.d
47#endif
48
49/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
50 * @ingroup grp_rt
51 * @{
52 */
53
54/** @name The AArch64 register encoding - deprecated.
55 * @deprecated Use ARMV8_A64_REG_XXX instead.
56 * @todo correct code and drop these remaining ones.
57 * @{ */
58#define ARMV8_AARCH64_REG_X0 0
59#define ARMV8_AARCH64_REG_X1 1
60#define ARMV8_AARCH64_REG_X2 2
61#define ARMV8_AARCH64_REG_X3 3
62#define ARMV8_AARCH64_REG_ZR 31
63/** @} */
64
65/** @name The AArch64 general purpose register encoding.
66 * @{ */
67#define ARMV8_A64_REG_X0 0
68#define ARMV8_A64_REG_X1 1
69#define ARMV8_A64_REG_X2 2
70#define ARMV8_A64_REG_X3 3
71#define ARMV8_A64_REG_X4 4
72#define ARMV8_A64_REG_X5 5
73#define ARMV8_A64_REG_X6 6
74#define ARMV8_A64_REG_X7 7
75#define ARMV8_A64_REG_X8 8
76#define ARMV8_A64_REG_X9 9
77#define ARMV8_A64_REG_X10 10
78#define ARMV8_A64_REG_X11 11
79#define ARMV8_A64_REG_X12 12
80#define ARMV8_A64_REG_X13 13
81#define ARMV8_A64_REG_X14 14
82#define ARMV8_A64_REG_X15 15
83#define ARMV8_A64_REG_X16 16
84#define ARMV8_A64_REG_X17 17
85#define ARMV8_A64_REG_X18 18
86#define ARMV8_A64_REG_X19 19
87#define ARMV8_A64_REG_X20 20
88#define ARMV8_A64_REG_X21 21
89#define ARMV8_A64_REG_X22 22
90#define ARMV8_A64_REG_X23 23
91#define ARMV8_A64_REG_X24 24
92#define ARMV8_A64_REG_X25 25
93#define ARMV8_A64_REG_X26 26
94#define ARMV8_A64_REG_X27 27
95#define ARMV8_A64_REG_X28 28
96#define ARMV8_A64_REG_X29 29
97#define ARMV8_A64_REG_X30 30
98/** @} */
99
100/** @name The AArch64 32-bit general purpose register names.
101 * @{ */
102#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
103#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
104#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
105#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
106#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
107#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
108#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
109#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
110#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
111#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
112#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
113#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
114#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
115#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
116#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
117#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
118#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
119#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
120#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
121#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
122#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
123#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
124#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
125#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
126#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
127#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
128#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
129#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
130#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
131#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
132#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
133/** @} */
134
135/** @name The AArch64 register 31.
136 * @note Register 31 typically refers to the zero register, but can also in
137 * select case (by instruction and opecode field) refer the to stack
138 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
139 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
140 * 31 will be the zero register.
141 * @{ */
142/** The stack pointer. */
143#define ARMV8_A64_REG_SP 31
144/** The zero register. Reads as zero, writes ignored. */
145#define ARMV8_A64_REG_XZR 31
146/** The zero register, the 32-bit register name. */
147#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
148/** @} */
149
150/** @name AArch64 register aliases
151 * @{ */
152/** The link register is typically mapped to x30 as that's the default pick of
153 * the RET instruction. */
154#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
155/** Frame base pointer is typically mapped to x29. */
156#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
157/** @} */
158
159
160/** @name System register encoding.
161 * @{
162 */
163/** Mask for the op0 part of an MSR/MRS instruction */
164#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
165/** Shift for the op0 part of an MSR/MRS instruction */
166#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
167/** Returns the op0 part of the given MRS/MSR instruction. */
168#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
169/** Mask for the op1 part of an MSR/MRS instruction */
170#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
171/** Shift for the op1 part of an MSR/MRS instruction */
172#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
173/** Returns the op1 part of the given MRS/MSR instruction. */
174#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
175/** Mask for the CRn part of an MSR/MRS instruction */
176#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
177 | RT_BIT_32(15) )
178/** Shift for the CRn part of an MSR/MRS instruction */
179#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
180/** Returns the CRn part of the given MRS/MSR instruction. */
181#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
182/** Mask for the CRm part of an MSR/MRS instruction */
183#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
184 | RT_BIT_32(11) )
185/** Shift for the CRm part of an MSR/MRS instruction */
186#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
187/** Returns the CRn part of the given MRS/MSR instruction. */
188#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
189/** Mask for the op2 part of an MSR/MRS instruction */
190#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
191/** Shift for the op2 part of an MSR/MRS instruction */
192#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
193/** Returns the op2 part of the given MRS/MSR instruction. */
194#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
195/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
196#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
197 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
198 | ARMV8_AARCH64_SYSREG_OP2_MASK)
199/** @} */
200
201/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
202 * IPRT specific and not part of the ARMv8 specification.
203 * @{ */
204#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
205 UINT16_C( (((a_Op0) & 0x3) << 14) \
206 | (((a_Op1) & 0x7) << 11) \
207 | (((a_CRn) & 0xf) << 7) \
208 | (((a_CRm) & 0xf) << 3) \
209 | ((a_Op2) & 0x7))
210/** Returns the internal system register ID from the given MRS/MSR instruction. */
211#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
212 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
213 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
214 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
215 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
216 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
217/** Encodes the given system register ID in the given MSR/MRS instruction. */
218#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
219 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
220/** @} */
221
222
223/** @name System register IDs.
224 * @{ */
225/** OSLAR_EL1 register - WO. */
226#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
227/** OSLSR_EL1 register - RO. */
228#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
229/** OSDLR_EL1 register - RW. */
230#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
231
232/** MIDR_EL1 register - RO. */
233#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
234/** MIPDR_EL1 register - RO. */
235#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
236/** REVIDR_EL1 register - RO. */
237#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
238/** ID_PFR0_EL1 register - RO. */
239#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
240/** ID_PFR1_EL1 register - RO. */
241#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
242/** ID_DFR0_EL1 register - RO. */
243#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
244/** ID_AFR0_EL1 register - RO. */
245#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
246/** ID_MMFR0_EL1 register - RO. */
247#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
248/** ID_MMFR1_EL1 register - RO. */
249#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
250/** ID_MMFR2_EL1 register - RO. */
251#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
252/** ID_MMFR3_EL1 register - RO. */
253#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
254
255/** ID_ISAR0_EL1 register - RO. */
256#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
257/** ID_ISAR1_EL1 register - RO. */
258#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
259/** ID_ISAR2_EL1 register - RO. */
260#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
261/** ID_ISAR3_EL1 register - RO. */
262#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
263/** ID_ISAR4_EL1 register - RO. */
264#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
265/** ID_ISAR5_EL1 register - RO. */
266#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
267/** ID_MMFR4_EL1 register - RO. */
268#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
269/** ID_ISAR6_EL1 register - RO. */
270#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
271
272/** MVFR0_EL1 register - RO. */
273#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
274/** MVFR1_EL1 register - RO. */
275#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
276/** MVFR2_EL1 register - RO. */
277#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
278/** ID_PFR2_EL1 register - RO. */
279#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
280/** ID_DFR1_EL1 register - RO. */
281#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
282/** ID_MMFR5_EL1 register - RO. */
283#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
284
285/** ID_AA64PFR0_EL1 register - RO. */
286#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
287/** ID_AA64PFR0_EL1 register - RO. */
288#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
289/** ID_AA64ZFR0_EL1 register - RO. */
290#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
291/** ID_AA64SMFR0_EL1 register - RO. */
292#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
293
294/** ID_AA64DFR0_EL1 register - RO. */
295#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
296/** ID_AA64DFR0_EL1 register - RO. */
297#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
298/** ID_AA64AFR0_EL1 register - RO. */
299#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
300/** ID_AA64AFR1_EL1 register - RO. */
301#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
302
303/** ID_AA64ISAR0_EL1 register - RO. */
304#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
305/** ID_AA64ISAR1_EL1 register - RO. */
306#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
307/** ID_AA64ISAR2_EL1 register - RO. */
308#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
309
310/** ID_AA64MMFR0_EL1 register - RO. */
311#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
312/** ID_AA64MMFR1_EL1 register - RO. */
313#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
314/** ID_AA64MMFR2_EL1 register - RO. */
315#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
316
317/** SCTRL_EL1 register - RW. */
318#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
319/** ACTRL_EL1 register - RW. */
320#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
321/** CPACR_EL1 register - RW. */
322#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
323/** RGSR_EL1 register - RW. */
324#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
325/** GCR_EL1 register - RW. */
326#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
327
328/** ZCR_EL1 register - RW. */
329#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
330/** TRFCR_EL1 register - RW. */
331#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
332/** SMPRI_EL1 register - RW. */
333#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
334/** SMCR_EL1 register - RW. */
335#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
336
337/** TTBR0_EL1 register - RW. */
338#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
339/** TTBR1_EL1 register - RW. */
340#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
341/** TCR_EL1 register - RW. */
342#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
343
344/** @todo APIA,APIB,APDA,APDB,APGA registers. */
345
346/** SPSR_EL1 register - RW. */
347#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
348/** ELR_EL1 register - RW. */
349#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
350
351/** SP_EL0 register - RW. */
352#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
353
354/** PSTATE.SPSel value. */
355#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
356/** PSTATE.CurrentEL value. */
357#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
358/** PSTATE.PAN value. */
359#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
360/** PSTATE.UAO value. */
361#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
362
363/** PSTATE.ALLINT value. */
364#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
365
366/** ICC_PMR_EL1 register - RW. */
367#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
368
369/** AFSR0_EL1 register - RW. */
370#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
371/** AFSR1_EL1 register - RW. */
372#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
373
374/** ESR_EL1 register - RW. */
375#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
376
377/** ERRIDR_EL1 register - RO. */
378#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
379/** ERRSELR_EL1 register - RW. */
380#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
381
382/** ICC_IAR0_EL1 register - RO. */
383#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
384/** ICC_EOIR0_EL1 register - WO. */
385#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
386/** ICC_HPPIR0_EL1 register - WO. */
387#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
388/** ICC_BPR0_EL1 register - RW. */
389#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
390/** ICC_AP0R0_EL1 register - RW. */
391#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
392/** ICC_AP0R1_EL1 register - RW. */
393#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
394/** ICC_AP0R2_EL1 register - RW. */
395#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
396/** ICC_AP0R3_EL1 register - RW. */
397#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
398
399/** ICC_AP1R0_EL1 register - RW. */
400#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
401/** ICC_AP1R1_EL1 register - RW. */
402#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
403/** ICC_AP1R2_EL1 register - RW. */
404#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
405/** ICC_AP1R3_EL1 register - RW. */
406#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
407/** ICC_NMIAR1_EL1 register - RO. */
408#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
409
410/** ICC_DIR_EL1 register - WO. */
411#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
412/** ICC_RPR_EL1 register - RO. */
413#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
414/** ICC_SGI1R_EL1 register - WO. */
415#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
416/** ICC_ASGI1R_EL1 register - WO. */
417#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
418/** ICC_SGI0R_EL1 register - WO. */
419#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
420
421/** ICC_IAR1_EL1 register - RO. */
422#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
423/** ICC_EOIR1_EL1 register - WO. */
424#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
425/** ICC_HPPIR1_EL1 register - RO. */
426#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
427/** ICC_BPR1_EL1 register - RW. */
428#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
429/** ICC_CTLR_EL1 register - RW. */
430#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
431/** ICC_SRE_EL1 register - RW. */
432#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
433/** ICC_IGRPEN0_EL1 register - RW. */
434#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
435/** ICC_IGRPEN1_EL1 register - RW. */
436#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
437
438/** NZCV - Status Flags - ??. */
439#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
440/** DAIF - Interrupt Mask Bits - ??. */
441#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
442/** SVCR - Streaming Vector Control Register - ??. */
443#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
444/** DIT - Data Independent Timing - ??. */
445#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
446/** SSBS - Speculative Store Bypass Safe - ??. */
447#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
448/** TCO - Tag Check Override - ??. */
449#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
450
451/** CNTV_CTL_EL0 register - RW. */
452#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
453/** @} */
454
455
456/**
457 * SPSR_EL2 (according to chapter C5.2.19)
458 */
459typedef union ARMV8SPSREL2
460{
461 /** The plain unsigned view. */
462 uint64_t u;
463 /** The 8-bit view. */
464 uint8_t au8[8];
465 /** The 16-bit view. */
466 uint16_t au16[4];
467 /** The 32-bit view. */
468 uint32_t au32[2];
469 /** The 64-bit view. */
470 uint64_t u64;
471} ARMV8SPSREL2;
472/** Pointer to SPSR_EL2. */
473typedef ARMV8SPSREL2 *PARMV8SPSREL2;
474/** Pointer to const SPSR_EL2. */
475typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
476
477
478/** @name SPSR_EL2 (When exception is taken from AArch64 state)
479 * @{
480 */
481/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
482#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
483#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
484/** Bit 0 - SP - Selected stack pointer. */
485#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
486#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
487/** Bit 1 - Reserved (read as zero). */
488#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
489/** Bit 2 - 3 - EL - Exception level. */
490#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
491#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
492#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
493#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
494/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
495#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
496#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
497/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
498#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
499#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
500/** Bit 6 - I - FIQ interrupt mask. */
501#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
502#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
503/** Bit 7 - I - IRQ interrupt mask. */
504#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
505#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
506/** Bit 8 - A - SError interrupt mask. */
507#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
508#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
509/** Bit 9 - D - Debug Exception mask. */
510#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
511#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
512/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
513#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
514#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
515#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
516/** Bit 12 - SSBS - Speculative Store Bypass. */
517#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
518#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
519/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
520#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
521#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
522/** Bit 14 - 19 - Reserved (read as zero). */
523#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
524 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
525/** Bit 20 - IL - Illegal Execution State flag. */
526#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
527#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
528/** Bit 21 - SS - Software Step flag. */
529#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
530#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
531/** Bit 22 - PAN - Privileged Access Never flag. */
532#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
533#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
534/** Bit 23 - UAO - User Access Override flag. */
535#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
536#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
537/** Bit 24 - DIT - Data Independent Timing flag. */
538#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
539#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
540/** Bit 25 - TCO - Tag Check Override flag. */
541#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
542#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
543/** Bit 26 - 27 - Reserved (read as zero). */
544#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
545/** Bit 28 - V - Overflow condition flag. */
546#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
547#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
548/** Bit 29 - C - Carry condition flag. */
549#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
550#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
551/** Bit 30 - Z - Zero condition flag. */
552#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
553#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
554/** Bit 31 - N - Negative condition flag. */
555#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
556#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
557/** Bit 32 - 63 - Reserved (read as zero). */
558#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
559/** Checks whether the given SPSR value contains a AARCH64 execution state. */
560#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
561/** @} */
562
563/** @name Aarch64 Exception levels
564 * @{ */
565/** Exception Level 0 - User mode. */
566#define ARMV8_AARCH64_EL_0 0
567/** Exception Level 1 - Supervisor mode. */
568#define ARMV8_AARCH64_EL_1 1
569/** Exception Level 2 - Hypervisor mode. */
570#define ARMV8_AARCH64_EL_2 2
571/** @} */
572
573
574/** @name ESR_EL2 (Exception Syndrome Register, EL2)
575 * @{
576 */
577/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
578#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
579#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
580/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
581#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
582#define ARMV8_ESR_EL2_IL_BIT 25
583#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
584#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
585/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
586#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
587 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
588#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
589/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
590#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
591 | RT_BIT_64(35) | RT_BIT_64(36))
592#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
593/** @} */
594
595
596/** @name ESR_EL2 Exception Classes (EC)
597 * @{ */
598/** Unknown exception reason. */
599#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
600/** Trapped WF* instruction. */
601#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
602/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
603#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
604/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
605#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
606/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
607#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
608/** AArch32 - Trapped LDC or STC access. */
609#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
610/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
611#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
612/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
613#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
614/** AArch32 - Trapped pointer authentication instruction. */
615#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
616/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
617#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
618/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
619#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
620/** FEAT_BTI - Branch Target Exception. */
621#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
622/** Illegal Execution State. */
623#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
624/** AArch32 - SVC instruction execution. */
625#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
626/** AArch32 - HVC instruction execution. */
627#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
628/** AArch32 - SMC instruction execution. */
629#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
630/** AArch64 - SVC instruction execution. */
631#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
632/** AArch64 - HVC instruction execution. */
633#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
634/** AArch64 - SMC instruction execution. */
635#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
636/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
637#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
638/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
639#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
640/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
641#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
642/** FEAT_TME - Exception from TSTART instruction. */
643#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
644/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
645#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
646/** FEAT_SME - Access to SME functionality trapped. */
647#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
648/** FEAT_RME - Exception from Granule Protection Check. */
649#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
650/** Instruction Abort from a lower Exception level. */
651#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
652/** Instruction Abort from the same Exception level. */
653#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
654/** PC alignment fault exception. */
655#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
656/** Data Abort from a lower Exception level. */
657#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
658/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
659#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
660/** SP alignment fault exception. */
661#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
662/** FEAT_MOPS - Memory Operation Exception. */
663#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
664/** AArch32 - Trapped floating point exception. */
665#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
666/** AArch64 - Trapped floating point exception. */
667#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
668/** SError interrupt. */
669#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
670/** Breakpoint Exception from a lower Exception level. */
671#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
672/** Breakpoint Exception from the same Exception level. */
673#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
674/** Software Step Exception from a lower Exception level. */
675#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
676/** Software Step Exception from the same Exception level. */
677#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
678/** Watchpoint Exception from a lower Exception level. */
679#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
680/** Watchpoint Exception from the same Exception level. */
681#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
682/** AArch32 - BKPT instruction execution. */
683#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
684/** AArch32 - Vector Catch exception. */
685#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
686/** AArch64 - BRK instruction execution. */
687#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
688/** @} */
689
690
691/** @name ISS encoding for Data Abort exceptions.
692 * @{ */
693/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
694#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
695 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
696#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
697/** Bit 6 - WnR - Write not Read. */
698#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
699#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
700/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
701#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
702#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
703/** Bit 8 - CM - Cache maintenance instruction. */
704#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
705#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
706/** Bit 9 - EA - External abort type. */
707#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
708#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
709/** Bit 10 - FnV - FAR not Valid. */
710#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
711#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
712/** Bit 11 - 12 - LST - Load/Store Type. */
713#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
714#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
715/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
716#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
717#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
718/** Bit 14 - AR - Acquire/Release semantics. */
719#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
720#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
721/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
722#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
723#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
724/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
725#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
726 | RT_BIT_32(19) | RT_BIT_32(20))
727#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
728/** Bit 21 - SSE - Syndrome Sign Extend. */
729#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
730#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
731/** Bit 22 - 23 - SAS - Syndrome Access Size. */
732#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
733#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
734/** Bit 24 - ISV - Instruction Syndrome Valid. */
735#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
736#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
737/** @} */
738
739
740/** @name Data Fault Status Code (DFSC).
741 * @{ */
742/** Address size fault, level 0 of translation or translation table base register. */
743#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
744/** Address size fault, level 1. */
745#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
746/** Address size fault, level 2. */
747#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
748/** Address size fault, level 3. */
749#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
750/** Translation fault, level 0. */
751#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
752/** Translation fault, level 1. */
753#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
754/** Translation fault, level 2. */
755#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
756/** Translation fault, level 3. */
757#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
758/** FEAT_LPA2 - Access flag fault, level 0. */
759#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
760/** Access flag fault, level 1. */
761#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
762/** Access flag fault, level 2. */
763#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
764/** Access flag fault, level 3. */
765#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
766/** FEAT_LPA2 - Permission fault, level 0. */
767#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
768/** Permission fault, level 1. */
769#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
770/** Permission fault, level 2. */
771#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
772/** Permission fault, level 3. */
773#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
774/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
775#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
776/** FEAT_MTE2 - Synchronous Tag Check Fault. */
777#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
778/** @todo Do the rest (lazy developer). */
779/** @} */
780
781
782/** @name SAS encoding.
783 * @{ */
784/** Byte access. */
785#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
786/** Halfword access (uint16_t). */
787#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
788/** Word access (uint32_t). */
789#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
790/** Doubleword access (uint64_t). */
791#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
792/** @} */
793
794
795/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
796 * @{ */
797/** Bit 0 - Direction flag. */
798#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
799#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
800/** Bit 1 - 4 - CRm value from the instruction. */
801#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
802 | RT_BIT_32(4))
803#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
804/** Bit 5 - 9 - Rt value from the instruction. */
805#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
806 | RT_BIT_32(8) | RT_BIT_32(9))
807#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
808/** Bit 10 - 13 - CRn value from the instruction. */
809#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
810 | RT_BIT_32(13))
811#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
812/** Bit 14 - 16 - Op2 value from the instruction. */
813#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
814#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
815/** Bit 17 - 19 - Op2 value from the instruction. */
816#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
817#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
818/** Bit 20 - 21 - Op0 value from the instruction. */
819#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
820#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
821/** Bit 22 - 24 - Reserved. */
822#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
823/** @} */
824
825
826/** @name ISS encoding for trapped HVC instruction exceptions.
827 * @{ */
828/** Bit 0 - 15 - imm16 value of the instruction. */
829#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
830#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
831/** @} */
832
833
834/** @name TCR_EL1 - Translation Control Register (EL1)
835 * @{
836 */
837/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
838#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
839 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
840#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
841/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
842#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
843#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
844/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
845#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
846#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
847/** Non cacheable. */
848# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
849/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
850# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
851/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
852# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
853/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
854# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
855/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
856#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
857#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
858/** Non cacheable. */
859# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
860/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
861# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
862/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
863# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
864/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
865# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
866/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
867#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
868#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
869/** Non shareable. */
870# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
871/** Invalid value. */
872# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
873/** Outer Shareable. */
874# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
875/** Inner Shareable. */
876# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
877/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
878#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15))
879#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
880/** Invalid granule size. */
881# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
882/** 16KiB granule size. */
883# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
884/** 4KiB granule size. */
885# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
886/** 64KiB granule size. */
887# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
888/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
889#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
890 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
891#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
892/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
893#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
894#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
895/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
896#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
897#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
898/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
899#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
900#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
901/** Non cacheable. */
902# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
903/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
904# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
905/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
906# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
907/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
908# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
909/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
910#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
911#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
912/** Non cacheable. */
913# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
914/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
915# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
916/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
917# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
918/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
919# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
920/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
921#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
922#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
923/** Non shareable. */
924# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
925/** Invalid value. */
926# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
927/** Outer Shareable. */
928# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
929/** Inner Shareable. */
930# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
931/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
932#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
933#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
934/** Invalid granule size. */
935# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
936/** 16KiB granule size. */
937# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
938/** 4KiB granule size. */
939# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
940/** 64KiB granule size. */
941# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
942/** Bit 32 - 34 - Intermediate Physical Address Size. */
943#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
944#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
945/** IPA - 32 bits, 4GiB. */
946# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
947/** IPA - 36 bits, 64GiB. */
948# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
949/** IPA - 40 bits, 1TiB. */
950# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
951/** IPA - 42 bits, 4TiB. */
952# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
953/** IPA - 44 bits, 16TiB. */
954# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
955/** IPA - 48 bits, 256TiB. */
956# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
957/** IPA - 52 bits, 4PiB. */
958# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
959/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
960#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
961#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
962/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
963#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
964#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
965/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
966#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
967#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
968/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
969#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
970#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
971/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
972#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
973#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
974/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
975#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
976#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
977/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
978#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
979#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
980/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
981#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
982#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
983/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
984#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
985#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
986/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
987#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
988#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
989/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
990#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
991#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
992/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
993#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
994#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
995/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
996#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
997#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
998/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
999#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1000#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1001/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1002#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1003#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1004/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1005#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1006#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1007/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1008#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1009#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1010/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1011#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1012#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1013/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1014#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1015#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1016/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1017#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1018#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1019/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1020#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1021#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1022/** Bit 57 - TCMA0 */
1023#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1024#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1025/** Bit 58 - TCMA1 */
1026#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1027#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1028/** Bit 59 - Data Sharing(?). */
1029#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1030#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1031/** @} */
1032
1033
1034/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1035 * @{
1036 */
1037/** Bit 0 - Common not Private (FEAT_TTCNP). */
1038#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1039#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1040/** Bit 1 - 47 - Translation table base address. */
1041#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1042#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1)
1043/** Bit 48 - 63 - ASID. */
1044#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1045#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1046/** @} */
1047
1048
1049/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1050 * @{ */
1051/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1052#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1053#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1054#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1055/** @} */
1056
1057
1058/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1059 * @{ */
1060/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1061#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1062#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1063#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1064/** @} */
1065
1066
1067/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1068 * @{ */
1069/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1070#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1071#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1072#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1073/** @} */
1074
1075
1076/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1077 * @{ */
1078/** Bit 0 - Common Binary Pointer Register - RW. */
1079#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1080#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1081/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1082#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1083#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1084/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1085#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1086#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1087/** Bit 8 - 10 - Priority bits - RO. */
1088#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1089#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1090/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1091#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1092#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1093/** INTIDS are 16-bit wide. */
1094# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1095/** INTIDS are 24-bit wide. */
1096# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1097/** Bit 14 - SEI Supported - RO. */
1098#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1099#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1100/** Bit 15 - Affinity 3 Valid - RO. */
1101#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1102#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1103/** Bit 18 - Range Selector Support - RO. */
1104#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1105#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1106/** Bit 19 - Extended INTID range supported - RO. */
1107#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1108#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1109/** All RW bits. */
1110#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1111/** All RO bits (including Res0). */
1112#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1113/** @} */
1114
1115
1116/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1117 * @{ */
1118/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1119#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1120#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1121/** @} */
1122
1123
1124/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1125 * @{ */
1126/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1127#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1128#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1129/** @} */
1130
1131
1132/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1133 * @{ */
1134/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1135#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1136#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1137/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1138#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1139#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1140/** Bit 24 - 27 - The INTID of the SGI. */
1141#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1142#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1143/* Bit 28 - 31 - Reserved. */
1144/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1145#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1146#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1147/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1148#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1149#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1150/* Bit 41 - 43 - Reserved. */
1151/** Bit 44 - 47 - Range selector. */
1152#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1153#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1154/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1155#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1156#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1157/* Bit 56 - 63 - Reserved. */
1158/** @} */
1159
1160
1161/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1162 * @{ */
1163/** Bit 0 - Enables the timer. */
1164#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1165#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1166/** Bit 1 - Timer interrupt mask bit. */
1167#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1168#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1169/** Bit 2 - Timer status bit. */
1170#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1171#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1172/** @} */
1173
1174
1175/** @name OSLAR_EL1 - OS Lock Access Register.
1176 * @{ */
1177/** Bit 0 - The OS Lock status bit. */
1178#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1179#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1180/** @} */
1181
1182
1183/** @name OSLSR_EL1 - OS Lock Status Register.
1184 * @{ */
1185/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1186#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1187#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1188/** Bit 1 - The OS Lock status bit. */
1189#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1190#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1191/** Bit 2 - Not 32-bit access. */
1192#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1193#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1194/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1195#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1196#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1197/** @} */
1198
1199
1200/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1201 * @{ */
1202/* Bit 0 - 3 - Reserved. */
1203/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1204#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1205#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1206/** No AES instructions implemented. */
1207# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1208/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1209# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1210/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1211# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1212/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1213#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1214#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1215/** No SHA1 instructions implemented. */
1216# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1217/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1218# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1219/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1220#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1221#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1222/** No SHA2 instructions implemented. */
1223# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1224/** SHA256 instructions implemented (FEAT_SHA256). */
1225# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1226/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1227# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1228/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1229#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1230#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1231/** No CRC32 instructions implemented. */
1232# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1233/** CRC32 instructions implemented (FEAT_CRC32). */
1234# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1235/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1236#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1237#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1238/** No Atomic instructions implemented. */
1239# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1240/** Atomic instructions implemented (FEAT_LSE). */
1241# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1242/** Bit 24 - 27 - Indicates support for TME instructions. */
1243#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1244#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1245/** TME instructions are not implemented. */
1246# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1247/** TME instructions are implemented. */
1248# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1249/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1250#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1251#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1252/** No RDMA instructions implemented. */
1253# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1254/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1255# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1256/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1257#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1258#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1259/** No SHA3 instructions implemented. */
1260# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1261/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1262# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1263/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1264#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1265#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1266/** No SM3 instructions implemented. */
1267# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1268/** SM3 instructions implemented (FEAT_SM3). */
1269# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1270/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1271#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1272#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1273/** No SM4 instructions implemented. */
1274# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1275/** SM4 instructions implemented (FEAT_SM4). */
1276# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1277/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1278#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1279#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1280/** No Dot Product instructions implemented. */
1281# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1282/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1283# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1284/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1285#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1286#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1287/** FMLAL and FMLSL instructions are not implemented. */
1288# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1289/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1290# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1291/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1292#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1293#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1294/** No flag manipulation instructions implemented. */
1295# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1296/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1297# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1298/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1299# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1300/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1301#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1302#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1303/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1304# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1305/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1306# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1307/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1308# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1309/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1310#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1311#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1312/** No Random Number instructions implemented. */
1313# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1314/** RNDR and RDNRRS registers are implemented . */
1315# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1316/** @} */
1317
1318
1319/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1320 * @{ */
1321/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1322#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1323#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1324/** DC CVAP not supported. */
1325# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1326/** DC CVAP supported (FEAT_DPB). */
1327# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1328/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1329# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1330/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1331#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1332#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1333/** Address Authentication using the QARMA5 algorithm is not implemented. */
1334# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1335/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1336# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1337/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1338# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1339/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1340# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1341/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1342# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1343/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1344# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1345/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1346#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1347#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1348/** Address Authentication using the QARMA5 algorithm is not implemented. */
1349# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1350/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1351# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1352/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1353# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1354/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1355# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1356/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1357# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1358/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1359# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1360/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1361#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1362#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1363/** No FJCVTZS instruction implemented. */
1364# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1365/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1366# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1367/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1368#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1369#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1370/** No FCMLA and FCADD instructions implemented. */
1371# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1372/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1373# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1374/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1375#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1376#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1377/** No RCpc instructions implemented. */
1378# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1379/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1380# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1381/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1382# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1383/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1384#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1385#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1386/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1387# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1388/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1389# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1390/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1391#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1392#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1393/** Generic Authentication using an implementation defined algorithm is not implemented. */
1394# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1395/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1396# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1397/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1398#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1399#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1400/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1401# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1402/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1403# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1404/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1405#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1406#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1407/** No SB instructions implemented. */
1408# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1409/** SB instructions implemented (FEAT_SB). */
1410# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1411/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1412#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1413#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1414/** Prediction invalidation instructions are not implemented. */
1415# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1416/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1417# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1418/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1419#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1420#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1421/** BFloat16 instructions are not implemented. */
1422# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1423/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1424# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1425/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1426# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1427/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1428#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1429#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1430/** Data Gathering Hint instructions are not implemented. */
1431# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1432/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1433# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1434/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1435#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1436#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1437/** No Int8 matrix multiplication instructions implemented. */
1438# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1439/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1440# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1441/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1442#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1443#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1444/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1445# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1446/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1447# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1448/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1449#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1450#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1451/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1452# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1453/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1454# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1455/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1456# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1457/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1458# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1459/** @} */
1460
1461
1462/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1463 * @{ */
1464/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1465#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1466#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1467/** WFET and WFIT are not supported. */
1468# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1469/** WFET and WFIT are supported (FEAT_WFxT). */
1470# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1471/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1472#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1473#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1474/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1475# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1476/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1477# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1478/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1479#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1480#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1481/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1482# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1483/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1484# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1485/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1486#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1487#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1488/** Address Authentication using the QARMA3 algorithm is not implemented. */
1489# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1490/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1491# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1492/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1493# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1494/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1495# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1496/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1497# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1498/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1499# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1500/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1501#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1502#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1503/** No Memory Copy and Memory Set instructions implemented. */
1504# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1505/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1506# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1507/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1508#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1509#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1510/** BC instruction is not implemented. */
1511# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1512/** BC instruction is implemented (FEAT_HBC). */
1513# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1514/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1515#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1516#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1517/** ConstPACField() returns FALSE. */
1518# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1519/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1520# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1521/* Bit 28 - 63 - Reserved. */
1522/** @} */
1523
1524
1525/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1526 * @{ */
1527/** Bit 0 - 3 - EL0 Exception level handling. */
1528#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1529#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1530/** EL0 can be executed in AArch64 state only. */
1531# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1532/** EL0 can be executed in AArch64 and AArch32 state. */
1533# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1534/** Bit 4 - 7 - EL1 Exception level handling. */
1535#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1536#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1537/** EL1 can be executed in AArch64 state only. */
1538# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1539/** EL1 can be executed in AArch64 and AArch32 state. */
1540# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1541/** Bit 8 - 11 - EL2 Exception level handling. */
1542#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1543#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1544/** EL2 is not implemented. */
1545# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1546/** EL2 can be executed in AArch64 state only. */
1547# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1548/** EL2 can be executed in AArch64 and AArch32 state. */
1549# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1550/** Bit 12 - 15 - EL3 Exception level handling. */
1551#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1552#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1553/** EL3 is not implemented. */
1554# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1555/** EL3 can be executed in AArch64 state only. */
1556# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1557/** EL3 can be executed in AArch64 and AArch32 state. */
1558# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1559/** Bit 16 - 19 - Floating-point support. */
1560#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1561#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1562/** Floating-point is implemented and support single and double precision. */
1563# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1564/** Floating-point is implemented and support single, double and half precision. */
1565# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1566/** Floating-point is not implemented. */
1567# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1568/** Bit 20 - 23 - Advanced SIMD support. */
1569#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1570#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1571/** Advanced SIMD is implemented and support single and double precision. */
1572# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1573/** Advanced SIMD is implemented and support single, double and half precision. */
1574# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1575/** Advanced SIMD is not implemented. */
1576# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1577/** Bit 24 - 27 - System register GIC CPU interface support. */
1578#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1579#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1580/** GIC CPU interface system registers are not implemented. */
1581# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1582/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1583# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1584/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1585# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1586/** Bit 28 - 31 - RAS Extension version. */
1587#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1588#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1589/** No RAS extension. */
1590# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1591/** RAS Extension implemented. */
1592# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1593/** FEAT_RASv1p1 implemented. */
1594# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1595/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1596#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1597#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1598/** SVE is not supported. */
1599# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1600/** SVE is supported. */
1601# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1602/** Bit 36 - 39 - Secure EL2 support. */
1603#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1604#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1605/** Secure EL2 is not supported. */
1606# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1607/** Secure EL2 is implemented. */
1608# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1609/** Bit 40 - 43 - MPAM support. */
1610#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1611#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
1612/** MPAM extension major version number is 0. */
1613# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
1614/** MPAM extension major version number is 1. */
1615# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
1616/** Bit 44 - 47 - Activity Monitor Extension support. */
1617#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1618#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
1619/** Activity Monitor extension is not implemented. */
1620# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
1621/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
1622# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
1623/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
1624# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
1625/** Bit 48 - 51 - Data Independent Timing support. */
1626#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1627#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
1628/** AArch64 does not guarantee constant execution time of any instructions. */
1629# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
1630/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
1631# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
1632/** Bit 52 - 55 - Realm Management Extension support. */
1633#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1634#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
1635/** Realm Management Extension not implemented. */
1636# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
1637/** RMEv1 is implemented (FEAT_RME). */
1638# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
1639/** Bit 56 - 59 - Speculative use out of context branch targets support. */
1640#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1641#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
1642/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
1643# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
1644/** FEAT_CSV2 is implemented. */
1645# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
1646/** FEAT_CSV2_2 is implemented. */
1647# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
1648/** FEAT_CSV2_3 is implemented. */
1649# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
1650/** Bit 60 - 63 - Speculative use of faulting data support. */
1651#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1652#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
1653/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
1654# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
1655/** FEAT_CSV3 is supported . */
1656# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
1657/** @} */
1658
1659
1660/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
1661 * @{ */
1662/** Bit 0 - 3 - Branch Target Identification support. */
1663#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1664#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
1665/** The Branch Target Identification mechanism is not implemented. */
1666# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
1667/** The Branch Target Identifcation mechanism is implemented. */
1668# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
1669/** Bit 4 - 7 - Speculative Store Bypassing control support. */
1670#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1671#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
1672/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
1673# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
1674/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
1675# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
1676/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
1677 * to directly read and write the PSTATE.SSBS field. */
1678# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
1679/** Bit 8 - 11 - Memory Tagging Extension support. */
1680#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1681#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
1682/** MTE is not implemented. */
1683# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
1684/** Instruction only Memory Tagging Extensions implemented. */
1685# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
1686/** Full Memory Tagging Extension implemented. */
1687# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
1688/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
1689# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
1690/** Bit 12 - 15 - RAS Extension fractional field. */
1691#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1692#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
1693/** RAS Extension is implemented. */
1694# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
1695/** FEAT_RASv1p1 is implemented. */
1696# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
1697/** Bit 16 - 19 - MPAM minor version number. */
1698#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1699#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
1700/** The minor version of number of the MPAM extension is 0. */
1701# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
1702/** The minor version of number of the MPAM extension is 1. */
1703# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
1704/* Bit 20 - 23 - Reserved. */
1705/** Bit 24 - 27 - Scalable Matrix Extension support. */
1706#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1707#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
1708/** Scalable Matrix Extensions are not implemented. */
1709# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
1710/** Scalable Matrix Extensions are implemented (FEAT_SME). */
1711# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
1712/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
1713# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
1714/** Bit 28 - 31 - Random Number trap to EL3 support. */
1715#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1716#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
1717/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
1718# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
1719/** Trapping of RNDR and RDNRRS to EL3 is supported. */
1720# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
1721/** Bit 32 - 35 - CSV2 fractional field. */
1722#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1723#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
1724/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
1725# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
1726/** FEAT_CSV2_1p1 is implemented. */
1727# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
1728/** FEAT_CSV2_1p2 is implemented. */
1729# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
1730/** Bit 36 - 39 - Non-maskable Interrupt support. */
1731#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1732#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
1733/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
1734# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
1735/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
1736# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
1737/** @} */
1738
1739
1740/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
1741 * @{ */
1742/** Bit 0 - 3 - Physical Address range supported. */
1743#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1744#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
1745/** Physical Address range is 32 bits, 4GiB. */
1746# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
1747/** Physical Address range is 36 bits, 64GiB. */
1748# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
1749/** Physical Address range is 40 bits, 1TiB. */
1750# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
1751/** Physical Address range is 42 bits, 4TiB. */
1752# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
1753/** Physical Address range is 44 bits, 16TiB. */
1754# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
1755/** Physical Address range is 48 bits, 256TiB. */
1756# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
1757/** Physical Address range is 52 bits, 4PiB. */
1758# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
1759/** Bit 4 - 7 - Number of ASID bits. */
1760#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1761#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
1762/** ASID bits is 8. */
1763# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
1764/** ASID bits is 16. */
1765# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
1766/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
1767#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1768#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
1769/** No mixed-endian support. */
1770# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
1771/** Mixed-endian supported. */
1772# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
1773/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
1774#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1775#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
1776/** No distinction between Secure and Non-secure Memory supported. */
1777# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
1778/** Distinction between Secure and Non-secure Memory supported. */
1779# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
1780/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
1781#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1782#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
1783/** No mixed-endian support at EL0. */
1784# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
1785/** Mixed-endian support at EL0. */
1786# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
1787/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
1788#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1789#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
1790/** 16KiB granule size not supported. */
1791# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
1792/** 16KiB granule size is supported. */
1793# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
1794/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1795# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
1796/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
1797#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1798#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
1799/** 64KiB granule supported. */
1800# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
1801/** 64KiB granule not supported. */
1802# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
1803/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
1804#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1805#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
1806/** 4KiB granule supported. */
1807# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
1808/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1809# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
1810/** 4KiB granule not supported. */
1811# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
1812/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
1813#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1814#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
1815/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
1816# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
1817/** 16KiB granule not supported at stage 2. */
1818# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
1819/** 16KiB granule supported at stage 2. */
1820# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
1821/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1822# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
1823/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
1824#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1825#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
1826/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
1827# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
1828/** 64KiB granule not supported at stage 2. */
1829# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
1830/** 64KiB granule supported at stage 2. */
1831# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
1832/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1833#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1834#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
1835/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
1836# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
1837/** 4KiB granule not supported at stage 2. */
1838# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
1839/** 4KiB granule supported at stage 2. */
1840# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
1841/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1842# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
1843/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
1844#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1845#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
1846/** All exception entries and exits are context synchronization events. */
1847# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
1848/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
1849# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
1850/* Bit 48 - 55 - Reserved. */
1851/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
1852#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1853#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
1854/** Fine-grained trap controls are not implemented. */
1855# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
1856/** Fine-grained trap controls are implemented (FEAT_FGT). */
1857# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
1858/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
1859#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1860#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
1861/** Enhanced Counter Virtualization is not implemented. */
1862# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
1863/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
1864# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
1865/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
1866# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
1867/** @} */
1868
1869
1870/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
1871 * @{ */
1872/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
1873#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1874#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
1875/** Hardware update of the Access flag and dirty state are not supported. */
1876# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
1877/** Support for hardware update of the Access flag for Block and Page descriptors. */
1878# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
1879/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
1880# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
1881/** Bit 4 - 7 - EL1 Exception level handling. */
1882#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1883#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
1884/** VMID bits is 8. */
1885# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
1886/** VMID bits is 16 (FEAT_VMID16). */
1887# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
1888/** Bit 8 - 11 - Virtualization Host Extensions support. */
1889#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1890#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
1891/** Virtualization Host Extensions are not supported. */
1892# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
1893/** Virtualization Host Extensions are supported. */
1894# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
1895/** Bit 12 - 15 - Hierarchical Permission Disables. */
1896#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1897#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
1898/** Disabling of hierarchical controls not supported. */
1899# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
1900/** Disabling of hierarchical controls supported (FEAT_HPDS). */
1901# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
1902/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
1903# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
1904/** Bit 16 - 19 - LORegions support. */
1905#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1906#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
1907/** LORegions not supported. */
1908# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
1909/** LORegions supported. */
1910# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
1911/** Bit 20 - 23 - Privileged Access Never support. */
1912#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1913#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
1914/** PAN not supported. */
1915# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
1916/** PAN supported (FEAT_PAN). */
1917# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
1918/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
1919# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
1920/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
1921# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
1922/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
1923#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1924#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
1925/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
1926# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
1927/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
1928# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
1929/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
1930#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1931#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
1932/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
1933# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
1934/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
1935# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
1936/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
1937#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1938#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
1939/** Configurable delayed trapping of WFE is not supported. */
1940# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
1941/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
1942# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
1943/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
1944#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1945#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
1946/** Enhanced Translation Synchronization is not supported. */
1947# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
1948/** Enhanced Translation Synchronization is implemented. */
1949# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
1950/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1951#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1952#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
1953/** HCRX_EL2 and its associated EL3 trap are not supported. */
1954# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
1955/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
1956# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
1957/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
1958#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1959#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
1960/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
1961# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
1962/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
1963# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
1964/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
1965#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1966#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
1967/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
1968# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
1969/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
1970# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
1971/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
1972#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1973#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
1974/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
1975# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
1976/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
1977# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
1978/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
1979#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1980#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
1981/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
1982# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
1983/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
1984# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
1985/* Bit 60 - 63 - Reserved. */
1986/** @} */
1987
1988
1989/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
1990 * @{ */
1991/** Bit 0 - 3 - Indicates support for Common not Private translations. */
1992#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1993#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
1994/** Common not Private translations are not supported. */
1995# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
1996/** Support for Common not Private translations (FEAT_TTNCP). */
1997# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
1998/** Bit 4 - 7 - Indicates support for User Access Override. */
1999#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2000#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2001/** User Access Override is not supported. */
2002# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2003/** User Access Override is supported (FEAT_UAO). */
2004# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2005/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2006#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2007#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2008/** LSMAOE and nTLSMD bits are not supported. */
2009# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2010/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2011# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2012/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2013#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2014#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2015/** IESB bit is not supported. */
2016# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2017/** IESB bit is supported (FEAT_IESB). */
2018# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2019/** Bit 16 - 19 - Indicates support for larger virtual address. */
2020#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2021#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2022/** Virtual address range is 48 bits. */
2023# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2024/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2025# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2026/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2027#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2028#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2029/** CCSIDR_EL1 register format is 32-bit. */
2030# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2031/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2032# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2033/** Bit 24 - 27 - Indicates support for nested virtualization. */
2034#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2035#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2036/** Nested virtualization is not supported. */
2037# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2038/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2039# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2040/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2041# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2042/** Bit 28 - 31 - Indicates support for small translation tables. */
2043#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2044#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2045/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2046# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2047/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2048# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2049/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2050#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2051#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2052/** Unaligned single-copy atomicity and atomic functions are not supported. */
2053# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2054/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2055# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2056/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2057#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2058#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2059/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2060# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2061/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2062# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2063/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2064#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2065#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2066/** HCR_EL2.FWB bit is not supported. */
2067# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2068/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2069# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2070/* Bit 44 - 47 - Reserved. */
2071/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2072#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2073#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2074/** TLB maintenance instructions by address have bits [47:44] Res0. */
2075# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2076/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2077# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2078/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2079 * changing block size for a translation. */
2080#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2081#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2082/** Level 0 support for changing block size is supported (FEAT_BBM). */
2083# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2084/** Level 1 support for changing block size is supported (FEAT_BBM). */
2085# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2086/** Level 2 support for changing block size is supported (FEAT_BBM). */
2087# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2088/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2089#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2090#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2091/** Enhanced Virtualization Traps are not supported. */
2092# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2093/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2094# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2095/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2096# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2097/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2098#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2099#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2100/** E0PDx mechanism is not supported. */
2101# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2102/** E0PDx mechanism is supported (FEAT_E0PD). */
2103# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2104/** @} */
2105
2106
2107/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2108 * @{ */
2109/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2110#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2111#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2112/** Armv8 debug architecture version. */
2113# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2114/** Armv8 debug architecture version with virtualization host extensions. */
2115# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2116/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2117# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2118/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2119# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2120/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2121# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2122/** Bit 4 - 7 - Indicates trace support. */
2123#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2124#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2125/** Trace unit System registers not implemented. */
2126# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2127/** Trace unit System registers supported. */
2128# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2129/** Bit 8 - 11 - Performance Monitors Extension version. */
2130#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2131#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2132/** Performance Monitors Extension not supported. */
2133# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2134/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2135# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2136/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2137# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2138/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2139# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2140/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2141# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2142/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2143# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2144/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2145# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2146/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2147#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2148#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2149/* Bit 16 - 19 - Reserved 0. */
2150/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2151#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2152#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2153/* Bit 24 - 27 - Reserved 0. */
2154/** Bit 28 - 31 - Number of context-aware breakpoints. */
2155#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2156#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2157/** Bit 32 - 35 - Statistical Profiling Extension version. */
2158#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2159#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2160/** Statistical Profiling Extension not implemented. */
2161# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2162/** Statistical Profiling Extension supported (FEAT_SPE). */
2163# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2164/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2165# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2166/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2167# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2168/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2169# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2170/** Bit 36 - 39 - OS Double Lock implemented. */
2171#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2172#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2173/** OS Double Lock is not implemented. */
2174# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2175/** OS Double Lock is supported (FEAT_DoubleLock). */
2176# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2177/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2178#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2179#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2180/** Armv8.4 self-hosted Trace Extension not implemented. */
2181# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2182/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2183# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2184/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2185#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2186#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2187/** Trace Buffer Extension is not implemented. */
2188# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2189/** Trace Buffer Extension is supported (FEAT_TRBE). */
2190# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2191/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2192#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2193#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2194/** Multi-threaded PMU extension is not implemented. */
2195# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2196/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2197# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2198/** Multi-threaded PMU extension is not implemented. */
2199# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2200/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2201#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2202#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2203/** Branch Record Buffer extension is not implemented. */
2204# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2205/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2206# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2207/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2208# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2209/* Bit 56 - 59 - Reserved. */
2210/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2211#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2212#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2213/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2214# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2215/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2216# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2217/** @} */
2218
2219
2220#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
2221/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2222 * @ingroup grp_rt_armv8
2223 *
2224 * A few inlined functions and macros for assiting in encoding common ARMv8
2225 * instructions.
2226 *
2227 * @{ */
2228
2229/** A64: Return instruction. */
2230#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2231/** A64: Return instruction with LR pointer authentication using SP and key A. */
2232#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2233/** A64: Return instruction with LR pointer authentication using SP and key B. */
2234#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2235/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2236#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2237/** A64: Insert pointer authentication code into LR using SP and key B. */
2238#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2239/** A64: Insert pointer authentication code into LR using XZR and key B. */
2240#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2241/** A64: Invert the carry flag (PSTATE.C). */
2242#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
2243
2244
2245typedef enum
2246{
2247 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
2248 * and update the register. */
2249 kArm64InstrStLdPairType_PostIndex = 1,
2250 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2251 * but don't update the register. */
2252 kArm64InstrStLdPairType_Signed = 2,
2253 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2254 * and update the register. */
2255 kArm64InstrStLdPairType_PreIndex = 3
2256} ARM64INSTRSTLDPAIRTYPE;
2257
2258/**
2259 * A64: Encodes either stp (store register pair) or ldp (load register pair).
2260 *
2261 * @returns The encoded instruction.
2262 * @param fLoad true for ldp, false of stp.
2263 * @param u2Opc When @a fSimdFp is @c false:
2264 * - 0 for 32-bit GPRs (Wt).
2265 * - 1 for encoding stgp or ldpsw.
2266 * - 2 for 64-bit GRPs (Xt).
2267 * - 3 illegal.
2268 * When @a fSimdFp is @c true:
2269 * - 0 for 32-bit SIMD&FP registers (St).
2270 * - 1 for 64-bit SIMD&FP registers (Dt).
2271 * - 2 for 128-bit SIMD&FP regsiters (Qt).
2272 * @param enmType The instruction variant wrt addressing and updating of the
2273 * addressing register.
2274 * @param iReg1 The first register to store/load.
2275 * @param iReg2 The second register to store/load.
2276 * @param iBaseReg The base register to use when addressing. SP is allowed.
2277 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
2278 * will be multiplied by the register size.
2279 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
2280 * stgp/ldpsw instructions.
2281 */
2282DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
2283 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2284 bool fSimdFp = false)
2285{
2286 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
2287 return (u2Opc << 30)
2288 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
2289 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
2290 | ((uint32_t)enmType << 23)
2291 | ((uint32_t)fLoad << 22)
2292 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
2293 | (iReg2 << 10)
2294 | (iBaseReg << 5)
2295 | iReg1;
2296}
2297
2298typedef enum /* Size VR Opc */
2299{ /* \ | / */
2300 kArmv8A64InstrLdStType_Mask_Size = 0x300,
2301 kArmv8A64InstrLdStType_Mask_VR = 0x010,
2302 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
2303 kArmv8A64InstrLdStType_Shift_Size = 8,
2304 kArmv8A64InstrLdStType_Shift_VR = 4,
2305 kArmv8A64InstrLdStType_Shift_Opc = 0,
2306
2307 kArmv8A64InstrLdStType_St_Byte = 0x000,
2308 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
2309 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
2310 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
2311
2312 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
2313 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
2314 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
2315 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
2316
2317 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
2318 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
2319 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
2320
2321 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
2322 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
2323
2324 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
2325
2326 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
2327 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
2328 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
2329 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
2330
2331 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
2332 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
2333
2334 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
2335 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
2336
2337 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
2338 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
2339
2340} ARMV8A64INSTRLDSTTYPE;
2341/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
2342#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
2343
2344
2345/**
2346 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2347 *
2348 * @returns The encoded instruction.
2349 * @param u32Opcode The base opcode value.
2350 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2351 * @param iReg The register to load into / store.
2352 * @param iBaseReg The base register to use when addressing. SP is allowed.
2353 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2354 */
2355DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
2356 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2357{
2358 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
2359 return u32Opcode
2360 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2361 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2362 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2363 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
2364 | (iBaseReg << 5)
2365 | iReg;
2366}
2367
2368
2369/**
2370 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2371 *
2372 * @returns The encoded instruction.
2373 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2374 * @param iReg The register to load into / store.
2375 * @param iBaseReg The base register to use when addressing. SP is allowed.
2376 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2377 */
2378DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
2379 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2380{
2381 /* 3 2 1 0 */
2382 /* 10987654321098765432109876543210 */
2383 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
2384 enmType, iReg, iBaseReg, i9ImmDisp);
2385}
2386
2387/**
2388 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
2389 *
2390 * @returns The encoded instruction.
2391 * @param enmType The load/store instruction type. Prefech not valid.
2392 * @param iReg The register to load into / store.
2393 * @param iBaseReg The base register to use when addressing. SP is allowed.
2394 * Written back.
2395 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2396 */
2397DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2398 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2399{
2400 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2401 /* 10987654321098765432109876543210 */
2402 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
2403 enmType, iReg, iBaseReg, i9ImmDisp);
2404}
2405
2406/**
2407 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
2408 *
2409 * @returns The encoded instruction.
2410 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2411 * @param iReg The register to load into / store.
2412 * @param iBaseReg The base register to use when addressing. SP is allowed.
2413 * Written back.
2414 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2415 */
2416DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2417 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2418{
2419 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2420 /* 10987654321098765432109876543210 */
2421 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
2422 enmType, iReg, iBaseReg, i9ImmDisp);
2423}
2424
2425/**
2426 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
2427 *
2428 * @returns The encoded instruction.
2429 * @param enmType The load/store instruction type. Prefech not valid,
2430 * nor any SIMD&FP variants.
2431 * @param iReg The register to load into / store.
2432 * @param iBaseReg The base register to use when addressing. SP is allowed.
2433 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2434 */
2435DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
2436 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2437{
2438 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
2439 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
2440 /* 3 2 1 0 */
2441 /* 10987654321098765432109876543210 */
2442 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
2443 enmType, iReg, iBaseReg, i9ImmDisp);
2444}
2445
2446
2447/**
2448 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
2449 *
2450 * @returns The encoded instruction.
2451 * @param enmType The load/store instruction type. Prefech not valid,
2452 * nor any SIMD&FP variants.
2453 * @param iReg The register to load into / store.
2454 * @param iBaseReg The base register to use when addressing. SP is allowed.
2455 * @param u12ImmDisp Addressing displacement, scaled by size.
2456 */
2457DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
2458 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
2459{
2460 Assert(u12ImmDisp < 4096U);
2461 Assert(iReg < 32); /* 3 2 1 0 */
2462 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2463 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
2464 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2465 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2466 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2467 | (u12ImmDisp << 10)
2468 | (iBaseReg << 5)
2469 | iReg;
2470}
2471
2472typedef enum
2473{
2474 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
2475 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
2476 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
2477 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
2478} ARMV8A64INSTRLDSTEXTEND;
2479
2480/**
2481 * A64: Encodes load/store w/ index register.
2482 *
2483 * @returns The encoded instruction.
2484 * @param enmType The load/store instruction type.
2485 * @param iReg The register to load into / store.
2486 * @param iBaseReg The base register to use when addressing. SP is allowed.
2487 * @param iRegIndex The index register.
2488 * @param enmExtend The extending to apply to @a iRegIndex.
2489 * @param fShifted Whether to shift the index. The shift amount corresponds
2490 * to the access size (thus irrelevant for byte accesses).
2491 */
2492DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
2493 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
2494 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
2495 bool fShifted = false)
2496{
2497 Assert(iRegIndex < 32);
2498 Assert(iReg < 32); /* 3 2 1 0 */
2499 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2500 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
2501 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2502 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2503 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2504 | (iRegIndex << 16)
2505 | ((uint32_t)enmExtend << 13)
2506 | ((uint32_t)fShifted << 12)
2507 | (iBaseReg << 5)
2508 | iReg;
2509}
2510
2511typedef enum /* VR Opc */
2512{ /* \ | */
2513 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
2514 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
2515 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
2516 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
2517
2518 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
2519 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
2520 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
2521 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
2522
2523 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
2524 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
2525 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
2526} ARMV8A64INSTRLDRLITTERAL;
2527
2528
2529/**
2530 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
2531 *
2532 * @returns The encoded instruction.
2533 * @param enmType The load instruction type.
2534 * @param iReg The register to load into.
2535 * @param i19Imm The signed immediate value, multiplied by 4 regardless
2536 * of access size.
2537 */
2538DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
2539{
2540 Assert(i19Imm >= -262144 && i19Imm < 262144);
2541 Assert(iReg < 32); /* 3 2 1 0 */
2542 /* 10987654321098765432109876543210 */
2543 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
2544 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
2545 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
2546 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
2547 | iReg;
2548}
2549
2550
2551typedef enum
2552{
2553 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
2554 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
2555 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
2556} ARMV8A64INSTRMOVWIDE;
2557
2558/**
2559 * A64: Encode a move wide immediate instruction.
2560 *
2561 * @returns The encoded instruction.
2562 * @param enmType The load instruction type.
2563 * @param iRegDst The register to mov the immediate into.
2564 * @param uImm16 The immediate value.
2565 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
2566 * half-words to target:
2567 * - 0 for bits 15:00,
2568 * - 1 for bits 31:16,
2569 * - 2 for bits 47:32 (f64Bit=true only),
2570 * - 3 for bits 63:48 (f64Bit=true only).
2571 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
2572 */
2573DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
2574 uint32_t iHalfWord = 0, bool f64Bit = true)
2575{
2576 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
2577 return ((uint32_t)f64Bit << 31)
2578 | ((uint32_t)enmType << 29)
2579 | UINT32_C(0x12800000)
2580 | (iHalfWord << 21)
2581 | (uImm16 << 5)
2582 | iRegDst;
2583}
2584
2585/** A64: Encodes a MOVN instruction.
2586 * @see Armv8A64MkInstrMovWide for parameter details. */
2587DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2588{
2589 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
2590}
2591
2592/** A64: Encodes a MOVZ instruction.
2593 * @see Armv8A64MkInstrMovWide for parameter details. */
2594DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2595{
2596 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
2597}
2598
2599/** A64: Encodes a MOVK instruction.
2600 * @see Armv8A64MkInstrMovWide for parameter details. */
2601DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2602{
2603 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
2604}
2605
2606
2607typedef enum
2608{
2609 kArmv8A64InstrShift_Lsl = 0,
2610 kArmv8A64InstrShift_Lsr,
2611 kArmv8A64InstrShift_Asr,
2612 kArmv8A64InstrShift_Ror
2613} ARMV8A64INSTRSHIFT;
2614
2615
2616/**
2617 * A64: Encodes a logical instruction with a shifted 2nd register operand.
2618 *
2619 * @returns The encoded instruction.
2620 * @param u2Opc The logical operation to perform.
2621 * @param fNot Whether to complement the 2nd operand.
2622 * @param iRegResult The output register.
2623 * @param iReg1 The 1st register operand.
2624 * @param iReg2Shifted The 2nd register operand, to which the optional
2625 * shifting is applied.
2626 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
2627 * GPRs.
2628 * @param offShift6 The shift amount (default: none).
2629 * @param enmShift The shift operation (default: LSL).
2630 */
2631DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
2632 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
2633 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
2634{
2635 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
2636 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
2637 return ((uint32_t)f64Bit << 31)
2638 | (u2Opc << 29)
2639 | UINT32_C(0x0a000000)
2640 | ((uint32_t)enmShift << 22)
2641 | ((uint32_t)fNot << 21)
2642 | (iReg2Shifted << 16)
2643 | (offShift6 << 10)
2644 | (iReg1 << 5)
2645 | iRegResult;
2646}
2647
2648
2649/** A64: Encodes an AND instruction.
2650 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2651DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2652 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2653{
2654 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2655}
2656
2657
2658/** A64: Encodes an BIC instruction.
2659 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2660DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2661 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2662{
2663 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2664}
2665
2666
2667/** A64: Encodes an ORR instruction.
2668 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2669DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2670 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2671{
2672 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2673}
2674
2675
2676/** A64: Encodes an MOV instruction.
2677 * This is an alias for "orr dst, xzr, src". */
2678DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
2679{
2680 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
2681}
2682
2683
2684/** A64: Encodes an ORN instruction.
2685 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2686DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2687 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2688{
2689 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2690}
2691
2692
2693/** A64: Encodes an EOR instruction.
2694 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2695DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2696 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2697{
2698 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2699}
2700
2701
2702/** A64: Encodes an EON instruction.
2703 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2704DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2705 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2706{
2707 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2708}
2709
2710
2711/** A64: Encodes an ANDS instruction.
2712 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2713DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2714 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2715{
2716 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2717}
2718
2719
2720/** A64: Encodes an BICS instruction.
2721 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2722DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2723 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2724{
2725 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2726}
2727
2728# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
2729
2730/**
2731 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
2732 *
2733 * @returns The decoded mask.
2734 * @param uImm6SizeLen The immS value from the instruction. (No N part
2735 * here, as that must be zero for instructions
2736 * operating on 32-bit wide registers.)
2737 * @param uImm6Rotations The immR value from the instruction.
2738 */
2739DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
2740{
2741 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
2742
2743 /* Determine the element size. */
2744 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
2745 Assert(cBitsElementLog2 + 1U != 0U);
2746
2747 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
2748 Assert(uImm6Rotations < cBitsElement);
2749
2750 /* Extract the number of bits set to 1: */
2751 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
2752 Assert(cBitsSetTo1 < cBitsElement);
2753 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
2754
2755 /* Produce the unrotated pattern. */
2756 static const uint32_t s_auReplicate[]
2757 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
2758 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
2759
2760 /* Rotate it and return. */
2761 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
2762}
2763
2764
2765/**
2766 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
2767 *
2768 * @returns The decoded mask.
2769 * @param uImm7SizeLen The N:immS value from the instruction.
2770 * @param uImm6Rotations The immR value from the instruction.
2771 */
2772DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
2773{
2774 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
2775
2776 /* Determine the element size. */
2777 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
2778 Assert(cBitsElementLog2 + 1U != 0U);
2779
2780 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
2781 Assert(uImm6Rotations < cBitsElement);
2782
2783 /* Extract the number of bits set to 1: */
2784 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
2785 Assert(cBitsSetTo1 < cBitsElement);
2786 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
2787
2788 /* Produce the unrotated pattern. */
2789 static const uint64_t s_auReplicate[]
2790 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
2791 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
2792
2793 /* Rotate it and return. */
2794 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
2795}
2796
2797
2798/**
2799 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
2800 * the immS value.
2801 */
2802DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
2803{
2804 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
2805}
2806
2807
2808/**
2809 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
2810 * 32-bit bitmask to a set of immediates for those instructions.
2811 *
2812 * @returns true if successful, false if not.
2813 * @param fMask The mask value to convert.
2814 * @param puImm6SizeLen Where to return the immS part (N is always zero for
2815 * 32-bit wide masks).
2816 * @param puImm6Rotations Where to return the immR.
2817 */
2818DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
2819{
2820 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
2821 if ((uint32_t)(fMask + 1U) <= 1)
2822 return false;
2823
2824 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
2825 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
2826 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
2827 if (cRor)
2828 fMask = ASMRotateRightU32(fMask, cRor);
2829 else
2830 fMask = ASMRotateLeftU32(fMask, cRol);
2831 Assert(fMask & RT_BIT_32(0));
2832 Assert(!(fMask & RT_BIT_32(31)));
2833
2834 /* Count the trailing ones and leading zeros. */
2835 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
2836 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
2837
2838 /* The potential element length is then the sum of the two above. */
2839 unsigned const cBitsElement = cOnes + cZeros;
2840 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
2841 return false;
2842
2843 /* Special case: 32 bits element size. Since we're done here. */
2844 if (cBitsElement == 32)
2845 *puImm6SizeLen = cOnes - 1;
2846 else
2847 {
2848 /* Extract the element bits and check that these are replicated in the whole pattern. */
2849 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
2850 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
2851
2852 static const uint32_t s_auReplicate[]
2853 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
2854 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
2855 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
2856 else
2857 return false;
2858 }
2859 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
2860
2861 return true;
2862}
2863
2864
2865/**
2866 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
2867 * 64-bit bitmask to a set of immediates for those instructions.
2868 *
2869 * @returns true if successful, false if not.
2870 * @param fMask The mask value to convert.
2871 * @param puImm7SizeLen Where to return the N:immS part.
2872 * @param puImm6Rotations Where to return the immR.
2873 */
2874DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
2875{
2876 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
2877 if ((uint64_t)(fMask + 1U) <= 1)
2878 return false;
2879
2880 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
2881 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
2882 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
2883 if (cRor)
2884 fMask = ASMRotateRightU64(fMask, cRor);
2885 else
2886 fMask = ASMRotateLeftU64(fMask, cRol);
2887 Assert(fMask & RT_BIT_64(0));
2888 Assert(!(fMask & RT_BIT_64(63)));
2889
2890 /* Count the trailing ones and leading zeros. */
2891 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
2892 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
2893
2894 /* The potential element length is then the sum of the two above. */
2895 unsigned const cBitsElement = cOnes + cZeros;
2896 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
2897 return false;
2898
2899 /* Special case: 64 bits element size. Since we're done here. */
2900 if (cBitsElement == 64)
2901 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
2902 else
2903 {
2904 /* Extract the element bits and check that these are replicated in the whole pattern. */
2905 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
2906 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
2907
2908 static const uint64_t s_auReplicate[]
2909 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
2910 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
2911 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
2912 else
2913 return false;
2914 }
2915 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
2916
2917 return true;
2918}
2919
2920# endif /* IPRT_INCLUDED_asm_h */
2921
2922/**
2923 * A64: Encodes a logical instruction with an complicated immediate mask.
2924 *
2925 * The @a uImm7SizeLen parameter specifies two things:
2926 * 1. the element size and
2927 * 2. the number of bits set to 1 in the pattern.
2928 *
2929 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
2930 * top) and using the position of the first bit set as a power of two.
2931 *
2932 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
2933 * |---|---|---|---|---|---|---|--------------|
2934 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
2935 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
2936 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
2937 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
2938 * | 0 | 0 | x | x | x | x | x | 32 bits |
2939 * | 1 | x | x | x | x | x | x | 64 bits |
2940 *
2941 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
2942 * there is always one zero bit in the pattern).
2943 *
2944 * The @a uImm6Rotations parameter specifies how many bits to the right,
2945 * the element pattern is rotated. The rotation count must be less than the
2946 * element bit count (size).
2947 *
2948 * @returns The encoded instruction.
2949 * @param u2Opc The logical operation to perform.
2950 * @param iRegResult The output register.
2951 * @param iRegSrc The 1st register operand.
2952 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
2953 * field at the top of the 6-bit 'imms' field.
2954 *
2955 * @param uImm6Rotations The rotation count.
2956 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
2957 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
2958 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
2959 */
2960DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
2961 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
2962{
2963 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x1f)));
2964 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
2965 return ((uint32_t)f64Bit << 31)
2966 | (u2Opc << 29)
2967 | UINT32_C(0x12000000)
2968 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
2969 | (uImm6Rotations << 16)
2970 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
2971 | (iRegSrc << 5)
2972 | iRegResult;
2973}
2974
2975
2976/** A64: Encodes an AND instruction w/ complicated immediate mask.
2977 * @see Armv8A64MkInstrLogicalImm for parameter details. */
2978DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
2979 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
2980{
2981 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
2982}
2983
2984
2985/** A64: Encodes an ORR instruction w/ complicated immediate mask.
2986 * @see Armv8A64MkInstrLogicalImm for parameter details. */
2987DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
2988 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
2989{
2990 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
2991}
2992
2993
2994/** A64: Encodes an EOR instruction w/ complicated immediate mask.
2995 * @see Armv8A64MkInstrLogicalImm for parameter details. */
2996DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
2997 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
2998{
2999 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3000}
3001
3002
3003/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
3004 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3005DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
3006 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3007{
3008 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3009}
3010
3011
3012/** A64: Encodes an TST instruction w/ complicated immediate mask.
3013 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3014DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
3015 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3016{
3017 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3018}
3019
3020
3021/**
3022 * A64: Encodes a bitfield instruction.
3023 *
3024 * @returns The encoded instruction.
3025 * @param u2Opc The bitfield operation to perform.
3026 * @param iRegResult The output register.
3027 * @param iRegSrc The 1st register operand.
3028 * @param cImm6Ror The right rotation count.
3029 * @param uImm6S The leftmost bit to be moved.
3030 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3031 * @param uN1 This must match @a f64Bit for all instructions
3032 * currently specified.
3033 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3034 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3035 */
3036DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3037 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
3038{
3039 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
3040 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
3041 return ((uint32_t)f64Bit << 31)
3042 | (u2Opc << 29)
3043 | UINT32_C(0x13000000)
3044 | (uN1 << 22)
3045 | (cImm6Ror << 16)
3046 | (uImm6S << 10)
3047 | (iRegSrc << 5)
3048 | iRegResult;
3049}
3050
3051
3052/** A64: Encodes a SBFM instruction.
3053 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3054DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3055 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3056{
3057 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3058}
3059
3060
3061/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
3062 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3063DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3064{
3065 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
3066}
3067
3068
3069/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
3070 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3071DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3072{
3073 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
3074}
3075
3076
3077/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
3078 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3079DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
3080{
3081 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
3082}
3083
3084
3085/** A64: Encodes a BFM instruction.
3086 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3087DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3088 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3089{
3090 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3091}
3092
3093
3094/** A64: Encodes a BFI instruction (insert).
3095 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3096DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
3097 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3098{
3099 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3100 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
3101 cBitsWidth - 1, f64Bit);
3102}
3103
3104
3105/** A64: Encodes an UBFM instruction.
3106 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3107DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3108 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3109{
3110 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3111}
3112
3113
3114/** A64: Encodes an UBFX instruction (zero extending extract).
3115 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3116DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
3117 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3118{
3119 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3120}
3121
3122
3123/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
3124 * shifted into destination).
3125 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3126DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
3127 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
3128{
3129 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
3130 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
3131}
3132
3133
3134/** A64: Encodes an LSL instruction w/ immediate shift value.
3135 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3136DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3137{
3138 uint32_t const cWidth = f64Bit ? 63 : 31;
3139 Assert(cShift > 0); Assert(cShift <= cWidth);
3140 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
3141 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
3142}
3143
3144
3145/** A64: Encodes an LSR instruction w/ immediate shift value.
3146 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3147DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3148{
3149 uint32_t const cWidth = f64Bit ? 63 : 31;
3150 Assert(cShift > 0); Assert(cShift <= cWidth);
3151 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
3152}
3153
3154
3155/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
3156 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3157DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3158{
3159 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
3160}
3161
3162
3163/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
3164 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3165DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3166{
3167 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
3168}
3169
3170
3171/**
3172 * A64: Encodes an EXTR instruction with an immediate.
3173 *
3174 * @returns The encoded instruction.
3175 * @param iRegResult The register to store the result in. ZR is valid.
3176 * @param iRegLow The register holding the least significant bits in the
3177 * extraction. ZR is valid.
3178 * @param iRegHigh The register holding the most significant bits in the
3179 * extraction. ZR is valid.
3180 * @param uLsb The bit number of the least significant bit, or where in
3181 * @a iRegLow to start the
3182 * extraction.
3183 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3184 */
3185DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
3186 bool f64Bit = true)
3187{
3188 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
3189 return ((uint32_t)f64Bit << 31)
3190 | UINT32_C(0x13800000)
3191 | ((uint32_t)f64Bit << 22) /*N*/
3192 | (iRegHigh << 16)
3193 | (uLsb << 10)
3194 | (iRegLow << 5)
3195 | iRegResult;
3196}
3197
3198
3199/** A64: Rotates the value of a register (alias for EXTR). */
3200DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3201{
3202 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
3203}
3204
3205
3206/**
3207 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
3208 *
3209 * @returns The encoded instruction.
3210 * @param fSub true for sub and subs, false for add and
3211 * adds.
3212 * @param iRegResult The register to store the result in.
3213 * SP is valid when @a fSetFlags = false,
3214 * and ZR is valid otherwise.
3215 * @param iRegSrc The register containing the augend (@a fSub
3216 * = false) or minuend (@a fSub = true). SP is
3217 * a valid registers for all variations.
3218 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
3219 * (@a fSub = true).
3220 * @param f64Bit true for 64-bit GRPs (default), false for
3221 * 32-bit GPRs.
3222 * @param fSetFlags Whether to set flags (adds / subs) or not
3223 * (add / sub - default).
3224 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
3225 * bits to the left, or not (default).
3226 */
3227DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
3228 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
3229 bool fSetFlags = false, bool fShift12 = false)
3230{
3231 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
3232 return ((uint32_t)f64Bit << 31)
3233 | ((uint32_t)fSub << 30)
3234 | ((uint32_t)fSetFlags << 29)
3235 | UINT32_C(0x11000000)
3236 | ((uint32_t)fShift12 << 22)
3237 | (uImm12AddendSubtrahend << 10)
3238 | (iRegSrc << 5)
3239 | iRegResult;
3240}
3241
3242
3243/** Alias for sub zxr, reg, \#uimm12. */
3244DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
3245 bool f64Bit = true, bool fShift12 = false)
3246{
3247 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
3248 f64Bit, true /*fSetFlags*/, fShift12);
3249}
3250
3251
3252/** ADD dst, src, \#uimm12 */
3253DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
3254 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3255{
3256 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
3257}
3258
3259
3260/** SUB dst, src, \#uimm12 */
3261DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
3262 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3263{
3264 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
3265}
3266
3267
3268/**
3269 * A64: Encodes either add, adds, sub or subs with shifted register.
3270 *
3271 * @returns The encoded instruction.
3272 * @param fSub true for sub and subs, false for add and
3273 * adds.
3274 * @param iRegResult The register to store the result in.
3275 * SP is NOT valid, but ZR is.
3276 * @param iRegSrc1 The register containing the augend (@a fSub
3277 * = false) or minuend (@a fSub = true).
3278 * SP is NOT valid, but ZR is.
3279 * @param iRegSrc2 The register containing the addened (@a fSub
3280 * = false) or subtrahend (@a fSub = true).
3281 * SP is NOT valid, but ZR is.
3282 * @param f64Bit true for 64-bit GRPs (default), false for
3283 * 32-bit GPRs.
3284 * @param fSetFlags Whether to set flags (adds / subs) or not
3285 * (add / sub - default).
3286 * @param cShift The shift count to apply to @a iRegSrc2.
3287 * @param enmShift The shift type to apply to the @a iRegSrc2
3288 * register. kArmv8A64InstrShift_Ror is
3289 * reserved.
3290 */
3291DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3292 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3293 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3294{
3295 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3296 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
3297
3298 return ((uint32_t)f64Bit << 31)
3299 | ((uint32_t)fSub << 30)
3300 | ((uint32_t)fSetFlags << 29)
3301 | UINT32_C(0x0b000000)
3302 | ((uint32_t)enmShift << 22)
3303 | (iRegSrc2 << 16)
3304 | (cShift << 10)
3305 | (iRegSrc1 << 5)
3306 | iRegResult;
3307}
3308
3309
3310/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
3311DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
3312 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3313{
3314 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
3315 f64Bit, true /*fSetFlags*/, cShift, enmShift);
3316}
3317
3318
3319/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3320DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3321 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3322 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3323{
3324 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3325}
3326
3327
3328/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3329DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3330 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3331 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3332{
3333 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3334}
3335
3336
3337/** NEG dst */
3338DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
3339{
3340 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
3341}
3342
3343
3344/** Extension option for 'extended register' instructions. */
3345typedef enum ARMV8A64INSTREXTEND
3346{
3347 kArmv8A64InstrExtend_UxtB = 0,
3348 kArmv8A64InstrExtend_UxtH,
3349 kArmv8A64InstrExtend_UxtW,
3350 kArmv8A64InstrExtend_UxtX,
3351 kArmv8A64InstrExtend_SxtB,
3352 kArmv8A64InstrExtend_SxtH,
3353 kArmv8A64InstrExtend_SxtW,
3354 kArmv8A64InstrExtend_SxtX,
3355 /** The default is either UXTW or UXTX depending on whether the instruction
3356 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
3357 * to the f64Bit value. */
3358 kArmv8A64InstrExtend_Default
3359} ARMV8A64INSTREXTEND;
3360
3361
3362/**
3363 * A64: Encodes either add, adds, sub or subs with extended register encoding.
3364 *
3365 * @returns The encoded instruction.
3366 * @param fSub true for sub and subs, false for add and
3367 * adds.
3368 * @param iRegResult The register to store the result in.
3369 * SP is NOT valid, but ZR is.
3370 * @param iRegSrc1 The register containing the augend (@a fSub
3371 * = false) or minuend (@a fSub = true).
3372 * SP is valid, but ZR is NOT.
3373 * @param iRegSrc2 The register containing the addened (@a fSub
3374 * = false) or subtrahend (@a fSub = true).
3375 * SP is NOT valid, but ZR is.
3376 * @param f64Bit true for 64-bit GRPs (default), false for
3377 * 32-bit GPRs.
3378 * @param fSetFlags Whether to set flags (adds / subs) or not
3379 * (add / sub - default).
3380 * @param enmExtend The type of extension to apply to @a
3381 * iRegSrc2.
3382 * @param cShift The left shift count to apply to @a iRegSrc2
3383 * after enmExtend processing is done.
3384 * Max shift is 4 for some reason.
3385 */
3386DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3387 bool f64Bit = true, bool fSetFlags = false,
3388 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
3389 uint32_t cShift = 0)
3390{
3391 if (enmExtend == kArmv8A64InstrExtend_Default)
3392 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
3393 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
3394
3395 return ((uint32_t)f64Bit << 31)
3396 | ((uint32_t)fSub << 30)
3397 | ((uint32_t)fSetFlags << 29)
3398 | UINT32_C(0x0b200000)
3399 | (iRegSrc2 << 16)
3400 | ((uint32_t)enmExtend << 13)
3401 | (cShift << 10)
3402 | (iRegSrc1 << 5)
3403 | iRegResult;
3404}
3405
3406
3407/**
3408 * A64: Encodes a B (unconditional branch w/ imm) instruction.
3409 *
3410 * @returns The encoded instruction.
3411 * @param iImm26 Signed number of instruction to jump (i.e. *4).
3412 */
3413DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
3414{
3415 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
3416 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
3417}
3418
3419
3420/**
3421 * A64: Encodes a BL (unconditional call w/ imm) instruction.
3422 *
3423 * @returns The encoded instruction.
3424 * @param iImm26 Signed number of instruction to jump (i.e. *4).
3425 */
3426DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
3427{
3428 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
3429}
3430
3431
3432/**
3433 * A64: Encodes a BR (unconditional branch w/ register) instruction.
3434 *
3435 * @returns The encoded instruction.
3436 * @param iReg The register containing the target address.
3437 */
3438DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
3439{
3440 Assert(iReg < 32);
3441 return UINT32_C(0xd61f0000) | (iReg << 5);
3442}
3443
3444
3445/**
3446 * A64: Encodes a BLR instruction.
3447 *
3448 * @returns The encoded instruction.
3449 * @param iReg The register containing the target address.
3450 */
3451DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
3452{
3453 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
3454}
3455
3456
3457/**
3458 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
3459 *
3460 * @returns The encoded instruction.
3461 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
3462 * its not zero.
3463 * @param iImm19 Signed number of instruction to jump (i.e. *4).
3464 * @param iReg The GPR to check for zero / non-zero value.
3465 * @param f64Bit true for 64-bit register, false for 32-bit.
3466 */
3467DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
3468{
3469 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
3470 return ((uint32_t)f64Bit << 31)
3471 | UINT32_C(0x34000000)
3472 | ((uint32_t)fJmpIfNotZero << 24)
3473 | (((uint32_t)iImm19 & 0x7ffff) << 5)
3474 | iReg;
3475}
3476
3477
3478/**
3479 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
3480 *
3481 * @returns The encoded instruction.
3482 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
3483 * its not zero.
3484 * @param iImm14 Signed number of instruction to jump (i.e. *4).
3485 * @param iReg The GPR to check for zero / non-zero value.
3486 * @param iBitNo The bit to test for.
3487 */
3488DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
3489{
3490 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
3491 return ((uint32_t)(iBitNo & 0x20) << (31-5))
3492 | UINT32_C(0x36000000)
3493 | ((uint32_t)fJmpIfNotZero << 24)
3494 | ((iBitNo & 0x1f) << 19)
3495 | (((uint32_t)iImm14 & 0x3fff) << 5)
3496 | iReg;
3497}
3498
3499
3500
3501/** Armv8 Condition codes. */
3502typedef enum ARMV8INSTRCOND
3503{
3504 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
3505 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
3506
3507 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
3508 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
3509 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
3510 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
3511
3512 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
3513 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
3514
3515 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
3516 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
3517
3518 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
3519 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
3520
3521 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
3522 kArmv8InstrCond_Lt, /**< b - Signed less than. */
3523
3524 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
3525 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
3526
3527 kArmv8InstrCond_Al, /**< e - Condition is always true. */
3528 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
3529} ARMV8INSTRCOND;
3530
3531/**
3532 * A64: Encodes conditional branch instruction w/ immediate target.
3533 *
3534 * @returns The encoded instruction.
3535 * @param enmCond The branch condition.
3536 * @param iImm19 Signed number of instruction to jump (i.e. *4).
3537 */
3538DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
3539{
3540 Assert((unsigned)enmCond < 16);
3541 return UINT32_C(0x54000000)
3542 | (((uint32_t)iImm19 & 0x7ffff) << 5)
3543 | (uint32_t)enmCond;
3544}
3545
3546
3547/**
3548 * A64: Encodes the BRK instruction.
3549 *
3550 * @returns The encoded instruction.
3551 * @param uImm16 Unsigned immediate value.
3552 */
3553DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
3554{
3555 Assert(uImm16 < _64K);
3556 return UINT32_C(0xd4200000)
3557 | (uImm16 << 5);
3558}
3559
3560/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
3561 * @{ */
3562#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
3563#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
3564#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
3565#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
3566#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
3567#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
3568#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
3569#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
3570
3571#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
3572#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
3573#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
3574#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
3575#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
3576#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
3577#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
3578#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
3579/** @} */
3580
3581/**
3582 * A64: Encodes CCMP or CCMN with two register operands.
3583 *
3584 * @returns The encoded instruction.
3585 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
3586 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
3587 * @param fNzcv The N, Z, C & V flags values to load if the condition
3588 * does not match. See RMA64_NZCV_F_XXX.
3589 * @param enmCond The condition guarding the compare.
3590 * @param fCCmp Set for CCMP (default), clear for CCMN.
3591 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3592 */
3593DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
3594 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
3595{
3596 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
3597
3598 return ((uint32_t)f64Bit << 31)
3599 | ((uint32_t)fCCmp << 30)
3600 | UINT32_C(0x3a400000)
3601 | (iRegSrc2 << 16)
3602 | ((uint32_t)enmCond << 12)
3603 | (iRegSrc1 << 5)
3604 | fNzcv;
3605}
3606
3607/** CCMP w/ reg. */
3608DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
3609 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3610{
3611 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
3612}
3613
3614
3615/** CCMN w/ reg. */
3616DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
3617 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3618{
3619 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
3620}
3621
3622
3623/**
3624 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
3625 *
3626 * @returns The encoded instruction.
3627 * @param iRegSrc The register. SP is NOT valid, but ZR is.
3628 * @param uImm5 The immediate, to compare iRegSrc with.
3629 * @param fNzcv The N, Z, C & V flags values to load if the condition
3630 * does not match. See RMA64_NZCV_F_XXX.
3631 * @param enmCond The condition guarding the compare.
3632 * @param fCCmp Set for CCMP (default), clear for CCMN.
3633 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3634 */
3635DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
3636 bool fCCmp = true, bool f64Bit = true)
3637{
3638 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
3639
3640 return ((uint32_t)f64Bit << 31)
3641 | ((uint32_t)fCCmp << 30)
3642 | UINT32_C(0x3a400800)
3643 | (uImm5 << 16)
3644 | ((uint32_t)enmCond << 12)
3645 | (iRegSrc << 5)
3646 | fNzcv;
3647}
3648
3649/** CCMP w/ immediate. */
3650DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
3651 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3652{
3653 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
3654}
3655
3656
3657/** CCMN w/ immediate. */
3658DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
3659 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3660{
3661 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
3662}
3663
3664
3665/**
3666 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
3667 *
3668 * @returns The encoded instruction.
3669 * @param uOp Opcode bit 30.
3670 * @param uOp2 Opcode bits 11:10.
3671 * @param iRegResult The result register. SP is NOT valid, but ZR is.
3672 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
3673 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
3674 * @param enmCond The condition guarding the compare.
3675 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3676 */
3677DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
3678 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
3679{
3680 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3681
3682 return ((uint32_t)f64Bit << 31)
3683 | (uOp << 30)
3684 | UINT32_C(0x1a800000)
3685 | (iRegSrc2 << 16)
3686 | ((uint32_t)enmCond << 12)
3687 | (uOp2 << 10)
3688 | (iRegSrc1 << 5)
3689 | iRegResult;
3690}
3691
3692
3693/** A64: Encodes CSEL.
3694 * @see Armv8A64MkInstrCondSelect for details. */
3695DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3696 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3697{
3698 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
3699}
3700
3701
3702/** A64: Encodes CSINC.
3703 * @see Armv8A64MkInstrCondSelect for details. */
3704DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3705 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3706{
3707 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
3708}
3709
3710
3711/** A64: Encodes CSET.
3712 * @see Armv8A64MkInstrCondSelect for details. */
3713DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
3714{
3715 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
3716 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
3717 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
3718}
3719
3720
3721/** A64: Encodes CSINV.
3722 * @see Armv8A64MkInstrCondSelect for details. */
3723DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3724 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3725{
3726 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
3727}
3728
3729/** A64: Encodes CSETM.
3730 * @see Armv8A64MkInstrCondSelect for details. */
3731DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
3732{
3733 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
3734 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
3735 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
3736}
3737
3738
3739/** A64: Encodes CSNEG.
3740 * @see Armv8A64MkInstrCondSelect for details. */
3741DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3742 ARMV8INSTRCOND enmCond, bool f64Bit = true)
3743{
3744 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
3745}
3746
3747
3748/**
3749 * A64: Encodes REV instruction.
3750 *
3751 * @returns The encoded instruction.
3752 * @param iRegDst The destination register. SP is NOT valid.
3753 * @param iRegSrc The source register. SP is NOT valid, but ZR is
3754 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3755 */
3756DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
3757{
3758 Assert(iRegDst < 32); Assert(iRegSrc < 32);
3759
3760 return ((uint32_t)f64Bit << 31)
3761 | UINT32_C(0x5ac00800)
3762 | ((uint32_t)f64Bit << 10)
3763 | (iRegSrc << 5)
3764 | iRegDst;
3765}
3766
3767
3768/**
3769 * A64: Encodes REV16 instruction.
3770 *
3771 * @returns The encoded instruction.
3772 * @param iRegDst The destination register. SP is NOT valid.
3773 * @param iRegSrc The source register. SP is NOT valid, but ZR is
3774 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3775 */
3776DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
3777{
3778 Assert(iRegDst < 32); Assert(iRegSrc < 32);
3779
3780 return ((uint32_t)f64Bit << 31)
3781 | UINT32_C(0x5ac00400)
3782 | (iRegSrc << 5)
3783 | iRegDst;
3784}
3785
3786
3787/**
3788 * A64: Encodes SETF8 & SETF16.
3789 *
3790 * @returns The encoded instruction.
3791 * @param iRegResult The register holding the result. SP is NOT valid.
3792 * @param f16Bit Set for SETF16, clear for SETF8.
3793 */
3794DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
3795{
3796 Assert(iRegResult < 32);
3797
3798 return UINT32_C(0x3a00080d)
3799 | ((uint32_t)f16Bit << 14)
3800 | (iRegResult << 5);
3801}
3802
3803
3804/**
3805 * A64: Encodes MRS (for reading a system register into a GPR).
3806 *
3807 * @returns The encoded instruction.
3808 * @param iRegDst The register to put the result into. SP is NOT valid.
3809 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
3810 * IPRT specific format, of the register to read.
3811 */
3812DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
3813{
3814 Assert(iRegDst < 32);
3815 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
3816
3817 /* Note. The top bit of idSysReg must always be set and is also set in
3818 0xd5300000, otherwise we'll be encoding a different instruction. */
3819 return UINT32_C(0xd5300000)
3820 | (idSysReg << 5)
3821 | iRegDst;
3822}
3823
3824
3825/**
3826 * A64: Encodes MSR (for writing a GPR to a system register).
3827 *
3828 * @returns The encoded instruction.
3829 * @param iRegSrc The register which value to write. SP is NOT valid.
3830 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
3831 * IPRT specific format, of the register to write.
3832 */
3833DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
3834{
3835 Assert(iRegSrc < 32);
3836 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
3837
3838 /* Note. The top bit of idSysReg must always be set and is also set in
3839 0xd5100000, otherwise we'll be encoding a different instruction. */
3840 return UINT32_C(0xd5100000)
3841 | (idSysReg << 5)
3842 | iRegSrc;
3843}
3844
3845
3846/** @} */
3847
3848#endif /* !dtrace && __cplusplus */
3849
3850/** @} */
3851
3852#endif /* !IPRT_INCLUDED_armv8_h */
3853
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