armv8.h@ 105174

Last change on this file since 105174 was 105174, checked in by vboxsync, 5 months ago
include/iprt/armv8.h: Add helper for 3 operand floating point instructions, bugref:10652
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1	/** @file
2	* IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef IPRT_INCLUDED_armv8_h
37	#define IPRT_INCLUDED_armv8_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/cdefs.h>
44	# ifndef RT_IN_ASSEMBLER
45	# include <iprt/types.h>
46	# include <iprt/assert.h>
47	# endif
48	# include <iprt/assertcompile.h>
49	#else
50	# pragma D depends_on library vbox-types.d
51	#endif
52
53	/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
54	* @ingroup grp_rt
55	* @{
56	*/
57
58	/** @name The AArch64 register encoding - deprecated.
59	* @deprecated Use ARMV8_A64_REG_XXX instead.
60	* @todo correct code and drop these remaining ones.
61	* @{ */
62	#define ARMV8_AARCH64_REG_X0 0
63	#define ARMV8_AARCH64_REG_X1 1
64	#define ARMV8_AARCH64_REG_X2 2
65	#define ARMV8_AARCH64_REG_X3 3
66	#define ARMV8_AARCH64_REG_ZR 31
67	/** @} */
68
69	/** @name The AArch64 general purpose register encoding.
70	* @{ */
71	#define ARMV8_A64_REG_X0 0
72	#define ARMV8_A64_REG_X1 1
73	#define ARMV8_A64_REG_X2 2
74	#define ARMV8_A64_REG_X3 3
75	#define ARMV8_A64_REG_X4 4
76	#define ARMV8_A64_REG_X5 5
77	#define ARMV8_A64_REG_X6 6
78	#define ARMV8_A64_REG_X7 7
79	#define ARMV8_A64_REG_X8 8
80	#define ARMV8_A64_REG_X9 9
81	#define ARMV8_A64_REG_X10 10
82	#define ARMV8_A64_REG_X11 11
83	#define ARMV8_A64_REG_X12 12
84	#define ARMV8_A64_REG_X13 13
85	#define ARMV8_A64_REG_X14 14
86	#define ARMV8_A64_REG_X15 15
87	#define ARMV8_A64_REG_X16 16
88	#define ARMV8_A64_REG_X17 17
89	#define ARMV8_A64_REG_X18 18
90	#define ARMV8_A64_REG_X19 19
91	#define ARMV8_A64_REG_X20 20
92	#define ARMV8_A64_REG_X21 21
93	#define ARMV8_A64_REG_X22 22
94	#define ARMV8_A64_REG_X23 23
95	#define ARMV8_A64_REG_X24 24
96	#define ARMV8_A64_REG_X25 25
97	#define ARMV8_A64_REG_X26 26
98	#define ARMV8_A64_REG_X27 27
99	#define ARMV8_A64_REG_X28 28
100	#define ARMV8_A64_REG_X29 29
101	#define ARMV8_A64_REG_X30 30
102	/** @} */
103
104	/** @name The AArch64 32-bit general purpose register names.
105	* @{ */
106	#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
107	#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
108	#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
109	#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
110	#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
111	#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
112	#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
113	#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
114	#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
115	#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
116	#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
117	#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
118	#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
119	#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
120	#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
121	#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
122	#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
123	#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
124	#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
125	#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
126	#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
127	#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
128	#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
129	#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
130	#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
131	#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
132	#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
133	#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
134	#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
135	#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
136	#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
137	/** @} */
138
139	/** @name The AArch64 NEON scalar register encoding.
140	* @{ */
141	#define ARMV8_A64_REG_Q0 0
142	#define ARMV8_A64_REG_Q1 1
143	#define ARMV8_A64_REG_Q2 2
144	#define ARMV8_A64_REG_Q3 3
145	#define ARMV8_A64_REG_Q4 4
146	#define ARMV8_A64_REG_Q5 5
147	#define ARMV8_A64_REG_Q6 6
148	#define ARMV8_A64_REG_Q7 7
149	#define ARMV8_A64_REG_Q8 8
150	#define ARMV8_A64_REG_Q9 9
151	#define ARMV8_A64_REG_Q10 10
152	#define ARMV8_A64_REG_Q11 11
153	#define ARMV8_A64_REG_Q12 12
154	#define ARMV8_A64_REG_Q13 13
155	#define ARMV8_A64_REG_Q14 14
156	#define ARMV8_A64_REG_Q15 15
157	#define ARMV8_A64_REG_Q16 16
158	#define ARMV8_A64_REG_Q17 17
159	#define ARMV8_A64_REG_Q18 18
160	#define ARMV8_A64_REG_Q19 19
161	#define ARMV8_A64_REG_Q20 20
162	#define ARMV8_A64_REG_Q21 21
163	#define ARMV8_A64_REG_Q22 22
164	#define ARMV8_A64_REG_Q23 23
165	#define ARMV8_A64_REG_Q24 24
166	#define ARMV8_A64_REG_Q25 25
167	#define ARMV8_A64_REG_Q26 26
168	#define ARMV8_A64_REG_Q27 27
169	#define ARMV8_A64_REG_Q28 28
170	#define ARMV8_A64_REG_Q29 29
171	#define ARMV8_A64_REG_Q30 30
172	#define ARMV8_A64_REG_Q31 31
173	/** @} */
174
175	/** @name The AArch64 NEON vector register encoding.
176	* @{ */
177	#define ARMV8_A64_REG_V0 ARMV8_A64_REG_Q0
178	#define ARMV8_A64_REG_V1 ARMV8_A64_REG_Q1
179	#define ARMV8_A64_REG_V2 ARMV8_A64_REG_Q2
180	#define ARMV8_A64_REG_V3 ARMV8_A64_REG_Q3
181	#define ARMV8_A64_REG_V4 ARMV8_A64_REG_Q4
182	#define ARMV8_A64_REG_V5 ARMV8_A64_REG_Q5
183	#define ARMV8_A64_REG_V6 ARMV8_A64_REG_Q6
184	#define ARMV8_A64_REG_V7 ARMV8_A64_REG_Q7
185	#define ARMV8_A64_REG_V8 ARMV8_A64_REG_Q8
186	#define ARMV8_A64_REG_V9 ARMV8_A64_REG_Q9
187	#define ARMV8_A64_REG_V10 ARMV8_A64_REG_Q10
188	#define ARMV8_A64_REG_V11 ARMV8_A64_REG_Q11
189	#define ARMV8_A64_REG_V12 ARMV8_A64_REG_Q12
190	#define ARMV8_A64_REG_V13 ARMV8_A64_REG_Q13
191	#define ARMV8_A64_REG_V14 ARMV8_A64_REG_Q14
192	#define ARMV8_A64_REG_V15 ARMV8_A64_REG_Q15
193	#define ARMV8_A64_REG_V16 ARMV8_A64_REG_Q16
194	#define ARMV8_A64_REG_V17 ARMV8_A64_REG_Q17
195	#define ARMV8_A64_REG_V18 ARMV8_A64_REG_Q18
196	#define ARMV8_A64_REG_V19 ARMV8_A64_REG_Q19
197	#define ARMV8_A64_REG_V20 ARMV8_A64_REG_Q20
198	#define ARMV8_A64_REG_V21 ARMV8_A64_REG_Q21
199	#define ARMV8_A64_REG_V22 ARMV8_A64_REG_Q22
200	#define ARMV8_A64_REG_V23 ARMV8_A64_REG_Q23
201	#define ARMV8_A64_REG_V24 ARMV8_A64_REG_Q24
202	#define ARMV8_A64_REG_V25 ARMV8_A64_REG_Q25
203	#define ARMV8_A64_REG_V26 ARMV8_A64_REG_Q26
204	#define ARMV8_A64_REG_V27 ARMV8_A64_REG_Q27
205	#define ARMV8_A64_REG_V28 ARMV8_A64_REG_Q28
206	#define ARMV8_A64_REG_V29 ARMV8_A64_REG_Q29
207	#define ARMV8_A64_REG_V30 ARMV8_A64_REG_Q30
208	#define ARMV8_A64_REG_V31 ARMV8_A64_REG_Q31
209	/** @} */
210
211	/** @name The AArch64 register 31.
212	* @note Register 31 typically refers to the zero register, but can also in
213	* select case (by instruction and opecode field) refer the to stack
214	* pointer of the current exception level. ARM typically uses \<Xn\|SP\>
215	* to indicate that register 31 is taken as SP, if just \<Xn\> is used
216	* 31 will be the zero register.
217	* @{ */
218	/** The stack pointer. */
219	#define ARMV8_A64_REG_SP 31
220	/** The zero register. Reads as zero, writes ignored. */
221	#define ARMV8_A64_REG_XZR 31
222	/** The zero register, the 32-bit register name. */
223	#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
224	/** @} */
225
226	/** @name AArch64 register aliases
227	* @{ */
228	/** The link register is typically mapped to x30 as that's the default pick of
229	* the RET instruction. */
230	#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
231	/** Frame base pointer is typically mapped to x29. */
232	#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
233	/** @} */
234
235
236	/** @name System register encoding.
237	* @{
238	*/
239	/** Mask for the op0 part of an MSR/MRS instruction */
240	#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) \| RT_BIT_32(20))
241	/** Shift for the op0 part of an MSR/MRS instruction */
242	#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
243	/** Returns the op0 part of the given MRS/MSR instruction. */
244	#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
245	/** Mask for the op1 part of an MSR/MRS instruction */
246	#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18))
247	/** Shift for the op1 part of an MSR/MRS instruction */
248	#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
249	/** Returns the op1 part of the given MRS/MSR instruction. */
250	#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
251	/** Mask for the CRn part of an MSR/MRS instruction */
252	#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \
253	\| RT_BIT_32(15) )
254	/** Shift for the CRn part of an MSR/MRS instruction */
255	#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
256	/** Returns the CRn part of the given MRS/MSR instruction. */
257	#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
258	/** Mask for the CRm part of an MSR/MRS instruction */
259	#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \
260	\| RT_BIT_32(11) )
261	/** Shift for the CRm part of an MSR/MRS instruction */
262	#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
263	/** Returns the CRn part of the given MRS/MSR instruction. */
264	#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
265	/** Mask for the op2 part of an MSR/MRS instruction */
266	#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7))
267	/** Shift for the op2 part of an MSR/MRS instruction */
268	#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
269	/** Returns the op2 part of the given MRS/MSR instruction. */
270	#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
271	/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
272	#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK \| ARMV8_AARCH64_SYSREG_OP1_MASK \
273	\| ARMV8_AARCH64_SYSREG_CRN_MASK \| ARMV8_AARCH64_SYSREG_CRN_MASK \
274	\| ARMV8_AARCH64_SYSREG_OP2_MASK)
275	/** @} */
276
277	/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
278	* IPRT specific and not part of the ARMv8 specification.
279	* @{ */
280	#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
281	UINT16_C( (((a_Op0) & 0x3) << 14) \
282	\| (((a_Op1) & 0x7) << 11) \
283	\| (((a_CRn) & 0xf) << 7) \
284	\| (((a_CRm) & 0xf) << 3) \
285	\| ((a_Op2) & 0x7))
286	/** Returns the internal system register ID from the given MRS/MSR instruction. */
287	#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
288	ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
289	ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
290	ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
291	ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
292	ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
293	/** Encodes the given system register ID in the given MSR/MRS instruction. */
294	#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
295	((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) \| (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
296	/** @} */
297
298
299	/** @name System register IDs.
300	* @{ */
301	/** MDSCR_EL1 - RW. */
302	#define ARMV8_AARCH64_SYSREG_MDSCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 2)
303	/** DBGBVR<0..15>_EL1 register - RW. */
304	#define ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 4)
305	/** DBGBCR<0..15>_EL1 register - RW. */
306	#define ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 5)
307	/** DBGWVR<0..15>_EL1 register - RW. */
308	#define ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 6)
309	/** DBGWCR<0..15>_EL1 register - RW. */
310	#define ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 7)
311	/** MDCCINT_EL1 register - RW. */
312	#define ARMV8_AARCH64_SYSREG_MDCCINT_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 0)
313	/** OSLAR_EL1 register - WO. */
314	#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
315	/** OSLSR_EL1 register - RO. */
316	#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
317	/** OSDLR_EL1 register - RW. */
318	#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
319
320	/** MIDR_EL1 register - RO. */
321	#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
322	/** MIPDR_EL1 register - RO. */
323	#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
324	/** REVIDR_EL1 register - RO. */
325	#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
326	/** ID_PFR0_EL1 register - RO. */
327	#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
328	/** ID_PFR1_EL1 register - RO. */
329	#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
330	/** ID_DFR0_EL1 register - RO. */
331	#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
332	/** ID_AFR0_EL1 register - RO. */
333	#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
334	/** ID_MMFR0_EL1 register - RO. */
335	#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
336	/** ID_MMFR1_EL1 register - RO. */
337	#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
338	/** ID_MMFR2_EL1 register - RO. */
339	#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
340	/** ID_MMFR3_EL1 register - RO. */
341	#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
342
343	/** ID_ISAR0_EL1 register - RO. */
344	#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
345	/** ID_ISAR1_EL1 register - RO. */
346	#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
347	/** ID_ISAR2_EL1 register - RO. */
348	#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
349	/** ID_ISAR3_EL1 register - RO. */
350	#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
351	/** ID_ISAR4_EL1 register - RO. */
352	#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
353	/** ID_ISAR5_EL1 register - RO. */
354	#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
355	/** ID_MMFR4_EL1 register - RO. */
356	#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
357	/** ID_ISAR6_EL1 register - RO. */
358	#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
359
360	/** MVFR0_EL1 register - RO. */
361	#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
362	/** MVFR1_EL1 register - RO. */
363	#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
364	/** MVFR2_EL1 register - RO. */
365	#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
366	/** ID_PFR2_EL1 register - RO. */
367	#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
368	/** ID_DFR1_EL1 register - RO. */
369	#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
370	/** ID_MMFR5_EL1 register - RO. */
371	#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
372
373	/** ID_AA64PFR0_EL1 register - RO. */
374	#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
375	/** ID_AA64PFR0_EL1 register - RO. */
376	#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
377	/** ID_AA64ZFR0_EL1 register - RO. */
378	#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
379	/** ID_AA64SMFR0_EL1 register - RO. */
380	#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
381
382	/** ID_AA64DFR0_EL1 register - RO. */
383	#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
384	/** ID_AA64DFR0_EL1 register - RO. */
385	#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
386	/** ID_AA64AFR0_EL1 register - RO. */
387	#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
388	/** ID_AA64AFR1_EL1 register - RO. */
389	#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
390
391	/** ID_AA64ISAR0_EL1 register - RO. */
392	#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
393	/** ID_AA64ISAR1_EL1 register - RO. */
394	#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
395	/** ID_AA64ISAR2_EL1 register - RO. */
396	#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
397
398	/** ID_AA64MMFR0_EL1 register - RO. */
399	#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
400	/** ID_AA64MMFR1_EL1 register - RO. */
401	#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
402	/** ID_AA64MMFR2_EL1 register - RO. */
403	#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
404
405	/** SCTRL_EL1 register - RW. */
406	#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
407	/** ACTRL_EL1 register - RW. */
408	#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
409	/** CPACR_EL1 register - RW. */
410	#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
411	/** RGSR_EL1 register - RW. */
412	#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
413	/** GCR_EL1 register - RW. */
414	#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
415
416	/** ZCR_EL1 register - RW. */
417	#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
418	/** TRFCR_EL1 register - RW. */
419	#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
420	/** SMPRI_EL1 register - RW. */
421	#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
422	/** SMCR_EL1 register - RW. */
423	#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
424
425	/** TTBR0_EL1 register - RW. */
426	#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
427	/** TTBR1_EL1 register - RW. */
428	#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
429	/** TCR_EL1 register - RW. */
430	#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
431
432	/** APIAKeyLo_EL1 register - RW. */
433	#define ARMV8_AARCH64_SYSREG_APIAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 0)
434	/** APIAKeyHi_EL1 register - RW. */
435	#define ARMV8_AARCH64_SYSREG_APIAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 1)
436	/** APIBKeyLo_EL1 register - RW. */
437	#define ARMV8_AARCH64_SYSREG_APIBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 2)
438	/** APIBKeyHi_EL1 register - RW. */
439	#define ARMV8_AARCH64_SYSREG_APIBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 3)
440
441	/** APDAKeyLo_EL1 register - RW. */
442	#define ARMV8_AARCH64_SYSREG_APDAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 0)
443	/** APDAKeyHi_EL1 register - RW. */
444	#define ARMV8_AARCH64_SYSREG_APDAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 1)
445	/** APDBKeyLo_EL1 register - RW. */
446	#define ARMV8_AARCH64_SYSREG_APDBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 2)
447	/** APDBKeyHi_EL1 register - RW. */
448	#define ARMV8_AARCH64_SYSREG_APDBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 3)
449
450	/** APGAKeyLo_EL1 register - RW. */
451	#define ARMV8_AARCH64_SYSREG_APGAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 0)
452	/** APGAKeyHi_EL1 register - RW. */
453	#define ARMV8_AARCH64_SYSREG_APGAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 1)
454
455	/** SPSR_EL1 register - RW. */
456	#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
457	/** ELR_EL1 register - RW. */
458	#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
459
460	/** SP_EL0 register - RW. */
461	#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
462
463	/** PSTATE.SPSel value. */
464	#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
465	/** PSTATE.CurrentEL value. */
466	#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
467	/** PSTATE.PAN value. */
468	#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
469	/** PSTATE.UAO value. */
470	#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
471
472	/** PSTATE.ALLINT value. */
473	#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
474
475	/** ICC_PMR_EL1 register - RW. */
476	#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
477
478	/** AFSR0_EL1 register - RW. */
479	#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
480	/** AFSR1_EL1 register - RW. */
481	#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
482
483	/** ESR_EL1 register - RW. */
484	#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
485
486	/** ERRIDR_EL1 register - RO. */
487	#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
488	/** ERRSELR_EL1 register - RW. */
489	#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
490
491	/** FAR_EL1 register - RW. */
492	#define ARMV8_AARCH64_SYSREG_FAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 6, 0, 0)
493
494	/** PAR_EL1 register - RW. */
495	#define ARMV8_AARCH64_SYSREG_PAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 7, 4, 0)
496
497	/** MAIR_EL1 register - RW. */
498	#define ARMV8_AARCH64_SYSREG_MAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 2, 0)
499
500	/** AMAIR_EL1 register - RW. */
501	#define ARMV8_AARCH64_SYSREG_AMAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 3, 0)
502
503	/** VBAR_EL1 register - RW. */
504	#define ARMV8_AARCH64_SYSREG_VBAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 0, 0)
505
506	/** ICC_IAR0_EL1 register - RO. */
507	#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
508	/** ICC_EOIR0_EL1 register - WO. */
509	#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
510	/** ICC_HPPIR0_EL1 register - WO. */
511	#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
512	/** ICC_BPR0_EL1 register - RW. */
513	#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
514	/** ICC_AP0R0_EL1 register - RW. */
515	#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
516	/** ICC_AP0R1_EL1 register - RW. */
517	#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
518	/** ICC_AP0R2_EL1 register - RW. */
519	#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
520	/** ICC_AP0R3_EL1 register - RW. */
521	#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
522
523	/** ICC_AP1R0_EL1 register - RW. */
524	#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
525	/** ICC_AP1R1_EL1 register - RW. */
526	#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
527	/** ICC_AP1R2_EL1 register - RW. */
528	#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
529	/** ICC_AP1R3_EL1 register - RW. */
530	#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
531	/** ICC_NMIAR1_EL1 register - RO. */
532	#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
533
534	/** ICC_DIR_EL1 register - WO. */
535	#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
536	/** ICC_RPR_EL1 register - RO. */
537	#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
538	/** ICC_SGI1R_EL1 register - WO. */
539	#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
540	/** ICC_ASGI1R_EL1 register - WO. */
541	#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
542	/** ICC_SGI0R_EL1 register - WO. */
543	#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
544
545	/** ICC_IAR1_EL1 register - RO. */
546	#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
547	/** ICC_EOIR1_EL1 register - WO. */
548	#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
549	/** ICC_HPPIR1_EL1 register - RO. */
550	#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
551	/** ICC_BPR1_EL1 register - RW. */
552	#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
553	/** ICC_CTLR_EL1 register - RW. */
554	#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
555	/** ICC_SRE_EL1 register - RW. */
556	#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
557	/** ICC_IGRPEN0_EL1 register - RW. */
558	#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
559	/** ICC_IGRPEN1_EL1 register - RW. */
560	#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
561
562	/** CONTEXTIDR_EL1 register - RW. */
563	#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 1)
564	/** TPIDR_EL1 register - RW. */
565	#define ARMV8_AARCH64_SYSREG_TPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 4)
566
567	/** CNTKCTL_EL1 register - RW. */
568	#define ARMV8_AARCH64_SYSREG_CNTKCTL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 14, 1, 0)
569
570	/** CSSELR_EL1 register - RW. */
571	#define ARMV8_AARCH64_SYSREG_CSSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 2, 0, 0, 0)
572
573	/** NZCV - Status Flags - ??. */
574	#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
575	/** DAIF - Interrupt Mask Bits - ??. */
576	#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
577	/** SVCR - Streaming Vector Control Register - ??. */
578	#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
579	/** DIT - Data Independent Timing - ??. */
580	#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
581	/** SSBS - Speculative Store Bypass Safe - ??. */
582	#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
583	/** TCO - Tag Check Override - ??. */
584	#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
585
586	/** TPIDR_EL0 register - RW. */
587	#define ARMV8_AARCH64_SYSREG_TPIDR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 2)
588	/** TPIDRRO_EL0 register - RO. */
589	#define ARMV8_AARCH64_SYSREG_TPIDRRO_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 3)
590
591	/** CNTFRQ_EL0 register - RW. */
592	#define ARMV8_AARCH64_SYSREG_CNTFRQ_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 0)
593	/** CNTVCT_EL0 register - RW. */
594	#define ARMV8_AARCH64_SYSREG_CNTVCT_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 2)
595
596	/** CNTV_CTL_EL0 register - RW. */
597	#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
598	/** @} */
599
600
601	#ifndef RT_IN_ASSEMBLER
602	/**
603	* SPSR_EL2 (according to chapter C5.2.19)
604	*/
605	typedef union ARMV8SPSREL2
606	{
607	/** The plain unsigned view. */
608	uint64_t u;
609	/** The 8-bit view. */
610	uint8_t au8[8];
611	/** The 16-bit view. */
612	uint16_t au16[4];
613	/** The 32-bit view. */
614	uint32_t au32[2];
615	/** The 64-bit view. */
616	uint64_t u64;
617	} ARMV8SPSREL2;
618	/** Pointer to SPSR_EL2. */
619	typedef ARMV8SPSREL2 *PARMV8SPSREL2;
620	/** Pointer to const SPSR_EL2. */
621	typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
622	#endif /* !RT_IN_ASSEMBLER */
623
624
625	/** @name SPSR_EL2 (When exception is taken from AArch64 state)
626	* @{
627	*/
628	/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
629	#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
630	#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
631	/** Bit 0 - SP - Selected stack pointer. */
632	#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
633	#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
634	/** Bit 1 - Reserved (read as zero). */
635	#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
636	/** Bit 2 - 3 - EL - Exception level. */
637	#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) \| RT_BIT_64(3))
638	#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
639	#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
640	#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
641	/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
642	#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
643	#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
644	/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
645	#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
646	#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
647	/** Bit 6 - I - FIQ interrupt mask. */
648	#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
649	#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
650	/** Bit 7 - I - IRQ interrupt mask. */
651	#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
652	#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
653	/** Bit 8 - A - SError interrupt mask. */
654	#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
655	#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
656	/** Bit 9 - D - Debug Exception mask. */
657	#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
658	#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
659	/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
660	#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) \| RT_BIT_64(11))
661	#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
662	#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
663	/** Bit 12 - SSBS - Speculative Store Bypass. */
664	#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
665	#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
666	/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
667	#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
668	#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
669	/** Bit 14 - 19 - Reserved (read as zero). */
670	#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) \| RT_BIT_64(15) \| RT_BIT_64(16) \
671	\| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
672	/** Bit 20 - IL - Illegal Execution State flag. */
673	#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
674	#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
675	/** Bit 21 - SS - Software Step flag. */
676	#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
677	#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
678	/** Bit 22 - PAN - Privileged Access Never flag. */
679	#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
680	#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
681	/** Bit 23 - UAO - User Access Override flag. */
682	#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
683	#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
684	/** Bit 24 - DIT - Data Independent Timing flag. */
685	#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
686	#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
687	/** Bit 25 - TCO - Tag Check Override flag. */
688	#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
689	#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
690	/** Bit 26 - 27 - Reserved (read as zero). */
691	#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) \| RT_BIT_64(27))
692	/** Bit 28 - V - Overflow condition flag. */
693	#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
694	#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
695	/** Bit 29 - C - Carry condition flag. */
696	#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
697	#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
698	/** Bit 30 - Z - Zero condition flag. */
699	#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
700	#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
701	/** Bit 31 - N - Negative condition flag. */
702	#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
703	#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
704	/** Bit 32 - 63 - Reserved (read as zero). */
705	#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
706	/** Checks whether the given SPSR value contains a AARCH64 execution state. */
707	#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
708	/** @} */
709
710	/** @name Aarch64 Exception levels
711	* @{ */
712	/** Exception Level 0 - User mode. */
713	#define ARMV8_AARCH64_EL_0 0
714	/** Exception Level 1 - Supervisor mode. */
715	#define ARMV8_AARCH64_EL_1 1
716	/** Exception Level 2 - Hypervisor mode. */
717	#define ARMV8_AARCH64_EL_2 2
718	/** @} */
719
720
721	/** @name ESR_EL2 (Exception Syndrome Register, EL2)
722	* @{
723	*/
724	/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
725	#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
726	#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
727	/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
728	#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
729	#define ARMV8_ESR_EL2_IL_BIT 25
730	#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
731	#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
732	/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
733	#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) \| RT_BIT_64(27) \| RT_BIT_64(28) \
734	\| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
735	#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
736	/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
737	#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \
738	\| RT_BIT_64(35) \| RT_BIT_64(36))
739	#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
740	/** @} */
741
742
743	/** @name ESR_EL2 Exception Classes (EC)
744	* @{ */
745	/** Unknown exception reason. */
746	#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
747	/** Trapped WF* instruction. */
748	#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
749	/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
750	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
751	/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
752	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
753	/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
754	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
755	/** AArch32 - Trapped LDC or STC access. */
756	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
757	/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
758	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
759	/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
760	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
761	/** AArch32 - Trapped pointer authentication instruction. */
762	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
763	/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
764	#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
765	/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
766	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
767	/** FEAT_BTI - Branch Target Exception. */
768	#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
769	/** Illegal Execution State. */
770	#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
771	/** AArch32 - SVC instruction execution. */
772	#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
773	/** AArch32 - HVC instruction execution. */
774	#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
775	/** AArch32 - SMC instruction execution. */
776	#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
777	/** AArch64 - SVC instruction execution. */
778	#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
779	/** AArch64 - HVC instruction execution. */
780	#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
781	/** AArch64 - SMC instruction execution. */
782	#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
783	/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
784	#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
785	/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
786	#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
787	/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
788	#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
789	/** FEAT_TME - Exception from TSTART instruction. */
790	#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
791	/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
792	#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
793	/** FEAT_SME - Access to SME functionality trapped. */
794	#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
795	/** FEAT_RME - Exception from Granule Protection Check. */
796	#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
797	/** Instruction Abort from a lower Exception level. */
798	#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
799	/** Instruction Abort from the same Exception level. */
800	#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
801	/** PC alignment fault exception. */
802	#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
803	/** Data Abort from a lower Exception level. */
804	#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
805	/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
806	#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
807	/** SP alignment fault exception. */
808	#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
809	/** FEAT_MOPS - Memory Operation Exception. */
810	#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
811	/** AArch32 - Trapped floating point exception. */
812	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
813	/** AArch64 - Trapped floating point exception. */
814	#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
815	/** SError interrupt. */
816	#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
817	/** Breakpoint Exception from a lower Exception level. */
818	#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
819	/** Breakpoint Exception from the same Exception level. */
820	#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
821	/** Software Step Exception from a lower Exception level. */
822	#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
823	/** Software Step Exception from the same Exception level. */
824	#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
825	/** Watchpoint Exception from a lower Exception level. */
826	#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
827	/** Watchpoint Exception from the same Exception level. */
828	#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
829	/** AArch32 - BKPT instruction execution. */
830	#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
831	/** AArch32 - Vector Catch exception. */
832	#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
833	/** AArch64 - BRK instruction execution. */
834	#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
835	/** @} */
836
837
838	/** @name ISS encoding for Data Abort exceptions.
839	* @{ */
840	/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
841	#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) \| RT_BIT_32(1) \| RT_BIT_32(2) \
842	\| RT_BIT_32(3) \| RT_BIT_32(4) \| RT_BIT_32(5))
843	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
844	/** Bit 6 - WnR - Write not Read. */
845	#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
846	#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
847	/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
848	#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
849	#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
850	/** Bit 8 - CM - Cache maintenance instruction. */
851	#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
852	#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
853	/** Bit 9 - EA - External abort type. */
854	#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
855	#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
856	/** Bit 10 - FnV - FAR not Valid. */
857	#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
858	#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
859	/** Bit 11 - 12 - LST - Load/Store Type. */
860	#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) \| RT_BIT_32(12))
861	#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
862	/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
863	#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
864	#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
865	/** Bit 14 - AR - Acquire/Release semantics. */
866	#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
867	#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
868	/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
869	#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
870	#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
871	/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
872	#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18) \
873	\| RT_BIT_32(19) \| RT_BIT_32(20))
874	#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
875	/** Bit 21 - SSE - Syndrome Sign Extend. */
876	#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
877	#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
878	/** Bit 22 - 23 - SAS - Syndrome Access Size. */
879	#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) \| RT_BIT_32(23))
880	#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
881	/** Bit 24 - ISV - Instruction Syndrome Valid. */
882	#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
883	#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
884	/** @} */
885
886
887	/** @name Data Fault Status Code (DFSC).
888	* @{ */
889	/** Address size fault, level 0 of translation or translation table base register. */
890	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
891	/** Address size fault, level 1. */
892	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
893	/** Address size fault, level 2. */
894	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
895	/** Address size fault, level 3. */
896	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
897	/** Translation fault, level 0. */
898	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
899	/** Translation fault, level 1. */
900	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
901	/** Translation fault, level 2. */
902	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
903	/** Translation fault, level 3. */
904	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
905	/** FEAT_LPA2 - Access flag fault, level 0. */
906	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
907	/** Access flag fault, level 1. */
908	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
909	/** Access flag fault, level 2. */
910	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
911	/** Access flag fault, level 3. */
912	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
913	/** FEAT_LPA2 - Permission fault, level 0. */
914	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
915	/** Permission fault, level 1. */
916	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
917	/** Permission fault, level 2. */
918	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
919	/** Permission fault, level 3. */
920	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
921	/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
922	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
923	/** FEAT_MTE2 - Synchronous Tag Check Fault. */
924	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
925	/** @todo Do the rest (lazy developer). */
926	/** @} */
927
928
929	/** @name SAS encoding.
930	* @{ */
931	/** Byte access. */
932	#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
933	/** Halfword access (uint16_t). */
934	#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
935	/** Word access (uint32_t). */
936	#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
937	/** Doubleword access (uint64_t). */
938	#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
939	/** @} */
940
941
942	/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
943	* @{ */
944	/** Bit 0 - Direction flag. */
945	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
946	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
947	/** Bit 1 - 4 - CRm value from the instruction. */
948	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) \| RT_BIT_32(2) \| RT_BIT_32(3) \
949	\| RT_BIT_32(4))
950	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
951	/** Bit 5 - 9 - Rt value from the instruction. */
952	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7) \
953	\| RT_BIT_32(8) \| RT_BIT_32(9))
954	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
955	/** Bit 10 - 13 - CRn value from the instruction. */
956	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \
957	\| RT_BIT_32(13))
958	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
959	/** Bit 14 - 16 - Op2 value from the instruction. */
960	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(16))
961	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
962	/** Bit 17 - 19 - Op2 value from the instruction. */
963	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) \| RT_BIT_32(18) \| RT_BIT_32(19))
964	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
965	/** Bit 20 - 21 - Op0 value from the instruction. */
966	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) \| RT_BIT_32(21))
967	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
968	/** Bit 22 - 24 - Reserved. */
969	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24))
970	/** @} */
971
972
973	/** @name ISS encoding for trapped HVC instruction exceptions.
974	* @{ */
975	/** Bit 0 - 15 - imm16 value of the instruction. */
976	#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
977	#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
978	/** @} */
979
980
981	/** @name TCR_EL1 - Translation Control Register (EL1)
982	* @{
983	*/
984	/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
985	#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \
986	\| RT_BIT_64(3) \| RT_BIT_64(4) \| RT_BIT_64(5))
987	#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
988	/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
989	#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
990	#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
991	/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
992	#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) \| RT_BIT_64(9))
993	#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
994	/** Non cacheable. */
995	# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
996	/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
997	# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
998	/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
999	# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
1000	/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1001	# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
1002	/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1003	#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) \| RT_BIT_64(11))
1004	#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
1005	/** Non cacheable. */
1006	# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
1007	/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1008	# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
1009	/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1010	# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
1011	/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1012	# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
1013	/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
1014	#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) \| RT_BIT_64(13))
1015	#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
1016	/** Non shareable. */
1017	# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
1018	/** Invalid value. */
1019	# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
1020	/** Outer Shareable. */
1021	# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
1022	/** Inner Shareable. */
1023	# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
1024	/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
1025	#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) \| RT_BIT_64(15))
1026	#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
1027	/** Invalid granule size. */
1028	# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
1029	/** 16KiB granule size. */
1030	# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
1031	/** 4KiB granule size. */
1032	# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
1033	/** 64KiB granule size. */
1034	# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
1035	/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
1036	#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \
1037	\| RT_BIT_64(19) \| RT_BIT_64(20) \| RT_BIT_64(21))
1038	#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
1039	/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
1040	#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
1041	#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
1042	/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
1043	#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
1044	#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
1045	/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1046	#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) \| RT_BIT_64(25))
1047	#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
1048	/** Non cacheable. */
1049	# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
1050	/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1051	# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
1052	/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1053	# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
1054	/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1055	# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
1056	/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1057	#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) \| RT_BIT_64(27))
1058	#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
1059	/** Non cacheable. */
1060	# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
1061	/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1062	# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
1063	/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1064	# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
1065	/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1066	# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
1067	/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
1068	#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) \| RT_BIT_64(29))
1069	#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
1070	/** Non shareable. */
1071	# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
1072	/** Invalid value. */
1073	# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
1074	/** Outer Shareable. */
1075	# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
1076	/** Inner Shareable. */
1077	# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
1078	/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
1079	#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) \| RT_BIT_64(31))
1080	#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
1081	/** Invalid granule size. */
1082	# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
1083	/** 16KiB granule size. */
1084	# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
1085	/** 4KiB granule size. */
1086	# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
1087	/** 64KiB granule size. */
1088	# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
1089	/** Bit 32 - 34 - Intermediate Physical Address Size. */
1090	#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34))
1091	#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
1092	/** IPA - 32 bits, 4GiB. */
1093	# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
1094	/** IPA - 36 bits, 64GiB. */
1095	# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
1096	/** IPA - 40 bits, 1TiB. */
1097	# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
1098	/** IPA - 42 bits, 4TiB. */
1099	# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
1100	/** IPA - 44 bits, 16TiB. */
1101	# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
1102	/** IPA - 48 bits, 256TiB. */
1103	# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
1104	/** IPA - 52 bits, 4PiB. */
1105	# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
1106	/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
1107	#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
1108	#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
1109	/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
1110	#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
1111	#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
1112	/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
1113	#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
1114	#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
1115	/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
1116	#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
1117	#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
1118	/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
1119	#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
1120	#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
1121	/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
1122	#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
1123	#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
1124	/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
1125	#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
1126	#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
1127	/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
1128	#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
1129	#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
1130	/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
1131	#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
1132	#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
1133	/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
1134	#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
1135	#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
1136	/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
1137	#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
1138	#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
1139	/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
1140	#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
1141	#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
1142	/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
1143	#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
1144	#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
1145	/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
1146	#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1147	#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1148	/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1149	#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1150	#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1151	/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1152	#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1153	#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1154	/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1155	#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1156	#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1157	/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1158	#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1159	#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1160	/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1161	#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1162	#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1163	/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1164	#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1165	#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1166	/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1167	#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1168	#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1169	/** Bit 57 - TCMA0 */
1170	#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1171	#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1172	/** Bit 58 - TCMA1 */
1173	#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1174	#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1175	/** Bit 59 - Data Sharing(?). */
1176	#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1177	#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1178	/** @} */
1179
1180
1181	/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1182	* @{
1183	*/
1184	/** Bit 0 - Common not Private (FEAT_TTCNP). */
1185	#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1186	#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1187	/** Bit 1 - 47 - Translation table base address. */
1188	#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1189	#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1)
1190	/** Bit 48 - 63 - ASID. */
1191	#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1192	#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1193	/** @} */
1194
1195
1196	/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1197	* @{ */
1198	/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1199	#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1200	#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1201	#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1202	/** @} */
1203
1204
1205	/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1206	* @{ */
1207	/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1208	#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2))
1209	#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1210	#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1211	/** @} */
1212
1213
1214	/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1215	* @{ */
1216	/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1217	#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2))
1218	#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1219	#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1220	/** @} */
1221
1222
1223	/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1224	* @{ */
1225	/** Bit 0 - Common Binary Pointer Register - RW. */
1226	#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1227	#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1228	/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1229	#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1230	#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1231	/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1232	#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1233	#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1234	/** Bit 8 - 10 - Priority bits - RO. */
1235	#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
1236	#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1237	/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1238	#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) \| RT_BIT_64(12) \| RT_BIT_64(13))
1239	#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1240	/** INTIDS are 16-bit wide. */
1241	# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1242	/** INTIDS are 24-bit wide. */
1243	# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1244	/** Bit 14 - SEI Supported - RO. */
1245	#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1246	#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1247	/** Bit 15 - Affinity 3 Valid - RO. */
1248	#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1249	#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1250	/** Bit 18 - Range Selector Support - RO. */
1251	#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1252	#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1253	/** Bit 19 - Extended INTID range supported - RO. */
1254	#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1255	#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1256	/** All RW bits. */
1257	#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR \| ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE \| ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1258	/** All RO bits (including Res0). */
1259	#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1260	/** @} */
1261
1262
1263	/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1264	* @{ */
1265	/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1266	#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1267	#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1268	/** @} */
1269
1270
1271	/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1272	* @{ */
1273	/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1274	#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1275	#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1276	/** @} */
1277
1278
1279	/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1280	* @{ */
1281	/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1282	#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1283	#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1284	/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1285	#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1286	#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1287	/** Bit 24 - 27 - The INTID of the SGI. */
1288	#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) \| RT_BIT_64(25) \| RT_BIT_64(26) \| RT_BIT_64(27))
1289	#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1290	/* Bit 28 - 31 - Reserved. */
1291	/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1292	#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1293	#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1294	/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1295	#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1296	#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1297	/* Bit 41 - 43 - Reserved. */
1298	/** Bit 44 - 47 - Range selector. */
1299	#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) \| RT_BIT_64(45) \| RT_BIT_64(46) \| RT_BIT_64(47))
1300	#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1301	/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1302	#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1303	#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1304	/* Bit 56 - 63 - Reserved. */
1305	/** @} */
1306
1307
1308	/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1309	* @{ */
1310	/** Bit 0 - Enables the timer. */
1311	#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1312	#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1313	/** Bit 1 - Timer interrupt mask bit. */
1314	#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1315	#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1316	/** Bit 2 - Timer status bit. */
1317	#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1318	#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1319	/** @} */
1320
1321
1322	/** @name OSLAR_EL1 - OS Lock Access Register.
1323	* @{ */
1324	/** Bit 0 - The OS Lock status bit. */
1325	#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1326	#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1327	/** @} */
1328
1329
1330	/** @name OSLSR_EL1 - OS Lock Status Register.
1331	* @{ */
1332	/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1333	#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1334	#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1335	/** Bit 1 - The OS Lock status bit. */
1336	#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1337	#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1338	/** Bit 2 - Not 32-bit access. */
1339	#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1340	#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1341	/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1342	#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1343	#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1344	/** @} */
1345
1346
1347	/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1348	* @{ */
1349	/* Bit 0 - 3 - Reserved. */
1350	/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1351	#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) \| RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7))
1352	#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1353	/** No AES instructions implemented. */
1354	# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1355	/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1356	# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1357	/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1358	# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1359	/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1360	#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10) \| RT_BIT_64(11))
1361	#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1362	/** No SHA1 instructions implemented. */
1363	# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1364	/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1365	# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1366	/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1367	#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) \| RT_BIT_64(13) \| RT_BIT_64(14) \| RT_BIT_64(15))
1368	#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1369	/** No SHA2 instructions implemented. */
1370	# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1371	/** SHA256 instructions implemented (FEAT_SHA256). */
1372	# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1373	/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1374	# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1375	/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1376	#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
1377	#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1378	/** No CRC32 instructions implemented. */
1379	# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1380	/** CRC32 instructions implemented (FEAT_CRC32). */
1381	# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1382	/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1383	#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) \| RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23))
1384	#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1385	/** No Atomic instructions implemented. */
1386	# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1387	/** Atomic instructions implemented (FEAT_LSE). */
1388	# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1389	/** Bit 24 - 27 - Indicates support for TME instructions. */
1390	#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) \| RT_BIT_64(25) \| RT_BIT_64(26) \| RT_BIT_64(27))
1391	#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1392	/** TME instructions are not implemented. */
1393	# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1394	/** TME instructions are implemented. */
1395	# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1396	/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1397	#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) \| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
1398	#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1399	/** No RDMA instructions implemented. */
1400	# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1401	/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1402	# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1403	/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1404	#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \| RT_BIT_64(35))
1405	#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1406	/** No SHA3 instructions implemented. */
1407	# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1408	/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1409	# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1410	/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1411	#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) \| RT_BIT_64(37) \| RT_BIT_64(38) \| RT_BIT_64(39))
1412	#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1413	/** No SM3 instructions implemented. */
1414	# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1415	/** SM3 instructions implemented (FEAT_SM3). */
1416	# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1417	/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1418	#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) \| RT_BIT_64(41) \| RT_BIT_64(42) \| RT_BIT_64(43))
1419	#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1420	/** No SM4 instructions implemented. */
1421	# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1422	/** SM4 instructions implemented (FEAT_SM4). */
1423	# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1424	/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1425	#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) \| RT_BIT_64(45) \| RT_BIT_64(46) \| RT_BIT_64(47))
1426	#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1427	/** No Dot Product instructions implemented. */
1428	# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1429	/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1430	# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1431	/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1432	#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) \| RT_BIT_64(49) \| RT_BIT_64(50) \| RT_BIT_64(51))
1433	#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1434	/** FMLAL and FMLSL instructions are not implemented. */
1435	# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1436	/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1437	# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1438	/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1439	#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) \| RT_BIT_64(53) \| RT_BIT_64(54) \| RT_BIT_64(55))
1440	#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1441	/** No flag manipulation instructions implemented. */
1442	# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1443	/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1444	# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1445	/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1446	# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1447	/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1448	#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) \| RT_BIT_64(57) \| RT_BIT_64(58) \| RT_BIT_64(59))
1449	#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1450	/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1451	# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1452	/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1453	# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1454	/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1455	# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1456	/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1457	#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) \| RT_BIT_64(61) \| RT_BIT_64(62) \| RT_BIT_64(63))
1458	#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1459	/** No Random Number instructions implemented. */
1460	# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1461	/** RNDR and RDNRRS registers are implemented . */
1462	# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1463	/** @} */
1464
1465
1466	/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1467	* @{ */
1468	/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1469	#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
1470	#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1471	/** DC CVAP not supported. */
1472	# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1473	/** DC CVAP supported (FEAT_DPB). */
1474	# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1475	/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1476	# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1477	/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1478	#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) \| RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7))
1479	#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1480	/** Address Authentication using the QARMA5 algorithm is not implemented. */
1481	# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1482	/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1483	# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1484	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1485	# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1486	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1487	# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1488	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1489	# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1490	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1491	# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1492	/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1493	#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10) \| RT_BIT_64(11))
1494	#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1495	/** Address Authentication using the QARMA5 algorithm is not implemented. */
1496	# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1497	/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1498	# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1499	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1500	# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1501	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1502	# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1503	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1504	# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1505	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1506	# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1507	/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1508	#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) \| RT_BIT_64(13) \| RT_BIT_64(14) \| RT_BIT_64(15))
1509	#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1510	/** No FJCVTZS instruction implemented. */
1511	# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1512	/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1513	# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1514	/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1515	#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
1516	#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1517	/** No FCMLA and FCADD instructions implemented. */
1518	# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1519	/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1520	# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1521	/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1522	#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) \| RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23))
1523	#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1524	/** No RCpc instructions implemented. */
1525	# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1526	/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1527	# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1528	/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1529	# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1530	/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1531	#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) \| RT_BIT_64(25) \| RT_BIT_64(26) \| RT_BIT_64(27))
1532	#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1533	/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1534	# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1535	/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1536	# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1537	/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1538	#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) \| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
1539	#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1540	/** Generic Authentication using an implementation defined algorithm is not implemented. */
1541	# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1542	/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1543	# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1544	/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1545	#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \| RT_BIT_64(35))
1546	#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1547	/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1548	# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1549	/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1550	# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1551	/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1552	#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) \| RT_BIT_64(37) \| RT_BIT_64(38) \| RT_BIT_64(39))
1553	#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1554	/** No SB instructions implemented. */
1555	# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1556	/** SB instructions implemented (FEAT_SB). */
1557	# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1558	/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1559	#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) \| RT_BIT_64(41) \| RT_BIT_64(42) \| RT_BIT_64(43))
1560	#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1561	/** Prediction invalidation instructions are not implemented. */
1562	# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1563	/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1564	# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1565	/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1566	#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) \| RT_BIT_64(45) \| RT_BIT_64(46) \| RT_BIT_64(47))
1567	#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1568	/** BFloat16 instructions are not implemented. */
1569	# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1570	/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1571	# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1572	/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1573	# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1574	/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1575	#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) \| RT_BIT_64(49) \| RT_BIT_64(50) \| RT_BIT_64(51))
1576	#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1577	/** Data Gathering Hint instructions are not implemented. */
1578	# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1579	/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1580	# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1581	/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1582	#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) \| RT_BIT_64(53) \| RT_BIT_64(54) \| RT_BIT_64(55))
1583	#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1584	/** No Int8 matrix multiplication instructions implemented. */
1585	# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1586	/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1587	# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1588	/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1589	#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) \| RT_BIT_64(57) \| RT_BIT_64(58) \| RT_BIT_64(59))
1590	#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1591	/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1592	# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1593	/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1594	# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1595	/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1596	#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) \| RT_BIT_64(61) \| RT_BIT_64(62) \| RT_BIT_64(63))
1597	#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1598	/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1599	# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1600	/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1601	# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1602	/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1603	# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1604	/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1605	# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1606	/** @} */
1607
1608
1609	/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1610	* @{ */
1611	/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1612	#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
1613	#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1614	/** WFET and WFIT are not supported. */
1615	# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1616	/** WFET and WFIT are supported (FEAT_WFxT). */
1617	# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1618	/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1619	#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) \| RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7))
1620	#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1621	/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1622	# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1623	/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1624	# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1625	/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1626	#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10) \| RT_BIT_64(11))
1627	#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1628	/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1629	# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1630	/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1631	# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1632	/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1633	#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) \| RT_BIT_64(13) \| RT_BIT_64(14) \| RT_BIT_64(15))
1634	#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1635	/** Address Authentication using the QARMA3 algorithm is not implemented. */
1636	# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1637	/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1638	# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1639	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1640	# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1641	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1642	# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1643	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1644	# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1645	/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1646	# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1647	/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1648	#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
1649	#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1650	/** No Memory Copy and Memory Set instructions implemented. */
1651	# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1652	/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1653	# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1654	/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1655	#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) \| RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23))
1656	#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1657	/** BC instruction is not implemented. */
1658	# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1659	/** BC instruction is implemented (FEAT_HBC). */
1660	# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1661	/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1662	#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) \| RT_BIT_64(25) \| RT_BIT_64(26) \| RT_BIT_64(27))
1663	#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1664	/** ConstPACField() returns FALSE. */
1665	# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1666	/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1667	# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1668	/* Bit 28 - 63 - Reserved. */
1669	/** @} */
1670
1671
1672	/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1673	* @{ */
1674	/** Bit 0 - 3 - EL0 Exception level handling. */
1675	#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
1676	#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1677	/** EL0 can be executed in AArch64 state only. */
1678	# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1679	/** EL0 can be executed in AArch64 and AArch32 state. */
1680	# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1681	/** Bit 4 - 7 - EL1 Exception level handling. */
1682	#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) \| RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7))
1683	#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1684	/** EL1 can be executed in AArch64 state only. */
1685	# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1686	/** EL1 can be executed in AArch64 and AArch32 state. */
1687	# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1688	/** Bit 8 - 11 - EL2 Exception level handling. */
1689	#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10) \| RT_BIT_64(11))
1690	#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1691	/** EL2 is not implemented. */
1692	# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1693	/** EL2 can be executed in AArch64 state only. */
1694	# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1695	/** EL2 can be executed in AArch64 and AArch32 state. */
1696	# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1697	/** Bit 12 - 15 - EL3 Exception level handling. */
1698	#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) \| RT_BIT_64(13) \| RT_BIT_64(14) \| RT_BIT_64(15))
1699	#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1700	/** EL3 is not implemented. */
1701	# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1702	/** EL3 can be executed in AArch64 state only. */
1703	# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1704	/** EL3 can be executed in AArch64 and AArch32 state. */
1705	# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1706	/** Bit 16 - 19 - Floating-point support. */
1707	#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
1708	#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1709	/** Floating-point is implemented and support single and double precision. */
1710	# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1711	/** Floating-point is implemented and support single, double and half precision. */
1712	# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1713	/** Floating-point is not implemented. */
1714	# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1715	/** Bit 20 - 23 - Advanced SIMD support. */
1716	#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) \| RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23))
1717	#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1718	/** Advanced SIMD is implemented and support single and double precision. */
1719	# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1720	/** Advanced SIMD is implemented and support single, double and half precision. */
1721	# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1722	/** Advanced SIMD is not implemented. */
1723	# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1724	/** Bit 24 - 27 - System register GIC CPU interface support. */
1725	#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) \| RT_BIT_64(25) \| RT_BIT_64(26) \| RT_BIT_64(27))
1726	#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1727	/** GIC CPU interface system registers are not implemented. */
1728	# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1729	/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1730	# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1731	/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1732	# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1733	/** Bit 28 - 31 - RAS Extension version. */
1734	#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) \| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
1735	#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1736	/** No RAS extension. */
1737	# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1738	/** RAS Extension implemented. */
1739	# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1740	/** FEAT_RASv1p1 implemented. */
1741	# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1742	/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1743	#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \| RT_BIT_64(35))
1744	#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1745	/** SVE is not supported. */
1746	# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1747	/** SVE is supported. */
1748	# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1749	/** Bit 36 - 39 - Secure EL2 support. */
1750	#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) \| RT_BIT_64(37) \| RT_BIT_64(38) \| RT_BIT_64(39))
1751	#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1752	/** Secure EL2 is not supported. */
1753	# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1754	/** Secure EL2 is implemented. */
1755	# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1756	/** Bit 40 - 43 - MPAM support. */
1757	#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) \| RT_BIT_64(41) \| RT_BIT_64(42) \| RT_BIT_64(43))
1758	#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
1759	/** MPAM extension major version number is 0. */
1760	# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
1761	/** MPAM extension major version number is 1. */
1762	# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
1763	/** Bit 44 - 47 - Activity Monitor Extension support. */
1764	#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) \| RT_BIT_64(45) \| RT_BIT_64(46) \| RT_BIT_64(47))
1765	#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
1766	/** Activity Monitor extension is not implemented. */
1767	# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
1768	/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
1769	# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
1770	/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
1771	# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
1772	/** Bit 48 - 51 - Data Independent Timing support. */
1773	#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) \| RT_BIT_64(49) \| RT_BIT_64(50) \| RT_BIT_64(51))
1774	#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
1775	/** AArch64 does not guarantee constant execution time of any instructions. */
1776	# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
1777	/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
1778	# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
1779	/** Bit 52 - 55 - Realm Management Extension support. */
1780	#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) \| RT_BIT_64(53) \| RT_BIT_64(54) \| RT_BIT_64(55))
1781	#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
1782	/** Realm Management Extension not implemented. */
1783	# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
1784	/** RMEv1 is implemented (FEAT_RME). */
1785	# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
1786	/** Bit 56 - 59 - Speculative use out of context branch targets support. */
1787	#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) \| RT_BIT_64(57) \| RT_BIT_64(58) \| RT_BIT_64(59))
1788	#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
1789	/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
1790	# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
1791	/** FEAT_CSV2 is implemented. */
1792	# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
1793	/** FEAT_CSV2_2 is implemented. */
1794	# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
1795	/** FEAT_CSV2_3 is implemented. */
1796	# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
1797	/** Bit 60 - 63 - Speculative use of faulting data support. */
1798	#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) \| RT_BIT_64(61) \| RT_BIT_64(62) \| RT_BIT_64(63))
1799	#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
1800	/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
1801	# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
1802	/** FEAT_CSV3 is supported . */
1803	# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
1804	/** @} */
1805
1806
1807	/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
1808	* @{ */
1809	/** Bit 0 - 3 - Branch Target Identification support. */
1810	#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
1811	#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
1812	/** The Branch Target Identification mechanism is not implemented. */
1813	# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
1814	/** The Branch Target Identifcation mechanism is implemented. */
1815	# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
1816	/** Bit 4 - 7 - Speculative Store Bypassing control support. */
1817	#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) \| RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7))
1818	#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
1819	/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
1820	# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
1821	/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
1822	# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
1823	/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
1824	* to directly read and write the PSTATE.SSBS field. */
1825	# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
1826	/** Bit 8 - 11 - Memory Tagging Extension support. */
1827	#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10) \| RT_BIT_64(11))
1828	#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
1829	/** MTE is not implemented. */
1830	# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
1831	/** Instruction only Memory Tagging Extensions implemented. */
1832	# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
1833	/** Full Memory Tagging Extension implemented. */
1834	# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
1835	/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
1836	# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
1837	/** Bit 12 - 15 - RAS Extension fractional field. */
1838	#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) \| RT_BIT_64(13) \| RT_BIT_64(14) \| RT_BIT_64(15))
1839	#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
1840	/** RAS Extension is implemented. */
1841	# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
1842	/** FEAT_RASv1p1 is implemented. */
1843	# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
1844	/** Bit 16 - 19 - MPAM minor version number. */
1845	#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
1846	#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
1847	/** The minor version of number of the MPAM extension is 0. */
1848	# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
1849	/** The minor version of number of the MPAM extension is 1. */
1850	# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
1851	/* Bit 20 - 23 - Reserved. */
1852	/** Bit 24 - 27 - Scalable Matrix Extension support. */
1853	#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) \| RT_BIT_64(25) \| RT_BIT_64(26) \| RT_BIT_64(27))
1854	#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
1855	/** Scalable Matrix Extensions are not implemented. */
1856	# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
1857	/** Scalable Matrix Extensions are implemented (FEAT_SME). */
1858	# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
1859	/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
1860	# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
1861	/** Bit 28 - 31 - Random Number trap to EL3 support. */
1862	#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) \| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
1863	#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
1864	/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
1865	# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
1866	/** Trapping of RNDR and RDNRRS to EL3 is supported. */
1867	# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
1868	/** Bit 32 - 35 - CSV2 fractional field. */
1869	#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \| RT_BIT_64(35))
1870	#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
1871	/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
1872	# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
1873	/** FEAT_CSV2_1p1 is implemented. */
1874	# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
1875	/** FEAT_CSV2_1p2 is implemented. */
1876	# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
1877	/** Bit 36 - 39 - Non-maskable Interrupt support. */
1878	#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) \| RT_BIT_64(37) \| RT_BIT_64(38) \| RT_BIT_64(39))
1879	#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
1880	/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
1881	# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
1882	/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
1883	# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
1884	/** @} */
1885
1886
1887	/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
1888	* @{ */
1889	/** Bit 0 - 3 - Physical Address range supported. */
1890	#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
1891	#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
1892	/** Physical Address range is 32 bits, 4GiB. */
1893	# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
1894	/** Physical Address range is 36 bits, 64GiB. */
1895	# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
1896	/** Physical Address range is 40 bits, 1TiB. */
1897	# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
1898	/** Physical Address range is 42 bits, 4TiB. */
1899	# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
1900	/** Physical Address range is 44 bits, 16TiB. */
1901	# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
1902	/** Physical Address range is 48 bits, 256TiB. */
1903	# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
1904	/** Physical Address range is 52 bits, 4PiB. */
1905	# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
1906	/** Bit 4 - 7 - Number of ASID bits. */
1907	#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) \| RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7))
1908	#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
1909	/** ASID bits is 8. */
1910	# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
1911	/** ASID bits is 16. */
1912	# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
1913	/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
1914	#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10) \| RT_BIT_64(11))
1915	#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
1916	/** No mixed-endian support. */
1917	# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
1918	/** Mixed-endian supported. */
1919	# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
1920	/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
1921	#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) \| RT_BIT_64(13) \| RT_BIT_64(14) \| RT_BIT_64(15))
1922	#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
1923	/** No distinction between Secure and Non-secure Memory supported. */
1924	# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
1925	/** Distinction between Secure and Non-secure Memory supported. */
1926	# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
1927	/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
1928	#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
1929	#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
1930	/** No mixed-endian support at EL0. */
1931	# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
1932	/** Mixed-endian support at EL0. */
1933	# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
1934	/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
1935	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) \| RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23))
1936	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
1937	/** 16KiB granule size not supported. */
1938	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
1939	/** 16KiB granule size is supported. */
1940	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
1941	/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1942	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
1943	/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
1944	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) \| RT_BIT_64(25) \| RT_BIT_64(26) \| RT_BIT_64(27))
1945	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
1946	/** 64KiB granule supported. */
1947	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
1948	/** 64KiB granule not supported. */
1949	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
1950	/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
1951	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) \| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
1952	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
1953	/** 4KiB granule supported. */
1954	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
1955	/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1956	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
1957	/** 4KiB granule not supported. */
1958	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
1959	/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
1960	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \| RT_BIT_64(35))
1961	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
1962	/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
1963	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
1964	/** 16KiB granule not supported at stage 2. */
1965	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
1966	/** 16KiB granule supported at stage 2. */
1967	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
1968	/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1969	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
1970	/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
1971	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) \| RT_BIT_64(37) \| RT_BIT_64(38) \| RT_BIT_64(39))
1972	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
1973	/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
1974	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
1975	/** 64KiB granule not supported at stage 2. */
1976	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
1977	/** 64KiB granule supported at stage 2. */
1978	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
1979	/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1980	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) \| RT_BIT_64(41) \| RT_BIT_64(42) \| RT_BIT_64(43))
1981	#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
1982	/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
1983	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
1984	/** 4KiB granule not supported at stage 2. */
1985	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
1986	/** 4KiB granule supported at stage 2. */
1987	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
1988	/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1989	# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
1990	/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
1991	#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) \| RT_BIT_64(45) \| RT_BIT_64(46) \| RT_BIT_64(47))
1992	#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
1993	/** All exception entries and exits are context synchronization events. */
1994	# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
1995	/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
1996	# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
1997	/* Bit 48 - 55 - Reserved. */
1998	/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
1999	#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) \| RT_BIT_64(57) \| RT_BIT_64(58) \| RT_BIT_64(59))
2000	#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
2001	/** Fine-grained trap controls are not implemented. */
2002	# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
2003	/** Fine-grained trap controls are implemented (FEAT_FGT). */
2004	# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
2005	/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
2006	#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) \| RT_BIT_64(61) \| RT_BIT_64(62) \| RT_BIT_64(63))
2007	#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
2008	/** Enhanced Counter Virtualization is not implemented. */
2009	# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
2010	/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
2011	# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
2012	/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
2013	# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
2014	/** @} */
2015
2016
2017	/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
2018	* @{ */
2019	/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
2020	#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
2021	#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
2022	/** Hardware update of the Access flag and dirty state are not supported. */
2023	# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
2024	/** Support for hardware update of the Access flag for Block and Page descriptors. */
2025	# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
2026	/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
2027	# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
2028	/** Bit 4 - 7 - EL1 Exception level handling. */
2029	#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) \| RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7))
2030	#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
2031	/** VMID bits is 8. */
2032	# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
2033	/** VMID bits is 16 (FEAT_VMID16). */
2034	# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
2035	/** Bit 8 - 11 - Virtualization Host Extensions support. */
2036	#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10) \| RT_BIT_64(11))
2037	#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
2038	/** Virtualization Host Extensions are not supported. */
2039	# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
2040	/** Virtualization Host Extensions are supported. */
2041	# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
2042	/** Bit 12 - 15 - Hierarchical Permission Disables. */
2043	#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) \| RT_BIT_64(13) \| RT_BIT_64(14) \| RT_BIT_64(15))
2044	#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
2045	/** Disabling of hierarchical controls not supported. */
2046	# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
2047	/** Disabling of hierarchical controls supported (FEAT_HPDS). */
2048	# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
2049	/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
2050	# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
2051	/** Bit 16 - 19 - LORegions support. */
2052	#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
2053	#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
2054	/** LORegions not supported. */
2055	# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
2056	/** LORegions supported. */
2057	# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
2058	/** Bit 20 - 23 - Privileged Access Never support. */
2059	#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) \| RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23))
2060	#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
2061	/** PAN not supported. */
2062	# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
2063	/** PAN supported (FEAT_PAN). */
2064	# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
2065	/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
2066	# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
2067	/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
2068	# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
2069	/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
2070	#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) \| RT_BIT_64(25) \| RT_BIT_64(26) \| RT_BIT_64(27))
2071	#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
2072	/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
2073	# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
2074	/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
2075	# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
2076	/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
2077	#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) \| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
2078	#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
2079	/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
2080	# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
2081	/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
2082	# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
2083	/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
2084	#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \| RT_BIT_64(35))
2085	#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
2086	/** Configurable delayed trapping of WFE is not supported. */
2087	# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
2088	/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
2089	# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
2090	/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
2091	#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) \| RT_BIT_64(37) \| RT_BIT_64(38) \| RT_BIT_64(39))
2092	#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
2093	/** Enhanced Translation Synchronization is not supported. */
2094	# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
2095	/** Enhanced Translation Synchronization is implemented. */
2096	# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
2097	/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2098	#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) \| RT_BIT_64(41) \| RT_BIT_64(42) \| RT_BIT_64(43))
2099	#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
2100	/** HCRX_EL2 and its associated EL3 trap are not supported. */
2101	# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
2102	/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
2103	# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
2104	/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
2105	#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) \| RT_BIT_64(45) \| RT_BIT_64(46) \| RT_BIT_64(47))
2106	#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
2107	/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
2108	# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
2109	/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
2110	# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
2111	/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
2112	#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) \| RT_BIT_64(49) \| RT_BIT_64(50) \| RT_BIT_64(51))
2113	#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
2114	/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
2115	# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
2116	/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
2117	# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
2118	/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
2119	#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) \| RT_BIT_64(53) \| RT_BIT_64(54) \| RT_BIT_64(55))
2120	#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
2121	/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
2122	# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
2123	/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
2124	# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
2125	/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
2126	#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) \| RT_BIT_64(57) \| RT_BIT_64(58) \| RT_BIT_64(59))
2127	#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
2128	/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
2129	# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
2130	/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
2131	# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
2132	/* Bit 60 - 63 - Reserved. */
2133	/** @} */
2134
2135
2136	/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
2137	* @{ */
2138	/** Bit 0 - 3 - Indicates support for Common not Private translations. */
2139	#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
2140	#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
2141	/** Common not Private translations are not supported. */
2142	# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
2143	/** Support for Common not Private translations (FEAT_TTNCP). */
2144	# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
2145	/** Bit 4 - 7 - Indicates support for User Access Override. */
2146	#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) \| RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7))
2147	#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2148	/** User Access Override is not supported. */
2149	# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2150	/** User Access Override is supported (FEAT_UAO). */
2151	# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2152	/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2153	#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10) \| RT_BIT_64(11))
2154	#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2155	/** LSMAOE and nTLSMD bits are not supported. */
2156	# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2157	/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2158	# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2159	/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2160	#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) \| RT_BIT_64(13) \| RT_BIT_64(14) \| RT_BIT_64(15))
2161	#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2162	/** IESB bit is not supported. */
2163	# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2164	/** IESB bit is supported (FEAT_IESB). */
2165	# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2166	/** Bit 16 - 19 - Indicates support for larger virtual address. */
2167	#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
2168	#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2169	/** Virtual address range is 48 bits. */
2170	# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2171	/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2172	# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2173	/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2174	#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) \| RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23))
2175	#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2176	/** CCSIDR_EL1 register format is 32-bit. */
2177	# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2178	/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2179	# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2180	/** Bit 24 - 27 - Indicates support for nested virtualization. */
2181	#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) \| RT_BIT_64(25) \| RT_BIT_64(26) \| RT_BIT_64(27))
2182	#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2183	/** Nested virtualization is not supported. */
2184	# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2185	/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2186	# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2187	/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2188	# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2189	/** Bit 28 - 31 - Indicates support for small translation tables. */
2190	#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) \| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
2191	#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2192	/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2193	# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2194	/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2195	# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2196	/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2197	#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \| RT_BIT_64(35))
2198	#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2199	/** Unaligned single-copy atomicity and atomic functions are not supported. */
2200	# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2201	/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2202	# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2203	/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2204	#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) \| RT_BIT_64(37) \| RT_BIT_64(38) \| RT_BIT_64(39))
2205	#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2206	/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2207	# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2208	/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2209	# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2210	/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2211	#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) \| RT_BIT_64(41) \| RT_BIT_64(42) \| RT_BIT_64(43))
2212	#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2213	/** HCR_EL2.FWB bit is not supported. */
2214	# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2215	/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2216	# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2217	/* Bit 44 - 47 - Reserved. */
2218	/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2219	#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) \| RT_BIT_64(49) \| RT_BIT_64(50) \| RT_BIT_64(51))
2220	#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2221	/** TLB maintenance instructions by address have bits [47:44] Res0. */
2222	# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2223	/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2224	# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2225	/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2226	* changing block size for a translation. */
2227	#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) \| RT_BIT_64(53) \| RT_BIT_64(54) \| RT_BIT_64(55))
2228	#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2229	/** Level 0 support for changing block size is supported (FEAT_BBM). */
2230	# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2231	/** Level 1 support for changing block size is supported (FEAT_BBM). */
2232	# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2233	/** Level 2 support for changing block size is supported (FEAT_BBM). */
2234	# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2235	/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2236	#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) \| RT_BIT_64(57) \| RT_BIT_64(58) \| RT_BIT_64(59))
2237	#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2238	/** Enhanced Virtualization Traps are not supported. */
2239	# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2240	/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2241	# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2242	/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2243	# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2244	/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2245	#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) \| RT_BIT_64(61) \| RT_BIT_64(62) \| RT_BIT_64(63))
2246	#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2247	/** E0PDx mechanism is not supported. */
2248	# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2249	/** E0PDx mechanism is supported (FEAT_E0PD). */
2250	# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2251	/** @} */
2252
2253
2254	/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2255	* @{ */
2256	/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2257	#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
2258	#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2259	/** Armv8 debug architecture version. */
2260	# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2261	/** Armv8 debug architecture version with virtualization host extensions. */
2262	# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2263	/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2264	# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2265	/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2266	# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2267	/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2268	# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2269	/** Bit 4 - 7 - Indicates trace support. */
2270	#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) \| RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7))
2271	#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2272	/** Trace unit System registers not implemented. */
2273	# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2274	/** Trace unit System registers supported. */
2275	# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2276	/** Bit 8 - 11 - Performance Monitors Extension version. */
2277	#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10) \| RT_BIT_64(11))
2278	#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2279	/** Performance Monitors Extension not supported. */
2280	# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2281	/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2282	# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2283	/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2284	# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2285	/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2286	# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2287	/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2288	# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2289	/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2290	# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2291	/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2292	# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2293	/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2294	#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) \| RT_BIT_64(13) \| RT_BIT_64(14) \| RT_BIT_64(15))
2295	#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2296	/* Bit 16 - 19 - Reserved 0. */
2297	/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2298	#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) \| RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23))
2299	#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2300	/* Bit 24 - 27 - Reserved 0. */
2301	/** Bit 28 - 31 - Number of context-aware breakpoints. */
2302	#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) \| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
2303	#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2304	/** Bit 32 - 35 - Statistical Profiling Extension version. */
2305	#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \| RT_BIT_64(35))
2306	#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2307	/** Statistical Profiling Extension not implemented. */
2308	# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2309	/** Statistical Profiling Extension supported (FEAT_SPE). */
2310	# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2311	/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2312	# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2313	/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2314	# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2315	/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2316	# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2317	/** Bit 36 - 39 - OS Double Lock implemented. */
2318	#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) \| RT_BIT_64(37) \| RT_BIT_64(38) \| RT_BIT_64(39))
2319	#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2320	/** OS Double Lock is not implemented. */
2321	# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2322	/** OS Double Lock is supported (FEAT_DoubleLock). */
2323	# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2324	/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2325	#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) \| RT_BIT_64(41) \| RT_BIT_64(42) \| RT_BIT_64(43))
2326	#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2327	/** Armv8.4 self-hosted Trace Extension not implemented. */
2328	# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2329	/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2330	# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2331	/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2332	#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) \| RT_BIT_64(45) \| RT_BIT_64(46) \| RT_BIT_64(47))
2333	#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2334	/** Trace Buffer Extension is not implemented. */
2335	# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2336	/** Trace Buffer Extension is supported (FEAT_TRBE). */
2337	# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2338	/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2339	#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) \| RT_BIT_64(49) \| RT_BIT_64(50) \| RT_BIT_64(51))
2340	#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2341	/** Multi-threaded PMU extension is not implemented. */
2342	# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2343	/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2344	# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2345	/** Multi-threaded PMU extension is not implemented. */
2346	# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2347	/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2348	#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) \| RT_BIT_64(53) \| RT_BIT_64(54) \| RT_BIT_64(55))
2349	#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2350	/** Branch Record Buffer extension is not implemented. */
2351	# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2352	/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2353	# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2354	/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2355	# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2356	/* Bit 56 - 59 - Reserved. */
2357	/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2358	#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) \| RT_BIT_64(61) \| RT_BIT_64(62) \| RT_BIT_64(63))
2359	#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2360	/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2361	# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2362	/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2363	# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2364	/** @} */
2365
2366
2367	#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) \|\| defined(DOXYGEN_RUNNING)
2368	/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2369	* @ingroup grp_rt_armv8
2370	*
2371	* A few inlined functions and macros for assiting in encoding common ARMv8
2372	* instructions.
2373	*
2374	* @{ */
2375
2376	/** A64: Official NOP instruction. */
2377	#define ARMV8_A64_INSTR_NOP UINT32_C(0xd503201f)
2378	/** A64: Return instruction. */
2379	#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2380	/** A64: Return instruction with LR pointer authentication using SP and key A. */
2381	#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2382	/** A64: Return instruction with LR pointer authentication using SP and key B. */
2383	#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2384	/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2385	#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2386	/** A64: Insert pointer authentication code into LR using SP and key B. */
2387	#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2388	/** A64: Insert pointer authentication code into LR using XZR and key B. */
2389	#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2390	/** A64: Invert the carry flag (PSTATE.C). */
2391	#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
2392
2393
2394	typedef enum
2395	{
2396	/** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
2397	* and update the register. */
2398	kArm64InstrStLdPairType_PostIndex = 1,
2399	/** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2400	* but don't update the register. */
2401	kArm64InstrStLdPairType_Signed = 2,
2402	/** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2403	* and update the register. */
2404	kArm64InstrStLdPairType_PreIndex = 3
2405	} ARM64INSTRSTLDPAIRTYPE;
2406
2407	/**
2408	* A64: Encodes either stp (store register pair) or ldp (load register pair).
2409	*
2410	* @returns The encoded instruction.
2411	* @param fLoad true for ldp, false of stp.
2412	* @param u2Opc When @a fSimdFp is @c false:
2413	* - 0 for 32-bit GPRs (Wt).
2414	* - 1 for encoding stgp or ldpsw.
2415	* - 2 for 64-bit GRPs (Xt).
2416	* - 3 illegal.
2417	* When @a fSimdFp is @c true:
2418	* - 0 for 32-bit SIMD&FP registers (St).
2419	* - 1 for 64-bit SIMD&FP registers (Dt).
2420	* - 2 for 128-bit SIMD&FP regsiters (Qt).
2421	* @param enmType The instruction variant wrt addressing and updating of the
2422	* addressing register.
2423	* @param iReg1 The first register to store/load.
2424	* @param iReg2 The second register to store/load.
2425	* @param iBaseReg The base register to use when addressing. SP is allowed.
2426	* @param iImm7 Signed addressing immediate value scaled, range -64..63,
2427	* will be multiplied by the register size.
2428	* @param fSimdFp true for SIMD&FP registers, false for GPRs and
2429	* stgp/ldpsw instructions.
2430	*/
2431	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
2432	uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2433	bool fSimdFp = false)
2434	{
2435	Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
2436	return (u2Opc << 30)
2437	\| UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
2438	\| ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
2439	\| ((uint32_t)enmType << 23)
2440	\| ((uint32_t)fLoad << 22)
2441	\| (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
2442	\| (iReg2 << 10)
2443	\| (iBaseReg << 5)
2444	\| iReg1;
2445	}
2446
2447
2448	/** A64: ldp x1, x2, [x3] */
2449	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2450	ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2451	bool f64Bit = true)
2452	{
2453	return Armv8A64MkInstrStLdPair(true /fLoad/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2454	}
2455
2456
2457	/** A64: stp x1, x2, [x3] */
2458	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2459	ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2460	bool f64Bit = true)
2461	{
2462	return Armv8A64MkInstrStLdPair(false /fLoad/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2463	}
2464
2465
2466	typedef enum /* Size VR Opc */
2467	{ /* \ \| / */
2468	kArmv8A64InstrLdStType_Mask_Size = 0x300,
2469	kArmv8A64InstrLdStType_Mask_VR = 0x010,
2470	kArmv8A64InstrLdStType_Mask_Opc = 0x003,
2471	kArmv8A64InstrLdStType_Shift_Size = 8,
2472	kArmv8A64InstrLdStType_Shift_VR = 4,
2473	kArmv8A64InstrLdStType_Shift_Opc = 0,
2474
2475	kArmv8A64InstrLdStType_St_Byte = 0x000,
2476	kArmv8A64InstrLdStType_Ld_Byte = 0x001,
2477	kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
2478	kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
2479
2480	kArmv8A64InstrLdStType_St_Half = 0x100, /*< Half = 16-bit /
2481	kArmv8A64InstrLdStType_Ld_Half = 0x101, /*< Half = 16-bit /
2482	kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /*< Half = 16-bit /
2483	kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /*< Half = 16-bit /
2484
2485	kArmv8A64InstrLdStType_St_Word = 0x200, /*< Word = 32-bit /
2486	kArmv8A64InstrLdStType_Ld_Word = 0x201, /*< Word = 32-bit /
2487	kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /*< Word = 32-bit /
2488
2489	kArmv8A64InstrLdStType_St_Dword = 0x300, /*< Dword = 64-bit /
2490	kArmv8A64InstrLdStType_Ld_Dword = 0x301, /*< Dword = 64-bit /
2491
2492	kArmv8A64InstrLdStType_Prefetch = 0x302, /*< Not valid in all variations, check docs. /
2493
2494	kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
2495	kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
2496	kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
2497	kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
2498
2499	kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /*< Half = 16-bit /
2500	kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /*< Half = 16-bit /
2501
2502	kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /*< Word = 32-bit /
2503	kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /*< Word = 32-bit /
2504
2505	kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /*< Dword = 64-bit /
2506	kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /*< Dword = 64-bit /
2507
2508	} ARMV8A64INSTRLDSTTYPE;
2509	/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
2510	#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
2511
2512
2513	/**
2514	* A64: Encodes load/store with unscaled 9-bit signed immediate.
2515	*
2516	* @returns The encoded instruction.
2517	* @param u32Opcode The base opcode value.
2518	* @param enmType The load/store instruction type. Prefech valid (PRFUM)
2519	* @param iReg The register to load into / store.
2520	* @param iBaseReg The base register to use when addressing. SP is allowed.
2521	* @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2522	*/
2523	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
2524	uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2525	{
2526	Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
2527	return u32Opcode
2528	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2529	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2530	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2531	\| (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
2532	\| (iBaseReg << 5)
2533	\| iReg;
2534	}
2535
2536
2537	/**
2538	* A64: Encodes load/store with unscaled 9-bit signed immediate.
2539	*
2540	* @returns The encoded instruction.
2541	* @param enmType The load/store instruction type. Prefech valid (PRFUM)
2542	* @param iReg The register to load into / store.
2543	* @param iBaseReg The base register to use when addressing. SP is allowed.
2544	* @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2545	*/
2546	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
2547	uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2548	{
2549	/* 3 2 1 0 */
2550	/* 10987654321098765432109876543210 */
2551	return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
2552	enmType, iReg, iBaseReg, i9ImmDisp);
2553	}
2554
2555	/**
2556	* A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
2557	*
2558	* @returns The encoded instruction.
2559	* @param enmType The load/store instruction type. Prefech not valid.
2560	* @param iReg The register to load into / store.
2561	* @param iBaseReg The base register to use when addressing. SP is allowed.
2562	* Written back.
2563	* @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2564	*/
2565	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2566	uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2567	{
2568	Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2569	/* 10987654321098765432109876543210 */
2570	return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
2571	enmType, iReg, iBaseReg, i9ImmDisp);
2572	}
2573
2574	/**
2575	* A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
2576	*
2577	* @returns The encoded instruction.
2578	* @param enmType The load/store instruction type. Prefech valid (PRFUM)
2579	* @param iReg The register to load into / store.
2580	* @param iBaseReg The base register to use when addressing. SP is allowed.
2581	* Written back.
2582	* @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2583	*/
2584	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2585	uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2586	{
2587	Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2588	/* 10987654321098765432109876543210 */
2589	return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
2590	enmType, iReg, iBaseReg, i9ImmDisp);
2591	}
2592
2593	/**
2594	* A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
2595	*
2596	* @returns The encoded instruction.
2597	* @param enmType The load/store instruction type. Prefech not valid,
2598	* nor any SIMD&FP variants.
2599	* @param iReg The register to load into / store.
2600	* @param iBaseReg The base register to use when addressing. SP is allowed.
2601	* @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2602	*/
2603	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
2604	uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2605	{
2606	Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
2607	Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
2608	/* 3 2 1 0 */
2609	/* 10987654321098765432109876543210 */
2610	return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
2611	enmType, iReg, iBaseReg, i9ImmDisp);
2612	}
2613
2614
2615	/**
2616	* A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
2617	*
2618	* @returns The encoded instruction.
2619	* @param enmType The load/store instruction type. Prefech not valid,
2620	* nor any SIMD&FP variants.
2621	* @param iReg The register to load into / store.
2622	* @param iBaseReg The base register to use when addressing. SP is allowed.
2623	* @param u12ImmDisp Addressing displacement, scaled by size.
2624	*/
2625	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
2626	uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
2627	{
2628	Assert(u12ImmDisp < 4096U);
2629	Assert(iReg < 32); /* 3 2 1 0 */
2630	Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2631	return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
2632	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2633	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2634	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2635	\| (u12ImmDisp << 10)
2636	\| (iBaseReg << 5)
2637	\| iReg;
2638	}
2639
2640	typedef enum
2641	{
2642	kArmv8A64InstrLdStExtend_Uxtw = 2, /*< Zero-extend (32-bit) word. /
2643	kArmv8A64InstrLdStExtend_Lsl = 3, /*< Shift left (64-bit). /
2644	kArmv8A64InstrLdStExtend_Sxtw = 6, /*< Sign-extend (32-bit) word. /
2645	kArmv8A64InstrLdStExtend_Sxtx = 7 /*< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). /
2646	} ARMV8A64INSTRLDSTEXTEND;
2647
2648	/**
2649	* A64: Encodes load/store w/ index register.
2650	*
2651	* @returns The encoded instruction.
2652	* @param enmType The load/store instruction type.
2653	* @param iReg The register to load into / store.
2654	* @param iBaseReg The base register to use when addressing. SP is allowed.
2655	* @param iRegIndex The index register.
2656	* @param enmExtend The extending to apply to @a iRegIndex.
2657	* @param fShifted Whether to shift the index. The shift amount corresponds
2658	* to the access size (thus irrelevant for byte accesses).
2659	*/
2660	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
2661	uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
2662	ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
2663	bool fShifted = false)
2664	{
2665	Assert(iRegIndex < 32);
2666	Assert(iReg < 32); /* 3 2 1 0 */
2667	Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2668	return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
2669	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2670	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2671	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2672	\| (iRegIndex << 16)
2673	\| ((uint32_t)enmExtend << 13)
2674	\| ((uint32_t)fShifted << 12)
2675	\| (iBaseReg << 5)
2676	\| iReg;
2677	}
2678
2679	typedef enum /* VR Opc */
2680	{ /* \ \| */
2681	kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
2682	kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
2683	kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
2684	kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
2685
2686	kArmv8A64InstrLdrLitteral_Word = 0x00, /*< word = 32-bit /
2687	kArmv8A64InstrLdrLitteral_Dword = 0x01, /*< dword = 64-bit /
2688	kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /*< Loads word, signextending it to 64-bit /
2689	kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /*< prfm /
2690
2691	kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /*< word = 32-bit /
2692	kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /*< dword = 64-bit /
2693	kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
2694	} ARMV8A64INSTRLDRLITTERAL;
2695
2696
2697	/**
2698	* A64: Encodes load w/ a PC relative 19-bit signed immediate.
2699	*
2700	* @returns The encoded instruction.
2701	* @param enmType The load instruction type.
2702	* @param iReg The register to load into.
2703	* @param i19Imm The signed immediate value, multiplied by 4 regardless
2704	* of access size.
2705	*/
2706	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
2707	{
2708	Assert(i19Imm >= -262144 && i19Imm < 262144);
2709	Assert(iReg < 32); /* 3 2 1 0 */
2710	/* 10987654321098765432109876543210 */
2711	return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
2712	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
2713	\| (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
2714	\| (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
2715	\| iReg;
2716	}
2717
2718
2719	typedef enum
2720	{
2721	kArmv8A64InstrMovWide_Not = 0, /*< MOVN - reg = ~(imm16 << hw16; */
2722	kArmv8A64InstrMovWide_Zero = 2, /*< MOVZ - reg = imm16 << hw16; */
2723	kArmv8A64InstrMovWide_Keep = 3 /*< MOVK - keep the other halfwords. /
2724	} ARMV8A64INSTRMOVWIDE;
2725
2726	/**
2727	* A64: Encode a move wide immediate instruction.
2728	*
2729	* @returns The encoded instruction.
2730	* @param enmType The load instruction type.
2731	* @param iRegDst The register to mov the immediate into.
2732	* @param uImm16 The immediate value.
2733	* @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
2734	* half-words to target:
2735	* - 0 for bits 15:00,
2736	* - 1 for bits 31:16,
2737	* - 2 for bits 47:32 (f64Bit=true only),
2738	* - 3 for bits 63:48 (f64Bit=true only).
2739	* @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
2740	*/
2741	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
2742	uint32_t iHalfWord = 0, bool f64Bit = true)
2743	{
2744	Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
2745	return ((uint32_t)f64Bit << 31)
2746	\| ((uint32_t)enmType << 29)
2747	\| UINT32_C(0x12800000)
2748	\| (iHalfWord << 21)
2749	\| (uImm16 << 5)
2750	\| iRegDst;
2751	}
2752
2753	/** A64: Encodes a MOVN instruction.
2754	* @see Armv8A64MkInstrMovWide for parameter details. */
2755	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2756	{
2757	return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
2758	}
2759
2760	/** A64: Encodes a MOVZ instruction.
2761	* @see Armv8A64MkInstrMovWide for parameter details. */
2762	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2763	{
2764	return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
2765	}
2766
2767	/** A64: Encodes a MOVK instruction.
2768	* @see Armv8A64MkInstrMovWide for parameter details. */
2769	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2770	{
2771	return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
2772	}
2773
2774
2775	typedef enum
2776	{
2777	kArmv8A64InstrShift_Lsl = 0,
2778	kArmv8A64InstrShift_Lsr,
2779	kArmv8A64InstrShift_Asr,
2780	kArmv8A64InstrShift_Ror
2781	} ARMV8A64INSTRSHIFT;
2782
2783
2784	/**
2785	* A64: Encodes a logical instruction with a shifted 2nd register operand.
2786	*
2787	* @returns The encoded instruction.
2788	* @param u2Opc The logical operation to perform.
2789	* @param fNot Whether to complement the 2nd operand.
2790	* @param iRegResult The output register.
2791	* @param iReg1 The 1st register operand.
2792	* @param iReg2Shifted The 2nd register operand, to which the optional
2793	* shifting is applied.
2794	* @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
2795	* GPRs.
2796	* @param offShift6 The shift amount (default: none).
2797	* @param enmShift The shift operation (default: LSL).
2798	*/
2799	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
2800	uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
2801	bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
2802	{
2803	Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
2804	Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
2805	return ((uint32_t)f64Bit << 31)
2806	\| (u2Opc << 29)
2807	\| UINT32_C(0x0a000000)
2808	\| ((uint32_t)enmShift << 22)
2809	\| ((uint32_t)fNot << 21)
2810	\| (iReg2Shifted << 16)
2811	\| (offShift6 << 10)
2812	\| (iReg1 << 5)
2813	\| iRegResult;
2814	}
2815
2816
2817	/** A64: Encodes an AND instruction.
2818	* @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2819	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2820	uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2821	{
2822	return Armv8A64MkInstrLogicalShiftedReg(0, false /fNot/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2823	}
2824
2825
2826	/** A64: Encodes an BIC instruction.
2827	* @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2828	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2829	uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2830	{
2831	return Armv8A64MkInstrLogicalShiftedReg(0, true /fNot/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2832	}
2833
2834
2835	/** A64: Encodes an ORR instruction.
2836	* @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2837	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2838	uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2839	{
2840	return Armv8A64MkInstrLogicalShiftedReg(1, false /fNot/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2841	}
2842
2843
2844	/** A64: Encodes an MOV instruction.
2845	* This is an alias for "orr dst, xzr, src". */
2846	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
2847	{
2848	return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
2849	}
2850
2851
2852	/** A64: Encodes an ORN instruction.
2853	* @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2854	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2855	uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2856	{
2857	return Armv8A64MkInstrLogicalShiftedReg(1, true /fNot/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2858	}
2859
2860
2861	/** A64: Encodes an EOR instruction.
2862	* @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2863	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2864	uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2865	{
2866	return Armv8A64MkInstrLogicalShiftedReg(2, false /fNot/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2867	}
2868
2869
2870	/** A64: Encodes an EON instruction.
2871	* @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2872	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2873	uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2874	{
2875	return Armv8A64MkInstrLogicalShiftedReg(2, true /fNot/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2876	}
2877
2878
2879	/** A64: Encodes an ANDS instruction.
2880	* @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2881	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2882	uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2883	{
2884	return Armv8A64MkInstrLogicalShiftedReg(3, false /fNot/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2885	}
2886
2887
2888	/** A64: Encodes an BICS instruction.
2889	* @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2890	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2891	uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2892	{
2893	return Armv8A64MkInstrLogicalShiftedReg(3, true /fNot/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2894	}
2895
2896
2897
2898	/*
2899	* Data processing instructions with two source register operands.
2900	*/
2901
2902
2903	/** A64: Encodes an SUBP instruction. */
2904	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
2905	{
2906	Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
2907	return UINT32_C(0x80000000)
2908	\| UINT32_C(0x1ac00000)
2909	\| (UINT32_C(0) << 10)
2910	\| (iRegSubtrahend << 16)
2911	\| (iRegMinuend << 5)
2912	\| iRegResult;
2913	}
2914
2915
2916	/** A64: Encodes an SUBPS instruction. */
2917	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
2918	{
2919	Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
2920	return UINT32_C(0x80000000)
2921	\| UINT32_C(0x20000000)
2922	\| UINT32_C(0x1ac00000)
2923	\| (UINT32_C(0) << 10)
2924	\| (iRegSubtrahend << 16)
2925	\| (iRegMinuend << 5)
2926	\| iRegResult;
2927	}
2928
2929
2930	/** A64: Encodes an UDIV instruction. */
2931	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
2932	{
2933	Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
2934	return ((uint32_t)f64Bit << 31)
2935	\| UINT32_C(0x1ac00000)
2936	\| (UINT32_C(2) << 10)
2937	\| (iRegDivisor << 16)
2938	\| (iRegDividend << 5)
2939	\| iRegResult;
2940	}
2941
2942
2943	/** A64: Encodes an SDIV instruction. */
2944	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
2945	{
2946	Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
2947	return ((uint32_t)f64Bit << 31)
2948	\| UINT32_C(0x1ac00000)
2949	\| (UINT32_C(3) << 10)
2950	\| (iRegDivisor << 16)
2951	\| (iRegDividend << 5)
2952	\| iRegResult;
2953	}
2954
2955
2956	/** A64: Encodes an IRG instruction. */
2957	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
2958	{
2959	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
2960	return UINT32_C(0x80000000)
2961	\| UINT32_C(0x1ac00000)
2962	\| (UINT32_C(4) << 10)
2963	\| (iRegSrc2 << 16)
2964	\| (iRegSrc1 << 5)
2965	\| iRegResult;
2966	}
2967
2968
2969	/** A64: Encodes a GMI instruction. */
2970	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
2971	{
2972	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
2973	return UINT32_C(0x80000000)
2974	\| UINT32_C(0x1ac00000)
2975	\| (UINT32_C(5) << 10)
2976	\| (iRegSrc2 << 16)
2977	\| (iRegSrc1 << 5)
2978	\| iRegResult;
2979	}
2980
2981
2982	/** A64: Encodes an LSLV instruction. */
2983	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2984	{
2985	Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2986	return ((uint32_t)f64Bit << 31)
2987	\| UINT32_C(0x1ac00000)
2988	\| (UINT32_C(8) << 10)
2989	\| (iRegCount << 16)
2990	\| (iRegSrc << 5)
2991	\| iRegResult;
2992	}
2993
2994
2995	/** A64: Encodes an LSRV instruction. */
2996	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2997	{
2998	Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2999	return ((uint32_t)f64Bit << 31)
3000	\| UINT32_C(0x1ac00000)
3001	\| (UINT32_C(9) << 10)
3002	\| (iRegCount << 16)
3003	\| (iRegSrc << 5)
3004	\| iRegResult;
3005	}
3006
3007
3008	/** A64: Encodes an ASRV instruction. */
3009	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3010	{
3011	Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3012	return ((uint32_t)f64Bit << 31)
3013	\| UINT32_C(0x1ac00000)
3014	\| (UINT32_C(10) << 10)
3015	\| (iRegCount << 16)
3016	\| (iRegSrc << 5)
3017	\| iRegResult;
3018	}
3019
3020
3021	/** A64: Encodes a RORV instruction. */
3022	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3023	{
3024	Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3025	return ((uint32_t)f64Bit << 31)
3026	\| UINT32_C(0x1ac00000)
3027	\| (UINT32_C(11) << 10)
3028	\| (iRegCount << 16)
3029	\| (iRegSrc << 5)
3030	\| iRegResult;
3031	}
3032
3033
3034	/** A64: Encodes a PACGA instruction. */
3035	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3036	{
3037	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3038	return UINT32_C(0x80000000)
3039	\| UINT32_C(0x1ac00000)
3040	\| (UINT32_C(12) << 10)
3041	\| (iRegSrc2 << 16)
3042	\| (iRegSrc1 << 5)
3043	\| iRegResult;
3044	}
3045
3046
3047	/** A64: Encodes a CRC32* instruction. */
3048	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3049	{
3050	Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3051	return ((uint32_t)(uSize == 3) << 31)
3052	\| UINT32_C(0x1ac00000)
3053	\| (UINT32_C(16) << 10)
3054	\| (uSize << 10)
3055	\| (iRegValue << 16)
3056	\| (iRegCrc << 5)
3057	\| iRegResult;
3058	}
3059
3060
3061	/** A64: Encodes a CRC32B instruction. */
3062	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3063	{
3064	return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
3065	}
3066
3067
3068	/** A64: Encodes a CRC32H instruction. */
3069	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3070	{
3071	return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
3072	}
3073
3074
3075	/** A64: Encodes a CRC32W instruction. */
3076	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3077	{
3078	return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
3079	}
3080
3081
3082	/** A64: Encodes a CRC32X instruction. */
3083	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3084	{
3085	return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
3086	}
3087
3088
3089	/** A64: Encodes a CRC32C* instruction. */
3090	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3091	{
3092	Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3093	return ((uint32_t)(uSize == 3) << 31)
3094	\| UINT32_C(0x1ac00000)
3095	\| (UINT32_C(20) << 10)
3096	\| (uSize << 10)
3097	\| (iRegValue << 16)
3098	\| (iRegCrc << 5)
3099	\| iRegResult;
3100	}
3101
3102
3103	/** A64: Encodes a CRC32B instruction. */
3104	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3105	{
3106	return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
3107	}
3108
3109
3110	/** A64: Encodes a CRC32CH instruction. */
3111	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3112	{
3113	return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
3114	}
3115
3116
3117	/** A64: Encodes a CRC32CW instruction. */
3118	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3119	{
3120	return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
3121	}
3122
3123
3124	/** A64: Encodes a CRC32CX instruction. */
3125	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3126	{
3127	return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
3128	}
3129
3130
3131	/** A64: Encodes an SMAX instruction. */
3132	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3133	{
3134	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3135	return ((uint32_t)f64Bit << 31)
3136	\| UINT32_C(0x1ac00000)
3137	\| (UINT32_C(24) << 10)
3138	\| (iRegSrc2 << 16)
3139	\| (iRegSrc1 << 5)
3140	\| iRegResult;
3141	}
3142
3143
3144	/** A64: Encodes an UMAX instruction. */
3145	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3146	{
3147	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3148	return ((uint32_t)f64Bit << 31)
3149	\| UINT32_C(0x1ac00000)
3150	\| (UINT32_C(25) << 10)
3151	\| (iRegSrc2 << 16)
3152	\| (iRegSrc1 << 5)
3153	\| iRegResult;
3154	}
3155
3156
3157	/** A64: Encodes an SMIN instruction. */
3158	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3159	{
3160	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3161	return ((uint32_t)f64Bit << 31)
3162	\| UINT32_C(0x1ac00000)
3163	\| (UINT32_C(26) << 10)
3164	\| (iRegSrc2 << 16)
3165	\| (iRegSrc1 << 5)
3166	\| iRegResult;
3167	}
3168
3169
3170	/** A64: Encodes an UMIN instruction. */
3171	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3172	{
3173	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3174	return ((uint32_t)f64Bit << 31)
3175	\| UINT32_C(0x1ac00000)
3176	\| (UINT32_C(27) << 10)
3177	\| (iRegSrc2 << 16)
3178	\| (iRegSrc1 << 5)
3179	\| iRegResult;
3180	}
3181
3182
3183	# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
3184
3185	/**
3186	* Converts immS and immR values (to logical instructions) to a 32-bit mask.
3187	*
3188	* @returns The decoded mask.
3189	* @param uImm6SizeLen The immS value from the instruction. (No N part
3190	* here, as that must be zero for instructions
3191	* operating on 32-bit wide registers.)
3192	* @param uImm6Rotations The immR value from the instruction.
3193	*/
3194	DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3195	{
3196	Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
3197
3198	/* Determine the element size. */
3199	unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
3200	Assert(cBitsElementLog2 + 1U != 0U);
3201
3202	unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3203	Assert(uImm6Rotations < cBitsElement);
3204
3205	/* Extract the number of bits set to 1: */
3206	unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
3207	Assert(cBitsSetTo1 < cBitsElement);
3208	uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
3209
3210	/* Produce the unrotated pattern. */
3211	static const uint32_t s_auReplicate[]
3212	= { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3213	uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3214
3215	/* Rotate it and return. */
3216	return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
3217	}
3218
3219
3220	/**
3221	* Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
3222	*
3223	* @returns The decoded mask.
3224	* @param uImm7SizeLen The N:immS value from the instruction.
3225	* @param uImm6Rotations The immR value from the instruction.
3226	*/
3227	DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
3228	{
3229	Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
3230
3231	/* Determine the element size. */
3232	unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
3233	Assert(cBitsElementLog2 + 1U != 0U);
3234
3235	unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3236	Assert(uImm6Rotations < cBitsElement);
3237
3238	/* Extract the number of bits set to 1: */
3239	unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
3240	Assert(cBitsSetTo1 < cBitsElement);
3241	uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
3242
3243	/* Produce the unrotated pattern. */
3244	static const uint64_t s_auReplicate[]
3245	= { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3246	uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3247
3248	/* Rotate it and return. */
3249	return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
3250	}
3251
3252
3253	/**
3254	* Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
3255	* the immS value.
3256	*/
3257	DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3258	{
3259	return Armv8A64ConvertImmRImmS2Mask64((uN << 6) \| uImm6SizeLen, uImm6Rotations);
3260	}
3261
3262
3263	/**
3264	* Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3265	* 32-bit bitmask to a set of immediates for those instructions.
3266	*
3267	* @returns true if successful, false if not.
3268	* @param fMask The mask value to convert.
3269	* @param puImm6SizeLen Where to return the immS part (N is always zero for
3270	* 32-bit wide masks).
3271	* @param puImm6Rotations Where to return the immR.
3272	*/
3273	DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t puImm6SizeLen, uint32_t puImm6Rotations)
3274	{
3275	/* Fend off 0 and UINT32_MAX as these cannot be represented. */
3276	if ((uint32_t)(fMask + 1U) <= 1)
3277	return false;
3278
3279	/* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3280	unsigned const cRor = ASMCountTrailingZerosU32(fMask);
3281	unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
3282	if (cRor)
3283	fMask = ASMRotateRightU32(fMask, cRor);
3284	else
3285	fMask = ASMRotateLeftU32(fMask, cRol);
3286	Assert(fMask & RT_BIT_32(0));
3287	Assert(!(fMask & RT_BIT_32(31)));
3288
3289	/* Count the trailing ones and leading zeros. */
3290	unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
3291	unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
3292
3293	/* The potential element length is then the sum of the two above. */
3294	unsigned const cBitsElement = cOnes + cZeros;
3295	if (!RT_IS_POWER_OF_TWO(cBitsElement) \|\| cBitsElement < 2)
3296	return false;
3297
3298	/* Special case: 32 bits element size. Since we're done here. */
3299	if (cBitsElement == 32)
3300	*puImm6SizeLen = cOnes - 1;
3301	else
3302	{
3303	/* Extract the element bits and check that these are replicated in the whole pattern. */
3304	uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
3305	unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
3306
3307	static const uint32_t s_auReplicate[]
3308	= { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3309	if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3310	*puImm6SizeLen = (cOnes - 1) \| ((0x3e << cBitsElementLog2) & 0x3f);
3311	else
3312	return false;
3313	}
3314	*puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3315
3316	return true;
3317	}
3318
3319
3320	/**
3321	* Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3322	* 64-bit bitmask to a set of immediates for those instructions.
3323	*
3324	* @returns true if successful, false if not.
3325	* @param fMask The mask value to convert.
3326	* @param puImm7SizeLen Where to return the N:immS part.
3327	* @param puImm6Rotations Where to return the immR.
3328	*/
3329	DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t puImm7SizeLen, uint32_t puImm6Rotations)
3330	{
3331	/* Fend off 0 and UINT64_MAX as these cannot be represented. */
3332	if ((uint64_t)(fMask + 1U) <= 1)
3333	return false;
3334
3335	/* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3336	unsigned const cRor = ASMCountTrailingZerosU64(fMask);
3337	unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
3338	if (cRor)
3339	fMask = ASMRotateRightU64(fMask, cRor);
3340	else
3341	fMask = ASMRotateLeftU64(fMask, cRol);
3342	Assert(fMask & RT_BIT_64(0));
3343	Assert(!(fMask & RT_BIT_64(63)));
3344
3345	/* Count the trailing ones and leading zeros. */
3346	unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
3347	unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
3348
3349	/* The potential element length is then the sum of the two above. */
3350	unsigned const cBitsElement = cOnes + cZeros;
3351	if (!RT_IS_POWER_OF_TWO(cBitsElement) \|\| cBitsElement < 2)
3352	return false;
3353
3354	/* Special case: 64 bits element size. Since we're done here. */
3355	if (cBitsElement == 64)
3356	puImm7SizeLen = (cOnes - 1) \| 0x40 /N*/;
3357	else
3358	{
3359	/* Extract the element bits and check that these are replicated in the whole pattern. */
3360	uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
3361	unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
3362
3363	static const uint64_t s_auReplicate[]
3364	= { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3365	if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3366	*puImm7SizeLen = (cOnes - 1) \| ((0x3e << cBitsElementLog2) & 0x3f);
3367	else
3368	return false;
3369	}
3370	*puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3371
3372	return true;
3373	}
3374
3375	# endif /* IPRT_INCLUDED_asm_h */
3376
3377	/**
3378	* A64: Encodes a logical instruction with an complicated immediate mask.
3379	*
3380	* The @a uImm7SizeLen parameter specifies two things:
3381	* 1. the element size and
3382	* 2. the number of bits set to 1 in the pattern.
3383	*
3384	* The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
3385	* top) and using the position of the first bit set as a power of two.
3386	*
3387	* \| N \| 5 \| 4 \| 3 \| 2 \| 1 \| 0 \| element size \|
3388	* \|---\|---\|---\|---\|---\|---\|---\|--------------\|
3389	* \| 0 \| 1 \| 1 \| 1 \| 1 \| 0 \| x \| 2 bits \|
3390	* \| 0 \| 1 \| 1 \| 1 \| 0 \| x \| x \| 4 bits \|
3391	* \| 0 \| 1 \| 1 \| 0 \| x \| x \| x \| 8 bits \|
3392	* \| 0 \| 1 \| 0 \| x \| x \| x \| x \| 16 bits \|
3393	* \| 0 \| 0 \| x \| x \| x \| x \| x \| 32 bits \|
3394	* \| 1 \| x \| x \| x \| x \| x \| x \| 64 bits \|
3395	*
3396	* The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
3397	* there is always one zero bit in the pattern).
3398	*
3399	* The @a uImm6Rotations parameter specifies how many bits to the right,
3400	* the element pattern is rotated. The rotation count must be less than the
3401	* element bit count (size).
3402	*
3403	* @returns The encoded instruction.
3404	* @param u2Opc The logical operation to perform.
3405	* @param iRegResult The output register.
3406	* @param iRegSrc The 1st register operand.
3407	* @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
3408	* field at the top of the 6-bit 'imms' field.
3409	*
3410	* @param uImm6Rotations The rotation count.
3411	* @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3412	* @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3413	* https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3414	*/
3415	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3416	uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
3417	{
3418	Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x3f)));
3419	Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
3420	return ((uint32_t)f64Bit << 31)
3421	\| (u2Opc << 29)
3422	\| UINT32_C(0x12000000)
3423	\| ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
3424	\| (uImm6Rotations << 16)
3425	\| ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
3426	\| (iRegSrc << 5)
3427	\| iRegResult;
3428	}
3429
3430
3431	/** A64: Encodes an AND instruction w/ complicated immediate mask.
3432	* @see Armv8A64MkInstrLogicalImm for parameter details. */
3433	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
3434	uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3435	{
3436	return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3437	}
3438
3439
3440	/** A64: Encodes an ORR instruction w/ complicated immediate mask.
3441	* @see Armv8A64MkInstrLogicalImm for parameter details. */
3442	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
3443	uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3444	{
3445	return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3446	}
3447
3448
3449	/** A64: Encodes an EOR instruction w/ complicated immediate mask.
3450	* @see Armv8A64MkInstrLogicalImm for parameter details. */
3451	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
3452	uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3453	{
3454	return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3455	}
3456
3457
3458	/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
3459	* @see Armv8A64MkInstrLogicalImm for parameter details. */
3460	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
3461	uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3462	{
3463	return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3464	}
3465
3466
3467	/** A64: Encodes an TST instruction w/ complicated immediate mask.
3468	* @see Armv8A64MkInstrLogicalImm for parameter details. */
3469	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
3470	uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3471	{
3472	return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3473	}
3474
3475
3476	/**
3477	* A64: Encodes a bitfield instruction.
3478	*
3479	* @returns The encoded instruction.
3480	* @param u2Opc The bitfield operation to perform.
3481	* @param iRegResult The output register.
3482	* @param iRegSrc The 1st register operand.
3483	* @param cImm6Ror The right rotation count.
3484	* @param uImm6S The leftmost bit to be moved.
3485	* @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3486	* @param uN1 This must match @a f64Bit for all instructions
3487	* currently specified.
3488	* @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3489	* https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3490	*/
3491	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3492	uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
3493	{
3494	Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
3495	Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
3496	return ((uint32_t)f64Bit << 31)
3497	\| (u2Opc << 29)
3498	\| UINT32_C(0x13000000)
3499	\| (uN1 << 22)
3500	\| (cImm6Ror << 16)
3501	\| (uImm6S << 10)
3502	\| (iRegSrc << 5)
3503	\| iRegResult;
3504	}
3505
3506
3507	/** A64: Encodes a SBFM instruction.
3508	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3509	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3510	bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3511	{
3512	return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3513	}
3514
3515
3516	/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
3517	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3518	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3519	{
3520	return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
3521	}
3522
3523
3524	/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
3525	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3526	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3527	{
3528	return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
3529	}
3530
3531
3532	/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
3533	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3534	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
3535	{
3536	return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /f64Bit/);
3537	}
3538
3539
3540	/** A64: Encodes an ASR instruction w/ immediate shift value.
3541	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3542	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3543	{
3544	uint32_t const cWidth = f64Bit ? 63 : 31;
3545	Assert(cShift > 0); Assert(cShift <= cWidth);
3546	return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /uImm6S/, f64Bit, f64Bit);
3547	}
3548
3549
3550	/** A64: Encodes a BFM instruction.
3551	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3552	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3553	bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3554	{
3555	return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3556	}
3557
3558
3559	/** A64: Encodes a BFI instruction (insert).
3560	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3561	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
3562	uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3563	{
3564	Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3565	return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
3566	cBitsWidth - 1, f64Bit);
3567	}
3568
3569
3570	/** A64: Encodes a BFXIL instruction (insert low).
3571	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3572	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfxil(uint32_t iRegResult, uint32_t iRegSrc,
3573	uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3574	{
3575	Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3576	Assert(offFirstBit + cBitsWidth <= (f64Bit ? 64U : 32U));
3577	return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3578	}
3579
3580
3581	/** A64: Encodes an UBFM instruction.
3582	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3583	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3584	bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3585	{
3586	return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3587	}
3588
3589
3590	/** A64: Encodes an UBFX instruction (zero extending extract).
3591	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3592	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
3593	uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3594	{
3595	return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3596	}
3597
3598
3599	/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
3600	* shifted into destination).
3601	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3602	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
3603	uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
3604	{
3605	uint32_t fMask = f64Bit ? 0x3f : 0x1f;
3606	return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
3607	}
3608
3609
3610	/** A64: Encodes an LSL instruction w/ immediate shift value.
3611	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3612	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3613	{
3614	uint32_t const cWidth = f64Bit ? 63 : 31;
3615	Assert(cShift > 0); Assert(cShift <= cWidth);
3616	return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
3617	cWidth - cShift /uImm6S/, f64Bit, f64Bit);
3618	}
3619
3620
3621	/** A64: Encodes an LSR instruction w/ immediate shift value.
3622	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3623	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3624	{
3625	uint32_t const cWidth = f64Bit ? 63 : 31;
3626	Assert(cShift > 0); Assert(cShift <= cWidth);
3627	return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /uImm6S/, f64Bit, f64Bit);
3628	}
3629
3630
3631	/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
3632	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3633	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3634	{
3635	return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
3636	}
3637
3638
3639	/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
3640	* @see Armv8A64MkInstrBitfieldImm for parameter details. */
3641	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3642	{
3643	return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
3644	}
3645
3646
3647	/**
3648	* A64: Encodes an EXTR instruction with an immediate.
3649	*
3650	* @returns The encoded instruction.
3651	* @param iRegResult The register to store the result in. ZR is valid.
3652	* @param iRegLow The register holding the least significant bits in the
3653	* extraction. ZR is valid.
3654	* @param iRegHigh The register holding the most significant bits in the
3655	* extraction. ZR is valid.
3656	* @param uLsb The bit number of the least significant bit, or where in
3657	* @a iRegLow to start the
3658	* extraction.
3659	* @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3660	*/
3661	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
3662	bool f64Bit = true)
3663	{
3664	Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
3665	return ((uint32_t)f64Bit << 31)
3666	\| UINT32_C(0x13800000)
3667	\| ((uint32_t)f64Bit << 22) /N/
3668	\| (iRegHigh << 16)
3669	\| (uLsb << 10)
3670	\| (iRegLow << 5)
3671	\| iRegResult;
3672	}
3673
3674
3675	/** A64: Rotates the value of a register (alias for EXTR). */
3676	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3677	{
3678	return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
3679	}
3680
3681
3682	/**
3683	* A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
3684	*
3685	* @returns The encoded instruction.
3686	* @param fSub true for sub and subs, false for add and
3687	* adds.
3688	* @param iRegResult The register to store the result in.
3689	* SP is valid when @a fSetFlags = false,
3690	* and ZR is valid otherwise.
3691	* @param iRegSrc The register containing the augend (@a fSub
3692	* = false) or minuend (@a fSub = true). SP is
3693	* a valid registers for all variations.
3694	* @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
3695	* (@a fSub = true).
3696	* @param f64Bit true for 64-bit GRPs (default), false for
3697	* 32-bit GPRs.
3698	* @param fSetFlags Whether to set flags (adds / subs) or not
3699	* (add / sub - default).
3700	* @param fShift12 Whether to shift uImm12AddendSubtrahend 12
3701	* bits to the left, or not (default).
3702	*/
3703	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
3704	uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
3705	bool fSetFlags = false, bool fShift12 = false)
3706	{
3707	Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
3708	return ((uint32_t)f64Bit << 31)
3709	\| ((uint32_t)fSub << 30)
3710	\| ((uint32_t)fSetFlags << 29)
3711	\| UINT32_C(0x11000000)
3712	\| ((uint32_t)fShift12 << 22)
3713	\| (uImm12AddendSubtrahend << 10)
3714	\| (iRegSrc << 5)
3715	\| iRegResult;
3716	}
3717
3718
3719	/** Alias for sub zxr, reg, \#uimm12. */
3720	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
3721	bool f64Bit = true, bool fShift12 = false)
3722	{
3723	return Armv8A64MkInstrAddSubUImm12(true /fSub/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
3724	f64Bit, true /fSetFlags/, fShift12);
3725	}
3726
3727
3728	/** ADD dst, src, \#uimm12 */
3729	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
3730	bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3731	{
3732	return Armv8A64MkInstrAddSubUImm12(false /fSub/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
3733	}
3734
3735
3736	/** SUB dst, src, \#uimm12 */
3737	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
3738	bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3739	{
3740	return Armv8A64MkInstrAddSubUImm12(true /fSub/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
3741	}
3742
3743
3744	/**
3745	* A64: Encodes either add, adds, sub or subs with shifted register.
3746	*
3747	* @returns The encoded instruction.
3748	* @param fSub true for sub and subs, false for add and
3749	* adds.
3750	* @param iRegResult The register to store the result in.
3751	* SP is NOT valid, but ZR is.
3752	* @param iRegSrc1 The register containing the augend (@a fSub
3753	* = false) or minuend (@a fSub = true).
3754	* SP is NOT valid, but ZR is.
3755	* @param iRegSrc2 The register containing the addened (@a fSub
3756	* = false) or subtrahend (@a fSub = true).
3757	* SP is NOT valid, but ZR is.
3758	* @param f64Bit true for 64-bit GRPs (default), false for
3759	* 32-bit GPRs.
3760	* @param fSetFlags Whether to set flags (adds / subs) or not
3761	* (add / sub - default).
3762	* @param cShift The shift count to apply to @a iRegSrc2.
3763	* @param enmShift The shift type to apply to the @a iRegSrc2
3764	* register. kArmv8A64InstrShift_Ror is
3765	* reserved.
3766	*/
3767	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3768	bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3769	ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3770	{
3771	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3772	Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
3773
3774	return ((uint32_t)f64Bit << 31)
3775	\| ((uint32_t)fSub << 30)
3776	\| ((uint32_t)fSetFlags << 29)
3777	\| UINT32_C(0x0b000000)
3778	\| ((uint32_t)enmShift << 22)
3779	\| (iRegSrc2 << 16)
3780	\| (cShift << 10)
3781	\| (iRegSrc1 << 5)
3782	\| iRegResult;
3783	}
3784
3785
3786	/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
3787	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
3788	ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3789	{
3790	return Armv8A64MkInstrAddSubReg(true /fSub/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
3791	f64Bit, true /fSetFlags/, cShift, enmShift);
3792	}
3793
3794
3795	/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3796	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3797	bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3798	ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3799	{
3800	return Armv8A64MkInstrAddSubReg(false /fSub/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3801	}
3802
3803
3804	/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3805	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3806	bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3807	ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3808	{
3809	return Armv8A64MkInstrAddSubReg(true /fSub/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3810	}
3811
3812
3813	/** NEG dst */
3814	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
3815	{
3816	return Armv8A64MkInstrAddSubReg(true /fSub/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
3817	}
3818
3819
3820	/** Extension option for 'extended register' instructions. */
3821	typedef enum ARMV8A64INSTREXTEND
3822	{
3823	kArmv8A64InstrExtend_UxtB = 0,
3824	kArmv8A64InstrExtend_UxtH,
3825	kArmv8A64InstrExtend_UxtW,
3826	kArmv8A64InstrExtend_UxtX,
3827	kArmv8A64InstrExtend_SxtB,
3828	kArmv8A64InstrExtend_SxtH,
3829	kArmv8A64InstrExtend_SxtW,
3830	kArmv8A64InstrExtend_SxtX,
3831	/** The default is either UXTW or UXTX depending on whether the instruction
3832	* is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
3833	* to the f64Bit value. */
3834	kArmv8A64InstrExtend_Default
3835	} ARMV8A64INSTREXTEND;
3836
3837
3838	/**
3839	* A64: Encodes either add, adds, sub or subs with extended register encoding.
3840	*
3841	* @returns The encoded instruction.
3842	* @param fSub true for sub and subs, false for add and
3843	* adds.
3844	* @param iRegResult The register to store the result in.
3845	* SP is NOT valid, but ZR is.
3846	* @param iRegSrc1 The register containing the augend (@a fSub
3847	* = false) or minuend (@a fSub = true).
3848	* SP is valid, but ZR is NOT.
3849	* @param iRegSrc2 The register containing the addened (@a fSub
3850	* = false) or subtrahend (@a fSub = true).
3851	* SP is NOT valid, but ZR is.
3852	* @param f64Bit true for 64-bit GRPs (default), false for
3853	* 32-bit GPRs.
3854	* @param fSetFlags Whether to set flags (adds / subs) or not
3855	* (add / sub - default).
3856	* @param enmExtend The type of extension to apply to @a
3857	* iRegSrc2.
3858	* @param cShift The left shift count to apply to @a iRegSrc2
3859	* after enmExtend processing is done.
3860	* Max shift is 4 for some reason.
3861	*/
3862	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3863	bool f64Bit = true, bool fSetFlags = false,
3864	ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
3865	uint32_t cShift = 0)
3866	{
3867	if (enmExtend == kArmv8A64InstrExtend_Default)
3868	enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
3869	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
3870
3871	return ((uint32_t)f64Bit << 31)
3872	\| ((uint32_t)fSub << 30)
3873	\| ((uint32_t)fSetFlags << 29)
3874	\| UINT32_C(0x0b200000)
3875	\| (iRegSrc2 << 16)
3876	\| ((uint32_t)enmExtend << 13)
3877	\| (cShift << 10)
3878	\| (iRegSrc1 << 5)
3879	\| iRegResult;
3880	}
3881
3882
3883	/**
3884	* A64: Encodes either adc, adcs, sbc or sbcs with two source registers.
3885	*
3886	* @returns The encoded instruction.
3887	* @param fSub true for sbc and sbcs, false for adc and
3888	* adcs.
3889	* @param iRegResult The register to store the result in. SP is
3890	* NOT valid, but ZR is.
3891	* @param iRegSrc1 The register containing the augend (@a fSub
3892	* = false) or minuend (@a fSub = true).
3893	* SP is NOT valid, but ZR is.
3894	* @param iRegSrc2 The register containing the addened (@a fSub
3895	* = false) or subtrahend (@a fSub = true).
3896	* SP is NOT valid, but ZR is.
3897	* @param f64Bit true for 64-bit GRPs (default), false for
3898	* 32-bit GPRs.
3899	* @param fSetFlags Whether to set flags (adds / subs) or not
3900	* (add / sub - default).
3901	*/
3902	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcSbc(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3903	bool f64Bit = true, bool fSetFlags = false)
3904	{
3905	Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3906
3907	return ((uint32_t)f64Bit << 31)
3908	\| ((uint32_t)fSub << 30)
3909	\| ((uint32_t)fSetFlags << 29)
3910	\| UINT32_C(0x1a000000)
3911	\| (iRegSrc2 << 16)
3912	\| (iRegSrc1 << 5)
3913	\| iRegResult;
3914	}
3915
3916
3917	/** ADC dst, reg1, reg2 */
3918	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3919	bool f64Bit = true, bool fSetFlags = false)
3920	{
3921	return Armv8A64MkInstrAdcSbc(false /fSub/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
3922	}
3923
3924
3925	/** ADCS dst, reg1, reg2 */
3926	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3927	{
3928	return Armv8A64MkInstrAdcSbc(false /fSub/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /fSetFlags/);
3929	}
3930
3931
3932	/** SBC dst, reg1, reg2 */
3933	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3934	bool f64Bit = true, bool fSetFlags = false)
3935	{
3936	return Armv8A64MkInstrAdcSbc(true /fSub/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
3937	}
3938
3939
3940	/** SBCS dst, reg1, reg2 */
3941	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3942	{
3943	return Armv8A64MkInstrAdcSbc(true /fSub/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /fSetFlags/);
3944	}
3945
3946
3947	/**
3948	* A64: Encodes a B (unconditional branch w/ imm) instruction.
3949	*
3950	* @returns The encoded instruction.
3951	* @param iImm26 Signed number of instruction to jump (i.e. *4).
3952	*/
3953	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
3954	{
3955	Assert(iImm26 >= -67108864 && iImm26 < 67108864);
3956	return UINT32_C(0x14000000) \| ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
3957	}
3958
3959
3960	/**
3961	* A64: Encodes a BL (unconditional call w/ imm) instruction.
3962	*
3963	* @returns The encoded instruction.
3964	* @param iImm26 Signed number of instruction to jump (i.e. *4).
3965	*/
3966	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
3967	{
3968	return Armv8A64MkInstrB(iImm26) \| RT_BIT_32(31);
3969	}
3970
3971
3972	/**
3973	* A64: Encodes a BR (unconditional branch w/ register) instruction.
3974	*
3975	* @returns The encoded instruction.
3976	* @param iReg The register containing the target address.
3977	*/
3978	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
3979	{
3980	Assert(iReg < 32);
3981	return UINT32_C(0xd61f0000) \| (iReg << 5);
3982	}
3983
3984
3985	/**
3986	* A64: Encodes a BLR instruction.
3987	*
3988	* @returns The encoded instruction.
3989	* @param iReg The register containing the target address.
3990	*/
3991	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
3992	{
3993	return Armv8A64MkInstrBr(iReg) \| RT_BIT_32(21);
3994	}
3995
3996
3997	/**
3998	* A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
3999	*
4000	* @returns The encoded instruction.
4001	* @param fJmpIfNotZero false to jump if register is zero, true to jump if
4002	* its not zero.
4003	* @param iImm19 Signed number of instruction to jump (i.e. *4).
4004	* @param iReg The GPR to check for zero / non-zero value.
4005	* @param f64Bit true for 64-bit register, false for 32-bit.
4006	*/
4007	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4008	{
4009	Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
4010	return ((uint32_t)f64Bit << 31)
4011	\| UINT32_C(0x34000000)
4012	\| ((uint32_t)fJmpIfNotZero << 24)
4013	\| (((uint32_t)iImm19 & 0x7ffff) << 5)
4014	\| iReg;
4015	}
4016
4017
4018	/** A64: Encodes the CBZ instructions. */
4019	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4020	{
4021	return Armv8A64MkInstrCbzCbnz(false /fJmpIfNotZero/, iImm19, iReg, f64Bit);
4022	}
4023
4024
4025	/** A64: Encodes the CBNZ instructions. */
4026	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbnz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4027	{
4028	return Armv8A64MkInstrCbzCbnz(true /fJmpIfNotZero/, iImm19, iReg, f64Bit);
4029	}
4030
4031
4032	/**
4033	* A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
4034	*
4035	* @returns The encoded instruction.
4036	* @param fJmpIfNotZero false to jump if register is zero, true to jump if
4037	* its not zero.
4038	* @param iImm14 Signed number of instruction to jump (i.e. *4).
4039	* @param iReg The GPR to check for zero / non-zero value.
4040	* @param iBitNo The bit to test for.
4041	*/
4042	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4043	{
4044	Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
4045	return ((uint32_t)(iBitNo & 0x20) << (31-5))
4046	\| UINT32_C(0x36000000)
4047	\| ((uint32_t)fJmpIfNotZero << 24)
4048	\| ((iBitNo & 0x1f) << 19)
4049	\| (((uint32_t)iImm14 & 0x3fff) << 5)
4050	\| iReg;
4051	}
4052
4053
4054	/**
4055	* A64: Encodes TBZ (conditional branch w/ immediate) instructions.
4056	*
4057	* @returns The encoded instruction.
4058	* @param iImm14 Signed number of instruction to jump (i.e. *4).
4059	* @param iReg The GPR to check for zero / non-zero value.
4060	* @param iBitNo The bit to test for.
4061	*/
4062	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4063	{
4064	return Armv8A64MkInstrTbzTbnz(false /fJmpIfNotZero/, iImm14, iReg, iBitNo);
4065	}
4066
4067
4068	/**
4069	* A64: Encodes TBNZ (conditional branch w/ immediate) instructions.
4070	*
4071	* @returns The encoded instruction.
4072	* @param iImm14 Signed number of instruction to jump (i.e. *4).
4073	* @param iReg The GPR to check for zero / non-zero value.
4074	* @param iBitNo The bit to test for.
4075	*/
4076	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbnz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4077	{
4078	return Armv8A64MkInstrTbzTbnz(true /fJmpIfNotZero/, iImm14, iReg, iBitNo);
4079	}
4080
4081
4082
4083	/** Armv8 Condition codes. */
4084	typedef enum ARMV8INSTRCOND
4085	{
4086	kArmv8InstrCond_Eq = 0, /*< 0 - Equal - Zero set. /
4087	kArmv8InstrCond_Ne, /*< 1 - Not equal - Zero clear. /
4088
4089	kArmv8InstrCond_Cs, /*< 2 - Carry set (also known as 'HS'). /
4090	kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /*< 2 - Unsigned higher or same. /
4091	kArmv8InstrCond_Cc, /*< 3 - Carry clear (also known as 'LO'). /
4092	kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /*< 3 - Unsigned lower. /
4093
4094	kArmv8InstrCond_Mi, /*< 4 - Negative result (minus). /
4095	kArmv8InstrCond_Pl, /*< 5 - Positive or zero result (plus). /
4096
4097	kArmv8InstrCond_Vs, /*< 6 - Overflow set. /
4098	kArmv8InstrCond_Vc, /*< 7 - Overflow clear. /
4099
4100	kArmv8InstrCond_Hi, /*< 8 - Unsigned higher. /
4101	kArmv8InstrCond_Ls, /*< 9 - Unsigned lower or same. /
4102
4103	kArmv8InstrCond_Ge, /*< a - Signed greater or equal. /
4104	kArmv8InstrCond_Lt, /*< b - Signed less than. /
4105
4106	kArmv8InstrCond_Gt, /*< c - Signed greater than. /
4107	kArmv8InstrCond_Le, /*< d - Signed less or equal. /
4108
4109	kArmv8InstrCond_Al, /*< e - Condition is always true. /
4110	kArmv8InstrCond_Al1 /*< f - Condition is always true. /
4111	} ARMV8INSTRCOND;
4112
4113	/**
4114	* A64: Encodes conditional branch instruction w/ immediate target.
4115	*
4116	* @returns The encoded instruction.
4117	* @param enmCond The branch condition.
4118	* @param iImm19 Signed number of instruction to jump (i.e. *4).
4119	*/
4120	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
4121	{
4122	Assert((unsigned)enmCond < 16);
4123	return UINT32_C(0x54000000)
4124	\| (((uint32_t)iImm19 & 0x7ffff) << 5)
4125	\| (uint32_t)enmCond;
4126	}
4127
4128
4129	/**
4130	* A64: Encodes the BRK instruction.
4131	*
4132	* @returns The encoded instruction.
4133	* @param uImm16 Unsigned immediate value.
4134	*/
4135	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
4136	{
4137	Assert(uImm16 < _64K);
4138	return UINT32_C(0xd4200000)
4139	\| (uImm16 << 5);
4140	}
4141
4142	/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
4143	* @{ */
4144	#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
4145	#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
4146	#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
4147	#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
4148	#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
4149	#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
4150	#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
4151	#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
4152
4153	#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
4154	#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
4155	#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
4156	#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
4157	#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
4158	#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
4159	#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
4160	#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
4161	/** @} */
4162
4163	/**
4164	* A64: Encodes CCMP or CCMN with two register operands.
4165	*
4166	* @returns The encoded instruction.
4167	* @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
4168	* @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
4169	* @param fNzcv The N, Z, C & V flags values to load if the condition
4170	* does not match. See RMA64_NZCV_F_XXX.
4171	* @param enmCond The condition guarding the compare.
4172	* @param fCCmp Set for CCMP (default), clear for CCMN.
4173	* @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4174	*/
4175	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4176	ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
4177	{
4178	Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
4179
4180	return ((uint32_t)f64Bit << 31)
4181	\| ((uint32_t)fCCmp << 30)
4182	\| UINT32_C(0x3a400000)
4183	\| (iRegSrc2 << 16)
4184	\| ((uint32_t)enmCond << 12)
4185	\| (iRegSrc1 << 5)
4186	\| fNzcv;
4187	}
4188
4189	/** CCMP w/ reg. */
4190	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4191	ARMV8INSTRCOND enmCond, bool f64Bit = true)
4192	{
4193	return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /fCCmp/, f64Bit);
4194	}
4195
4196
4197	/** CCMN w/ reg. */
4198	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4199	ARMV8INSTRCOND enmCond, bool f64Bit = true)
4200	{
4201	return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /fCCmp/, f64Bit);
4202	}
4203
4204
4205	/**
4206	* A64: Encodes CCMP or CCMN with register and 5-bit immediate.
4207	*
4208	* @returns The encoded instruction.
4209	* @param iRegSrc The register. SP is NOT valid, but ZR is.
4210	* @param uImm5 The immediate, to compare iRegSrc with.
4211	* @param fNzcv The N, Z, C & V flags values to load if the condition
4212	* does not match. See RMA64_NZCV_F_XXX.
4213	* @param enmCond The condition guarding the compare.
4214	* @param fCCmp Set for CCMP (default), clear for CCMN.
4215	* @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4216	*/
4217	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
4218	bool fCCmp = true, bool f64Bit = true)
4219	{
4220	Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
4221
4222	return ((uint32_t)f64Bit << 31)
4223	\| ((uint32_t)fCCmp << 30)
4224	\| UINT32_C(0x3a400800)
4225	\| (uImm5 << 16)
4226	\| ((uint32_t)enmCond << 12)
4227	\| (iRegSrc << 5)
4228	\| fNzcv;
4229	}
4230
4231	/** CCMP w/ immediate. */
4232	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4233	ARMV8INSTRCOND enmCond, bool f64Bit = true)
4234	{
4235	return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /fCCmp/, f64Bit);
4236	}
4237
4238
4239	/** CCMN w/ immediate. */
4240	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4241	ARMV8INSTRCOND enmCond, bool f64Bit = true)
4242	{
4243	return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /fCCmp/, f64Bit);
4244	}
4245
4246
4247	/**
4248	* A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
4249	*
4250	* @returns The encoded instruction.
4251	* @param uOp Opcode bit 30.
4252	* @param uOp2 Opcode bits 11:10.
4253	* @param iRegResult The result register. SP is NOT valid, but ZR is.
4254	* @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
4255	* @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
4256	* @param enmCond The condition guarding the compare.
4257	* @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4258	*/
4259	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
4260	uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4261	{
4262	Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4263
4264	return ((uint32_t)f64Bit << 31)
4265	\| (uOp << 30)
4266	\| UINT32_C(0x1a800000)
4267	\| (iRegSrc2 << 16)
4268	\| ((uint32_t)enmCond << 12)
4269	\| (uOp2 << 10)
4270	\| (iRegSrc1 << 5)
4271	\| iRegResult;
4272	}
4273
4274
4275	/** A64: Encodes CSEL.
4276	* @see Armv8A64MkInstrCondSelect for details. */
4277	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4278	ARMV8INSTRCOND enmCond, bool f64Bit = true)
4279	{
4280	return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4281	}
4282
4283
4284	/** A64: Encodes CSINC.
4285	* @see Armv8A64MkInstrCondSelect for details. */
4286	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4287	ARMV8INSTRCOND enmCond, bool f64Bit = true)
4288	{
4289	return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4290	}
4291
4292
4293	/** A64: Encodes CSET.
4294	* @see Armv8A64MkInstrCondSelect for details. */
4295	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4296	{
4297	Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4298	enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4299	return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4300	}
4301
4302
4303	/** A64: Encodes CSINV.
4304	* @see Armv8A64MkInstrCondSelect for details. */
4305	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4306	ARMV8INSTRCOND enmCond, bool f64Bit = true)
4307	{
4308	return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4309	}
4310
4311	/** A64: Encodes CSETM.
4312	* @see Armv8A64MkInstrCondSelect for details. */
4313	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4314	{
4315	Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4316	enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4317	return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4318	}
4319
4320
4321	/** A64: Encodes CSNEG.
4322	* @see Armv8A64MkInstrCondSelect for details. */
4323	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4324	ARMV8INSTRCOND enmCond, bool f64Bit = true)
4325	{
4326	return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4327	}
4328
4329
4330	/**
4331	* A64: Encodes REV instruction.
4332	*
4333	* @returns The encoded instruction.
4334	* @param iRegDst The destination register. SP is NOT valid.
4335	* @param iRegSrc The source register. SP is NOT valid, but ZR is
4336	* @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4337	*/
4338	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4339	{
4340	Assert(iRegDst < 32); Assert(iRegSrc < 32);
4341
4342	return ((uint32_t)f64Bit << 31)
4343	\| UINT32_C(0x5ac00800)
4344	\| ((uint32_t)f64Bit << 10)
4345	\| (iRegSrc << 5)
4346	\| iRegDst;
4347	}
4348
4349
4350	/**
4351	* A64: Encodes REV16 instruction.
4352	*
4353	* @returns The encoded instruction.
4354	* @param iRegDst The destination register. SP is NOT valid.
4355	* @param iRegSrc The source register. SP is NOT valid, but ZR is
4356	* @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4357	*/
4358	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4359	{
4360	Assert(iRegDst < 32); Assert(iRegSrc < 32);
4361
4362	return ((uint32_t)f64Bit << 31)
4363	\| UINT32_C(0x5ac00400)
4364	\| (iRegSrc << 5)
4365	\| iRegDst;
4366	}
4367
4368
4369	/**
4370	* A64: Encodes SETF8 & SETF16.
4371	*
4372	* @returns The encoded instruction.
4373	* @param iRegResult The register holding the result. SP is NOT valid.
4374	* @param f16Bit Set for SETF16, clear for SETF8.
4375	*/
4376	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
4377	{
4378	Assert(iRegResult < 32);
4379
4380	return UINT32_C(0x3a00080d)
4381	\| ((uint32_t)f16Bit << 14)
4382	\| (iRegResult << 5);
4383	}
4384
4385
4386	/**
4387	* A64: Encodes RMIF.
4388	*
4389	* @returns The encoded instruction.
4390	* @param iRegSrc The source register to get flags from.
4391	* @param cRotateRight The right rotate count (LSB bit offset).
4392	* @param fMask Mask of which flag bits to set:
4393	* - bit 0: V
4394	* - bit 1: C
4395	* - bit 2: Z
4396	* - bit 3: N
4397	*/
4398	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRmif(uint32_t iRegSrc, uint32_t cRotateRight, uint32_t fMask)
4399	{
4400	Assert(iRegSrc < 32); Assert(cRotateRight < 64); Assert(fMask <= 0xf);
4401
4402	return UINT32_C(0xba000400)
4403	\| (cRotateRight << 15)
4404	\| (iRegSrc << 5)
4405	\| fMask;
4406	}
4407
4408
4409	/**
4410	* A64: Encodes MRS (for reading a system register into a GPR).
4411	*
4412	* @returns The encoded instruction.
4413	* @param iRegDst The register to put the result into. SP is NOT valid.
4414	* @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4415	* IPRT specific format, of the register to read.
4416	*/
4417	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
4418	{
4419	Assert(iRegDst < 32);
4420	Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4421
4422	/* Note. The top bit of idSysReg must always be set and is also set in
4423	0xd5300000, otherwise we'll be encoding a different instruction. */
4424	return UINT32_C(0xd5300000)
4425	\| (idSysReg << 5)
4426	\| iRegDst;
4427	}
4428
4429
4430	/**
4431	* A64: Encodes MSR (for writing a GPR to a system register).
4432	*
4433	* @returns The encoded instruction.
4434	* @param iRegSrc The register which value to write. SP is NOT valid.
4435	* @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4436	* IPRT specific format, of the register to write.
4437	*/
4438	DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
4439	{
4440	Assert(iRegSrc < 32);
4441	Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4442
4443	/* Note. The top bit of idSysReg must always be set and is also set in
4444	0xd5100000, otherwise we'll be encoding a different instruction. */
4445	return UINT32_C(0xd5100000)
4446	\| (idSysReg << 5)
4447	\| iRegSrc;
4448	}
4449
4450
4451	/** @} */
4452
4453
4454	/** @defgroup grp_rt_armv8_mkinstr_vec Vector Instruction Encoding Helpers
4455	* @ingroup grp_rt_armv8_mkinstr
4456	*
4457	* A few inlined functions and macros for assisting in encoding common ARMv8
4458	* Neon/SIMD instructions.
4459	*
4460	* @{ */
4461
4462	/** Armv8 vector logical operation. */
4463	typedef enum
4464	{
4465	kArmv8VecInstrLogicOp_And = 0, /*< AND /
4466	kArmv8VecInstrLogicOp_Bic = RT_BIT_32(22), /*< BIC /
4467	kArmv8VecInstrLogicOp_Orr = RT_BIT_32(23), /*< ORR /
4468	kArmv8VecInstrLogicOp_Orn = RT_BIT_32(23) \| RT_BIT_32(22), /*< ORN /
4469	kArmv8VecInstrLogicOp_Eor = RT_BIT_32(29), /*< EOR /
4470	kArmv8VecInstrLogicOp_Bsl = RT_BIT_32(29) \| RT_BIT_32(22), /*< BSL /
4471	kArmv8VecInstrLogicOp_Bit = RT_BIT_32(29) \| RT_BIT_32(23), /*< BIT /
4472	kArmv8VecInstrLogicOp_Bif = RT_BIT_32(29) \| RT_BIT_32(23) \| RT_BIT_32(22) /*< BIF /
4473	} ARMV8INSTRVECLOGICOP;
4474
4475
4476	/**
4477	* A64: Encodes logical instruction (vector, register).
4478	*
4479	* @returns The encoded instruction.
4480	* @param enmOp The operation to encode.
4481	* @param iVecRegDst The vector register to put the result into.
4482	* @param iVecRegSrc1 The 1st source register.
4483	* @param iVecRegSrc2 The 2nd source register.
4484	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4485	* or just the low 64-bit (false).
4486	*/
4487	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrLogical(ARMV8INSTRVECLOGICOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4488	bool f128Bit = true)
4489	{
4490	Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4491
4492	return UINT32_C(0x0e201c00)
4493	\| (uint32_t)enmOp
4494	\| ((uint32_t)f128Bit << 30)
4495	\| (iVecRegSrc2 << 16)
4496	\| (iVecRegSrc1 << 5)
4497	\| iVecRegDst;
4498	}
4499
4500
4501	/**
4502	* A64: Encodes ORR (vector, register).
4503	*
4504	* @returns The encoded instruction.
4505	* @param iVecRegDst The vector register to put the result into.
4506	* @param iVecRegSrc1 The 1st source register.
4507	* @param iVecRegSrc2 The 2nd source register.
4508	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4509	* or just the low 64-bit (false).
4510	*/
4511	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrOrr(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4512	bool f128Bit = true)
4513	{
4514	return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Orr, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
4515	}
4516
4517
4518	/**
4519	* A64: Encodes EOR (vector, register).
4520	*
4521	* @returns The encoded instruction.
4522	* @param iVecRegDst The vector register to put the result into.
4523	* @param iVecRegSrc1 The 1st source register.
4524	* @param iVecRegSrc2 The 2nd source register.
4525	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4526	* or just the low 64-bit (false).
4527	*/
4528	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrEor(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4529	bool f128Bit = true)
4530	{
4531	return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Eor, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
4532	}
4533
4534
4535	/**
4536	* A64: Encodes AND (vector, register).
4537	*
4538	* @returns The encoded instruction.
4539	* @param iVecRegDst The vector register to put the result into.
4540	* @param iVecRegSrc1 The 1st source register.
4541	* @param iVecRegSrc2 The 2nd source register.
4542	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4543	* or just the low 64-bit (false).
4544	*/
4545	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAnd(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4546	bool f128Bit = true)
4547	{
4548	return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_And, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
4549	}
4550
4551
4552	/** Armv8 UMOV/INS vector element size. */
4553	typedef enum ARMV8INSTRUMOVINSSZ
4554	{
4555	kArmv8InstrUmovInsSz_U8 = 0, /*< Byte. /
4556	kArmv8InstrUmovInsSz_U16 = 1, /*< Halfword. /
4557	kArmv8InstrUmovInsSz_U32 = 2, /*< 32-bit. /
4558	kArmv8InstrUmovInsSz_U64 = 3 /*< 64-bit (only valid when the destination is a 64-bit register. /
4559	} ARMV8INSTRUMOVINSSZ;
4560
4561
4562	/**
4563	* A64: Encodes UMOV (vector, register).
4564	*
4565	* @returns The encoded instruction.
4566	* @param iRegDst The register to put the result into.
4567	* @param iVecRegSrc The vector source register.
4568	* @param idxElem The element index.
4569	* @param enmSz Element size of the source vector register.
4570	* @param fDst64Bit Flag whether the destination register is 64-bit (true) or 32-bit (false).
4571	*/
4572	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUmov(uint32_t iRegDst, uint32_t iVecRegSrc, uint8_t idxElem,
4573	ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64, bool fDst64Bit = true)
4574	{
4575	Assert(iRegDst < 32); Assert(iVecRegSrc < 32);
4576	Assert((fDst64Bit && enmSz == kArmv8InstrUmovInsSz_U64) \|\| (!fDst64Bit && enmSz != kArmv8InstrUmovInsSz_U64));
4577	Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
4578	\|\| (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
4579	\|\| (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
4580	\|\| (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
4581
4582	return UINT32_C(0x0e003c00)
4583	\| ((uint32_t)fDst64Bit << 30)
4584	\| ((uint32_t)idxElem << (16 + enmSz + 1))
4585	\| (RT_BIT_32(enmSz) << 16)
4586	\| (iVecRegSrc << 5)
4587	\| iRegDst;
4588	}
4589
4590
4591	/**
4592	* A64: Encodes INS (vector, register).
4593	*
4594	* @returns The encoded instruction.
4595	* @param iVecRegDst The vector register to put the result into.
4596	* @param iRegSrc The source register.
4597	* @param idxElem The element index for the destination.
4598	* @param enmSz Element size of the source vector register.
4599	*
4600	* @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
4601	*/
4602	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrIns(uint32_t iVecRegDst, uint32_t iRegSrc, uint8_t idxElem,
4603	ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64)
4604	{
4605	Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
4606	Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
4607	\|\| (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
4608	\|\| (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
4609	\|\| (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
4610
4611	return UINT32_C(0x4e001c00)
4612	\| ((uint32_t)idxElem << (16 + enmSz + 1))
4613	\| (RT_BIT_32(enmSz) << 16)
4614	\| (iRegSrc << 5)
4615	\| iVecRegDst;
4616	}
4617
4618
4619	/**
4620	* A64: Encodes DUP (vector, register).
4621	*
4622	* @returns The encoded instruction.
4623	* @param iVecRegDst The vector register to put the result into.
4624	* @param iRegSrc The source register (ZR is valid).
4625	* @param enmSz Element size of the source vector register.
4626	* @param f128Bit Flag whether the instruction operates on the whole 128-bit of the vector register (true) or
4627	* just the low 64-bit (false).
4628	*
4629	* @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
4630	*/
4631	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrDup(uint32_t iVecRegDst, uint32_t iRegSrc, ARMV8INSTRUMOVINSSZ enmSz,
4632	bool f128Bit = true)
4633	{
4634	Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
4635	Assert( (enmSz == kArmv8InstrUmovInsSz_U8)
4636	\|\| (enmSz == kArmv8InstrUmovInsSz_U16)
4637	\|\| (enmSz == kArmv8InstrUmovInsSz_U32)
4638	\|\| (enmSz == kArmv8InstrUmovInsSz_U64));
4639
4640	return UINT32_C(0x0e000c00)
4641	\| ((uint32_t)f128Bit << 30)
4642	\| (RT_BIT_32(enmSz) << 16)
4643	\| (iRegSrc << 5)
4644	\| iVecRegDst;
4645	}
4646
4647
4648	/** Armv8 vector compare to zero vector element size. */
4649	typedef enum ARMV8INSTRVECCMPZEROSZ
4650	{
4651	kArmv8InstrCmpZeroSz_S8 = 0, /*< Byte. /
4652	kArmv8InstrCmpZeroSz_S16 = 1, /*< Halfword. /
4653	kArmv8InstrCmpZeroSz_S32 = 2, /*< 32-bit. /
4654	kArmv8InstrCmpZeroSz_S64 = 3 /*< 64-bit. /
4655	} ARMV8INSTRVECCMPZEROSZ;
4656
4657
4658	/** Armv8 vector compare to zero vector operation. */
4659	typedef enum ARMV8INSTRVECCMPZEROOP
4660	{
4661	kArmv8InstrCmpZeroOp_Gt = 0, /*< Greater than. /
4662	kArmv8InstrCmpZeroOp_Ge = RT_BIT_32(29), /*< Greater than or equal to. /
4663	kArmv8InstrCmpZeroOp_Eq = RT_BIT_32(12), /*< Equal to. /
4664	kArmv8InstrCmpZeroOp_Le = RT_BIT_32(29) \| RT_BIT_32(12) /*< Lower than or equal to. /
4665	} ARMV8INSTRVECCMPZEROOP;
4666
4667
4668	/**
4669	* A64: Encodes CMGT, CMGE, CMEQ or CMLE against zero (vector, register).
4670	*
4671	* @returns The encoded instruction.
4672	* @param iVecRegDst The vector register to put the result into.
4673	* @param iVecRegSrc The vector source register.
4674	* @param enmSz Vector element size.
4675	* @param enmOp The compare operation against to encode.
4676	*/
4677	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpToZero(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECCMPZEROSZ enmSz,
4678	ARMV8INSTRVECCMPZEROOP enmOp)
4679	{
4680	Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4681
4682	return UINT32_C(0x5e208800)
4683	\| ((uint32_t)enmSz << 22)
4684	\| (RT_BIT_32(enmSz) << 16)
4685	\| (iVecRegSrc << 5)
4686	\| iVecRegDst
4687	\| (uint32_t)enmOp;
4688	}
4689
4690
4691	/**
4692	* A64: Encodes CNT (vector, register).
4693	*
4694	* @returns The encoded instruction.
4695	* @param iVecRegDst The vector register to put the result into.
4696	* @param iVecRegSrc The vector source register.
4697	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4698	* or just the low 64-bit (false).
4699	*/
4700	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCnt(uint32_t iVecRegDst, uint32_t iVecRegSrc, bool f128Bit = true)
4701	{
4702	Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4703
4704	return UINT32_C(0x0e205800)
4705	\| ((uint32_t)f128Bit << 30)
4706	\| (iVecRegSrc << 5)
4707	\| iVecRegDst;
4708	}
4709
4710
4711	/** Armv8 vector unsigned sum long across vector element size. */
4712	typedef enum ARMV8INSTRVECUADDLVSZ
4713	{
4714	kArmv8InstrUAddLVSz_8B = 0, /*< 8 x 8-bit. /
4715	kArmv8InstrUAddLVSz_16B = RT_BIT_32(30), /*< 16 x 8-bit. /
4716	kArmv8InstrUAddLVSz_4H = 1, /*< 4 x 16-bit. /
4717	kArmv8InstrUAddLVSz_8H = RT_BIT_32(30) \| 1, /*< 8 x 16-bit. /
4718	kArmv8InstrUAddLVSz_4S = RT_BIT_32(30) \| 2 /*< 4 x 32-bit. /
4719	} ARMV8INSTRVECUADDLVSZ;
4720
4721
4722	/**
4723	* A64: Encodes UADDLV (vector, register).
4724	*
4725	* @returns The encoded instruction.
4726	* @param iVecRegDst The vector register to put the result into.
4727	* @param iVecRegSrc The vector source register.
4728	* @param enmSz Element size.
4729	*/
4730	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUAddLV(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECUADDLVSZ enmSz)
4731	{
4732	Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4733
4734	return UINT32_C(0x2e303800)
4735	\| ((uint32_t)enmSz)
4736	\| (iVecRegSrc << 5)
4737	\| iVecRegDst;
4738	}
4739
4740
4741	/** Armv8 USHR/USRA/URSRA/SSHR/SRSA/SSHR vector element size. */
4742	typedef enum ARMV8INSTRUSHIFTSZ
4743	{
4744	kArmv8InstrShiftSz_U8 = 8, /*< Byte. /
4745	kArmv8InstrShiftSz_U16 = 16, /*< Halfword. /
4746	kArmv8InstrShiftSz_U32 = 32, /*< 32-bit. /
4747	kArmv8InstrShiftSz_U64 = 64 /*< 64-bit. /
4748	} ARMV8INSTRUSHIFTSZ;
4749
4750	/**
4751	* A64: Encodes USHR/USRA/URSRA/SSHR/SRSA/SSHR (vector, register).
4752	*
4753	* @returns The encoded instruction.
4754	* @param iVecRegDst The vector register to put the result into.
4755	* @param iVecRegSrc The vector source register.
4756	* @param cShift Number of bits to shift.
4757	* @param enmSz Element size.
4758	* @param fUnsigned Flag whether this a signed or unsigned shift,
4759	* @param fRound Flag whether this is the rounding shift variant.
4760	* @param fAccum Flag whether this is the accumulate shift variant.
4761	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4762	* or just the low 64-bit (false).
4763	*/
4764	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShrImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
4765	bool fUnsigned = true, bool fRound = false, bool fAccum = false, bool f128Bit = true)
4766	{
4767	Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4768	Assert( cShift >= 1
4769	&& ( (enmSz == kArmv8InstrShiftSz_U8 && cShift <= 8)
4770	\|\| (enmSz == kArmv8InstrShiftSz_U16 && cShift <= 16)
4771	\|\| (enmSz == kArmv8InstrShiftSz_U32 && cShift <= 32)
4772	\|\| (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
4773
4774	return UINT32_C(0x0f000400)
4775	\| ((uint32_t)f128Bit << 30)
4776	\| ((uint32_t)fUnsigned << 29)
4777	\| ((((uint32_t)enmSz << 1) - cShift) << 16)
4778	\| ((uint32_t)fRound << 13)
4779	\| ((uint32_t)fAccum << 12)
4780	\| (iVecRegSrc << 5)
4781	\| iVecRegDst;
4782	}
4783
4784
4785	/**
4786	* A64: Encodes SHL (vector, register).
4787	*
4788	* @returns The encoded instruction.
4789	* @param iVecRegDst The vector register to put the result into.
4790	* @param iVecRegSrc The vector source register.
4791	* @param cShift Number of bits to shift.
4792	* @param enmSz Element size.
4793	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4794	* or just the low 64-bit (false).
4795	*/
4796	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
4797	bool f128Bit = true)
4798	{
4799	Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4800	Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
4801	\|\| (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
4802	\|\| (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
4803	\|\| (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
4804
4805	return UINT32_C(0x0f005400)
4806	\| ((uint32_t)f128Bit << 30)
4807	\| (((uint32_t)enmSz \| cShift) << 16)
4808	\| (iVecRegSrc << 5)
4809	\| iVecRegDst;
4810	}
4811
4812
4813	/** Armv8 vector arith ops element size. */
4814	typedef enum ARMV8INSTRVECARITHSZ
4815	{
4816	kArmv8VecInstrArithSz_8 = 0, /*< 8-bit. /
4817	kArmv8VecInstrArithSz_16 = 1, /*< 16-bit. /
4818	kArmv8VecInstrArithSz_32 = 2, /*< 32-bit. /
4819	kArmv8VecInstrArithSz_64 = 3 /*< 64-bit. /
4820	} ARMV8INSTRVECARITHSZ;
4821
4822
4823	/** Armv8 vector arithmetic operation. */
4824	typedef enum
4825	{
4826	kArmv8VecInstrArithOp_Add = RT_BIT_32(15), /*< ADD /
4827	kArmv8VecInstrArithOp_Sub = RT_BIT_32(29) \| RT_BIT_32(15), /*< SUB /
4828	kArmv8VecInstrArithOp_UnsignSat_Add = RT_BIT_32(29) \| RT_BIT_32(11), /*< UQADD /
4829	kArmv8VecInstrArithOp_UnsignSat_Sub = RT_BIT_32(29) \| RT_BIT_32(13) \| RT_BIT_32(11), /*< UQSUB /
4830	kArmv8VecInstrArithOp_SignSat_Add = RT_BIT_32(11), /*< SQADD /
4831	kArmv8VecInstrArithOp_SignSat_Sub = RT_BIT_32(13) \| RT_BIT_32(11), /*< SQSUB /
4832	kArmv8VecInstrArithOp_Mul = RT_BIT_32(15) \| RT_BIT_32(12) \| RT_BIT_32(11) /*< MUL /
4833	} ARMV8INSTRVECARITHOP;
4834
4835
4836	/**
4837	* A64: Encodes an arithmetic operation (vector, register).
4838	*
4839	* @returns The encoded instruction.
4840	* @param enmOp The operation to encode.
4841	* @param iVecRegDst The vector register to put the result into.
4842	* @param iVecRegSrc1 The first vector source register.
4843	* @param iVecRegSrc2 The second vector source register.
4844	* @param enmSz Element size.
4845	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4846	* or just the low 64-bit (false).
4847	*/
4848	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrArithOp(ARMV8INSTRVECARITHOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4849	ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4850	{
4851	Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4852
4853	return UINT32_C(0x0e200400)
4854	\| (uint32_t)enmOp
4855	\| ((uint32_t)f128Bit << 30)
4856	\| ((uint32_t)enmSz << 22)
4857	\| (iVecRegSrc2 << 16)
4858	\| (iVecRegSrc1 << 5)
4859	\| iVecRegDst;
4860	}
4861
4862
4863	/** Armv8 vector compare operation. */
4864	typedef enum ARMV8VECINSTRCMPOP
4865	{
4866	/* U insn[15:10] */
4867	kArmv8VecInstrCmpOp_Gt = UINT32_C(0x3400), /*< Greater than (>) (signed) /
4868	kArmv8VecInstrCmpOp_Ge = UINT32_C(0x3c00), /*< Greater or equal (>=) (signed) /
4869	kArmv8VecInstrCmpOp_Hi = RT_BIT_32(29) \| UINT32_C(0x3400), /*< Greater than (>) (unsigned) /
4870	kArmv8VecInstrCmpOp_Hs = RT_BIT_32(29) \| UINT32_C(0x3c00), /*< Greater or equal (>=) (unsigned) /
4871	kArmv8VecInstrCmpOp_Eq = RT_BIT_32(29) \| UINT32_C(0x8c00) /*< Equal (==) (unsigned) /
4872	} ARMV8VECINSTRCMPOP;
4873
4874	/**
4875	* A64: Encodes CMEQ/CMGE/CMGT/CMHI/CMHS (register variant) (vector, register).
4876	*
4877	* @returns The encoded instruction.
4878	* @param enmOp The operation to perform.
4879	* @param iVecRegDst The vector register to put the result into.
4880	* @param iVecRegSrc1 The first vector source register.
4881	* @param iVecRegSrc2 The second vector source register.
4882	* @param enmSz Element size.
4883	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4884	* or just the low 64-bit (false).
4885	*/
4886	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmp(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4887	ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4888	{
4889	Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4890
4891	return UINT32_C(0x0e200000)
4892	\| ((uint32_t)f128Bit << 30)
4893	\| ((uint32_t)enmSz << 22)
4894	\| (iVecRegSrc2 << 16)
4895	\| ((uint32_t)enmOp)
4896	\| (iVecRegSrc1 << 5)
4897	\| iVecRegDst;
4898	}
4899
4900
4901	/** Armv8 vector compare against zero operation. */
4902	typedef enum ARMV8VECINSTRCMPZEROOP
4903	{
4904	/* U insn[15:10] */
4905	kArmv8VecInstrCmpZeroOp_Gt = UINT32_C(0x8800), /*< Greater than zero (>) (signed) /
4906	kArmv8VecInstrCmpZeroOp_Eq = UINT32_C(0x9800), /*< Equal to zero (==) /
4907	kArmv8VecInstrCmpZeroOp_Lt = UINT32_C(0xa800), /*< Lower than zero (>=) (signed) /
4908	kArmv8VecInstrCmpZeroOp_Ge = RT_BIT_32(29) \| UINT32_C(0x8800), /*< Greater or equal to zero (>=) (signed) /
4909	kArmv8VecInstrCmpZeroOp_Le = RT_BIT_32(29) \| UINT32_C(0x9800) /*< Lower or equal to zero (<=) (signed) /
4910	} ARMV8VECINSTRCMPZEROOP;
4911
4912	/**
4913	* A64: Encodes CMEQ/CMGE/CMGT/CMLE/CMLT (zero variant) (vector, register).
4914	*
4915	* @returns The encoded instruction.
4916	* @param enmOp The operation to perform.
4917	* @param iVecRegDst The vector register to put the result into.
4918	* @param iVecRegSrc The first vector source register.
4919	* @param enmSz Element size.
4920	* @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4921	* or just the low 64-bit (false).
4922	*/
4923	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpAgainstZero(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc,
4924	ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4925	{
4926	Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4927
4928	return UINT32_C(0x0e200000)
4929	\| ((uint32_t)f128Bit << 30)
4930	\| ((uint32_t)enmSz << 22)
4931	\| ((uint32_t)enmOp)
4932	\| (iVecRegSrc << 5)
4933	\| iVecRegDst;
4934	}
4935
4936
4937	/** Armv8 [Signed,Unsigned] Extract {Unsigned} operation. */
4938	typedef enum
4939	{
4940	kArmv8VecInstrQxtnOp_Sqxtn = RT_BIT_32(14), /*< SQXTN /
4941	kArmv8VecInstrQxtnOp_Sqxtun = RT_BIT_32(29) \| RT_BIT_32(13), /*< SQXTUN /
4942	kArmv8VecInstrQxtnOp_Uqxtn = RT_BIT_32(29) \| RT_BIT_32(14) /*< UQXTN /
4943	} ARMV8INSTRVECQXTNOP;
4944
4945	/**
4946	* A64: Encodes SQXTN/SQXTN2/UQXTN/UQXTN2/SQXTUN/SQXTUN2 (vector, register).
4947	*
4948	* @returns The encoded instruction.
4949	* @param enmOp The operation to perform.
4950	* @param fUpper Flag whether to write the result to the lower (false) or upper (true) half of the destinatiom register.
4951	* @param iVecRegDst The vector register to put the result into.
4952	* @param iVecRegSrc The first vector source register.
4953	* @param enmSz Element size.
4954	*/
4955	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrQxtn(ARMV8INSTRVECQXTNOP enmOp, bool fUpper, uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECARITHSZ enmSz)
4956	{
4957	Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4958
4959	return UINT32_C(0x0e210800)
4960	\| ((uint32_t)enmOp)
4961	\| ((uint32_t)fUpper << 30)
4962	\| ((uint32_t)enmSz << 22)
4963	\| (iVecRegSrc << 5)
4964	\| iVecRegDst;
4965	}
4966
4967
4968	/** Armv8 floating point size. */
4969	typedef enum
4970	{
4971	kArmv8VecInstrFpSz_2x_Single = 0, /*< 2x single precision values in the low 64-bit of the 128-bit register. /
4972	kArmv8VecInstrFpSz_4x_Single = RT_BIT_32(30), /*< 4x single precision values in the 128-bit register. /
4973	kArmv8VecInstrFpSz_2x_Double = RT_BIT_32(30) \| RT_BIT_32(22), /*< 2x double precision values in the 128-bit register. /
4974	} ARMV8INSTRVECFPSZ;
4975
4976
4977	/** Armv8 3 operand floating point operation. */
4978	typedef enum
4979	{
4980	/* insn[29] insn[23] insn[15:11] */
4981	kArmv8VecInstrFpOp_Add = UINT32_C(0xd000), /*< FADD /
4982	kArmv8VecInstrFpOp_Sub = RT_BIT_32(23) \| UINT32_C(0xd000), /*< FADD /
4983	kArmv8VecInstrFpOp_AddPairwise = RT_BIT_32(29) \| UINT32_C(0xd000), /*< FADDP /
4984	kArmv8VecInstrFpOp_Mul = RT_BIT_32(29) \| UINT32_C(0xd800), /*< FMUL /
4985	kArmv8VecInstrFpOp_Div = RT_BIT_32(29) \| UINT32_C(0xf800), /*< FDIV /
4986
4987	kArmv8VecInstrFpOp_Max = UINT32_C(0xf000), /*< FMAX /
4988	kArmv8VecInstrFpOp_MaxNumber = UINT32_C(0xc000), /*< FMAXNM /
4989	kArmv8VecInstrFpOp_MaxNumberPairwise = RT_BIT_32(29) \| UINT32_C(0xc000), /*< FMAXNMP /
4990	kArmv8VecInstrFpOp_MaxPairwise = RT_BIT_32(29) \| UINT32_C(0xf000), /*< FMAXP /
4991
4992	kArmv8VecInstrFpOp_Min = RT_BIT_32(23) \| UINT32_C(0xf000), /*< FMIN /
4993	kArmv8VecInstrFpOp_MinNumber = RT_BIT_32(23) \| UINT32_C(0xc000), /*< FMINNM /
4994	kArmv8VecInstrFpOp_MinNumberPairwise = RT_BIT_32(29) \| RT_BIT_32(23) \| UINT32_C(0xc000), /*< FMINNMP /
4995	kArmv8VecInstrFpOp_MinPairwise = RT_BIT_32(29) \| RT_BIT_32(23) \| UINT32_C(0xf000), /*< FMINP /
4996
4997	kArmv8VecInstrFpOp_Fmla = UINT32_C(0xc800), /*< FMLA /
4998	kArmv8VecInstrFpOp_Fmls = RT_BIT_32(23) \| UINT32_C(0xc800), /*< FMLS /
4999	} ARMV8INSTRVECFPOP;
5000
5001	/**
5002	* A64: Encodes a 3 operand floating point operation (vector, register).
5003	*
5004	* @returns The encoded instruction.
5005	* @param enmOp The operation to perform.
5006	* @param enmSz The size to operate on.
5007	* @param iVecRegDst The vector register to put the result into.
5008	* @param iVecRegSrc1 The first vector source register.
5009	* @param iVecRegSrc2 The second vector source register.
5010	*/
5011	DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrFp3Op(ARMV8INSTRVECFPOP enmOp, ARMV8INSTRVECFPSZ enmSz, uint32_t iVecRegDst,
5012	uint32_t iVecRegSrc1, uint32_t iVecRegSrc2)
5013	{
5014	Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5015
5016	return UINT32_C(0x0e200400)
5017	\| ((uint32_t)enmOp)
5018	\| ((uint32_t)enmSz)
5019	\| (iVecRegSrc2 << 16)
5020	\| (iVecRegSrc1 << 5)
5021	\| iVecRegDst;
5022	}
5023
5024
5025	/** @} */
5026
5027	#endif /* !dtrace && __cplusplus */
5028
5029	/** @} */
5030
5031	#endif /* !IPRT_INCLUDED_armv8_h */
5032

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source: vbox/trunk/include/iprt/armv8.h@ 105174

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