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source: vbox/trunk/include/iprt/armv8.h@ 105385

Last change on this file since 105385 was 105385, checked in by vboxsync, 7 months ago

include/iprt/armv8.h: Add definitions for FPCR and FPSR registers, bugref:10652
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/cdefs.h>
44# ifndef RT_IN_ASSEMBLER
45# include <iprt/types.h>
46# include <iprt/assert.h>
47# endif
48# include <iprt/assertcompile.h>
49#else
50# pragma D depends_on library vbox-types.d
51#endif
52
53/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
54 * @ingroup grp_rt
55 * @{
56 */
57
58/** @name The AArch64 register encoding - deprecated.
59 * @deprecated Use ARMV8_A64_REG_XXX instead.
60 * @todo correct code and drop these remaining ones.
61 * @{ */
62#define ARMV8_AARCH64_REG_X0 0
63#define ARMV8_AARCH64_REG_X1 1
64#define ARMV8_AARCH64_REG_X2 2
65#define ARMV8_AARCH64_REG_X3 3
66#define ARMV8_AARCH64_REG_ZR 31
67/** @} */
68
69/** @name The AArch64 general purpose register encoding.
70 * @{ */
71#define ARMV8_A64_REG_X0 0
72#define ARMV8_A64_REG_X1 1
73#define ARMV8_A64_REG_X2 2
74#define ARMV8_A64_REG_X3 3
75#define ARMV8_A64_REG_X4 4
76#define ARMV8_A64_REG_X5 5
77#define ARMV8_A64_REG_X6 6
78#define ARMV8_A64_REG_X7 7
79#define ARMV8_A64_REG_X8 8
80#define ARMV8_A64_REG_X9 9
81#define ARMV8_A64_REG_X10 10
82#define ARMV8_A64_REG_X11 11
83#define ARMV8_A64_REG_X12 12
84#define ARMV8_A64_REG_X13 13
85#define ARMV8_A64_REG_X14 14
86#define ARMV8_A64_REG_X15 15
87#define ARMV8_A64_REG_X16 16
88#define ARMV8_A64_REG_X17 17
89#define ARMV8_A64_REG_X18 18
90#define ARMV8_A64_REG_X19 19
91#define ARMV8_A64_REG_X20 20
92#define ARMV8_A64_REG_X21 21
93#define ARMV8_A64_REG_X22 22
94#define ARMV8_A64_REG_X23 23
95#define ARMV8_A64_REG_X24 24
96#define ARMV8_A64_REG_X25 25
97#define ARMV8_A64_REG_X26 26
98#define ARMV8_A64_REG_X27 27
99#define ARMV8_A64_REG_X28 28
100#define ARMV8_A64_REG_X29 29
101#define ARMV8_A64_REG_X30 30
102/** @} */
103
104/** @name The AArch64 32-bit general purpose register names.
105 * @{ */
106#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
107#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
108#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
109#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
110#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
111#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
112#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
113#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
114#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
115#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
116#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
117#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
118#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
119#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
120#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
121#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
122#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
123#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
124#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
125#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
126#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
127#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
128#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
129#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
130#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
131#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
132#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
133#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
134#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
135#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
136#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
137/** @} */
138
139/** @name The AArch64 NEON scalar register encoding.
140 * @{ */
141#define ARMV8_A64_REG_Q0 0
142#define ARMV8_A64_REG_Q1 1
143#define ARMV8_A64_REG_Q2 2
144#define ARMV8_A64_REG_Q3 3
145#define ARMV8_A64_REG_Q4 4
146#define ARMV8_A64_REG_Q5 5
147#define ARMV8_A64_REG_Q6 6
148#define ARMV8_A64_REG_Q7 7
149#define ARMV8_A64_REG_Q8 8
150#define ARMV8_A64_REG_Q9 9
151#define ARMV8_A64_REG_Q10 10
152#define ARMV8_A64_REG_Q11 11
153#define ARMV8_A64_REG_Q12 12
154#define ARMV8_A64_REG_Q13 13
155#define ARMV8_A64_REG_Q14 14
156#define ARMV8_A64_REG_Q15 15
157#define ARMV8_A64_REG_Q16 16
158#define ARMV8_A64_REG_Q17 17
159#define ARMV8_A64_REG_Q18 18
160#define ARMV8_A64_REG_Q19 19
161#define ARMV8_A64_REG_Q20 20
162#define ARMV8_A64_REG_Q21 21
163#define ARMV8_A64_REG_Q22 22
164#define ARMV8_A64_REG_Q23 23
165#define ARMV8_A64_REG_Q24 24
166#define ARMV8_A64_REG_Q25 25
167#define ARMV8_A64_REG_Q26 26
168#define ARMV8_A64_REG_Q27 27
169#define ARMV8_A64_REG_Q28 28
170#define ARMV8_A64_REG_Q29 29
171#define ARMV8_A64_REG_Q30 30
172#define ARMV8_A64_REG_Q31 31
173/** @} */
174
175/** @name The AArch64 NEON vector register encoding.
176 * @{ */
177#define ARMV8_A64_REG_V0 ARMV8_A64_REG_Q0
178#define ARMV8_A64_REG_V1 ARMV8_A64_REG_Q1
179#define ARMV8_A64_REG_V2 ARMV8_A64_REG_Q2
180#define ARMV8_A64_REG_V3 ARMV8_A64_REG_Q3
181#define ARMV8_A64_REG_V4 ARMV8_A64_REG_Q4
182#define ARMV8_A64_REG_V5 ARMV8_A64_REG_Q5
183#define ARMV8_A64_REG_V6 ARMV8_A64_REG_Q6
184#define ARMV8_A64_REG_V7 ARMV8_A64_REG_Q7
185#define ARMV8_A64_REG_V8 ARMV8_A64_REG_Q8
186#define ARMV8_A64_REG_V9 ARMV8_A64_REG_Q9
187#define ARMV8_A64_REG_V10 ARMV8_A64_REG_Q10
188#define ARMV8_A64_REG_V11 ARMV8_A64_REG_Q11
189#define ARMV8_A64_REG_V12 ARMV8_A64_REG_Q12
190#define ARMV8_A64_REG_V13 ARMV8_A64_REG_Q13
191#define ARMV8_A64_REG_V14 ARMV8_A64_REG_Q14
192#define ARMV8_A64_REG_V15 ARMV8_A64_REG_Q15
193#define ARMV8_A64_REG_V16 ARMV8_A64_REG_Q16
194#define ARMV8_A64_REG_V17 ARMV8_A64_REG_Q17
195#define ARMV8_A64_REG_V18 ARMV8_A64_REG_Q18
196#define ARMV8_A64_REG_V19 ARMV8_A64_REG_Q19
197#define ARMV8_A64_REG_V20 ARMV8_A64_REG_Q20
198#define ARMV8_A64_REG_V21 ARMV8_A64_REG_Q21
199#define ARMV8_A64_REG_V22 ARMV8_A64_REG_Q22
200#define ARMV8_A64_REG_V23 ARMV8_A64_REG_Q23
201#define ARMV8_A64_REG_V24 ARMV8_A64_REG_Q24
202#define ARMV8_A64_REG_V25 ARMV8_A64_REG_Q25
203#define ARMV8_A64_REG_V26 ARMV8_A64_REG_Q26
204#define ARMV8_A64_REG_V27 ARMV8_A64_REG_Q27
205#define ARMV8_A64_REG_V28 ARMV8_A64_REG_Q28
206#define ARMV8_A64_REG_V29 ARMV8_A64_REG_Q29
207#define ARMV8_A64_REG_V30 ARMV8_A64_REG_Q30
208#define ARMV8_A64_REG_V31 ARMV8_A64_REG_Q31
209/** @} */
210
211/** @name The AArch64 register 31.
212 * @note Register 31 typically refers to the zero register, but can also in
213 * select case (by instruction and opecode field) refer the to stack
214 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
215 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
216 * 31 will be the zero register.
217 * @{ */
218/** The stack pointer. */
219#define ARMV8_A64_REG_SP 31
220/** The zero register. Reads as zero, writes ignored. */
221#define ARMV8_A64_REG_XZR 31
222/** The zero register, the 32-bit register name. */
223#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
224/** @} */
225
226/** @name AArch64 register aliases
227 * @{ */
228/** The link register is typically mapped to x30 as that's the default pick of
229 * the RET instruction. */
230#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
231/** Frame base pointer is typically mapped to x29. */
232#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
233/** @} */
234
235
236/** @name System register encoding.
237 * @{
238 */
239/** Mask for the op0 part of an MSR/MRS instruction */
240#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
241/** Shift for the op0 part of an MSR/MRS instruction */
242#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
243/** Returns the op0 part of the given MRS/MSR instruction. */
244#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
245/** Mask for the op1 part of an MSR/MRS instruction */
246#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
247/** Shift for the op1 part of an MSR/MRS instruction */
248#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
249/** Returns the op1 part of the given MRS/MSR instruction. */
250#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
251/** Mask for the CRn part of an MSR/MRS instruction */
252#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
253 | RT_BIT_32(15) )
254/** Shift for the CRn part of an MSR/MRS instruction */
255#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
256/** Returns the CRn part of the given MRS/MSR instruction. */
257#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
258/** Mask for the CRm part of an MSR/MRS instruction */
259#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
260 | RT_BIT_32(11) )
261/** Shift for the CRm part of an MSR/MRS instruction */
262#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
263/** Returns the CRn part of the given MRS/MSR instruction. */
264#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
265/** Mask for the op2 part of an MSR/MRS instruction */
266#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
267/** Shift for the op2 part of an MSR/MRS instruction */
268#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
269/** Returns the op2 part of the given MRS/MSR instruction. */
270#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
271/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
272#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
273 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
274 | ARMV8_AARCH64_SYSREG_OP2_MASK)
275/** @} */
276
277/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
278 * IPRT specific and not part of the ARMv8 specification.
279 * @{ */
280#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
281 UINT16_C( (((a_Op0) & 0x3) << 14) \
282 | (((a_Op1) & 0x7) << 11) \
283 | (((a_CRn) & 0xf) << 7) \
284 | (((a_CRm) & 0xf) << 3) \
285 | ((a_Op2) & 0x7))
286/** Returns the internal system register ID from the given MRS/MSR instruction. */
287#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
288 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
289 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
290 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
291 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
292 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
293/** Encodes the given system register ID in the given MSR/MRS instruction. */
294#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
295 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
296/** @} */
297
298
299/** @name System register IDs.
300 * @{ */
301/** MDSCR_EL1 - RW. */
302#define ARMV8_AARCH64_SYSREG_MDSCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 2)
303/** DBGBVR<0..15>_EL1 register - RW. */
304#define ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 4)
305/** DBGBCR<0..15>_EL1 register - RW. */
306#define ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 5)
307/** DBGWVR<0..15>_EL1 register - RW. */
308#define ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 6)
309/** DBGWCR<0..15>_EL1 register - RW. */
310#define ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 7)
311/** MDCCINT_EL1 register - RW. */
312#define ARMV8_AARCH64_SYSREG_MDCCINT_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 0)
313/** OSLAR_EL1 register - WO. */
314#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
315/** OSLSR_EL1 register - RO. */
316#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
317/** OSDLR_EL1 register - RW. */
318#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
319
320/** MIDR_EL1 register - RO. */
321#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
322/** MIPDR_EL1 register - RO. */
323#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
324/** REVIDR_EL1 register - RO. */
325#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
326/** ID_PFR0_EL1 register - RO. */
327#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
328/** ID_PFR1_EL1 register - RO. */
329#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
330/** ID_DFR0_EL1 register - RO. */
331#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
332/** ID_AFR0_EL1 register - RO. */
333#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
334/** ID_MMFR0_EL1 register - RO. */
335#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
336/** ID_MMFR1_EL1 register - RO. */
337#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
338/** ID_MMFR2_EL1 register - RO. */
339#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
340/** ID_MMFR3_EL1 register - RO. */
341#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
342
343/** ID_ISAR0_EL1 register - RO. */
344#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
345/** ID_ISAR1_EL1 register - RO. */
346#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
347/** ID_ISAR2_EL1 register - RO. */
348#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
349/** ID_ISAR3_EL1 register - RO. */
350#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
351/** ID_ISAR4_EL1 register - RO. */
352#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
353/** ID_ISAR5_EL1 register - RO. */
354#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
355/** ID_MMFR4_EL1 register - RO. */
356#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
357/** ID_ISAR6_EL1 register - RO. */
358#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
359
360/** MVFR0_EL1 register - RO. */
361#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
362/** MVFR1_EL1 register - RO. */
363#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
364/** MVFR2_EL1 register - RO. */
365#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
366/** ID_PFR2_EL1 register - RO. */
367#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
368/** ID_DFR1_EL1 register - RO. */
369#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
370/** ID_MMFR5_EL1 register - RO. */
371#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
372
373/** ID_AA64PFR0_EL1 register - RO. */
374#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
375/** ID_AA64PFR0_EL1 register - RO. */
376#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
377/** ID_AA64ZFR0_EL1 register - RO. */
378#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
379/** ID_AA64SMFR0_EL1 register - RO. */
380#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
381
382/** ID_AA64DFR0_EL1 register - RO. */
383#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
384/** ID_AA64DFR0_EL1 register - RO. */
385#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
386/** ID_AA64AFR0_EL1 register - RO. */
387#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
388/** ID_AA64AFR1_EL1 register - RO. */
389#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
390
391/** ID_AA64ISAR0_EL1 register - RO. */
392#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
393/** ID_AA64ISAR1_EL1 register - RO. */
394#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
395/** ID_AA64ISAR2_EL1 register - RO. */
396#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
397
398/** ID_AA64MMFR0_EL1 register - RO. */
399#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
400/** ID_AA64MMFR1_EL1 register - RO. */
401#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
402/** ID_AA64MMFR2_EL1 register - RO. */
403#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
404
405/** SCTRL_EL1 register - RW. */
406#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
407/** ACTRL_EL1 register - RW. */
408#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
409/** CPACR_EL1 register - RW. */
410#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
411/** RGSR_EL1 register - RW. */
412#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
413/** GCR_EL1 register - RW. */
414#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
415
416/** ZCR_EL1 register - RW. */
417#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
418/** TRFCR_EL1 register - RW. */
419#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
420/** SMPRI_EL1 register - RW. */
421#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
422/** SMCR_EL1 register - RW. */
423#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
424
425/** TTBR0_EL1 register - RW. */
426#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
427/** TTBR1_EL1 register - RW. */
428#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
429/** TCR_EL1 register - RW. */
430#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
431
432/** APIAKeyLo_EL1 register - RW. */
433#define ARMV8_AARCH64_SYSREG_APIAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 0)
434/** APIAKeyHi_EL1 register - RW. */
435#define ARMV8_AARCH64_SYSREG_APIAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 1)
436/** APIBKeyLo_EL1 register - RW. */
437#define ARMV8_AARCH64_SYSREG_APIBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 2)
438/** APIBKeyHi_EL1 register - RW. */
439#define ARMV8_AARCH64_SYSREG_APIBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 3)
440
441/** APDAKeyLo_EL1 register - RW. */
442#define ARMV8_AARCH64_SYSREG_APDAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 0)
443/** APDAKeyHi_EL1 register - RW. */
444#define ARMV8_AARCH64_SYSREG_APDAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 1)
445/** APDBKeyLo_EL1 register - RW. */
446#define ARMV8_AARCH64_SYSREG_APDBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 2)
447/** APDBKeyHi_EL1 register - RW. */
448#define ARMV8_AARCH64_SYSREG_APDBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 3)
449
450/** APGAKeyLo_EL1 register - RW. */
451#define ARMV8_AARCH64_SYSREG_APGAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 0)
452/** APGAKeyHi_EL1 register - RW. */
453#define ARMV8_AARCH64_SYSREG_APGAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 1)
454
455/** SPSR_EL1 register - RW. */
456#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
457/** ELR_EL1 register - RW. */
458#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
459
460/** SP_EL0 register - RW. */
461#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
462
463/** PSTATE.SPSel value. */
464#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
465/** PSTATE.CurrentEL value. */
466#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
467/** PSTATE.PAN value. */
468#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
469/** PSTATE.UAO value. */
470#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
471
472/** PSTATE.ALLINT value. */
473#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
474
475/** ICC_PMR_EL1 register - RW. */
476#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
477
478/** AFSR0_EL1 register - RW. */
479#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
480/** AFSR1_EL1 register - RW. */
481#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
482
483/** ESR_EL1 register - RW. */
484#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
485
486/** ERRIDR_EL1 register - RO. */
487#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
488/** ERRSELR_EL1 register - RW. */
489#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
490
491/** FAR_EL1 register - RW. */
492#define ARMV8_AARCH64_SYSREG_FAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 6, 0, 0)
493
494/** PAR_EL1 register - RW. */
495#define ARMV8_AARCH64_SYSREG_PAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 7, 4, 0)
496
497/** MAIR_EL1 register - RW. */
498#define ARMV8_AARCH64_SYSREG_MAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 2, 0)
499
500/** AMAIR_EL1 register - RW. */
501#define ARMV8_AARCH64_SYSREG_AMAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 3, 0)
502
503/** VBAR_EL1 register - RW. */
504#define ARMV8_AARCH64_SYSREG_VBAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 0, 0)
505
506/** ICC_IAR0_EL1 register - RO. */
507#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
508/** ICC_EOIR0_EL1 register - WO. */
509#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
510/** ICC_HPPIR0_EL1 register - WO. */
511#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
512/** ICC_BPR0_EL1 register - RW. */
513#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
514/** ICC_AP0R0_EL1 register - RW. */
515#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
516/** ICC_AP0R1_EL1 register - RW. */
517#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
518/** ICC_AP0R2_EL1 register - RW. */
519#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
520/** ICC_AP0R3_EL1 register - RW. */
521#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
522
523/** ICC_AP1R0_EL1 register - RW. */
524#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
525/** ICC_AP1R1_EL1 register - RW. */
526#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
527/** ICC_AP1R2_EL1 register - RW. */
528#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
529/** ICC_AP1R3_EL1 register - RW. */
530#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
531/** ICC_NMIAR1_EL1 register - RO. */
532#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
533
534/** ICC_DIR_EL1 register - WO. */
535#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
536/** ICC_RPR_EL1 register - RO. */
537#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
538/** ICC_SGI1R_EL1 register - WO. */
539#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
540/** ICC_ASGI1R_EL1 register - WO. */
541#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
542/** ICC_SGI0R_EL1 register - WO. */
543#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
544
545/** ICC_IAR1_EL1 register - RO. */
546#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
547/** ICC_EOIR1_EL1 register - WO. */
548#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
549/** ICC_HPPIR1_EL1 register - RO. */
550#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
551/** ICC_BPR1_EL1 register - RW. */
552#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
553/** ICC_CTLR_EL1 register - RW. */
554#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
555/** ICC_SRE_EL1 register - RW. */
556#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
557/** ICC_IGRPEN0_EL1 register - RW. */
558#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
559/** ICC_IGRPEN1_EL1 register - RW. */
560#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
561
562/** CONTEXTIDR_EL1 register - RW. */
563#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 1)
564/** TPIDR_EL1 register - RW. */
565#define ARMV8_AARCH64_SYSREG_TPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 4)
566
567/** CNTKCTL_EL1 register - RW. */
568#define ARMV8_AARCH64_SYSREG_CNTKCTL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 14, 1, 0)
569
570/** CSSELR_EL1 register - RW. */
571#define ARMV8_AARCH64_SYSREG_CSSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 2, 0, 0, 0)
572
573/** NZCV - Status Flags - ??. */
574#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
575/** DAIF - Interrupt Mask Bits - ??. */
576#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
577/** SVCR - Streaming Vector Control Register - ??. */
578#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
579/** DIT - Data Independent Timing - ??. */
580#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
581/** SSBS - Speculative Store Bypass Safe - ??. */
582#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
583/** TCO - Tag Check Override - ??. */
584#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
585
586/** FPCR register - RW. */
587#define ARMV8_AARCH64_SYSREG_FPCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 0)
588/** FPSR register - RW. */
589#define ARMV8_AARCH64_SYSREG_FPSR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 1)
590
591/** TPIDR_EL0 register - RW. */
592#define ARMV8_AARCH64_SYSREG_TPIDR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 2)
593/** TPIDRRO_EL0 register - RO. */
594#define ARMV8_AARCH64_SYSREG_TPIDRRO_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 3)
595
596/** CNTFRQ_EL0 register - RW. */
597#define ARMV8_AARCH64_SYSREG_CNTFRQ_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 0)
598/** CNTVCT_EL0 register - RW. */
599#define ARMV8_AARCH64_SYSREG_CNTVCT_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 2)
600
601/** CNTV_CTL_EL0 register - RW. */
602#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
603/** @} */
604
605
606#ifndef RT_IN_ASSEMBLER
607/**
608 * SPSR_EL2 (according to chapter C5.2.19)
609 */
610typedef union ARMV8SPSREL2
611{
612 /** The plain unsigned view. */
613 uint64_t u;
614 /** The 8-bit view. */
615 uint8_t au8[8];
616 /** The 16-bit view. */
617 uint16_t au16[4];
618 /** The 32-bit view. */
619 uint32_t au32[2];
620 /** The 64-bit view. */
621 uint64_t u64;
622} ARMV8SPSREL2;
623/** Pointer to SPSR_EL2. */
624typedef ARMV8SPSREL2 *PARMV8SPSREL2;
625/** Pointer to const SPSR_EL2. */
626typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
627#endif /* !RT_IN_ASSEMBLER */
628
629
630/** @name SPSR_EL2 (When exception is taken from AArch64 state)
631 * @{
632 */
633/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
634#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
635#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
636/** Bit 0 - SP - Selected stack pointer. */
637#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
638#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
639/** Bit 1 - Reserved (read as zero). */
640#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
641/** Bit 2 - 3 - EL - Exception level. */
642#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
643#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
644#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
645#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
646/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
647#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
648#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
649/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
650#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
651#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
652/** Bit 6 - I - FIQ interrupt mask. */
653#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
654#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
655/** Bit 7 - I - IRQ interrupt mask. */
656#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
657#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
658/** Bit 8 - A - SError interrupt mask. */
659#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
660#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
661/** Bit 9 - D - Debug Exception mask. */
662#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
663#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
664/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
665#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
666#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
667#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
668/** Bit 12 - SSBS - Speculative Store Bypass. */
669#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
670#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
671/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
672#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
673#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
674/** Bit 14 - 19 - Reserved (read as zero). */
675#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
676 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
677/** Bit 20 - IL - Illegal Execution State flag. */
678#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
679#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
680/** Bit 21 - SS - Software Step flag. */
681#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
682#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
683/** Bit 22 - PAN - Privileged Access Never flag. */
684#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
685#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
686/** Bit 23 - UAO - User Access Override flag. */
687#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
688#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
689/** Bit 24 - DIT - Data Independent Timing flag. */
690#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
691#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
692/** Bit 25 - TCO - Tag Check Override flag. */
693#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
694#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
695/** Bit 26 - 27 - Reserved (read as zero). */
696#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
697/** Bit 28 - V - Overflow condition flag. */
698#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
699#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
700/** Bit 29 - C - Carry condition flag. */
701#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
702#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
703/** Bit 30 - Z - Zero condition flag. */
704#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
705#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
706/** Bit 31 - N - Negative condition flag. */
707#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
708#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
709/** Bit 32 - 63 - Reserved (read as zero). */
710#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
711/** Checks whether the given SPSR value contains a AARCH64 execution state. */
712#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
713/** @} */
714
715/** @name Aarch64 Exception levels
716 * @{ */
717/** Exception Level 0 - User mode. */
718#define ARMV8_AARCH64_EL_0 0
719/** Exception Level 1 - Supervisor mode. */
720#define ARMV8_AARCH64_EL_1 1
721/** Exception Level 2 - Hypervisor mode. */
722#define ARMV8_AARCH64_EL_2 2
723/** @} */
724
725
726/** @name ESR_EL2 (Exception Syndrome Register, EL2)
727 * @{
728 */
729/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
730#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
731#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
732/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
733#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
734#define ARMV8_ESR_EL2_IL_BIT 25
735#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
736#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
737/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
738#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
739 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
740#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
741/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
742#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
743 | RT_BIT_64(35) | RT_BIT_64(36))
744#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
745/** @} */
746
747
748/** @name ESR_EL2 Exception Classes (EC)
749 * @{ */
750/** Unknown exception reason. */
751#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
752/** Trapped WF* instruction. */
753#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
754/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
755#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
756/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
757#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
758/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
759#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
760/** AArch32 - Trapped LDC or STC access. */
761#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
762/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
763#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
764/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
765#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
766/** AArch32 - Trapped pointer authentication instruction. */
767#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
768/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
769#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
770/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
771#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
772/** FEAT_BTI - Branch Target Exception. */
773#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
774/** Illegal Execution State. */
775#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
776/** AArch32 - SVC instruction execution. */
777#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
778/** AArch32 - HVC instruction execution. */
779#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
780/** AArch32 - SMC instruction execution. */
781#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
782/** AArch64 - SVC instruction execution. */
783#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
784/** AArch64 - HVC instruction execution. */
785#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
786/** AArch64 - SMC instruction execution. */
787#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
788/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
789#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
790/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
791#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
792/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
793#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
794/** FEAT_TME - Exception from TSTART instruction. */
795#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
796/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
797#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
798/** FEAT_SME - Access to SME functionality trapped. */
799#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
800/** FEAT_RME - Exception from Granule Protection Check. */
801#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
802/** Instruction Abort from a lower Exception level. */
803#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
804/** Instruction Abort from the same Exception level. */
805#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
806/** PC alignment fault exception. */
807#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
808/** Data Abort from a lower Exception level. */
809#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
810/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
811#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
812/** SP alignment fault exception. */
813#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
814/** FEAT_MOPS - Memory Operation Exception. */
815#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
816/** AArch32 - Trapped floating point exception. */
817#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
818/** AArch64 - Trapped floating point exception. */
819#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
820/** SError interrupt. */
821#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
822/** Breakpoint Exception from a lower Exception level. */
823#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
824/** Breakpoint Exception from the same Exception level. */
825#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
826/** Software Step Exception from a lower Exception level. */
827#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
828/** Software Step Exception from the same Exception level. */
829#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
830/** Watchpoint Exception from a lower Exception level. */
831#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
832/** Watchpoint Exception from the same Exception level. */
833#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
834/** AArch32 - BKPT instruction execution. */
835#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
836/** AArch32 - Vector Catch exception. */
837#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
838/** AArch64 - BRK instruction execution. */
839#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
840/** @} */
841
842
843/** @name ISS encoding for Data Abort exceptions.
844 * @{ */
845/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
846#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
847 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
848#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
849/** Bit 6 - WnR - Write not Read. */
850#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
851#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
852/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
853#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
854#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
855/** Bit 8 - CM - Cache maintenance instruction. */
856#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
857#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
858/** Bit 9 - EA - External abort type. */
859#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
860#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
861/** Bit 10 - FnV - FAR not Valid. */
862#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
863#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
864/** Bit 11 - 12 - LST - Load/Store Type. */
865#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
866#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
867/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
868#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
869#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
870/** Bit 14 - AR - Acquire/Release semantics. */
871#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
872#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
873/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
874#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
875#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
876/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
877#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
878 | RT_BIT_32(19) | RT_BIT_32(20))
879#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
880/** Bit 21 - SSE - Syndrome Sign Extend. */
881#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
882#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
883/** Bit 22 - 23 - SAS - Syndrome Access Size. */
884#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
885#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
886/** Bit 24 - ISV - Instruction Syndrome Valid. */
887#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
888#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
889/** @} */
890
891
892/** @name Data Fault Status Code (DFSC).
893 * @{ */
894/** Address size fault, level 0 of translation or translation table base register. */
895#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
896/** Address size fault, level 1. */
897#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
898/** Address size fault, level 2. */
899#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
900/** Address size fault, level 3. */
901#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
902/** Translation fault, level 0. */
903#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
904/** Translation fault, level 1. */
905#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
906/** Translation fault, level 2. */
907#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
908/** Translation fault, level 3. */
909#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
910/** FEAT_LPA2 - Access flag fault, level 0. */
911#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
912/** Access flag fault, level 1. */
913#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
914/** Access flag fault, level 2. */
915#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
916/** Access flag fault, level 3. */
917#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
918/** FEAT_LPA2 - Permission fault, level 0. */
919#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
920/** Permission fault, level 1. */
921#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
922/** Permission fault, level 2. */
923#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
924/** Permission fault, level 3. */
925#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
926/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
927#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
928/** FEAT_MTE2 - Synchronous Tag Check Fault. */
929#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
930/** @todo Do the rest (lazy developer). */
931/** @} */
932
933
934/** @name SAS encoding.
935 * @{ */
936/** Byte access. */
937#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
938/** Halfword access (uint16_t). */
939#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
940/** Word access (uint32_t). */
941#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
942/** Doubleword access (uint64_t). */
943#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
944/** @} */
945
946
947/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
948 * @{ */
949/** Bit 0 - Direction flag. */
950#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
951#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
952/** Bit 1 - 4 - CRm value from the instruction. */
953#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
954 | RT_BIT_32(4))
955#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
956/** Bit 5 - 9 - Rt value from the instruction. */
957#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
958 | RT_BIT_32(8) | RT_BIT_32(9))
959#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
960/** Bit 10 - 13 - CRn value from the instruction. */
961#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
962 | RT_BIT_32(13))
963#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
964/** Bit 14 - 16 - Op2 value from the instruction. */
965#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
966#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
967/** Bit 17 - 19 - Op2 value from the instruction. */
968#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
969#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
970/** Bit 20 - 21 - Op0 value from the instruction. */
971#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
972#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
973/** Bit 22 - 24 - Reserved. */
974#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
975/** @} */
976
977
978/** @name ISS encoding for trapped HVC instruction exceptions.
979 * @{ */
980/** Bit 0 - 15 - imm16 value of the instruction. */
981#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
982#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
983/** @} */
984
985
986/** @name TCR_EL1 - Translation Control Register (EL1)
987 * @{
988 */
989/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
990#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
991 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
992#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
993/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
994#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
995#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
996/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
997#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
998#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
999/** Non cacheable. */
1000# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
1001/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1002# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
1003/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1004# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
1005/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1006# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
1007/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1008#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
1009#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
1010/** Non cacheable. */
1011# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
1012/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1013# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
1014/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1015# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
1016/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1017# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
1018/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
1019#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
1020#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
1021/** Non shareable. */
1022# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
1023/** Invalid value. */
1024# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
1025/** Outer Shareable. */
1026# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
1027/** Inner Shareable. */
1028# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
1029/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
1030#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15))
1031#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
1032/** Invalid granule size. */
1033# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
1034/** 16KiB granule size. */
1035# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
1036/** 4KiB granule size. */
1037# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
1038/** 64KiB granule size. */
1039# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
1040/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
1041#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
1042 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
1043#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
1044/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
1045#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
1046#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
1047/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
1048#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
1049#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
1050/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1051#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
1052#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
1053/** Non cacheable. */
1054# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
1055/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1056# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
1057/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1058# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
1059/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1060# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
1061/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1062#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
1063#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
1064/** Non cacheable. */
1065# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
1066/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1067# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
1068/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1069# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
1070/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1071# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
1072/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
1073#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
1074#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
1075/** Non shareable. */
1076# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
1077/** Invalid value. */
1078# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
1079/** Outer Shareable. */
1080# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
1081/** Inner Shareable. */
1082# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
1083/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
1084#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
1085#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
1086/** Invalid granule size. */
1087# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
1088/** 16KiB granule size. */
1089# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
1090/** 4KiB granule size. */
1091# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
1092/** 64KiB granule size. */
1093# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
1094/** Bit 32 - 34 - Intermediate Physical Address Size. */
1095#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
1096#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
1097/** IPA - 32 bits, 4GiB. */
1098# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
1099/** IPA - 36 bits, 64GiB. */
1100# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
1101/** IPA - 40 bits, 1TiB. */
1102# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
1103/** IPA - 42 bits, 4TiB. */
1104# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
1105/** IPA - 44 bits, 16TiB. */
1106# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
1107/** IPA - 48 bits, 256TiB. */
1108# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
1109/** IPA - 52 bits, 4PiB. */
1110# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
1111/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
1112#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
1113#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
1114/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
1115#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
1116#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
1117/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
1118#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
1119#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
1120/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
1121#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
1122#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
1123/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
1124#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
1125#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
1126/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
1127#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
1128#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
1129/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
1130#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
1131#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
1132/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
1133#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
1134#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
1135/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
1136#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
1137#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
1138/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
1139#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
1140#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
1141/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
1142#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
1143#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
1144/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
1145#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
1146#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
1147/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
1148#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
1149#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
1150/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
1151#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1152#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1153/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1154#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1155#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1156/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1157#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1158#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1159/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1160#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1161#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1162/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1163#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1164#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1165/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1166#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1167#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1168/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1169#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1170#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1171/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1172#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1173#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1174/** Bit 57 - TCMA0 */
1175#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1176#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1177/** Bit 58 - TCMA1 */
1178#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1179#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1180/** Bit 59 - Data Sharing(?). */
1181#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1182#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1183/** @} */
1184
1185
1186/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1187 * @{
1188 */
1189/** Bit 0 - Common not Private (FEAT_TTCNP). */
1190#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1191#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1192/** Bit 1 - 47 - Translation table base address. */
1193#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1194#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1)
1195/** Bit 48 - 63 - ASID. */
1196#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1197#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1198/** @} */
1199
1200
1201/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1202 * @{ */
1203/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1204#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1205#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1206#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1207/** @} */
1208
1209
1210/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1211 * @{ */
1212/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1213#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1214#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1215#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1216/** @} */
1217
1218
1219/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1220 * @{ */
1221/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1222#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1223#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1224#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1225/** @} */
1226
1227
1228/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1229 * @{ */
1230/** Bit 0 - Common Binary Pointer Register - RW. */
1231#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1232#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1233/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1234#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1235#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1236/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1237#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1238#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1239/** Bit 8 - 10 - Priority bits - RO. */
1240#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1241#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1242/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1243#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1244#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1245/** INTIDS are 16-bit wide. */
1246# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1247/** INTIDS are 24-bit wide. */
1248# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1249/** Bit 14 - SEI Supported - RO. */
1250#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1251#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1252/** Bit 15 - Affinity 3 Valid - RO. */
1253#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1254#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1255/** Bit 18 - Range Selector Support - RO. */
1256#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1257#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1258/** Bit 19 - Extended INTID range supported - RO. */
1259#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1260#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1261/** All RW bits. */
1262#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1263/** All RO bits (including Res0). */
1264#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1265/** @} */
1266
1267
1268/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1269 * @{ */
1270/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1271#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1272#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1273/** @} */
1274
1275
1276/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1277 * @{ */
1278/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1279#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1280#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1281/** @} */
1282
1283
1284/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1285 * @{ */
1286/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1287#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1288#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1289/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1290#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1291#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1292/** Bit 24 - 27 - The INTID of the SGI. */
1293#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1294#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1295/* Bit 28 - 31 - Reserved. */
1296/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1297#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1298#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1299/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1300#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1301#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1302/* Bit 41 - 43 - Reserved. */
1303/** Bit 44 - 47 - Range selector. */
1304#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1305#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1306/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1307#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1308#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1309/* Bit 56 - 63 - Reserved. */
1310/** @} */
1311
1312
1313/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1314 * @{ */
1315/** Bit 0 - Enables the timer. */
1316#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1317#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1318/** Bit 1 - Timer interrupt mask bit. */
1319#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1320#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1321/** Bit 2 - Timer status bit. */
1322#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1323#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1324/** @} */
1325
1326
1327/** @name OSLAR_EL1 - OS Lock Access Register.
1328 * @{ */
1329/** Bit 0 - The OS Lock status bit. */
1330#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1331#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1332/** @} */
1333
1334
1335/** @name OSLSR_EL1 - OS Lock Status Register.
1336 * @{ */
1337/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1338#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1339#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1340/** Bit 1 - The OS Lock status bit. */
1341#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1342#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1343/** Bit 2 - Not 32-bit access. */
1344#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1345#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1346/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1347#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1348#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1349/** @} */
1350
1351
1352/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1353 * @{ */
1354/* Bit 0 - 3 - Reserved. */
1355/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1356#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1357#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1358/** No AES instructions implemented. */
1359# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1360/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1361# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1362/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1363# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1364/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1365#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1366#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1367/** No SHA1 instructions implemented. */
1368# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1369/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1370# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1371/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1372#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1373#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1374/** No SHA2 instructions implemented. */
1375# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1376/** SHA256 instructions implemented (FEAT_SHA256). */
1377# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1378/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1379# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1380/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1381#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1382#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1383/** No CRC32 instructions implemented. */
1384# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1385/** CRC32 instructions implemented (FEAT_CRC32). */
1386# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1387/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1388#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1389#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1390/** No Atomic instructions implemented. */
1391# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1392/** Atomic instructions implemented (FEAT_LSE). */
1393# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1394/** Bit 24 - 27 - Indicates support for TME instructions. */
1395#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1396#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1397/** TME instructions are not implemented. */
1398# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1399/** TME instructions are implemented. */
1400# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1401/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1402#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1403#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1404/** No RDMA instructions implemented. */
1405# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1406/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1407# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1408/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1409#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1410#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1411/** No SHA3 instructions implemented. */
1412# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1413/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1414# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1415/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1416#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1417#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1418/** No SM3 instructions implemented. */
1419# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1420/** SM3 instructions implemented (FEAT_SM3). */
1421# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1422/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1423#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1424#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1425/** No SM4 instructions implemented. */
1426# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1427/** SM4 instructions implemented (FEAT_SM4). */
1428# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1429/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1430#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1431#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1432/** No Dot Product instructions implemented. */
1433# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1434/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1435# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1436/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1437#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1438#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1439/** FMLAL and FMLSL instructions are not implemented. */
1440# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1441/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1442# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1443/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1444#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1445#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1446/** No flag manipulation instructions implemented. */
1447# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1448/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1449# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1450/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1451# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1452/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1453#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1454#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1455/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1456# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1457/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1458# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1459/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1460# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1461/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1462#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1463#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1464/** No Random Number instructions implemented. */
1465# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1466/** RNDR and RDNRRS registers are implemented . */
1467# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1468/** @} */
1469
1470
1471/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1472 * @{ */
1473/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1474#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1475#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1476/** DC CVAP not supported. */
1477# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1478/** DC CVAP supported (FEAT_DPB). */
1479# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1480/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1481# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1482/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1483#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1484#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1485/** Address Authentication using the QARMA5 algorithm is not implemented. */
1486# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1487/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1488# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1489/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1490# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1491/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1492# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1493/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1494# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1495/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1496# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1497/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1498#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1499#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1500/** Address Authentication using the QARMA5 algorithm is not implemented. */
1501# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1502/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1503# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1504/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1505# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1506/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1507# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1508/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1509# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1510/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1511# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1512/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1513#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1514#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1515/** No FJCVTZS instruction implemented. */
1516# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1517/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1518# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1519/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1520#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1521#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1522/** No FCMLA and FCADD instructions implemented. */
1523# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1524/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1525# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1526/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1527#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1528#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1529/** No RCpc instructions implemented. */
1530# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1531/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1532# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1533/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1534# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1535/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1536#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1537#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1538/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1539# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1540/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1541# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1542/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1543#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1544#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1545/** Generic Authentication using an implementation defined algorithm is not implemented. */
1546# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1547/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1548# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1549/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1550#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1551#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1552/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1553# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1554/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1555# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1556/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1557#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1558#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1559/** No SB instructions implemented. */
1560# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1561/** SB instructions implemented (FEAT_SB). */
1562# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1563/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1564#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1565#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1566/** Prediction invalidation instructions are not implemented. */
1567# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1568/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1569# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1570/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1571#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1572#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1573/** BFloat16 instructions are not implemented. */
1574# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1575/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1576# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1577/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1578# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1579/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1580#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1581#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1582/** Data Gathering Hint instructions are not implemented. */
1583# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1584/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1585# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1586/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1587#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1588#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1589/** No Int8 matrix multiplication instructions implemented. */
1590# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1591/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1592# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1593/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1594#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1595#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1596/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1597# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1598/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1599# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1600/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1601#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1602#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1603/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1604# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1605/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1606# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1607/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1608# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1609/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1610# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1611/** @} */
1612
1613
1614/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1615 * @{ */
1616/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1617#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1618#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1619/** WFET and WFIT are not supported. */
1620# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1621/** WFET and WFIT are supported (FEAT_WFxT). */
1622# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1623/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1624#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1625#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1626/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1627# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1628/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1629# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1630/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1631#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1632#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1633/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1634# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1635/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1636# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1637/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1638#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1639#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1640/** Address Authentication using the QARMA3 algorithm is not implemented. */
1641# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1642/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1643# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1644/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1645# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1646/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1647# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1648/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1649# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1650/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1651# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1652/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1653#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1654#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1655/** No Memory Copy and Memory Set instructions implemented. */
1656# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1657/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1658# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1659/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1660#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1661#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1662/** BC instruction is not implemented. */
1663# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1664/** BC instruction is implemented (FEAT_HBC). */
1665# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1666/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1667#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1668#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1669/** ConstPACField() returns FALSE. */
1670# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1671/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1672# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1673/* Bit 28 - 63 - Reserved. */
1674/** @} */
1675
1676
1677/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1678 * @{ */
1679/** Bit 0 - 3 - EL0 Exception level handling. */
1680#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1681#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1682/** EL0 can be executed in AArch64 state only. */
1683# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1684/** EL0 can be executed in AArch64 and AArch32 state. */
1685# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1686/** Bit 4 - 7 - EL1 Exception level handling. */
1687#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1688#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1689/** EL1 can be executed in AArch64 state only. */
1690# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1691/** EL1 can be executed in AArch64 and AArch32 state. */
1692# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1693/** Bit 8 - 11 - EL2 Exception level handling. */
1694#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1695#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1696/** EL2 is not implemented. */
1697# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1698/** EL2 can be executed in AArch64 state only. */
1699# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1700/** EL2 can be executed in AArch64 and AArch32 state. */
1701# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1702/** Bit 12 - 15 - EL3 Exception level handling. */
1703#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1704#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1705/** EL3 is not implemented. */
1706# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1707/** EL3 can be executed in AArch64 state only. */
1708# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1709/** EL3 can be executed in AArch64 and AArch32 state. */
1710# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1711/** Bit 16 - 19 - Floating-point support. */
1712#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1713#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1714/** Floating-point is implemented and support single and double precision. */
1715# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1716/** Floating-point is implemented and support single, double and half precision. */
1717# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1718/** Floating-point is not implemented. */
1719# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1720/** Bit 20 - 23 - Advanced SIMD support. */
1721#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1722#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1723/** Advanced SIMD is implemented and support single and double precision. */
1724# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1725/** Advanced SIMD is implemented and support single, double and half precision. */
1726# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1727/** Advanced SIMD is not implemented. */
1728# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1729/** Bit 24 - 27 - System register GIC CPU interface support. */
1730#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1731#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1732/** GIC CPU interface system registers are not implemented. */
1733# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1734/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1735# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1736/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1737# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1738/** Bit 28 - 31 - RAS Extension version. */
1739#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1740#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1741/** No RAS extension. */
1742# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1743/** RAS Extension implemented. */
1744# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1745/** FEAT_RASv1p1 implemented. */
1746# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1747/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1748#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1749#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1750/** SVE is not supported. */
1751# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1752/** SVE is supported. */
1753# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1754/** Bit 36 - 39 - Secure EL2 support. */
1755#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1756#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1757/** Secure EL2 is not supported. */
1758# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1759/** Secure EL2 is implemented. */
1760# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1761/** Bit 40 - 43 - MPAM support. */
1762#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1763#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
1764/** MPAM extension major version number is 0. */
1765# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
1766/** MPAM extension major version number is 1. */
1767# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
1768/** Bit 44 - 47 - Activity Monitor Extension support. */
1769#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1770#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
1771/** Activity Monitor extension is not implemented. */
1772# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
1773/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
1774# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
1775/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
1776# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
1777/** Bit 48 - 51 - Data Independent Timing support. */
1778#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1779#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
1780/** AArch64 does not guarantee constant execution time of any instructions. */
1781# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
1782/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
1783# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
1784/** Bit 52 - 55 - Realm Management Extension support. */
1785#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1786#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
1787/** Realm Management Extension not implemented. */
1788# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
1789/** RMEv1 is implemented (FEAT_RME). */
1790# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
1791/** Bit 56 - 59 - Speculative use out of context branch targets support. */
1792#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1793#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
1794/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
1795# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
1796/** FEAT_CSV2 is implemented. */
1797# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
1798/** FEAT_CSV2_2 is implemented. */
1799# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
1800/** FEAT_CSV2_3 is implemented. */
1801# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
1802/** Bit 60 - 63 - Speculative use of faulting data support. */
1803#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1804#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
1805/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
1806# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
1807/** FEAT_CSV3 is supported . */
1808# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
1809/** @} */
1810
1811
1812/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
1813 * @{ */
1814/** Bit 0 - 3 - Branch Target Identification support. */
1815#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1816#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
1817/** The Branch Target Identification mechanism is not implemented. */
1818# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
1819/** The Branch Target Identifcation mechanism is implemented. */
1820# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
1821/** Bit 4 - 7 - Speculative Store Bypassing control support. */
1822#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1823#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
1824/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
1825# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
1826/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
1827# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
1828/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
1829 * to directly read and write the PSTATE.SSBS field. */
1830# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
1831/** Bit 8 - 11 - Memory Tagging Extension support. */
1832#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1833#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
1834/** MTE is not implemented. */
1835# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
1836/** Instruction only Memory Tagging Extensions implemented. */
1837# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
1838/** Full Memory Tagging Extension implemented. */
1839# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
1840/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
1841# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
1842/** Bit 12 - 15 - RAS Extension fractional field. */
1843#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1844#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
1845/** RAS Extension is implemented. */
1846# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
1847/** FEAT_RASv1p1 is implemented. */
1848# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
1849/** Bit 16 - 19 - MPAM minor version number. */
1850#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1851#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
1852/** The minor version of number of the MPAM extension is 0. */
1853# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
1854/** The minor version of number of the MPAM extension is 1. */
1855# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
1856/* Bit 20 - 23 - Reserved. */
1857/** Bit 24 - 27 - Scalable Matrix Extension support. */
1858#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1859#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
1860/** Scalable Matrix Extensions are not implemented. */
1861# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
1862/** Scalable Matrix Extensions are implemented (FEAT_SME). */
1863# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
1864/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
1865# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
1866/** Bit 28 - 31 - Random Number trap to EL3 support. */
1867#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1868#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
1869/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
1870# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
1871/** Trapping of RNDR and RDNRRS to EL3 is supported. */
1872# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
1873/** Bit 32 - 35 - CSV2 fractional field. */
1874#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1875#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
1876/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
1877# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
1878/** FEAT_CSV2_1p1 is implemented. */
1879# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
1880/** FEAT_CSV2_1p2 is implemented. */
1881# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
1882/** Bit 36 - 39 - Non-maskable Interrupt support. */
1883#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1884#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
1885/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
1886# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
1887/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
1888# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
1889/** @} */
1890
1891
1892/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
1893 * @{ */
1894/** Bit 0 - 3 - Physical Address range supported. */
1895#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1896#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
1897/** Physical Address range is 32 bits, 4GiB. */
1898# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
1899/** Physical Address range is 36 bits, 64GiB. */
1900# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
1901/** Physical Address range is 40 bits, 1TiB. */
1902# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
1903/** Physical Address range is 42 bits, 4TiB. */
1904# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
1905/** Physical Address range is 44 bits, 16TiB. */
1906# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
1907/** Physical Address range is 48 bits, 256TiB. */
1908# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
1909/** Physical Address range is 52 bits, 4PiB. */
1910# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
1911/** Bit 4 - 7 - Number of ASID bits. */
1912#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1913#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
1914/** ASID bits is 8. */
1915# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
1916/** ASID bits is 16. */
1917# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
1918/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
1919#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1920#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
1921/** No mixed-endian support. */
1922# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
1923/** Mixed-endian supported. */
1924# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
1925/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
1926#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1927#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
1928/** No distinction between Secure and Non-secure Memory supported. */
1929# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
1930/** Distinction between Secure and Non-secure Memory supported. */
1931# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
1932/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
1933#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1934#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
1935/** No mixed-endian support at EL0. */
1936# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
1937/** Mixed-endian support at EL0. */
1938# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
1939/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
1940#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1941#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
1942/** 16KiB granule size not supported. */
1943# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
1944/** 16KiB granule size is supported. */
1945# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
1946/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1947# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
1948/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
1949#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1950#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
1951/** 64KiB granule supported. */
1952# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
1953/** 64KiB granule not supported. */
1954# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
1955/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
1956#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1957#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
1958/** 4KiB granule supported. */
1959# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
1960/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1961# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
1962/** 4KiB granule not supported. */
1963# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
1964/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
1965#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1966#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
1967/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
1968# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
1969/** 16KiB granule not supported at stage 2. */
1970# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
1971/** 16KiB granule supported at stage 2. */
1972# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
1973/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1974# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
1975/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
1976#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1977#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
1978/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
1979# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
1980/** 64KiB granule not supported at stage 2. */
1981# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
1982/** 64KiB granule supported at stage 2. */
1983# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
1984/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1985#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1986#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
1987/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
1988# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
1989/** 4KiB granule not supported at stage 2. */
1990# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
1991/** 4KiB granule supported at stage 2. */
1992# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
1993/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1994# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
1995/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
1996#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1997#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
1998/** All exception entries and exits are context synchronization events. */
1999# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
2000/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
2001# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
2002/* Bit 48 - 55 - Reserved. */
2003/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
2004#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2005#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
2006/** Fine-grained trap controls are not implemented. */
2007# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
2008/** Fine-grained trap controls are implemented (FEAT_FGT). */
2009# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
2010/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
2011#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2012#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
2013/** Enhanced Counter Virtualization is not implemented. */
2014# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
2015/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
2016# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
2017/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
2018# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
2019/** @} */
2020
2021
2022/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
2023 * @{ */
2024/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
2025#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2026#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
2027/** Hardware update of the Access flag and dirty state are not supported. */
2028# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
2029/** Support for hardware update of the Access flag for Block and Page descriptors. */
2030# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
2031/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
2032# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
2033/** Bit 4 - 7 - EL1 Exception level handling. */
2034#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2035#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
2036/** VMID bits is 8. */
2037# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
2038/** VMID bits is 16 (FEAT_VMID16). */
2039# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
2040/** Bit 8 - 11 - Virtualization Host Extensions support. */
2041#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2042#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
2043/** Virtualization Host Extensions are not supported. */
2044# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
2045/** Virtualization Host Extensions are supported. */
2046# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
2047/** Bit 12 - 15 - Hierarchical Permission Disables. */
2048#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2049#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
2050/** Disabling of hierarchical controls not supported. */
2051# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
2052/** Disabling of hierarchical controls supported (FEAT_HPDS). */
2053# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
2054/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
2055# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
2056/** Bit 16 - 19 - LORegions support. */
2057#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2058#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
2059/** LORegions not supported. */
2060# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
2061/** LORegions supported. */
2062# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
2063/** Bit 20 - 23 - Privileged Access Never support. */
2064#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2065#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
2066/** PAN not supported. */
2067# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
2068/** PAN supported (FEAT_PAN). */
2069# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
2070/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
2071# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
2072/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
2073# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
2074/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
2075#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2076#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
2077/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
2078# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
2079/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
2080# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
2081/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
2082#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2083#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
2084/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
2085# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
2086/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
2087# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
2088/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
2089#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2090#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
2091/** Configurable delayed trapping of WFE is not supported. */
2092# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
2093/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
2094# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
2095/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
2096#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2097#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
2098/** Enhanced Translation Synchronization is not supported. */
2099# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
2100/** Enhanced Translation Synchronization is implemented. */
2101# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
2102/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2103#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2104#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
2105/** HCRX_EL2 and its associated EL3 trap are not supported. */
2106# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
2107/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
2108# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
2109/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
2110#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2111#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
2112/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
2113# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
2114/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
2115# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
2116/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
2117#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2118#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
2119/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
2120# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
2121/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
2122# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
2123/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
2124#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2125#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
2126/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
2127# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
2128/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
2129# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
2130/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
2131#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2132#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
2133/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
2134# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
2135/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
2136# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
2137/* Bit 60 - 63 - Reserved. */
2138/** @} */
2139
2140
2141/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
2142 * @{ */
2143/** Bit 0 - 3 - Indicates support for Common not Private translations. */
2144#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2145#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
2146/** Common not Private translations are not supported. */
2147# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
2148/** Support for Common not Private translations (FEAT_TTNCP). */
2149# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
2150/** Bit 4 - 7 - Indicates support for User Access Override. */
2151#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2152#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2153/** User Access Override is not supported. */
2154# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2155/** User Access Override is supported (FEAT_UAO). */
2156# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2157/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2158#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2159#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2160/** LSMAOE and nTLSMD bits are not supported. */
2161# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2162/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2163# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2164/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2165#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2166#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2167/** IESB bit is not supported. */
2168# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2169/** IESB bit is supported (FEAT_IESB). */
2170# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2171/** Bit 16 - 19 - Indicates support for larger virtual address. */
2172#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2173#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2174/** Virtual address range is 48 bits. */
2175# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2176/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2177# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2178/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2179#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2180#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2181/** CCSIDR_EL1 register format is 32-bit. */
2182# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2183/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2184# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2185/** Bit 24 - 27 - Indicates support for nested virtualization. */
2186#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2187#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2188/** Nested virtualization is not supported. */
2189# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2190/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2191# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2192/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2193# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2194/** Bit 28 - 31 - Indicates support for small translation tables. */
2195#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2196#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2197/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2198# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2199/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2200# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2201/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2202#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2203#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2204/** Unaligned single-copy atomicity and atomic functions are not supported. */
2205# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2206/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2207# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2208/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2209#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2210#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2211/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2212# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2213/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2214# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2215/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2216#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2217#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2218/** HCR_EL2.FWB bit is not supported. */
2219# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2220/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2221# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2222/* Bit 44 - 47 - Reserved. */
2223/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2224#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2225#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2226/** TLB maintenance instructions by address have bits [47:44] Res0. */
2227# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2228/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2229# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2230/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2231 * changing block size for a translation. */
2232#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2233#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2234/** Level 0 support for changing block size is supported (FEAT_BBM). */
2235# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2236/** Level 1 support for changing block size is supported (FEAT_BBM). */
2237# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2238/** Level 2 support for changing block size is supported (FEAT_BBM). */
2239# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2240/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2241#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2242#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2243/** Enhanced Virtualization Traps are not supported. */
2244# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2245/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2246# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2247/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2248# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2249/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2250#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2251#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2252/** E0PDx mechanism is not supported. */
2253# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2254/** E0PDx mechanism is supported (FEAT_E0PD). */
2255# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2256/** @} */
2257
2258
2259/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2260 * @{ */
2261/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2262#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2263#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2264/** Armv8 debug architecture version. */
2265# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2266/** Armv8 debug architecture version with virtualization host extensions. */
2267# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2268/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2269# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2270/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2271# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2272/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2273# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2274/** Bit 4 - 7 - Indicates trace support. */
2275#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2276#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2277/** Trace unit System registers not implemented. */
2278# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2279/** Trace unit System registers supported. */
2280# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2281/** Bit 8 - 11 - Performance Monitors Extension version. */
2282#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2283#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2284/** Performance Monitors Extension not supported. */
2285# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2286/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2287# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2288/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2289# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2290/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2291# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2292/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2293# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2294/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2295# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2296/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2297# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2298/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2299#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2300#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2301/* Bit 16 - 19 - Reserved 0. */
2302/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2303#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2304#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2305/* Bit 24 - 27 - Reserved 0. */
2306/** Bit 28 - 31 - Number of context-aware breakpoints. */
2307#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2308#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2309/** Bit 32 - 35 - Statistical Profiling Extension version. */
2310#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2311#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2312/** Statistical Profiling Extension not implemented. */
2313# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2314/** Statistical Profiling Extension supported (FEAT_SPE). */
2315# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2316/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2317# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2318/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2319# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2320/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2321# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2322/** Bit 36 - 39 - OS Double Lock implemented. */
2323#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2324#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2325/** OS Double Lock is not implemented. */
2326# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2327/** OS Double Lock is supported (FEAT_DoubleLock). */
2328# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2329/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2330#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2331#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2332/** Armv8.4 self-hosted Trace Extension not implemented. */
2333# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2334/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2335# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2336/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2337#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2338#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2339/** Trace Buffer Extension is not implemented. */
2340# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2341/** Trace Buffer Extension is supported (FEAT_TRBE). */
2342# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2343/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2344#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2345#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2346/** Multi-threaded PMU extension is not implemented. */
2347# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2348/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2349# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2350/** Multi-threaded PMU extension is not implemented. */
2351# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2352/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2353#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2354#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2355/** Branch Record Buffer extension is not implemented. */
2356# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2357/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2358# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2359/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2360# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2361/* Bit 56 - 59 - Reserved. */
2362/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2363#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2364#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2365/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2366# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2367/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2368# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2369/** @} */
2370
2371
2372/** @name FPCR - AArch64 Floating Point Control Register.
2373 * @{ */
2374/** Bit 0 - Flush Inputs to Zero when FEAT_AFP is supported. */
2375#define ARMV8_FPCR_FIZ RT_BIT_64(0)
2376/** Bit 1 - Alternate Handling of floating-point numbers when FEAT_AFP is supported. */
2377#define ARMV8_FPCR_AH RT_BIT_64(1)
2378/** Bit 2 - Controls how the output elements other than the lowest element of the vector are determined for
2379 * Advanced SIMD scalar instructions, when FEAT_AFP is supported. */
2380#define ARMV8_FPCR_NEP RT_BIT_64(2)
2381/* Bit 3 - 7 - Reserved.*/
2382/** Bit 8 - Invalid Operation floating-point exception trap enable. */
2383#define ARMV8_FPCR_IOE RT_BIT_64(8)
2384/** Bit 9 - Divide by Zero floating-point exception trap enable. */
2385#define ARMV8_FPCR_DZE RT_BIT_64(9)
2386/** Bit 10 - Overflow floating-point exception trap enable. */
2387#define ARMV8_FPCR_OFE RT_BIT_64(10)
2388/** Bit 11 - Underflow floating-point exception trap enable. */
2389#define ARMV8_FPCR_UFE RT_BIT_64(11)
2390/** Bit 12 - Inexact floating-point exception trap enable. */
2391#define ARMV8_FPCR_IXE RT_BIT_64(12)
2392/** Bit 13 - Controls numeric behavior of BFloat16 dot productions calculations performed,
2393 * supported when FEAT_EBF16 is supported. */
2394#define ARMV8_FPCR_EBF RT_BIT_64(13)
2395/* Bit 14 - Reserved */
2396/** Bit 15 - Input Denormal floating-point exception trap enable. */
2397#define ARMV8_FPCR_IDE RT_BIT_64(15)
2398/* Bit 16 - 18 - Reserved for AArch64 (Len field for AArch32). */
2399/** Bit 19 - Flushing denormalized numbers to zero control bit on half-precision data-processing instructions,
2400 * available when FEAT_FP16 is supported. */
2401#define ARMV8_FPCR_FZ16 RT_BIT_64(19)
2402/* Bit 20 - 21 - Reserved for AArch64 (Stride field dor AArch32). */
2403/** Bit 22 - 23 - Rounding Mode control field. */
2404#define ARMV8_FPCR_RMODE_MASK (RT_BIT_64(22) | RT_BIT_64(23))
2405#define ARMV8_FPCR_RMODE_SHIFT 22
2406/** Round to Nearest (RN) mode. */
2407# define ARMV8_FPCR_RMODE_RN 0
2408/** Round towards Plus Infinity (RP) mode. */
2409# define ARMV8_FPCR_RMODE_RP 1
2410/** Round towards Minus Infinity (RM) mode. */
2411# define ARMV8_FPCR_RMODE_RP 2
2412/** Round towards Zero (RZ) mode. */
2413# define ARMV8_FPCR_RMODE_RZ 3
2414/** Bit 24 - Flushing denormalized numbers to zero control bit. */
2415#define ARMV8_FPCR_FZ RT_BIT_64(24)
2416/** Bit 25 - Default NaN use for NaN propagation. */
2417#define ARMV8_FPCR_DN RT_BIT_64(25)
2418/** Bit 26 - Alternative half-precision control bit. */
2419#define ARMV8_FPCR_AHP RT_BIT_64(26)
2420/* Bit 27 - 63 - Reserved. */
2421/** @} */
2422
2423
2424/** @name FPSR - AArch64 Floating Point Status Register.
2425 * @{ */
2426/** Bit 0 - Invalid Operation cumulative floating-point exception bit. */
2427#define ARMV8_FPSR_IOC RT_BIT_64(0)
2428/** Bit 1 - Divide by Zero cumulative floating-point exception bit. */
2429#define ARMV8_FPSR_DZC RT_BIT_64(1)
2430/** Bit 2 - Overflow cumulative floating-point exception bit. */
2431#define ARMV8_FPSR_OFC RT_BIT_64(2)
2432/** Bit 3 - Underflow cumulative floating-point exception bit. */
2433#define ARMV8_FPSR_OFC RT_BIT_64(3)
2434/** Bit 4 - Inexact cumulative floating-point exception bit. */
2435#define ARMV8_FPSR_IXC RT_BIT_64(4)
2436/* Bit 5 - 6 - Reserved. */
2437/** Bit 7 - Input Denormal cumulative floating-point exception bit. */
2438#define ARMV8_FPSR_IDC RT_BIT_64(7)
2439/* Bit 8 - 26 - Reserved. */
2440/** Bit 27 - Cumulative saturation bit, Advanced SIMD only. */
2441#define ARMV8_FPSR_QC RT_BIT_64(27)
2442/* Bit 28 - 31 - NZCV bits for AArch32 floating point operations. */
2443/* Bit 32 - 63 - Reserved. */
2444/** @} */
2445
2446
2447#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
2448/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2449 * @ingroup grp_rt_armv8
2450 *
2451 * A few inlined functions and macros for assiting in encoding common ARMv8
2452 * instructions.
2453 *
2454 * @{ */
2455
2456/** A64: Official NOP instruction. */
2457#define ARMV8_A64_INSTR_NOP UINT32_C(0xd503201f)
2458/** A64: Return instruction. */
2459#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2460/** A64: Return instruction with LR pointer authentication using SP and key A. */
2461#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2462/** A64: Return instruction with LR pointer authentication using SP and key B. */
2463#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2464/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2465#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2466/** A64: Insert pointer authentication code into LR using SP and key B. */
2467#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2468/** A64: Insert pointer authentication code into LR using XZR and key B. */
2469#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2470/** A64: Invert the carry flag (PSTATE.C). */
2471#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
2472
2473
2474typedef enum
2475{
2476 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
2477 * and update the register. */
2478 kArm64InstrStLdPairType_PostIndex = 1,
2479 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2480 * but don't update the register. */
2481 kArm64InstrStLdPairType_Signed = 2,
2482 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2483 * and update the register. */
2484 kArm64InstrStLdPairType_PreIndex = 3
2485} ARM64INSTRSTLDPAIRTYPE;
2486
2487/**
2488 * A64: Encodes either stp (store register pair) or ldp (load register pair).
2489 *
2490 * @returns The encoded instruction.
2491 * @param fLoad true for ldp, false of stp.
2492 * @param u2Opc When @a fSimdFp is @c false:
2493 * - 0 for 32-bit GPRs (Wt).
2494 * - 1 for encoding stgp or ldpsw.
2495 * - 2 for 64-bit GRPs (Xt).
2496 * - 3 illegal.
2497 * When @a fSimdFp is @c true:
2498 * - 0 for 32-bit SIMD&FP registers (St).
2499 * - 1 for 64-bit SIMD&FP registers (Dt).
2500 * - 2 for 128-bit SIMD&FP regsiters (Qt).
2501 * @param enmType The instruction variant wrt addressing and updating of the
2502 * addressing register.
2503 * @param iReg1 The first register to store/load.
2504 * @param iReg2 The second register to store/load.
2505 * @param iBaseReg The base register to use when addressing. SP is allowed.
2506 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
2507 * will be multiplied by the register size.
2508 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
2509 * stgp/ldpsw instructions.
2510 */
2511DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
2512 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2513 bool fSimdFp = false)
2514{
2515 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
2516 return (u2Opc << 30)
2517 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
2518 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
2519 | ((uint32_t)enmType << 23)
2520 | ((uint32_t)fLoad << 22)
2521 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
2522 | (iReg2 << 10)
2523 | (iBaseReg << 5)
2524 | iReg1;
2525}
2526
2527
2528/** A64: ldp x1, x2, [x3] */
2529DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2530 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2531 bool f64Bit = true)
2532{
2533 return Armv8A64MkInstrStLdPair(true /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2534}
2535
2536
2537/** A64: stp x1, x2, [x3] */
2538DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2539 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2540 bool f64Bit = true)
2541{
2542 return Armv8A64MkInstrStLdPair(false /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2543}
2544
2545
2546typedef enum /* Size VR Opc */
2547{ /* \ | / */
2548 kArmv8A64InstrLdStType_Mask_Size = 0x300,
2549 kArmv8A64InstrLdStType_Mask_VR = 0x010,
2550 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
2551 kArmv8A64InstrLdStType_Shift_Size = 8,
2552 kArmv8A64InstrLdStType_Shift_VR = 4,
2553 kArmv8A64InstrLdStType_Shift_Opc = 0,
2554
2555 kArmv8A64InstrLdStType_St_Byte = 0x000,
2556 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
2557 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
2558 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
2559
2560 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
2561 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
2562 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
2563 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
2564
2565 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
2566 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
2567 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
2568
2569 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
2570 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
2571
2572 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
2573
2574 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
2575 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
2576 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
2577 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
2578
2579 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
2580 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
2581
2582 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
2583 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
2584
2585 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
2586 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
2587
2588} ARMV8A64INSTRLDSTTYPE;
2589/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
2590#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
2591
2592
2593/**
2594 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2595 *
2596 * @returns The encoded instruction.
2597 * @param u32Opcode The base opcode value.
2598 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2599 * @param iReg The register to load into / store.
2600 * @param iBaseReg The base register to use when addressing. SP is allowed.
2601 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2602 */
2603DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
2604 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2605{
2606 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
2607 return u32Opcode
2608 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2609 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2610 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2611 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
2612 | (iBaseReg << 5)
2613 | iReg;
2614}
2615
2616
2617/**
2618 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2619 *
2620 * @returns The encoded instruction.
2621 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2622 * @param iReg The register to load into / store.
2623 * @param iBaseReg The base register to use when addressing. SP is allowed.
2624 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2625 */
2626DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
2627 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2628{
2629 /* 3 2 1 0 */
2630 /* 10987654321098765432109876543210 */
2631 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
2632 enmType, iReg, iBaseReg, i9ImmDisp);
2633}
2634
2635/**
2636 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
2637 *
2638 * @returns The encoded instruction.
2639 * @param enmType The load/store instruction type. Prefech not valid.
2640 * @param iReg The register to load into / store.
2641 * @param iBaseReg The base register to use when addressing. SP is allowed.
2642 * Written back.
2643 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2644 */
2645DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2646 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2647{
2648 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2649 /* 10987654321098765432109876543210 */
2650 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
2651 enmType, iReg, iBaseReg, i9ImmDisp);
2652}
2653
2654/**
2655 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
2656 *
2657 * @returns The encoded instruction.
2658 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2659 * @param iReg The register to load into / store.
2660 * @param iBaseReg The base register to use when addressing. SP is allowed.
2661 * Written back.
2662 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2663 */
2664DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2665 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2666{
2667 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2668 /* 10987654321098765432109876543210 */
2669 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
2670 enmType, iReg, iBaseReg, i9ImmDisp);
2671}
2672
2673/**
2674 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
2675 *
2676 * @returns The encoded instruction.
2677 * @param enmType The load/store instruction type. Prefech not valid,
2678 * nor any SIMD&FP variants.
2679 * @param iReg The register to load into / store.
2680 * @param iBaseReg The base register to use when addressing. SP is allowed.
2681 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2682 */
2683DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
2684 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2685{
2686 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
2687 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
2688 /* 3 2 1 0 */
2689 /* 10987654321098765432109876543210 */
2690 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
2691 enmType, iReg, iBaseReg, i9ImmDisp);
2692}
2693
2694
2695/**
2696 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
2697 *
2698 * @returns The encoded instruction.
2699 * @param enmType The load/store instruction type. Prefech not valid,
2700 * nor any SIMD&FP variants.
2701 * @param iReg The register to load into / store.
2702 * @param iBaseReg The base register to use when addressing. SP is allowed.
2703 * @param u12ImmDisp Addressing displacement, scaled by size.
2704 */
2705DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
2706 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
2707{
2708 Assert(u12ImmDisp < 4096U);
2709 Assert(iReg < 32); /* 3 2 1 0 */
2710 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2711 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
2712 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2713 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2714 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2715 | (u12ImmDisp << 10)
2716 | (iBaseReg << 5)
2717 | iReg;
2718}
2719
2720typedef enum
2721{
2722 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
2723 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
2724 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
2725 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
2726} ARMV8A64INSTRLDSTEXTEND;
2727
2728/**
2729 * A64: Encodes load/store w/ index register.
2730 *
2731 * @returns The encoded instruction.
2732 * @param enmType The load/store instruction type.
2733 * @param iReg The register to load into / store.
2734 * @param iBaseReg The base register to use when addressing. SP is allowed.
2735 * @param iRegIndex The index register.
2736 * @param enmExtend The extending to apply to @a iRegIndex.
2737 * @param fShifted Whether to shift the index. The shift amount corresponds
2738 * to the access size (thus irrelevant for byte accesses).
2739 */
2740DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
2741 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
2742 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
2743 bool fShifted = false)
2744{
2745 Assert(iRegIndex < 32);
2746 Assert(iReg < 32); /* 3 2 1 0 */
2747 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2748 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
2749 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2750 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2751 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2752 | (iRegIndex << 16)
2753 | ((uint32_t)enmExtend << 13)
2754 | ((uint32_t)fShifted << 12)
2755 | (iBaseReg << 5)
2756 | iReg;
2757}
2758
2759typedef enum /* VR Opc */
2760{ /* \ | */
2761 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
2762 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
2763 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
2764 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
2765
2766 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
2767 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
2768 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
2769 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
2770
2771 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
2772 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
2773 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
2774} ARMV8A64INSTRLDRLITTERAL;
2775
2776
2777/**
2778 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
2779 *
2780 * @returns The encoded instruction.
2781 * @param enmType The load instruction type.
2782 * @param iReg The register to load into.
2783 * @param i19Imm The signed immediate value, multiplied by 4 regardless
2784 * of access size.
2785 */
2786DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
2787{
2788 Assert(i19Imm >= -262144 && i19Imm < 262144);
2789 Assert(iReg < 32); /* 3 2 1 0 */
2790 /* 10987654321098765432109876543210 */
2791 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
2792 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
2793 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
2794 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
2795 | iReg;
2796}
2797
2798
2799typedef enum
2800{
2801 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
2802 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
2803 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
2804} ARMV8A64INSTRMOVWIDE;
2805
2806/**
2807 * A64: Encode a move wide immediate instruction.
2808 *
2809 * @returns The encoded instruction.
2810 * @param enmType The load instruction type.
2811 * @param iRegDst The register to mov the immediate into.
2812 * @param uImm16 The immediate value.
2813 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
2814 * half-words to target:
2815 * - 0 for bits 15:00,
2816 * - 1 for bits 31:16,
2817 * - 2 for bits 47:32 (f64Bit=true only),
2818 * - 3 for bits 63:48 (f64Bit=true only).
2819 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
2820 */
2821DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
2822 uint32_t iHalfWord = 0, bool f64Bit = true)
2823{
2824 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
2825 return ((uint32_t)f64Bit << 31)
2826 | ((uint32_t)enmType << 29)
2827 | UINT32_C(0x12800000)
2828 | (iHalfWord << 21)
2829 | (uImm16 << 5)
2830 | iRegDst;
2831}
2832
2833/** A64: Encodes a MOVN instruction.
2834 * @see Armv8A64MkInstrMovWide for parameter details. */
2835DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2836{
2837 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
2838}
2839
2840/** A64: Encodes a MOVZ instruction.
2841 * @see Armv8A64MkInstrMovWide for parameter details. */
2842DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2843{
2844 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
2845}
2846
2847/** A64: Encodes a MOVK instruction.
2848 * @see Armv8A64MkInstrMovWide for parameter details. */
2849DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2850{
2851 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
2852}
2853
2854
2855typedef enum
2856{
2857 kArmv8A64InstrShift_Lsl = 0,
2858 kArmv8A64InstrShift_Lsr,
2859 kArmv8A64InstrShift_Asr,
2860 kArmv8A64InstrShift_Ror
2861} ARMV8A64INSTRSHIFT;
2862
2863
2864/**
2865 * A64: Encodes a logical instruction with a shifted 2nd register operand.
2866 *
2867 * @returns The encoded instruction.
2868 * @param u2Opc The logical operation to perform.
2869 * @param fNot Whether to complement the 2nd operand.
2870 * @param iRegResult The output register.
2871 * @param iReg1 The 1st register operand.
2872 * @param iReg2Shifted The 2nd register operand, to which the optional
2873 * shifting is applied.
2874 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
2875 * GPRs.
2876 * @param offShift6 The shift amount (default: none).
2877 * @param enmShift The shift operation (default: LSL).
2878 */
2879DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
2880 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
2881 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
2882{
2883 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
2884 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
2885 return ((uint32_t)f64Bit << 31)
2886 | (u2Opc << 29)
2887 | UINT32_C(0x0a000000)
2888 | ((uint32_t)enmShift << 22)
2889 | ((uint32_t)fNot << 21)
2890 | (iReg2Shifted << 16)
2891 | (offShift6 << 10)
2892 | (iReg1 << 5)
2893 | iRegResult;
2894}
2895
2896
2897/** A64: Encodes an AND instruction.
2898 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2899DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2900 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2901{
2902 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2903}
2904
2905
2906/** A64: Encodes an BIC instruction.
2907 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2908DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2909 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2910{
2911 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2912}
2913
2914
2915/** A64: Encodes an ORR instruction.
2916 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2917DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2918 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2919{
2920 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2921}
2922
2923
2924/** A64: Encodes an MOV instruction.
2925 * This is an alias for "orr dst, xzr, src". */
2926DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
2927{
2928 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
2929}
2930
2931
2932/** A64: Encodes an ORN instruction.
2933 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2934DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2935 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2936{
2937 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2938}
2939
2940
2941/** A64: Encodes an EOR instruction.
2942 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2943DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2944 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2945{
2946 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2947}
2948
2949
2950/** A64: Encodes an EON instruction.
2951 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2952DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2953 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2954{
2955 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2956}
2957
2958
2959/** A64: Encodes an ANDS instruction.
2960 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2961DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2962 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2963{
2964 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2965}
2966
2967
2968/** A64: Encodes an BICS instruction.
2969 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2970DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2971 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2972{
2973 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2974}
2975
2976
2977
2978/*
2979 * Data processing instructions with two source register operands.
2980 */
2981
2982
2983/** A64: Encodes an SUBP instruction. */
2984DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
2985{
2986 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
2987 return UINT32_C(0x80000000)
2988 | UINT32_C(0x1ac00000)
2989 | (UINT32_C(0) << 10)
2990 | (iRegSubtrahend << 16)
2991 | (iRegMinuend << 5)
2992 | iRegResult;
2993}
2994
2995
2996/** A64: Encodes an SUBPS instruction. */
2997DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
2998{
2999 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3000 return UINT32_C(0x80000000)
3001 | UINT32_C(0x20000000)
3002 | UINT32_C(0x1ac00000)
3003 | (UINT32_C(0) << 10)
3004 | (iRegSubtrahend << 16)
3005 | (iRegMinuend << 5)
3006 | iRegResult;
3007}
3008
3009
3010/** A64: Encodes an UDIV instruction. */
3011DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3012{
3013 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3014 return ((uint32_t)f64Bit << 31)
3015 | UINT32_C(0x1ac00000)
3016 | (UINT32_C(2) << 10)
3017 | (iRegDivisor << 16)
3018 | (iRegDividend << 5)
3019 | iRegResult;
3020}
3021
3022
3023/** A64: Encodes an SDIV instruction. */
3024DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3025{
3026 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3027 return ((uint32_t)f64Bit << 31)
3028 | UINT32_C(0x1ac00000)
3029 | (UINT32_C(3) << 10)
3030 | (iRegDivisor << 16)
3031 | (iRegDividend << 5)
3032 | iRegResult;
3033}
3034
3035
3036/** A64: Encodes an IRG instruction. */
3037DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3038{
3039 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3040 return UINT32_C(0x80000000)
3041 | UINT32_C(0x1ac00000)
3042 | (UINT32_C(4) << 10)
3043 | (iRegSrc2 << 16)
3044 | (iRegSrc1 << 5)
3045 | iRegResult;
3046}
3047
3048
3049/** A64: Encodes a GMI instruction. */
3050DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3051{
3052 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3053 return UINT32_C(0x80000000)
3054 | UINT32_C(0x1ac00000)
3055 | (UINT32_C(5) << 10)
3056 | (iRegSrc2 << 16)
3057 | (iRegSrc1 << 5)
3058 | iRegResult;
3059}
3060
3061
3062/** A64: Encodes an LSLV instruction. */
3063DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3064{
3065 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3066 return ((uint32_t)f64Bit << 31)
3067 | UINT32_C(0x1ac00000)
3068 | (UINT32_C(8) << 10)
3069 | (iRegCount << 16)
3070 | (iRegSrc << 5)
3071 | iRegResult;
3072}
3073
3074
3075/** A64: Encodes an LSRV instruction. */
3076DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3077{
3078 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3079 return ((uint32_t)f64Bit << 31)
3080 | UINT32_C(0x1ac00000)
3081 | (UINT32_C(9) << 10)
3082 | (iRegCount << 16)
3083 | (iRegSrc << 5)
3084 | iRegResult;
3085}
3086
3087
3088/** A64: Encodes an ASRV instruction. */
3089DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3090{
3091 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3092 return ((uint32_t)f64Bit << 31)
3093 | UINT32_C(0x1ac00000)
3094 | (UINT32_C(10) << 10)
3095 | (iRegCount << 16)
3096 | (iRegSrc << 5)
3097 | iRegResult;
3098}
3099
3100
3101/** A64: Encodes a RORV instruction. */
3102DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3103{
3104 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3105 return ((uint32_t)f64Bit << 31)
3106 | UINT32_C(0x1ac00000)
3107 | (UINT32_C(11) << 10)
3108 | (iRegCount << 16)
3109 | (iRegSrc << 5)
3110 | iRegResult;
3111}
3112
3113
3114/** A64: Encodes a PACGA instruction. */
3115DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3116{
3117 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3118 return UINT32_C(0x80000000)
3119 | UINT32_C(0x1ac00000)
3120 | (UINT32_C(12) << 10)
3121 | (iRegSrc2 << 16)
3122 | (iRegSrc1 << 5)
3123 | iRegResult;
3124}
3125
3126
3127/** A64: Encodes a CRC32* instruction. */
3128DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3129{
3130 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3131 return ((uint32_t)(uSize == 3) << 31)
3132 | UINT32_C(0x1ac00000)
3133 | (UINT32_C(16) << 10)
3134 | (uSize << 10)
3135 | (iRegValue << 16)
3136 | (iRegCrc << 5)
3137 | iRegResult;
3138}
3139
3140
3141/** A64: Encodes a CRC32B instruction. */
3142DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3143{
3144 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
3145}
3146
3147
3148/** A64: Encodes a CRC32H instruction. */
3149DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3150{
3151 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
3152}
3153
3154
3155/** A64: Encodes a CRC32W instruction. */
3156DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3157{
3158 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
3159}
3160
3161
3162/** A64: Encodes a CRC32X instruction. */
3163DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3164{
3165 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
3166}
3167
3168
3169/** A64: Encodes a CRC32C* instruction. */
3170DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3171{
3172 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3173 return ((uint32_t)(uSize == 3) << 31)
3174 | UINT32_C(0x1ac00000)
3175 | (UINT32_C(20) << 10)
3176 | (uSize << 10)
3177 | (iRegValue << 16)
3178 | (iRegCrc << 5)
3179 | iRegResult;
3180}
3181
3182
3183/** A64: Encodes a CRC32B instruction. */
3184DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3185{
3186 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
3187}
3188
3189
3190/** A64: Encodes a CRC32CH instruction. */
3191DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3192{
3193 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
3194}
3195
3196
3197/** A64: Encodes a CRC32CW instruction. */
3198DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3199{
3200 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
3201}
3202
3203
3204/** A64: Encodes a CRC32CX instruction. */
3205DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3206{
3207 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
3208}
3209
3210
3211/** A64: Encodes an SMAX instruction. */
3212DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3213{
3214 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3215 return ((uint32_t)f64Bit << 31)
3216 | UINT32_C(0x1ac00000)
3217 | (UINT32_C(24) << 10)
3218 | (iRegSrc2 << 16)
3219 | (iRegSrc1 << 5)
3220 | iRegResult;
3221}
3222
3223
3224/** A64: Encodes an UMAX instruction. */
3225DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3226{
3227 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3228 return ((uint32_t)f64Bit << 31)
3229 | UINT32_C(0x1ac00000)
3230 | (UINT32_C(25) << 10)
3231 | (iRegSrc2 << 16)
3232 | (iRegSrc1 << 5)
3233 | iRegResult;
3234}
3235
3236
3237/** A64: Encodes an SMIN instruction. */
3238DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3239{
3240 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3241 return ((uint32_t)f64Bit << 31)
3242 | UINT32_C(0x1ac00000)
3243 | (UINT32_C(26) << 10)
3244 | (iRegSrc2 << 16)
3245 | (iRegSrc1 << 5)
3246 | iRegResult;
3247}
3248
3249
3250/** A64: Encodes an UMIN instruction. */
3251DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3252{
3253 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3254 return ((uint32_t)f64Bit << 31)
3255 | UINT32_C(0x1ac00000)
3256 | (UINT32_C(27) << 10)
3257 | (iRegSrc2 << 16)
3258 | (iRegSrc1 << 5)
3259 | iRegResult;
3260}
3261
3262
3263# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
3264
3265/**
3266 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
3267 *
3268 * @returns The decoded mask.
3269 * @param uImm6SizeLen The immS value from the instruction. (No N part
3270 * here, as that must be zero for instructions
3271 * operating on 32-bit wide registers.)
3272 * @param uImm6Rotations The immR value from the instruction.
3273 */
3274DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3275{
3276 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
3277
3278 /* Determine the element size. */
3279 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
3280 Assert(cBitsElementLog2 + 1U != 0U);
3281
3282 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3283 Assert(uImm6Rotations < cBitsElement);
3284
3285 /* Extract the number of bits set to 1: */
3286 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
3287 Assert(cBitsSetTo1 < cBitsElement);
3288 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
3289
3290 /* Produce the unrotated pattern. */
3291 static const uint32_t s_auReplicate[]
3292 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3293 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3294
3295 /* Rotate it and return. */
3296 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
3297}
3298
3299
3300/**
3301 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
3302 *
3303 * @returns The decoded mask.
3304 * @param uImm7SizeLen The N:immS value from the instruction.
3305 * @param uImm6Rotations The immR value from the instruction.
3306 */
3307DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
3308{
3309 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
3310
3311 /* Determine the element size. */
3312 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
3313 Assert(cBitsElementLog2 + 1U != 0U);
3314
3315 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3316 Assert(uImm6Rotations < cBitsElement);
3317
3318 /* Extract the number of bits set to 1: */
3319 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
3320 Assert(cBitsSetTo1 < cBitsElement);
3321 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
3322
3323 /* Produce the unrotated pattern. */
3324 static const uint64_t s_auReplicate[]
3325 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3326 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3327
3328 /* Rotate it and return. */
3329 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
3330}
3331
3332
3333/**
3334 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
3335 * the immS value.
3336 */
3337DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3338{
3339 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
3340}
3341
3342
3343/**
3344 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3345 * 32-bit bitmask to a set of immediates for those instructions.
3346 *
3347 * @returns true if successful, false if not.
3348 * @param fMask The mask value to convert.
3349 * @param puImm6SizeLen Where to return the immS part (N is always zero for
3350 * 32-bit wide masks).
3351 * @param puImm6Rotations Where to return the immR.
3352 */
3353DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
3354{
3355 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
3356 if ((uint32_t)(fMask + 1U) <= 1)
3357 return false;
3358
3359 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3360 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
3361 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
3362 if (cRor)
3363 fMask = ASMRotateRightU32(fMask, cRor);
3364 else
3365 fMask = ASMRotateLeftU32(fMask, cRol);
3366 Assert(fMask & RT_BIT_32(0));
3367 Assert(!(fMask & RT_BIT_32(31)));
3368
3369 /* Count the trailing ones and leading zeros. */
3370 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
3371 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
3372
3373 /* The potential element length is then the sum of the two above. */
3374 unsigned const cBitsElement = cOnes + cZeros;
3375 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3376 return false;
3377
3378 /* Special case: 32 bits element size. Since we're done here. */
3379 if (cBitsElement == 32)
3380 *puImm6SizeLen = cOnes - 1;
3381 else
3382 {
3383 /* Extract the element bits and check that these are replicated in the whole pattern. */
3384 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
3385 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
3386
3387 static const uint32_t s_auReplicate[]
3388 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3389 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3390 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3391 else
3392 return false;
3393 }
3394 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3395
3396 return true;
3397}
3398
3399
3400/**
3401 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3402 * 64-bit bitmask to a set of immediates for those instructions.
3403 *
3404 * @returns true if successful, false if not.
3405 * @param fMask The mask value to convert.
3406 * @param puImm7SizeLen Where to return the N:immS part.
3407 * @param puImm6Rotations Where to return the immR.
3408 */
3409DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
3410{
3411 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
3412 if ((uint64_t)(fMask + 1U) <= 1)
3413 return false;
3414
3415 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3416 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
3417 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
3418 if (cRor)
3419 fMask = ASMRotateRightU64(fMask, cRor);
3420 else
3421 fMask = ASMRotateLeftU64(fMask, cRol);
3422 Assert(fMask & RT_BIT_64(0));
3423 Assert(!(fMask & RT_BIT_64(63)));
3424
3425 /* Count the trailing ones and leading zeros. */
3426 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
3427 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
3428
3429 /* The potential element length is then the sum of the two above. */
3430 unsigned const cBitsElement = cOnes + cZeros;
3431 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3432 return false;
3433
3434 /* Special case: 64 bits element size. Since we're done here. */
3435 if (cBitsElement == 64)
3436 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
3437 else
3438 {
3439 /* Extract the element bits and check that these are replicated in the whole pattern. */
3440 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
3441 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
3442
3443 static const uint64_t s_auReplicate[]
3444 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3445 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3446 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3447 else
3448 return false;
3449 }
3450 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3451
3452 return true;
3453}
3454
3455# endif /* IPRT_INCLUDED_asm_h */
3456
3457/**
3458 * A64: Encodes a logical instruction with an complicated immediate mask.
3459 *
3460 * The @a uImm7SizeLen parameter specifies two things:
3461 * 1. the element size and
3462 * 2. the number of bits set to 1 in the pattern.
3463 *
3464 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
3465 * top) and using the position of the first bit set as a power of two.
3466 *
3467 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
3468 * |---|---|---|---|---|---|---|--------------|
3469 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
3470 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
3471 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
3472 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
3473 * | 0 | 0 | x | x | x | x | x | 32 bits |
3474 * | 1 | x | x | x | x | x | x | 64 bits |
3475 *
3476 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
3477 * there is always one zero bit in the pattern).
3478 *
3479 * The @a uImm6Rotations parameter specifies how many bits to the right,
3480 * the element pattern is rotated. The rotation count must be less than the
3481 * element bit count (size).
3482 *
3483 * @returns The encoded instruction.
3484 * @param u2Opc The logical operation to perform.
3485 * @param iRegResult The output register.
3486 * @param iRegSrc The 1st register operand.
3487 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
3488 * field at the top of the 6-bit 'imms' field.
3489 *
3490 * @param uImm6Rotations The rotation count.
3491 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3492 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3493 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3494 */
3495DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3496 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
3497{
3498 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x3f)));
3499 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
3500 return ((uint32_t)f64Bit << 31)
3501 | (u2Opc << 29)
3502 | UINT32_C(0x12000000)
3503 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
3504 | (uImm6Rotations << 16)
3505 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
3506 | (iRegSrc << 5)
3507 | iRegResult;
3508}
3509
3510
3511/** A64: Encodes an AND instruction w/ complicated immediate mask.
3512 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3513DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
3514 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3515{
3516 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3517}
3518
3519
3520/** A64: Encodes an ORR instruction w/ complicated immediate mask.
3521 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3522DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
3523 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3524{
3525 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3526}
3527
3528
3529/** A64: Encodes an EOR instruction w/ complicated immediate mask.
3530 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3531DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
3532 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3533{
3534 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3535}
3536
3537
3538/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
3539 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3540DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
3541 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3542{
3543 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3544}
3545
3546
3547/** A64: Encodes an TST instruction w/ complicated immediate mask.
3548 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3549DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
3550 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3551{
3552 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3553}
3554
3555
3556/**
3557 * A64: Encodes a bitfield instruction.
3558 *
3559 * @returns The encoded instruction.
3560 * @param u2Opc The bitfield operation to perform.
3561 * @param iRegResult The output register.
3562 * @param iRegSrc The 1st register operand.
3563 * @param cImm6Ror The right rotation count.
3564 * @param uImm6S The leftmost bit to be moved.
3565 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3566 * @param uN1 This must match @a f64Bit for all instructions
3567 * currently specified.
3568 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3569 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3570 */
3571DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3572 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
3573{
3574 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
3575 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
3576 return ((uint32_t)f64Bit << 31)
3577 | (u2Opc << 29)
3578 | UINT32_C(0x13000000)
3579 | (uN1 << 22)
3580 | (cImm6Ror << 16)
3581 | (uImm6S << 10)
3582 | (iRegSrc << 5)
3583 | iRegResult;
3584}
3585
3586
3587/** A64: Encodes a SBFM instruction.
3588 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3589DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3590 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3591{
3592 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3593}
3594
3595
3596/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
3597 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3598DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3599{
3600 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
3601}
3602
3603
3604/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
3605 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3606DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3607{
3608 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
3609}
3610
3611
3612/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
3613 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3614DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
3615{
3616 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
3617}
3618
3619
3620/** A64: Encodes an ASR instruction w/ immediate shift value.
3621 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3622DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3623{
3624 uint32_t const cWidth = f64Bit ? 63 : 31;
3625 Assert(cShift > 0); Assert(cShift <= cWidth);
3626 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
3627}
3628
3629
3630/** A64: Encodes a BFM instruction.
3631 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3632DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3633 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3634{
3635 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3636}
3637
3638
3639/** A64: Encodes a BFI instruction (insert).
3640 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3641DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
3642 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3643{
3644 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3645 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
3646 cBitsWidth - 1, f64Bit);
3647}
3648
3649
3650/** A64: Encodes a BFXIL instruction (insert low).
3651 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3652DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfxil(uint32_t iRegResult, uint32_t iRegSrc,
3653 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3654{
3655 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3656 Assert(offFirstBit + cBitsWidth <= (f64Bit ? 64U : 32U));
3657 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3658}
3659
3660
3661/** A64: Encodes an UBFM instruction.
3662 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3663DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3664 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3665{
3666 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3667}
3668
3669
3670/** A64: Encodes an UBFX instruction (zero extending extract).
3671 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3672DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
3673 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3674{
3675 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3676}
3677
3678
3679/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
3680 * shifted into destination).
3681 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3682DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
3683 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
3684{
3685 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
3686 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
3687}
3688
3689
3690/** A64: Encodes an LSL instruction w/ immediate shift value.
3691 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3692DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3693{
3694 uint32_t const cWidth = f64Bit ? 63 : 31;
3695 Assert(cShift > 0); Assert(cShift <= cWidth);
3696 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
3697 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
3698}
3699
3700
3701/** A64: Encodes an LSR instruction w/ immediate shift value.
3702 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3703DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3704{
3705 uint32_t const cWidth = f64Bit ? 63 : 31;
3706 Assert(cShift > 0); Assert(cShift <= cWidth);
3707 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
3708}
3709
3710
3711/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
3712 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3713DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3714{
3715 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
3716}
3717
3718
3719/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
3720 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3721DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3722{
3723 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
3724}
3725
3726
3727/**
3728 * A64: Encodes an EXTR instruction with an immediate.
3729 *
3730 * @returns The encoded instruction.
3731 * @param iRegResult The register to store the result in. ZR is valid.
3732 * @param iRegLow The register holding the least significant bits in the
3733 * extraction. ZR is valid.
3734 * @param iRegHigh The register holding the most significant bits in the
3735 * extraction. ZR is valid.
3736 * @param uLsb The bit number of the least significant bit, or where in
3737 * @a iRegLow to start the
3738 * extraction.
3739 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3740 */
3741DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
3742 bool f64Bit = true)
3743{
3744 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
3745 return ((uint32_t)f64Bit << 31)
3746 | UINT32_C(0x13800000)
3747 | ((uint32_t)f64Bit << 22) /*N*/
3748 | (iRegHigh << 16)
3749 | (uLsb << 10)
3750 | (iRegLow << 5)
3751 | iRegResult;
3752}
3753
3754
3755/** A64: Rotates the value of a register (alias for EXTR). */
3756DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3757{
3758 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
3759}
3760
3761
3762/**
3763 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
3764 *
3765 * @returns The encoded instruction.
3766 * @param fSub true for sub and subs, false for add and
3767 * adds.
3768 * @param iRegResult The register to store the result in.
3769 * SP is valid when @a fSetFlags = false,
3770 * and ZR is valid otherwise.
3771 * @param iRegSrc The register containing the augend (@a fSub
3772 * = false) or minuend (@a fSub = true). SP is
3773 * a valid registers for all variations.
3774 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
3775 * (@a fSub = true).
3776 * @param f64Bit true for 64-bit GRPs (default), false for
3777 * 32-bit GPRs.
3778 * @param fSetFlags Whether to set flags (adds / subs) or not
3779 * (add / sub - default).
3780 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
3781 * bits to the left, or not (default).
3782 */
3783DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
3784 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
3785 bool fSetFlags = false, bool fShift12 = false)
3786{
3787 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
3788 return ((uint32_t)f64Bit << 31)
3789 | ((uint32_t)fSub << 30)
3790 | ((uint32_t)fSetFlags << 29)
3791 | UINT32_C(0x11000000)
3792 | ((uint32_t)fShift12 << 22)
3793 | (uImm12AddendSubtrahend << 10)
3794 | (iRegSrc << 5)
3795 | iRegResult;
3796}
3797
3798
3799/** Alias for sub zxr, reg, \#uimm12. */
3800DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
3801 bool f64Bit = true, bool fShift12 = false)
3802{
3803 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
3804 f64Bit, true /*fSetFlags*/, fShift12);
3805}
3806
3807
3808/** ADD dst, src, \#uimm12 */
3809DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
3810 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3811{
3812 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
3813}
3814
3815
3816/** SUB dst, src, \#uimm12 */
3817DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
3818 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3819{
3820 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
3821}
3822
3823
3824/**
3825 * A64: Encodes either add, adds, sub or subs with shifted register.
3826 *
3827 * @returns The encoded instruction.
3828 * @param fSub true for sub and subs, false for add and
3829 * adds.
3830 * @param iRegResult The register to store the result in.
3831 * SP is NOT valid, but ZR is.
3832 * @param iRegSrc1 The register containing the augend (@a fSub
3833 * = false) or minuend (@a fSub = true).
3834 * SP is NOT valid, but ZR is.
3835 * @param iRegSrc2 The register containing the addened (@a fSub
3836 * = false) or subtrahend (@a fSub = true).
3837 * SP is NOT valid, but ZR is.
3838 * @param f64Bit true for 64-bit GRPs (default), false for
3839 * 32-bit GPRs.
3840 * @param fSetFlags Whether to set flags (adds / subs) or not
3841 * (add / sub - default).
3842 * @param cShift The shift count to apply to @a iRegSrc2.
3843 * @param enmShift The shift type to apply to the @a iRegSrc2
3844 * register. kArmv8A64InstrShift_Ror is
3845 * reserved.
3846 */
3847DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3848 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3849 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3850{
3851 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3852 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
3853
3854 return ((uint32_t)f64Bit << 31)
3855 | ((uint32_t)fSub << 30)
3856 | ((uint32_t)fSetFlags << 29)
3857 | UINT32_C(0x0b000000)
3858 | ((uint32_t)enmShift << 22)
3859 | (iRegSrc2 << 16)
3860 | (cShift << 10)
3861 | (iRegSrc1 << 5)
3862 | iRegResult;
3863}
3864
3865
3866/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
3867DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
3868 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3869{
3870 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
3871 f64Bit, true /*fSetFlags*/, cShift, enmShift);
3872}
3873
3874
3875/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3876DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3877 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3878 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3879{
3880 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3881}
3882
3883
3884/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3885DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3886 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3887 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3888{
3889 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3890}
3891
3892
3893/** NEG dst */
3894DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
3895{
3896 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
3897}
3898
3899
3900/** Extension option for 'extended register' instructions. */
3901typedef enum ARMV8A64INSTREXTEND
3902{
3903 kArmv8A64InstrExtend_UxtB = 0,
3904 kArmv8A64InstrExtend_UxtH,
3905 kArmv8A64InstrExtend_UxtW,
3906 kArmv8A64InstrExtend_UxtX,
3907 kArmv8A64InstrExtend_SxtB,
3908 kArmv8A64InstrExtend_SxtH,
3909 kArmv8A64InstrExtend_SxtW,
3910 kArmv8A64InstrExtend_SxtX,
3911 /** The default is either UXTW or UXTX depending on whether the instruction
3912 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
3913 * to the f64Bit value. */
3914 kArmv8A64InstrExtend_Default
3915} ARMV8A64INSTREXTEND;
3916
3917
3918/**
3919 * A64: Encodes either add, adds, sub or subs with extended register encoding.
3920 *
3921 * @returns The encoded instruction.
3922 * @param fSub true for sub and subs, false for add and
3923 * adds.
3924 * @param iRegResult The register to store the result in.
3925 * SP is NOT valid, but ZR is.
3926 * @param iRegSrc1 The register containing the augend (@a fSub
3927 * = false) or minuend (@a fSub = true).
3928 * SP is valid, but ZR is NOT.
3929 * @param iRegSrc2 The register containing the addened (@a fSub
3930 * = false) or subtrahend (@a fSub = true).
3931 * SP is NOT valid, but ZR is.
3932 * @param f64Bit true for 64-bit GRPs (default), false for
3933 * 32-bit GPRs.
3934 * @param fSetFlags Whether to set flags (adds / subs) or not
3935 * (add / sub - default).
3936 * @param enmExtend The type of extension to apply to @a
3937 * iRegSrc2.
3938 * @param cShift The left shift count to apply to @a iRegSrc2
3939 * after enmExtend processing is done.
3940 * Max shift is 4 for some reason.
3941 */
3942DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3943 bool f64Bit = true, bool fSetFlags = false,
3944 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
3945 uint32_t cShift = 0)
3946{
3947 if (enmExtend == kArmv8A64InstrExtend_Default)
3948 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
3949 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
3950
3951 return ((uint32_t)f64Bit << 31)
3952 | ((uint32_t)fSub << 30)
3953 | ((uint32_t)fSetFlags << 29)
3954 | UINT32_C(0x0b200000)
3955 | (iRegSrc2 << 16)
3956 | ((uint32_t)enmExtend << 13)
3957 | (cShift << 10)
3958 | (iRegSrc1 << 5)
3959 | iRegResult;
3960}
3961
3962
3963/**
3964 * A64: Encodes either adc, adcs, sbc or sbcs with two source registers.
3965 *
3966 * @returns The encoded instruction.
3967 * @param fSub true for sbc and sbcs, false for adc and
3968 * adcs.
3969 * @param iRegResult The register to store the result in. SP is
3970 * NOT valid, but ZR is.
3971 * @param iRegSrc1 The register containing the augend (@a fSub
3972 * = false) or minuend (@a fSub = true).
3973 * SP is NOT valid, but ZR is.
3974 * @param iRegSrc2 The register containing the addened (@a fSub
3975 * = false) or subtrahend (@a fSub = true).
3976 * SP is NOT valid, but ZR is.
3977 * @param f64Bit true for 64-bit GRPs (default), false for
3978 * 32-bit GPRs.
3979 * @param fSetFlags Whether to set flags (adds / subs) or not
3980 * (add / sub - default).
3981 */
3982DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcSbc(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3983 bool f64Bit = true, bool fSetFlags = false)
3984{
3985 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3986
3987 return ((uint32_t)f64Bit << 31)
3988 | ((uint32_t)fSub << 30)
3989 | ((uint32_t)fSetFlags << 29)
3990 | UINT32_C(0x1a000000)
3991 | (iRegSrc2 << 16)
3992 | (iRegSrc1 << 5)
3993 | iRegResult;
3994}
3995
3996
3997/** ADC dst, reg1, reg2 */
3998DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3999 bool f64Bit = true, bool fSetFlags = false)
4000{
4001 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4002}
4003
4004
4005/** ADCS dst, reg1, reg2 */
4006DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4007{
4008 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4009}
4010
4011
4012/** SBC dst, reg1, reg2 */
4013DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4014 bool f64Bit = true, bool fSetFlags = false)
4015{
4016 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4017}
4018
4019
4020/** SBCS dst, reg1, reg2 */
4021DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4022{
4023 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4024}
4025
4026
4027/**
4028 * A64: Encodes a B (unconditional branch w/ imm) instruction.
4029 *
4030 * @returns The encoded instruction.
4031 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4032 */
4033DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
4034{
4035 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
4036 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
4037}
4038
4039
4040/**
4041 * A64: Encodes a BL (unconditional call w/ imm) instruction.
4042 *
4043 * @returns The encoded instruction.
4044 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4045 */
4046DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
4047{
4048 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
4049}
4050
4051
4052/**
4053 * A64: Encodes a BR (unconditional branch w/ register) instruction.
4054 *
4055 * @returns The encoded instruction.
4056 * @param iReg The register containing the target address.
4057 */
4058DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
4059{
4060 Assert(iReg < 32);
4061 return UINT32_C(0xd61f0000) | (iReg << 5);
4062}
4063
4064
4065/**
4066 * A64: Encodes a BLR instruction.
4067 *
4068 * @returns The encoded instruction.
4069 * @param iReg The register containing the target address.
4070 */
4071DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
4072{
4073 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
4074}
4075
4076
4077/**
4078 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
4079 *
4080 * @returns The encoded instruction.
4081 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4082 * its not zero.
4083 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4084 * @param iReg The GPR to check for zero / non-zero value.
4085 * @param f64Bit true for 64-bit register, false for 32-bit.
4086 */
4087DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4088{
4089 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
4090 return ((uint32_t)f64Bit << 31)
4091 | UINT32_C(0x34000000)
4092 | ((uint32_t)fJmpIfNotZero << 24)
4093 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4094 | iReg;
4095}
4096
4097
4098/** A64: Encodes the CBZ instructions. */
4099DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4100{
4101 return Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4102}
4103
4104
4105/** A64: Encodes the CBNZ instructions. */
4106DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbnz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4107{
4108 return Armv8A64MkInstrCbzCbnz(true /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4109}
4110
4111
4112/**
4113 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
4114 *
4115 * @returns The encoded instruction.
4116 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4117 * its not zero.
4118 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4119 * @param iReg The GPR to check for zero / non-zero value.
4120 * @param iBitNo The bit to test for.
4121 */
4122DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4123{
4124 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
4125 return ((uint32_t)(iBitNo & 0x20) << (31-5))
4126 | UINT32_C(0x36000000)
4127 | ((uint32_t)fJmpIfNotZero << 24)
4128 | ((iBitNo & 0x1f) << 19)
4129 | (((uint32_t)iImm14 & 0x3fff) << 5)
4130 | iReg;
4131}
4132
4133
4134/**
4135 * A64: Encodes TBZ (conditional branch w/ immediate) instructions.
4136 *
4137 * @returns The encoded instruction.
4138 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4139 * @param iReg The GPR to check for zero / non-zero value.
4140 * @param iBitNo The bit to test for.
4141 */
4142DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4143{
4144 return Armv8A64MkInstrTbzTbnz(false /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4145}
4146
4147
4148/**
4149 * A64: Encodes TBNZ (conditional branch w/ immediate) instructions.
4150 *
4151 * @returns The encoded instruction.
4152 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4153 * @param iReg The GPR to check for zero / non-zero value.
4154 * @param iBitNo The bit to test for.
4155 */
4156DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbnz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4157{
4158 return Armv8A64MkInstrTbzTbnz(true /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4159}
4160
4161
4162
4163/** Armv8 Condition codes. */
4164typedef enum ARMV8INSTRCOND
4165{
4166 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
4167 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
4168
4169 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
4170 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
4171 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
4172 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
4173
4174 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
4175 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
4176
4177 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
4178 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
4179
4180 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
4181 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
4182
4183 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
4184 kArmv8InstrCond_Lt, /**< b - Signed less than. */
4185
4186 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
4187 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
4188
4189 kArmv8InstrCond_Al, /**< e - Condition is always true. */
4190 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
4191} ARMV8INSTRCOND;
4192
4193/**
4194 * A64: Encodes conditional branch instruction w/ immediate target.
4195 *
4196 * @returns The encoded instruction.
4197 * @param enmCond The branch condition.
4198 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4199 */
4200DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
4201{
4202 Assert((unsigned)enmCond < 16);
4203 return UINT32_C(0x54000000)
4204 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4205 | (uint32_t)enmCond;
4206}
4207
4208
4209/**
4210 * A64: Encodes the BRK instruction.
4211 *
4212 * @returns The encoded instruction.
4213 * @param uImm16 Unsigned immediate value.
4214 */
4215DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
4216{
4217 Assert(uImm16 < _64K);
4218 return UINT32_C(0xd4200000)
4219 | (uImm16 << 5);
4220}
4221
4222/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
4223 * @{ */
4224#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
4225#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
4226#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
4227#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
4228#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
4229#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
4230#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
4231#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
4232
4233#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
4234#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
4235#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
4236#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
4237#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
4238#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
4239#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
4240#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
4241/** @} */
4242
4243/**
4244 * A64: Encodes CCMP or CCMN with two register operands.
4245 *
4246 * @returns The encoded instruction.
4247 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
4248 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
4249 * @param fNzcv The N, Z, C & V flags values to load if the condition
4250 * does not match. See RMA64_NZCV_F_XXX.
4251 * @param enmCond The condition guarding the compare.
4252 * @param fCCmp Set for CCMP (default), clear for CCMN.
4253 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4254 */
4255DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4256 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
4257{
4258 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
4259
4260 return ((uint32_t)f64Bit << 31)
4261 | ((uint32_t)fCCmp << 30)
4262 | UINT32_C(0x3a400000)
4263 | (iRegSrc2 << 16)
4264 | ((uint32_t)enmCond << 12)
4265 | (iRegSrc1 << 5)
4266 | fNzcv;
4267}
4268
4269/** CCMP w/ reg. */
4270DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4271 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4272{
4273 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4274}
4275
4276
4277/** CCMN w/ reg. */
4278DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4279 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4280{
4281 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4282}
4283
4284
4285/**
4286 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
4287 *
4288 * @returns The encoded instruction.
4289 * @param iRegSrc The register. SP is NOT valid, but ZR is.
4290 * @param uImm5 The immediate, to compare iRegSrc with.
4291 * @param fNzcv The N, Z, C & V flags values to load if the condition
4292 * does not match. See RMA64_NZCV_F_XXX.
4293 * @param enmCond The condition guarding the compare.
4294 * @param fCCmp Set for CCMP (default), clear for CCMN.
4295 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4296 */
4297DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
4298 bool fCCmp = true, bool f64Bit = true)
4299{
4300 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
4301
4302 return ((uint32_t)f64Bit << 31)
4303 | ((uint32_t)fCCmp << 30)
4304 | UINT32_C(0x3a400800)
4305 | (uImm5 << 16)
4306 | ((uint32_t)enmCond << 12)
4307 | (iRegSrc << 5)
4308 | fNzcv;
4309}
4310
4311/** CCMP w/ immediate. */
4312DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4313 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4314{
4315 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4316}
4317
4318
4319/** CCMN w/ immediate. */
4320DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4321 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4322{
4323 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4324}
4325
4326
4327/**
4328 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
4329 *
4330 * @returns The encoded instruction.
4331 * @param uOp Opcode bit 30.
4332 * @param uOp2 Opcode bits 11:10.
4333 * @param iRegResult The result register. SP is NOT valid, but ZR is.
4334 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
4335 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
4336 * @param enmCond The condition guarding the compare.
4337 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4338 */
4339DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
4340 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4341{
4342 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4343
4344 return ((uint32_t)f64Bit << 31)
4345 | (uOp << 30)
4346 | UINT32_C(0x1a800000)
4347 | (iRegSrc2 << 16)
4348 | ((uint32_t)enmCond << 12)
4349 | (uOp2 << 10)
4350 | (iRegSrc1 << 5)
4351 | iRegResult;
4352}
4353
4354
4355/** A64: Encodes CSEL.
4356 * @see Armv8A64MkInstrCondSelect for details. */
4357DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4358 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4359{
4360 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4361}
4362
4363
4364/** A64: Encodes CSINC.
4365 * @see Armv8A64MkInstrCondSelect for details. */
4366DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4367 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4368{
4369 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4370}
4371
4372
4373/** A64: Encodes CSET.
4374 * @see Armv8A64MkInstrCondSelect for details. */
4375DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4376{
4377 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4378 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4379 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4380}
4381
4382
4383/** A64: Encodes CSINV.
4384 * @see Armv8A64MkInstrCondSelect for details. */
4385DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4386 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4387{
4388 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4389}
4390
4391/** A64: Encodes CSETM.
4392 * @see Armv8A64MkInstrCondSelect for details. */
4393DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4394{
4395 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4396 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4397 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4398}
4399
4400
4401/** A64: Encodes CSNEG.
4402 * @see Armv8A64MkInstrCondSelect for details. */
4403DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4404 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4405{
4406 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4407}
4408
4409
4410/**
4411 * A64: Encodes REV instruction.
4412 *
4413 * @returns The encoded instruction.
4414 * @param iRegDst The destination register. SP is NOT valid.
4415 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4416 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4417 */
4418DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4419{
4420 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4421
4422 return ((uint32_t)f64Bit << 31)
4423 | UINT32_C(0x5ac00800)
4424 | ((uint32_t)f64Bit << 10)
4425 | (iRegSrc << 5)
4426 | iRegDst;
4427}
4428
4429
4430/**
4431 * A64: Encodes REV16 instruction.
4432 *
4433 * @returns The encoded instruction.
4434 * @param iRegDst The destination register. SP is NOT valid.
4435 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4436 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4437 */
4438DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4439{
4440 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4441
4442 return ((uint32_t)f64Bit << 31)
4443 | UINT32_C(0x5ac00400)
4444 | (iRegSrc << 5)
4445 | iRegDst;
4446}
4447
4448
4449/**
4450 * A64: Encodes SETF8 & SETF16.
4451 *
4452 * @returns The encoded instruction.
4453 * @param iRegResult The register holding the result. SP is NOT valid.
4454 * @param f16Bit Set for SETF16, clear for SETF8.
4455 */
4456DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
4457{
4458 Assert(iRegResult < 32);
4459
4460 return UINT32_C(0x3a00080d)
4461 | ((uint32_t)f16Bit << 14)
4462 | (iRegResult << 5);
4463}
4464
4465
4466/**
4467 * A64: Encodes RMIF.
4468 *
4469 * @returns The encoded instruction.
4470 * @param iRegSrc The source register to get flags from.
4471 * @param cRotateRight The right rotate count (LSB bit offset).
4472 * @param fMask Mask of which flag bits to set:
4473 * - bit 0: V
4474 * - bit 1: C
4475 * - bit 2: Z
4476 * - bit 3: N
4477 */
4478DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRmif(uint32_t iRegSrc, uint32_t cRotateRight, uint32_t fMask)
4479{
4480 Assert(iRegSrc < 32); Assert(cRotateRight < 64); Assert(fMask <= 0xf);
4481
4482 return UINT32_C(0xba000400)
4483 | (cRotateRight << 15)
4484 | (iRegSrc << 5)
4485 | fMask;
4486}
4487
4488
4489/**
4490 * A64: Encodes MRS (for reading a system register into a GPR).
4491 *
4492 * @returns The encoded instruction.
4493 * @param iRegDst The register to put the result into. SP is NOT valid.
4494 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4495 * IPRT specific format, of the register to read.
4496 */
4497DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
4498{
4499 Assert(iRegDst < 32);
4500 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4501
4502 /* Note. The top bit of idSysReg must always be set and is also set in
4503 0xd5300000, otherwise we'll be encoding a different instruction. */
4504 return UINT32_C(0xd5300000)
4505 | (idSysReg << 5)
4506 | iRegDst;
4507}
4508
4509
4510/**
4511 * A64: Encodes MSR (for writing a GPR to a system register).
4512 *
4513 * @returns The encoded instruction.
4514 * @param iRegSrc The register which value to write. SP is NOT valid.
4515 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4516 * IPRT specific format, of the register to write.
4517 */
4518DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
4519{
4520 Assert(iRegSrc < 32);
4521 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4522
4523 /* Note. The top bit of idSysReg must always be set and is also set in
4524 0xd5100000, otherwise we'll be encoding a different instruction. */
4525 return UINT32_C(0xd5100000)
4526 | (idSysReg << 5)
4527 | iRegSrc;
4528}
4529
4530
4531/** @} */
4532
4533
4534/** @defgroup grp_rt_armv8_mkinstr_vec Vector Instruction Encoding Helpers
4535 * @ingroup grp_rt_armv8_mkinstr
4536 *
4537 * A few inlined functions and macros for assisting in encoding common ARMv8
4538 * Neon/SIMD instructions.
4539 *
4540 * @{ */
4541
4542/** Armv8 vector logical operation. */
4543typedef enum
4544{
4545 kArmv8VecInstrLogicOp_And = 0, /**< AND */
4546 kArmv8VecInstrLogicOp_Bic = RT_BIT_32(22), /**< BIC */
4547 kArmv8VecInstrLogicOp_Orr = RT_BIT_32(23), /**< ORR */
4548 kArmv8VecInstrLogicOp_Orn = RT_BIT_32(23) | RT_BIT_32(22), /**< ORN */
4549 kArmv8VecInstrLogicOp_Eor = RT_BIT_32(29), /**< EOR */
4550 kArmv8VecInstrLogicOp_Bsl = RT_BIT_32(29) | RT_BIT_32(22), /**< BSL */
4551 kArmv8VecInstrLogicOp_Bit = RT_BIT_32(29) | RT_BIT_32(23), /**< BIT */
4552 kArmv8VecInstrLogicOp_Bif = RT_BIT_32(29) | RT_BIT_32(23) | RT_BIT_32(22) /**< BIF */
4553} ARMV8INSTRVECLOGICOP;
4554
4555
4556/**
4557 * A64: Encodes logical instruction (vector, register).
4558 *
4559 * @returns The encoded instruction.
4560 * @param enmOp The operation to encode.
4561 * @param iVecRegDst The vector register to put the result into.
4562 * @param iVecRegSrc1 The 1st source register.
4563 * @param iVecRegSrc2 The 2nd source register.
4564 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4565 * or just the low 64-bit (false).
4566 */
4567DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrLogical(ARMV8INSTRVECLOGICOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4568 bool f128Bit = true)
4569{
4570 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4571
4572 return UINT32_C(0x0e201c00)
4573 | (uint32_t)enmOp
4574 | ((uint32_t)f128Bit << 30)
4575 | (iVecRegSrc2 << 16)
4576 | (iVecRegSrc1 << 5)
4577 | iVecRegDst;
4578}
4579
4580
4581/**
4582 * A64: Encodes ORR (vector, register).
4583 *
4584 * @returns The encoded instruction.
4585 * @param iVecRegDst The vector register to put the result into.
4586 * @param iVecRegSrc1 The 1st source register.
4587 * @param iVecRegSrc2 The 2nd source register.
4588 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4589 * or just the low 64-bit (false).
4590 */
4591DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrOrr(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4592 bool f128Bit = true)
4593{
4594 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Orr, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
4595}
4596
4597
4598/**
4599 * A64: Encodes EOR (vector, register).
4600 *
4601 * @returns The encoded instruction.
4602 * @param iVecRegDst The vector register to put the result into.
4603 * @param iVecRegSrc1 The 1st source register.
4604 * @param iVecRegSrc2 The 2nd source register.
4605 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4606 * or just the low 64-bit (false).
4607 */
4608DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrEor(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4609 bool f128Bit = true)
4610{
4611 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Eor, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
4612}
4613
4614
4615/**
4616 * A64: Encodes AND (vector, register).
4617 *
4618 * @returns The encoded instruction.
4619 * @param iVecRegDst The vector register to put the result into.
4620 * @param iVecRegSrc1 The 1st source register.
4621 * @param iVecRegSrc2 The 2nd source register.
4622 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4623 * or just the low 64-bit (false).
4624 */
4625DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAnd(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4626 bool f128Bit = true)
4627{
4628 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_And, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
4629}
4630
4631
4632/** Armv8 UMOV/INS vector element size. */
4633typedef enum ARMV8INSTRUMOVINSSZ
4634{
4635 kArmv8InstrUmovInsSz_U8 = 0, /**< Byte. */
4636 kArmv8InstrUmovInsSz_U16 = 1, /**< Halfword. */
4637 kArmv8InstrUmovInsSz_U32 = 2, /**< 32-bit. */
4638 kArmv8InstrUmovInsSz_U64 = 3 /**< 64-bit (only valid when the destination is a 64-bit register. */
4639} ARMV8INSTRUMOVINSSZ;
4640
4641
4642/**
4643 * A64: Encodes UMOV (vector, register).
4644 *
4645 * @returns The encoded instruction.
4646 * @param iRegDst The register to put the result into.
4647 * @param iVecRegSrc The vector source register.
4648 * @param idxElem The element index.
4649 * @param enmSz Element size of the source vector register.
4650 * @param fDst64Bit Flag whether the destination register is 64-bit (true) or 32-bit (false).
4651 */
4652DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUmov(uint32_t iRegDst, uint32_t iVecRegSrc, uint8_t idxElem,
4653 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64, bool fDst64Bit = true)
4654{
4655 Assert(iRegDst < 32); Assert(iVecRegSrc < 32);
4656 Assert((fDst64Bit && enmSz == kArmv8InstrUmovInsSz_U64) || (!fDst64Bit && enmSz != kArmv8InstrUmovInsSz_U64));
4657 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
4658 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
4659 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
4660 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
4661
4662 return UINT32_C(0x0e003c00)
4663 | ((uint32_t)fDst64Bit << 30)
4664 | ((uint32_t)idxElem << (16 + enmSz + 1))
4665 | (RT_BIT_32(enmSz) << 16)
4666 | (iVecRegSrc << 5)
4667 | iRegDst;
4668}
4669
4670
4671/**
4672 * A64: Encodes INS (vector, register).
4673 *
4674 * @returns The encoded instruction.
4675 * @param iVecRegDst The vector register to put the result into.
4676 * @param iRegSrc The source register.
4677 * @param idxElem The element index for the destination.
4678 * @param enmSz Element size of the source vector register.
4679 *
4680 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
4681 */
4682DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrIns(uint32_t iVecRegDst, uint32_t iRegSrc, uint8_t idxElem,
4683 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64)
4684{
4685 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
4686 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
4687 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
4688 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
4689 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
4690
4691 return UINT32_C(0x4e001c00)
4692 | ((uint32_t)idxElem << (16 + enmSz + 1))
4693 | (RT_BIT_32(enmSz) << 16)
4694 | (iRegSrc << 5)
4695 | iVecRegDst;
4696}
4697
4698
4699/**
4700 * A64: Encodes DUP (vector, register).
4701 *
4702 * @returns The encoded instruction.
4703 * @param iVecRegDst The vector register to put the result into.
4704 * @param iRegSrc The source register (ZR is valid).
4705 * @param enmSz Element size of the source vector register.
4706 * @param f128Bit Flag whether the instruction operates on the whole 128-bit of the vector register (true) or
4707 * just the low 64-bit (false).
4708 *
4709 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
4710 */
4711DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrDup(uint32_t iVecRegDst, uint32_t iRegSrc, ARMV8INSTRUMOVINSSZ enmSz,
4712 bool f128Bit = true)
4713{
4714 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
4715 Assert( (enmSz == kArmv8InstrUmovInsSz_U8)
4716 || (enmSz == kArmv8InstrUmovInsSz_U16)
4717 || (enmSz == kArmv8InstrUmovInsSz_U32)
4718 || (enmSz == kArmv8InstrUmovInsSz_U64));
4719
4720 return UINT32_C(0x0e000c00)
4721 | ((uint32_t)f128Bit << 30)
4722 | (RT_BIT_32(enmSz) << 16)
4723 | (iRegSrc << 5)
4724 | iVecRegDst;
4725}
4726
4727
4728/** Armv8 vector compare to zero vector element size. */
4729typedef enum ARMV8INSTRVECCMPZEROSZ
4730{
4731 kArmv8InstrCmpZeroSz_S8 = 0, /**< Byte. */
4732 kArmv8InstrCmpZeroSz_S16 = 1, /**< Halfword. */
4733 kArmv8InstrCmpZeroSz_S32 = 2, /**< 32-bit. */
4734 kArmv8InstrCmpZeroSz_S64 = 3 /**< 64-bit. */
4735} ARMV8INSTRVECCMPZEROSZ;
4736
4737
4738/** Armv8 vector compare to zero vector operation. */
4739typedef enum ARMV8INSTRVECCMPZEROOP
4740{
4741 kArmv8InstrCmpZeroOp_Gt = 0, /**< Greater than. */
4742 kArmv8InstrCmpZeroOp_Ge = RT_BIT_32(29), /**< Greater than or equal to. */
4743 kArmv8InstrCmpZeroOp_Eq = RT_BIT_32(12), /**< Equal to. */
4744 kArmv8InstrCmpZeroOp_Le = RT_BIT_32(29) | RT_BIT_32(12) /**< Lower than or equal to. */
4745} ARMV8INSTRVECCMPZEROOP;
4746
4747
4748/**
4749 * A64: Encodes CMGT, CMGE, CMEQ or CMLE against zero (vector, register).
4750 *
4751 * @returns The encoded instruction.
4752 * @param iVecRegDst The vector register to put the result into.
4753 * @param iVecRegSrc The vector source register.
4754 * @param enmSz Vector element size.
4755 * @param enmOp The compare operation against to encode.
4756 */
4757DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpToZero(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECCMPZEROSZ enmSz,
4758 ARMV8INSTRVECCMPZEROOP enmOp)
4759{
4760 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4761
4762 return UINT32_C(0x5e208800)
4763 | ((uint32_t)enmSz << 22)
4764 | (RT_BIT_32(enmSz) << 16)
4765 | (iVecRegSrc << 5)
4766 | iVecRegDst
4767 | (uint32_t)enmOp;
4768}
4769
4770
4771/**
4772 * A64: Encodes CNT (vector, register).
4773 *
4774 * @returns The encoded instruction.
4775 * @param iVecRegDst The vector register to put the result into.
4776 * @param iVecRegSrc The vector source register.
4777 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4778 * or just the low 64-bit (false).
4779 */
4780DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCnt(uint32_t iVecRegDst, uint32_t iVecRegSrc, bool f128Bit = true)
4781{
4782 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4783
4784 return UINT32_C(0x0e205800)
4785 | ((uint32_t)f128Bit << 30)
4786 | (iVecRegSrc << 5)
4787 | iVecRegDst;
4788}
4789
4790
4791/** Armv8 vector unsigned sum long across vector element size. */
4792typedef enum ARMV8INSTRVECUADDLVSZ
4793{
4794 kArmv8InstrUAddLVSz_8B = 0, /**< 8 x 8-bit. */
4795 kArmv8InstrUAddLVSz_16B = RT_BIT_32(30), /**< 16 x 8-bit. */
4796 kArmv8InstrUAddLVSz_4H = 1, /**< 4 x 16-bit. */
4797 kArmv8InstrUAddLVSz_8H = RT_BIT_32(30) | 1, /**< 8 x 16-bit. */
4798 kArmv8InstrUAddLVSz_4S = RT_BIT_32(30) | 2 /**< 4 x 32-bit. */
4799} ARMV8INSTRVECUADDLVSZ;
4800
4801
4802/**
4803 * A64: Encodes UADDLV (vector, register).
4804 *
4805 * @returns The encoded instruction.
4806 * @param iVecRegDst The vector register to put the result into.
4807 * @param iVecRegSrc The vector source register.
4808 * @param enmSz Element size.
4809 */
4810DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUAddLV(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECUADDLVSZ enmSz)
4811{
4812 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4813
4814 return UINT32_C(0x2e303800)
4815 | ((uint32_t)enmSz)
4816 | (iVecRegSrc << 5)
4817 | iVecRegDst;
4818}
4819
4820
4821/** Armv8 USHR/USRA/URSRA/SSHR/SRSA/SSHR vector element size. */
4822typedef enum ARMV8INSTRUSHIFTSZ
4823{
4824 kArmv8InstrShiftSz_U8 = 8, /**< Byte. */
4825 kArmv8InstrShiftSz_U16 = 16, /**< Halfword. */
4826 kArmv8InstrShiftSz_U32 = 32, /**< 32-bit. */
4827 kArmv8InstrShiftSz_U64 = 64 /**< 64-bit. */
4828} ARMV8INSTRUSHIFTSZ;
4829
4830/**
4831 * A64: Encodes USHR/USRA/URSRA/SSHR/SRSA/SSHR (vector, register).
4832 *
4833 * @returns The encoded instruction.
4834 * @param iVecRegDst The vector register to put the result into.
4835 * @param iVecRegSrc The vector source register.
4836 * @param cShift Number of bits to shift.
4837 * @param enmSz Element size.
4838 * @param fUnsigned Flag whether this a signed or unsigned shift,
4839 * @param fRound Flag whether this is the rounding shift variant.
4840 * @param fAccum Flag whether this is the accumulate shift variant.
4841 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4842 * or just the low 64-bit (false).
4843 */
4844DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShrImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
4845 bool fUnsigned = true, bool fRound = false, bool fAccum = false, bool f128Bit = true)
4846{
4847 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4848 Assert( cShift >= 1
4849 && ( (enmSz == kArmv8InstrShiftSz_U8 && cShift <= 8)
4850 || (enmSz == kArmv8InstrShiftSz_U16 && cShift <= 16)
4851 || (enmSz == kArmv8InstrShiftSz_U32 && cShift <= 32)
4852 || (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
4853
4854 return UINT32_C(0x0f000400)
4855 | ((uint32_t)f128Bit << 30)
4856 | ((uint32_t)fUnsigned << 29)
4857 | ((((uint32_t)enmSz << 1) - cShift) << 16)
4858 | ((uint32_t)fRound << 13)
4859 | ((uint32_t)fAccum << 12)
4860 | (iVecRegSrc << 5)
4861 | iVecRegDst;
4862}
4863
4864
4865/**
4866 * A64: Encodes SHL (vector, register).
4867 *
4868 * @returns The encoded instruction.
4869 * @param iVecRegDst The vector register to put the result into.
4870 * @param iVecRegSrc The vector source register.
4871 * @param cShift Number of bits to shift.
4872 * @param enmSz Element size.
4873 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4874 * or just the low 64-bit (false).
4875 */
4876DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
4877 bool f128Bit = true)
4878{
4879 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4880 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
4881 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
4882 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
4883 || (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
4884
4885 return UINT32_C(0x0f005400)
4886 | ((uint32_t)f128Bit << 30)
4887 | (((uint32_t)enmSz | cShift) << 16)
4888 | (iVecRegSrc << 5)
4889 | iVecRegDst;
4890}
4891
4892
4893/** Armv8 vector arith ops element size. */
4894typedef enum ARMV8INSTRVECARITHSZ
4895{
4896 kArmv8VecInstrArithSz_8 = 0, /**< 8-bit. */
4897 kArmv8VecInstrArithSz_16 = 1, /**< 16-bit. */
4898 kArmv8VecInstrArithSz_32 = 2, /**< 32-bit. */
4899 kArmv8VecInstrArithSz_64 = 3 /**< 64-bit. */
4900} ARMV8INSTRVECARITHSZ;
4901
4902
4903/** Armv8 vector arithmetic operation. */
4904typedef enum
4905{
4906 kArmv8VecInstrArithOp_Add = RT_BIT_32(15), /**< ADD */
4907 kArmv8VecInstrArithOp_Sub = RT_BIT_32(29) | RT_BIT_32(15), /**< SUB */
4908 kArmv8VecInstrArithOp_UnsignSat_Add = RT_BIT_32(29) | RT_BIT_32(11), /**< UQADD */
4909 kArmv8VecInstrArithOp_UnsignSat_Sub = RT_BIT_32(29) | RT_BIT_32(13) | RT_BIT_32(11), /**< UQSUB */
4910 kArmv8VecInstrArithOp_SignSat_Add = RT_BIT_32(11), /**< SQADD */
4911 kArmv8VecInstrArithOp_SignSat_Sub = RT_BIT_32(13) | RT_BIT_32(11), /**< SQSUB */
4912 kArmv8VecInstrArithOp_Mul = RT_BIT_32(15) | RT_BIT_32(12) | RT_BIT_32(11) /**< MUL */
4913} ARMV8INSTRVECARITHOP;
4914
4915
4916/**
4917 * A64: Encodes an arithmetic operation (vector, register).
4918 *
4919 * @returns The encoded instruction.
4920 * @param enmOp The operation to encode.
4921 * @param iVecRegDst The vector register to put the result into.
4922 * @param iVecRegSrc1 The first vector source register.
4923 * @param iVecRegSrc2 The second vector source register.
4924 * @param enmSz Element size.
4925 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4926 * or just the low 64-bit (false).
4927 */
4928DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrArithOp(ARMV8INSTRVECARITHOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4929 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4930{
4931 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4932
4933 return UINT32_C(0x0e200400)
4934 | (uint32_t)enmOp
4935 | ((uint32_t)f128Bit << 30)
4936 | ((uint32_t)enmSz << 22)
4937 | (iVecRegSrc2 << 16)
4938 | (iVecRegSrc1 << 5)
4939 | iVecRegDst;
4940}
4941
4942
4943/** Armv8 vector compare operation. */
4944typedef enum ARMV8VECINSTRCMPOP
4945{
4946 /* U insn[15:10] */
4947 kArmv8VecInstrCmpOp_Gt = UINT32_C(0x3400), /**< Greater than (>) (signed) */
4948 kArmv8VecInstrCmpOp_Ge = UINT32_C(0x3c00), /**< Greater or equal (>=) (signed) */
4949 kArmv8VecInstrCmpOp_Hi = RT_BIT_32(29) | UINT32_C(0x3400), /**< Greater than (>) (unsigned) */
4950 kArmv8VecInstrCmpOp_Hs = RT_BIT_32(29) | UINT32_C(0x3c00), /**< Greater or equal (>=) (unsigned) */
4951 kArmv8VecInstrCmpOp_Eq = RT_BIT_32(29) | UINT32_C(0x8c00) /**< Equal (==) (unsigned) */
4952} ARMV8VECINSTRCMPOP;
4953
4954/**
4955 * A64: Encodes CMEQ/CMGE/CMGT/CMHI/CMHS (register variant) (vector, register).
4956 *
4957 * @returns The encoded instruction.
4958 * @param enmOp The operation to perform.
4959 * @param iVecRegDst The vector register to put the result into.
4960 * @param iVecRegSrc1 The first vector source register.
4961 * @param iVecRegSrc2 The second vector source register.
4962 * @param enmSz Element size.
4963 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4964 * or just the low 64-bit (false).
4965 */
4966DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmp(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4967 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4968{
4969 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4970
4971 return UINT32_C(0x0e200000)
4972 | ((uint32_t)f128Bit << 30)
4973 | ((uint32_t)enmSz << 22)
4974 | (iVecRegSrc2 << 16)
4975 | ((uint32_t)enmOp)
4976 | (iVecRegSrc1 << 5)
4977 | iVecRegDst;
4978}
4979
4980
4981/** Armv8 vector compare against zero operation. */
4982typedef enum ARMV8VECINSTRCMPZEROOP
4983{
4984 /* U insn[15:10] */
4985 kArmv8VecInstrCmpZeroOp_Gt = UINT32_C(0x8800), /**< Greater than zero (>) (signed) */
4986 kArmv8VecInstrCmpZeroOp_Eq = UINT32_C(0x9800), /**< Equal to zero (==) */
4987 kArmv8VecInstrCmpZeroOp_Lt = UINT32_C(0xa800), /**< Lower than zero (>=) (signed) */
4988 kArmv8VecInstrCmpZeroOp_Ge = RT_BIT_32(29) | UINT32_C(0x8800), /**< Greater or equal to zero (>=) (signed) */
4989 kArmv8VecInstrCmpZeroOp_Le = RT_BIT_32(29) | UINT32_C(0x9800) /**< Lower or equal to zero (<=) (signed) */
4990} ARMV8VECINSTRCMPZEROOP;
4991
4992/**
4993 * A64: Encodes CMEQ/CMGE/CMGT/CMLE/CMLT (zero variant) (vector, register).
4994 *
4995 * @returns The encoded instruction.
4996 * @param enmOp The operation to perform.
4997 * @param iVecRegDst The vector register to put the result into.
4998 * @param iVecRegSrc The first vector source register.
4999 * @param enmSz Element size.
5000 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5001 * or just the low 64-bit (false).
5002 */
5003DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpAgainstZero(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc,
5004 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5005{
5006 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5007
5008 return UINT32_C(0x0e200000)
5009 | ((uint32_t)f128Bit << 30)
5010 | ((uint32_t)enmSz << 22)
5011 | ((uint32_t)enmOp)
5012 | (iVecRegSrc << 5)
5013 | iVecRegDst;
5014}
5015
5016
5017/** Armv8 [Signed,Unsigned] Extract {Unsigned} operation. */
5018typedef enum
5019{
5020 kArmv8VecInstrQxtnOp_Sqxtn = RT_BIT_32(14), /**< SQXTN */
5021 kArmv8VecInstrQxtnOp_Sqxtun = RT_BIT_32(29) | RT_BIT_32(13), /**< SQXTUN */
5022 kArmv8VecInstrQxtnOp_Uqxtn = RT_BIT_32(29) | RT_BIT_32(14) /**< UQXTN */
5023} ARMV8INSTRVECQXTNOP;
5024
5025/**
5026 * A64: Encodes SQXTN/SQXTN2/UQXTN/UQXTN2/SQXTUN/SQXTUN2 (vector, register).
5027 *
5028 * @returns The encoded instruction.
5029 * @param enmOp The operation to perform.
5030 * @param fUpper Flag whether to write the result to the lower (false) or upper (true) half of the destinatiom register.
5031 * @param iVecRegDst The vector register to put the result into.
5032 * @param iVecRegSrc The first vector source register.
5033 * @param enmSz Element size.
5034 */
5035DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrQxtn(ARMV8INSTRVECQXTNOP enmOp, bool fUpper, uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECARITHSZ enmSz)
5036{
5037 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5038
5039 return UINT32_C(0x0e210800)
5040 | ((uint32_t)enmOp)
5041 | ((uint32_t)fUpper << 30)
5042 | ((uint32_t)enmSz << 22)
5043 | (iVecRegSrc << 5)
5044 | iVecRegDst;
5045}
5046
5047
5048/** Armv8 floating point size. */
5049typedef enum
5050{
5051 kArmv8VecInstrFpSz_2x_Single = 0, /**< 2x single precision values in the low 64-bit of the 128-bit register. */
5052 kArmv8VecInstrFpSz_4x_Single = RT_BIT_32(30), /**< 4x single precision values in the 128-bit register. */
5053 kArmv8VecInstrFpSz_2x_Double = RT_BIT_32(30) | RT_BIT_32(22) /**< 2x double precision values in the 128-bit register. */
5054} ARMV8INSTRVECFPSZ;
5055
5056
5057/** Armv8 3 operand floating point operation. */
5058typedef enum
5059{
5060 /* insn[29] insn[23] insn[15:11] */
5061 kArmv8VecInstrFpOp_Add = UINT32_C(0xd000), /**< FADD */
5062 kArmv8VecInstrFpOp_Sub = RT_BIT_32(23) | UINT32_C(0xd000), /**< FADD */
5063 kArmv8VecInstrFpOp_AddPairwise = RT_BIT_32(29) | UINT32_C(0xd000), /**< FADDP */
5064 kArmv8VecInstrFpOp_Mul = RT_BIT_32(29) | UINT32_C(0xd800), /**< FMUL */
5065 kArmv8VecInstrFpOp_Div = RT_BIT_32(29) | UINT32_C(0xf800), /**< FDIV */
5066
5067 kArmv8VecInstrFpOp_Max = UINT32_C(0xf000), /**< FMAX */
5068 kArmv8VecInstrFpOp_MaxNumber = UINT32_C(0xc000), /**< FMAXNM */
5069 kArmv8VecInstrFpOp_MaxNumberPairwise = RT_BIT_32(29) | UINT32_C(0xc000), /**< FMAXNMP */
5070 kArmv8VecInstrFpOp_MaxPairwise = RT_BIT_32(29) | UINT32_C(0xf000), /**< FMAXP */
5071
5072 kArmv8VecInstrFpOp_Min = RT_BIT_32(23) | UINT32_C(0xf000), /**< FMIN */
5073 kArmv8VecInstrFpOp_MinNumber = RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNM */
5074 kArmv8VecInstrFpOp_MinNumberPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNMP */
5075 kArmv8VecInstrFpOp_MinPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xf000), /**< FMINP */
5076
5077 kArmv8VecInstrFpOp_Fmla = UINT32_C(0xc800), /**< FMLA */
5078 kArmv8VecInstrFpOp_Fmls = RT_BIT_32(23) | UINT32_C(0xc800) /**< FMLS */
5079} ARMV8INSTRVECFPOP;
5080
5081/**
5082 * A64: Encodes a 3 operand floating point operation (vector, register).
5083 *
5084 * @returns The encoded instruction.
5085 * @param enmOp The operation to perform.
5086 * @param enmSz The size to operate on.
5087 * @param iVecRegDst The vector register to put the result into.
5088 * @param iVecRegSrc1 The first vector source register.
5089 * @param iVecRegSrc2 The second vector source register.
5090 */
5091DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrFp3Op(ARMV8INSTRVECFPOP enmOp, ARMV8INSTRVECFPSZ enmSz, uint32_t iVecRegDst,
5092 uint32_t iVecRegSrc1, uint32_t iVecRegSrc2)
5093{
5094 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5095
5096 return UINT32_C(0x0e200400)
5097 | ((uint32_t)enmOp)
5098 | ((uint32_t)enmSz)
5099 | (iVecRegSrc2 << 16)
5100 | (iVecRegSrc1 << 5)
5101 | iVecRegDst;
5102}
5103
5104
5105/** @} */
5106
5107#endif /* !dtrace && __cplusplus */
5108
5109/** @} */
5110
5111#endif /* !IPRT_INCLUDED_armv8_h */
5112
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