VirtualBox

source: vbox/trunk/include/iprt/armv8.h@ 106880

Last change on this file since 106880 was 106463, checked in by vboxsync, 6 weeks ago

VMM: Filter out some more PMU register accesses Windows/ARM is doing until we have a proper PMU emulation, bugref:10778
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/cdefs.h>
44# ifndef RT_IN_ASSEMBLER
45# include <iprt/types.h>
46# include <iprt/assert.h>
47# endif
48# include <iprt/assertcompile.h>
49#else
50# pragma D depends_on library vbox-types.d
51#endif
52
53/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
54 * @ingroup grp_rt
55 * @{
56 */
57
58/** @name The AArch64 register encoding - deprecated.
59 * @deprecated Use ARMV8_A64_REG_XXX instead.
60 * @todo correct code and drop these remaining ones.
61 * @{ */
62#define ARMV8_AARCH64_REG_X0 0
63#define ARMV8_AARCH64_REG_X1 1
64#define ARMV8_AARCH64_REG_X2 2
65#define ARMV8_AARCH64_REG_X3 3
66#define ARMV8_AARCH64_REG_ZR 31
67/** @} */
68
69/** @name The AArch64 general purpose register encoding.
70 * @{ */
71#define ARMV8_A64_REG_X0 0
72#define ARMV8_A64_REG_X1 1
73#define ARMV8_A64_REG_X2 2
74#define ARMV8_A64_REG_X3 3
75#define ARMV8_A64_REG_X4 4
76#define ARMV8_A64_REG_X5 5
77#define ARMV8_A64_REG_X6 6
78#define ARMV8_A64_REG_X7 7
79#define ARMV8_A64_REG_X8 8
80#define ARMV8_A64_REG_X9 9
81#define ARMV8_A64_REG_X10 10
82#define ARMV8_A64_REG_X11 11
83#define ARMV8_A64_REG_X12 12
84#define ARMV8_A64_REG_X13 13
85#define ARMV8_A64_REG_X14 14
86#define ARMV8_A64_REG_X15 15
87#define ARMV8_A64_REG_X16 16
88#define ARMV8_A64_REG_X17 17
89#define ARMV8_A64_REG_X18 18
90#define ARMV8_A64_REG_X19 19
91#define ARMV8_A64_REG_X20 20
92#define ARMV8_A64_REG_X21 21
93#define ARMV8_A64_REG_X22 22
94#define ARMV8_A64_REG_X23 23
95#define ARMV8_A64_REG_X24 24
96#define ARMV8_A64_REG_X25 25
97#define ARMV8_A64_REG_X26 26
98#define ARMV8_A64_REG_X27 27
99#define ARMV8_A64_REG_X28 28
100#define ARMV8_A64_REG_X29 29
101#define ARMV8_A64_REG_X30 30
102/** @} */
103
104/** @name The AArch64 32-bit general purpose register names.
105 * @{ */
106#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
107#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
108#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
109#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
110#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
111#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
112#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
113#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
114#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
115#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
116#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
117#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
118#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
119#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
120#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
121#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
122#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
123#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
124#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
125#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
126#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
127#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
128#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
129#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
130#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
131#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
132#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
133#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
134#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
135#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
136#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
137/** @} */
138
139/** @name The AArch64 NEON scalar register encoding.
140 * @{ */
141#define ARMV8_A64_REG_Q0 0
142#define ARMV8_A64_REG_Q1 1
143#define ARMV8_A64_REG_Q2 2
144#define ARMV8_A64_REG_Q3 3
145#define ARMV8_A64_REG_Q4 4
146#define ARMV8_A64_REG_Q5 5
147#define ARMV8_A64_REG_Q6 6
148#define ARMV8_A64_REG_Q7 7
149#define ARMV8_A64_REG_Q8 8
150#define ARMV8_A64_REG_Q9 9
151#define ARMV8_A64_REG_Q10 10
152#define ARMV8_A64_REG_Q11 11
153#define ARMV8_A64_REG_Q12 12
154#define ARMV8_A64_REG_Q13 13
155#define ARMV8_A64_REG_Q14 14
156#define ARMV8_A64_REG_Q15 15
157#define ARMV8_A64_REG_Q16 16
158#define ARMV8_A64_REG_Q17 17
159#define ARMV8_A64_REG_Q18 18
160#define ARMV8_A64_REG_Q19 19
161#define ARMV8_A64_REG_Q20 20
162#define ARMV8_A64_REG_Q21 21
163#define ARMV8_A64_REG_Q22 22
164#define ARMV8_A64_REG_Q23 23
165#define ARMV8_A64_REG_Q24 24
166#define ARMV8_A64_REG_Q25 25
167#define ARMV8_A64_REG_Q26 26
168#define ARMV8_A64_REG_Q27 27
169#define ARMV8_A64_REG_Q28 28
170#define ARMV8_A64_REG_Q29 29
171#define ARMV8_A64_REG_Q30 30
172#define ARMV8_A64_REG_Q31 31
173/** @} */
174
175/** @name The AArch64 NEON vector register encoding.
176 * @{ */
177#define ARMV8_A64_REG_V0 ARMV8_A64_REG_Q0
178#define ARMV8_A64_REG_V1 ARMV8_A64_REG_Q1
179#define ARMV8_A64_REG_V2 ARMV8_A64_REG_Q2
180#define ARMV8_A64_REG_V3 ARMV8_A64_REG_Q3
181#define ARMV8_A64_REG_V4 ARMV8_A64_REG_Q4
182#define ARMV8_A64_REG_V5 ARMV8_A64_REG_Q5
183#define ARMV8_A64_REG_V6 ARMV8_A64_REG_Q6
184#define ARMV8_A64_REG_V7 ARMV8_A64_REG_Q7
185#define ARMV8_A64_REG_V8 ARMV8_A64_REG_Q8
186#define ARMV8_A64_REG_V9 ARMV8_A64_REG_Q9
187#define ARMV8_A64_REG_V10 ARMV8_A64_REG_Q10
188#define ARMV8_A64_REG_V11 ARMV8_A64_REG_Q11
189#define ARMV8_A64_REG_V12 ARMV8_A64_REG_Q12
190#define ARMV8_A64_REG_V13 ARMV8_A64_REG_Q13
191#define ARMV8_A64_REG_V14 ARMV8_A64_REG_Q14
192#define ARMV8_A64_REG_V15 ARMV8_A64_REG_Q15
193#define ARMV8_A64_REG_V16 ARMV8_A64_REG_Q16
194#define ARMV8_A64_REG_V17 ARMV8_A64_REG_Q17
195#define ARMV8_A64_REG_V18 ARMV8_A64_REG_Q18
196#define ARMV8_A64_REG_V19 ARMV8_A64_REG_Q19
197#define ARMV8_A64_REG_V20 ARMV8_A64_REG_Q20
198#define ARMV8_A64_REG_V21 ARMV8_A64_REG_Q21
199#define ARMV8_A64_REG_V22 ARMV8_A64_REG_Q22
200#define ARMV8_A64_REG_V23 ARMV8_A64_REG_Q23
201#define ARMV8_A64_REG_V24 ARMV8_A64_REG_Q24
202#define ARMV8_A64_REG_V25 ARMV8_A64_REG_Q25
203#define ARMV8_A64_REG_V26 ARMV8_A64_REG_Q26
204#define ARMV8_A64_REG_V27 ARMV8_A64_REG_Q27
205#define ARMV8_A64_REG_V28 ARMV8_A64_REG_Q28
206#define ARMV8_A64_REG_V29 ARMV8_A64_REG_Q29
207#define ARMV8_A64_REG_V30 ARMV8_A64_REG_Q30
208#define ARMV8_A64_REG_V31 ARMV8_A64_REG_Q31
209/** @} */
210
211/** @name The AArch64 register 31.
212 * @note Register 31 typically refers to the zero register, but can also in
213 * select case (by instruction and opecode field) refer the to stack
214 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
215 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
216 * 31 will be the zero register.
217 * @{ */
218/** The stack pointer. */
219#define ARMV8_A64_REG_SP 31
220/** The zero register. Reads as zero, writes ignored. */
221#define ARMV8_A64_REG_XZR 31
222/** The zero register, the 32-bit register name. */
223#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
224/** @} */
225
226/** @name AArch64 register aliases
227 * @{ */
228/** The link register is typically mapped to x30 as that's the default pick of
229 * the RET instruction. */
230#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
231/** Frame base pointer is typically mapped to x29. */
232#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
233/** @} */
234
235
236/** @name System register encoding.
237 * @{
238 */
239/** Mask for the op0 part of an MSR/MRS instruction */
240#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
241/** Shift for the op0 part of an MSR/MRS instruction */
242#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
243/** Returns the op0 part of the given MRS/MSR instruction. */
244#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
245/** Mask for the op1 part of an MSR/MRS instruction */
246#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
247/** Shift for the op1 part of an MSR/MRS instruction */
248#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
249/** Returns the op1 part of the given MRS/MSR instruction. */
250#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
251/** Mask for the CRn part of an MSR/MRS instruction */
252#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
253 | RT_BIT_32(15) )
254/** Shift for the CRn part of an MSR/MRS instruction */
255#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
256/** Returns the CRn part of the given MRS/MSR instruction. */
257#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
258/** Mask for the CRm part of an MSR/MRS instruction */
259#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
260 | RT_BIT_32(11) )
261/** Shift for the CRm part of an MSR/MRS instruction */
262#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
263/** Returns the CRn part of the given MRS/MSR instruction. */
264#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
265/** Mask for the op2 part of an MSR/MRS instruction */
266#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
267/** Shift for the op2 part of an MSR/MRS instruction */
268#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
269/** Returns the op2 part of the given MRS/MSR instruction. */
270#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
271/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
272#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
273 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
274 | ARMV8_AARCH64_SYSREG_OP2_MASK)
275/** @} */
276
277/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
278 * IPRT specific and not part of the ARMv8 specification.
279 * @{ */
280#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
281 (uint16_t)( (((a_Op0) & 0x3) << 14) \
282 | (((a_Op1) & 0x7) << 11) \
283 | (((a_CRn) & 0xf) << 7) \
284 | (((a_CRm) & 0xf) << 3) \
285 | ((a_Op2) & 0x7))
286/** Returns the internal system register ID from the given MRS/MSR instruction. */
287#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
288 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
289 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
290 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
291 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
292 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
293/** Encodes the given system register ID in the given MSR/MRS instruction. */
294#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
295 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
296/** @} */
297
298
299/** @name System register IDs.
300 * @{ */
301/** OSDTRRX_EL1 register - RW. */
302#define ARMV8_AARCH64_SYSREG_OSDTRRX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 0, 2)
303/** MDSCR_EL1 - RW. */
304#define ARMV8_AARCH64_SYSREG_MDSCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 2)
305/** DBGBVR<0..15>_EL1 register - RW. */
306#define ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 4)
307/** DBGBCR<0..15>_EL1 register - RW. */
308#define ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 5)
309/** DBGWVR<0..15>_EL1 register - RW. */
310#define ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 6)
311/** DBGWCR<0..15>_EL1 register - RW. */
312#define ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 7)
313/** MDCCINT_EL1 register - RW. */
314#define ARMV8_AARCH64_SYSREG_MDCCINT_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 0)
315/** OSDTRTX_EL1 register - RW. */
316#define ARMV8_AARCH64_SYSREG_OSDTRTX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 3, 2)
317/** OSECCR_EL1 register - RW. */
318#define ARMV8_AARCH64_SYSREG_OSECCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 6, 2)
319/** MDRAR_EL1 register - RO. */
320#define ARMV8_AARCH64_SYSREG_MDRAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 0)
321/** OSLAR_EL1 register - WO. */
322#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
323/** OSLSR_EL1 register - RO. */
324#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
325/** OSDLR_EL1 register - RW. */
326#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
327
328/** MIDR_EL1 register - RO. */
329#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
330/** MIPDR_EL1 register - RO. */
331#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
332/** REVIDR_EL1 register - RO. */
333#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
334/** ID_PFR0_EL1 register - RO. */
335#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
336/** ID_PFR1_EL1 register - RO. */
337#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
338/** ID_DFR0_EL1 register - RO. */
339#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
340/** ID_AFR0_EL1 register - RO. */
341#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
342/** ID_MMFR0_EL1 register - RO. */
343#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
344/** ID_MMFR1_EL1 register - RO. */
345#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
346/** ID_MMFR2_EL1 register - RO. */
347#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
348/** ID_MMFR3_EL1 register - RO. */
349#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
350
351/** ID_ISAR0_EL1 register - RO. */
352#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
353/** ID_ISAR1_EL1 register - RO. */
354#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
355/** ID_ISAR2_EL1 register - RO. */
356#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
357/** ID_ISAR3_EL1 register - RO. */
358#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
359/** ID_ISAR4_EL1 register - RO. */
360#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
361/** ID_ISAR5_EL1 register - RO. */
362#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
363/** ID_MMFR4_EL1 register - RO. */
364#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
365/** ID_ISAR6_EL1 register - RO. */
366#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
367
368/** MVFR0_EL1 register - RO. */
369#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
370/** MVFR1_EL1 register - RO. */
371#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
372/** MVFR2_EL1 register - RO. */
373#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
374/** ID_PFR2_EL1 register - RO. */
375#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
376/** ID_DFR1_EL1 register - RO. */
377#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
378/** ID_MMFR5_EL1 register - RO. */
379#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
380
381/** ID_AA64PFR0_EL1 register - RO. */
382#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
383/** ID_AA64PFR0_EL1 register - RO. */
384#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
385/** ID_AA64ZFR0_EL1 register - RO. */
386#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
387/** ID_AA64SMFR0_EL1 register - RO. */
388#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
389
390/** ID_AA64DFR0_EL1 register - RO. */
391#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
392/** ID_AA64DFR0_EL1 register - RO. */
393#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
394/** ID_AA64AFR0_EL1 register - RO. */
395#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
396/** ID_AA64AFR1_EL1 register - RO. */
397#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
398
399/** ID_AA64ISAR0_EL1 register - RO. */
400#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
401/** ID_AA64ISAR1_EL1 register - RO. */
402#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
403/** ID_AA64ISAR2_EL1 register - RO. */
404#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
405
406/** ID_AA64MMFR0_EL1 register - RO. */
407#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
408/** ID_AA64MMFR1_EL1 register - RO. */
409#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
410/** ID_AA64MMFR2_EL1 register - RO. */
411#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
412
413/** SCTRL_EL1 register - RW. */
414#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
415/** ACTRL_EL1 register - RW. */
416#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
417/** CPACR_EL1 register - RW. */
418#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
419/** RGSR_EL1 register - RW. */
420#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
421/** GCR_EL1 register - RW. */
422#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
423
424/** ZCR_EL1 register - RW. */
425#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
426/** TRFCR_EL1 register - RW. */
427#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
428/** SMPRI_EL1 register - RW. */
429#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
430/** SMCR_EL1 register - RW. */
431#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
432
433/** TTBR0_EL1 register - RW. */
434#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
435/** TTBR1_EL1 register - RW. */
436#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
437/** TCR_EL1 register - RW. */
438#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
439
440/** APIAKeyLo_EL1 register - RW. */
441#define ARMV8_AARCH64_SYSREG_APIAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 0)
442/** APIAKeyHi_EL1 register - RW. */
443#define ARMV8_AARCH64_SYSREG_APIAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 1)
444/** APIBKeyLo_EL1 register - RW. */
445#define ARMV8_AARCH64_SYSREG_APIBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 2)
446/** APIBKeyHi_EL1 register - RW. */
447#define ARMV8_AARCH64_SYSREG_APIBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 3)
448
449/** APDAKeyLo_EL1 register - RW. */
450#define ARMV8_AARCH64_SYSREG_APDAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 0)
451/** APDAKeyHi_EL1 register - RW. */
452#define ARMV8_AARCH64_SYSREG_APDAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 1)
453/** APDBKeyLo_EL1 register - RW. */
454#define ARMV8_AARCH64_SYSREG_APDBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 2)
455/** APDBKeyHi_EL1 register - RW. */
456#define ARMV8_AARCH64_SYSREG_APDBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 3)
457
458/** APGAKeyLo_EL1 register - RW. */
459#define ARMV8_AARCH64_SYSREG_APGAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 0)
460/** APGAKeyHi_EL1 register - RW. */
461#define ARMV8_AARCH64_SYSREG_APGAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 1)
462
463/** SPSR_EL1 register - RW. */
464#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
465/** ELR_EL1 register - RW. */
466#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
467
468/** SP_EL0 register - RW. */
469#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
470
471/** PSTATE.SPSel value. */
472#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
473/** PSTATE.CurrentEL value. */
474#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
475/** PSTATE.PAN value. */
476#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
477/** PSTATE.UAO value. */
478#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
479
480/** PSTATE.ALLINT value. */
481#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
482
483/** ICC_PMR_EL1 register - RW. */
484#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
485
486/** AFSR0_EL1 register - RW. */
487#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
488/** AFSR1_EL1 register - RW. */
489#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
490
491/** ESR_EL1 register - RW. */
492#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
493
494/** ERRIDR_EL1 register - RO. */
495#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
496/** ERRSELR_EL1 register - RW. */
497#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
498
499/** FAR_EL1 register - RW. */
500#define ARMV8_AARCH64_SYSREG_FAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 6, 0, 0)
501
502/** PAR_EL1 register - RW. */
503#define ARMV8_AARCH64_SYSREG_PAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 7, 4, 0)
504
505/** PMINTENCLR_EL1 register - RW. */
506#define ARMV8_AARCH64_SYSREG_PMINTENCLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 9, 14, 2)
507
508/** MAIR_EL1 register - RW. */
509#define ARMV8_AARCH64_SYSREG_MAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 2, 0)
510
511/** AMAIR_EL1 register - RW. */
512#define ARMV8_AARCH64_SYSREG_AMAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 3, 0)
513
514/** VBAR_EL1 register - RW. */
515#define ARMV8_AARCH64_SYSREG_VBAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 0, 0)
516
517/** ICC_IAR0_EL1 register - RO. */
518#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
519/** ICC_EOIR0_EL1 register - WO. */
520#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
521/** ICC_HPPIR0_EL1 register - WO. */
522#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
523/** ICC_BPR0_EL1 register - RW. */
524#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
525/** ICC_AP0R0_EL1 register - RW. */
526#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
527/** ICC_AP0R1_EL1 register - RW. */
528#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
529/** ICC_AP0R2_EL1 register - RW. */
530#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
531/** ICC_AP0R3_EL1 register - RW. */
532#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
533
534/** ICC_AP1R0_EL1 register - RW. */
535#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
536/** ICC_AP1R1_EL1 register - RW. */
537#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
538/** ICC_AP1R2_EL1 register - RW. */
539#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
540/** ICC_AP1R3_EL1 register - RW. */
541#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
542/** ICC_NMIAR1_EL1 register - RO. */
543#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
544
545/** ICC_DIR_EL1 register - WO. */
546#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
547/** ICC_RPR_EL1 register - RO. */
548#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
549/** ICC_SGI1R_EL1 register - WO. */
550#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
551/** ICC_ASGI1R_EL1 register - WO. */
552#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
553/** ICC_SGI0R_EL1 register - WO. */
554#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
555
556/** ICC_IAR1_EL1 register - RO. */
557#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
558/** ICC_EOIR1_EL1 register - WO. */
559#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
560/** ICC_HPPIR1_EL1 register - RO. */
561#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
562/** ICC_BPR1_EL1 register - RW. */
563#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
564/** ICC_CTLR_EL1 register - RW. */
565#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
566/** ICC_SRE_EL1 register - RW. */
567#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
568/** ICC_IGRPEN0_EL1 register - RW. */
569#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
570/** ICC_IGRPEN1_EL1 register - RW. */
571#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
572
573/** CONTEXTIDR_EL1 register - RW. */
574#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 1)
575/** TPIDR_EL1 register - RW. */
576#define ARMV8_AARCH64_SYSREG_TPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 4)
577
578/** CNTKCTL_EL1 register - RW. */
579#define ARMV8_AARCH64_SYSREG_CNTKCTL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 14, 1, 0)
580
581/** CSSELR_EL1 register - RW. */
582#define ARMV8_AARCH64_SYSREG_CSSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 2, 0, 0, 0)
583
584/** NZCV - Status Flags - ??. */
585#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
586/** DAIF - Interrupt Mask Bits - ??. */
587#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
588/** SVCR - Streaming Vector Control Register - ??. */
589#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
590/** DIT - Data Independent Timing - ??. */
591#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
592/** SSBS - Speculative Store Bypass Safe - ??. */
593#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
594/** TCO - Tag Check Override - ??. */
595#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
596
597/** FPCR register - RW. */
598#define ARMV8_AARCH64_SYSREG_FPCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 0)
599/** FPSR register - RW. */
600#define ARMV8_AARCH64_SYSREG_FPSR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 1)
601
602/** PMCR_EL0 register - RW. */
603#define ARMV8_AARCH64_SYSREG_PMCR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 0)
604/** PMCNTENSET_EL0 register - RW. */
605#define ARMV8_AARCH64_SYSREG_PMCNTENSET_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 1)
606/** PMCNTENCLR_EL0 register - RW. */
607#define ARMV8_AARCH64_SYSREG_PMCNTENCLR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 2)
608/** PMOVSCLR_EL0 register - RW. */
609#define ARMV8_AARCH64_SYSREG_PMOVSCLR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 3)
610
611/** PMCCNTR_EL0 register - RW. */
612#define ARMV8_AARCH64_SYSREG_PMCCNTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 13, 0)
613
614/** PMUSERENR_EL0 register - RW. */
615#define ARMV8_AARCH64_SYSREG_PMUSERENR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 14, 0)
616
617/** PMCCFILTR_EL0 register - RW. */
618#define ARMV8_AARCH64_SYSREG_PMCCFILTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 15, 7)
619
620/** ICC_SRE_EL2 register - RW. */
621#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 9, 5)
622
623/** TPIDR_EL0 register - RW. */
624#define ARMV8_AARCH64_SYSREG_TPIDR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 2)
625/** TPIDRRO_EL0 register - RO. */
626#define ARMV8_AARCH64_SYSREG_TPIDRRO_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 3)
627
628/** CNTFRQ_EL0 register - RW. */
629#define ARMV8_AARCH64_SYSREG_CNTFRQ_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 0)
630/** CNTVCT_EL0 register - RW. */
631#define ARMV8_AARCH64_SYSREG_CNTVCT_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 2)
632
633/** CNTP_TVAL_EL0 register - RW. */
634#define ARMV8_AARCH64_SYSREG_CNTP_TVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 0)
635/** CNTP_CTL_EL0 register - RW. */
636#define ARMV8_AARCH64_SYSREG_CNTP_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 1)
637/** CNTP_CVAL_EL0 register - RW. */
638#define ARMV8_AARCH64_SYSREG_CNTP_CVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 2)
639
640/** CNTV_CTL_EL0 register - RW. */
641#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
642
643/** VPIDR_EL2 register - RW. */
644#define ARMV8_AARCH64_SYSREG_VPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 0)
645/** VMPIDR_EL2 register - RW. */
646#define ARMV8_AARCH64_SYSREG_VMPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 5)
647
648/** SCTLR_EL2 register - RW. */
649#define ARMV8_AARCH64_SYSREG_SCTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 0)
650/** ACTLR_EL2 register - RW. */
651#define ARMV8_AARCH64_SYSREG_ACTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 1)
652
653/** HCR_EL2 register - RW. */
654#define ARMV8_AARCH64_SYSREG_HCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 0)
655/** MDCR_EL2 register - RW. */
656#define ARMV8_AARCH64_SYSREG_MDCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 1)
657/** CPTR_EL2 register - RW. */
658#define ARMV8_AARCH64_SYSREG_CPTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 2)
659/** HSTR_EL2 register - RW. */
660#define ARMV8_AARCH64_SYSREG_HSTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 3)
661/** HFGRTR_EL2 register - RW. */
662#define ARMV8_AARCH64_SYSREG_HFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 4)
663/** HFGWTR_EL2 register - RW. */
664#define ARMV8_AARCH64_SYSREG_HFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 5)
665/** HFGITR_EL2 register - RW. */
666#define ARMV8_AARCH64_SYSREG_HFGITR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 6)
667/** HACR_EL2 register - RW. */
668#define ARMV8_AARCH64_SYSREG_HACR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 7)
669
670/** ZCR_EL2 register - RW. */
671#define ARMV8_AARCH64_SYSREG_ZCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 0)
672/** TRFCR_EL2 register - RW. */
673#define ARMV8_AARCH64_SYSREG_TRFCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 1)
674/** HCRX_EL2 register - RW. */
675#define ARMV8_AARCH64_SYSREG_HCRX_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 2)
676
677/** SDER32_EL2 register - RW. */
678#define ARMV8_AARCH64_SYSREG_SDER32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 3, 0)
679
680/** TTBR0_EL2 register - RW. */
681#define ARMV8_AARCH64_SYSREG_TTBR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 0)
682/** TTBR1_EL2 register - RW. */
683#define ARMV8_AARCH64_SYSREG_TTBR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 1)
684/** TCR_EL2 register - RW. */
685#define ARMV8_AARCH64_SYSREG_TCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 2)
686
687/** VTTBR_EL2 register - RW. */
688#define ARMV8_AARCH64_SYSREG_VTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 0)
689/** VTCR_EL2 register - RW. */
690#define ARMV8_AARCH64_SYSREG_VTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 2)
691
692/** VNCR_EL2 register - RW. */
693#define ARMV8_AARCH64_SYSREG_VNCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 2, 0)
694
695/** VSTTBR_EL2 register - RW. */
696#define ARMV8_AARCH64_SYSREG_VSTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 0)
697/** VSTCR_EL2 register - RW. */
698#define ARMV8_AARCH64_SYSREG_VSTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 2)
699
700/** DACR32_EL2 register - RW. */
701#define ARMV8_AARCH64_SYSREG_DACR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 0, 0)
702
703/** HDFGRTR_EL2 register - RW. */
704#define ARMV8_AARCH64_SYSREG_HDFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 4)
705/** HDFGWTR_EL2 register - RW. */
706#define ARMV8_AARCH64_SYSREG_HDFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 5)
707/** HAFGRTR_EL2 register - RW. */
708#define ARMV8_AARCH64_SYSREG_HAFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 6)
709
710/** SPSR_EL2 register - RW. */
711#define ARMV8_AARCH64_SYSREG_SPSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 0)
712/** ELR_EL2 register - RW. */
713#define ARMV8_AARCH64_SYSREG_ELR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 1)
714
715/** SP_EL1 register - RW. */
716#define ARMV8_AARCH64_SYSREG_SP_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 1, 0)
717
718/** IFSR32_EL2 register - RW. */
719#define ARMV8_AARCH64_SYSREG_IFSR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 0, 1)
720
721/** AFSR0_EL2 register - RW. */
722#define ARMV8_AARCH64_SYSREG_AFSR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 0)
723/** AFSR1_EL2 register - RW. */
724#define ARMV8_AARCH64_SYSREG_AFSR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 1)
725
726/** ESR_EL2 register - RW. */
727#define ARMV8_AARCH64_SYSREG_ESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 0)
728/** VSESR_EL2 register - RW. */
729#define ARMV8_AARCH64_SYSREG_VSESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 3)
730
731/** FPEXC32_EL2 register - RW. */
732#define ARMV8_AARCH64_SYSREG_FPEXC32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 3, 0)
733
734/** TFSR_EL2 register - RW. */
735#define ARMV8_AARCH64_SYSREG_TFSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 6, 0)
736
737/** FAR_EL2 register - RW. */
738#define ARMV8_AARCH64_SYSREG_FAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 0)
739/** HPFAR_EL2 register - RW. */
740#define ARMV8_AARCH64_SYSREG_HPFAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 4)
741
742/** PMSCR_EL2 register - RW. */
743#define ARMV8_AARCH64_SYSREG_PMSCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 9, 9, 0)
744
745/** MAIR_EL2 register - RW. */
746#define ARMV8_AARCH64_SYSREG_MAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 2, 0)
747
748/** AMAIR_EL2 register - RW. */
749#define ARMV8_AARCH64_SYSREG_AMAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 3, 0)
750
751/** MPAMHCR_EL2 register - RW. */
752#define ARMV8_AARCH64_SYSREG_MPAMHCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 0)
753/** MPAMVPMV_EL2 register - RW. */
754#define ARMV8_AARCH64_SYSREG_MPAMVPMV_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 1)
755
756/** MPAM2_EL2 register - RW. */
757#define ARMV8_AARCH64_SYSREG_MPAM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 5, 0)
758
759/** MPAMVPM0_EL2 register - RW. */
760#define ARMV8_AARCH64_SYSREG_MPAMVPM0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 0)
761/** MPAMVPM1_EL2 register - RW. */
762#define ARMV8_AARCH64_SYSREG_MPAMVPM1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 1)
763/** MPAMVPM2_EL2 register - RW. */
764#define ARMV8_AARCH64_SYSREG_MPAMVPM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 2)
765/** MPAMVPM3_EL2 register - RW. */
766#define ARMV8_AARCH64_SYSREG_MPAMVPM3_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 3)
767/** MPAMVPM4_EL2 register - RW. */
768#define ARMV8_AARCH64_SYSREG_MPAMVPM4_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 4)
769/** MPAMVPM5_EL2 register - RW. */
770#define ARMV8_AARCH64_SYSREG_MPAMVPM5_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 5)
771/** MPAMVPM6_EL2 register - RW. */
772#define ARMV8_AARCH64_SYSREG_MPAMVPM6_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 6)
773/** MPAMVPM7_EL2 register - RW. */
774#define ARMV8_AARCH64_SYSREG_MPAMVPM7_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 7)
775
776/** VBAR_EL2 register - RW. */
777#define ARMV8_AARCH64_SYSREG_VBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 0)
778/** RVBAR_EL2 register - RW. */
779#define ARMV8_AARCH64_SYSREG_RVBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 1)
780/** RMR_EL2 register - RW. */
781#define ARMV8_AARCH64_SYSREG_RMR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 2)
782
783/** VDISR_EL2 register - RW. */
784#define ARMV8_AARCH64_SYSREG_VDISR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 1, 1)
785
786/** CONTEXTIDR_EL2 register - RW. */
787#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 1)
788/** TPIDR_EL2 register - RW. */
789#define ARMV8_AARCH64_SYSREG_TPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 2)
790/** SCXTNUM_EL2 register - RW. */
791#define ARMV8_AARCH64_SYSREG_SCXTNUM_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 7)
792
793/** CNTVOFF_EL2 register - RW. */
794#define ARMV8_AARCH64_SYSREG_CNTVOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 3)
795/** CNTPOFF_EL2 register - RW. */
796#define ARMV8_AARCH64_SYSREG_CNTPOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 6)
797
798/** CNTHCTL_EL2 register - RW. */
799#define ARMV8_AARCH64_SYSREG_CNTHCTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 1, 0)
800
801/** CNTHP_TVAL_EL2 register - RW. */
802#define ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 0)
803/** CNTHP_CTL_EL2 register - RW. */
804#define ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 1)
805/** CNTHP_CVAL_EL2 register - RW. */
806#define ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 2)
807
808/** CNTHV_TVAL_EL2 register - RW. */
809#define ARMV8_AARCH64_SYSREG_CNTHV_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 0)
810/** CNTHV_CTL_EL2 register - RW. */
811#define ARMV8_AARCH64_SYSREG_CNTHV_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 1)
812/** CNTHV_CVAL_EL2 register - RW. */
813#define ARMV8_AARCH64_SYSREG_CNTHV_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 2)
814
815/** CNTHVS_TVAL_EL2 register - RW. */
816#define ARMV8_AARCH64_SYSREG_CNTHVS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 0)
817/** CNTHVS_CTL_EL2 register - RW. */
818#define ARMV8_AARCH64_SYSREG_CNTHVS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 1)
819/** CNTHVS_CVAL_EL2 register - RW. */
820#define ARMV8_AARCH64_SYSREG_CNTHVS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 2)
821
822/** CNTHPS_TVAL_EL2 register - RW. */
823#define ARMV8_AARCH64_SYSREG_CNTHPS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 0)
824/** CNTHPS_CTL_EL2 register - RW. */
825#define ARMV8_AARCH64_SYSREG_CNTHPS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 1)
826/** CNTHPS_CVAL_EL2 register - RW. */
827#define ARMV8_AARCH64_SYSREG_CNTHPS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 2)
828
829/** SP_EL2 register - RW. */
830#define ARMV8_AARCH64_SYSREG_SP_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 6, 4, 1, 0)
831/** @} */
832
833
834#ifndef RT_IN_ASSEMBLER
835/**
836 * SPSR_EL2 (according to chapter C5.2.19)
837 */
838typedef union ARMV8SPSREL2
839{
840 /** The plain unsigned view. */
841 uint64_t u;
842 /** The 8-bit view. */
843 uint8_t au8[8];
844 /** The 16-bit view. */
845 uint16_t au16[4];
846 /** The 32-bit view. */
847 uint32_t au32[2];
848 /** The 64-bit view. */
849 uint64_t u64;
850} ARMV8SPSREL2;
851/** Pointer to SPSR_EL2. */
852typedef ARMV8SPSREL2 *PARMV8SPSREL2;
853/** Pointer to const SPSR_EL2. */
854typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
855#endif /* !RT_IN_ASSEMBLER */
856
857
858/** @name SPSR_EL2 (When exception is taken from AArch64 state)
859 * @{
860 */
861/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
862#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
863#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
864/** Bit 0 - SP - Selected stack pointer. */
865#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
866#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
867/** Bit 1 - Reserved (read as zero). */
868#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
869/** Bit 2 - 3 - EL - Exception level. */
870#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
871#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
872#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
873#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
874/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
875#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
876#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
877/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
878#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
879#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
880/** Bit 6 - I - FIQ interrupt mask. */
881#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
882#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
883/** Bit 7 - I - IRQ interrupt mask. */
884#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
885#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
886/** Bit 8 - A - SError interrupt mask. */
887#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
888#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
889/** Bit 9 - D - Debug Exception mask. */
890#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
891#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
892/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
893#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
894#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
895#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
896/** Bit 12 - SSBS - Speculative Store Bypass. */
897#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
898#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
899/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
900#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
901#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
902/** Bit 14 - 19 - Reserved (read as zero). */
903#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
904 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
905/** Bit 20 - IL - Illegal Execution State flag. */
906#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
907#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
908/** Bit 21 - SS - Software Step flag. */
909#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
910#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
911/** Bit 22 - PAN - Privileged Access Never flag. */
912#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
913#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
914/** Bit 23 - UAO - User Access Override flag. */
915#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
916#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
917/** Bit 24 - DIT - Data Independent Timing flag. */
918#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
919#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
920/** Bit 25 - TCO - Tag Check Override flag. */
921#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
922#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
923/** Bit 26 - 27 - Reserved (read as zero). */
924#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
925/** Bit 28 - V - Overflow condition flag. */
926#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
927#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
928/** Bit 29 - C - Carry condition flag. */
929#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
930#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
931/** Bit 30 - Z - Zero condition flag. */
932#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
933#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
934/** Bit 31 - N - Negative condition flag. */
935#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
936#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
937/** Bit 32 - 63 - Reserved (read as zero). */
938#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
939/** Checks whether the given SPSR value contains a AARCH64 execution state. */
940#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
941/** @} */
942
943/** @name Aarch64 Exception levels
944 * @{ */
945/** Exception Level 0 - User mode. */
946#define ARMV8_AARCH64_EL_0 0
947/** Exception Level 1 - Supervisor mode. */
948#define ARMV8_AARCH64_EL_1 1
949/** Exception Level 2 - Hypervisor mode. */
950#define ARMV8_AARCH64_EL_2 2
951/** @} */
952
953
954/** @name ESR_EL2 (Exception Syndrome Register, EL2)
955 * @{
956 */
957/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
958#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
959#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
960/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
961#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
962#define ARMV8_ESR_EL2_IL_BIT 25
963#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
964#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
965/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
966#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
967 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
968#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
969/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
970#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
971 | RT_BIT_64(35) | RT_BIT_64(36))
972#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
973/** @} */
974
975
976/** @name ESR_EL2 Exception Classes (EC)
977 * @{ */
978/** Unknown exception reason. */
979#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
980/** Trapped WF* instruction. */
981#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
982/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
983#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
984/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
985#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
986/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
987#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
988/** AArch32 - Trapped LDC or STC access. */
989#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
990/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
991#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
992/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
993#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
994/** AArch32 - Trapped pointer authentication instruction. */
995#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
996/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
997#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
998/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
999#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
1000/** FEAT_BTI - Branch Target Exception. */
1001#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
1002/** Illegal Execution State. */
1003#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
1004/** AArch32 - SVC instruction execution. */
1005#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
1006/** AArch32 - HVC instruction execution. */
1007#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
1008/** AArch32 - SMC instruction execution. */
1009#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
1010/** AArch64 - SVC instruction execution. */
1011#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
1012/** AArch64 - HVC instruction execution. */
1013#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
1014/** AArch64 - SMC instruction execution. */
1015#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
1016/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
1017#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
1018/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
1019#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
1020/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
1021#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
1022/** FEAT_TME - Exception from TSTART instruction. */
1023#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
1024/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
1025#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
1026/** FEAT_SME - Access to SME functionality trapped. */
1027#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
1028/** FEAT_RME - Exception from Granule Protection Check. */
1029#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
1030/** Instruction Abort from a lower Exception level. */
1031#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
1032/** Instruction Abort from the same Exception level. */
1033#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
1034/** PC alignment fault exception. */
1035#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
1036/** Data Abort from a lower Exception level. */
1037#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
1038/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
1039#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
1040/** SP alignment fault exception. */
1041#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
1042/** FEAT_MOPS - Memory Operation Exception. */
1043#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
1044/** AArch32 - Trapped floating point exception. */
1045#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
1046/** AArch64 - Trapped floating point exception. */
1047#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
1048/** SError interrupt. */
1049#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
1050/** Breakpoint Exception from a lower Exception level. */
1051#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
1052/** Breakpoint Exception from the same Exception level. */
1053#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
1054/** Software Step Exception from a lower Exception level. */
1055#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
1056/** Software Step Exception from the same Exception level. */
1057#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
1058/** Watchpoint Exception from a lower Exception level. */
1059#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
1060/** Watchpoint Exception from the same Exception level. */
1061#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
1062/** AArch32 - BKPT instruction execution. */
1063#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
1064/** AArch32 - Vector Catch exception. */
1065#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
1066/** AArch64 - BRK instruction execution. */
1067#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
1068/** @} */
1069
1070
1071/** @name ISS encoding for Data Abort exceptions.
1072 * @{ */
1073/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
1074#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
1075 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
1076#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
1077/** Bit 6 - WnR - Write not Read. */
1078#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
1079#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
1080/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
1081#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
1082#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
1083/** Bit 8 - CM - Cache maintenance instruction. */
1084#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
1085#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
1086/** Bit 9 - EA - External abort type. */
1087#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
1088#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
1089/** Bit 10 - FnV - FAR not Valid. */
1090#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
1091#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
1092/** Bit 11 - 12 - LST - Load/Store Type. */
1093#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
1094#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
1095/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
1096#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
1097#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
1098/** Bit 14 - AR - Acquire/Release semantics. */
1099#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
1100#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
1101/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
1102#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
1103#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
1104/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
1105#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
1106 | RT_BIT_32(19) | RT_BIT_32(20))
1107#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
1108/** Bit 21 - SSE - Syndrome Sign Extend. */
1109#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
1110#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
1111/** Bit 22 - 23 - SAS - Syndrome Access Size. */
1112#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
1113#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
1114/** Bit 24 - ISV - Instruction Syndrome Valid. */
1115#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
1116#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
1117/** @} */
1118
1119
1120/** @name Data Fault Status Code (DFSC).
1121 * @{ */
1122/** Address size fault, level 0 of translation or translation table base register. */
1123#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
1124/** Address size fault, level 1. */
1125#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
1126/** Address size fault, level 2. */
1127#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
1128/** Address size fault, level 3. */
1129#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
1130/** Translation fault, level 0. */
1131#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
1132/** Translation fault, level 1. */
1133#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
1134/** Translation fault, level 2. */
1135#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
1136/** Translation fault, level 3. */
1137#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
1138/** FEAT_LPA2 - Access flag fault, level 0. */
1139#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
1140/** Access flag fault, level 1. */
1141#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
1142/** Access flag fault, level 2. */
1143#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
1144/** Access flag fault, level 3. */
1145#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
1146/** FEAT_LPA2 - Permission fault, level 0. */
1147#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
1148/** Permission fault, level 1. */
1149#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
1150/** Permission fault, level 2. */
1151#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
1152/** Permission fault, level 3. */
1153#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
1154/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
1155#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
1156/** FEAT_MTE2 - Synchronous Tag Check Fault. */
1157#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
1158/** @todo Do the rest (lazy developer). */
1159/** @} */
1160
1161
1162/** @name SAS encoding.
1163 * @{ */
1164/** Byte access. */
1165#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
1166/** Halfword access (uint16_t). */
1167#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
1168/** Word access (uint32_t). */
1169#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
1170/** Doubleword access (uint64_t). */
1171#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
1172/** @} */
1173
1174
1175/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
1176 * @{ */
1177/** Bit 0 - Direction flag. */
1178#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
1179#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
1180/** Bit 1 - 4 - CRm value from the instruction. */
1181#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
1182 | RT_BIT_32(4))
1183#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
1184/** Bit 5 - 9 - Rt value from the instruction. */
1185#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
1186 | RT_BIT_32(8) | RT_BIT_32(9))
1187#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
1188/** Bit 10 - 13 - CRn value from the instruction. */
1189#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
1190 | RT_BIT_32(13))
1191#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
1192/** Bit 14 - 16 - Op2 value from the instruction. */
1193#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
1194#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
1195/** Bit 17 - 19 - Op2 value from the instruction. */
1196#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
1197#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
1198/** Bit 20 - 21 - Op0 value from the instruction. */
1199#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
1200#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
1201/** Bit 22 - 24 - Reserved. */
1202#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
1203/** @} */
1204
1205
1206/** @name ISS encoding for trapped HVC instruction exceptions.
1207 * @{ */
1208/** Bit 0 - 15 - imm16 value of the instruction. */
1209#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
1210#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
1211/** @} */
1212
1213
1214/** @name TCR_EL1 - Translation Control Register (EL1)
1215 * @{
1216 */
1217/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
1218#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
1219 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
1220#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
1221/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
1222#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
1223#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
1224/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1225#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
1226#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
1227/** Non cacheable. */
1228# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
1229/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1230# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
1231/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1232# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
1233/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1234# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
1235/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1236#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
1237#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
1238/** Non cacheable. */
1239# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
1240/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1241# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
1242/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1243# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
1244/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1245# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
1246/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
1247#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
1248#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
1249/** Non shareable. */
1250# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
1251/** Invalid value. */
1252# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
1253/** Outer Shareable. */
1254# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
1255/** Inner Shareable. */
1256# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
1257/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
1258#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15))
1259#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
1260/** Invalid granule size. */
1261# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
1262/** 16KiB granule size. */
1263# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
1264/** 4KiB granule size. */
1265# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
1266/** 64KiB granule size. */
1267# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
1268/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
1269#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
1270 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
1271#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
1272/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
1273#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
1274#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
1275/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
1276#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
1277#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
1278/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1279#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
1280#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
1281/** Non cacheable. */
1282# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
1283/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1284# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
1285/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1286# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
1287/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1288# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
1289/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1290#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
1291#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
1292/** Non cacheable. */
1293# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
1294/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1295# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
1296/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1297# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
1298/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1299# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
1300/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
1301#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
1302#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
1303/** Non shareable. */
1304# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
1305/** Invalid value. */
1306# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
1307/** Outer Shareable. */
1308# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
1309/** Inner Shareable. */
1310# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
1311/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
1312#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
1313#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
1314/** Invalid granule size. */
1315# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
1316/** 16KiB granule size. */
1317# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
1318/** 4KiB granule size. */
1319# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
1320/** 64KiB granule size. */
1321# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
1322/** Bit 32 - 34 - Intermediate Physical Address Size. */
1323#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
1324#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
1325/** IPA - 32 bits, 4GiB. */
1326# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
1327/** IPA - 36 bits, 64GiB. */
1328# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
1329/** IPA - 40 bits, 1TiB. */
1330# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
1331/** IPA - 42 bits, 4TiB. */
1332# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
1333/** IPA - 44 bits, 16TiB. */
1334# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
1335/** IPA - 48 bits, 256TiB. */
1336# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
1337/** IPA - 52 bits, 4PiB. */
1338# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
1339/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
1340#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
1341#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
1342/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
1343#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
1344#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
1345/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
1346#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
1347#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
1348/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
1349#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
1350#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
1351/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
1352#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
1353#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
1354/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
1355#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
1356#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
1357/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
1358#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
1359#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
1360/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
1361#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
1362#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
1363/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
1364#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
1365#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
1366/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
1367#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
1368#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
1369/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
1370#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
1371#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
1372/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
1373#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
1374#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
1375/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
1376#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
1377#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
1378/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
1379#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1380#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1381/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1382#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1383#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1384/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1385#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1386#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1387/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1388#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1389#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1390/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1391#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1392#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1393/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1394#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1395#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1396/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1397#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1398#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1399/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1400#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1401#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1402/** Bit 57 - TCMA0 */
1403#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1404#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1405/** Bit 58 - TCMA1 */
1406#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1407#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1408/** Bit 59 - Data Sharing(?). */
1409#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1410#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1411/** @} */
1412
1413
1414/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1415 * @{
1416 */
1417/** Bit 0 - Common not Private (FEAT_TTCNP). */
1418#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1419#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1420/** Bit 1 - 47 - Translation table base address. */
1421#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1422#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) ((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR)
1423/** Bit 48 - 63 - ASID. */
1424#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1425#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1426/** @} */
1427
1428
1429/** @name MDSCR_EL1 - MOnitor Debug System Control Register (EL1).
1430 * @{ */
1431/** Bit 0 - SS - Software step control bit. */
1432#define ARMV8_MDSCR_EL1_AARCH64_SS RT_BIT_64(0)
1433#define ARMV8_MDSCR_EL1_AARCH64_SS_BIT 0
1434/** @} */
1435
1436
1437/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1438 * @{ */
1439/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1440#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1441#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1442#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1443/** @} */
1444
1445
1446/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1447 * @{ */
1448/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1449#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1450#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1451#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1452/** @} */
1453
1454
1455/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1456 * @{ */
1457/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1458#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1459#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1460#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1461/** @} */
1462
1463
1464/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1465 * @{ */
1466/** Bit 0 - Common Binary Pointer Register - RW. */
1467#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1468#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1469/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1470#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1471#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1472/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1473#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1474#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1475/** Bit 8 - 10 - Priority bits - RO. */
1476#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1477#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1478/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1479#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1480#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1481/** INTIDS are 16-bit wide. */
1482# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1483/** INTIDS are 24-bit wide. */
1484# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1485/** Bit 14 - SEI Supported - RO. */
1486#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1487#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1488/** Bit 15 - Affinity 3 Valid - RO. */
1489#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1490#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1491/** Bit 18 - Range Selector Support - RO. */
1492#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1493#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1494/** Bit 19 - Extended INTID range supported - RO. */
1495#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1496#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1497/** All RW bits. */
1498#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1499/** All RO bits (including Res0). */
1500#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1501/** @} */
1502
1503
1504/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1505 * @{ */
1506/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1507#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1508#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1509/** @} */
1510
1511
1512/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1513 * @{ */
1514/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1515#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1516#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1517/** @} */
1518
1519
1520/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1521 * @{ */
1522/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1523#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1524#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1525/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1526#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1527#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1528/** Bit 24 - 27 - The INTID of the SGI. */
1529#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1530#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1531/* Bit 28 - 31 - Reserved. */
1532/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1533#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1534#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1535/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1536#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1537#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1538/* Bit 41 - 43 - Reserved. */
1539/** Bit 44 - 47 - Range selector. */
1540#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1541#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1542/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1543#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1544#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1545/* Bit 56 - 63 - Reserved. */
1546/** @} */
1547
1548
1549/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1550 * @{ */
1551/** Bit 0 - Enables the timer. */
1552#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1553#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1554/** Bit 1 - Timer interrupt mask bit. */
1555#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1556#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1557/** Bit 2 - Timer status bit. */
1558#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1559#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1560/** @} */
1561
1562
1563/** @name OSLAR_EL1 - OS Lock Access Register.
1564 * @{ */
1565/** Bit 0 - The OS Lock status bit. */
1566#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1567#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1568/** @} */
1569
1570
1571/** @name OSLSR_EL1 - OS Lock Status Register.
1572 * @{ */
1573/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1574#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1575#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1576/** Bit 1 - The OS Lock status bit. */
1577#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1578#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1579/** Bit 2 - Not 32-bit access. */
1580#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1581#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1582/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1583#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1584#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1585/** @} */
1586
1587
1588/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1589 * @{ */
1590/* Bit 0 - 3 - Reserved. */
1591/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1592#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1593#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1594/** No AES instructions implemented. */
1595# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1596/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1597# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1598/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1599# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1600/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1601#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1602#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1603/** No SHA1 instructions implemented. */
1604# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1605/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1606# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1607/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1608#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1609#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1610/** No SHA2 instructions implemented. */
1611# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1612/** SHA256 instructions implemented (FEAT_SHA256). */
1613# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1614/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1615# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1616/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1617#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1618#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1619/** No CRC32 instructions implemented. */
1620# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1621/** CRC32 instructions implemented (FEAT_CRC32). */
1622# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1623/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1624#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1625#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1626/** No Atomic instructions implemented. */
1627# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1628/** Atomic instructions implemented (FEAT_LSE). */
1629# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1630/** Bit 24 - 27 - Indicates support for TME instructions. */
1631#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1632#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1633/** TME instructions are not implemented. */
1634# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1635/** TME instructions are implemented. */
1636# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1637/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1638#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1639#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1640/** No RDMA instructions implemented. */
1641# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1642/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1643# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1644/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1645#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1646#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1647/** No SHA3 instructions implemented. */
1648# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1649/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1650# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1651/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1652#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1653#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1654/** No SM3 instructions implemented. */
1655# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1656/** SM3 instructions implemented (FEAT_SM3). */
1657# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1658/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1659#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1660#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1661/** No SM4 instructions implemented. */
1662# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1663/** SM4 instructions implemented (FEAT_SM4). */
1664# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1665/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1666#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1667#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1668/** No Dot Product instructions implemented. */
1669# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1670/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1671# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1672/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1673#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1674#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1675/** FMLAL and FMLSL instructions are not implemented. */
1676# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1677/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1678# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1679/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1680#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1681#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1682/** No flag manipulation instructions implemented. */
1683# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1684/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1685# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1686/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1687# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1688/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1689#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1690#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1691/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1692# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1693/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1694# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1695/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1696# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1697/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1698#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1699#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1700/** No Random Number instructions implemented. */
1701# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1702/** RNDR and RDNRRS registers are implemented . */
1703# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1704/** @} */
1705
1706
1707/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1708 * @{ */
1709/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1710#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1711#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1712/** DC CVAP not supported. */
1713# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1714/** DC CVAP supported (FEAT_DPB). */
1715# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1716/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1717# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1718/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1719#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1720#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1721/** Address Authentication using the QARMA5 algorithm is not implemented. */
1722# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1723/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1724# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1725/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1726# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1727/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1728# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1729/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1730# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1731/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1732# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1733/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1734#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1735#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1736/** Address Authentication using the QARMA5 algorithm is not implemented. */
1737# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1738/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1739# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1740/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1741# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1742/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1743# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1744/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1745# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1746/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1747# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1748/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1749#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1750#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1751/** No FJCVTZS instruction implemented. */
1752# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1753/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1754# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1755/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1756#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1757#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1758/** No FCMLA and FCADD instructions implemented. */
1759# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1760/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1761# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1762/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1763#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1764#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1765/** No RCpc instructions implemented. */
1766# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1767/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1768# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1769/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1770# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1771/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1772#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1773#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1774/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1775# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1776/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1777# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1778/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1779#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1780#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1781/** Generic Authentication using an implementation defined algorithm is not implemented. */
1782# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1783/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1784# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1785/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1786#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1787#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1788/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1789# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1790/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1791# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1792/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1793#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1794#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1795/** No SB instructions implemented. */
1796# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1797/** SB instructions implemented (FEAT_SB). */
1798# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1799/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1800#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1801#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1802/** Prediction invalidation instructions are not implemented. */
1803# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1804/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1805# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1806/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1807#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1808#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1809/** BFloat16 instructions are not implemented. */
1810# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1811/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1812# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1813/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1814# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1815/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1816#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1817#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1818/** Data Gathering Hint instructions are not implemented. */
1819# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1820/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1821# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1822/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1823#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1824#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1825/** No Int8 matrix multiplication instructions implemented. */
1826# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1827/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1828# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1829/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1830#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1831#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1832/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1833# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1834/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1835# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1836/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1837#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1838#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1839/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1840# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1841/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1842# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1843/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1844# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1845/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1846# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1847/** @} */
1848
1849
1850/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1851 * @{ */
1852/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1853#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1854#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1855/** WFET and WFIT are not supported. */
1856# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1857/** WFET and WFIT are supported (FEAT_WFxT). */
1858# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1859/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1860#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1861#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1862/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1863# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1864/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1865# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1866/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1867#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1868#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1869/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1870# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1871/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1872# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1873/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1874#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1875#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1876/** Address Authentication using the QARMA3 algorithm is not implemented. */
1877# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1878/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1879# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1880/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1881# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1882/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1883# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1884/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1885# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1886/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1887# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1888/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1889#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1890#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1891/** No Memory Copy and Memory Set instructions implemented. */
1892# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1893/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1894# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1895/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1896#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1897#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1898/** BC instruction is not implemented. */
1899# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1900/** BC instruction is implemented (FEAT_HBC). */
1901# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1902/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1903#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1904#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1905/** ConstPACField() returns FALSE. */
1906# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1907/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1908# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1909/* Bit 28 - 63 - Reserved. */
1910/** @} */
1911
1912
1913/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1914 * @{ */
1915/** Bit 0 - 3 - EL0 Exception level handling. */
1916#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1917#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1918/** EL0 can be executed in AArch64 state only. */
1919# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1920/** EL0 can be executed in AArch64 and AArch32 state. */
1921# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1922/** Bit 4 - 7 - EL1 Exception level handling. */
1923#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1924#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1925/** EL1 can be executed in AArch64 state only. */
1926# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1927/** EL1 can be executed in AArch64 and AArch32 state. */
1928# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1929/** Bit 8 - 11 - EL2 Exception level handling. */
1930#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1931#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1932/** EL2 is not implemented. */
1933# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1934/** EL2 can be executed in AArch64 state only. */
1935# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1936/** EL2 can be executed in AArch64 and AArch32 state. */
1937# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1938/** Bit 12 - 15 - EL3 Exception level handling. */
1939#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1940#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1941/** EL3 is not implemented. */
1942# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1943/** EL3 can be executed in AArch64 state only. */
1944# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1945/** EL3 can be executed in AArch64 and AArch32 state. */
1946# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1947/** Bit 16 - 19 - Floating-point support. */
1948#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1949#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1950/** Floating-point is implemented and support single and double precision. */
1951# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1952/** Floating-point is implemented and support single, double and half precision. */
1953# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1954/** Floating-point is not implemented. */
1955# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1956/** Bit 20 - 23 - Advanced SIMD support. */
1957#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1958#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1959/** Advanced SIMD is implemented and support single and double precision. */
1960# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1961/** Advanced SIMD is implemented and support single, double and half precision. */
1962# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1963/** Advanced SIMD is not implemented. */
1964# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1965/** Bit 24 - 27 - System register GIC CPU interface support. */
1966#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1967#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1968/** GIC CPU interface system registers are not implemented. */
1969# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1970/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1971# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1972/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1973# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1974/** Bit 28 - 31 - RAS Extension version. */
1975#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1976#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1977/** No RAS extension. */
1978# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1979/** RAS Extension implemented. */
1980# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1981/** FEAT_RASv1p1 implemented. */
1982# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1983/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1984#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1985#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1986/** SVE is not supported. */
1987# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1988/** SVE is supported. */
1989# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1990/** Bit 36 - 39 - Secure EL2 support. */
1991#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1992#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1993/** Secure EL2 is not supported. */
1994# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1995/** Secure EL2 is implemented. */
1996# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1997/** Bit 40 - 43 - MPAM support. */
1998#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1999#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
2000/** MPAM extension major version number is 0. */
2001# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
2002/** MPAM extension major version number is 1. */
2003# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
2004/** Bit 44 - 47 - Activity Monitor Extension support. */
2005#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2006#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
2007/** Activity Monitor extension is not implemented. */
2008# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
2009/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
2010# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
2011/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
2012# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
2013/** Bit 48 - 51 - Data Independent Timing support. */
2014#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2015#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
2016/** AArch64 does not guarantee constant execution time of any instructions. */
2017# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
2018/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
2019# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
2020/** Bit 52 - 55 - Realm Management Extension support. */
2021#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2022#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
2023/** Realm Management Extension not implemented. */
2024# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
2025/** RMEv1 is implemented (FEAT_RME). */
2026# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
2027/** Bit 56 - 59 - Speculative use out of context branch targets support. */
2028#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2029#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
2030/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
2031# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
2032/** FEAT_CSV2 is implemented. */
2033# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
2034/** FEAT_CSV2_2 is implemented. */
2035# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
2036/** FEAT_CSV2_3 is implemented. */
2037# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
2038/** Bit 60 - 63 - Speculative use of faulting data support. */
2039#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2040#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
2041/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
2042# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
2043/** FEAT_CSV3 is supported . */
2044# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
2045/** @} */
2046
2047
2048/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
2049 * @{ */
2050/** Bit 0 - 3 - Branch Target Identification support. */
2051#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2052#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
2053/** The Branch Target Identification mechanism is not implemented. */
2054# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
2055/** The Branch Target Identifcation mechanism is implemented. */
2056# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
2057/** Bit 4 - 7 - Speculative Store Bypassing control support. */
2058#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2059#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
2060/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
2061# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
2062/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
2063# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
2064/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
2065 * to directly read and write the PSTATE.SSBS field. */
2066# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
2067/** Bit 8 - 11 - Memory Tagging Extension support. */
2068#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2069#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
2070/** MTE is not implemented. */
2071# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
2072/** Instruction only Memory Tagging Extensions implemented. */
2073# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
2074/** Full Memory Tagging Extension implemented. */
2075# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
2076/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
2077# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
2078/** Bit 12 - 15 - RAS Extension fractional field. */
2079#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2080#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
2081/** RAS Extension is implemented. */
2082# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
2083/** FEAT_RASv1p1 is implemented. */
2084# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
2085/** Bit 16 - 19 - MPAM minor version number. */
2086#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2087#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
2088/** The minor version of number of the MPAM extension is 0. */
2089# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
2090/** The minor version of number of the MPAM extension is 1. */
2091# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
2092/* Bit 20 - 23 - Reserved. */
2093/** Bit 24 - 27 - Scalable Matrix Extension support. */
2094#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2095#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
2096/** Scalable Matrix Extensions are not implemented. */
2097# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
2098/** Scalable Matrix Extensions are implemented (FEAT_SME). */
2099# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
2100/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
2101# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
2102/** Bit 28 - 31 - Random Number trap to EL3 support. */
2103#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2104#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
2105/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
2106# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
2107/** Trapping of RNDR and RDNRRS to EL3 is supported. */
2108# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
2109/** Bit 32 - 35 - CSV2 fractional field. */
2110#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2111#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
2112/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
2113# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
2114/** FEAT_CSV2_1p1 is implemented. */
2115# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
2116/** FEAT_CSV2_1p2 is implemented. */
2117# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
2118/** Bit 36 - 39 - Non-maskable Interrupt support. */
2119#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2120#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
2121/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
2122# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
2123/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
2124# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
2125/** @} */
2126
2127
2128/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
2129 * @{ */
2130/** Bit 0 - 3 - Physical Address range supported. */
2131#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2132#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
2133/** Physical Address range is 32 bits, 4GiB. */
2134# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
2135/** Physical Address range is 36 bits, 64GiB. */
2136# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
2137/** Physical Address range is 40 bits, 1TiB. */
2138# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
2139/** Physical Address range is 42 bits, 4TiB. */
2140# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
2141/** Physical Address range is 44 bits, 16TiB. */
2142# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
2143/** Physical Address range is 48 bits, 256TiB. */
2144# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
2145/** Physical Address range is 52 bits, 4PiB. */
2146# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
2147/** Bit 4 - 7 - Number of ASID bits. */
2148#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2149#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
2150/** ASID bits is 8. */
2151# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
2152/** ASID bits is 16. */
2153# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
2154/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
2155#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2156#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
2157/** No mixed-endian support. */
2158# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
2159/** Mixed-endian supported. */
2160# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
2161/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
2162#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2163#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
2164/** No distinction between Secure and Non-secure Memory supported. */
2165# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
2166/** Distinction between Secure and Non-secure Memory supported. */
2167# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
2168/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
2169#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2170#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
2171/** No mixed-endian support at EL0. */
2172# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
2173/** Mixed-endian support at EL0. */
2174# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
2175/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
2176#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2177#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
2178/** 16KiB granule size not supported. */
2179# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
2180/** 16KiB granule size is supported. */
2181# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
2182/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2183# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
2184/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
2185#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2186#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
2187/** 64KiB granule supported. */
2188# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
2189/** 64KiB granule not supported. */
2190# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
2191/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
2192#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2193#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
2194/** 4KiB granule supported. */
2195# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
2196/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2197# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
2198/** 4KiB granule not supported. */
2199# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
2200/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
2201#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2202#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
2203/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
2204# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
2205/** 16KiB granule not supported at stage 2. */
2206# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
2207/** 16KiB granule supported at stage 2. */
2208# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
2209/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2210# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
2211/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
2212#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2213#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
2214/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
2215# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
2216/** 64KiB granule not supported at stage 2. */
2217# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
2218/** 64KiB granule supported at stage 2. */
2219# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
2220/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2221#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2222#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
2223/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
2224# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
2225/** 4KiB granule not supported at stage 2. */
2226# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
2227/** 4KiB granule supported at stage 2. */
2228# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
2229/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2230# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
2231/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
2232#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2233#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
2234/** All exception entries and exits are context synchronization events. */
2235# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
2236/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
2237# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
2238/* Bit 48 - 55 - Reserved. */
2239/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
2240#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2241#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
2242/** Fine-grained trap controls are not implemented. */
2243# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
2244/** Fine-grained trap controls are implemented (FEAT_FGT). */
2245# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
2246/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
2247#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2248#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
2249/** Enhanced Counter Virtualization is not implemented. */
2250# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
2251/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
2252# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
2253/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
2254# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
2255/** @} */
2256
2257
2258/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
2259 * @{ */
2260/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
2261#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2262#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
2263/** Hardware update of the Access flag and dirty state are not supported. */
2264# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
2265/** Support for hardware update of the Access flag for Block and Page descriptors. */
2266# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
2267/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
2268# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
2269/** Bit 4 - 7 - EL1 Exception level handling. */
2270#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2271#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
2272/** VMID bits is 8. */
2273# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
2274/** VMID bits is 16 (FEAT_VMID16). */
2275# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
2276/** Bit 8 - 11 - Virtualization Host Extensions support. */
2277#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2278#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
2279/** Virtualization Host Extensions are not supported. */
2280# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
2281/** Virtualization Host Extensions are supported. */
2282# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
2283/** Bit 12 - 15 - Hierarchical Permission Disables. */
2284#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2285#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
2286/** Disabling of hierarchical controls not supported. */
2287# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
2288/** Disabling of hierarchical controls supported (FEAT_HPDS). */
2289# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
2290/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
2291# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
2292/** Bit 16 - 19 - LORegions support. */
2293#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2294#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
2295/** LORegions not supported. */
2296# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
2297/** LORegions supported. */
2298# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
2299/** Bit 20 - 23 - Privileged Access Never support. */
2300#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2301#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
2302/** PAN not supported. */
2303# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
2304/** PAN supported (FEAT_PAN). */
2305# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
2306/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
2307# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
2308/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
2309# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
2310/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
2311#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2312#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
2313/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
2314# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
2315/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
2316# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
2317/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
2318#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2319#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
2320/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
2321# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
2322/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
2323# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
2324/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
2325#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2326#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
2327/** Configurable delayed trapping of WFE is not supported. */
2328# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
2329/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
2330# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
2331/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
2332#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2333#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
2334/** Enhanced Translation Synchronization is not supported. */
2335# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
2336/** Enhanced Translation Synchronization is implemented. */
2337# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
2338/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2339#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2340#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
2341/** HCRX_EL2 and its associated EL3 trap are not supported. */
2342# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
2343/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
2344# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
2345/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
2346#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2347#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
2348/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
2349# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
2350/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
2351# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
2352/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
2353#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2354#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
2355/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
2356# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
2357/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
2358# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
2359/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
2360#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2361#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
2362/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
2363# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
2364/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
2365# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
2366/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
2367#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2368#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
2369/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
2370# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
2371/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
2372# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
2373/* Bit 60 - 63 - Reserved. */
2374/** @} */
2375
2376
2377/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
2378 * @{ */
2379/** Bit 0 - 3 - Indicates support for Common not Private translations. */
2380#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2381#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
2382/** Common not Private translations are not supported. */
2383# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
2384/** Support for Common not Private translations (FEAT_TTNCP). */
2385# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
2386/** Bit 4 - 7 - Indicates support for User Access Override. */
2387#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2388#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2389/** User Access Override is not supported. */
2390# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2391/** User Access Override is supported (FEAT_UAO). */
2392# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2393/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2394#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2395#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2396/** LSMAOE and nTLSMD bits are not supported. */
2397# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2398/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2399# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2400/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2401#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2402#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2403/** IESB bit is not supported. */
2404# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2405/** IESB bit is supported (FEAT_IESB). */
2406# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2407/** Bit 16 - 19 - Indicates support for larger virtual address. */
2408#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2409#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2410/** Virtual address range is 48 bits. */
2411# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2412/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2413# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2414/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2415#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2416#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2417/** CCSIDR_EL1 register format is 32-bit. */
2418# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2419/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2420# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2421/** Bit 24 - 27 - Indicates support for nested virtualization. */
2422#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2423#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2424/** Nested virtualization is not supported. */
2425# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2426/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2427# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2428/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2429# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2430/** Bit 28 - 31 - Indicates support for small translation tables. */
2431#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2432#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2433/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2434# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2435/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2436# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2437/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2438#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2439#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2440/** Unaligned single-copy atomicity and atomic functions are not supported. */
2441# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2442/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2443# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2444/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2445#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2446#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2447/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2448# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2449/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2450# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2451/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2452#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2453#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2454/** HCR_EL2.FWB bit is not supported. */
2455# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2456/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2457# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2458/* Bit 44 - 47 - Reserved. */
2459/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2460#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2461#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2462/** TLB maintenance instructions by address have bits [47:44] Res0. */
2463# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2464/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2465# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2466/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2467 * changing block size for a translation. */
2468#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2469#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2470/** Level 0 support for changing block size is supported (FEAT_BBM). */
2471# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2472/** Level 1 support for changing block size is supported (FEAT_BBM). */
2473# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2474/** Level 2 support for changing block size is supported (FEAT_BBM). */
2475# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2476/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2477#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2478#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2479/** Enhanced Virtualization Traps are not supported. */
2480# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2481/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2482# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2483/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2484# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2485/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2486#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2487#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2488/** E0PDx mechanism is not supported. */
2489# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2490/** E0PDx mechanism is supported (FEAT_E0PD). */
2491# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2492/** @} */
2493
2494
2495/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2496 * @{ */
2497/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2498#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2499#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2500/** Armv8 debug architecture version. */
2501# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2502/** Armv8 debug architecture version with virtualization host extensions. */
2503# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2504/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2505# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2506/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2507# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2508/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2509# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2510/** Bit 4 - 7 - Indicates trace support. */
2511#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2512#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2513/** Trace unit System registers not implemented. */
2514# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2515/** Trace unit System registers supported. */
2516# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2517/** Bit 8 - 11 - Performance Monitors Extension version. */
2518#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2519#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2520/** Performance Monitors Extension not supported. */
2521# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2522/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2523# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2524/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2525# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2526/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2527# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2528/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2529# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2530/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2531# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2532/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2533# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2534/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2535#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2536#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2537/* Bit 16 - 19 - Reserved 0. */
2538/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2539#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2540#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2541/* Bit 24 - 27 - Reserved 0. */
2542/** Bit 28 - 31 - Number of context-aware breakpoints. */
2543#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2544#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2545/** Bit 32 - 35 - Statistical Profiling Extension version. */
2546#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2547#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2548/** Statistical Profiling Extension not implemented. */
2549# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2550/** Statistical Profiling Extension supported (FEAT_SPE). */
2551# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2552/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2553# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2554/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2555# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2556/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2557# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2558/** Bit 36 - 39 - OS Double Lock implemented. */
2559#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2560#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2561/** OS Double Lock is not implemented. */
2562# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2563/** OS Double Lock is supported (FEAT_DoubleLock). */
2564# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2565/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2566#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2567#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2568/** Armv8.4 self-hosted Trace Extension not implemented. */
2569# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2570/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2571# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2572/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2573#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2574#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2575/** Trace Buffer Extension is not implemented. */
2576# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2577/** Trace Buffer Extension is supported (FEAT_TRBE). */
2578# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2579/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2580#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2581#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2582/** Multi-threaded PMU extension is not implemented. */
2583# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2584/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2585# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2586/** Multi-threaded PMU extension is not implemented. */
2587# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2588/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2589#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2590#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2591/** Branch Record Buffer extension is not implemented. */
2592# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2593/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2594# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2595/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2596# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2597/* Bit 56 - 59 - Reserved. */
2598/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2599#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2600#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2601/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2602# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2603/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2604# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2605/** @} */
2606
2607
2608/** @name FPCR - AArch64 Floating Point Control Register.
2609 * @{ */
2610/** Bit 0 - Flush Inputs to Zero when FEAT_AFP is supported. */
2611#define ARMV8_FPCR_FIZ RT_BIT_64(0)
2612#define ARMV8_FPCR_FIZ_BIT 0
2613/** Bit 1 - Alternate Handling of floating-point numbers when FEAT_AFP is supported. */
2614#define ARMV8_FPCR_AH RT_BIT_64(1)
2615#define ARMV8_FPCR_AH_BIT 1
2616/** Bit 2 - Controls how the output elements other than the lowest element of the vector are determined for
2617 * Advanced SIMD scalar instructions, when FEAT_AFP is supported. */
2618#define ARMV8_FPCR_NEP RT_BIT_64(2)
2619#define ARMV8_FPCR_NEP_BIT 2
2620/* Bit 3 - 7 - Reserved.*/
2621/** Bit 8 - Invalid Operation floating-point exception trap enable. */
2622#define ARMV8_FPCR_IOE RT_BIT_64(8)
2623#define ARMV8_FPCR_IOE_BIT 8
2624/** Bit 9 - Divide by Zero floating-point exception trap enable. */
2625#define ARMV8_FPCR_DZE RT_BIT_64(9)
2626#define ARMV8_FPCR_DZE_BIT 9
2627/** Bit 10 - Overflow floating-point exception trap enable. */
2628#define ARMV8_FPCR_OFE RT_BIT_64(10)
2629#define ARMV8_FPCR_OFE_BIT 10
2630/** Bit 11 - Underflow floating-point exception trap enable. */
2631#define ARMV8_FPCR_UFE RT_BIT_64(11)
2632#define ARMV8_FPCR_UFE_BIT 11
2633/** Bit 12 - Inexact floating-point exception trap enable. */
2634#define ARMV8_FPCR_IXE RT_BIT_64(12)
2635#define ARMV8_FPCR_IXE_BIT 12
2636/** Bit 13 - Controls numeric behavior of BFloat16 dot productions calculations performed,
2637 * supported when FEAT_EBF16 is supported. */
2638#define ARMV8_FPCR_EBF RT_BIT_64(13)
2639#define ARMV8_FPCR_EBF_BIT 13
2640/* Bit 14 - Reserved */
2641/** Bit 15 - Input Denormal floating-point exception trap enable. */
2642#define ARMV8_FPCR_IDE RT_BIT_64(15)
2643#define ARMV8_FPCR_IDE_BIT 15
2644/* Bit 16 - 18 - Reserved for AArch64 (Len field for AArch32). */
2645/** Bit 19 - Flushing denormalized numbers to zero control bit on half-precision data-processing instructions,
2646 * available when FEAT_FP16 is supported. */
2647#define ARMV8_FPCR_FZ16 RT_BIT_64(19)
2648#define ARMV8_FPCR_FZ16_BIT 19
2649/* Bit 20 - 21 - Reserved for AArch64 (Stride field dor AArch32). */
2650/** Bit 22 - 23 - Rounding Mode control field. */
2651#define ARMV8_FPCR_RMODE_MASK (RT_BIT_64(22) | RT_BIT_64(23))
2652#define ARMV8_FPCR_RMODE_SHIFT 22
2653/** Round to Nearest (RN) mode. */
2654# define ARMV8_FPCR_RMODE_RN 0
2655/** Round towards Plus Infinity (RP) mode. */
2656# define ARMV8_FPCR_RMODE_RP 1
2657/** Round towards Minus Infinity (RM) mode. */
2658# define ARMV8_FPCR_RMODE_RM 2
2659/** Round towards Zero (RZ) mode. */
2660# define ARMV8_FPCR_RMODE_RZ 3
2661/** Bit 24 - Flushing denormalized numbers to zero control bit. */
2662#define ARMV8_FPCR_FZ RT_BIT_64(24)
2663#define ARMV8_FPCR_FZ_BIT 24
2664/** Bit 25 - Default NaN use for NaN propagation. */
2665#define ARMV8_FPCR_DN RT_BIT_64(25)
2666#define ARMV8_FPCR_DN_BIT 25
2667/** Bit 26 - Alternative half-precision control bit. */
2668#define ARMV8_FPCR_AHP RT_BIT_64(26)
2669#define ARMV8_FPCR_AHP_BIT 26
2670/* Bit 27 - 63 - Reserved. */
2671/** @} */
2672
2673
2674/** @name FPSR - AArch64 Floating Point Status Register.
2675 * @{ */
2676/** Bit 0 - Invalid Operation cumulative floating-point exception bit. */
2677#define ARMV8_FPSR_IOC RT_BIT_64(0)
2678/** Bit 1 - Divide by Zero cumulative floating-point exception bit. */
2679#define ARMV8_FPSR_DZC RT_BIT_64(1)
2680/** Bit 2 - Overflow cumulative floating-point exception bit. */
2681#define ARMV8_FPSR_OFC RT_BIT_64(2)
2682/** Bit 3 - Underflow cumulative floating-point exception bit. */
2683#define ARMV8_FPSR_UFC RT_BIT_64(3)
2684/** Bit 4 - Inexact cumulative floating-point exception bit. */
2685#define ARMV8_FPSR_IXC RT_BIT_64(4)
2686/* Bit 5 - 6 - Reserved. */
2687/** Bit 7 - Input Denormal cumulative floating-point exception bit. */
2688#define ARMV8_FPSR_IDC RT_BIT_64(7)
2689/* Bit 8 - 26 - Reserved. */
2690/** Bit 27 - Cumulative saturation bit, Advanced SIMD only. */
2691#define ARMV8_FPSR_QC RT_BIT_64(27)
2692/* Bit 28 - 31 - NZCV bits for AArch32 floating point operations. */
2693/* Bit 32 - 63 - Reserved. */
2694/** @} */
2695
2696
2697
2698/** @name SCTLR_EL1 - AArch64 System Control Register (EL1).
2699 * @{ */
2700/** Bit 0 - MMU enable for EL1 and EL0 stage 1 address translation. */
2701#define ARMV8_SCTLR_EL1_M RT_BIT_64(0)
2702/** Bit 1 - Alignment check enable for EL1 and EL0. */
2703#define ARMV8_SCTLR_EL1_A RT_BIT_64(1)
2704/** Bit 2 - Stage 1 cacheability control, for data accesses. */
2705#define ARMV8_SCTLR_EL1_C RT_BIT_64(2)
2706/** Bit 3 - SP alignment check enable. */
2707#define ARMV8_SCTLR_EL1_SA RT_BIT_64(3)
2708/** Bit 4 - SP alignment check enable for EL0. */
2709#define ARMV8_SCTLR_EL1_SA0 RT_BIT_64(4)
2710/** Bit 5 - System instruction memory barrier enable from AArch32 EL0. */
2711#define ARMV8_SCTLR_EL1_CP15BEN RT_BIT_64(5)
2712/** Bit 6 - Non-aligned access enable. */
2713#define ARMV8_SCTLR_EL1_nAA RT_BIT_64(6)
2714/** Bit 7 - IT disable, disables some uses of IT instructions at EL0 using AArch32. */
2715#define ARMV8_SCTLR_EL1_ITD RT_BIT_64(7)
2716/** Bit 8 - SETEND instruction disable, disables SETEND instructions at EL0 using AArch32. */
2717#define ARMV8_SCTLR_EL1_SED RT_BIT_64(8)
2718/** Bit 9 - User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D,A,I,F} masks to EL1. */
2719#define ARMV8_SCTLR_EL1_UMA RT_BIT_64(9)
2720/** Bit 10 - Enable EL0 acccess to the CFP*, DVP* and CPP* instructions if FEAT_SPECRES is supported. */
2721#define ARMV8_SCTLR_EL1_EnRCTX RT_BIT_64(10)
2722/** Bit 11 - Exception Exit is Context Synchronizing (FEAT_ExS required). */
2723#define ARMV8_SCTLR_EL1_EOS RT_BIT_64(11)
2724/** Bit 12 - Stage 1 instruction access cacheability control, for access at EL0 and EL1. */
2725#define ARMV8_SCTLR_EL1_I RT_BIT_64(12)
2726/** @todo Finish (lazy developer). */
2727/** @} */
2728
2729
2730/** @name SCTLR_EL2 - AArch64 System Control Register (EL2) - 32-bit.
2731 * @{ */
2732/** Bit 0 - MMU enable for EL2. */
2733#define ARMV8_SCTLR_EL2_M RT_BIT_64(0)
2734/** Bit 1 - Alignment check enable. */
2735#define ARMV8_SCTLR_EL2_A RT_BIT_64(1)
2736/** Bit 2 - Global enable for data and unified caches. */
2737#define ARMV8_SCTLR_EL2_C RT_BIT_64(2)
2738/** Bit 3 - SP alignment check enable. */
2739#define ARMV8_SCTLR_EL2_SA RT_BIT_64(3)
2740/* Bit 4 - 11 - Reserved. */
2741/** Bit 12 - Instruction cache enable. */
2742#define ARMV8_SCTLR_EL2_I RT_BIT_64(12)
2743/* Bit 13 - 18 - Reserved. */
2744/** Bit 19 - Force treatment of all memory regions with write permissions as XN. */
2745#define ARMV8_SCTLR_EL2_WXN RT_BIT_64(19)
2746/* Bit 20 - 24 - Reserved. */
2747/** Bit 25 - Exception endianess - set means big endian, clear little endian. */
2748#define ARMV8_SCTLR_EL2_EE RT_BIT_64(25)
2749/* Bit 26 - 31 - Reserved. */
2750/** @} */
2751
2752
2753#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
2754/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2755 * @ingroup grp_rt_armv8
2756 *
2757 * A few inlined functions and macros for assiting in encoding common ARMv8
2758 * instructions.
2759 *
2760 * @{ */
2761
2762/** A64: Official NOP instruction. */
2763#define ARMV8_A64_INSTR_NOP UINT32_C(0xd503201f)
2764/** A64: Return instruction. */
2765#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2766/** A64: Return instruction with LR pointer authentication using SP and key A. */
2767#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2768/** A64: Return instruction with LR pointer authentication using SP and key B. */
2769#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2770/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2771#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2772/** A64: Insert pointer authentication code into LR using SP and key B. */
2773#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2774/** A64: Insert pointer authentication code into LR using XZR and key B. */
2775#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2776/** A64: Invert the carry flag (PSTATE.C). */
2777#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
2778
2779
2780/** Memory barrier: Shareability domain. */
2781typedef enum
2782{
2783 kArm64InstMbReqDomain_OuterShareable = 0,
2784 kArm64InstMbReqDomain_Nonshareable,
2785 kArm64InstMbReqDomain_InnerShareable,
2786 kArm64InstMbReqDomain_FullSystem
2787} ARM64INSTRMBREQDOMAIN;
2788
2789/** Memory barrier: Access type. */
2790typedef enum
2791{
2792 kArm64InstMbReqType_All0 = 0, /**< Special. Only used with PSSBB and SSBB. */
2793 kArm64InstMbReqType_Reads,
2794 kArm64InstMbReqType_Writes,
2795 kArm64InstMbReqType_All
2796} ARM64INSTRMBREQTYPE;
2797
2798/**
2799 * A64: DMB option
2800 */
2801DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDmb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
2802 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
2803{
2804 return UINT32_C(0xd50330bf)
2805 | ((uint32_t)enmDomain << 8)
2806 | ((uint32_t)enmType << 10);
2807}
2808
2809
2810/**
2811 * A64: DSB option
2812 */
2813DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
2814 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
2815{
2816 return UINT32_C(0xd503309f)
2817 | ((uint32_t)enmDomain << 8)
2818 | ((uint32_t)enmType << 10);
2819}
2820
2821
2822/**
2823 * A64: SSBB
2824 */
2825DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSsbb(void)
2826{
2827 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_OuterShareable, kArm64InstMbReqType_All0);
2828}
2829
2830
2831/**
2832 * A64: PSSBB
2833 */
2834DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPSsbb(void)
2835{
2836 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_Nonshareable, kArm64InstMbReqType_All0);
2837}
2838
2839
2840/**
2841 * A64: ISB option
2842 *
2843 * @note Only the default option selection is supported, all others are
2844 * currently reserved.
2845 */
2846DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
2847 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
2848{
2849 return UINT32_C(0xd50330df)
2850 | ((uint32_t)enmDomain << 8)
2851 | ((uint32_t)enmType << 10);
2852}
2853
2854
2855typedef enum
2856{
2857 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
2858 * and update the register. */
2859 kArm64InstrStLdPairType_PostIndex = 1,
2860 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2861 * but don't update the register. */
2862 kArm64InstrStLdPairType_Signed = 2,
2863 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2864 * and update the register. */
2865 kArm64InstrStLdPairType_PreIndex = 3
2866} ARM64INSTRSTLDPAIRTYPE;
2867
2868/**
2869 * A64: Encodes either stp (store register pair) or ldp (load register pair).
2870 *
2871 * @returns The encoded instruction.
2872 * @param fLoad true for ldp, false of stp.
2873 * @param u2Opc When @a fSimdFp is @c false:
2874 * - 0 for 32-bit GPRs (Wt).
2875 * - 1 for encoding stgp or ldpsw.
2876 * - 2 for 64-bit GRPs (Xt).
2877 * - 3 illegal.
2878 * When @a fSimdFp is @c true:
2879 * - 0 for 32-bit SIMD&FP registers (St).
2880 * - 1 for 64-bit SIMD&FP registers (Dt).
2881 * - 2 for 128-bit SIMD&FP regsiters (Qt).
2882 * @param enmType The instruction variant wrt addressing and updating of the
2883 * addressing register.
2884 * @param iReg1 The first register to store/load.
2885 * @param iReg2 The second register to store/load.
2886 * @param iBaseReg The base register to use when addressing. SP is allowed.
2887 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
2888 * will be multiplied by the register size.
2889 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
2890 * stgp/ldpsw instructions.
2891 */
2892DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
2893 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2894 bool fSimdFp = false)
2895{
2896 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
2897 return (u2Opc << 30)
2898 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
2899 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
2900 | ((uint32_t)enmType << 23)
2901 | ((uint32_t)fLoad << 22)
2902 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
2903 | (iReg2 << 10)
2904 | (iBaseReg << 5)
2905 | iReg1;
2906}
2907
2908
2909/** A64: ldp x1, x2, [x3] */
2910DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2911 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2912 bool f64Bit = true)
2913{
2914 return Armv8A64MkInstrStLdPair(true /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2915}
2916
2917
2918/** A64: stp x1, x2, [x3] */
2919DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2920 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2921 bool f64Bit = true)
2922{
2923 return Armv8A64MkInstrStLdPair(false /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2924}
2925
2926
2927typedef enum /* Size VR Opc */
2928{ /* \ | / */
2929 kArmv8A64InstrLdStType_Mask_Size = 0x300,
2930 kArmv8A64InstrLdStType_Mask_VR = 0x010,
2931 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
2932 kArmv8A64InstrLdStType_Shift_Size = 8,
2933 kArmv8A64InstrLdStType_Shift_VR = 4,
2934 kArmv8A64InstrLdStType_Shift_Opc = 0,
2935
2936 kArmv8A64InstrLdStType_St_Byte = 0x000,
2937 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
2938 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
2939 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
2940
2941 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
2942 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
2943 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
2944 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
2945
2946 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
2947 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
2948 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
2949
2950 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
2951 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
2952
2953 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
2954
2955 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
2956 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
2957 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
2958 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
2959
2960 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
2961 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
2962
2963 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
2964 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
2965
2966 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
2967 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
2968
2969} ARMV8A64INSTRLDSTTYPE;
2970/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
2971#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
2972
2973
2974/**
2975 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2976 *
2977 * @returns The encoded instruction.
2978 * @param u32Opcode The base opcode value.
2979 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2980 * @param iReg The register to load into / store.
2981 * @param iBaseReg The base register to use when addressing. SP is allowed.
2982 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2983 */
2984DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
2985 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2986{
2987 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
2988 return u32Opcode
2989 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2990 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2991 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2992 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
2993 | (iBaseReg << 5)
2994 | iReg;
2995}
2996
2997
2998/**
2999 * A64: Encodes load/store with unscaled 9-bit signed immediate.
3000 *
3001 * @returns The encoded instruction.
3002 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3003 * @param iReg The register to load into / store.
3004 * @param iBaseReg The base register to use when addressing. SP is allowed.
3005 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3006 */
3007DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
3008 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3009{
3010 /* 3 2 1 0 */
3011 /* 10987654321098765432109876543210 */
3012 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
3013 enmType, iReg, iBaseReg, i9ImmDisp);
3014}
3015
3016/**
3017 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
3018 *
3019 * @returns The encoded instruction.
3020 * @param enmType The load/store instruction type. Prefech not valid.
3021 * @param iReg The register to load into / store.
3022 * @param iBaseReg The base register to use when addressing. SP is allowed.
3023 * Written back.
3024 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3025 */
3026DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3027 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3028{
3029 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3030 /* 10987654321098765432109876543210 */
3031 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
3032 enmType, iReg, iBaseReg, i9ImmDisp);
3033}
3034
3035/**
3036 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
3037 *
3038 * @returns The encoded instruction.
3039 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3040 * @param iReg The register to load into / store.
3041 * @param iBaseReg The base register to use when addressing. SP is allowed.
3042 * Written back.
3043 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3044 */
3045DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3046 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3047{
3048 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3049 /* 10987654321098765432109876543210 */
3050 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
3051 enmType, iReg, iBaseReg, i9ImmDisp);
3052}
3053
3054/**
3055 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
3056 *
3057 * @returns The encoded instruction.
3058 * @param enmType The load/store instruction type. Prefech not valid,
3059 * nor any SIMD&FP variants.
3060 * @param iReg The register to load into / store.
3061 * @param iBaseReg The base register to use when addressing. SP is allowed.
3062 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3063 */
3064DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
3065 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3066{
3067 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
3068 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
3069 /* 3 2 1 0 */
3070 /* 10987654321098765432109876543210 */
3071 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
3072 enmType, iReg, iBaseReg, i9ImmDisp);
3073}
3074
3075
3076/**
3077 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
3078 *
3079 * @returns The encoded instruction.
3080 * @param enmType The load/store instruction type. Prefech not valid,
3081 * nor any SIMD&FP variants.
3082 * @param iReg The register to load into / store.
3083 * @param iBaseReg The base register to use when addressing. SP is allowed.
3084 * @param u12ImmDisp Addressing displacement, scaled by size.
3085 */
3086DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
3087 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
3088{
3089 Assert(u12ImmDisp < 4096U);
3090 Assert(iReg < 32); /* 3 2 1 0 */
3091 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3092 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
3093 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3094 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3095 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3096 | (u12ImmDisp << 10)
3097 | (iBaseReg << 5)
3098 | iReg;
3099}
3100
3101typedef enum
3102{
3103 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
3104 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
3105 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
3106 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
3107} ARMV8A64INSTRLDSTEXTEND;
3108
3109/**
3110 * A64: Encodes load/store w/ index register.
3111 *
3112 * @returns The encoded instruction.
3113 * @param enmType The load/store instruction type.
3114 * @param iReg The register to load into / store.
3115 * @param iBaseReg The base register to use when addressing. SP is allowed.
3116 * @param iRegIndex The index register.
3117 * @param enmExtend The extending to apply to @a iRegIndex.
3118 * @param fShifted Whether to shift the index. The shift amount corresponds
3119 * to the access size (thus irrelevant for byte accesses).
3120 */
3121DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
3122 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
3123 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
3124 bool fShifted = false)
3125{
3126 Assert(iRegIndex < 32);
3127 Assert(iReg < 32); /* 3 2 1 0 */
3128 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3129 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
3130 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3131 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3132 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3133 | (iRegIndex << 16)
3134 | ((uint32_t)enmExtend << 13)
3135 | ((uint32_t)fShifted << 12)
3136 | (iBaseReg << 5)
3137 | iReg;
3138}
3139
3140typedef enum /* VR Opc */
3141{ /* \ | */
3142 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
3143 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
3144 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
3145 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
3146
3147 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
3148 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
3149 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
3150 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
3151
3152 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
3153 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
3154 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
3155} ARMV8A64INSTRLDRLITTERAL;
3156
3157
3158/**
3159 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
3160 *
3161 * @returns The encoded instruction.
3162 * @param enmType The load instruction type.
3163 * @param iReg The register to load into.
3164 * @param i19Imm The signed immediate value, multiplied by 4 regardless
3165 * of access size.
3166 */
3167DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
3168{
3169 Assert(i19Imm >= -262144 && i19Imm < 262144);
3170 Assert(iReg < 32); /* 3 2 1 0 */
3171 /* 10987654321098765432109876543210 */
3172 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
3173 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
3174 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
3175 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
3176 | iReg;
3177}
3178
3179
3180typedef enum
3181{
3182 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
3183 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
3184 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
3185} ARMV8A64INSTRMOVWIDE;
3186
3187/**
3188 * A64: Encode a move wide immediate instruction.
3189 *
3190 * @returns The encoded instruction.
3191 * @param enmType The load instruction type.
3192 * @param iRegDst The register to mov the immediate into.
3193 * @param uImm16 The immediate value.
3194 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
3195 * half-words to target:
3196 * - 0 for bits 15:00,
3197 * - 1 for bits 31:16,
3198 * - 2 for bits 47:32 (f64Bit=true only),
3199 * - 3 for bits 63:48 (f64Bit=true only).
3200 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
3201 */
3202DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
3203 uint32_t iHalfWord = 0, bool f64Bit = true)
3204{
3205 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
3206 return ((uint32_t)f64Bit << 31)
3207 | ((uint32_t)enmType << 29)
3208 | UINT32_C(0x12800000)
3209 | (iHalfWord << 21)
3210 | (uImm16 << 5)
3211 | iRegDst;
3212}
3213
3214/** A64: Encodes a MOVN instruction.
3215 * @see Armv8A64MkInstrMovWide for parameter details. */
3216DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3217{
3218 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
3219}
3220
3221/** A64: Encodes a MOVZ instruction.
3222 * @see Armv8A64MkInstrMovWide for parameter details. */
3223DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3224{
3225 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
3226}
3227
3228/** A64: Encodes a MOVK instruction.
3229 * @see Armv8A64MkInstrMovWide for parameter details. */
3230DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3231{
3232 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
3233}
3234
3235
3236typedef enum
3237{
3238 kArmv8A64InstrShift_Lsl = 0,
3239 kArmv8A64InstrShift_Lsr,
3240 kArmv8A64InstrShift_Asr,
3241 kArmv8A64InstrShift_Ror
3242} ARMV8A64INSTRSHIFT;
3243
3244
3245/**
3246 * A64: Encodes a logical instruction with a shifted 2nd register operand.
3247 *
3248 * @returns The encoded instruction.
3249 * @param u2Opc The logical operation to perform.
3250 * @param fNot Whether to complement the 2nd operand.
3251 * @param iRegResult The output register.
3252 * @param iReg1 The 1st register operand.
3253 * @param iReg2Shifted The 2nd register operand, to which the optional
3254 * shifting is applied.
3255 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
3256 * GPRs.
3257 * @param offShift6 The shift amount (default: none).
3258 * @param enmShift The shift operation (default: LSL).
3259 */
3260DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
3261 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
3262 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
3263{
3264 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
3265 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
3266 return ((uint32_t)f64Bit << 31)
3267 | (u2Opc << 29)
3268 | UINT32_C(0x0a000000)
3269 | ((uint32_t)enmShift << 22)
3270 | ((uint32_t)fNot << 21)
3271 | (iReg2Shifted << 16)
3272 | (offShift6 << 10)
3273 | (iReg1 << 5)
3274 | iRegResult;
3275}
3276
3277
3278/** A64: Encodes an AND instruction.
3279 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3280DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3281 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3282{
3283 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3284}
3285
3286
3287/** A64: Encodes an BIC instruction.
3288 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3289DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3290 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3291{
3292 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3293}
3294
3295
3296/** A64: Encodes an ORR instruction.
3297 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3298DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3299 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3300{
3301 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3302}
3303
3304
3305/** A64: Encodes an MOV instruction.
3306 * This is an alias for "orr dst, xzr, src". */
3307DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
3308{
3309 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
3310}
3311
3312
3313/** A64: Encodes an ORN instruction.
3314 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3315DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3316 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3317{
3318 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3319}
3320
3321
3322/** A64: Encodes an EOR instruction.
3323 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3324DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3325 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3326{
3327 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3328}
3329
3330
3331/** A64: Encodes an EON instruction.
3332 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3333DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3334 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3335{
3336 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3337}
3338
3339
3340/** A64: Encodes an ANDS instruction.
3341 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3342DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3343 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3344{
3345 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3346}
3347
3348
3349/** A64: Encodes an BICS instruction.
3350 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3351DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3352 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3353{
3354 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3355}
3356
3357
3358
3359/*
3360 * Data processing instructions with two source register operands.
3361 */
3362
3363
3364/** A64: Encodes an SUBP instruction. */
3365DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3366{
3367 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3368 return UINT32_C(0x80000000)
3369 | UINT32_C(0x1ac00000)
3370 | (UINT32_C(0) << 10)
3371 | (iRegSubtrahend << 16)
3372 | (iRegMinuend << 5)
3373 | iRegResult;
3374}
3375
3376
3377/** A64: Encodes an SUBPS instruction. */
3378DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3379{
3380 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3381 return UINT32_C(0x80000000)
3382 | UINT32_C(0x20000000)
3383 | UINT32_C(0x1ac00000)
3384 | (UINT32_C(0) << 10)
3385 | (iRegSubtrahend << 16)
3386 | (iRegMinuend << 5)
3387 | iRegResult;
3388}
3389
3390
3391/** A64: Encodes an UDIV instruction. */
3392DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3393{
3394 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3395 return ((uint32_t)f64Bit << 31)
3396 | UINT32_C(0x1ac00000)
3397 | (UINT32_C(2) << 10)
3398 | (iRegDivisor << 16)
3399 | (iRegDividend << 5)
3400 | iRegResult;
3401}
3402
3403
3404/** A64: Encodes an SDIV instruction. */
3405DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3406{
3407 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3408 return ((uint32_t)f64Bit << 31)
3409 | UINT32_C(0x1ac00000)
3410 | (UINT32_C(3) << 10)
3411 | (iRegDivisor << 16)
3412 | (iRegDividend << 5)
3413 | iRegResult;
3414}
3415
3416
3417/** A64: Encodes an IRG instruction. */
3418DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3419{
3420 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3421 return UINT32_C(0x80000000)
3422 | UINT32_C(0x1ac00000)
3423 | (UINT32_C(4) << 10)
3424 | (iRegSrc2 << 16)
3425 | (iRegSrc1 << 5)
3426 | iRegResult;
3427}
3428
3429
3430/** A64: Encodes a GMI instruction. */
3431DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3432{
3433 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3434 return UINT32_C(0x80000000)
3435 | UINT32_C(0x1ac00000)
3436 | (UINT32_C(5) << 10)
3437 | (iRegSrc2 << 16)
3438 | (iRegSrc1 << 5)
3439 | iRegResult;
3440}
3441
3442
3443/** A64: Encodes an LSLV instruction. */
3444DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3445{
3446 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3447 return ((uint32_t)f64Bit << 31)
3448 | UINT32_C(0x1ac00000)
3449 | (UINT32_C(8) << 10)
3450 | (iRegCount << 16)
3451 | (iRegSrc << 5)
3452 | iRegResult;
3453}
3454
3455
3456/** A64: Encodes an LSRV instruction. */
3457DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3458{
3459 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3460 return ((uint32_t)f64Bit << 31)
3461 | UINT32_C(0x1ac00000)
3462 | (UINT32_C(9) << 10)
3463 | (iRegCount << 16)
3464 | (iRegSrc << 5)
3465 | iRegResult;
3466}
3467
3468
3469/** A64: Encodes an ASRV instruction. */
3470DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3471{
3472 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3473 return ((uint32_t)f64Bit << 31)
3474 | UINT32_C(0x1ac00000)
3475 | (UINT32_C(10) << 10)
3476 | (iRegCount << 16)
3477 | (iRegSrc << 5)
3478 | iRegResult;
3479}
3480
3481
3482/** A64: Encodes a RORV instruction. */
3483DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3484{
3485 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3486 return ((uint32_t)f64Bit << 31)
3487 | UINT32_C(0x1ac00000)
3488 | (UINT32_C(11) << 10)
3489 | (iRegCount << 16)
3490 | (iRegSrc << 5)
3491 | iRegResult;
3492}
3493
3494
3495/** A64: Encodes a PACGA instruction. */
3496DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3497{
3498 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3499 return UINT32_C(0x80000000)
3500 | UINT32_C(0x1ac00000)
3501 | (UINT32_C(12) << 10)
3502 | (iRegSrc2 << 16)
3503 | (iRegSrc1 << 5)
3504 | iRegResult;
3505}
3506
3507
3508/** A64: Encodes a CRC32* instruction. */
3509DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3510{
3511 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3512 return ((uint32_t)(uSize == 3) << 31)
3513 | UINT32_C(0x1ac00000)
3514 | (UINT32_C(16) << 10)
3515 | (uSize << 10)
3516 | (iRegValue << 16)
3517 | (iRegCrc << 5)
3518 | iRegResult;
3519}
3520
3521
3522/** A64: Encodes a CRC32B instruction. */
3523DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3524{
3525 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
3526}
3527
3528
3529/** A64: Encodes a CRC32H instruction. */
3530DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3531{
3532 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
3533}
3534
3535
3536/** A64: Encodes a CRC32W instruction. */
3537DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3538{
3539 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
3540}
3541
3542
3543/** A64: Encodes a CRC32X instruction. */
3544DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3545{
3546 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
3547}
3548
3549
3550/** A64: Encodes a CRC32C* instruction. */
3551DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3552{
3553 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3554 return ((uint32_t)(uSize == 3) << 31)
3555 | UINT32_C(0x1ac00000)
3556 | (UINT32_C(20) << 10)
3557 | (uSize << 10)
3558 | (iRegValue << 16)
3559 | (iRegCrc << 5)
3560 | iRegResult;
3561}
3562
3563
3564/** A64: Encodes a CRC32B instruction. */
3565DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3566{
3567 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
3568}
3569
3570
3571/** A64: Encodes a CRC32CH instruction. */
3572DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3573{
3574 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
3575}
3576
3577
3578/** A64: Encodes a CRC32CW instruction. */
3579DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3580{
3581 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
3582}
3583
3584
3585/** A64: Encodes a CRC32CX instruction. */
3586DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3587{
3588 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
3589}
3590
3591
3592/** A64: Encodes an SMAX instruction. */
3593DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3594{
3595 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3596 return ((uint32_t)f64Bit << 31)
3597 | UINT32_C(0x1ac00000)
3598 | (UINT32_C(24) << 10)
3599 | (iRegSrc2 << 16)
3600 | (iRegSrc1 << 5)
3601 | iRegResult;
3602}
3603
3604
3605/** A64: Encodes an UMAX instruction. */
3606DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3607{
3608 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3609 return ((uint32_t)f64Bit << 31)
3610 | UINT32_C(0x1ac00000)
3611 | (UINT32_C(25) << 10)
3612 | (iRegSrc2 << 16)
3613 | (iRegSrc1 << 5)
3614 | iRegResult;
3615}
3616
3617
3618/** A64: Encodes an SMIN instruction. */
3619DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3620{
3621 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3622 return ((uint32_t)f64Bit << 31)
3623 | UINT32_C(0x1ac00000)
3624 | (UINT32_C(26) << 10)
3625 | (iRegSrc2 << 16)
3626 | (iRegSrc1 << 5)
3627 | iRegResult;
3628}
3629
3630
3631/** A64: Encodes an UMIN instruction. */
3632DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3633{
3634 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3635 return ((uint32_t)f64Bit << 31)
3636 | UINT32_C(0x1ac00000)
3637 | (UINT32_C(27) << 10)
3638 | (iRegSrc2 << 16)
3639 | (iRegSrc1 << 5)
3640 | iRegResult;
3641}
3642
3643
3644# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
3645
3646/**
3647 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
3648 *
3649 * @returns The decoded mask.
3650 * @param uImm6SizeLen The immS value from the instruction. (No N part
3651 * here, as that must be zero for instructions
3652 * operating on 32-bit wide registers.)
3653 * @param uImm6Rotations The immR value from the instruction.
3654 */
3655DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3656{
3657 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
3658
3659 /* Determine the element size. */
3660 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
3661 Assert(cBitsElementLog2 + 1U != 0U);
3662
3663 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3664 Assert(uImm6Rotations < cBitsElement);
3665
3666 /* Extract the number of bits set to 1: */
3667 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
3668 Assert(cBitsSetTo1 < cBitsElement);
3669 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
3670
3671 /* Produce the unrotated pattern. */
3672 static const uint32_t s_auReplicate[]
3673 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3674 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3675
3676 /* Rotate it and return. */
3677 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
3678}
3679
3680
3681/**
3682 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
3683 *
3684 * @returns The decoded mask.
3685 * @param uImm7SizeLen The N:immS value from the instruction.
3686 * @param uImm6Rotations The immR value from the instruction.
3687 */
3688DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
3689{
3690 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
3691
3692 /* Determine the element size. */
3693 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
3694 Assert(cBitsElementLog2 + 1U != 0U);
3695
3696 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3697 Assert(uImm6Rotations < cBitsElement);
3698
3699 /* Extract the number of bits set to 1: */
3700 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
3701 Assert(cBitsSetTo1 < cBitsElement);
3702 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
3703
3704 /* Produce the unrotated pattern. */
3705 static const uint64_t s_auReplicate[]
3706 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3707 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3708
3709 /* Rotate it and return. */
3710 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
3711}
3712
3713
3714/**
3715 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
3716 * the immS value.
3717 */
3718DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3719{
3720 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
3721}
3722
3723
3724/**
3725 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3726 * 32-bit bitmask to a set of immediates for those instructions.
3727 *
3728 * @returns true if successful, false if not.
3729 * @param fMask The mask value to convert.
3730 * @param puImm6SizeLen Where to return the immS part (N is always zero for
3731 * 32-bit wide masks).
3732 * @param puImm6Rotations Where to return the immR.
3733 */
3734DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
3735{
3736 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
3737 if ((uint32_t)(fMask + 1U) <= 1)
3738 return false;
3739
3740 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3741 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
3742 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
3743 if (cRor)
3744 fMask = ASMRotateRightU32(fMask, cRor);
3745 else
3746 fMask = ASMRotateLeftU32(fMask, cRol);
3747 Assert(fMask & RT_BIT_32(0));
3748 Assert(!(fMask & RT_BIT_32(31)));
3749
3750 /* Count the trailing ones and leading zeros. */
3751 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
3752 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
3753
3754 /* The potential element length is then the sum of the two above. */
3755 unsigned const cBitsElement = cOnes + cZeros;
3756 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3757 return false;
3758
3759 /* Special case: 32 bits element size. Since we're done here. */
3760 if (cBitsElement == 32)
3761 *puImm6SizeLen = cOnes - 1;
3762 else
3763 {
3764 /* Extract the element bits and check that these are replicated in the whole pattern. */
3765 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
3766 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
3767
3768 static const uint32_t s_auReplicate[]
3769 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3770 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3771 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3772 else
3773 return false;
3774 }
3775 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3776
3777 return true;
3778}
3779
3780
3781/**
3782 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3783 * 64-bit bitmask to a set of immediates for those instructions.
3784 *
3785 * @returns true if successful, false if not.
3786 * @param fMask The mask value to convert.
3787 * @param puImm7SizeLen Where to return the N:immS part.
3788 * @param puImm6Rotations Where to return the immR.
3789 */
3790DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
3791{
3792 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
3793 if ((uint64_t)(fMask + 1U) <= 1)
3794 return false;
3795
3796 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3797 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
3798 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
3799 if (cRor)
3800 fMask = ASMRotateRightU64(fMask, cRor);
3801 else
3802 fMask = ASMRotateLeftU64(fMask, cRol);
3803 Assert(fMask & RT_BIT_64(0));
3804 Assert(!(fMask & RT_BIT_64(63)));
3805
3806 /* Count the trailing ones and leading zeros. */
3807 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
3808 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
3809
3810 /* The potential element length is then the sum of the two above. */
3811 unsigned const cBitsElement = cOnes + cZeros;
3812 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3813 return false;
3814
3815 /* Special case: 64 bits element size. Since we're done here. */
3816 if (cBitsElement == 64)
3817 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
3818 else
3819 {
3820 /* Extract the element bits and check that these are replicated in the whole pattern. */
3821 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
3822 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
3823
3824 static const uint64_t s_auReplicate[]
3825 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3826 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3827 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3828 else
3829 return false;
3830 }
3831 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3832
3833 return true;
3834}
3835
3836# endif /* IPRT_INCLUDED_asm_h */
3837
3838/**
3839 * A64: Encodes a logical instruction with an complicated immediate mask.
3840 *
3841 * The @a uImm7SizeLen parameter specifies two things:
3842 * 1. the element size and
3843 * 2. the number of bits set to 1 in the pattern.
3844 *
3845 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
3846 * top) and using the position of the first bit set as a power of two.
3847 *
3848 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
3849 * |---|---|---|---|---|---|---|--------------|
3850 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
3851 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
3852 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
3853 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
3854 * | 0 | 0 | x | x | x | x | x | 32 bits |
3855 * | 1 | x | x | x | x | x | x | 64 bits |
3856 *
3857 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
3858 * there is always one zero bit in the pattern).
3859 *
3860 * The @a uImm6Rotations parameter specifies how many bits to the right,
3861 * the element pattern is rotated. The rotation count must be less than the
3862 * element bit count (size).
3863 *
3864 * @returns The encoded instruction.
3865 * @param u2Opc The logical operation to perform.
3866 * @param iRegResult The output register.
3867 * @param iRegSrc The 1st register operand.
3868 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
3869 * field at the top of the 6-bit 'imms' field.
3870 *
3871 * @param uImm6Rotations The rotation count.
3872 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3873 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3874 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3875 */
3876DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3877 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
3878{
3879 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x3f)));
3880 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
3881 return ((uint32_t)f64Bit << 31)
3882 | (u2Opc << 29)
3883 | UINT32_C(0x12000000)
3884 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
3885 | (uImm6Rotations << 16)
3886 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
3887 | (iRegSrc << 5)
3888 | iRegResult;
3889}
3890
3891
3892/** A64: Encodes an AND instruction w/ complicated immediate mask.
3893 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3894DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
3895 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3896{
3897 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3898}
3899
3900
3901/** A64: Encodes an ORR instruction w/ complicated immediate mask.
3902 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3903DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
3904 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3905{
3906 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3907}
3908
3909
3910/** A64: Encodes an EOR instruction w/ complicated immediate mask.
3911 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3912DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
3913 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3914{
3915 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3916}
3917
3918
3919/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
3920 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3921DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
3922 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3923{
3924 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3925}
3926
3927
3928/** A64: Encodes an TST instruction w/ complicated immediate mask.
3929 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3930DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
3931 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3932{
3933 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3934}
3935
3936
3937/**
3938 * A64: Encodes a bitfield instruction.
3939 *
3940 * @returns The encoded instruction.
3941 * @param u2Opc The bitfield operation to perform.
3942 * @param iRegResult The output register.
3943 * @param iRegSrc The 1st register operand.
3944 * @param cImm6Ror The right rotation count.
3945 * @param uImm6S The leftmost bit to be moved.
3946 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3947 * @param uN1 This must match @a f64Bit for all instructions
3948 * currently specified.
3949 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3950 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3951 */
3952DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3953 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
3954{
3955 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
3956 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
3957 return ((uint32_t)f64Bit << 31)
3958 | (u2Opc << 29)
3959 | UINT32_C(0x13000000)
3960 | (uN1 << 22)
3961 | (cImm6Ror << 16)
3962 | (uImm6S << 10)
3963 | (iRegSrc << 5)
3964 | iRegResult;
3965}
3966
3967
3968/** A64: Encodes a SBFM instruction.
3969 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3970DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3971 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3972{
3973 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3974}
3975
3976
3977/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
3978 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3979DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3980{
3981 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
3982}
3983
3984
3985/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
3986 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3987DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3988{
3989 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
3990}
3991
3992
3993/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
3994 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3995DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
3996{
3997 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
3998}
3999
4000
4001/** A64: Encodes an ASR instruction w/ immediate shift value.
4002 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4003DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4004{
4005 uint32_t const cWidth = f64Bit ? 63 : 31;
4006 Assert(cShift > 0); Assert(cShift <= cWidth);
4007 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
4008}
4009
4010
4011/** A64: Encodes a BFM instruction.
4012 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4013DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4014 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4015{
4016 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4017}
4018
4019
4020/** A64: Encodes a BFI instruction (insert).
4021 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4022DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
4023 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4024{
4025 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4026 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
4027 cBitsWidth - 1, f64Bit);
4028}
4029
4030
4031/** A64: Encodes a BFC instruction (clear).
4032 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4033DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfc(uint32_t iRegResult,
4034 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4035{
4036 return Armv8A64MkInstrBfi(iRegResult, ARMV8_A64_REG_XZR, offFirstBit, cBitsWidth, f64Bit);
4037}
4038
4039
4040/** A64: Encodes a BFXIL instruction (insert low).
4041 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4042DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfxil(uint32_t iRegResult, uint32_t iRegSrc,
4043 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4044{
4045 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4046 Assert(offFirstBit + cBitsWidth <= (f64Bit ? 64U : 32U));
4047 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4048}
4049
4050
4051/** A64: Encodes an UBFM instruction.
4052 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4053DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4054 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4055{
4056 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4057}
4058
4059
4060/** A64: Encodes an UBFX instruction (zero extending extract).
4061 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4062DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
4063 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4064{
4065 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4066}
4067
4068
4069/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
4070 * shifted into destination).
4071 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4072DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
4073 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
4074{
4075 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
4076 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
4077}
4078
4079
4080/** A64: Encodes an LSL instruction w/ immediate shift value.
4081 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4082DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4083{
4084 uint32_t const cWidth = f64Bit ? 63 : 31;
4085 Assert(cShift > 0); Assert(cShift <= cWidth);
4086 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
4087 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
4088}
4089
4090
4091/** A64: Encodes an LSR instruction w/ immediate shift value.
4092 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4093DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4094{
4095 uint32_t const cWidth = f64Bit ? 63 : 31;
4096 Assert(cShift > 0); Assert(cShift <= cWidth);
4097 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
4098}
4099
4100
4101/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
4102 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4103DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4104{
4105 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
4106}
4107
4108
4109/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
4110 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4111DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4112{
4113 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
4114}
4115
4116
4117/**
4118 * A64: Encodes an EXTR instruction with an immediate.
4119 *
4120 * @returns The encoded instruction.
4121 * @param iRegResult The register to store the result in. ZR is valid.
4122 * @param iRegLow The register holding the least significant bits in the
4123 * extraction. ZR is valid.
4124 * @param iRegHigh The register holding the most significant bits in the
4125 * extraction. ZR is valid.
4126 * @param uLsb The bit number of the least significant bit, or where in
4127 * @a iRegLow to start the
4128 * extraction.
4129 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4130 */
4131DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
4132 bool f64Bit = true)
4133{
4134 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
4135 return ((uint32_t)f64Bit << 31)
4136 | UINT32_C(0x13800000)
4137 | ((uint32_t)f64Bit << 22) /*N*/
4138 | (iRegHigh << 16)
4139 | (uLsb << 10)
4140 | (iRegLow << 5)
4141 | iRegResult;
4142}
4143
4144
4145/** A64: Rotates the value of a register (alias for EXTR). */
4146DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4147{
4148 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
4149}
4150
4151
4152/**
4153 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
4154 *
4155 * @returns The encoded instruction.
4156 * @param fSub true for sub and subs, false for add and
4157 * adds.
4158 * @param iRegResult The register to store the result in.
4159 * SP is valid when @a fSetFlags = false,
4160 * and ZR is valid otherwise.
4161 * @param iRegSrc The register containing the augend (@a fSub
4162 * = false) or minuend (@a fSub = true). SP is
4163 * a valid registers for all variations.
4164 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
4165 * (@a fSub = true).
4166 * @param f64Bit true for 64-bit GRPs (default), false for
4167 * 32-bit GPRs.
4168 * @param fSetFlags Whether to set flags (adds / subs) or not
4169 * (add / sub - default).
4170 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
4171 * bits to the left, or not (default).
4172 */
4173DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
4174 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
4175 bool fSetFlags = false, bool fShift12 = false)
4176{
4177 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
4178 return ((uint32_t)f64Bit << 31)
4179 | ((uint32_t)fSub << 30)
4180 | ((uint32_t)fSetFlags << 29)
4181 | UINT32_C(0x11000000)
4182 | ((uint32_t)fShift12 << 22)
4183 | (uImm12AddendSubtrahend << 10)
4184 | (iRegSrc << 5)
4185 | iRegResult;
4186}
4187
4188
4189/** Alias for sub zxr, reg, \#uimm12. */
4190DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
4191 bool f64Bit = true, bool fShift12 = false)
4192{
4193 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
4194 f64Bit, true /*fSetFlags*/, fShift12);
4195}
4196
4197
4198/** ADD dst, src, \#uimm12 */
4199DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
4200 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4201{
4202 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
4203}
4204
4205
4206/** SUB dst, src, \#uimm12 */
4207DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
4208 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4209{
4210 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
4211}
4212
4213
4214/**
4215 * A64: Encodes either add, adds, sub or subs with shifted register.
4216 *
4217 * @returns The encoded instruction.
4218 * @param fSub true for sub and subs, false for add and
4219 * adds.
4220 * @param iRegResult The register to store the result in.
4221 * SP is NOT valid, but ZR is.
4222 * @param iRegSrc1 The register containing the augend (@a fSub
4223 * = false) or minuend (@a fSub = true).
4224 * SP is NOT valid, but ZR is.
4225 * @param iRegSrc2 The register containing the addened (@a fSub
4226 * = false) or subtrahend (@a fSub = true).
4227 * SP is NOT valid, but ZR is.
4228 * @param f64Bit true for 64-bit GRPs (default), false for
4229 * 32-bit GPRs.
4230 * @param fSetFlags Whether to set flags (adds / subs) or not
4231 * (add / sub - default).
4232 * @param cShift The shift count to apply to @a iRegSrc2.
4233 * @param enmShift The shift type to apply to the @a iRegSrc2
4234 * register. kArmv8A64InstrShift_Ror is
4235 * reserved.
4236 */
4237DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4238 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4239 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4240{
4241 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4242 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
4243
4244 return ((uint32_t)f64Bit << 31)
4245 | ((uint32_t)fSub << 30)
4246 | ((uint32_t)fSetFlags << 29)
4247 | UINT32_C(0x0b000000)
4248 | ((uint32_t)enmShift << 22)
4249 | (iRegSrc2 << 16)
4250 | (cShift << 10)
4251 | (iRegSrc1 << 5)
4252 | iRegResult;
4253}
4254
4255
4256/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
4257DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
4258 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4259{
4260 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
4261 f64Bit, true /*fSetFlags*/, cShift, enmShift);
4262}
4263
4264
4265/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4266DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4267 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4268 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4269{
4270 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4271}
4272
4273
4274/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4275DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4276 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4277 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4278{
4279 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4280}
4281
4282
4283/** NEG dst */
4284DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
4285{
4286 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
4287}
4288
4289
4290/** Extension option for 'extended register' instructions. */
4291typedef enum ARMV8A64INSTREXTEND
4292{
4293 kArmv8A64InstrExtend_UxtB = 0,
4294 kArmv8A64InstrExtend_UxtH,
4295 kArmv8A64InstrExtend_UxtW,
4296 kArmv8A64InstrExtend_UxtX,
4297 kArmv8A64InstrExtend_SxtB,
4298 kArmv8A64InstrExtend_SxtH,
4299 kArmv8A64InstrExtend_SxtW,
4300 kArmv8A64InstrExtend_SxtX,
4301 /** The default is either UXTW or UXTX depending on whether the instruction
4302 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
4303 * to the f64Bit value. */
4304 kArmv8A64InstrExtend_Default
4305} ARMV8A64INSTREXTEND;
4306
4307
4308/**
4309 * A64: Encodes either add, adds, sub or subs with extended register encoding.
4310 *
4311 * @returns The encoded instruction.
4312 * @param fSub true for sub and subs, false for add and
4313 * adds.
4314 * @param iRegResult The register to store the result in.
4315 * SP is NOT valid, but ZR is.
4316 * @param iRegSrc1 The register containing the augend (@a fSub
4317 * = false) or minuend (@a fSub = true).
4318 * SP is valid, but ZR is NOT.
4319 * @param iRegSrc2 The register containing the addened (@a fSub
4320 * = false) or subtrahend (@a fSub = true).
4321 * SP is NOT valid, but ZR is.
4322 * @param f64Bit true for 64-bit GRPs (default), false for
4323 * 32-bit GPRs.
4324 * @param fSetFlags Whether to set flags (adds / subs) or not
4325 * (add / sub - default).
4326 * @param enmExtend The type of extension to apply to @a
4327 * iRegSrc2.
4328 * @param cShift The left shift count to apply to @a iRegSrc2
4329 * after enmExtend processing is done.
4330 * Max shift is 4 for some reason.
4331 */
4332DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4333 bool f64Bit = true, bool fSetFlags = false,
4334 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
4335 uint32_t cShift = 0)
4336{
4337 if (enmExtend == kArmv8A64InstrExtend_Default)
4338 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
4339 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
4340
4341 return ((uint32_t)f64Bit << 31)
4342 | ((uint32_t)fSub << 30)
4343 | ((uint32_t)fSetFlags << 29)
4344 | UINT32_C(0x0b200000)
4345 | (iRegSrc2 << 16)
4346 | ((uint32_t)enmExtend << 13)
4347 | (cShift << 10)
4348 | (iRegSrc1 << 5)
4349 | iRegResult;
4350}
4351
4352
4353/**
4354 * A64: Encodes either adc, adcs, sbc or sbcs with two source registers.
4355 *
4356 * @returns The encoded instruction.
4357 * @param fSub true for sbc and sbcs, false for adc and
4358 * adcs.
4359 * @param iRegResult The register to store the result in. SP is
4360 * NOT valid, but ZR is.
4361 * @param iRegSrc1 The register containing the augend (@a fSub
4362 * = false) or minuend (@a fSub = true).
4363 * SP is NOT valid, but ZR is.
4364 * @param iRegSrc2 The register containing the addened (@a fSub
4365 * = false) or subtrahend (@a fSub = true).
4366 * SP is NOT valid, but ZR is.
4367 * @param f64Bit true for 64-bit GRPs (default), false for
4368 * 32-bit GPRs.
4369 * @param fSetFlags Whether to set flags (adds / subs) or not
4370 * (add / sub - default).
4371 */
4372DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcSbc(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4373 bool f64Bit = true, bool fSetFlags = false)
4374{
4375 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4376
4377 return ((uint32_t)f64Bit << 31)
4378 | ((uint32_t)fSub << 30)
4379 | ((uint32_t)fSetFlags << 29)
4380 | UINT32_C(0x1a000000)
4381 | (iRegSrc2 << 16)
4382 | (iRegSrc1 << 5)
4383 | iRegResult;
4384}
4385
4386
4387/** ADC dst, reg1, reg2 */
4388DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4389 bool f64Bit = true, bool fSetFlags = false)
4390{
4391 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4392}
4393
4394
4395/** ADCS dst, reg1, reg2 */
4396DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4397{
4398 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4399}
4400
4401
4402/** SBC dst, reg1, reg2 */
4403DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4404 bool f64Bit = true, bool fSetFlags = false)
4405{
4406 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4407}
4408
4409
4410/** SBCS dst, reg1, reg2 */
4411DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4412{
4413 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4414}
4415
4416
4417/**
4418 * A64: Encodes a B (unconditional branch w/ imm) instruction.
4419 *
4420 * @returns The encoded instruction.
4421 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4422 */
4423DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
4424{
4425 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
4426 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
4427}
4428
4429
4430/**
4431 * A64: Encodes a BL (unconditional call w/ imm) instruction.
4432 *
4433 * @returns The encoded instruction.
4434 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4435 */
4436DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
4437{
4438 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
4439}
4440
4441
4442/**
4443 * A64: Encodes a BR (unconditional branch w/ register) instruction.
4444 *
4445 * @returns The encoded instruction.
4446 * @param iReg The register containing the target address.
4447 */
4448DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
4449{
4450 Assert(iReg < 32);
4451 return UINT32_C(0xd61f0000) | (iReg << 5);
4452}
4453
4454
4455/**
4456 * A64: Encodes a BLR instruction.
4457 *
4458 * @returns The encoded instruction.
4459 * @param iReg The register containing the target address.
4460 */
4461DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
4462{
4463 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
4464}
4465
4466
4467/**
4468 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
4469 *
4470 * @returns The encoded instruction.
4471 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4472 * its not zero.
4473 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4474 * @param iReg The GPR to check for zero / non-zero value.
4475 * @param f64Bit true for 64-bit register, false for 32-bit.
4476 */
4477DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4478{
4479 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
4480 return ((uint32_t)f64Bit << 31)
4481 | UINT32_C(0x34000000)
4482 | ((uint32_t)fJmpIfNotZero << 24)
4483 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4484 | iReg;
4485}
4486
4487
4488/** A64: Encodes the CBZ instructions. */
4489DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4490{
4491 return Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4492}
4493
4494
4495/** A64: Encodes the CBNZ instructions. */
4496DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbnz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4497{
4498 return Armv8A64MkInstrCbzCbnz(true /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4499}
4500
4501
4502/**
4503 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
4504 *
4505 * @returns The encoded instruction.
4506 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4507 * its not zero.
4508 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4509 * @param iReg The GPR to check for zero / non-zero value.
4510 * @param iBitNo The bit to test for.
4511 */
4512DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4513{
4514 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
4515 return ((uint32_t)(iBitNo & 0x20) << (31-5))
4516 | UINT32_C(0x36000000)
4517 | ((uint32_t)fJmpIfNotZero << 24)
4518 | ((iBitNo & 0x1f) << 19)
4519 | (((uint32_t)iImm14 & 0x3fff) << 5)
4520 | iReg;
4521}
4522
4523
4524/**
4525 * A64: Encodes TBZ (conditional branch w/ immediate) instructions.
4526 *
4527 * @returns The encoded instruction.
4528 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4529 * @param iReg The GPR to check for zero / non-zero value.
4530 * @param iBitNo The bit to test for.
4531 */
4532DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4533{
4534 return Armv8A64MkInstrTbzTbnz(false /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4535}
4536
4537
4538/**
4539 * A64: Encodes TBNZ (conditional branch w/ immediate) instructions.
4540 *
4541 * @returns The encoded instruction.
4542 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4543 * @param iReg The GPR to check for zero / non-zero value.
4544 * @param iBitNo The bit to test for.
4545 */
4546DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbnz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4547{
4548 return Armv8A64MkInstrTbzTbnz(true /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4549}
4550
4551
4552
4553/** Armv8 Condition codes. */
4554typedef enum ARMV8INSTRCOND
4555{
4556 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
4557 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
4558
4559 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
4560 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
4561 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
4562 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
4563
4564 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
4565 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
4566
4567 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
4568 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
4569
4570 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
4571 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
4572
4573 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
4574 kArmv8InstrCond_Lt, /**< b - Signed less than. */
4575
4576 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
4577 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
4578
4579 kArmv8InstrCond_Al, /**< e - Condition is always true. */
4580 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
4581} ARMV8INSTRCOND;
4582
4583/**
4584 * A64: Encodes conditional branch instruction w/ immediate target.
4585 *
4586 * @returns The encoded instruction.
4587 * @param enmCond The branch condition.
4588 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4589 */
4590DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
4591{
4592 Assert((unsigned)enmCond < 16);
4593 return UINT32_C(0x54000000)
4594 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4595 | (uint32_t)enmCond;
4596}
4597
4598
4599/**
4600 * A64: Encodes the BRK instruction.
4601 *
4602 * @returns The encoded instruction.
4603 * @param uImm16 Unsigned immediate value.
4604 */
4605DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
4606{
4607 Assert(uImm16 < _64K);
4608 return UINT32_C(0xd4200000)
4609 | (uImm16 << 5);
4610}
4611
4612/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
4613 * @{ */
4614#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
4615#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
4616#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
4617#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
4618#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
4619#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
4620#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
4621#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
4622
4623#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
4624#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
4625#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
4626#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
4627#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
4628#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
4629#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
4630#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
4631/** @} */
4632
4633/**
4634 * A64: Encodes CCMP or CCMN with two register operands.
4635 *
4636 * @returns The encoded instruction.
4637 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
4638 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
4639 * @param fNzcv The N, Z, C & V flags values to load if the condition
4640 * does not match. See RMA64_NZCV_F_XXX.
4641 * @param enmCond The condition guarding the compare.
4642 * @param fCCmp Set for CCMP (default), clear for CCMN.
4643 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4644 */
4645DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4646 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
4647{
4648 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
4649
4650 return ((uint32_t)f64Bit << 31)
4651 | ((uint32_t)fCCmp << 30)
4652 | UINT32_C(0x3a400000)
4653 | (iRegSrc2 << 16)
4654 | ((uint32_t)enmCond << 12)
4655 | (iRegSrc1 << 5)
4656 | fNzcv;
4657}
4658
4659/** CCMP w/ reg. */
4660DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4661 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4662{
4663 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4664}
4665
4666
4667/** CCMN w/ reg. */
4668DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4669 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4670{
4671 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4672}
4673
4674
4675/**
4676 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
4677 *
4678 * @returns The encoded instruction.
4679 * @param iRegSrc The register. SP is NOT valid, but ZR is.
4680 * @param uImm5 The immediate, to compare iRegSrc with.
4681 * @param fNzcv The N, Z, C & V flags values to load if the condition
4682 * does not match. See RMA64_NZCV_F_XXX.
4683 * @param enmCond The condition guarding the compare.
4684 * @param fCCmp Set for CCMP (default), clear for CCMN.
4685 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4686 */
4687DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
4688 bool fCCmp = true, bool f64Bit = true)
4689{
4690 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
4691
4692 return ((uint32_t)f64Bit << 31)
4693 | ((uint32_t)fCCmp << 30)
4694 | UINT32_C(0x3a400800)
4695 | (uImm5 << 16)
4696 | ((uint32_t)enmCond << 12)
4697 | (iRegSrc << 5)
4698 | fNzcv;
4699}
4700
4701/** CCMP w/ immediate. */
4702DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4703 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4704{
4705 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4706}
4707
4708
4709/** CCMN w/ immediate. */
4710DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4711 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4712{
4713 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4714}
4715
4716
4717/**
4718 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
4719 *
4720 * @returns The encoded instruction.
4721 * @param uOp Opcode bit 30.
4722 * @param uOp2 Opcode bits 11:10.
4723 * @param iRegResult The result register. SP is NOT valid, but ZR is.
4724 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
4725 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
4726 * @param enmCond The condition guarding the compare.
4727 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4728 */
4729DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
4730 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4731{
4732 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4733
4734 return ((uint32_t)f64Bit << 31)
4735 | (uOp << 30)
4736 | UINT32_C(0x1a800000)
4737 | (iRegSrc2 << 16)
4738 | ((uint32_t)enmCond << 12)
4739 | (uOp2 << 10)
4740 | (iRegSrc1 << 5)
4741 | iRegResult;
4742}
4743
4744
4745/** A64: Encodes CSEL.
4746 * @see Armv8A64MkInstrCondSelect for details. */
4747DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4748 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4749{
4750 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4751}
4752
4753
4754/** A64: Encodes CSINC.
4755 * @see Armv8A64MkInstrCondSelect for details. */
4756DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4757 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4758{
4759 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4760}
4761
4762
4763/** A64: Encodes CSET.
4764 * @see Armv8A64MkInstrCondSelect for details. */
4765DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4766{
4767 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4768 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4769 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4770}
4771
4772
4773/** A64: Encodes CSINV.
4774 * @see Armv8A64MkInstrCondSelect for details. */
4775DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4776 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4777{
4778 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4779}
4780
4781/** A64: Encodes CSETM.
4782 * @see Armv8A64MkInstrCondSelect for details. */
4783DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4784{
4785 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4786 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4787 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4788}
4789
4790
4791/** A64: Encodes CSNEG.
4792 * @see Armv8A64MkInstrCondSelect for details. */
4793DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4794 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4795{
4796 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4797}
4798
4799
4800/**
4801 * A64: Encodes REV instruction.
4802 *
4803 * @returns The encoded instruction.
4804 * @param iRegDst The destination register. SP is NOT valid.
4805 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4806 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4807 */
4808DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4809{
4810 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4811
4812 return ((uint32_t)f64Bit << 31)
4813 | UINT32_C(0x5ac00800)
4814 | ((uint32_t)f64Bit << 10)
4815 | (iRegSrc << 5)
4816 | iRegDst;
4817}
4818
4819
4820/**
4821 * A64: Encodes REV16 instruction.
4822 *
4823 * @returns The encoded instruction.
4824 * @param iRegDst The destination register. SP is NOT valid.
4825 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4826 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4827 */
4828DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4829{
4830 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4831
4832 return ((uint32_t)f64Bit << 31)
4833 | UINT32_C(0x5ac00400)
4834 | (iRegSrc << 5)
4835 | iRegDst;
4836}
4837
4838
4839/**
4840 * A64: Encodes SETF8 & SETF16.
4841 *
4842 * @returns The encoded instruction.
4843 * @param iRegResult The register holding the result. SP is NOT valid.
4844 * @param f16Bit Set for SETF16, clear for SETF8.
4845 */
4846DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
4847{
4848 Assert(iRegResult < 32);
4849
4850 return UINT32_C(0x3a00080d)
4851 | ((uint32_t)f16Bit << 14)
4852 | (iRegResult << 5);
4853}
4854
4855
4856/**
4857 * A64: Encodes RMIF.
4858 *
4859 * @returns The encoded instruction.
4860 * @param iRegSrc The source register to get flags from.
4861 * @param cRotateRight The right rotate count (LSB bit offset).
4862 * @param fMask Mask of which flag bits to set:
4863 * - bit 0: V
4864 * - bit 1: C
4865 * - bit 2: Z
4866 * - bit 3: N
4867 */
4868DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRmif(uint32_t iRegSrc, uint32_t cRotateRight, uint32_t fMask)
4869{
4870 Assert(iRegSrc < 32); Assert(cRotateRight < 64); Assert(fMask <= 0xf);
4871
4872 return UINT32_C(0xba000400)
4873 | (cRotateRight << 15)
4874 | (iRegSrc << 5)
4875 | fMask;
4876}
4877
4878
4879/**
4880 * A64: Encodes MRS (for reading a system register into a GPR).
4881 *
4882 * @returns The encoded instruction.
4883 * @param iRegDst The register to put the result into. SP is NOT valid.
4884 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4885 * IPRT specific format, of the register to read.
4886 */
4887DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
4888{
4889 Assert(iRegDst < 32);
4890 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4891
4892 /* Note. The top bit of idSysReg must always be set and is also set in
4893 0xd5300000, otherwise we'll be encoding a different instruction. */
4894 return UINT32_C(0xd5300000)
4895 | (idSysReg << 5)
4896 | iRegDst;
4897}
4898
4899
4900/**
4901 * A64: Encodes MSR (for writing a GPR to a system register).
4902 *
4903 * @returns The encoded instruction.
4904 * @param iRegSrc The register which value to write. SP is NOT valid.
4905 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4906 * IPRT specific format, of the register to write.
4907 */
4908DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
4909{
4910 Assert(iRegSrc < 32);
4911 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4912
4913 /* Note. The top bit of idSysReg must always be set and is also set in
4914 0xd5100000, otherwise we'll be encoding a different instruction. */
4915 return UINT32_C(0xd5100000)
4916 | (idSysReg << 5)
4917 | iRegSrc;
4918}
4919
4920
4921/** @} */
4922
4923
4924/** @defgroup grp_rt_armv8_mkinstr_vec Vector Instruction Encoding Helpers
4925 * @ingroup grp_rt_armv8_mkinstr
4926 *
4927 * A few inlined functions and macros for assisting in encoding common ARMv8
4928 * Neon/SIMD instructions.
4929 *
4930 * @{ */
4931
4932/** Armv8 vector logical operation. */
4933typedef enum
4934{
4935 kArmv8VecInstrLogicOp_And = 0, /**< AND */
4936 kArmv8VecInstrLogicOp_Bic = RT_BIT_32(22), /**< BIC */
4937 kArmv8VecInstrLogicOp_Orr = RT_BIT_32(23), /**< ORR */
4938 kArmv8VecInstrLogicOp_Orn = RT_BIT_32(23) | RT_BIT_32(22), /**< ORN */
4939 kArmv8VecInstrLogicOp_Eor = RT_BIT_32(29), /**< EOR */
4940 kArmv8VecInstrLogicOp_Bsl = RT_BIT_32(29) | RT_BIT_32(22), /**< BSL */
4941 kArmv8VecInstrLogicOp_Bit = RT_BIT_32(29) | RT_BIT_32(23), /**< BIT */
4942 kArmv8VecInstrLogicOp_Bif = RT_BIT_32(29) | RT_BIT_32(23) | RT_BIT_32(22) /**< BIF */
4943} ARMV8INSTRVECLOGICOP;
4944
4945
4946/**
4947 * A64: Encodes logical instruction (vector, register).
4948 *
4949 * @returns The encoded instruction.
4950 * @param enmOp The operation to encode.
4951 * @param iVecRegDst The vector register to put the result into.
4952 * @param iVecRegSrc1 The 1st source register.
4953 * @param iVecRegSrc2 The 2nd source register.
4954 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4955 * or just the low 64-bit (false).
4956 */
4957DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrLogical(ARMV8INSTRVECLOGICOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4958 bool f128Bit = true)
4959{
4960 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4961
4962 return UINT32_C(0x0e201c00)
4963 | (uint32_t)enmOp
4964 | ((uint32_t)f128Bit << 30)
4965 | (iVecRegSrc2 << 16)
4966 | (iVecRegSrc1 << 5)
4967 | iVecRegDst;
4968}
4969
4970
4971/**
4972 * A64: Encodes ORR (vector, register).
4973 *
4974 * @returns The encoded instruction.
4975 * @param iVecRegDst The vector register to put the result into.
4976 * @param iVecRegSrc1 The 1st source register.
4977 * @param iVecRegSrc2 The 2nd source register.
4978 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4979 * or just the low 64-bit (false).
4980 */
4981DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrOrr(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4982 bool f128Bit = true)
4983{
4984 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Orr, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
4985}
4986
4987
4988/**
4989 * A64: Encodes EOR (vector, register).
4990 *
4991 * @returns The encoded instruction.
4992 * @param iVecRegDst The vector register to put the result into.
4993 * @param iVecRegSrc1 The 1st source register.
4994 * @param iVecRegSrc2 The 2nd source register.
4995 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4996 * or just the low 64-bit (false).
4997 */
4998DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrEor(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4999 bool f128Bit = true)
5000{
5001 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Eor, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5002}
5003
5004
5005/**
5006 * A64: Encodes AND (vector, register).
5007 *
5008 * @returns The encoded instruction.
5009 * @param iVecRegDst The vector register to put the result into.
5010 * @param iVecRegSrc1 The 1st source register.
5011 * @param iVecRegSrc2 The 2nd source register.
5012 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5013 * or just the low 64-bit (false).
5014 */
5015DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAnd(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5016 bool f128Bit = true)
5017{
5018 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_And, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5019}
5020
5021
5022/** Armv8 UMOV/INS vector element size. */
5023typedef enum ARMV8INSTRUMOVINSSZ
5024{
5025 kArmv8InstrUmovInsSz_U8 = 0, /**< Byte. */
5026 kArmv8InstrUmovInsSz_U16 = 1, /**< Halfword. */
5027 kArmv8InstrUmovInsSz_U32 = 2, /**< 32-bit. */
5028 kArmv8InstrUmovInsSz_U64 = 3 /**< 64-bit (only valid when the destination is a 64-bit register. */
5029} ARMV8INSTRUMOVINSSZ;
5030
5031
5032/**
5033 * A64: Encodes UMOV (vector, register).
5034 *
5035 * @returns The encoded instruction.
5036 * @param iRegDst The register to put the result into.
5037 * @param iVecRegSrc The vector source register.
5038 * @param idxElem The element index.
5039 * @param enmSz Element size of the source vector register.
5040 * @param fDst64Bit Flag whether the destination register is 64-bit (true) or 32-bit (false).
5041 */
5042DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUmov(uint32_t iRegDst, uint32_t iVecRegSrc, uint8_t idxElem,
5043 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64, bool fDst64Bit = true)
5044{
5045 Assert(iRegDst < 32); Assert(iVecRegSrc < 32);
5046 Assert((fDst64Bit && enmSz == kArmv8InstrUmovInsSz_U64) || (!fDst64Bit && enmSz != kArmv8InstrUmovInsSz_U64));
5047 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5048 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5049 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5050 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5051
5052 return UINT32_C(0x0e003c00)
5053 | ((uint32_t)fDst64Bit << 30)
5054 | ((uint32_t)idxElem << (16 + enmSz + 1))
5055 | (RT_BIT_32(enmSz) << 16)
5056 | (iVecRegSrc << 5)
5057 | iRegDst;
5058}
5059
5060
5061/**
5062 * A64: Encodes INS (vector, register).
5063 *
5064 * @returns The encoded instruction.
5065 * @param iVecRegDst The vector register to put the result into.
5066 * @param iRegSrc The source register.
5067 * @param idxElem The element index for the destination.
5068 * @param enmSz Element size of the source vector register.
5069 *
5070 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5071 */
5072DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrIns(uint32_t iVecRegDst, uint32_t iRegSrc, uint8_t idxElem,
5073 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64)
5074{
5075 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5076 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5077 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5078 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5079 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5080
5081 return UINT32_C(0x4e001c00)
5082 | ((uint32_t)idxElem << (16 + enmSz + 1))
5083 | (RT_BIT_32(enmSz) << 16)
5084 | (iRegSrc << 5)
5085 | iVecRegDst;
5086}
5087
5088
5089/**
5090 * A64: Encodes DUP (vector, register).
5091 *
5092 * @returns The encoded instruction.
5093 * @param iVecRegDst The vector register to put the result into.
5094 * @param iRegSrc The source register (ZR is valid).
5095 * @param enmSz Element size of the source vector register.
5096 * @param f128Bit Flag whether the instruction operates on the whole 128-bit of the vector register (true) or
5097 * just the low 64-bit (false).
5098 *
5099 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5100 */
5101DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrDup(uint32_t iVecRegDst, uint32_t iRegSrc, ARMV8INSTRUMOVINSSZ enmSz,
5102 bool f128Bit = true)
5103{
5104 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5105 Assert( (enmSz == kArmv8InstrUmovInsSz_U8)
5106 || (enmSz == kArmv8InstrUmovInsSz_U16)
5107 || (enmSz == kArmv8InstrUmovInsSz_U32)
5108 || (enmSz == kArmv8InstrUmovInsSz_U64));
5109
5110 return UINT32_C(0x0e000c00)
5111 | ((uint32_t)f128Bit << 30)
5112 | (RT_BIT_32(enmSz) << 16)
5113 | (iRegSrc << 5)
5114 | iVecRegDst;
5115}
5116
5117
5118/** Armv8 vector compare to zero vector element size. */
5119typedef enum ARMV8INSTRVECCMPZEROSZ
5120{
5121 kArmv8InstrCmpZeroSz_S8 = 0, /**< Byte. */
5122 kArmv8InstrCmpZeroSz_S16 = 1, /**< Halfword. */
5123 kArmv8InstrCmpZeroSz_S32 = 2, /**< 32-bit. */
5124 kArmv8InstrCmpZeroSz_S64 = 3 /**< 64-bit. */
5125} ARMV8INSTRVECCMPZEROSZ;
5126
5127
5128/** Armv8 vector compare to zero vector operation. */
5129typedef enum ARMV8INSTRVECCMPZEROOP
5130{
5131 kArmv8InstrCmpZeroOp_Gt = 0, /**< Greater than. */
5132 kArmv8InstrCmpZeroOp_Ge = RT_BIT_32(29), /**< Greater than or equal to. */
5133 kArmv8InstrCmpZeroOp_Eq = RT_BIT_32(12), /**< Equal to. */
5134 kArmv8InstrCmpZeroOp_Le = RT_BIT_32(29) | RT_BIT_32(12) /**< Lower than or equal to. */
5135} ARMV8INSTRVECCMPZEROOP;
5136
5137
5138/**
5139 * A64: Encodes CMGT, CMGE, CMEQ or CMLE against zero (vector, register).
5140 *
5141 * @returns The encoded instruction.
5142 * @param iVecRegDst The vector register to put the result into.
5143 * @param iVecRegSrc The vector source register.
5144 * @param enmSz Vector element size.
5145 * @param enmOp The compare operation against to encode.
5146 */
5147DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpToZero(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECCMPZEROSZ enmSz,
5148 ARMV8INSTRVECCMPZEROOP enmOp)
5149{
5150 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5151
5152 return UINT32_C(0x5e208800)
5153 | ((uint32_t)enmSz << 22)
5154 | (RT_BIT_32(enmSz) << 16)
5155 | (iVecRegSrc << 5)
5156 | iVecRegDst
5157 | (uint32_t)enmOp;
5158}
5159
5160
5161/**
5162 * A64: Encodes CNT (vector, register).
5163 *
5164 * @returns The encoded instruction.
5165 * @param iVecRegDst The vector register to put the result into.
5166 * @param iVecRegSrc The vector source register.
5167 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5168 * or just the low 64-bit (false).
5169 */
5170DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCnt(uint32_t iVecRegDst, uint32_t iVecRegSrc, bool f128Bit = true)
5171{
5172 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5173
5174 return UINT32_C(0x0e205800)
5175 | ((uint32_t)f128Bit << 30)
5176 | (iVecRegSrc << 5)
5177 | iVecRegDst;
5178}
5179
5180
5181/** Armv8 vector unsigned sum long across vector element size. */
5182typedef enum ARMV8INSTRVECUADDLVSZ
5183{
5184 kArmv8InstrUAddLVSz_8B = 0, /**< 8 x 8-bit. */
5185 kArmv8InstrUAddLVSz_16B = RT_BIT_32(30), /**< 16 x 8-bit. */
5186 kArmv8InstrUAddLVSz_4H = 1, /**< 4 x 16-bit. */
5187 kArmv8InstrUAddLVSz_8H = RT_BIT_32(30) | 1, /**< 8 x 16-bit. */
5188 kArmv8InstrUAddLVSz_4S = RT_BIT_32(30) | 2 /**< 4 x 32-bit. */
5189} ARMV8INSTRVECUADDLVSZ;
5190
5191
5192/**
5193 * A64: Encodes UADDLV (vector, register).
5194 *
5195 * @returns The encoded instruction.
5196 * @param iVecRegDst The vector register to put the result into.
5197 * @param iVecRegSrc The vector source register.
5198 * @param enmSz Element size.
5199 */
5200DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUAddLV(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECUADDLVSZ enmSz)
5201{
5202 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5203
5204 return UINT32_C(0x2e303800)
5205 | ((uint32_t)enmSz)
5206 | (iVecRegSrc << 5)
5207 | iVecRegDst;
5208}
5209
5210
5211/** Armv8 USHR/USRA/URSRA/SSHR/SRSA/SSHR vector element size. */
5212typedef enum ARMV8INSTRUSHIFTSZ
5213{
5214 kArmv8InstrShiftSz_U8 = 8, /**< Byte. */
5215 kArmv8InstrShiftSz_U16 = 16, /**< Halfword. */
5216 kArmv8InstrShiftSz_U32 = 32, /**< 32-bit. */
5217 kArmv8InstrShiftSz_U64 = 64 /**< 64-bit. */
5218} ARMV8INSTRUSHIFTSZ;
5219
5220/**
5221 * A64: Encodes USHR/USRA/URSRA/SSHR/SRSA/SSHR (vector, register).
5222 *
5223 * @returns The encoded instruction.
5224 * @param iVecRegDst The vector register to put the result into.
5225 * @param iVecRegSrc The vector source register.
5226 * @param cShift Number of bits to shift.
5227 * @param enmSz Element size.
5228 * @param fUnsigned Flag whether this a signed or unsigned shift,
5229 * @param fRound Flag whether this is the rounding shift variant.
5230 * @param fAccum Flag whether this is the accumulate shift variant.
5231 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5232 * or just the low 64-bit (false).
5233 */
5234DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShrImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5235 bool fUnsigned = true, bool fRound = false, bool fAccum = false, bool f128Bit = true)
5236{
5237 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5238 Assert( cShift >= 1
5239 && ( (enmSz == kArmv8InstrShiftSz_U8 && cShift <= 8)
5240 || (enmSz == kArmv8InstrShiftSz_U16 && cShift <= 16)
5241 || (enmSz == kArmv8InstrShiftSz_U32 && cShift <= 32)
5242 || (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
5243
5244 return UINT32_C(0x0f000400)
5245 | ((uint32_t)f128Bit << 30)
5246 | ((uint32_t)fUnsigned << 29)
5247 | ((((uint32_t)enmSz << 1) - cShift) << 16)
5248 | ((uint32_t)fRound << 13)
5249 | ((uint32_t)fAccum << 12)
5250 | (iVecRegSrc << 5)
5251 | iVecRegDst;
5252}
5253
5254
5255/**
5256 * A64: Encodes SHL (vector, register).
5257 *
5258 * @returns The encoded instruction.
5259 * @param iVecRegDst The vector register to put the result into.
5260 * @param iVecRegSrc The vector source register.
5261 * @param cShift Number of bits to shift.
5262 * @param enmSz Element size.
5263 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5264 * or just the low 64-bit (false).
5265 */
5266DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5267 bool f128Bit = true)
5268{
5269 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5270 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5271 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5272 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
5273 || (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
5274
5275 return UINT32_C(0x0f005400)
5276 | ((uint32_t)f128Bit << 30)
5277 | (((uint32_t)enmSz | cShift) << 16)
5278 | (iVecRegSrc << 5)
5279 | iVecRegDst;
5280}
5281
5282
5283/**
5284 * A64: Encodes SHLL/SHLL2/USHLL/USHLL2 (vector, register).
5285 *
5286 * @returns The encoded instruction.
5287 * @param iVecRegDst The vector register to put the result into.
5288 * @param iVecRegSrc The vector source register.
5289 * @param cShift Number of bits to shift.
5290 * @param enmSz Element size of the source vector register, the destination vector register
5291 * element size is twice as large, kArmv8InstrShiftSz_U64 is invalid.
5292 * @param fUnsigned Flag whether this is an unsigned shift left (true, default) or signed (false).
5293 * @param fUpper Flag whether this operates on the lower half (false, default) of the source vector register
5294 * or the upper half (true).
5295 */
5296DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUShll(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5297 bool fUnsigned = true, bool fUpper = false)
5298{
5299 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5300 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5301 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5302 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32));
5303
5304 return UINT32_C(0x0f00a400)
5305 | ((uint32_t)fUpper << 30)
5306 | ((uint32_t)fUnsigned << 29)
5307 | (((uint32_t)enmSz | cShift) << 16)
5308 | (iVecRegSrc << 5)
5309 | iVecRegDst;
5310}
5311
5312
5313/** Armv8 vector arith ops element size. */
5314typedef enum ARMV8INSTRVECARITHSZ
5315{
5316 kArmv8VecInstrArithSz_8 = 0, /**< 8-bit. */
5317 kArmv8VecInstrArithSz_16 = 1, /**< 16-bit. */
5318 kArmv8VecInstrArithSz_32 = 2, /**< 32-bit. */
5319 kArmv8VecInstrArithSz_64 = 3 /**< 64-bit. */
5320} ARMV8INSTRVECARITHSZ;
5321
5322
5323/** Armv8 vector arithmetic operation. */
5324typedef enum
5325{
5326 kArmv8VecInstrArithOp_Add = RT_BIT_32(15), /**< ADD */
5327 kArmv8VecInstrArithOp_Sub = RT_BIT_32(29) | RT_BIT_32(15), /**< SUB */
5328 kArmv8VecInstrArithOp_UnsignSat_Add = RT_BIT_32(29) | RT_BIT_32(11), /**< UQADD */
5329 kArmv8VecInstrArithOp_UnsignSat_Sub = RT_BIT_32(29) | RT_BIT_32(13) | RT_BIT_32(11), /**< UQSUB */
5330 kArmv8VecInstrArithOp_SignSat_Add = RT_BIT_32(11), /**< SQADD */
5331 kArmv8VecInstrArithOp_SignSat_Sub = RT_BIT_32(13) | RT_BIT_32(11), /**< SQSUB */
5332 kArmv8VecInstrArithOp_Mul = RT_BIT_32(15) | RT_BIT_32(12) | RT_BIT_32(11) /**< MUL */
5333} ARMV8INSTRVECARITHOP;
5334
5335
5336/**
5337 * A64: Encodes an arithmetic operation (vector, register).
5338 *
5339 * @returns The encoded instruction.
5340 * @param enmOp The operation to encode.
5341 * @param iVecRegDst The vector register to put the result into.
5342 * @param iVecRegSrc1 The first vector source register.
5343 * @param iVecRegSrc2 The second vector source register.
5344 * @param enmSz Element size.
5345 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5346 * or just the low 64-bit (false).
5347 */
5348DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrArithOp(ARMV8INSTRVECARITHOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5349 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5350{
5351 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5352
5353 return UINT32_C(0x0e200400)
5354 | (uint32_t)enmOp
5355 | ((uint32_t)f128Bit << 30)
5356 | ((uint32_t)enmSz << 22)
5357 | (iVecRegSrc2 << 16)
5358 | (iVecRegSrc1 << 5)
5359 | iVecRegDst;
5360}
5361
5362
5363/** Armv8 vector compare operation. */
5364typedef enum ARMV8VECINSTRCMPOP
5365{
5366 /* U insn[15:10] */
5367 kArmv8VecInstrCmpOp_Gt = UINT32_C(0x3400), /**< Greater than (>) (signed) */
5368 kArmv8VecInstrCmpOp_Ge = UINT32_C(0x3c00), /**< Greater or equal (>=) (signed) */
5369 kArmv8VecInstrCmpOp_Hi = RT_BIT_32(29) | UINT32_C(0x3400), /**< Greater than (>) (unsigned) */
5370 kArmv8VecInstrCmpOp_Hs = RT_BIT_32(29) | UINT32_C(0x3c00), /**< Greater or equal (>=) (unsigned) */
5371 kArmv8VecInstrCmpOp_Eq = RT_BIT_32(29) | UINT32_C(0x8c00) /**< Equal (==) (unsigned) */
5372} ARMV8VECINSTRCMPOP;
5373
5374/**
5375 * A64: Encodes CMEQ/CMGE/CMGT/CMHI/CMHS (register variant) (vector, register).
5376 *
5377 * @returns The encoded instruction.
5378 * @param enmOp The operation to perform.
5379 * @param iVecRegDst The vector register to put the result into.
5380 * @param iVecRegSrc1 The first vector source register.
5381 * @param iVecRegSrc2 The second vector source register.
5382 * @param enmSz Element size.
5383 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5384 * or just the low 64-bit (false).
5385 */
5386DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmp(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5387 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5388{
5389 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5390
5391 return UINT32_C(0x0e200000)
5392 | ((uint32_t)f128Bit << 30)
5393 | ((uint32_t)enmSz << 22)
5394 | (iVecRegSrc2 << 16)
5395 | ((uint32_t)enmOp)
5396 | (iVecRegSrc1 << 5)
5397 | iVecRegDst;
5398}
5399
5400
5401/** Armv8 vector compare against zero operation. */
5402typedef enum ARMV8VECINSTRCMPZEROOP
5403{
5404 /* U insn[15:10] */
5405 kArmv8VecInstrCmpZeroOp_Gt = UINT32_C(0x8800), /**< Greater than zero (>) (signed) */
5406 kArmv8VecInstrCmpZeroOp_Eq = UINT32_C(0x9800), /**< Equal to zero (==) */
5407 kArmv8VecInstrCmpZeroOp_Lt = UINT32_C(0xa800), /**< Lower than zero (>=) (signed) */
5408 kArmv8VecInstrCmpZeroOp_Ge = RT_BIT_32(29) | UINT32_C(0x8800), /**< Greater or equal to zero (>=) (signed) */
5409 kArmv8VecInstrCmpZeroOp_Le = RT_BIT_32(29) | UINT32_C(0x9800) /**< Lower or equal to zero (<=) (signed) */
5410} ARMV8VECINSTRCMPZEROOP;
5411
5412/**
5413 * A64: Encodes CMEQ/CMGE/CMGT/CMLE/CMLT (zero variant) (vector, register).
5414 *
5415 * @returns The encoded instruction.
5416 * @param enmOp The operation to perform.
5417 * @param iVecRegDst The vector register to put the result into.
5418 * @param iVecRegSrc The first vector source register.
5419 * @param enmSz Element size.
5420 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5421 * or just the low 64-bit (false).
5422 */
5423DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpAgainstZero(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc,
5424 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5425{
5426 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5427
5428 return UINT32_C(0x0e200000)
5429 | ((uint32_t)f128Bit << 30)
5430 | ((uint32_t)enmSz << 22)
5431 | ((uint32_t)enmOp)
5432 | (iVecRegSrc << 5)
5433 | iVecRegDst;
5434}
5435
5436
5437/** Armv8 [Signed,Unsigned] Extract {Unsigned} operation. */
5438typedef enum
5439{
5440 kArmv8VecInstrQxtnOp_Sqxtn = RT_BIT_32(14), /**< SQXTN */
5441 kArmv8VecInstrQxtnOp_Sqxtun = RT_BIT_32(29) | RT_BIT_32(13), /**< SQXTUN */
5442 kArmv8VecInstrQxtnOp_Uqxtn = RT_BIT_32(29) | RT_BIT_32(14) /**< UQXTN */
5443} ARMV8INSTRVECQXTNOP;
5444
5445/**
5446 * A64: Encodes SQXTN/SQXTN2/UQXTN/UQXTN2/SQXTUN/SQXTUN2 (vector, register).
5447 *
5448 * @returns The encoded instruction.
5449 * @param enmOp The operation to perform.
5450 * @param fUpper Flag whether to write the result to the lower (false) or upper (true) half of the destinatiom register.
5451 * @param iVecRegDst The vector register to put the result into.
5452 * @param iVecRegSrc The first vector source register.
5453 * @param enmSz Element size.
5454 */
5455DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrQxtn(ARMV8INSTRVECQXTNOP enmOp, bool fUpper, uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECARITHSZ enmSz)
5456{
5457 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5458
5459 return UINT32_C(0x0e210800)
5460 | ((uint32_t)enmOp)
5461 | ((uint32_t)fUpper << 30)
5462 | ((uint32_t)enmSz << 22)
5463 | (iVecRegSrc << 5)
5464 | iVecRegDst;
5465}
5466
5467
5468/** Armv8 floating point size. */
5469typedef enum
5470{
5471 kArmv8VecInstrFpSz_2x_Single = 0, /**< 2x single precision values in the low 64-bit of the 128-bit register. */
5472 kArmv8VecInstrFpSz_4x_Single = RT_BIT_32(30), /**< 4x single precision values in the 128-bit register. */
5473 kArmv8VecInstrFpSz_2x_Double = RT_BIT_32(30) | RT_BIT_32(22) /**< 2x double precision values in the 128-bit register. */
5474} ARMV8INSTRVECFPSZ;
5475
5476
5477/** Armv8 3 operand floating point operation. */
5478typedef enum
5479{
5480 /* insn[29] insn[23] insn[15:11] */
5481 kArmv8VecInstrFpOp_Add = UINT32_C(0xd000), /**< FADD */
5482 kArmv8VecInstrFpOp_Sub = RT_BIT_32(23) | UINT32_C(0xd000), /**< FADD */
5483 kArmv8VecInstrFpOp_AddPairwise = RT_BIT_32(29) | UINT32_C(0xd000), /**< FADDP */
5484 kArmv8VecInstrFpOp_Mul = RT_BIT_32(29) | UINT32_C(0xd800), /**< FMUL */
5485 kArmv8VecInstrFpOp_Div = RT_BIT_32(29) | UINT32_C(0xf800), /**< FDIV */
5486
5487 kArmv8VecInstrFpOp_Max = UINT32_C(0xf000), /**< FMAX */
5488 kArmv8VecInstrFpOp_MaxNumber = UINT32_C(0xc000), /**< FMAXNM */
5489 kArmv8VecInstrFpOp_MaxNumberPairwise = RT_BIT_32(29) | UINT32_C(0xc000), /**< FMAXNMP */
5490 kArmv8VecInstrFpOp_MaxPairwise = RT_BIT_32(29) | UINT32_C(0xf000), /**< FMAXP */
5491
5492 kArmv8VecInstrFpOp_Min = RT_BIT_32(23) | UINT32_C(0xf000), /**< FMIN */
5493 kArmv8VecInstrFpOp_MinNumber = RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNM */
5494 kArmv8VecInstrFpOp_MinNumberPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNMP */
5495 kArmv8VecInstrFpOp_MinPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xf000), /**< FMINP */
5496
5497 kArmv8VecInstrFpOp_Fmla = UINT32_C(0xc800), /**< FMLA */
5498 kArmv8VecInstrFpOp_Fmls = RT_BIT_32(23) | UINT32_C(0xc800) /**< FMLS */
5499} ARMV8INSTRVECFPOP;
5500
5501/**
5502 * A64: Encodes a 3 operand floating point operation (vector, register).
5503 *
5504 * @returns The encoded instruction.
5505 * @param enmOp The operation to perform.
5506 * @param enmSz The size to operate on.
5507 * @param iVecRegDst The vector register to put the result into.
5508 * @param iVecRegSrc1 The first vector source register.
5509 * @param iVecRegSrc2 The second vector source register.
5510 */
5511DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrFp3Op(ARMV8INSTRVECFPOP enmOp, ARMV8INSTRVECFPSZ enmSz, uint32_t iVecRegDst,
5512 uint32_t iVecRegSrc1, uint32_t iVecRegSrc2)
5513{
5514 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5515
5516 return UINT32_C(0x0e200400)
5517 | ((uint32_t)enmOp)
5518 | ((uint32_t)enmSz)
5519 | (iVecRegSrc2 << 16)
5520 | (iVecRegSrc1 << 5)
5521 | iVecRegDst;
5522}
5523
5524
5525/** @} */
5526
5527#endif /* !dtrace && __cplusplus */
5528
5529/** @} */
5530
5531#endif /* !IPRT_INCLUDED_armv8_h */
5532
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