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source: vbox/trunk/include/iprt/armv8.h@ 108791

Last change on this file since 108791 was 108791, checked in by vboxsync, 3 weeks ago

VMM/IEM: More ARM target work. jiraref:VBP-1598
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/cdefs.h>
44# ifndef RT_IN_ASSEMBLER
45# include <iprt/types.h>
46# include <iprt/assert.h>
47# endif
48# include <iprt/assertcompile.h>
49#else
50# pragma D depends_on library vbox-types.d
51#endif
52
53/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
54 * @ingroup grp_rt
55 * @{
56 */
57
58/** @name The AArch64 general purpose register encoding.
59 * @{ */
60#define ARMV8_A64_REG_X0 0
61#define ARMV8_A64_REG_X1 1
62#define ARMV8_A64_REG_X2 2
63#define ARMV8_A64_REG_X3 3
64#define ARMV8_A64_REG_X4 4
65#define ARMV8_A64_REG_X5 5
66#define ARMV8_A64_REG_X6 6
67#define ARMV8_A64_REG_X7 7
68#define ARMV8_A64_REG_X8 8
69#define ARMV8_A64_REG_X9 9
70#define ARMV8_A64_REG_X10 10
71#define ARMV8_A64_REG_X11 11
72#define ARMV8_A64_REG_X12 12
73#define ARMV8_A64_REG_X13 13
74#define ARMV8_A64_REG_X14 14
75#define ARMV8_A64_REG_X15 15
76#define ARMV8_A64_REG_X16 16
77#define ARMV8_A64_REG_X17 17
78#define ARMV8_A64_REG_X18 18
79#define ARMV8_A64_REG_X19 19
80#define ARMV8_A64_REG_X20 20
81#define ARMV8_A64_REG_X21 21
82#define ARMV8_A64_REG_X22 22
83#define ARMV8_A64_REG_X23 23
84#define ARMV8_A64_REG_X24 24
85#define ARMV8_A64_REG_X25 25
86#define ARMV8_A64_REG_X26 26
87#define ARMV8_A64_REG_X27 27
88#define ARMV8_A64_REG_X28 28
89#define ARMV8_A64_REG_X29 29
90#define ARMV8_A64_REG_X30 30
91/** @} */
92
93/** @name The AArch64 32-bit general purpose register names.
94 * @{ */
95#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
96#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
97#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
98#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
99#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
100#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
101#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
102#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
103#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
104#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
105#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
106#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
107#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
108#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
109#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
110#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
111#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
112#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
113#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
114#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
115#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
116#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
117#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
118#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
119#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
120#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
121#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
122#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
123#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
124#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
125#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
126/** @} */
127
128/** @name The AArch64 NEON scalar register encoding.
129 * @{ */
130#define ARMV8_A64_REG_Q0 0
131#define ARMV8_A64_REG_Q1 1
132#define ARMV8_A64_REG_Q2 2
133#define ARMV8_A64_REG_Q3 3
134#define ARMV8_A64_REG_Q4 4
135#define ARMV8_A64_REG_Q5 5
136#define ARMV8_A64_REG_Q6 6
137#define ARMV8_A64_REG_Q7 7
138#define ARMV8_A64_REG_Q8 8
139#define ARMV8_A64_REG_Q9 9
140#define ARMV8_A64_REG_Q10 10
141#define ARMV8_A64_REG_Q11 11
142#define ARMV8_A64_REG_Q12 12
143#define ARMV8_A64_REG_Q13 13
144#define ARMV8_A64_REG_Q14 14
145#define ARMV8_A64_REG_Q15 15
146#define ARMV8_A64_REG_Q16 16
147#define ARMV8_A64_REG_Q17 17
148#define ARMV8_A64_REG_Q18 18
149#define ARMV8_A64_REG_Q19 19
150#define ARMV8_A64_REG_Q20 20
151#define ARMV8_A64_REG_Q21 21
152#define ARMV8_A64_REG_Q22 22
153#define ARMV8_A64_REG_Q23 23
154#define ARMV8_A64_REG_Q24 24
155#define ARMV8_A64_REG_Q25 25
156#define ARMV8_A64_REG_Q26 26
157#define ARMV8_A64_REG_Q27 27
158#define ARMV8_A64_REG_Q28 28
159#define ARMV8_A64_REG_Q29 29
160#define ARMV8_A64_REG_Q30 30
161#define ARMV8_A64_REG_Q31 31
162/** @} */
163
164/** @name The AArch64 NEON vector register encoding.
165 * @{ */
166#define ARMV8_A64_REG_V0 ARMV8_A64_REG_Q0
167#define ARMV8_A64_REG_V1 ARMV8_A64_REG_Q1
168#define ARMV8_A64_REG_V2 ARMV8_A64_REG_Q2
169#define ARMV8_A64_REG_V3 ARMV8_A64_REG_Q3
170#define ARMV8_A64_REG_V4 ARMV8_A64_REG_Q4
171#define ARMV8_A64_REG_V5 ARMV8_A64_REG_Q5
172#define ARMV8_A64_REG_V6 ARMV8_A64_REG_Q6
173#define ARMV8_A64_REG_V7 ARMV8_A64_REG_Q7
174#define ARMV8_A64_REG_V8 ARMV8_A64_REG_Q8
175#define ARMV8_A64_REG_V9 ARMV8_A64_REG_Q9
176#define ARMV8_A64_REG_V10 ARMV8_A64_REG_Q10
177#define ARMV8_A64_REG_V11 ARMV8_A64_REG_Q11
178#define ARMV8_A64_REG_V12 ARMV8_A64_REG_Q12
179#define ARMV8_A64_REG_V13 ARMV8_A64_REG_Q13
180#define ARMV8_A64_REG_V14 ARMV8_A64_REG_Q14
181#define ARMV8_A64_REG_V15 ARMV8_A64_REG_Q15
182#define ARMV8_A64_REG_V16 ARMV8_A64_REG_Q16
183#define ARMV8_A64_REG_V17 ARMV8_A64_REG_Q17
184#define ARMV8_A64_REG_V18 ARMV8_A64_REG_Q18
185#define ARMV8_A64_REG_V19 ARMV8_A64_REG_Q19
186#define ARMV8_A64_REG_V20 ARMV8_A64_REG_Q20
187#define ARMV8_A64_REG_V21 ARMV8_A64_REG_Q21
188#define ARMV8_A64_REG_V22 ARMV8_A64_REG_Q22
189#define ARMV8_A64_REG_V23 ARMV8_A64_REG_Q23
190#define ARMV8_A64_REG_V24 ARMV8_A64_REG_Q24
191#define ARMV8_A64_REG_V25 ARMV8_A64_REG_Q25
192#define ARMV8_A64_REG_V26 ARMV8_A64_REG_Q26
193#define ARMV8_A64_REG_V27 ARMV8_A64_REG_Q27
194#define ARMV8_A64_REG_V28 ARMV8_A64_REG_Q28
195#define ARMV8_A64_REG_V29 ARMV8_A64_REG_Q29
196#define ARMV8_A64_REG_V30 ARMV8_A64_REG_Q30
197#define ARMV8_A64_REG_V31 ARMV8_A64_REG_Q31
198/** @} */
199
200/** @name The AArch64 register 31.
201 * @note Register 31 typically refers to the zero register, but can also in
202 * select case (by instruction and opecode field) refer the to stack
203 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
204 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
205 * 31 will be the zero register.
206 * @{ */
207/** The stack pointer. */
208#define ARMV8_A64_REG_SP 31
209/** The zero register. Reads as zero, writes ignored. */
210#define ARMV8_A64_REG_XZR 31
211/** The zero register, the 32-bit register name. */
212#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
213/** @} */
214
215/** @name AArch64 register aliases
216 * @{ */
217/** The link register is typically mapped to x30 as that's the default pick of
218 * the RET instruction. */
219#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
220/** Frame base pointer is typically mapped to x29. */
221#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
222/** @} */
223
224
225/** @name System register encoding.
226 * @{
227 */
228/** Mask for the op0 part of an MSR/MRS instruction */
229#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
230/** Shift for the op0 part of an MSR/MRS instruction */
231#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
232/** Returns the op0 part of the given MRS/MSR instruction. */
233#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
234/** Mask for the op1 part of an MSR/MRS instruction */
235#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
236/** Shift for the op1 part of an MSR/MRS instruction */
237#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
238/** Returns the op1 part of the given MRS/MSR instruction. */
239#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
240/** Mask for the CRn part of an MSR/MRS instruction */
241#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
242 | RT_BIT_32(15) )
243/** Shift for the CRn part of an MSR/MRS instruction */
244#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
245/** Returns the CRn part of the given MRS/MSR instruction. */
246#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
247/** Mask for the CRm part of an MSR/MRS instruction */
248#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
249 | RT_BIT_32(11) )
250/** Shift for the CRm part of an MSR/MRS instruction */
251#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
252/** Returns the CRn part of the given MRS/MSR instruction. */
253#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
254/** Mask for the op2 part of an MSR/MRS instruction */
255#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
256/** Shift for the op2 part of an MSR/MRS instruction */
257#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
258/** Returns the op2 part of the given MRS/MSR instruction. */
259#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
260/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
261#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
262 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
263 | ARMV8_AARCH64_SYSREG_OP2_MASK)
264/** @} */
265
266/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
267 * IPRT specific and not part of the ARMv8 specification.
268 * @{ */
269#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
270 (uint16_t)( (((a_Op0) & 0x3) << 14) \
271 | (((a_Op1) & 0x7) << 11) \
272 | (((a_CRn) & 0xf) << 7) \
273 | (((a_CRm) & 0xf) << 3) \
274 | ((a_Op2) & 0x7))
275/** Returns the internal system register ID from the given MRS/MSR instruction. */
276#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
277 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
278 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
279 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
280 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
281 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
282/** Encodes the given system register ID in the given MSR/MRS instruction. */
283#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
284 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
285/** @} */
286
287
288/** @name System register IDs.
289 * @{ */
290/** OSDTRRX_EL1 register - RW. */
291#define ARMV8_AARCH64_SYSREG_OSDTRRX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 0, 2)
292/** MDSCR_EL1 - RW. */
293#define ARMV8_AARCH64_SYSREG_MDSCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 2)
294/** DBGBVR<0..15>_EL1 register - RW. */
295#define ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 4)
296/** DBGBCR<0..15>_EL1 register - RW. */
297#define ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 5)
298/** DBGWVR<0..15>_EL1 register - RW. */
299#define ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 6)
300/** DBGWCR<0..15>_EL1 register - RW. */
301#define ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 7)
302/** MDCCINT_EL1 register - RW. */
303#define ARMV8_AARCH64_SYSREG_MDCCINT_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 0)
304/** OSDTRTX_EL1 register - RW. */
305#define ARMV8_AARCH64_SYSREG_OSDTRTX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 3, 2)
306/** OSECCR_EL1 register - RW. */
307#define ARMV8_AARCH64_SYSREG_OSECCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 6, 2)
308/** MDRAR_EL1 register - RO. */
309#define ARMV8_AARCH64_SYSREG_MDRAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 0)
310/** OSLAR_EL1 register - WO. */
311#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
312/** OSLSR_EL1 register - RO. */
313#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
314/** OSDLR_EL1 register - RW. */
315#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
316
317/** MIDR_EL1 register - RO. */
318#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
319/** MIPDR_EL1 register - RO. */
320#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
321/** REVIDR_EL1 register - RO. */
322#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
323/** ID_PFR0_EL1 register - RO. */
324#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
325/** ID_PFR1_EL1 register - RO. */
326#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
327/** ID_DFR0_EL1 register - RO. */
328#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
329/** ID_AFR0_EL1 register - RO. */
330#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
331/** ID_MMFR0_EL1 register - RO. */
332#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
333/** ID_MMFR1_EL1 register - RO. */
334#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
335/** ID_MMFR2_EL1 register - RO. */
336#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
337/** ID_MMFR3_EL1 register - RO. */
338#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
339
340/** ID_ISAR0_EL1 register - RO. */
341#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
342/** ID_ISAR1_EL1 register - RO. */
343#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
344/** ID_ISAR2_EL1 register - RO. */
345#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
346/** ID_ISAR3_EL1 register - RO. */
347#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
348/** ID_ISAR4_EL1 register - RO. */
349#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
350/** ID_ISAR5_EL1 register - RO. */
351#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
352/** ID_MMFR4_EL1 register - RO. */
353#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
354/** ID_ISAR6_EL1 register - RO. */
355#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
356
357/** MVFR0_EL1 register - RO. */
358#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
359/** MVFR1_EL1 register - RO. */
360#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
361/** MVFR2_EL1 register - RO. */
362#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
363/** ID_PFR2_EL1 register - RO. */
364#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
365/** ID_DFR1_EL1 register - RO. */
366#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
367/** ID_MMFR5_EL1 register - RO. */
368#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
369
370/** ID_AA64PFR0_EL1 register - RO. */
371#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
372/** ID_AA64PFR0_EL1 register - RO. */
373#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
374/** ID_AA64ZFR0_EL1 register - RO. */
375#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
376/** ID_AA64SMFR0_EL1 register - RO. */
377#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
378
379/** ID_AA64DFR0_EL1 register - RO. */
380#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
381/** ID_AA64DFR0_EL1 register - RO. */
382#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
383/** ID_AA64AFR0_EL1 register - RO. */
384#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
385/** ID_AA64AFR1_EL1 register - RO. */
386#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
387
388/** ID_AA64ISAR0_EL1 register - RO. */
389#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
390/** ID_AA64ISAR1_EL1 register - RO. */
391#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
392/** ID_AA64ISAR2_EL1 register - RO. */
393#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
394
395/** ID_AA64MMFR0_EL1 register - RO. */
396#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
397/** ID_AA64MMFR1_EL1 register - RO. */
398#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
399/** ID_AA64MMFR2_EL1 register - RO. */
400#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
401
402/** SCTRL_EL1 register - RW. */
403#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
404/** ACTRL_EL1 register - RW. */
405#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
406/** CPACR_EL1 register - RW. */
407#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
408/** RGSR_EL1 register - RW. */
409#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
410/** GCR_EL1 register - RW. */
411#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
412
413/** ZCR_EL1 register - RW. */
414#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
415/** TRFCR_EL1 register - RW. */
416#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
417/** SMPRI_EL1 register - RW. */
418#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
419/** SMCR_EL1 register - RW. */
420#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
421
422/** TTBR0_EL1 register - RW. */
423#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
424/** TTBR1_EL1 register - RW. */
425#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
426/** TCR_EL1 register - RW. */
427#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
428
429/** APIAKeyLo_EL1 register - RW. */
430#define ARMV8_AARCH64_SYSREG_APIAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 0)
431/** APIAKeyHi_EL1 register - RW. */
432#define ARMV8_AARCH64_SYSREG_APIAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 1)
433/** APIBKeyLo_EL1 register - RW. */
434#define ARMV8_AARCH64_SYSREG_APIBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 2)
435/** APIBKeyHi_EL1 register - RW. */
436#define ARMV8_AARCH64_SYSREG_APIBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 3)
437
438/** APDAKeyLo_EL1 register - RW. */
439#define ARMV8_AARCH64_SYSREG_APDAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 0)
440/** APDAKeyHi_EL1 register - RW. */
441#define ARMV8_AARCH64_SYSREG_APDAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 1)
442/** APDBKeyLo_EL1 register - RW. */
443#define ARMV8_AARCH64_SYSREG_APDBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 2)
444/** APDBKeyHi_EL1 register - RW. */
445#define ARMV8_AARCH64_SYSREG_APDBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 3)
446
447/** APGAKeyLo_EL1 register - RW. */
448#define ARMV8_AARCH64_SYSREG_APGAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 0)
449/** APGAKeyHi_EL1 register - RW. */
450#define ARMV8_AARCH64_SYSREG_APGAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 1)
451
452/** SPSR_EL1 register - RW. */
453#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
454/** ELR_EL1 register - RW. */
455#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
456
457/** SP_EL0 register - RW. */
458#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
459
460/** PSTATE.SPSel value. */
461#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
462/** PSTATE.CurrentEL value. */
463#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
464/** PSTATE.PAN value. */
465#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
466/** PSTATE.UAO value. */
467#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
468
469/** PSTATE.ALLINT value. */
470#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
471
472/** ICC_PMR_EL1 register - RW. */
473#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
474
475/** AFSR0_EL1 register - RW. */
476#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
477/** AFSR1_EL1 register - RW. */
478#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
479
480/** ESR_EL1 register - RW. */
481#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
482
483/** ERRIDR_EL1 register - RO. */
484#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
485/** ERRSELR_EL1 register - RW. */
486#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
487
488/** FAR_EL1 register - RW. */
489#define ARMV8_AARCH64_SYSREG_FAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 6, 0, 0)
490
491/** PAR_EL1 register - RW. */
492#define ARMV8_AARCH64_SYSREG_PAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 7, 4, 0)
493
494/** PMINTENCLR_EL1 register - RW. */
495#define ARMV8_AARCH64_SYSREG_PMINTENCLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 9, 14, 2)
496
497/** MAIR_EL1 register - RW. */
498#define ARMV8_AARCH64_SYSREG_MAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 2, 0)
499
500/** AMAIR_EL1 register - RW. */
501#define ARMV8_AARCH64_SYSREG_AMAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 3, 0)
502
503/** VBAR_EL1 register - RW. */
504#define ARMV8_AARCH64_SYSREG_VBAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 0, 0)
505
506/** ICC_IAR0_EL1 register - RO. */
507#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
508/** ICC_EOIR0_EL1 register - WO. */
509#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
510/** ICC_HPPIR0_EL1 register - WO. */
511#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
512/** ICC_BPR0_EL1 register - RW. */
513#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
514/** ICC_AP0R0_EL1 register - RW. */
515#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
516/** ICC_AP0R1_EL1 register - RW. */
517#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
518/** ICC_AP0R2_EL1 register - RW. */
519#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
520/** ICC_AP0R3_EL1 register - RW. */
521#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
522
523/** ICC_AP1R0_EL1 register - RW. */
524#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
525/** ICC_AP1R1_EL1 register - RW. */
526#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
527/** ICC_AP1R2_EL1 register - RW. */
528#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
529/** ICC_AP1R3_EL1 register - RW. */
530#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
531/** ICC_NMIAR1_EL1 register - RO. */
532#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
533
534/** ICC_DIR_EL1 register - WO. */
535#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
536/** ICC_RPR_EL1 register - RO. */
537#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
538/** ICC_SGI1R_EL1 register - WO. */
539#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
540/** ICC_ASGI1R_EL1 register - WO. */
541#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
542/** ICC_SGI0R_EL1 register - WO. */
543#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
544
545/** ICC_IAR1_EL1 register - RO. */
546#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
547/** ICC_EOIR1_EL1 register - WO. */
548#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
549/** ICC_HPPIR1_EL1 register - RO. */
550#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
551/** ICC_BPR1_EL1 register - RW. */
552#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
553/** ICC_CTLR_EL1 register - RW. */
554#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
555/** ICC_SRE_EL1 register - RW. */
556#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
557/** ICC_IGRPEN0_EL1 register - RW. */
558#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
559/** ICC_IGRPEN1_EL1 register - RW. */
560#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
561
562/** CONTEXTIDR_EL1 register - RW. */
563#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 1)
564/** TPIDR_EL1 register - RW. */
565#define ARMV8_AARCH64_SYSREG_TPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 4)
566
567/** CNTKCTL_EL1 register - RW. */
568#define ARMV8_AARCH64_SYSREG_CNTKCTL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 14, 1, 0)
569
570/** CSSELR_EL1 register - RW. */
571#define ARMV8_AARCH64_SYSREG_CSSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 2, 0, 0, 0)
572
573/** CTR_EL0 - Cache Type Register - RO. */
574#define ARMV8_AARCH64_SYSREG_CTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 0, 0, 1)
575/** DCZID_EL0 - Data Cache Zero ID Register - RO. */
576#define ARMV8_AARCH64_SYSREG_DCZID_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 0, 0, 7)
577
578
579/** NZCV - Status Flags - ??. */
580#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
581/** DAIF - Interrupt Mask Bits - ??. */
582#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
583/** SVCR - Streaming Vector Control Register - ??. */
584#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
585/** DIT - Data Independent Timing - ??. */
586#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
587/** SSBS - Speculative Store Bypass Safe - ??. */
588#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
589/** TCO - Tag Check Override - ??. */
590#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
591
592/** FPCR register - RW. */
593#define ARMV8_AARCH64_SYSREG_FPCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 0)
594/** FPSR register - RW. */
595#define ARMV8_AARCH64_SYSREG_FPSR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 1)
596
597/** PMCR_EL0 register - RW. */
598#define ARMV8_AARCH64_SYSREG_PMCR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 0)
599/** PMCNTENSET_EL0 register - RW. */
600#define ARMV8_AARCH64_SYSREG_PMCNTENSET_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 1)
601/** PMCNTENCLR_EL0 register - RW. */
602#define ARMV8_AARCH64_SYSREG_PMCNTENCLR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 2)
603/** PMOVSCLR_EL0 register - RW. */
604#define ARMV8_AARCH64_SYSREG_PMOVSCLR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 3)
605
606/** PMCCNTR_EL0 register - RW. */
607#define ARMV8_AARCH64_SYSREG_PMCCNTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 13, 0)
608
609/** PMUSERENR_EL0 register - RW. */
610#define ARMV8_AARCH64_SYSREG_PMUSERENR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 14, 0)
611
612/** PMCCFILTR_EL0 register - RW. */
613#define ARMV8_AARCH64_SYSREG_PMCCFILTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 15, 7)
614
615/** ICC_SRE_EL2 register - RW. */
616#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 9, 5)
617
618/** TPIDR_EL0 register - RW. */
619#define ARMV8_AARCH64_SYSREG_TPIDR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 2)
620/** TPIDRRO_EL0 register - RO. */
621#define ARMV8_AARCH64_SYSREG_TPIDRRO_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 3)
622
623/** CNTFRQ_EL0 register - RW. */
624#define ARMV8_AARCH64_SYSREG_CNTFRQ_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 0)
625/** CNTVCT_EL0 register - RW. */
626#define ARMV8_AARCH64_SYSREG_CNTVCT_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 2)
627
628/** CNTP_TVAL_EL0 register - RW. */
629#define ARMV8_AARCH64_SYSREG_CNTP_TVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 0)
630/** CNTP_CTL_EL0 register - RW. */
631#define ARMV8_AARCH64_SYSREG_CNTP_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 1)
632/** CNTP_CVAL_EL0 register - RW. */
633#define ARMV8_AARCH64_SYSREG_CNTP_CVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 2)
634
635/** CNTV_CTL_EL0 register - RW. */
636#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
637
638/** VPIDR_EL2 register - RW. */
639#define ARMV8_AARCH64_SYSREG_VPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 0)
640/** VMPIDR_EL2 register - RW. */
641#define ARMV8_AARCH64_SYSREG_VMPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 5)
642
643/** SCTLR_EL2 register - RW. */
644#define ARMV8_AARCH64_SYSREG_SCTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 0)
645/** ACTLR_EL2 register - RW. */
646#define ARMV8_AARCH64_SYSREG_ACTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 1)
647
648/** HCR_EL2 register - RW. */
649#define ARMV8_AARCH64_SYSREG_HCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 0)
650/** MDCR_EL2 register - RW. */
651#define ARMV8_AARCH64_SYSREG_MDCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 1)
652/** CPTR_EL2 register - RW. */
653#define ARMV8_AARCH64_SYSREG_CPTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 2)
654/** HSTR_EL2 register - RW. */
655#define ARMV8_AARCH64_SYSREG_HSTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 3)
656/** HFGRTR_EL2 register - RW. */
657#define ARMV8_AARCH64_SYSREG_HFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 4)
658/** HFGWTR_EL2 register - RW. */
659#define ARMV8_AARCH64_SYSREG_HFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 5)
660/** HFGITR_EL2 register - RW. */
661#define ARMV8_AARCH64_SYSREG_HFGITR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 6)
662/** HACR_EL2 register - RW. */
663#define ARMV8_AARCH64_SYSREG_HACR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 7)
664
665/** ZCR_EL2 register - RW. */
666#define ARMV8_AARCH64_SYSREG_ZCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 0)
667/** TRFCR_EL2 register - RW. */
668#define ARMV8_AARCH64_SYSREG_TRFCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 1)
669/** HCRX_EL2 register - RW. */
670#define ARMV8_AARCH64_SYSREG_HCRX_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 2)
671
672/** SDER32_EL2 register - RW. */
673#define ARMV8_AARCH64_SYSREG_SDER32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 3, 0)
674
675/** TTBR0_EL2 register - RW. */
676#define ARMV8_AARCH64_SYSREG_TTBR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 0)
677/** TTBR1_EL2 register - RW. */
678#define ARMV8_AARCH64_SYSREG_TTBR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 1)
679/** TCR_EL2 register - RW. */
680#define ARMV8_AARCH64_SYSREG_TCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 2)
681
682/** VTTBR_EL2 register - RW. */
683#define ARMV8_AARCH64_SYSREG_VTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 0)
684/** VTCR_EL2 register - RW. */
685#define ARMV8_AARCH64_SYSREG_VTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 2)
686
687/** VNCR_EL2 register - RW. */
688#define ARMV8_AARCH64_SYSREG_VNCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 2, 0)
689
690/** VSTTBR_EL2 register - RW. */
691#define ARMV8_AARCH64_SYSREG_VSTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 0)
692/** VSTCR_EL2 register - RW. */
693#define ARMV8_AARCH64_SYSREG_VSTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 2)
694
695/** DACR32_EL2 register - RW. */
696#define ARMV8_AARCH64_SYSREG_DACR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 0, 0)
697
698/** HDFGRTR_EL2 register - RW. */
699#define ARMV8_AARCH64_SYSREG_HDFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 4)
700/** HDFGWTR_EL2 register - RW. */
701#define ARMV8_AARCH64_SYSREG_HDFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 5)
702/** HAFGRTR_EL2 register - RW. */
703#define ARMV8_AARCH64_SYSREG_HAFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 6)
704
705/** SPSR_EL2 register - RW. */
706#define ARMV8_AARCH64_SYSREG_SPSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 0)
707/** ELR_EL2 register - RW. */
708#define ARMV8_AARCH64_SYSREG_ELR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 1)
709
710/** SP_EL1 register - RW. */
711#define ARMV8_AARCH64_SYSREG_SP_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 1, 0)
712
713/** IFSR32_EL2 register - RW. */
714#define ARMV8_AARCH64_SYSREG_IFSR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 0, 1)
715
716/** AFSR0_EL2 register - RW. */
717#define ARMV8_AARCH64_SYSREG_AFSR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 0)
718/** AFSR1_EL2 register - RW. */
719#define ARMV8_AARCH64_SYSREG_AFSR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 1)
720
721/** ESR_EL2 register - RW. */
722#define ARMV8_AARCH64_SYSREG_ESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 0)
723/** VSESR_EL2 register - RW. */
724#define ARMV8_AARCH64_SYSREG_VSESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 3)
725
726/** FPEXC32_EL2 register - RW. */
727#define ARMV8_AARCH64_SYSREG_FPEXC32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 3, 0)
728
729/** TFSR_EL2 register - RW. */
730#define ARMV8_AARCH64_SYSREG_TFSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 6, 0)
731
732/** FAR_EL2 register - RW. */
733#define ARMV8_AARCH64_SYSREG_FAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 0)
734/** HPFAR_EL2 register - RW. */
735#define ARMV8_AARCH64_SYSREG_HPFAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 4)
736
737/** PMSCR_EL2 register - RW. */
738#define ARMV8_AARCH64_SYSREG_PMSCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 9, 9, 0)
739
740/** MAIR_EL2 register - RW. */
741#define ARMV8_AARCH64_SYSREG_MAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 2, 0)
742
743/** AMAIR_EL2 register - RW. */
744#define ARMV8_AARCH64_SYSREG_AMAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 3, 0)
745
746/** MPAMHCR_EL2 register - RW. */
747#define ARMV8_AARCH64_SYSREG_MPAMHCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 0)
748/** MPAMVPMV_EL2 register - RW. */
749#define ARMV8_AARCH64_SYSREG_MPAMVPMV_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 1)
750
751/** MPAM2_EL2 register - RW. */
752#define ARMV8_AARCH64_SYSREG_MPAM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 5, 0)
753
754/** MPAMVPM0_EL2 register - RW. */
755#define ARMV8_AARCH64_SYSREG_MPAMVPM0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 0)
756/** MPAMVPM1_EL2 register - RW. */
757#define ARMV8_AARCH64_SYSREG_MPAMVPM1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 1)
758/** MPAMVPM2_EL2 register - RW. */
759#define ARMV8_AARCH64_SYSREG_MPAMVPM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 2)
760/** MPAMVPM3_EL2 register - RW. */
761#define ARMV8_AARCH64_SYSREG_MPAMVPM3_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 3)
762/** MPAMVPM4_EL2 register - RW. */
763#define ARMV8_AARCH64_SYSREG_MPAMVPM4_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 4)
764/** MPAMVPM5_EL2 register - RW. */
765#define ARMV8_AARCH64_SYSREG_MPAMVPM5_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 5)
766/** MPAMVPM6_EL2 register - RW. */
767#define ARMV8_AARCH64_SYSREG_MPAMVPM6_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 6)
768/** MPAMVPM7_EL2 register - RW. */
769#define ARMV8_AARCH64_SYSREG_MPAMVPM7_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 7)
770
771/** VBAR_EL2 register - RW. */
772#define ARMV8_AARCH64_SYSREG_VBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 0)
773/** RVBAR_EL2 register - RW. */
774#define ARMV8_AARCH64_SYSREG_RVBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 1)
775/** RMR_EL2 register - RW. */
776#define ARMV8_AARCH64_SYSREG_RMR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 2)
777
778/** VDISR_EL2 register - RW. */
779#define ARMV8_AARCH64_SYSREG_VDISR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 1, 1)
780
781/** CONTEXTIDR_EL2 register - RW. */
782#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 1)
783/** TPIDR_EL2 register - RW. */
784#define ARMV8_AARCH64_SYSREG_TPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 2)
785/** SCXTNUM_EL2 register - RW. */
786#define ARMV8_AARCH64_SYSREG_SCXTNUM_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 7)
787
788/** CNTVOFF_EL2 register - RW. */
789#define ARMV8_AARCH64_SYSREG_CNTVOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 3)
790/** CNTPOFF_EL2 register - RW. */
791#define ARMV8_AARCH64_SYSREG_CNTPOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 6)
792
793/** CNTHCTL_EL2 register - RW. */
794#define ARMV8_AARCH64_SYSREG_CNTHCTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 1, 0)
795
796/** CNTHP_TVAL_EL2 register - RW. */
797#define ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 0)
798/** CNTHP_CTL_EL2 register - RW. */
799#define ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 1)
800/** CNTHP_CVAL_EL2 register - RW. */
801#define ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 2)
802
803/** CNTHV_TVAL_EL2 register - RW. */
804#define ARMV8_AARCH64_SYSREG_CNTHV_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 0)
805/** CNTHV_CTL_EL2 register - RW. */
806#define ARMV8_AARCH64_SYSREG_CNTHV_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 1)
807/** CNTHV_CVAL_EL2 register - RW. */
808#define ARMV8_AARCH64_SYSREG_CNTHV_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 2)
809
810/** CNTHVS_TVAL_EL2 register - RW. */
811#define ARMV8_AARCH64_SYSREG_CNTHVS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 0)
812/** CNTHVS_CTL_EL2 register - RW. */
813#define ARMV8_AARCH64_SYSREG_CNTHVS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 1)
814/** CNTHVS_CVAL_EL2 register - RW. */
815#define ARMV8_AARCH64_SYSREG_CNTHVS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 2)
816
817/** CNTHPS_TVAL_EL2 register - RW. */
818#define ARMV8_AARCH64_SYSREG_CNTHPS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 0)
819/** CNTHPS_CTL_EL2 register - RW. */
820#define ARMV8_AARCH64_SYSREG_CNTHPS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 1)
821/** CNTHPS_CVAL_EL2 register - RW. */
822#define ARMV8_AARCH64_SYSREG_CNTHPS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 2)
823
824/** SP_EL2 register - RW. */
825#define ARMV8_AARCH64_SYSREG_SP_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 6, 4, 1, 0)
826
827/** SP_EL2 register - RW. */
828#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL3 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 6, 12, 12, 5)
829/** @} */
830
831
832#ifndef RT_IN_ASSEMBLER
833/**
834 * SPSR_EL2 (according to chapter C5.2.19)
835 */
836typedef union ARMV8SPSREL2
837{
838 /** The plain unsigned view. */
839 uint64_t u;
840 /** The 8-bit view. */
841 uint8_t au8[8];
842 /** The 16-bit view. */
843 uint16_t au16[4];
844 /** The 32-bit view. */
845 uint32_t au32[2];
846 /** The 64-bit view. */
847 uint64_t u64;
848} ARMV8SPSREL2;
849/** Pointer to SPSR_EL2. */
850typedef ARMV8SPSREL2 *PARMV8SPSREL2;
851/** Pointer to const SPSR_EL2. */
852typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
853#endif /* !RT_IN_ASSEMBLER */
854
855
856/** @name SPSR_EL2 (When exception is taken from AArch64 state)
857 * @{
858 */
859/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
860#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
861#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
862/** Bit 0 - SP - Selected stack pointer. */
863#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
864#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
865/** Bit 1 - Reserved (read as zero). */
866#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
867/** Bit 2 - 3 - EL - Exception level. */
868#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
869#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
870#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
871#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
872/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
873#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
874#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
875/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
876#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
877#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
878/** Bit 6 - I - FIQ interrupt mask. */
879#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
880#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
881/** Bit 7 - I - IRQ interrupt mask. */
882#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
883#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
884/** Bit 8 - A - SError interrupt mask. */
885#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
886#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
887/** Bit 9 - D - Debug Exception mask. */
888#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
889#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
890/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
891#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
892#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
893#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
894/** Bit 12 - SSBS - Speculative Store Bypass. */
895#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
896#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
897/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
898#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
899#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
900/** Bit 14 - 19 - Reserved (read as zero). */
901#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
902 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
903/** Bit 20 - IL - Illegal Execution State flag. */
904#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
905#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
906/** Bit 21 - SS - Software Step flag. */
907#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
908#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
909/** Bit 22 - PAN - Privileged Access Never flag. */
910#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
911#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
912/** Bit 23 - UAO - User Access Override flag. */
913#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
914#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
915/** Bit 24 - DIT - Data Independent Timing flag. */
916#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
917#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
918/** Bit 25 - TCO - Tag Check Override flag. */
919#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
920#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
921/** Bit 26 - 27 - Reserved (read as zero). */
922#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
923/** Bit 28 - V - Overflow condition flag. */
924#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
925#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
926/** Bit 29 - C - Carry condition flag. */
927#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
928#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
929/** Bit 30 - Z - Zero condition flag. */
930#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
931#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
932/** Bit 31 - N - Negative condition flag. */
933#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
934#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
935/** Bit 32 - 63 - Reserved (read as zero). */
936#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
937/** Checks whether the given SPSR value contains a AARCH64 execution state. */
938#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
939/** @} */
940
941/** @name Aarch64 Exception levels
942 * @{ */
943/** Exception Level 0 - User mode. */
944#define ARMV8_AARCH64_EL_0 0
945/** Exception Level 1 - Supervisor mode. */
946#define ARMV8_AARCH64_EL_1 1
947/** Exception Level 2 - Hypervisor mode. */
948#define ARMV8_AARCH64_EL_2 2
949/** @} */
950
951
952/** @name ESR_EL2 (Exception Syndrome Register, EL2)
953 * @{
954 */
955/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
956#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
957#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
958/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
959#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
960#define ARMV8_ESR_EL2_IL_BIT 25
961#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
962#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
963/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
964#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
965 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
966#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
967/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
968#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
969 | RT_BIT_64(35) | RT_BIT_64(36))
970#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
971/** @} */
972
973
974/** @name ESR_EL2 Exception Classes (EC)
975 * @{ */
976/** Unknown exception reason. */
977#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
978/** Trapped WF* instruction. */
979#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
980/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
981#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
982/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
983#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
984/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
985#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
986/** AArch32 - Trapped LDC or STC access. */
987#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
988/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
989#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
990/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
991#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
992/** AArch32 - Trapped pointer authentication instruction. */
993#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
994/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
995#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
996/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
997#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
998/** FEAT_BTI - Branch Target Exception. */
999#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
1000/** Illegal Execution State. */
1001#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
1002/** AArch32 - SVC instruction execution. */
1003#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
1004/** AArch32 - HVC instruction execution. */
1005#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
1006/** AArch32 - SMC instruction execution. */
1007#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
1008/** AArch64 - SVC instruction execution. */
1009#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
1010/** AArch64 - HVC instruction execution. */
1011#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
1012/** AArch64 - SMC instruction execution. */
1013#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
1014/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
1015#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
1016/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
1017#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
1018/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
1019#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
1020/** FEAT_TME - Exception from TSTART instruction. */
1021#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
1022/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
1023#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
1024/** FEAT_SME - Access to SME functionality trapped. */
1025#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
1026/** FEAT_RME - Exception from Granule Protection Check. */
1027#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
1028/** Instruction Abort from a lower Exception level. */
1029#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
1030/** Instruction Abort from the same Exception level. */
1031#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
1032/** PC alignment fault exception. */
1033#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
1034/** Data Abort from a lower Exception level. */
1035#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
1036/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
1037#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
1038/** SP alignment fault exception. */
1039#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
1040/** FEAT_MOPS - Memory Operation Exception. */
1041#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
1042/** AArch32 - Trapped floating point exception. */
1043#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
1044/** AArch64 - Trapped floating point exception. */
1045#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
1046/** SError interrupt. */
1047#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
1048/** Breakpoint Exception from a lower Exception level. */
1049#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
1050/** Breakpoint Exception from the same Exception level. */
1051#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
1052/** Software Step Exception from a lower Exception level. */
1053#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
1054/** Software Step Exception from the same Exception level. */
1055#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
1056/** Watchpoint Exception from a lower Exception level. */
1057#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
1058/** Watchpoint Exception from the same Exception level. */
1059#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
1060/** AArch32 - BKPT instruction execution. */
1061#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
1062/** AArch32 - Vector Catch exception. */
1063#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
1064/** AArch64 - BRK instruction execution. */
1065#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
1066/** @} */
1067
1068
1069/** @name ISS encoding for Data Abort exceptions.
1070 * @{ */
1071/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
1072#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
1073 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
1074#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
1075/** Bit 6 - WnR - Write not Read. */
1076#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
1077#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
1078/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
1079#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
1080#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
1081/** Bit 8 - CM - Cache maintenance instruction. */
1082#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
1083#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
1084/** Bit 9 - EA - External abort type. */
1085#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
1086#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
1087/** Bit 10 - FnV - FAR not Valid. */
1088#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
1089#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
1090/** Bit 11 - 12 - LST - Load/Store Type. */
1091#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
1092#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
1093/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
1094#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
1095#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
1096/** Bit 14 - AR - Acquire/Release semantics. */
1097#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
1098#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
1099/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
1100#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
1101#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
1102/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
1103#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
1104 | RT_BIT_32(19) | RT_BIT_32(20))
1105#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
1106/** Bit 21 - SSE - Syndrome Sign Extend. */
1107#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
1108#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
1109/** Bit 22 - 23 - SAS - Syndrome Access Size. */
1110#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
1111#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
1112/** Bit 24 - ISV - Instruction Syndrome Valid. */
1113#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
1114#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
1115/** @} */
1116
1117
1118/** @name Data Fault Status Code (DFSC).
1119 * @{ */
1120/** Address size fault, level 0 of translation or translation table base register. */
1121#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
1122/** Address size fault, level 1. */
1123#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
1124/** Address size fault, level 2. */
1125#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
1126/** Address size fault, level 3. */
1127#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
1128/** Translation fault, level 0. */
1129#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
1130/** Translation fault, level 1. */
1131#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
1132/** Translation fault, level 2. */
1133#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
1134/** Translation fault, level 3. */
1135#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
1136/** FEAT_LPA2 - Access flag fault, level 0. */
1137#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
1138/** Access flag fault, level 1. */
1139#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
1140/** Access flag fault, level 2. */
1141#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
1142/** Access flag fault, level 3. */
1143#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
1144/** FEAT_LPA2 - Permission fault, level 0. */
1145#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
1146/** Permission fault, level 1. */
1147#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
1148/** Permission fault, level 2. */
1149#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
1150/** Permission fault, level 3. */
1151#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
1152/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
1153#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
1154/** FEAT_MTE2 - Synchronous Tag Check Fault. */
1155#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
1156/** @todo Do the rest (lazy developer). */
1157/** @} */
1158
1159
1160/** @name SAS encoding.
1161 * @{ */
1162/** Byte access. */
1163#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
1164/** Halfword access (uint16_t). */
1165#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
1166/** Word access (uint32_t). */
1167#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
1168/** Doubleword access (uint64_t). */
1169#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
1170/** @} */
1171
1172
1173/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
1174 * @{ */
1175/** Bit 0 - Direction flag. */
1176#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
1177#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
1178/** Bit 1 - 4 - CRm value from the instruction. */
1179#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
1180 | RT_BIT_32(4))
1181#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
1182/** Bit 5 - 9 - Rt value from the instruction. */
1183#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
1184 | RT_BIT_32(8) | RT_BIT_32(9))
1185#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
1186/** Bit 10 - 13 - CRn value from the instruction. */
1187#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
1188 | RT_BIT_32(13))
1189#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
1190/** Bit 14 - 16 - Op2 value from the instruction. */
1191#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
1192#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
1193/** Bit 17 - 19 - Op2 value from the instruction. */
1194#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
1195#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
1196/** Bit 20 - 21 - Op0 value from the instruction. */
1197#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
1198#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
1199/** Bit 22 - 24 - Reserved. */
1200#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
1201/** @} */
1202
1203
1204/** @name ISS encoding for trapped HVC instruction exceptions.
1205 * @{ */
1206/** Bit 0 - 15 - imm16 value of the instruction. */
1207#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
1208#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
1209/** @} */
1210
1211
1212/** @name TCR_EL1 - Translation Control Register (EL1)
1213 * @{
1214 */
1215/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
1216#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
1217 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
1218#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
1219/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
1220#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
1221#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
1222/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1223#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
1224#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
1225/** Non cacheable. */
1226# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
1227/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1228# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
1229/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1230# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
1231/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1232# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
1233/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1234#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
1235#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
1236/** Non cacheable. */
1237# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
1238/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1239# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
1240/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1241# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
1242/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1243# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
1244/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
1245#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
1246#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
1247/** Non shareable. */
1248# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
1249/** Invalid value. */
1250# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
1251/** Outer Shareable. */
1252# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
1253/** Inner Shareable. */
1254# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
1255/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
1256#define ARMV8_TCR_EL1_AARCH64_TG0_MASK (RT_BIT_64(14) | RT_BIT_64(15))
1257#define ARMV8_TCR_EL1_AARCH64_TG0_SHIFT 14
1258#define ARMV8_TCR_EL1_AARCH64_TG0 ARMV8_TCR_EL1_AARCH64_TG0_MASK
1259#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> ARMV8_TCR_EL1_AARCH64_TG0_SHIFT)
1260/** Invalid granule size. */
1261# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
1262/** 16KiB granule size (shifted down). */
1263# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
1264/** 4KiB granule size (shifted down). */
1265# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
1266/** 64KiB granule size (shifted down). */
1267# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
1268/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
1269#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
1270 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
1271#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
1272/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
1273#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
1274#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
1275/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
1276#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
1277#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
1278/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1279#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
1280#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
1281/** Non cacheable. */
1282# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
1283/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1284# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
1285/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1286# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
1287/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1288# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
1289/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1290#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
1291#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
1292/** Non cacheable. */
1293# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
1294/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1295# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
1296/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1297# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
1298/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1299# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
1300/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
1301#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
1302#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
1303/** Non shareable. */
1304# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
1305/** Invalid value. */
1306# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
1307/** Outer Shareable. */
1308# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
1309/** Inner Shareable. */
1310# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
1311/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
1312#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
1313#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
1314/** Invalid granule size. */
1315# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
1316/** 16KiB granule size. */
1317# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
1318/** 4KiB granule size. */
1319# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
1320/** 64KiB granule size. */
1321# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
1322/** Bit 32 - 34 - Intermediate Physical Address Size. */
1323#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
1324#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
1325/** IPA - 32 bits, 4GiB. */
1326# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
1327/** IPA - 36 bits, 64GiB. */
1328# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
1329/** IPA - 40 bits, 1TiB. */
1330# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
1331/** IPA - 42 bits, 4TiB. */
1332# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
1333/** IPA - 44 bits, 16TiB. */
1334# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
1335/** IPA - 48 bits, 256TiB. */
1336# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
1337/** IPA - 52 bits, 4PiB. */
1338# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
1339/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
1340#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
1341#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
1342/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
1343#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
1344#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
1345/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
1346#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
1347#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
1348/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
1349#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
1350#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
1351/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
1352#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
1353#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
1354/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
1355#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
1356#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
1357/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
1358#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
1359#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
1360/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
1361#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
1362#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
1363/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
1364#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
1365#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
1366/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
1367#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
1368#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
1369/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
1370#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
1371#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
1372/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
1373#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
1374#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
1375/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
1376#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
1377#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
1378/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
1379#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1380#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1381/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1382#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1383#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1384/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1385#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1386#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1387/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1388#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1389#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1390/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1391#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1392#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1393/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1394#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1395#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1396/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1397#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1398#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1399/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1400#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1401#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1402/** Bit 57 - TCMA0 */
1403#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1404#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1405/** Bit 58 - TCMA1 */
1406#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1407#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1408/** Bit 59 - Data Sharing(?). */
1409#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1410#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1411/** @} */
1412
1413
1414/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1415 * @{
1416 */
1417/** Bit 0 - Common not Private (FEAT_TTCNP). */
1418#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1419#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1420/** Bit 1 - 47 - Translation table base address. */
1421#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1422#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) ((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR)
1423/** Bit 48 - 63 - ASID. */
1424#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1425#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1426/** @} */
1427
1428
1429/** @name MDSCR_EL1 - MOnitor Debug System Control Register (EL1).
1430 * @{ */
1431/** Bit 0 - SS - Software step control bit. */
1432#define ARMV8_MDSCR_EL1_AARCH64_SS RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_SS_BIT)
1433#define ARMV8_MDSCR_EL1_AARCH64_SS_BIT 0
1434/** Bit 6 - ERR. */
1435#define ARMV8_MDSCR_EL1_AARCH64_ERR RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_ERR_BIT)
1436#define ARMV8_MDSCR_EL1_AARCH64_ERR_BIT 6
1437/** Bit 12 - TDCC. */
1438#define ARMV8_MDSCR_EL1_AARCH64_TDCC RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TDCC_BIT)
1439#define ARMV8_MDSCR_EL1_AARCH64_TDCC_BIT 12
1440/** Bit 13 - KDE - Kernel Debugging Enabled. */
1441#define ARMV8_MDSCR_EL1_AARCH64_KDE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_KDE_BIT)
1442#define ARMV8_MDSCR_EL1_AARCH64_KDE_BIT 13
1443/** Bit 14 - HDE. */
1444#define ARMV8_MDSCR_EL1_AARCH64_HDE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_HDE_BIT)
1445#define ARMV8_MDSCR_EL1_AARCH64_HDE_BIT 14
1446/** Bit 15 - MDE. */
1447#define ARMV8_MDSCR_EL1_AARCH64_MDE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_MDE_BIT)
1448#define ARMV8_MDSCR_EL1_AARCH64_MDE_BIT 15
1449/** Bit 19 - SC2. */
1450#define ARMV8_MDSCR_EL1_AARCH64_SC2 RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_SC2_BIT)
1451#define ARMV8_MDSCR_EL1_AARCH64_SC2_BIT 19
1452/** Bit 21 - TDA. */
1453#define ARMV8_MDSCR_EL1_AARCH64_TDA RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TDA_BIT)
1454#define ARMV8_MDSCR_EL1_AARCH64_TDA_BIT 21
1455/** Bits 23:22 - INTdis. */
1456#define ARMV8_MDSCR_EL1_AARCH64_INTDIS_MASK UINT64_C(0x00c00000)
1457#define ARMV8_MDSCR_EL1_AARCH64_INTDIS_SHIFT 22
1458/** Bit 26 - TXU. */
1459#define ARMV8_MDSCR_EL1_AARCH64_TXU RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TXU_BIT)
1460#define ARMV8_MDSCR_EL1_AARCH64_TXU_BIT 26
1461/** Bit 29 - TXfull. */
1462#define ARMV8_MDSCR_EL1_AARCH64_TXFULL RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TXFULL_BIT)
1463#define ARMV8_MDSCR_EL1_AARCH64_TXFULL_BIT 29
1464/** Bit 30 - RXfull. */
1465#define ARMV8_MDSCR_EL1_AARCH64_RXFULL RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_RXFULL_BIT)
1466#define ARMV8_MDSCR_EL1_AARCH64_RXFULL_BIT 30
1467/** Bit 31 - TFO. */
1468#define ARMV8_MDSCR_EL1_AARCH64_TFO RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TFO_BIT)
1469#define ARMV8_MDSCR_EL1_AARCH64_TFO_BIT 31
1470/** Bit 32 - EMBWE. */
1471#define ARMV8_MDSCR_EL1_AARCH64_EMBWE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_EMBWE_BIT)
1472#define ARMV8_MDSCR_EL1_AARCH64_EMBWE_BIT 32
1473/** Bit 33 - TTA. */
1474#define ARMV8_MDSCR_EL1_AARCH64_TTA RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TTA_BIT)
1475#define ARMV8_MDSCR_EL1_AARCH64_TTA_BIT 33
1476/** Bit 34 - EnSPM. */
1477#define ARMV8_MDSCR_EL1_AARCH64_ENSPM RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_ENSPM_BIT)
1478#define ARMV8_MDSCR_EL1_AARCH64_ENSPM_BIT 34
1479/** Bit 35 - EHBWE. */
1480#define ARMV8_MDSCR_EL1_AARCH64_EHBWE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_EHBWE_BIT)
1481#define ARMV8_MDSCR_EL1_AARCH64_EHBWE_BIT 35
1482/** Bit 50 - EnSTEPOP. */
1483#define ARMV8_MDSCR_EL1_AARCH64_ENSTEPOP RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_ENSTEPOP_BIT)
1484#define ARMV8_MDSCR_EL1_AARCH64_ENSTEPOP_BIT 50
1485/** @} */
1486
1487
1488/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1489 * @{ */
1490/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1491#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1492#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1493#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1494/** @} */
1495
1496
1497/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1498 * @{ */
1499/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1500#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1501#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1502#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1503/** @} */
1504
1505
1506/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1507 * @{ */
1508/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1509#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1510#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1511#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1512/** @} */
1513
1514
1515/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1516 * @{ */
1517/** Bit 0 - Common Binary Pointer Register - RW. */
1518#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1519#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1520/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1521#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1522#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1523/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1524#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1525#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1526/** Bit 8 - 10 - Priority bits - RO. */
1527#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1528#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1529/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1530#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1531#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1532/** INTIDS are 16-bit wide. */
1533# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1534/** INTIDS are 24-bit wide. */
1535# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1536/** Bit 14 - SEI Supported - RO. */
1537#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1538#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1539/** Bit 15 - Affinity 3 Valid - RO. */
1540#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1541#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1542/** Bit 18 - Range Selector Support - RO. */
1543#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1544#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1545/** Bit 19 - Extended INTID range supported - RO. */
1546#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1547#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1548/** All RW bits. */
1549#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1550/** All RO bits (including Res0). */
1551#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1552/** @} */
1553
1554
1555/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1556 * @{ */
1557/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1558#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1559#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1560/** @} */
1561
1562
1563/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1564 * @{ */
1565/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1566#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1567#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1568/** @} */
1569
1570
1571/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1572 * @{ */
1573/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1574#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1575#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1576/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1577#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1578#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1579/** Bit 24 - 27 - The INTID of the SGI. */
1580#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1581#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1582/* Bit 28 - 31 - Reserved. */
1583/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1584#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1585#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1586/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1587#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1588#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1589/* Bit 41 - 43 - Reserved. */
1590/** Bit 44 - 47 - Range selector. */
1591#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1592#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1593/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1594#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1595#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1596/* Bit 56 - 63 - Reserved. */
1597/** @} */
1598
1599
1600/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1601 * @{ */
1602/** Bit 0 - Enables the timer. */
1603#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1604#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1605/** Bit 1 - Timer interrupt mask bit. */
1606#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1607#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1608/** Bit 2 - Timer status bit. */
1609#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1610#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1611/** @} */
1612
1613
1614/** @name OSLAR_EL1 - OS Lock Access Register.
1615 * @{ */
1616/** Bit 0 - The OS Lock status bit. */
1617#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1618#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1619/** @} */
1620
1621
1622/** @name OSLSR_EL1 - OS Lock Status Register.
1623 * @{ */
1624/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1625#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1626#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1627/** Bit 1 - The OS Lock status bit. */
1628#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1629#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1630/** Bit 2 - Not 32-bit access. */
1631#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1632#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1633/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1634#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1635#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1636/** @} */
1637
1638
1639/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1640 * @{ */
1641/* Bit 0 - 3 - Reserved. */
1642/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1643#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1644#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1645/** No AES instructions implemented. */
1646# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1647/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1648# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1649/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1650# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1651/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1652#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1653#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1654/** No SHA1 instructions implemented. */
1655# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1656/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1657# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1658/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1659#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1660#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1661/** No SHA2 instructions implemented. */
1662# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1663/** SHA256 instructions implemented (FEAT_SHA256). */
1664# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1665/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1666# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1667/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1668#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1669#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1670/** No CRC32 instructions implemented. */
1671# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1672/** CRC32 instructions implemented (FEAT_CRC32). */
1673# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1674/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1675#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1676#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1677/** No Atomic instructions implemented. */
1678# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1679/** Atomic instructions implemented (FEAT_LSE). */
1680# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1681/** Bit 24 - 27 - Indicates support for TME instructions. */
1682#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1683#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1684/** TME instructions are not implemented. */
1685# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1686/** TME instructions are implemented. */
1687# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1688/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1689#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1690#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1691/** No RDMA instructions implemented. */
1692# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1693/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1694# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1695/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1696#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1697#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1698/** No SHA3 instructions implemented. */
1699# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1700/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1701# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1702/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1703#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1704#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1705/** No SM3 instructions implemented. */
1706# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1707/** SM3 instructions implemented (FEAT_SM3). */
1708# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1709/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1710#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1711#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1712/** No SM4 instructions implemented. */
1713# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1714/** SM4 instructions implemented (FEAT_SM4). */
1715# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1716/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1717#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1718#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1719/** No Dot Product instructions implemented. */
1720# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1721/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1722# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1723/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1724#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1725#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1726/** FMLAL and FMLSL instructions are not implemented. */
1727# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1728/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1729# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1730/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1731#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1732#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1733/** No flag manipulation instructions implemented. */
1734# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1735/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1736# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1737/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1738# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1739/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1740#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1741#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1742/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1743# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1744/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1745# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1746/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1747# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1748/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1749#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1750#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1751/** No Random Number instructions implemented. */
1752# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1753/** RNDR and RDNRRS registers are implemented . */
1754# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1755/** @} */
1756
1757
1758/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1759 * @{ */
1760/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1761#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1762#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1763/** DC CVAP not supported. */
1764# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1765/** DC CVAP supported (FEAT_DPB). */
1766# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1767/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1768# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1769/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1770#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1771#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1772/** Address Authentication using the QARMA5 algorithm is not implemented. */
1773# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1774/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1775# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1776/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1777# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1778/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1779# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1780/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1781# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1782/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1783# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1784/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1785#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1786#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1787/** Address Authentication using the QARMA5 algorithm is not implemented. */
1788# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1789/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1790# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1791/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1792# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1793/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1794# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1795/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1796# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1797/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1798# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1799/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1800#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1801#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1802/** No FJCVTZS instruction implemented. */
1803# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1804/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1805# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1806/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1807#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1808#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1809/** No FCMLA and FCADD instructions implemented. */
1810# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1811/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1812# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1813/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1814#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1815#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1816/** No RCpc instructions implemented. */
1817# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1818/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1819# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1820/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1821# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1822/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1823#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1824#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1825/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1826# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1827/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1828# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1829/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1830#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1831#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1832/** Generic Authentication using an implementation defined algorithm is not implemented. */
1833# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1834/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1835# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1836/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1837#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1838#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1839/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1840# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1841/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1842# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1843/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1844#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1845#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1846/** No SB instructions implemented. */
1847# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1848/** SB instructions implemented (FEAT_SB). */
1849# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1850/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1851#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1852#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1853/** Prediction invalidation instructions are not implemented. */
1854# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1855/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1856# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1857/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1858#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1859#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1860/** BFloat16 instructions are not implemented. */
1861# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1862/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1863# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1864/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1865# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1866/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1867#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1868#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1869/** Data Gathering Hint instructions are not implemented. */
1870# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1871/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1872# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1873/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1874#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1875#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1876/** No Int8 matrix multiplication instructions implemented. */
1877# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1878/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1879# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1880/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1881#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1882#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1883/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1884# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1885/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1886# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1887/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1888#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1889#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1890/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1891# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1892/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1893# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1894/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1895# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1896/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1897# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1898/** @} */
1899
1900
1901/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1902 * @{ */
1903/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1904#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1905#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1906/** WFET and WFIT are not supported. */
1907# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1908/** WFET and WFIT are supported (FEAT_WFxT). */
1909# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1910/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1911#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1912#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1913/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1914# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1915/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1916# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1917/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1918#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1919#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1920/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1921# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1922/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1923# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1924/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1925#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1926#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1927/** Address Authentication using the QARMA3 algorithm is not implemented. */
1928# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1929/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1930# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1931/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1932# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1933/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1934# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1935/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1936# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1937/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1938# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1939/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1940#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1941#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1942/** No Memory Copy and Memory Set instructions implemented. */
1943# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1944/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1945# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1946/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1947#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1948#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1949/** BC instruction is not implemented. */
1950# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1951/** BC instruction is implemented (FEAT_HBC). */
1952# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1953/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1954#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1955#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1956/** ConstPACField() returns FALSE. */
1957# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1958/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1959# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1960/* Bit 28 - 63 - Reserved. */
1961/** @} */
1962
1963
1964/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1965 * @{ */
1966/** Bit 0 - 3 - EL0 Exception level handling. */
1967#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1968#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1969/** EL0 can be executed in AArch64 state only. */
1970# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1971/** EL0 can be executed in AArch64 and AArch32 state. */
1972# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1973/** Bit 4 - 7 - EL1 Exception level handling. */
1974#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1975#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1976/** EL1 can be executed in AArch64 state only. */
1977# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1978/** EL1 can be executed in AArch64 and AArch32 state. */
1979# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1980/** Bit 8 - 11 - EL2 Exception level handling. */
1981#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1982#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1983/** EL2 is not implemented. */
1984# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1985/** EL2 can be executed in AArch64 state only. */
1986# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1987/** EL2 can be executed in AArch64 and AArch32 state. */
1988# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1989/** Bit 12 - 15 - EL3 Exception level handling. */
1990#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1991#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1992/** EL3 is not implemented. */
1993# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1994/** EL3 can be executed in AArch64 state only. */
1995# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1996/** EL3 can be executed in AArch64 and AArch32 state. */
1997# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1998/** Bit 16 - 19 - Floating-point support. */
1999#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2000#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
2001/** Floating-point is implemented and support single and double precision. */
2002# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
2003/** Floating-point is implemented and support single, double and half precision. */
2004# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
2005/** Floating-point is not implemented. */
2006# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
2007/** Bit 20 - 23 - Advanced SIMD support. */
2008#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2009#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
2010/** Advanced SIMD is implemented and support single and double precision. */
2011# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
2012/** Advanced SIMD is implemented and support single, double and half precision. */
2013# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
2014/** Advanced SIMD is not implemented. */
2015# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
2016/** Bit 24 - 27 - System register GIC CPU interface support. */
2017#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2018#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
2019/** GIC CPU interface system registers are not implemented. */
2020# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
2021/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
2022# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
2023/** System register interface to version 4.1 of the GIC CPU interface is supported. */
2024# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
2025/** Bit 28 - 31 - RAS Extension version. */
2026#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2027#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
2028/** No RAS extension. */
2029# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
2030/** RAS Extension implemented. */
2031# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
2032/** FEAT_RASv1p1 implemented. */
2033# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
2034/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
2035#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2036#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
2037/** SVE is not supported. */
2038# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
2039/** SVE is supported. */
2040# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
2041/** Bit 36 - 39 - Secure EL2 support. */
2042#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2043#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
2044/** Secure EL2 is not supported. */
2045# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
2046/** Secure EL2 is implemented. */
2047# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
2048/** Bit 40 - 43 - MPAM support. */
2049#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2050#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
2051/** MPAM extension major version number is 0. */
2052# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
2053/** MPAM extension major version number is 1. */
2054# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
2055/** Bit 44 - 47 - Activity Monitor Extension support. */
2056#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2057#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
2058/** Activity Monitor extension is not implemented. */
2059# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
2060/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
2061# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
2062/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
2063# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
2064/** Bit 48 - 51 - Data Independent Timing support. */
2065#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2066#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
2067/** AArch64 does not guarantee constant execution time of any instructions. */
2068# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
2069/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
2070# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
2071/** Bit 52 - 55 - Realm Management Extension support. */
2072#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2073#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
2074/** Realm Management Extension not implemented. */
2075# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
2076/** RMEv1 is implemented (FEAT_RME). */
2077# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
2078/** Bit 56 - 59 - Speculative use out of context branch targets support. */
2079#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2080#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
2081/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
2082# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
2083/** FEAT_CSV2 is implemented. */
2084# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
2085/** FEAT_CSV2_2 is implemented. */
2086# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
2087/** FEAT_CSV2_3 is implemented. */
2088# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
2089/** Bit 60 - 63 - Speculative use of faulting data support. */
2090#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2091#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
2092/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
2093# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
2094/** FEAT_CSV3 is supported . */
2095# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
2096/** @} */
2097
2098
2099/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
2100 * @{ */
2101/** Bit 0 - 3 - Branch Target Identification support. */
2102#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2103#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
2104/** The Branch Target Identification mechanism is not implemented. */
2105# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
2106/** The Branch Target Identifcation mechanism is implemented. */
2107# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
2108/** Bit 4 - 7 - Speculative Store Bypassing control support. */
2109#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2110#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
2111/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
2112# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
2113/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
2114# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
2115/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
2116 * to directly read and write the PSTATE.SSBS field. */
2117# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
2118/** Bit 8 - 11 - Memory Tagging Extension support. */
2119#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2120#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
2121/** MTE is not implemented. */
2122# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
2123/** Instruction only Memory Tagging Extensions implemented. */
2124# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
2125/** Full Memory Tagging Extension implemented. */
2126# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
2127/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
2128# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
2129/** Bit 12 - 15 - RAS Extension fractional field. */
2130#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2131#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
2132/** RAS Extension is implemented. */
2133# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
2134/** FEAT_RASv1p1 is implemented. */
2135# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
2136/** Bit 16 - 19 - MPAM minor version number. */
2137#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2138#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
2139/** The minor version of number of the MPAM extension is 0. */
2140# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
2141/** The minor version of number of the MPAM extension is 1. */
2142# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
2143/* Bit 20 - 23 - Reserved. */
2144/** Bit 24 - 27 - Scalable Matrix Extension support. */
2145#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2146#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
2147/** Scalable Matrix Extensions are not implemented. */
2148# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
2149/** Scalable Matrix Extensions are implemented (FEAT_SME). */
2150# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
2151/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
2152# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
2153/** Bit 28 - 31 - Random Number trap to EL3 support. */
2154#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2155#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
2156/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
2157# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
2158/** Trapping of RNDR and RDNRRS to EL3 is supported. */
2159# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
2160/** Bit 32 - 35 - CSV2 fractional field. */
2161#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2162#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
2163/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
2164# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
2165/** FEAT_CSV2_1p1 is implemented. */
2166# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
2167/** FEAT_CSV2_1p2 is implemented. */
2168# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
2169/** Bit 36 - 39 - Non-maskable Interrupt support. */
2170#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2171#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
2172/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
2173# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
2174/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
2175# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
2176/** @} */
2177
2178
2179/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
2180 * @{ */
2181/** Bit 0 - 3 - Physical Address range supported. */
2182#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2183#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
2184/** Physical Address range is 32 bits, 4GiB. */
2185# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
2186/** Physical Address range is 36 bits, 64GiB. */
2187# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
2188/** Physical Address range is 40 bits, 1TiB. */
2189# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
2190/** Physical Address range is 42 bits, 4TiB. */
2191# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
2192/** Physical Address range is 44 bits, 16TiB. */
2193# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
2194/** Physical Address range is 48 bits, 256TiB. */
2195# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
2196/** Physical Address range is 52 bits, 4PiB. */
2197# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
2198/** Bit 4 - 7 - Number of ASID bits. */
2199#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2200#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
2201/** ASID bits is 8. */
2202# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
2203/** ASID bits is 16. */
2204# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
2205/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
2206#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2207#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
2208/** No mixed-endian support. */
2209# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
2210/** Mixed-endian supported. */
2211# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
2212/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
2213#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2214#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
2215/** No distinction between Secure and Non-secure Memory supported. */
2216# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
2217/** Distinction between Secure and Non-secure Memory supported. */
2218# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
2219/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
2220#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2221#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
2222/** No mixed-endian support at EL0. */
2223# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
2224/** Mixed-endian support at EL0. */
2225# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
2226/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
2227#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2228#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
2229/** 16KiB granule size not supported. */
2230# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
2231/** 16KiB granule size is supported. */
2232# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
2233/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2234# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
2235/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
2236#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2237#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
2238/** 64KiB granule supported. */
2239# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
2240/** 64KiB granule not supported. */
2241# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
2242/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
2243#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2244#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
2245/** 4KiB granule supported. */
2246# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
2247/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2248# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
2249/** 4KiB granule not supported. */
2250# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
2251/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
2252#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2253#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
2254/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
2255# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
2256/** 16KiB granule not supported at stage 2. */
2257# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
2258/** 16KiB granule supported at stage 2. */
2259# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
2260/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2261# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
2262/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
2263#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2264#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
2265/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
2266# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
2267/** 64KiB granule not supported at stage 2. */
2268# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
2269/** 64KiB granule supported at stage 2. */
2270# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
2271/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2272#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2273#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
2274/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
2275# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
2276/** 4KiB granule not supported at stage 2. */
2277# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
2278/** 4KiB granule supported at stage 2. */
2279# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
2280/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2281# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
2282/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
2283#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2284#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
2285/** All exception entries and exits are context synchronization events. */
2286# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
2287/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
2288# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
2289/* Bit 48 - 55 - Reserved. */
2290/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
2291#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2292#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
2293/** Fine-grained trap controls are not implemented. */
2294# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
2295/** Fine-grained trap controls are implemented (FEAT_FGT). */
2296# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
2297/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
2298#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2299#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
2300/** Enhanced Counter Virtualization is not implemented. */
2301# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
2302/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
2303# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
2304/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
2305# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
2306/** @} */
2307
2308
2309/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
2310 * @{ */
2311/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
2312#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2313#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
2314/** Hardware update of the Access flag and dirty state are not supported. */
2315# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
2316/** Support for hardware update of the Access flag for Block and Page descriptors. */
2317# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
2318/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
2319# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
2320/** Bit 4 - 7 - EL1 Exception level handling. */
2321#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2322#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
2323/** VMID bits is 8. */
2324# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
2325/** VMID bits is 16 (FEAT_VMID16). */
2326# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
2327/** Bit 8 - 11 - Virtualization Host Extensions support. */
2328#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2329#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
2330/** Virtualization Host Extensions are not supported. */
2331# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
2332/** Virtualization Host Extensions are supported. */
2333# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
2334/** Bit 12 - 15 - Hierarchical Permission Disables. */
2335#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2336#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
2337/** Disabling of hierarchical controls not supported. */
2338# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
2339/** Disabling of hierarchical controls supported (FEAT_HPDS). */
2340# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
2341/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
2342# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
2343/** Bit 16 - 19 - LORegions support. */
2344#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2345#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
2346/** LORegions not supported. */
2347# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
2348/** LORegions supported. */
2349# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
2350/** Bit 20 - 23 - Privileged Access Never support. */
2351#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2352#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
2353/** PAN not supported. */
2354# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
2355/** PAN supported (FEAT_PAN). */
2356# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
2357/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
2358# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
2359/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
2360# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
2361/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
2362#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2363#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
2364/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
2365# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
2366/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
2367# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
2368/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
2369#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2370#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
2371/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
2372# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
2373/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
2374# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
2375/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
2376#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2377#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
2378/** Configurable delayed trapping of WFE is not supported. */
2379# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
2380/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
2381# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
2382/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
2383#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2384#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
2385/** Enhanced Translation Synchronization is not supported. */
2386# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
2387/** Enhanced Translation Synchronization is implemented. */
2388# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
2389/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2390#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2391#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
2392/** HCRX_EL2 and its associated EL3 trap are not supported. */
2393# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
2394/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
2395# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
2396/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
2397#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2398#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
2399/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
2400# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
2401/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
2402# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
2403/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
2404#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2405#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
2406/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
2407# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
2408/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
2409# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
2410/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
2411#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2412#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
2413/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
2414# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
2415/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
2416# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
2417/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
2418#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2419#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
2420/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
2421# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
2422/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
2423# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
2424/* Bit 60 - 63 - Reserved. */
2425/** @} */
2426
2427
2428/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
2429 * @{ */
2430/** Bit 0 - 3 - Indicates support for Common not Private translations. */
2431#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2432#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
2433/** Common not Private translations are not supported. */
2434# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
2435/** Support for Common not Private translations (FEAT_TTNCP). */
2436# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
2437/** Bit 4 - 7 - Indicates support for User Access Override. */
2438#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2439#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2440/** User Access Override is not supported. */
2441# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2442/** User Access Override is supported (FEAT_UAO). */
2443# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2444/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2445#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2446#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2447/** LSMAOE and nTLSMD bits are not supported. */
2448# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2449/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2450# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2451/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2452#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2453#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2454/** IESB bit is not supported. */
2455# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2456/** IESB bit is supported (FEAT_IESB). */
2457# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2458/** Bit 16 - 19 - Indicates support for larger virtual address. */
2459#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2460#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2461/** Virtual address range is 48 bits. */
2462# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2463/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2464# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2465/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2466#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2467#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2468/** CCSIDR_EL1 register format is 32-bit. */
2469# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2470/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2471# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2472/** Bit 24 - 27 - Indicates support for nested virtualization. */
2473#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2474#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2475/** Nested virtualization is not supported. */
2476# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2477/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2478# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2479/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2480# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2481/** Bit 28 - 31 - Indicates support for small translation tables. */
2482#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2483#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2484/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2485# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2486/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2487# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2488/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2489#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2490#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2491/** Unaligned single-copy atomicity and atomic functions are not supported. */
2492# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2493/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2494# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2495/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2496#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2497#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2498/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2499# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2500/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2501# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2502/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2503#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2504#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2505/** HCR_EL2.FWB bit is not supported. */
2506# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2507/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2508# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2509/* Bit 44 - 47 - Reserved. */
2510/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2511#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2512#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2513/** TLB maintenance instructions by address have bits [47:44] Res0. */
2514# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2515/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2516# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2517/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2518 * changing block size for a translation. */
2519#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2520#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2521/** Level 0 support for changing block size is supported (FEAT_BBM). */
2522# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2523/** Level 1 support for changing block size is supported (FEAT_BBM). */
2524# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2525/** Level 2 support for changing block size is supported (FEAT_BBM). */
2526# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2527/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2528#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2529#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2530/** Enhanced Virtualization Traps are not supported. */
2531# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2532/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2533# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2534/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2535# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2536/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2537#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2538#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2539/** E0PDx mechanism is not supported. */
2540# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2541/** E0PDx mechanism is supported (FEAT_E0PD). */
2542# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2543/** @} */
2544
2545
2546/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2547 * @{ */
2548/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2549#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2550#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2551/** Armv8 debug architecture version. */
2552# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2553/** Armv8 debug architecture version with virtualization host extensions. */
2554# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2555/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2556# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2557/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2558# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2559/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2560# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2561/** Bit 4 - 7 - Indicates trace support. */
2562#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2563#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2564/** Trace unit System registers not implemented. */
2565# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2566/** Trace unit System registers supported. */
2567# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2568/** Bit 8 - 11 - Performance Monitors Extension version. */
2569#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2570#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2571/** Performance Monitors Extension not supported. */
2572# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2573/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2574# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2575/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2576# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2577/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2578# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2579/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2580# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2581/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2582# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2583/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2584# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2585/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2586#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2587#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2588/* Bit 16 - 19 - Reserved 0. */
2589/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2590#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2591#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2592/* Bit 24 - 27 - Reserved 0. */
2593/** Bit 28 - 31 - Number of context-aware breakpoints. */
2594#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2595#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2596/** Bit 32 - 35 - Statistical Profiling Extension version. */
2597#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2598#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2599/** Statistical Profiling Extension not implemented. */
2600# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2601/** Statistical Profiling Extension supported (FEAT_SPE). */
2602# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2603/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2604# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2605/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2606# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2607/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2608# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2609/** Bit 36 - 39 - OS Double Lock implemented. */
2610#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2611#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2612/** OS Double Lock is not implemented. */
2613# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2614/** OS Double Lock is supported (FEAT_DoubleLock). */
2615# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2616/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2617#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2618#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2619/** Armv8.4 self-hosted Trace Extension not implemented. */
2620# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2621/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2622# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2623/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2624#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2625#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2626/** Trace Buffer Extension is not implemented. */
2627# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2628/** Trace Buffer Extension is supported (FEAT_TRBE). */
2629# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2630/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2631#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2632#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2633/** Multi-threaded PMU extension is not implemented. */
2634# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2635/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2636# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2637/** Multi-threaded PMU extension is not implemented. */
2638# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2639/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2640#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2641#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2642/** Branch Record Buffer extension is not implemented. */
2643# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2644/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2645# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2646/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2647# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2648/* Bit 56 - 59 - Reserved. */
2649/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2650#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2651#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2652/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2653# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2654/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2655# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2656/** @} */
2657
2658
2659/** @name FPCR - AArch64 Floating Point Control Register.
2660 * @{ */
2661/** Bit 0 - Flush Inputs to Zero when FEAT_AFP is supported. */
2662#define ARMV8_FPCR_FIZ RT_BIT_64(0)
2663#define ARMV8_FPCR_FIZ_BIT 0
2664/** Bit 1 - Alternate Handling of floating-point numbers when FEAT_AFP is supported. */
2665#define ARMV8_FPCR_AH RT_BIT_64(1)
2666#define ARMV8_FPCR_AH_BIT 1
2667/** Bit 2 - Controls how the output elements other than the lowest element of the vector are determined for
2668 * Advanced SIMD scalar instructions, when FEAT_AFP is supported. */
2669#define ARMV8_FPCR_NEP RT_BIT_64(2)
2670#define ARMV8_FPCR_NEP_BIT 2
2671/* Bit 3 - 7 - Reserved.*/
2672/** Bit 8 - Invalid Operation floating-point exception trap enable. */
2673#define ARMV8_FPCR_IOE RT_BIT_64(8)
2674#define ARMV8_FPCR_IOE_BIT 8
2675/** Bit 9 - Divide by Zero floating-point exception trap enable. */
2676#define ARMV8_FPCR_DZE RT_BIT_64(9)
2677#define ARMV8_FPCR_DZE_BIT 9
2678/** Bit 10 - Overflow floating-point exception trap enable. */
2679#define ARMV8_FPCR_OFE RT_BIT_64(10)
2680#define ARMV8_FPCR_OFE_BIT 10
2681/** Bit 11 - Underflow floating-point exception trap enable. */
2682#define ARMV8_FPCR_UFE RT_BIT_64(11)
2683#define ARMV8_FPCR_UFE_BIT 11
2684/** Bit 12 - Inexact floating-point exception trap enable. */
2685#define ARMV8_FPCR_IXE RT_BIT_64(12)
2686#define ARMV8_FPCR_IXE_BIT 12
2687/** Bit 13 - Controls numeric behavior of BFloat16 dot productions calculations performed,
2688 * supported when FEAT_EBF16 is supported. */
2689#define ARMV8_FPCR_EBF RT_BIT_64(13)
2690#define ARMV8_FPCR_EBF_BIT 13
2691/* Bit 14 - Reserved */
2692/** Bit 15 - Input Denormal floating-point exception trap enable. */
2693#define ARMV8_FPCR_IDE RT_BIT_64(15)
2694#define ARMV8_FPCR_IDE_BIT 15
2695/* Bit 16 - 18 - Reserved for AArch64 (Len field for AArch32). */
2696/** Bit 19 - Flushing denormalized numbers to zero control bit on half-precision data-processing instructions,
2697 * available when FEAT_FP16 is supported. */
2698#define ARMV8_FPCR_FZ16 RT_BIT_64(19)
2699#define ARMV8_FPCR_FZ16_BIT 19
2700/* Bit 20 - 21 - Reserved for AArch64 (Stride field dor AArch32). */
2701/** Bit 22 - 23 - Rounding Mode control field. */
2702#define ARMV8_FPCR_RMODE_MASK (RT_BIT_64(22) | RT_BIT_64(23))
2703#define ARMV8_FPCR_RMODE_SHIFT 22
2704/** Round to Nearest (RN) mode. */
2705# define ARMV8_FPCR_RMODE_RN 0
2706/** Round towards Plus Infinity (RP) mode. */
2707# define ARMV8_FPCR_RMODE_RP 1
2708/** Round towards Minus Infinity (RM) mode. */
2709# define ARMV8_FPCR_RMODE_RM 2
2710/** Round towards Zero (RZ) mode. */
2711# define ARMV8_FPCR_RMODE_RZ 3
2712/** Bit 24 - Flushing denormalized numbers to zero control bit. */
2713#define ARMV8_FPCR_FZ RT_BIT_64(24)
2714#define ARMV8_FPCR_FZ_BIT 24
2715/** Bit 25 - Default NaN use for NaN propagation. */
2716#define ARMV8_FPCR_DN RT_BIT_64(25)
2717#define ARMV8_FPCR_DN_BIT 25
2718/** Bit 26 - Alternative half-precision control bit. */
2719#define ARMV8_FPCR_AHP RT_BIT_64(26)
2720#define ARMV8_FPCR_AHP_BIT 26
2721/* Bit 27 - 63 - Reserved. */
2722/** @} */
2723
2724
2725/** @name FPSR - AArch64 Floating Point Status Register.
2726 * @{ */
2727/** Bit 0 - Invalid Operation cumulative floating-point exception bit. */
2728#define ARMV8_FPSR_IOC RT_BIT_64(0)
2729/** Bit 1 - Divide by Zero cumulative floating-point exception bit. */
2730#define ARMV8_FPSR_DZC RT_BIT_64(1)
2731/** Bit 2 - Overflow cumulative floating-point exception bit. */
2732#define ARMV8_FPSR_OFC RT_BIT_64(2)
2733/** Bit 3 - Underflow cumulative floating-point exception bit. */
2734#define ARMV8_FPSR_UFC RT_BIT_64(3)
2735/** Bit 4 - Inexact cumulative floating-point exception bit. */
2736#define ARMV8_FPSR_IXC RT_BIT_64(4)
2737/* Bit 5 - 6 - Reserved. */
2738/** Bit 7 - Input Denormal cumulative floating-point exception bit. */
2739#define ARMV8_FPSR_IDC RT_BIT_64(7)
2740/* Bit 8 - 26 - Reserved. */
2741/** Bit 27 - Cumulative saturation bit, Advanced SIMD only. */
2742#define ARMV8_FPSR_QC RT_BIT_64(27)
2743/* Bit 28 - 31 - NZCV bits for AArch32 floating point operations. */
2744/* Bit 32 - 63 - Reserved. */
2745/** @} */
2746
2747
2748
2749/** @name SCTLR_EL1 - AArch64 System Control Register (EL1).
2750 * @{ */
2751/** Bit 0 - MMU enable for EL1 and EL0 stage 1 address translation. */
2752#define ARMV8_SCTLR_EL1_M RT_BIT_64(0)
2753/** Bit 1 - Alignment check enable for EL1 and EL0. */
2754#define ARMV8_SCTLR_EL1_A RT_BIT_64(1)
2755/** Bit 2 - Stage 1 cacheability control, for data accesses. */
2756#define ARMV8_SCTLR_EL1_C RT_BIT_64(2)
2757/** Bit 3 - SP alignment check enable. */
2758#define ARMV8_SCTLR_EL1_SA RT_BIT_64(3)
2759/** Bit 4 - SP alignment check enable for EL0. */
2760#define ARMV8_SCTLR_EL1_SA0 RT_BIT_64(4)
2761/** Bit 5 - System instruction memory barrier enable from AArch32 EL0. */
2762#define ARMV8_SCTLR_EL1_CP15BEN RT_BIT_64(5)
2763/** Bit 6 - Non-aligned access enable. */
2764#define ARMV8_SCTLR_EL1_NAA RT_BIT_64(6)
2765#define ARMV8_SCTLR_EL1_nAA RT_BIT_64(6)
2766/** Bit 7 - IT disable, disables some uses of IT instructions at EL0 using AArch32. */
2767#define ARMV8_SCTLR_EL1_ITD RT_BIT_64(7)
2768/** Bit 8 - SETEND instruction disable, disables SETEND instructions at EL0 using AArch32. */
2769#define ARMV8_SCTLR_EL1_SED RT_BIT_64(8)
2770/** Bit 9 - User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D,A,I,F} masks to EL1. */
2771#define ARMV8_SCTLR_EL1_UMA RT_BIT_64(9)
2772/** Bit 10 - Enable EL0 acccess to the CFP*, DVP* and CPP* instructions if FEAT_SPECRES is supported. */
2773#define ARMV8_SCTLR_EL1_ENRCTX RT_BIT_64(10)
2774#define ARMV8_SCTLR_EL1_EnRCTX ARMV8_SCTLR_EL1_ENRCTX
2775/** Bit 11 - Exception Exit is Context Synchronizing (FEAT_ExS required). */
2776#define ARMV8_SCTLR_EL1_EOS RT_BIT_64(11)
2777/** Bit 12 - Stage 1 instruction access cacheability control, for access at EL0 and EL1. */
2778#define ARMV8_SCTLR_EL1_I RT_BIT_64(12)
2779/** @todo Finish (lazy developer). */
2780/** @} */
2781
2782
2783/** @name SCTLR_EL2 - AArch64 System Control Register (EL2).
2784 * @{ */
2785/** Bit 0 - MMU enable for EL2. */
2786#define ARMV8_SCTLR_EL2_M RT_BIT_64(0)
2787/** Bit 1 - Alignment check enable. */
2788#define ARMV8_SCTLR_EL2_A RT_BIT_64(1)
2789/** Bit 2 - Global enable for data and unified caches. */
2790#define ARMV8_SCTLR_EL2_C RT_BIT_64(2)
2791/** Bit 3 - SP alignment check enable. */
2792#define ARMV8_SCTLR_EL2_SA RT_BIT_64(3)
2793/** Bit 4 - SA0. */
2794#define ARMV8_SCTLR_EL2_SA0 RT_BIT_64(4)
2795/** Bit 5 - CP15BEN. */
2796#define ARMV8_SCTLR_EL2_CP15BEN RT_BIT_64(5)
2797/** Bit 6 - nAA. */
2798#define ARMV8_SCTLR_EL2_NAA RT_BIT_64(6)
2799/** Bit 7 - IDT. */
2800#define ARMV8_SCTLR_EL2_IDT RT_BIT_64(7)
2801/** Bit 8 - SED. */
2802#define ARMV8_SCTLR_EL2_SED RT_BIT_64(8)
2803/* Bit 9 - RES0 (2024-12). */
2804/** Bit 10 - EnRCTX. */
2805#define ARMV8_SCTLR_EL2_ENRCTX RT_BIT_64(10)
2806/** Bit 11 - EOS. */
2807#define ARMV8_SCTLR_EL2_EOS RT_BIT_64(11)
2808/** Bit 12 - Instruction cache enable. */
2809#define ARMV8_SCTLR_EL2_I RT_BIT_64(12)
2810/** Bit 13 - EnDB. */
2811#define ARMV8_SCTLR_EL2_ENDB RT_BIT_64(13)
2812/** Bit 14 - DZE. */
2813#define ARMV8_SCTLR_EL2_DZE RT_BIT_64(14)
2814/** Bit 15 - UCT. */
2815#define ARMV8_SCTLR_EL2_UCT RT_BIT_64(15)
2816/** Bit 16 - nTWI. */
2817#define ARMV8_SCTLR_EL2_NTWI RT_BIT_64(16)
2818/* Bit 17 - RES0 (2024-12). */
2819/** Bit 18 - nTWE. */
2820#define ARMV8_SCTLR_EL2_NTWE RT_BIT_64(18)
2821/** Bit 19 - Force treatment of all memory regions with write permissions as XN. */
2822#define ARMV8_SCTLR_EL2_WXN RT_BIT_64(19)
2823/** Bit 20 - TSCXT. */
2824#define ARMV8_SCTLR_EL2_TSCXT RT_BIT_64(20)
2825/** Bit 21 - IESB. */
2826#define ARMV8_SCTLR_EL2_IESB RT_BIT_64(21)
2827/** Bit 22 - EIS. */
2828#define ARMV8_SCTLR_EL2_EIS RT_BIT_64(22)
2829/** Bit 23 - SPAN. */
2830#define ARMV8_SCTLR_EL2_SPAN RT_BIT_64(23)
2831/** Bit 24 - E0E. */
2832#define ARMV8_SCTLR_EL2_E0E RT_BIT_64(24)
2833/** Bit 25 - Exception endianess - set means big endian, clear little endian. */
2834#define ARMV8_SCTLR_EL2_EE RT_BIT_64(25)
2835/** @todo Finish (lazy developer). */
2836/** @} */
2837
2838
2839/** @name HCR_EL2 - AArch64 Hypervisor Configuration Register (EL2).
2840 * @{ */
2841#define ARMV8_HCR_EL2_VM RT_BIT_64(0)
2842#define ARMV8_HCR_EL2_SWIO RT_BIT_64(1)
2843#define ARMV8_HCR_EL2_PTW RT_BIT_64(2)
2844#define ARMV8_HCR_EL2_FMO RT_BIT_64(3)
2845#define ARMV8_HCR_EL2_IMO RT_BIT_64(4)
2846#define ARMV8_HCR_EL2_AMO RT_BIT_64(5)
2847#define ARMV8_HCR_EL2_VF RT_BIT_64(6)
2848#define ARMV8_HCR_EL2_VI RT_BIT_64(7)
2849#define ARMV8_HCR_EL2_VSE RT_BIT_64(8)
2850#define ARMV8_HCR_EL2_FB RT_BIT_64(9)
2851#define ARMV8_HCR_EL2_BSU_MASK (RT_BIT_64(10) | RT_BIT_64(11))
2852#define ARMV8_HCR_EL2_DC RT_BIT_64(12)
2853#define ARMV8_HCR_EL2_TWI RT_BIT_64(13)
2854#define ARMV8_HCR_EL2_TWE RT_BIT_64(14)
2855#define ARMV8_HCR_EL2_TID0 RT_BIT_64(15)
2856#define ARMV8_HCR_EL2_TID1 RT_BIT_64(16)
2857#define ARMV8_HCR_EL2_TID2 RT_BIT_64(17)
2858#define ARMV8_HCR_EL2_TID3 RT_BIT_64(18)
2859#define ARMV8_HCR_EL2_TSC RT_BIT_64(19)
2860#define ARMV8_HCR_EL2_TIDCP RT_BIT_64(20)
2861#define ARMV8_HCR_EL2_TACR RT_BIT_64(21)
2862#define ARMV8_HCR_EL2_TSW RT_BIT_64(22)
2863#define ARMV8_HCR_EL2_TDCP RT_BIT_64(23)
2864#define ARMV8_HCR_EL2_TPU RT_BIT_64(24)
2865#define ARMV8_HCR_EL2_TTLB RT_BIT_64(25)
2866#define ARMV8_HCR_EL2_TVM RT_BIT_64(26)
2867#define ARMV8_HCR_EL2_TGE RT_BIT_64(27)
2868#define ARMV8_HCR_EL2_TDZ RT_BIT_64(28)
2869#define ARMV8_HCR_EL2_HCD RT_BIT_64(29)
2870#define ARMV8_HCR_EL2_TRVM RT_BIT_64(30)
2871#define ARMV8_HCR_EL2_RW RT_BIT_64(31)
2872#define ARMV8_HCR_EL2_CD RT_BIT_64(32)
2873#define ARMV8_HCR_EL2_IC RT_BIT_64(33)
2874#define ARMV8_HCR_EL2_E2H RT_BIT_64(34)
2875#define ARMV8_HCR_EL2_TLOR RT_BIT_64(35)
2876#define ARMV8_HCR_EL2_TERR RT_BIT_64(36)
2877#define ARMV8_HCR_EL2_TEA RT_BIT_64(37)
2878#define ARMV8_HCR_EL2_MIOCNCE RT_BIT_64(38)
2879#define ARMV8_HCR_EL2_TME RT_BIT_64(39)
2880#define ARMV8_HCR_EL2_APK RT_BIT_64(40)
2881#define ARMV8_HCR_EL2_API RT_BIT_64(41)
2882#define ARMV8_HCR_EL2_NV RT_BIT_64(42)
2883#define ARMV8_HCR_EL2_NV1 RT_BIT_64(43)
2884#define ARMV8_HCR_EL2_AT RT_BIT_64(44)
2885#define ARMV8_HCR_EL2_NV2 RT_BIT_64(45)
2886#define ARMV8_HCR_EL2_FWB RT_BIT_64(46)
2887#define ARMV8_HCR_EL2_FIEN RT_BIT_64(47)
2888#define ARMV8_HCR_EL2_GPF RT_BIT_64(48)
2889#define ARMV8_HCR_EL2_TID4 RT_BIT_64(49)
2890#define ARMV8_HCR_EL2_TICAB RT_BIT_64(50)
2891#define ARMV8_HCR_EL2_AMVOFFEN RT_BIT_64(51)
2892#define ARMV8_HCR_EL2_TOCU RT_BIT_64(52)
2893#define ARMV8_HCR_EL2_ENSCXT RT_BIT_64(53)
2894#define ARMV8_HCR_EL2_TTLBIS RT_BIT_64(54)
2895#define ARMV8_HCR_EL2_TTLBOS RT_BIT_64(55)
2896#define ARMV8_HCR_EL2_ATA RT_BIT_64(56)
2897#define ARMV8_HCR_EL2_DCT RT_BIT_64(57)
2898#define ARMV8_HCR_EL2_TID5 RT_BIT_64(58)
2899#define ARMV8_HCR_EL2_TWEDEN RT_BIT_64(59)
2900#define ARMV8_HCR_EL2_TWEDL_MASK UINT64_C(0xf000000000000000)
2901/** @} */
2902
2903
2904/** @name MDCR_EL2 - AArch64 Monitor Debug Configuration Register (EL2).
2905 * @{ */
2906#define ARMV8_MDCR_EL2_HPMN_MASK UINT64_C(0x1f)
2907#define ARMV8_MDCR_EL2_TPMCR RT_BIT_64(5)
2908#define ARMV8_MDCR_EL2_TPM RT_BIT_64(6)
2909#define ARMV8_MDCR_EL2_HPME RT_BIT_64(7)
2910#define ARMV8_MDCR_EL2_TDE RT_BIT_64(8)
2911#define ARMV8_MDCR_EL2_TDA RT_BIT_64(9)
2912#define ARMV8_MDCR_EL2_TDOSA RT_BIT_64(10)
2913#define ARMV8_MDCR_EL2_TDRA RT_BIT_64(11)
2914#define ARMV8_MDCR_EL2_E2PB_MASK (RT_BIT_64(12) | RT_BIT_64(13))
2915#define ARMV8_MDCR_EL2_TPMS RT_BIT_64(14)
2916#define ARMV8_MDCR_EL2_ENSPM RT_BIT_64(15)
2917/* Bit 16 - RES0 (2024-12) */
2918#define ARMV8_MDCR_EL2_HPMD RT_BIT_64(17)
2919/* Bit 18 - RES0 (2024-12) */
2920#define ARMV8_MDCR_EL2_TTRF RT_BIT_64(19)
2921/* Bits 22:20 - RES0 (2024-12) */
2922#define ARMV8_MDCR_EL2_HCCD RT_BIT_64(23)
2923#define ARMV8_MDCR_EL2_E2TB_MASK (RT_BIT_64(24) | RT_BIT_64(25))
2924#define ARMV8_MDCR_EL2_HLP RT_BIT_64(26)
2925#define ARMV8_MDCR_EL2_TDCC RT_BIT_64(27)
2926#define ARMV8_MDCR_EL2_MTPME RT_BIT_64(28)
2927#define ARMV8_MDCR_EL2_HPMFZO RT_BIT_64(29)
2928#define ARMV8_MDCR_EL2_PMSSE_MASK (RT_BIT_64(30) | RT_BIT_64(31))
2929/* Bits 35:32 - RES0 (2024-12) */
2930#define ARMV8_MDCR_EL2_HPMFZS RT_BIT_64(36)
2931/* Bits 39:37 - RES0 (2024-12) */
2932#define ARMV8_MDCR_EL2_PMEE_MASK (RT_BIT_64(40) | RT_BIT_64(41))
2933/* Bit 42 - RES0 (2024-12) */
2934#define ARMV8_MDCR_EL2_EBWE RT_BIT_64(43)
2935/* Bits 49:44 - RES0 (2024-12) */
2936#define ARMV8_MDCR_EL2_ENSTEPOP RT_BIT_64(50)
2937/* Bits 63:51 - RES0 (2024-12) */
2938/** @} */
2939
2940
2941#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
2942/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2943 * @ingroup grp_rt_armv8
2944 *
2945 * A few inlined functions and macros for assiting in encoding common ARMv8
2946 * instructions.
2947 *
2948 * @{ */
2949
2950/** A64: Official NOP instruction. */
2951#define ARMV8_A64_INSTR_NOP UINT32_C(0xd503201f)
2952/** A64: Return instruction. */
2953#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2954/** A64: Return instruction with LR pointer authentication using SP and key A. */
2955#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2956/** A64: Return instruction with LR pointer authentication using SP and key B. */
2957#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2958/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2959#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2960/** A64: Insert pointer authentication code into LR using SP and key B. */
2961#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2962/** A64: Insert pointer authentication code into LR using XZR and key B. */
2963#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2964/** A64: Invert the carry flag (PSTATE.C). */
2965#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
2966
2967
2968/** Memory barrier: Shareability domain. */
2969typedef enum
2970{
2971 kArm64InstMbReqDomain_OuterShareable = 0,
2972 kArm64InstMbReqDomain_Nonshareable,
2973 kArm64InstMbReqDomain_InnerShareable,
2974 kArm64InstMbReqDomain_FullSystem
2975} ARM64INSTRMBREQDOMAIN;
2976
2977/** Memory barrier: Access type. */
2978typedef enum
2979{
2980 kArm64InstMbReqType_All0 = 0, /**< Special. Only used with PSSBB and SSBB. */
2981 kArm64InstMbReqType_Reads,
2982 kArm64InstMbReqType_Writes,
2983 kArm64InstMbReqType_All
2984} ARM64INSTRMBREQTYPE;
2985
2986/**
2987 * A64: DMB option
2988 */
2989DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDmb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
2990 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
2991{
2992 return UINT32_C(0xd50330bf)
2993 | ((uint32_t)enmDomain << 8)
2994 | ((uint32_t)enmType << 10);
2995}
2996
2997
2998/**
2999 * A64: DSB option
3000 */
3001DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
3002 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
3003{
3004 return UINT32_C(0xd503309f)
3005 | ((uint32_t)enmDomain << 8)
3006 | ((uint32_t)enmType << 10);
3007}
3008
3009
3010/**
3011 * A64: SSBB
3012 */
3013DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSsbb(void)
3014{
3015 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_OuterShareable, kArm64InstMbReqType_All0);
3016}
3017
3018
3019/**
3020 * A64: PSSBB
3021 */
3022DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPSsbb(void)
3023{
3024 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_Nonshareable, kArm64InstMbReqType_All0);
3025}
3026
3027
3028/**
3029 * A64: ISB option
3030 *
3031 * @note Only the default option selection is supported, all others are
3032 * currently reserved.
3033 */
3034DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
3035 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
3036{
3037 return UINT32_C(0xd50330df)
3038 | ((uint32_t)enmDomain << 8)
3039 | ((uint32_t)enmType << 10);
3040}
3041
3042
3043typedef enum
3044{
3045 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
3046 * and update the register. */
3047 kArm64InstrStLdPairType_PostIndex = 1,
3048 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
3049 * but don't update the register. */
3050 kArm64InstrStLdPairType_Signed = 2,
3051 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
3052 * and update the register. */
3053 kArm64InstrStLdPairType_PreIndex = 3
3054} ARM64INSTRSTLDPAIRTYPE;
3055
3056/**
3057 * A64: Encodes either stp (store register pair) or ldp (load register pair).
3058 *
3059 * @returns The encoded instruction.
3060 * @param fLoad true for ldp, false of stp.
3061 * @param u2Opc When @a fSimdFp is @c false:
3062 * - 0 for 32-bit GPRs (Wt).
3063 * - 1 for encoding stgp or ldpsw.
3064 * - 2 for 64-bit GRPs (Xt).
3065 * - 3 illegal.
3066 * When @a fSimdFp is @c true:
3067 * - 0 for 32-bit SIMD&FP registers (St).
3068 * - 1 for 64-bit SIMD&FP registers (Dt).
3069 * - 2 for 128-bit SIMD&FP regsiters (Qt).
3070 * @param enmType The instruction variant wrt addressing and updating of the
3071 * addressing register.
3072 * @param iReg1 The first register to store/load.
3073 * @param iReg2 The second register to store/load.
3074 * @param iBaseReg The base register to use when addressing. SP is allowed.
3075 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
3076 * will be multiplied by the register size.
3077 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
3078 * stgp/ldpsw instructions.
3079 */
3080DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
3081 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
3082 bool fSimdFp = false)
3083{
3084 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
3085 return (u2Opc << 30)
3086 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
3087 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
3088 | ((uint32_t)enmType << 23)
3089 | ((uint32_t)fLoad << 22)
3090 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
3091 | (iReg2 << 10)
3092 | (iBaseReg << 5)
3093 | iReg1;
3094}
3095
3096
3097/** A64: ldp x1, x2, [x3] */
3098DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
3099 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
3100 bool f64Bit = true)
3101{
3102 return Armv8A64MkInstrStLdPair(true /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
3103}
3104
3105
3106/** A64: stp x1, x2, [x3] */
3107DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
3108 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
3109 bool f64Bit = true)
3110{
3111 return Armv8A64MkInstrStLdPair(false /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
3112}
3113
3114
3115typedef enum /* Size VR Opc */
3116{ /* \ | / */
3117 kArmv8A64InstrLdStType_Mask_Size = 0x300,
3118 kArmv8A64InstrLdStType_Mask_VR = 0x010,
3119 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
3120 kArmv8A64InstrLdStType_Shift_Size = 8,
3121 kArmv8A64InstrLdStType_Shift_VR = 4,
3122 kArmv8A64InstrLdStType_Shift_Opc = 0,
3123
3124 kArmv8A64InstrLdStType_St_Byte = 0x000,
3125 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
3126 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
3127 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
3128
3129 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
3130 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
3131 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
3132 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
3133
3134 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
3135 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
3136 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
3137
3138 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
3139 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
3140
3141 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
3142
3143 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
3144 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
3145 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
3146 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
3147
3148 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
3149 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
3150
3151 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
3152 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
3153
3154 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
3155 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
3156
3157} ARMV8A64INSTRLDSTTYPE;
3158/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
3159#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
3160
3161
3162/**
3163 * A64: Encodes load/store with unscaled 9-bit signed immediate.
3164 *
3165 * @returns The encoded instruction.
3166 * @param u32Opcode The base opcode value.
3167 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3168 * @param iReg The register to load into / store.
3169 * @param iBaseReg The base register to use when addressing. SP is allowed.
3170 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3171 */
3172DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
3173 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3174{
3175 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
3176 return u32Opcode
3177 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3178 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3179 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3180 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
3181 | (iBaseReg << 5)
3182 | iReg;
3183}
3184
3185
3186/**
3187 * A64: Encodes load/store with unscaled 9-bit signed immediate.
3188 *
3189 * @returns The encoded instruction.
3190 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3191 * @param iReg The register to load into / store.
3192 * @param iBaseReg The base register to use when addressing. SP is allowed.
3193 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3194 */
3195DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
3196 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3197{
3198 /* 3 2 1 0 */
3199 /* 10987654321098765432109876543210 */
3200 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
3201 enmType, iReg, iBaseReg, i9ImmDisp);
3202}
3203
3204/**
3205 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
3206 *
3207 * @returns The encoded instruction.
3208 * @param enmType The load/store instruction type. Prefech not valid.
3209 * @param iReg The register to load into / store.
3210 * @param iBaseReg The base register to use when addressing. SP is allowed.
3211 * Written back.
3212 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3213 */
3214DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3215 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3216{
3217 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3218 /* 10987654321098765432109876543210 */
3219 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
3220 enmType, iReg, iBaseReg, i9ImmDisp);
3221}
3222
3223/**
3224 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
3225 *
3226 * @returns The encoded instruction.
3227 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3228 * @param iReg The register to load into / store.
3229 * @param iBaseReg The base register to use when addressing. SP is allowed.
3230 * Written back.
3231 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3232 */
3233DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3234 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3235{
3236 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3237 /* 10987654321098765432109876543210 */
3238 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
3239 enmType, iReg, iBaseReg, i9ImmDisp);
3240}
3241
3242/**
3243 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
3244 *
3245 * @returns The encoded instruction.
3246 * @param enmType The load/store instruction type. Prefech not valid,
3247 * nor any SIMD&FP variants.
3248 * @param iReg The register to load into / store.
3249 * @param iBaseReg The base register to use when addressing. SP is allowed.
3250 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3251 */
3252DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
3253 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3254{
3255 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
3256 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
3257 /* 3 2 1 0 */
3258 /* 10987654321098765432109876543210 */
3259 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
3260 enmType, iReg, iBaseReg, i9ImmDisp);
3261}
3262
3263
3264/**
3265 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
3266 *
3267 * @returns The encoded instruction.
3268 * @param enmType The load/store instruction type. Prefech not valid,
3269 * nor any SIMD&FP variants.
3270 * @param iReg The register to load into / store.
3271 * @param iBaseReg The base register to use when addressing. SP is allowed.
3272 * @param u12ImmDisp Addressing displacement, scaled by size.
3273 */
3274DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
3275 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
3276{
3277 Assert(u12ImmDisp < 4096U);
3278 Assert(iReg < 32); /* 3 2 1 0 */
3279 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3280 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
3281 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3282 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3283 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3284 | (u12ImmDisp << 10)
3285 | (iBaseReg << 5)
3286 | iReg;
3287}
3288
3289typedef enum
3290{
3291 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
3292 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
3293 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
3294 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
3295} ARMV8A64INSTRLDSTEXTEND;
3296
3297/**
3298 * A64: Encodes load/store w/ index register.
3299 *
3300 * @returns The encoded instruction.
3301 * @param enmType The load/store instruction type.
3302 * @param iReg The register to load into / store.
3303 * @param iBaseReg The base register to use when addressing. SP is allowed.
3304 * @param iRegIndex The index register.
3305 * @param enmExtend The extending to apply to @a iRegIndex.
3306 * @param fShifted Whether to shift the index. The shift amount corresponds
3307 * to the access size (thus irrelevant for byte accesses).
3308 */
3309DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
3310 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
3311 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
3312 bool fShifted = false)
3313{
3314 Assert(iRegIndex < 32);
3315 Assert(iReg < 32); /* 3 2 1 0 */
3316 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3317 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
3318 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3319 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3320 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3321 | (iRegIndex << 16)
3322 | ((uint32_t)enmExtend << 13)
3323 | ((uint32_t)fShifted << 12)
3324 | (iBaseReg << 5)
3325 | iReg;
3326}
3327
3328typedef enum /* VR Opc */
3329{ /* \ | */
3330 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
3331 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
3332 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
3333 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
3334
3335 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
3336 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
3337 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
3338 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
3339
3340 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
3341 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
3342 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
3343} ARMV8A64INSTRLDRLITTERAL;
3344
3345
3346/**
3347 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
3348 *
3349 * @returns The encoded instruction.
3350 * @param enmType The load instruction type.
3351 * @param iReg The register to load into.
3352 * @param i19Imm The signed immediate value, multiplied by 4 regardless
3353 * of access size.
3354 */
3355DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
3356{
3357 Assert(i19Imm >= -262144 && i19Imm < 262144);
3358 Assert(iReg < 32); /* 3 2 1 0 */
3359 /* 10987654321098765432109876543210 */
3360 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
3361 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
3362 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
3363 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
3364 | iReg;
3365}
3366
3367
3368typedef enum
3369{
3370 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
3371 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
3372 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
3373} ARMV8A64INSTRMOVWIDE;
3374
3375/**
3376 * A64: Encode a move wide immediate instruction.
3377 *
3378 * @returns The encoded instruction.
3379 * @param enmType The load instruction type.
3380 * @param iRegDst The register to mov the immediate into.
3381 * @param uImm16 The immediate value.
3382 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
3383 * half-words to target:
3384 * - 0 for bits 15:00,
3385 * - 1 for bits 31:16,
3386 * - 2 for bits 47:32 (f64Bit=true only),
3387 * - 3 for bits 63:48 (f64Bit=true only).
3388 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
3389 */
3390DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
3391 uint32_t iHalfWord = 0, bool f64Bit = true)
3392{
3393 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
3394 return ((uint32_t)f64Bit << 31)
3395 | ((uint32_t)enmType << 29)
3396 | UINT32_C(0x12800000)
3397 | (iHalfWord << 21)
3398 | (uImm16 << 5)
3399 | iRegDst;
3400}
3401
3402/** A64: Encodes a MOVN instruction.
3403 * @see Armv8A64MkInstrMovWide for parameter details. */
3404DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3405{
3406 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
3407}
3408
3409/** A64: Encodes a MOVZ instruction.
3410 * @see Armv8A64MkInstrMovWide for parameter details. */
3411DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3412{
3413 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
3414}
3415
3416/** A64: Encodes a MOVK instruction.
3417 * @see Armv8A64MkInstrMovWide for parameter details. */
3418DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3419{
3420 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
3421}
3422
3423
3424typedef enum
3425{
3426 kArmv8A64InstrShift_Lsl = 0,
3427 kArmv8A64InstrShift_Lsr,
3428 kArmv8A64InstrShift_Asr,
3429 kArmv8A64InstrShift_Ror
3430} ARMV8A64INSTRSHIFT;
3431
3432
3433/**
3434 * A64: Encodes a logical instruction with a shifted 2nd register operand.
3435 *
3436 * @returns The encoded instruction.
3437 * @param u2Opc The logical operation to perform.
3438 * @param fNot Whether to complement the 2nd operand.
3439 * @param iRegResult The output register.
3440 * @param iReg1 The 1st register operand.
3441 * @param iReg2Shifted The 2nd register operand, to which the optional
3442 * shifting is applied.
3443 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
3444 * GPRs.
3445 * @param offShift6 The shift amount (default: none).
3446 * @param enmShift The shift operation (default: LSL).
3447 */
3448DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
3449 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
3450 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
3451{
3452 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
3453 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
3454 return ((uint32_t)f64Bit << 31)
3455 | (u2Opc << 29)
3456 | UINT32_C(0x0a000000)
3457 | ((uint32_t)enmShift << 22)
3458 | ((uint32_t)fNot << 21)
3459 | (iReg2Shifted << 16)
3460 | (offShift6 << 10)
3461 | (iReg1 << 5)
3462 | iRegResult;
3463}
3464
3465
3466/** A64: Encodes an AND instruction.
3467 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3468DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3469 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3470{
3471 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3472}
3473
3474
3475/** A64: Encodes an BIC instruction.
3476 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3477DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3478 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3479{
3480 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3481}
3482
3483
3484/** A64: Encodes an ORR instruction.
3485 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3486DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3487 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3488{
3489 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3490}
3491
3492
3493/** A64: Encodes an MOV instruction.
3494 * This is an alias for "orr dst, xzr, src". */
3495DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
3496{
3497 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
3498}
3499
3500
3501/** A64: Encodes an ORN instruction.
3502 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3503DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3504 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3505{
3506 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3507}
3508
3509
3510/** A64: Encodes an EOR instruction.
3511 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3512DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3513 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3514{
3515 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3516}
3517
3518
3519/** A64: Encodes an EON instruction.
3520 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3521DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3522 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3523{
3524 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3525}
3526
3527
3528/** A64: Encodes an ANDS instruction.
3529 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3530DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3531 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3532{
3533 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3534}
3535
3536
3537/** A64: Encodes an BICS instruction.
3538 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3539DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3540 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3541{
3542 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3543}
3544
3545
3546
3547/*
3548 * Data processing instructions with two source register operands.
3549 */
3550
3551
3552/** A64: Encodes an SUBP instruction. */
3553DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3554{
3555 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3556 return UINT32_C(0x80000000)
3557 | UINT32_C(0x1ac00000)
3558 | (UINT32_C(0) << 10)
3559 | (iRegSubtrahend << 16)
3560 | (iRegMinuend << 5)
3561 | iRegResult;
3562}
3563
3564
3565/** A64: Encodes an SUBPS instruction. */
3566DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3567{
3568 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3569 return UINT32_C(0x80000000)
3570 | UINT32_C(0x20000000)
3571 | UINT32_C(0x1ac00000)
3572 | (UINT32_C(0) << 10)
3573 | (iRegSubtrahend << 16)
3574 | (iRegMinuend << 5)
3575 | iRegResult;
3576}
3577
3578
3579/** A64: Encodes an UDIV instruction. */
3580DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3581{
3582 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3583 return ((uint32_t)f64Bit << 31)
3584 | UINT32_C(0x1ac00000)
3585 | (UINT32_C(2) << 10)
3586 | (iRegDivisor << 16)
3587 | (iRegDividend << 5)
3588 | iRegResult;
3589}
3590
3591
3592/** A64: Encodes an SDIV instruction. */
3593DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3594{
3595 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3596 return ((uint32_t)f64Bit << 31)
3597 | UINT32_C(0x1ac00000)
3598 | (UINT32_C(3) << 10)
3599 | (iRegDivisor << 16)
3600 | (iRegDividend << 5)
3601 | iRegResult;
3602}
3603
3604
3605/** A64: Encodes an IRG instruction. */
3606DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3607{
3608 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3609 return UINT32_C(0x80000000)
3610 | UINT32_C(0x1ac00000)
3611 | (UINT32_C(4) << 10)
3612 | (iRegSrc2 << 16)
3613 | (iRegSrc1 << 5)
3614 | iRegResult;
3615}
3616
3617
3618/** A64: Encodes a GMI instruction. */
3619DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3620{
3621 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3622 return UINT32_C(0x80000000)
3623 | UINT32_C(0x1ac00000)
3624 | (UINT32_C(5) << 10)
3625 | (iRegSrc2 << 16)
3626 | (iRegSrc1 << 5)
3627 | iRegResult;
3628}
3629
3630
3631/** A64: Encodes an LSLV instruction. */
3632DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3633{
3634 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3635 return ((uint32_t)f64Bit << 31)
3636 | UINT32_C(0x1ac00000)
3637 | (UINT32_C(8) << 10)
3638 | (iRegCount << 16)
3639 | (iRegSrc << 5)
3640 | iRegResult;
3641}
3642
3643
3644/** A64: Encodes an LSRV instruction. */
3645DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3646{
3647 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3648 return ((uint32_t)f64Bit << 31)
3649 | UINT32_C(0x1ac00000)
3650 | (UINT32_C(9) << 10)
3651 | (iRegCount << 16)
3652 | (iRegSrc << 5)
3653 | iRegResult;
3654}
3655
3656
3657/** A64: Encodes an ASRV instruction. */
3658DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3659{
3660 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3661 return ((uint32_t)f64Bit << 31)
3662 | UINT32_C(0x1ac00000)
3663 | (UINT32_C(10) << 10)
3664 | (iRegCount << 16)
3665 | (iRegSrc << 5)
3666 | iRegResult;
3667}
3668
3669
3670/** A64: Encodes a RORV instruction. */
3671DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3672{
3673 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3674 return ((uint32_t)f64Bit << 31)
3675 | UINT32_C(0x1ac00000)
3676 | (UINT32_C(11) << 10)
3677 | (iRegCount << 16)
3678 | (iRegSrc << 5)
3679 | iRegResult;
3680}
3681
3682
3683/** A64: Encodes a PACGA instruction. */
3684DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3685{
3686 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3687 return UINT32_C(0x80000000)
3688 | UINT32_C(0x1ac00000)
3689 | (UINT32_C(12) << 10)
3690 | (iRegSrc2 << 16)
3691 | (iRegSrc1 << 5)
3692 | iRegResult;
3693}
3694
3695
3696/** A64: Encodes a CRC32* instruction. */
3697DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3698{
3699 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3700 return ((uint32_t)(uSize == 3) << 31)
3701 | UINT32_C(0x1ac00000)
3702 | (UINT32_C(16) << 10)
3703 | (uSize << 10)
3704 | (iRegValue << 16)
3705 | (iRegCrc << 5)
3706 | iRegResult;
3707}
3708
3709
3710/** A64: Encodes a CRC32B instruction. */
3711DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3712{
3713 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
3714}
3715
3716
3717/** A64: Encodes a CRC32H instruction. */
3718DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3719{
3720 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
3721}
3722
3723
3724/** A64: Encodes a CRC32W instruction. */
3725DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3726{
3727 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
3728}
3729
3730
3731/** A64: Encodes a CRC32X instruction. */
3732DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3733{
3734 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
3735}
3736
3737
3738/** A64: Encodes a CRC32C* instruction. */
3739DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3740{
3741 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3742 return ((uint32_t)(uSize == 3) << 31)
3743 | UINT32_C(0x1ac00000)
3744 | (UINT32_C(20) << 10)
3745 | (uSize << 10)
3746 | (iRegValue << 16)
3747 | (iRegCrc << 5)
3748 | iRegResult;
3749}
3750
3751
3752/** A64: Encodes a CRC32B instruction. */
3753DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3754{
3755 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
3756}
3757
3758
3759/** A64: Encodes a CRC32CH instruction. */
3760DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3761{
3762 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
3763}
3764
3765
3766/** A64: Encodes a CRC32CW instruction. */
3767DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3768{
3769 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
3770}
3771
3772
3773/** A64: Encodes a CRC32CX instruction. */
3774DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3775{
3776 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
3777}
3778
3779
3780/** A64: Encodes an SMAX instruction. */
3781DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3782{
3783 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3784 return ((uint32_t)f64Bit << 31)
3785 | UINT32_C(0x1ac00000)
3786 | (UINT32_C(24) << 10)
3787 | (iRegSrc2 << 16)
3788 | (iRegSrc1 << 5)
3789 | iRegResult;
3790}
3791
3792
3793/** A64: Encodes an UMAX instruction. */
3794DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3795{
3796 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3797 return ((uint32_t)f64Bit << 31)
3798 | UINT32_C(0x1ac00000)
3799 | (UINT32_C(25) << 10)
3800 | (iRegSrc2 << 16)
3801 | (iRegSrc1 << 5)
3802 | iRegResult;
3803}
3804
3805
3806/** A64: Encodes an SMIN instruction. */
3807DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3808{
3809 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3810 return ((uint32_t)f64Bit << 31)
3811 | UINT32_C(0x1ac00000)
3812 | (UINT32_C(26) << 10)
3813 | (iRegSrc2 << 16)
3814 | (iRegSrc1 << 5)
3815 | iRegResult;
3816}
3817
3818
3819/** A64: Encodes an UMIN instruction. */
3820DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3821{
3822 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3823 return ((uint32_t)f64Bit << 31)
3824 | UINT32_C(0x1ac00000)
3825 | (UINT32_C(27) << 10)
3826 | (iRegSrc2 << 16)
3827 | (iRegSrc1 << 5)
3828 | iRegResult;
3829}
3830
3831
3832# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
3833
3834/**
3835 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
3836 *
3837 * @returns The decoded mask.
3838 * @param uImm6SizeLen The immS value from the instruction. (No N part
3839 * here, as that must be zero for instructions
3840 * operating on 32-bit wide registers.)
3841 * @param uImm6Rotations The immR value from the instruction.
3842 */
3843DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3844{
3845 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
3846
3847 /* Determine the element size. */
3848 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
3849 Assert(cBitsElementLog2 + 1U != 0U);
3850
3851 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3852 Assert(uImm6Rotations < cBitsElement);
3853
3854 /* Extract the number of bits set to 1: */
3855 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
3856 Assert(cBitsSetTo1 < cBitsElement);
3857 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
3858
3859 /* Produce the unrotated pattern. */
3860 static const uint32_t s_auReplicate[]
3861 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3862 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3863
3864 /* Rotate it and return. */
3865 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
3866}
3867
3868
3869/**
3870 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
3871 *
3872 * @returns The decoded mask.
3873 * @param uImm7SizeLen The N:immS value from the instruction.
3874 * @param uImm6Rotations The immR value from the instruction.
3875 */
3876DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
3877{
3878 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
3879
3880 /* Determine the element size. */
3881 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
3882 Assert(cBitsElementLog2 + 1U != 0U);
3883
3884 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3885 Assert(uImm6Rotations < cBitsElement);
3886
3887 /* Extract the number of bits set to 1: */
3888 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
3889 Assert(cBitsSetTo1 < cBitsElement);
3890 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
3891
3892 /* Produce the unrotated pattern. */
3893 static const uint64_t s_auReplicate[]
3894 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3895 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3896
3897 /* Rotate it and return. */
3898 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
3899}
3900
3901
3902/**
3903 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
3904 * the immS value.
3905 */
3906DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3907{
3908 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
3909}
3910
3911
3912/**
3913 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3914 * 32-bit bitmask to a set of immediates for those instructions.
3915 *
3916 * @returns true if successful, false if not.
3917 * @param fMask The mask value to convert.
3918 * @param puImm6SizeLen Where to return the immS part (N is always zero for
3919 * 32-bit wide masks).
3920 * @param puImm6Rotations Where to return the immR.
3921 */
3922DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
3923{
3924 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
3925 if ((uint32_t)(fMask + 1U) <= 1)
3926 return false;
3927
3928 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3929 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
3930 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
3931 if (cRor)
3932 fMask = ASMRotateRightU32(fMask, cRor);
3933 else
3934 fMask = ASMRotateLeftU32(fMask, cRol);
3935 Assert(fMask & RT_BIT_32(0));
3936 Assert(!(fMask & RT_BIT_32(31)));
3937
3938 /* Count the trailing ones and leading zeros. */
3939 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
3940 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
3941
3942 /* The potential element length is then the sum of the two above. */
3943 unsigned const cBitsElement = cOnes + cZeros;
3944 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3945 return false;
3946
3947 /* Special case: 32 bits element size. Since we're done here. */
3948 if (cBitsElement == 32)
3949 *puImm6SizeLen = cOnes - 1;
3950 else
3951 {
3952 /* Extract the element bits and check that these are replicated in the whole pattern. */
3953 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
3954 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
3955
3956 static const uint32_t s_auReplicate[]
3957 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3958 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3959 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3960 else
3961 return false;
3962 }
3963 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3964
3965 return true;
3966}
3967
3968
3969/**
3970 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3971 * 64-bit bitmask to a set of immediates for those instructions.
3972 *
3973 * @returns true if successful, false if not.
3974 * @param fMask The mask value to convert.
3975 * @param puImm7SizeLen Where to return the N:immS part.
3976 * @param puImm6Rotations Where to return the immR.
3977 */
3978DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
3979{
3980 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
3981 if ((uint64_t)(fMask + 1U) <= 1)
3982 return false;
3983
3984 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3985 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
3986 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
3987 if (cRor)
3988 fMask = ASMRotateRightU64(fMask, cRor);
3989 else
3990 fMask = ASMRotateLeftU64(fMask, cRol);
3991 Assert(fMask & RT_BIT_64(0));
3992 Assert(!(fMask & RT_BIT_64(63)));
3993
3994 /* Count the trailing ones and leading zeros. */
3995 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
3996 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
3997
3998 /* The potential element length is then the sum of the two above. */
3999 unsigned const cBitsElement = cOnes + cZeros;
4000 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
4001 return false;
4002
4003 /* Special case: 64 bits element size. Since we're done here. */
4004 if (cBitsElement == 64)
4005 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
4006 else
4007 {
4008 /* Extract the element bits and check that these are replicated in the whole pattern. */
4009 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
4010 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
4011
4012 static const uint64_t s_auReplicate[]
4013 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
4014 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
4015 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
4016 else
4017 return false;
4018 }
4019 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
4020
4021 return true;
4022}
4023
4024# endif /* IPRT_INCLUDED_asm_h */
4025
4026/**
4027 * A64: Encodes a logical instruction with an complicated immediate mask.
4028 *
4029 * The @a uImm7SizeLen parameter specifies two things:
4030 * 1. the element size and
4031 * 2. the number of bits set to 1 in the pattern.
4032 *
4033 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
4034 * top) and using the position of the first bit set as a power of two.
4035 *
4036 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
4037 * |---|---|---|---|---|---|---|--------------|
4038 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
4039 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
4040 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
4041 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
4042 * | 0 | 0 | x | x | x | x | x | 32 bits |
4043 * | 1 | x | x | x | x | x | x | 64 bits |
4044 *
4045 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
4046 * there is always one zero bit in the pattern).
4047 *
4048 * The @a uImm6Rotations parameter specifies how many bits to the right,
4049 * the element pattern is rotated. The rotation count must be less than the
4050 * element bit count (size).
4051 *
4052 * @returns The encoded instruction.
4053 * @param u2Opc The logical operation to perform.
4054 * @param iRegResult The output register.
4055 * @param iRegSrc The 1st register operand.
4056 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
4057 * field at the top of the 6-bit 'imms' field.
4058 *
4059 * @param uImm6Rotations The rotation count.
4060 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
4061 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
4062 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
4063 */
4064DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
4065 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
4066{
4067 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x3f)));
4068 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
4069 return ((uint32_t)f64Bit << 31)
4070 | (u2Opc << 29)
4071 | UINT32_C(0x12000000)
4072 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
4073 | (uImm6Rotations << 16)
4074 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
4075 | (iRegSrc << 5)
4076 | iRegResult;
4077}
4078
4079
4080/** A64: Encodes an AND instruction w/ complicated immediate mask.
4081 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4082DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
4083 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4084{
4085 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4086}
4087
4088
4089/** A64: Encodes an ORR instruction w/ complicated immediate mask.
4090 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4091DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
4092 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4093{
4094 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4095}
4096
4097
4098/** A64: Encodes an EOR instruction w/ complicated immediate mask.
4099 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4100DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
4101 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4102{
4103 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4104}
4105
4106
4107/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
4108 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4109DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
4110 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4111{
4112 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4113}
4114
4115
4116/** A64: Encodes an TST instruction w/ complicated immediate mask.
4117 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4118DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
4119 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4120{
4121 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4122}
4123
4124
4125/**
4126 * A64: Encodes a bitfield instruction.
4127 *
4128 * @returns The encoded instruction.
4129 * @param u2Opc The bitfield operation to perform.
4130 * @param iRegResult The output register.
4131 * @param iRegSrc The 1st register operand.
4132 * @param cImm6Ror The right rotation count.
4133 * @param uImm6S The leftmost bit to be moved.
4134 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
4135 * @param uN1 This must match @a f64Bit for all instructions
4136 * currently specified.
4137 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
4138 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
4139 */
4140DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
4141 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
4142{
4143 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
4144 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
4145 return ((uint32_t)f64Bit << 31)
4146 | (u2Opc << 29)
4147 | UINT32_C(0x13000000)
4148 | (uN1 << 22)
4149 | (cImm6Ror << 16)
4150 | (uImm6S << 10)
4151 | (iRegSrc << 5)
4152 | iRegResult;
4153}
4154
4155
4156/** A64: Encodes a SBFM instruction.
4157 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4158DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4159 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4160{
4161 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4162}
4163
4164
4165/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
4166 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4167DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
4168{
4169 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
4170}
4171
4172
4173/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
4174 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4175DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
4176{
4177 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
4178}
4179
4180
4181/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
4182 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4183DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
4184{
4185 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
4186}
4187
4188
4189/** A64: Encodes an ASR instruction w/ immediate shift value.
4190 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4191DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4192{
4193 uint32_t const cWidth = f64Bit ? 63 : 31;
4194 Assert(cShift > 0); Assert(cShift <= cWidth);
4195 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
4196}
4197
4198
4199/** A64: Encodes a BFM instruction.
4200 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4201DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4202 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4203{
4204 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4205}
4206
4207
4208/** A64: Encodes a BFI instruction (insert).
4209 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4210DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
4211 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4212{
4213 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4214 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
4215 cBitsWidth - 1, f64Bit);
4216}
4217
4218
4219/** A64: Encodes a BFC instruction (clear).
4220 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4221DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfc(uint32_t iRegResult,
4222 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4223{
4224 return Armv8A64MkInstrBfi(iRegResult, ARMV8_A64_REG_XZR, offFirstBit, cBitsWidth, f64Bit);
4225}
4226
4227
4228/** A64: Encodes a BFXIL instruction (insert low).
4229 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4230DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfxil(uint32_t iRegResult, uint32_t iRegSrc,
4231 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4232{
4233 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4234 Assert(offFirstBit + cBitsWidth <= (f64Bit ? 64U : 32U));
4235 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4236}
4237
4238
4239/** A64: Encodes an UBFM instruction.
4240 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4241DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4242 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4243{
4244 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4245}
4246
4247
4248/** A64: Encodes an UBFX instruction (zero extending extract).
4249 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4250DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
4251 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4252{
4253 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4254}
4255
4256
4257/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
4258 * shifted into destination).
4259 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4260DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
4261 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
4262{
4263 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
4264 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
4265}
4266
4267
4268/** A64: Encodes an LSL instruction w/ immediate shift value.
4269 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4270DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4271{
4272 uint32_t const cWidth = f64Bit ? 63 : 31;
4273 Assert(cShift > 0); Assert(cShift <= cWidth);
4274 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
4275 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
4276}
4277
4278
4279/** A64: Encodes an LSR instruction w/ immediate shift value.
4280 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4281DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4282{
4283 uint32_t const cWidth = f64Bit ? 63 : 31;
4284 Assert(cShift > 0); Assert(cShift <= cWidth);
4285 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
4286}
4287
4288
4289/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
4290 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4291DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4292{
4293 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
4294}
4295
4296
4297/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
4298 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4299DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4300{
4301 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
4302}
4303
4304
4305/**
4306 * A64: Encodes an EXTR instruction with an immediate.
4307 *
4308 * @returns The encoded instruction.
4309 * @param iRegResult The register to store the result in. ZR is valid.
4310 * @param iRegLow The register holding the least significant bits in the
4311 * extraction. ZR is valid.
4312 * @param iRegHigh The register holding the most significant bits in the
4313 * extraction. ZR is valid.
4314 * @param uLsb The bit number of the least significant bit, or where in
4315 * @a iRegLow to start the
4316 * extraction.
4317 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4318 */
4319DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
4320 bool f64Bit = true)
4321{
4322 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
4323 return ((uint32_t)f64Bit << 31)
4324 | UINT32_C(0x13800000)
4325 | ((uint32_t)f64Bit << 22) /*N*/
4326 | (iRegHigh << 16)
4327 | (uLsb << 10)
4328 | (iRegLow << 5)
4329 | iRegResult;
4330}
4331
4332
4333/** A64: Rotates the value of a register (alias for EXTR). */
4334DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4335{
4336 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
4337}
4338
4339
4340/**
4341 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
4342 *
4343 * @returns The encoded instruction.
4344 * @param fSub true for sub and subs, false for add and
4345 * adds.
4346 * @param iRegResult The register to store the result in.
4347 * SP is valid when @a fSetFlags = false,
4348 * and ZR is valid otherwise.
4349 * @param iRegSrc The register containing the augend (@a fSub
4350 * = false) or minuend (@a fSub = true). SP is
4351 * a valid registers for all variations.
4352 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
4353 * (@a fSub = true).
4354 * @param f64Bit true for 64-bit GRPs (default), false for
4355 * 32-bit GPRs.
4356 * @param fSetFlags Whether to set flags (adds / subs) or not
4357 * (add / sub - default).
4358 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
4359 * bits to the left, or not (default).
4360 */
4361DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
4362 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
4363 bool fSetFlags = false, bool fShift12 = false)
4364{
4365 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
4366 return ((uint32_t)f64Bit << 31)
4367 | ((uint32_t)fSub << 30)
4368 | ((uint32_t)fSetFlags << 29)
4369 | UINT32_C(0x11000000)
4370 | ((uint32_t)fShift12 << 22)
4371 | (uImm12AddendSubtrahend << 10)
4372 | (iRegSrc << 5)
4373 | iRegResult;
4374}
4375
4376
4377/** Alias for sub zxr, reg, \#uimm12. */
4378DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
4379 bool f64Bit = true, bool fShift12 = false)
4380{
4381 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
4382 f64Bit, true /*fSetFlags*/, fShift12);
4383}
4384
4385
4386/** ADD dst, src, \#uimm12 */
4387DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
4388 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4389{
4390 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
4391}
4392
4393
4394/** SUB dst, src, \#uimm12 */
4395DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
4396 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4397{
4398 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
4399}
4400
4401
4402/**
4403 * A64: Encodes either add, adds, sub or subs with shifted register.
4404 *
4405 * @returns The encoded instruction.
4406 * @param fSub true for sub and subs, false for add and
4407 * adds.
4408 * @param iRegResult The register to store the result in.
4409 * SP is NOT valid, but ZR is.
4410 * @param iRegSrc1 The register containing the augend (@a fSub
4411 * = false) or minuend (@a fSub = true).
4412 * SP is NOT valid, but ZR is.
4413 * @param iRegSrc2 The register containing the addened (@a fSub
4414 * = false) or subtrahend (@a fSub = true).
4415 * SP is NOT valid, but ZR is.
4416 * @param f64Bit true for 64-bit GRPs (default), false for
4417 * 32-bit GPRs.
4418 * @param fSetFlags Whether to set flags (adds / subs) or not
4419 * (add / sub - default).
4420 * @param cShift The shift count to apply to @a iRegSrc2.
4421 * @param enmShift The shift type to apply to the @a iRegSrc2
4422 * register. kArmv8A64InstrShift_Ror is
4423 * reserved.
4424 */
4425DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4426 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4427 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4428{
4429 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4430 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
4431
4432 return ((uint32_t)f64Bit << 31)
4433 | ((uint32_t)fSub << 30)
4434 | ((uint32_t)fSetFlags << 29)
4435 | UINT32_C(0x0b000000)
4436 | ((uint32_t)enmShift << 22)
4437 | (iRegSrc2 << 16)
4438 | (cShift << 10)
4439 | (iRegSrc1 << 5)
4440 | iRegResult;
4441}
4442
4443
4444/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
4445DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
4446 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4447{
4448 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
4449 f64Bit, true /*fSetFlags*/, cShift, enmShift);
4450}
4451
4452
4453/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4454DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4455 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4456 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4457{
4458 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4459}
4460
4461
4462/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4463DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4464 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4465 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4466{
4467 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4468}
4469
4470
4471/** NEG dst */
4472DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
4473{
4474 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
4475}
4476
4477
4478/** Extension option for 'extended register' instructions. */
4479typedef enum ARMV8A64INSTREXTEND
4480{
4481 kArmv8A64InstrExtend_UxtB = 0,
4482 kArmv8A64InstrExtend_UxtH,
4483 kArmv8A64InstrExtend_UxtW,
4484 kArmv8A64InstrExtend_UxtX,
4485 kArmv8A64InstrExtend_SxtB,
4486 kArmv8A64InstrExtend_SxtH,
4487 kArmv8A64InstrExtend_SxtW,
4488 kArmv8A64InstrExtend_SxtX,
4489 /** The default is either UXTW or UXTX depending on whether the instruction
4490 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
4491 * to the f64Bit value. */
4492 kArmv8A64InstrExtend_Default
4493} ARMV8A64INSTREXTEND;
4494
4495
4496/**
4497 * A64: Encodes either add, adds, sub or subs with extended register encoding.
4498 *
4499 * @returns The encoded instruction.
4500 * @param fSub true for sub and subs, false for add and
4501 * adds.
4502 * @param iRegResult The register to store the result in.
4503 * SP is NOT valid, but ZR is.
4504 * @param iRegSrc1 The register containing the augend (@a fSub
4505 * = false) or minuend (@a fSub = true).
4506 * SP is valid, but ZR is NOT.
4507 * @param iRegSrc2 The register containing the addened (@a fSub
4508 * = false) or subtrahend (@a fSub = true).
4509 * SP is NOT valid, but ZR is.
4510 * @param f64Bit true for 64-bit GRPs (default), false for
4511 * 32-bit GPRs.
4512 * @param fSetFlags Whether to set flags (adds / subs) or not
4513 * (add / sub - default).
4514 * @param enmExtend The type of extension to apply to @a
4515 * iRegSrc2.
4516 * @param cShift The left shift count to apply to @a iRegSrc2
4517 * after enmExtend processing is done.
4518 * Max shift is 4 for some reason.
4519 */
4520DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4521 bool f64Bit = true, bool fSetFlags = false,
4522 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
4523 uint32_t cShift = 0)
4524{
4525 if (enmExtend == kArmv8A64InstrExtend_Default)
4526 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
4527 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
4528
4529 return ((uint32_t)f64Bit << 31)
4530 | ((uint32_t)fSub << 30)
4531 | ((uint32_t)fSetFlags << 29)
4532 | UINT32_C(0x0b200000)
4533 | (iRegSrc2 << 16)
4534 | ((uint32_t)enmExtend << 13)
4535 | (cShift << 10)
4536 | (iRegSrc1 << 5)
4537 | iRegResult;
4538}
4539
4540
4541/**
4542 * A64: Encodes either adc, adcs, sbc or sbcs with two source registers.
4543 *
4544 * @returns The encoded instruction.
4545 * @param fSub true for sbc and sbcs, false for adc and
4546 * adcs.
4547 * @param iRegResult The register to store the result in. SP is
4548 * NOT valid, but ZR is.
4549 * @param iRegSrc1 The register containing the augend (@a fSub
4550 * = false) or minuend (@a fSub = true).
4551 * SP is NOT valid, but ZR is.
4552 * @param iRegSrc2 The register containing the addened (@a fSub
4553 * = false) or subtrahend (@a fSub = true).
4554 * SP is NOT valid, but ZR is.
4555 * @param f64Bit true for 64-bit GRPs (default), false for
4556 * 32-bit GPRs.
4557 * @param fSetFlags Whether to set flags (adds / subs) or not
4558 * (add / sub - default).
4559 */
4560DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcSbc(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4561 bool f64Bit = true, bool fSetFlags = false)
4562{
4563 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4564
4565 return ((uint32_t)f64Bit << 31)
4566 | ((uint32_t)fSub << 30)
4567 | ((uint32_t)fSetFlags << 29)
4568 | UINT32_C(0x1a000000)
4569 | (iRegSrc2 << 16)
4570 | (iRegSrc1 << 5)
4571 | iRegResult;
4572}
4573
4574
4575/** ADC dst, reg1, reg2 */
4576DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4577 bool f64Bit = true, bool fSetFlags = false)
4578{
4579 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4580}
4581
4582
4583/** ADCS dst, reg1, reg2 */
4584DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4585{
4586 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4587}
4588
4589
4590/** SBC dst, reg1, reg2 */
4591DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4592 bool f64Bit = true, bool fSetFlags = false)
4593{
4594 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4595}
4596
4597
4598/** SBCS dst, reg1, reg2 */
4599DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4600{
4601 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4602}
4603
4604
4605/**
4606 * A64: Encodes a B (unconditional branch w/ imm) instruction.
4607 *
4608 * @returns The encoded instruction.
4609 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4610 */
4611DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
4612{
4613 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
4614 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
4615}
4616
4617
4618/**
4619 * A64: Encodes a BL (unconditional call w/ imm) instruction.
4620 *
4621 * @returns The encoded instruction.
4622 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4623 */
4624DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
4625{
4626 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
4627}
4628
4629
4630/**
4631 * A64: Encodes a BR (unconditional branch w/ register) instruction.
4632 *
4633 * @returns The encoded instruction.
4634 * @param iReg The register containing the target address.
4635 */
4636DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
4637{
4638 Assert(iReg < 32);
4639 return UINT32_C(0xd61f0000) | (iReg << 5);
4640}
4641
4642
4643/**
4644 * A64: Encodes a BLR instruction.
4645 *
4646 * @returns The encoded instruction.
4647 * @param iReg The register containing the target address.
4648 */
4649DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
4650{
4651 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
4652}
4653
4654
4655/**
4656 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
4657 *
4658 * @returns The encoded instruction.
4659 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4660 * its not zero.
4661 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4662 * @param iReg The GPR to check for zero / non-zero value.
4663 * @param f64Bit true for 64-bit register, false for 32-bit.
4664 */
4665DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4666{
4667 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
4668 return ((uint32_t)f64Bit << 31)
4669 | UINT32_C(0x34000000)
4670 | ((uint32_t)fJmpIfNotZero << 24)
4671 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4672 | iReg;
4673}
4674
4675
4676/** A64: Encodes the CBZ instructions. */
4677DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4678{
4679 return Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4680}
4681
4682
4683/** A64: Encodes the CBNZ instructions. */
4684DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbnz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4685{
4686 return Armv8A64MkInstrCbzCbnz(true /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4687}
4688
4689
4690/**
4691 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
4692 *
4693 * @returns The encoded instruction.
4694 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4695 * its not zero.
4696 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4697 * @param iReg The GPR to check for zero / non-zero value.
4698 * @param iBitNo The bit to test for.
4699 */
4700DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4701{
4702 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
4703 return ((uint32_t)(iBitNo & 0x20) << (31-5))
4704 | UINT32_C(0x36000000)
4705 | ((uint32_t)fJmpIfNotZero << 24)
4706 | ((iBitNo & 0x1f) << 19)
4707 | (((uint32_t)iImm14 & 0x3fff) << 5)
4708 | iReg;
4709}
4710
4711
4712/**
4713 * A64: Encodes TBZ (conditional branch w/ immediate) instructions.
4714 *
4715 * @returns The encoded instruction.
4716 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4717 * @param iReg The GPR to check for zero / non-zero value.
4718 * @param iBitNo The bit to test for.
4719 */
4720DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4721{
4722 return Armv8A64MkInstrTbzTbnz(false /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4723}
4724
4725
4726/**
4727 * A64: Encodes TBNZ (conditional branch w/ immediate) instructions.
4728 *
4729 * @returns The encoded instruction.
4730 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4731 * @param iReg The GPR to check for zero / non-zero value.
4732 * @param iBitNo The bit to test for.
4733 */
4734DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbnz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4735{
4736 return Armv8A64MkInstrTbzTbnz(true /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4737}
4738
4739
4740
4741/** Armv8 Condition codes. */
4742typedef enum ARMV8INSTRCOND
4743{
4744 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
4745 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
4746
4747 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
4748 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
4749 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
4750 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
4751
4752 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
4753 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
4754
4755 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
4756 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
4757
4758 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
4759 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
4760
4761 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
4762 kArmv8InstrCond_Lt, /**< b - Signed less than. */
4763
4764 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
4765 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
4766
4767 kArmv8InstrCond_Al, /**< e - Condition is always true. */
4768 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
4769} ARMV8INSTRCOND;
4770
4771/**
4772 * A64: Encodes conditional branch instruction w/ immediate target.
4773 *
4774 * @returns The encoded instruction.
4775 * @param enmCond The branch condition.
4776 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4777 */
4778DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
4779{
4780 Assert((unsigned)enmCond < 16);
4781 return UINT32_C(0x54000000)
4782 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4783 | (uint32_t)enmCond;
4784}
4785
4786
4787/**
4788 * A64: Encodes the BRK instruction.
4789 *
4790 * @returns The encoded instruction.
4791 * @param uImm16 Unsigned immediate value.
4792 */
4793DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
4794{
4795 Assert(uImm16 < _64K);
4796 return UINT32_C(0xd4200000)
4797 | (uImm16 << 5);
4798}
4799
4800/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
4801 * @{ */
4802#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
4803#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
4804#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
4805#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
4806#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
4807#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
4808#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
4809#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
4810
4811#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
4812#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
4813#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
4814#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
4815#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
4816#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
4817#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
4818#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
4819/** @} */
4820
4821/**
4822 * A64: Encodes CCMP or CCMN with two register operands.
4823 *
4824 * @returns The encoded instruction.
4825 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
4826 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
4827 * @param fNzcv The N, Z, C & V flags values to load if the condition
4828 * does not match. See RMA64_NZCV_F_XXX.
4829 * @param enmCond The condition guarding the compare.
4830 * @param fCCmp Set for CCMP (default), clear for CCMN.
4831 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4832 */
4833DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4834 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
4835{
4836 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
4837
4838 return ((uint32_t)f64Bit << 31)
4839 | ((uint32_t)fCCmp << 30)
4840 | UINT32_C(0x3a400000)
4841 | (iRegSrc2 << 16)
4842 | ((uint32_t)enmCond << 12)
4843 | (iRegSrc1 << 5)
4844 | fNzcv;
4845}
4846
4847/** CCMP w/ reg. */
4848DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4849 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4850{
4851 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4852}
4853
4854
4855/** CCMN w/ reg. */
4856DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4857 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4858{
4859 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4860}
4861
4862
4863/**
4864 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
4865 *
4866 * @returns The encoded instruction.
4867 * @param iRegSrc The register. SP is NOT valid, but ZR is.
4868 * @param uImm5 The immediate, to compare iRegSrc with.
4869 * @param fNzcv The N, Z, C & V flags values to load if the condition
4870 * does not match. See RMA64_NZCV_F_XXX.
4871 * @param enmCond The condition guarding the compare.
4872 * @param fCCmp Set for CCMP (default), clear for CCMN.
4873 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4874 */
4875DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
4876 bool fCCmp = true, bool f64Bit = true)
4877{
4878 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
4879
4880 return ((uint32_t)f64Bit << 31)
4881 | ((uint32_t)fCCmp << 30)
4882 | UINT32_C(0x3a400800)
4883 | (uImm5 << 16)
4884 | ((uint32_t)enmCond << 12)
4885 | (iRegSrc << 5)
4886 | fNzcv;
4887}
4888
4889/** CCMP w/ immediate. */
4890DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4891 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4892{
4893 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4894}
4895
4896
4897/** CCMN w/ immediate. */
4898DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4899 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4900{
4901 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4902}
4903
4904
4905/**
4906 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
4907 *
4908 * @returns The encoded instruction.
4909 * @param uOp Opcode bit 30.
4910 * @param uOp2 Opcode bits 11:10.
4911 * @param iRegResult The result register. SP is NOT valid, but ZR is.
4912 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
4913 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
4914 * @param enmCond The condition guarding the compare.
4915 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4916 */
4917DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
4918 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4919{
4920 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4921
4922 return ((uint32_t)f64Bit << 31)
4923 | (uOp << 30)
4924 | UINT32_C(0x1a800000)
4925 | (iRegSrc2 << 16)
4926 | ((uint32_t)enmCond << 12)
4927 | (uOp2 << 10)
4928 | (iRegSrc1 << 5)
4929 | iRegResult;
4930}
4931
4932
4933/** A64: Encodes CSEL.
4934 * @see Armv8A64MkInstrCondSelect for details. */
4935DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4936 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4937{
4938 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4939}
4940
4941
4942/** A64: Encodes CSINC.
4943 * @see Armv8A64MkInstrCondSelect for details. */
4944DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4945 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4946{
4947 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4948}
4949
4950
4951/** A64: Encodes CSET.
4952 * @see Armv8A64MkInstrCondSelect for details. */
4953DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4954{
4955 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4956 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4957 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4958}
4959
4960
4961/** A64: Encodes CSINV.
4962 * @see Armv8A64MkInstrCondSelect for details. */
4963DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4964 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4965{
4966 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4967}
4968
4969/** A64: Encodes CSETM.
4970 * @see Armv8A64MkInstrCondSelect for details. */
4971DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4972{
4973 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4974 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4975 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4976}
4977
4978
4979/** A64: Encodes CSNEG.
4980 * @see Armv8A64MkInstrCondSelect for details. */
4981DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4982 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4983{
4984 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4985}
4986
4987
4988/**
4989 * A64: Encodes REV instruction.
4990 *
4991 * @returns The encoded instruction.
4992 * @param iRegDst The destination register. SP is NOT valid.
4993 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4994 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4995 */
4996DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4997{
4998 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4999
5000 return ((uint32_t)f64Bit << 31)
5001 | UINT32_C(0x5ac00800)
5002 | ((uint32_t)f64Bit << 10)
5003 | (iRegSrc << 5)
5004 | iRegDst;
5005}
5006
5007
5008/**
5009 * A64: Encodes REV16 instruction.
5010 *
5011 * @returns The encoded instruction.
5012 * @param iRegDst The destination register. SP is NOT valid.
5013 * @param iRegSrc The source register. SP is NOT valid, but ZR is
5014 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
5015 */
5016DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
5017{
5018 Assert(iRegDst < 32); Assert(iRegSrc < 32);
5019
5020 return ((uint32_t)f64Bit << 31)
5021 | UINT32_C(0x5ac00400)
5022 | (iRegSrc << 5)
5023 | iRegDst;
5024}
5025
5026
5027/**
5028 * A64: Encodes SETF8 & SETF16.
5029 *
5030 * @returns The encoded instruction.
5031 * @param iRegResult The register holding the result. SP is NOT valid.
5032 * @param f16Bit Set for SETF16, clear for SETF8.
5033 */
5034DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
5035{
5036 Assert(iRegResult < 32);
5037
5038 return UINT32_C(0x3a00080d)
5039 | ((uint32_t)f16Bit << 14)
5040 | (iRegResult << 5);
5041}
5042
5043
5044/**
5045 * A64: Encodes RMIF.
5046 *
5047 * @returns The encoded instruction.
5048 * @param iRegSrc The source register to get flags from.
5049 * @param cRotateRight The right rotate count (LSB bit offset).
5050 * @param fMask Mask of which flag bits to set:
5051 * - bit 0: V
5052 * - bit 1: C
5053 * - bit 2: Z
5054 * - bit 3: N
5055 */
5056DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRmif(uint32_t iRegSrc, uint32_t cRotateRight, uint32_t fMask)
5057{
5058 Assert(iRegSrc < 32); Assert(cRotateRight < 64); Assert(fMask <= 0xf);
5059
5060 return UINT32_C(0xba000400)
5061 | (cRotateRight << 15)
5062 | (iRegSrc << 5)
5063 | fMask;
5064}
5065
5066
5067/**
5068 * A64: Encodes MRS (for reading a system register into a GPR).
5069 *
5070 * @returns The encoded instruction.
5071 * @param iRegDst The register to put the result into. SP is NOT valid.
5072 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
5073 * IPRT specific format, of the register to read.
5074 */
5075DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
5076{
5077 Assert(iRegDst < 32);
5078 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
5079
5080 /* Note. The top bit of idSysReg must always be set and is also set in
5081 0xd5300000, otherwise we'll be encoding a different instruction. */
5082 return UINT32_C(0xd5300000)
5083 | (idSysReg << 5)
5084 | iRegDst;
5085}
5086
5087
5088/**
5089 * A64: Encodes MSR (for writing a GPR to a system register).
5090 *
5091 * @returns The encoded instruction.
5092 * @param iRegSrc The register which value to write. SP is NOT valid.
5093 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
5094 * IPRT specific format, of the register to write.
5095 */
5096DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
5097{
5098 Assert(iRegSrc < 32);
5099 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
5100
5101 /* Note. The top bit of idSysReg must always be set and is also set in
5102 0xd5100000, otherwise we'll be encoding a different instruction. */
5103 return UINT32_C(0xd5100000)
5104 | (idSysReg << 5)
5105 | iRegSrc;
5106}
5107
5108
5109/** @} */
5110
5111
5112/** @defgroup grp_rt_armv8_mkinstr_vec Vector Instruction Encoding Helpers
5113 * @ingroup grp_rt_armv8_mkinstr
5114 *
5115 * A few inlined functions and macros for assisting in encoding common ARMv8
5116 * Neon/SIMD instructions.
5117 *
5118 * @{ */
5119
5120/** Armv8 vector logical operation. */
5121typedef enum
5122{
5123 kArmv8VecInstrLogicOp_And = 0, /**< AND */
5124 kArmv8VecInstrLogicOp_Bic = RT_BIT_32(22), /**< BIC */
5125 kArmv8VecInstrLogicOp_Orr = RT_BIT_32(23), /**< ORR */
5126 kArmv8VecInstrLogicOp_Orn = RT_BIT_32(23) | RT_BIT_32(22), /**< ORN */
5127 kArmv8VecInstrLogicOp_Eor = RT_BIT_32(29), /**< EOR */
5128 kArmv8VecInstrLogicOp_Bsl = RT_BIT_32(29) | RT_BIT_32(22), /**< BSL */
5129 kArmv8VecInstrLogicOp_Bit = RT_BIT_32(29) | RT_BIT_32(23), /**< BIT */
5130 kArmv8VecInstrLogicOp_Bif = RT_BIT_32(29) | RT_BIT_32(23) | RT_BIT_32(22) /**< BIF */
5131} ARMV8INSTRVECLOGICOP;
5132
5133
5134/**
5135 * A64: Encodes logical instruction (vector, register).
5136 *
5137 * @returns The encoded instruction.
5138 * @param enmOp The operation to encode.
5139 * @param iVecRegDst The vector register to put the result into.
5140 * @param iVecRegSrc1 The 1st source register.
5141 * @param iVecRegSrc2 The 2nd source register.
5142 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5143 * or just the low 64-bit (false).
5144 */
5145DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrLogical(ARMV8INSTRVECLOGICOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5146 bool f128Bit = true)
5147{
5148 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5149
5150 return UINT32_C(0x0e201c00)
5151 | (uint32_t)enmOp
5152 | ((uint32_t)f128Bit << 30)
5153 | (iVecRegSrc2 << 16)
5154 | (iVecRegSrc1 << 5)
5155 | iVecRegDst;
5156}
5157
5158
5159/**
5160 * A64: Encodes ORR (vector, register).
5161 *
5162 * @returns The encoded instruction.
5163 * @param iVecRegDst The vector register to put the result into.
5164 * @param iVecRegSrc1 The 1st source register.
5165 * @param iVecRegSrc2 The 2nd source register.
5166 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5167 * or just the low 64-bit (false).
5168 */
5169DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrOrr(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5170 bool f128Bit = true)
5171{
5172 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Orr, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5173}
5174
5175
5176/**
5177 * A64: Encodes EOR (vector, register).
5178 *
5179 * @returns The encoded instruction.
5180 * @param iVecRegDst The vector register to put the result into.
5181 * @param iVecRegSrc1 The 1st source register.
5182 * @param iVecRegSrc2 The 2nd source register.
5183 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5184 * or just the low 64-bit (false).
5185 */
5186DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrEor(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5187 bool f128Bit = true)
5188{
5189 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Eor, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5190}
5191
5192
5193/**
5194 * A64: Encodes AND (vector, register).
5195 *
5196 * @returns The encoded instruction.
5197 * @param iVecRegDst The vector register to put the result into.
5198 * @param iVecRegSrc1 The 1st source register.
5199 * @param iVecRegSrc2 The 2nd source register.
5200 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5201 * or just the low 64-bit (false).
5202 */
5203DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAnd(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5204 bool f128Bit = true)
5205{
5206 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_And, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5207}
5208
5209
5210/** Armv8 UMOV/INS vector element size. */
5211typedef enum ARMV8INSTRUMOVINSSZ
5212{
5213 kArmv8InstrUmovInsSz_U8 = 0, /**< Byte. */
5214 kArmv8InstrUmovInsSz_U16 = 1, /**< Halfword. */
5215 kArmv8InstrUmovInsSz_U32 = 2, /**< 32-bit. */
5216 kArmv8InstrUmovInsSz_U64 = 3 /**< 64-bit (only valid when the destination is a 64-bit register. */
5217} ARMV8INSTRUMOVINSSZ;
5218
5219
5220/**
5221 * A64: Encodes UMOV (vector, register).
5222 *
5223 * @returns The encoded instruction.
5224 * @param iRegDst The register to put the result into.
5225 * @param iVecRegSrc The vector source register.
5226 * @param idxElem The element index.
5227 * @param enmSz Element size of the source vector register.
5228 * @param fDst64Bit Flag whether the destination register is 64-bit (true) or 32-bit (false).
5229 */
5230DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUmov(uint32_t iRegDst, uint32_t iVecRegSrc, uint8_t idxElem,
5231 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64, bool fDst64Bit = true)
5232{
5233 Assert(iRegDst < 32); Assert(iVecRegSrc < 32);
5234 Assert((fDst64Bit && enmSz == kArmv8InstrUmovInsSz_U64) || (!fDst64Bit && enmSz != kArmv8InstrUmovInsSz_U64));
5235 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5236 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5237 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5238 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5239
5240 return UINT32_C(0x0e003c00)
5241 | ((uint32_t)fDst64Bit << 30)
5242 | ((uint32_t)idxElem << (16 + enmSz + 1))
5243 | (RT_BIT_32(enmSz) << 16)
5244 | (iVecRegSrc << 5)
5245 | iRegDst;
5246}
5247
5248
5249/**
5250 * A64: Encodes INS (vector, register).
5251 *
5252 * @returns The encoded instruction.
5253 * @param iVecRegDst The vector register to put the result into.
5254 * @param iRegSrc The source register.
5255 * @param idxElem The element index for the destination.
5256 * @param enmSz Element size of the source vector register.
5257 *
5258 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5259 */
5260DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrIns(uint32_t iVecRegDst, uint32_t iRegSrc, uint8_t idxElem,
5261 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64)
5262{
5263 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5264 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5265 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5266 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5267 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5268
5269 return UINT32_C(0x4e001c00)
5270 | ((uint32_t)idxElem << (16 + enmSz + 1))
5271 | (RT_BIT_32(enmSz) << 16)
5272 | (iRegSrc << 5)
5273 | iVecRegDst;
5274}
5275
5276
5277/**
5278 * A64: Encodes DUP (vector, register).
5279 *
5280 * @returns The encoded instruction.
5281 * @param iVecRegDst The vector register to put the result into.
5282 * @param iRegSrc The source register (ZR is valid).
5283 * @param enmSz Element size of the source vector register.
5284 * @param f128Bit Flag whether the instruction operates on the whole 128-bit of the vector register (true) or
5285 * just the low 64-bit (false).
5286 *
5287 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5288 */
5289DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrDup(uint32_t iVecRegDst, uint32_t iRegSrc, ARMV8INSTRUMOVINSSZ enmSz,
5290 bool f128Bit = true)
5291{
5292 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5293 Assert( (enmSz == kArmv8InstrUmovInsSz_U8)
5294 || (enmSz == kArmv8InstrUmovInsSz_U16)
5295 || (enmSz == kArmv8InstrUmovInsSz_U32)
5296 || (enmSz == kArmv8InstrUmovInsSz_U64));
5297
5298 return UINT32_C(0x0e000c00)
5299 | ((uint32_t)f128Bit << 30)
5300 | (RT_BIT_32(enmSz) << 16)
5301 | (iRegSrc << 5)
5302 | iVecRegDst;
5303}
5304
5305
5306/** Armv8 vector compare to zero vector element size. */
5307typedef enum ARMV8INSTRVECCMPZEROSZ
5308{
5309 kArmv8InstrCmpZeroSz_S8 = 0, /**< Byte. */
5310 kArmv8InstrCmpZeroSz_S16 = 1, /**< Halfword. */
5311 kArmv8InstrCmpZeroSz_S32 = 2, /**< 32-bit. */
5312 kArmv8InstrCmpZeroSz_S64 = 3 /**< 64-bit. */
5313} ARMV8INSTRVECCMPZEROSZ;
5314
5315
5316/** Armv8 vector compare to zero vector operation. */
5317typedef enum ARMV8INSTRVECCMPZEROOP
5318{
5319 kArmv8InstrCmpZeroOp_Gt = 0, /**< Greater than. */
5320 kArmv8InstrCmpZeroOp_Ge = RT_BIT_32(29), /**< Greater than or equal to. */
5321 kArmv8InstrCmpZeroOp_Eq = RT_BIT_32(12), /**< Equal to. */
5322 kArmv8InstrCmpZeroOp_Le = RT_BIT_32(29) | RT_BIT_32(12) /**< Lower than or equal to. */
5323} ARMV8INSTRVECCMPZEROOP;
5324
5325
5326/**
5327 * A64: Encodes CMGT, CMGE, CMEQ or CMLE against zero (vector, register).
5328 *
5329 * @returns The encoded instruction.
5330 * @param iVecRegDst The vector register to put the result into.
5331 * @param iVecRegSrc The vector source register.
5332 * @param enmSz Vector element size.
5333 * @param enmOp The compare operation against to encode.
5334 */
5335DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpToZero(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECCMPZEROSZ enmSz,
5336 ARMV8INSTRVECCMPZEROOP enmOp)
5337{
5338 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5339
5340 return UINT32_C(0x5e208800)
5341 | ((uint32_t)enmSz << 22)
5342 | (RT_BIT_32(enmSz) << 16)
5343 | (iVecRegSrc << 5)
5344 | iVecRegDst
5345 | (uint32_t)enmOp;
5346}
5347
5348
5349/**
5350 * A64: Encodes CNT (vector, register).
5351 *
5352 * @returns The encoded instruction.
5353 * @param iVecRegDst The vector register to put the result into.
5354 * @param iVecRegSrc The vector source register.
5355 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5356 * or just the low 64-bit (false).
5357 */
5358DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCnt(uint32_t iVecRegDst, uint32_t iVecRegSrc, bool f128Bit = true)
5359{
5360 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5361
5362 return UINT32_C(0x0e205800)
5363 | ((uint32_t)f128Bit << 30)
5364 | (iVecRegSrc << 5)
5365 | iVecRegDst;
5366}
5367
5368
5369/** Armv8 vector unsigned sum long across vector element size. */
5370typedef enum ARMV8INSTRVECUADDLVSZ
5371{
5372 kArmv8InstrUAddLVSz_8B = 0, /**< 8 x 8-bit. */
5373 kArmv8InstrUAddLVSz_16B = RT_BIT_32(30), /**< 16 x 8-bit. */
5374 kArmv8InstrUAddLVSz_4H = 1, /**< 4 x 16-bit. */
5375 kArmv8InstrUAddLVSz_8H = RT_BIT_32(30) | 1, /**< 8 x 16-bit. */
5376 kArmv8InstrUAddLVSz_4S = RT_BIT_32(30) | 2 /**< 4 x 32-bit. */
5377} ARMV8INSTRVECUADDLVSZ;
5378
5379
5380/**
5381 * A64: Encodes UADDLV (vector, register).
5382 *
5383 * @returns The encoded instruction.
5384 * @param iVecRegDst The vector register to put the result into.
5385 * @param iVecRegSrc The vector source register.
5386 * @param enmSz Element size.
5387 */
5388DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUAddLV(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECUADDLVSZ enmSz)
5389{
5390 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5391
5392 return UINT32_C(0x2e303800)
5393 | ((uint32_t)enmSz)
5394 | (iVecRegSrc << 5)
5395 | iVecRegDst;
5396}
5397
5398
5399/** Armv8 USHR/USRA/URSRA/SSHR/SRSA/SSHR vector element size. */
5400typedef enum ARMV8INSTRUSHIFTSZ
5401{
5402 kArmv8InstrShiftSz_U8 = 8, /**< Byte. */
5403 kArmv8InstrShiftSz_U16 = 16, /**< Halfword. */
5404 kArmv8InstrShiftSz_U32 = 32, /**< 32-bit. */
5405 kArmv8InstrShiftSz_U64 = 64 /**< 64-bit. */
5406} ARMV8INSTRUSHIFTSZ;
5407
5408/**
5409 * A64: Encodes USHR/USRA/URSRA/SSHR/SRSA/SSHR (vector, register).
5410 *
5411 * @returns The encoded instruction.
5412 * @param iVecRegDst The vector register to put the result into.
5413 * @param iVecRegSrc The vector source register.
5414 * @param cShift Number of bits to shift.
5415 * @param enmSz Element size.
5416 * @param fUnsigned Flag whether this a signed or unsigned shift,
5417 * @param fRound Flag whether this is the rounding shift variant.
5418 * @param fAccum Flag whether this is the accumulate shift variant.
5419 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5420 * or just the low 64-bit (false).
5421 */
5422DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShrImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5423 bool fUnsigned = true, bool fRound = false, bool fAccum = false, bool f128Bit = true)
5424{
5425 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5426 Assert( cShift >= 1
5427 && ( (enmSz == kArmv8InstrShiftSz_U8 && cShift <= 8)
5428 || (enmSz == kArmv8InstrShiftSz_U16 && cShift <= 16)
5429 || (enmSz == kArmv8InstrShiftSz_U32 && cShift <= 32)
5430 || (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
5431
5432 return UINT32_C(0x0f000400)
5433 | ((uint32_t)f128Bit << 30)
5434 | ((uint32_t)fUnsigned << 29)
5435 | ((((uint32_t)enmSz << 1) - cShift) << 16)
5436 | ((uint32_t)fRound << 13)
5437 | ((uint32_t)fAccum << 12)
5438 | (iVecRegSrc << 5)
5439 | iVecRegDst;
5440}
5441
5442
5443/**
5444 * A64: Encodes SHL (vector, register).
5445 *
5446 * @returns The encoded instruction.
5447 * @param iVecRegDst The vector register to put the result into.
5448 * @param iVecRegSrc The vector source register.
5449 * @param cShift Number of bits to shift.
5450 * @param enmSz Element size.
5451 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5452 * or just the low 64-bit (false).
5453 */
5454DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5455 bool f128Bit = true)
5456{
5457 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5458 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5459 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5460 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
5461 || (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
5462
5463 return UINT32_C(0x0f005400)
5464 | ((uint32_t)f128Bit << 30)
5465 | (((uint32_t)enmSz | cShift) << 16)
5466 | (iVecRegSrc << 5)
5467 | iVecRegDst;
5468}
5469
5470
5471/**
5472 * A64: Encodes SHLL/SHLL2/USHLL/USHLL2 (vector, register).
5473 *
5474 * @returns The encoded instruction.
5475 * @param iVecRegDst The vector register to put the result into.
5476 * @param iVecRegSrc The vector source register.
5477 * @param cShift Number of bits to shift.
5478 * @param enmSz Element size of the source vector register, the destination vector register
5479 * element size is twice as large, kArmv8InstrShiftSz_U64 is invalid.
5480 * @param fUnsigned Flag whether this is an unsigned shift left (true, default) or signed (false).
5481 * @param fUpper Flag whether this operates on the lower half (false, default) of the source vector register
5482 * or the upper half (true).
5483 */
5484DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUShll(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5485 bool fUnsigned = true, bool fUpper = false)
5486{
5487 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5488 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5489 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5490 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32));
5491
5492 return UINT32_C(0x0f00a400)
5493 | ((uint32_t)fUpper << 30)
5494 | ((uint32_t)fUnsigned << 29)
5495 | (((uint32_t)enmSz | cShift) << 16)
5496 | (iVecRegSrc << 5)
5497 | iVecRegDst;
5498}
5499
5500
5501/** Armv8 vector arith ops element size. */
5502typedef enum ARMV8INSTRVECARITHSZ
5503{
5504 kArmv8VecInstrArithSz_8 = 0, /**< 8-bit. */
5505 kArmv8VecInstrArithSz_16 = 1, /**< 16-bit. */
5506 kArmv8VecInstrArithSz_32 = 2, /**< 32-bit. */
5507 kArmv8VecInstrArithSz_64 = 3 /**< 64-bit. */
5508} ARMV8INSTRVECARITHSZ;
5509
5510
5511/** Armv8 vector arithmetic operation. */
5512typedef enum
5513{
5514 kArmv8VecInstrArithOp_Add = RT_BIT_32(15), /**< ADD */
5515 kArmv8VecInstrArithOp_Sub = RT_BIT_32(29) | RT_BIT_32(15), /**< SUB */
5516 kArmv8VecInstrArithOp_UnsignSat_Add = RT_BIT_32(29) | RT_BIT_32(11), /**< UQADD */
5517 kArmv8VecInstrArithOp_UnsignSat_Sub = RT_BIT_32(29) | RT_BIT_32(13) | RT_BIT_32(11), /**< UQSUB */
5518 kArmv8VecInstrArithOp_SignSat_Add = RT_BIT_32(11), /**< SQADD */
5519 kArmv8VecInstrArithOp_SignSat_Sub = RT_BIT_32(13) | RT_BIT_32(11), /**< SQSUB */
5520 kArmv8VecInstrArithOp_Mul = RT_BIT_32(15) | RT_BIT_32(12) | RT_BIT_32(11) /**< MUL */
5521} ARMV8INSTRVECARITHOP;
5522
5523
5524/**
5525 * A64: Encodes an arithmetic operation (vector, register).
5526 *
5527 * @returns The encoded instruction.
5528 * @param enmOp The operation to encode.
5529 * @param iVecRegDst The vector register to put the result into.
5530 * @param iVecRegSrc1 The first vector source register.
5531 * @param iVecRegSrc2 The second vector source register.
5532 * @param enmSz Element size.
5533 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5534 * or just the low 64-bit (false).
5535 */
5536DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrArithOp(ARMV8INSTRVECARITHOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5537 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5538{
5539 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5540
5541 return UINT32_C(0x0e200400)
5542 | (uint32_t)enmOp
5543 | ((uint32_t)f128Bit << 30)
5544 | ((uint32_t)enmSz << 22)
5545 | (iVecRegSrc2 << 16)
5546 | (iVecRegSrc1 << 5)
5547 | iVecRegDst;
5548}
5549
5550
5551/** Armv8 vector compare operation. */
5552typedef enum ARMV8VECINSTRCMPOP
5553{
5554 /* U insn[15:10] */
5555 kArmv8VecInstrCmpOp_Gt = UINT32_C(0x3400), /**< Greater than (>) (signed) */
5556 kArmv8VecInstrCmpOp_Ge = UINT32_C(0x3c00), /**< Greater or equal (>=) (signed) */
5557 kArmv8VecInstrCmpOp_Hi = RT_BIT_32(29) | UINT32_C(0x3400), /**< Greater than (>) (unsigned) */
5558 kArmv8VecInstrCmpOp_Hs = RT_BIT_32(29) | UINT32_C(0x3c00), /**< Greater or equal (>=) (unsigned) */
5559 kArmv8VecInstrCmpOp_Eq = RT_BIT_32(29) | UINT32_C(0x8c00) /**< Equal (==) (unsigned) */
5560} ARMV8VECINSTRCMPOP;
5561
5562/**
5563 * A64: Encodes CMEQ/CMGE/CMGT/CMHI/CMHS (register variant) (vector, register).
5564 *
5565 * @returns The encoded instruction.
5566 * @param enmOp The operation to perform.
5567 * @param iVecRegDst The vector register to put the result into.
5568 * @param iVecRegSrc1 The first vector source register.
5569 * @param iVecRegSrc2 The second vector source register.
5570 * @param enmSz Element size.
5571 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5572 * or just the low 64-bit (false).
5573 */
5574DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmp(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5575 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5576{
5577 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5578
5579 return UINT32_C(0x0e200000)
5580 | ((uint32_t)f128Bit << 30)
5581 | ((uint32_t)enmSz << 22)
5582 | (iVecRegSrc2 << 16)
5583 | ((uint32_t)enmOp)
5584 | (iVecRegSrc1 << 5)
5585 | iVecRegDst;
5586}
5587
5588
5589/** Armv8 vector compare against zero operation. */
5590typedef enum ARMV8VECINSTRCMPZEROOP
5591{
5592 /* U insn[15:10] */
5593 kArmv8VecInstrCmpZeroOp_Gt = UINT32_C(0x8800), /**< Greater than zero (>) (signed) */
5594 kArmv8VecInstrCmpZeroOp_Eq = UINT32_C(0x9800), /**< Equal to zero (==) */
5595 kArmv8VecInstrCmpZeroOp_Lt = UINT32_C(0xa800), /**< Lower than zero (>=) (signed) */
5596 kArmv8VecInstrCmpZeroOp_Ge = RT_BIT_32(29) | UINT32_C(0x8800), /**< Greater or equal to zero (>=) (signed) */
5597 kArmv8VecInstrCmpZeroOp_Le = RT_BIT_32(29) | UINT32_C(0x9800) /**< Lower or equal to zero (<=) (signed) */
5598} ARMV8VECINSTRCMPZEROOP;
5599
5600/**
5601 * A64: Encodes CMEQ/CMGE/CMGT/CMLE/CMLT (zero variant) (vector, register).
5602 *
5603 * @returns The encoded instruction.
5604 * @param enmOp The operation to perform.
5605 * @param iVecRegDst The vector register to put the result into.
5606 * @param iVecRegSrc The first vector source register.
5607 * @param enmSz Element size.
5608 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5609 * or just the low 64-bit (false).
5610 */
5611DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpAgainstZero(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc,
5612 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5613{
5614 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5615
5616 return UINT32_C(0x0e200000)
5617 | ((uint32_t)f128Bit << 30)
5618 | ((uint32_t)enmSz << 22)
5619 | ((uint32_t)enmOp)
5620 | (iVecRegSrc << 5)
5621 | iVecRegDst;
5622}
5623
5624
5625/** Armv8 [Signed,Unsigned] Extract {Unsigned} operation. */
5626typedef enum
5627{
5628 kArmv8VecInstrQxtnOp_Sqxtn = RT_BIT_32(14), /**< SQXTN */
5629 kArmv8VecInstrQxtnOp_Sqxtun = RT_BIT_32(29) | RT_BIT_32(13), /**< SQXTUN */
5630 kArmv8VecInstrQxtnOp_Uqxtn = RT_BIT_32(29) | RT_BIT_32(14) /**< UQXTN */
5631} ARMV8INSTRVECQXTNOP;
5632
5633/**
5634 * A64: Encodes SQXTN/SQXTN2/UQXTN/UQXTN2/SQXTUN/SQXTUN2 (vector, register).
5635 *
5636 * @returns The encoded instruction.
5637 * @param enmOp The operation to perform.
5638 * @param fUpper Flag whether to write the result to the lower (false) or upper (true) half of the destinatiom register.
5639 * @param iVecRegDst The vector register to put the result into.
5640 * @param iVecRegSrc The first vector source register.
5641 * @param enmSz Element size.
5642 */
5643DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrQxtn(ARMV8INSTRVECQXTNOP enmOp, bool fUpper, uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECARITHSZ enmSz)
5644{
5645 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5646
5647 return UINT32_C(0x0e210800)
5648 | ((uint32_t)enmOp)
5649 | ((uint32_t)fUpper << 30)
5650 | ((uint32_t)enmSz << 22)
5651 | (iVecRegSrc << 5)
5652 | iVecRegDst;
5653}
5654
5655
5656/** Armv8 floating point size. */
5657typedef enum
5658{
5659 kArmv8VecInstrFpSz_2x_Single = 0, /**< 2x single precision values in the low 64-bit of the 128-bit register. */
5660 kArmv8VecInstrFpSz_4x_Single = RT_BIT_32(30), /**< 4x single precision values in the 128-bit register. */
5661 kArmv8VecInstrFpSz_2x_Double = RT_BIT_32(30) | RT_BIT_32(22) /**< 2x double precision values in the 128-bit register. */
5662} ARMV8INSTRVECFPSZ;
5663
5664
5665/** Armv8 3 operand floating point operation. */
5666typedef enum
5667{
5668 /* insn[29] insn[23] insn[15:11] */
5669 kArmv8VecInstrFpOp_Add = UINT32_C(0xd000), /**< FADD */
5670 kArmv8VecInstrFpOp_Sub = RT_BIT_32(23) | UINT32_C(0xd000), /**< FADD */
5671 kArmv8VecInstrFpOp_AddPairwise = RT_BIT_32(29) | UINT32_C(0xd000), /**< FADDP */
5672 kArmv8VecInstrFpOp_Mul = RT_BIT_32(29) | UINT32_C(0xd800), /**< FMUL */
5673 kArmv8VecInstrFpOp_Div = RT_BIT_32(29) | UINT32_C(0xf800), /**< FDIV */
5674
5675 kArmv8VecInstrFpOp_Max = UINT32_C(0xf000), /**< FMAX */
5676 kArmv8VecInstrFpOp_MaxNumber = UINT32_C(0xc000), /**< FMAXNM */
5677 kArmv8VecInstrFpOp_MaxNumberPairwise = RT_BIT_32(29) | UINT32_C(0xc000), /**< FMAXNMP */
5678 kArmv8VecInstrFpOp_MaxPairwise = RT_BIT_32(29) | UINT32_C(0xf000), /**< FMAXP */
5679
5680 kArmv8VecInstrFpOp_Min = RT_BIT_32(23) | UINT32_C(0xf000), /**< FMIN */
5681 kArmv8VecInstrFpOp_MinNumber = RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNM */
5682 kArmv8VecInstrFpOp_MinNumberPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNMP */
5683 kArmv8VecInstrFpOp_MinPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xf000), /**< FMINP */
5684
5685 kArmv8VecInstrFpOp_Fmla = UINT32_C(0xc800), /**< FMLA */
5686 kArmv8VecInstrFpOp_Fmls = RT_BIT_32(23) | UINT32_C(0xc800) /**< FMLS */
5687} ARMV8INSTRVECFPOP;
5688
5689/**
5690 * A64: Encodes a 3 operand floating point operation (vector, register).
5691 *
5692 * @returns The encoded instruction.
5693 * @param enmOp The operation to perform.
5694 * @param enmSz The size to operate on.
5695 * @param iVecRegDst The vector register to put the result into.
5696 * @param iVecRegSrc1 The first vector source register.
5697 * @param iVecRegSrc2 The second vector source register.
5698 */
5699DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrFp3Op(ARMV8INSTRVECFPOP enmOp, ARMV8INSTRVECFPSZ enmSz, uint32_t iVecRegDst,
5700 uint32_t iVecRegSrc1, uint32_t iVecRegSrc2)
5701{
5702 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5703
5704 return UINT32_C(0x0e200400)
5705 | ((uint32_t)enmOp)
5706 | ((uint32_t)enmSz)
5707 | (iVecRegSrc2 << 16)
5708 | (iVecRegSrc1 << 5)
5709 | iVecRegDst;
5710}
5711
5712
5713/** @} */
5714
5715#endif /* !dtrace && __cplusplus */
5716
5717/** @} */
5718
5719#endif /* !IPRT_INCLUDED_armv8_h */
5720
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