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source: vbox/trunk/include/iprt/armv8.h@ 108858

Last change on this file since 108858 was 108858, checked in by vboxsync, 2 weeks ago

include/iprt/armv8.h: Some additional definitions, bugref:10388 [scm]
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/cdefs.h>
44# ifndef RT_IN_ASSEMBLER
45# include <iprt/types.h>
46# include <iprt/assert.h>
47# endif
48# include <iprt/assertcompile.h>
49#else
50# pragma D depends_on library vbox-types.d
51#endif
52
53/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
54 * @ingroup grp_rt
55 * @{
56 */
57
58/** @name The AArch64 general purpose register encoding.
59 * @{ */
60#define ARMV8_A64_REG_X0 0
61#define ARMV8_A64_REG_X1 1
62#define ARMV8_A64_REG_X2 2
63#define ARMV8_A64_REG_X3 3
64#define ARMV8_A64_REG_X4 4
65#define ARMV8_A64_REG_X5 5
66#define ARMV8_A64_REG_X6 6
67#define ARMV8_A64_REG_X7 7
68#define ARMV8_A64_REG_X8 8
69#define ARMV8_A64_REG_X9 9
70#define ARMV8_A64_REG_X10 10
71#define ARMV8_A64_REG_X11 11
72#define ARMV8_A64_REG_X12 12
73#define ARMV8_A64_REG_X13 13
74#define ARMV8_A64_REG_X14 14
75#define ARMV8_A64_REG_X15 15
76#define ARMV8_A64_REG_X16 16
77#define ARMV8_A64_REG_X17 17
78#define ARMV8_A64_REG_X18 18
79#define ARMV8_A64_REG_X19 19
80#define ARMV8_A64_REG_X20 20
81#define ARMV8_A64_REG_X21 21
82#define ARMV8_A64_REG_X22 22
83#define ARMV8_A64_REG_X23 23
84#define ARMV8_A64_REG_X24 24
85#define ARMV8_A64_REG_X25 25
86#define ARMV8_A64_REG_X26 26
87#define ARMV8_A64_REG_X27 27
88#define ARMV8_A64_REG_X28 28
89#define ARMV8_A64_REG_X29 29
90#define ARMV8_A64_REG_X30 30
91/** @} */
92
93/** @name The AArch64 32-bit general purpose register names.
94 * @{ */
95#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
96#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
97#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
98#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
99#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
100#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
101#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
102#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
103#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
104#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
105#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
106#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
107#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
108#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
109#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
110#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
111#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
112#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
113#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
114#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
115#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
116#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
117#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
118#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
119#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
120#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
121#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
122#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
123#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
124#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
125#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
126/** @} */
127
128/** @name The AArch64 NEON scalar register encoding.
129 * @{ */
130#define ARMV8_A64_REG_Q0 0
131#define ARMV8_A64_REG_Q1 1
132#define ARMV8_A64_REG_Q2 2
133#define ARMV8_A64_REG_Q3 3
134#define ARMV8_A64_REG_Q4 4
135#define ARMV8_A64_REG_Q5 5
136#define ARMV8_A64_REG_Q6 6
137#define ARMV8_A64_REG_Q7 7
138#define ARMV8_A64_REG_Q8 8
139#define ARMV8_A64_REG_Q9 9
140#define ARMV8_A64_REG_Q10 10
141#define ARMV8_A64_REG_Q11 11
142#define ARMV8_A64_REG_Q12 12
143#define ARMV8_A64_REG_Q13 13
144#define ARMV8_A64_REG_Q14 14
145#define ARMV8_A64_REG_Q15 15
146#define ARMV8_A64_REG_Q16 16
147#define ARMV8_A64_REG_Q17 17
148#define ARMV8_A64_REG_Q18 18
149#define ARMV8_A64_REG_Q19 19
150#define ARMV8_A64_REG_Q20 20
151#define ARMV8_A64_REG_Q21 21
152#define ARMV8_A64_REG_Q22 22
153#define ARMV8_A64_REG_Q23 23
154#define ARMV8_A64_REG_Q24 24
155#define ARMV8_A64_REG_Q25 25
156#define ARMV8_A64_REG_Q26 26
157#define ARMV8_A64_REG_Q27 27
158#define ARMV8_A64_REG_Q28 28
159#define ARMV8_A64_REG_Q29 29
160#define ARMV8_A64_REG_Q30 30
161#define ARMV8_A64_REG_Q31 31
162/** @} */
163
164/** @name The AArch64 NEON vector register encoding.
165 * @{ */
166#define ARMV8_A64_REG_V0 ARMV8_A64_REG_Q0
167#define ARMV8_A64_REG_V1 ARMV8_A64_REG_Q1
168#define ARMV8_A64_REG_V2 ARMV8_A64_REG_Q2
169#define ARMV8_A64_REG_V3 ARMV8_A64_REG_Q3
170#define ARMV8_A64_REG_V4 ARMV8_A64_REG_Q4
171#define ARMV8_A64_REG_V5 ARMV8_A64_REG_Q5
172#define ARMV8_A64_REG_V6 ARMV8_A64_REG_Q6
173#define ARMV8_A64_REG_V7 ARMV8_A64_REG_Q7
174#define ARMV8_A64_REG_V8 ARMV8_A64_REG_Q8
175#define ARMV8_A64_REG_V9 ARMV8_A64_REG_Q9
176#define ARMV8_A64_REG_V10 ARMV8_A64_REG_Q10
177#define ARMV8_A64_REG_V11 ARMV8_A64_REG_Q11
178#define ARMV8_A64_REG_V12 ARMV8_A64_REG_Q12
179#define ARMV8_A64_REG_V13 ARMV8_A64_REG_Q13
180#define ARMV8_A64_REG_V14 ARMV8_A64_REG_Q14
181#define ARMV8_A64_REG_V15 ARMV8_A64_REG_Q15
182#define ARMV8_A64_REG_V16 ARMV8_A64_REG_Q16
183#define ARMV8_A64_REG_V17 ARMV8_A64_REG_Q17
184#define ARMV8_A64_REG_V18 ARMV8_A64_REG_Q18
185#define ARMV8_A64_REG_V19 ARMV8_A64_REG_Q19
186#define ARMV8_A64_REG_V20 ARMV8_A64_REG_Q20
187#define ARMV8_A64_REG_V21 ARMV8_A64_REG_Q21
188#define ARMV8_A64_REG_V22 ARMV8_A64_REG_Q22
189#define ARMV8_A64_REG_V23 ARMV8_A64_REG_Q23
190#define ARMV8_A64_REG_V24 ARMV8_A64_REG_Q24
191#define ARMV8_A64_REG_V25 ARMV8_A64_REG_Q25
192#define ARMV8_A64_REG_V26 ARMV8_A64_REG_Q26
193#define ARMV8_A64_REG_V27 ARMV8_A64_REG_Q27
194#define ARMV8_A64_REG_V28 ARMV8_A64_REG_Q28
195#define ARMV8_A64_REG_V29 ARMV8_A64_REG_Q29
196#define ARMV8_A64_REG_V30 ARMV8_A64_REG_Q30
197#define ARMV8_A64_REG_V31 ARMV8_A64_REG_Q31
198/** @} */
199
200/** @name The AArch64 register 31.
201 * @note Register 31 typically refers to the zero register, but can also in
202 * select case (by instruction and opecode field) refer the to stack
203 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
204 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
205 * 31 will be the zero register.
206 * @{ */
207/** The stack pointer. */
208#define ARMV8_A64_REG_SP 31
209/** The zero register. Reads as zero, writes ignored. */
210#define ARMV8_A64_REG_XZR 31
211/** The zero register, the 32-bit register name. */
212#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
213/** @} */
214
215/** @name AArch64 register aliases
216 * @{ */
217/** The link register is typically mapped to x30 as that's the default pick of
218 * the RET instruction. */
219#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
220/** Frame base pointer is typically mapped to x29. */
221#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
222/** @} */
223
224
225/** @name System register encoding.
226 * @{
227 */
228/** Mask for the op0 part of an MSR/MRS instruction */
229#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
230/** Shift for the op0 part of an MSR/MRS instruction */
231#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
232/** Returns the op0 part of the given MRS/MSR instruction. */
233#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
234/** Mask for the op1 part of an MSR/MRS instruction */
235#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
236/** Shift for the op1 part of an MSR/MRS instruction */
237#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
238/** Returns the op1 part of the given MRS/MSR instruction. */
239#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
240/** Mask for the CRn part of an MSR/MRS instruction */
241#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
242 | RT_BIT_32(15) )
243/** Shift for the CRn part of an MSR/MRS instruction */
244#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
245/** Returns the CRn part of the given MRS/MSR instruction. */
246#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
247/** Mask for the CRm part of an MSR/MRS instruction */
248#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
249 | RT_BIT_32(11) )
250/** Shift for the CRm part of an MSR/MRS instruction */
251#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
252/** Returns the CRn part of the given MRS/MSR instruction. */
253#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
254/** Mask for the op2 part of an MSR/MRS instruction */
255#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
256/** Shift for the op2 part of an MSR/MRS instruction */
257#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
258/** Returns the op2 part of the given MRS/MSR instruction. */
259#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
260/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
261#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
262 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
263 | ARMV8_AARCH64_SYSREG_OP2_MASK)
264/** @} */
265
266/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
267 * IPRT specific and not part of the ARMv8 specification.
268 * @{ */
269#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
270 (uint16_t)( (((a_Op0) & 0x3) << 14) \
271 | (((a_Op1) & 0x7) << 11) \
272 | (((a_CRn) & 0xf) << 7) \
273 | (((a_CRm) & 0xf) << 3) \
274 | ((a_Op2) & 0x7))
275/** Returns the internal system register ID from the given MRS/MSR instruction. */
276#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
277 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
278 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
279 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
280 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
281 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
282/** Encodes the given system register ID in the given MSR/MRS instruction. */
283#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
284 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
285/** @} */
286
287
288/** @name System register IDs.
289 * @{ */
290/** OSDTRRX_EL1 register - RW. */
291#define ARMV8_AARCH64_SYSREG_OSDTRRX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 0, 2)
292/** MDSCR_EL1 - RW. */
293#define ARMV8_AARCH64_SYSREG_MDSCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 2)
294/** DBGBVR<0..15>_EL1 register - RW. */
295#define ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 4)
296/** DBGBCR<0..15>_EL1 register - RW. */
297#define ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 5)
298/** DBGWVR<0..15>_EL1 register - RW. */
299#define ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 6)
300/** DBGWCR<0..15>_EL1 register - RW. */
301#define ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 7)
302/** MDCCINT_EL1 register - RW. */
303#define ARMV8_AARCH64_SYSREG_MDCCINT_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 0)
304/** OSDTRTX_EL1 register - RW. */
305#define ARMV8_AARCH64_SYSREG_OSDTRTX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 3, 2)
306/** OSECCR_EL1 register - RW. */
307#define ARMV8_AARCH64_SYSREG_OSECCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 6, 2)
308/** MDRAR_EL1 register - RO. */
309#define ARMV8_AARCH64_SYSREG_MDRAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 0)
310/** OSLAR_EL1 register - WO. */
311#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
312/** OSLSR_EL1 register - RO. */
313#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
314/** OSDLR_EL1 register - RW. */
315#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
316
317/** MIDR_EL1 register - RO. */
318#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
319/** MIPDR_EL1 register - RO. */
320#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
321/** REVIDR_EL1 register - RO. */
322#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
323/** ID_PFR0_EL1 register - RO. */
324#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
325/** ID_PFR1_EL1 register - RO. */
326#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
327/** ID_DFR0_EL1 register - RO. */
328#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
329/** ID_AFR0_EL1 register - RO. */
330#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
331/** ID_MMFR0_EL1 register - RO. */
332#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
333/** ID_MMFR1_EL1 register - RO. */
334#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
335/** ID_MMFR2_EL1 register - RO. */
336#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
337/** ID_MMFR3_EL1 register - RO. */
338#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
339
340/** ID_ISAR0_EL1 register - RO. */
341#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
342/** ID_ISAR1_EL1 register - RO. */
343#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
344/** ID_ISAR2_EL1 register - RO. */
345#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
346/** ID_ISAR3_EL1 register - RO. */
347#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
348/** ID_ISAR4_EL1 register - RO. */
349#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
350/** ID_ISAR5_EL1 register - RO. */
351#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
352/** ID_MMFR4_EL1 register - RO. */
353#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
354/** ID_ISAR6_EL1 register - RO. */
355#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
356
357/** MVFR0_EL1 register - RO. */
358#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
359/** MVFR1_EL1 register - RO. */
360#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
361/** MVFR2_EL1 register - RO. */
362#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
363/** ID_PFR2_EL1 register - RO. */
364#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
365/** ID_DFR1_EL1 register - RO. */
366#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
367/** ID_MMFR5_EL1 register - RO. */
368#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
369
370/** ID_AA64PFR0_EL1 register - RO. */
371#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
372/** ID_AA64PFR0_EL1 register - RO. */
373#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
374/** ID_AA64ZFR0_EL1 register - RO. */
375#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
376/** ID_AA64SMFR0_EL1 register - RO. */
377#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
378
379/** ID_AA64DFR0_EL1 register - RO. */
380#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
381/** ID_AA64DFR0_EL1 register - RO. */
382#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
383/** ID_AA64AFR0_EL1 register - RO. */
384#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
385/** ID_AA64AFR1_EL1 register - RO. */
386#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
387
388/** ID_AA64ISAR0_EL1 register - RO. */
389#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
390/** ID_AA64ISAR1_EL1 register - RO. */
391#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
392/** ID_AA64ISAR2_EL1 register - RO. */
393#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
394
395/** ID_AA64MMFR0_EL1 register - RO. */
396#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
397/** ID_AA64MMFR1_EL1 register - RO. */
398#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
399/** ID_AA64MMFR2_EL1 register - RO. */
400#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
401
402/** SCTRL_EL1 register - RW. */
403#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
404/** ACTRL_EL1 register - RW. */
405#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
406/** CPACR_EL1 register - RW. */
407#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
408/** RGSR_EL1 register - RW. */
409#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
410/** GCR_EL1 register - RW. */
411#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
412
413/** ZCR_EL1 register - RW. */
414#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
415/** TRFCR_EL1 register - RW. */
416#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
417/** SMPRI_EL1 register - RW. */
418#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
419/** SMCR_EL1 register - RW. */
420#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
421
422/** TTBR0_EL1 register - RW. */
423#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
424/** TTBR1_EL1 register - RW. */
425#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
426/** TCR_EL1 register - RW. */
427#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
428
429/** APIAKeyLo_EL1 register - RW. */
430#define ARMV8_AARCH64_SYSREG_APIAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 0)
431/** APIAKeyHi_EL1 register - RW. */
432#define ARMV8_AARCH64_SYSREG_APIAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 1)
433/** APIBKeyLo_EL1 register - RW. */
434#define ARMV8_AARCH64_SYSREG_APIBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 2)
435/** APIBKeyHi_EL1 register - RW. */
436#define ARMV8_AARCH64_SYSREG_APIBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 3)
437
438/** APDAKeyLo_EL1 register - RW. */
439#define ARMV8_AARCH64_SYSREG_APDAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 0)
440/** APDAKeyHi_EL1 register - RW. */
441#define ARMV8_AARCH64_SYSREG_APDAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 1)
442/** APDBKeyLo_EL1 register - RW. */
443#define ARMV8_AARCH64_SYSREG_APDBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 2)
444/** APDBKeyHi_EL1 register - RW. */
445#define ARMV8_AARCH64_SYSREG_APDBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 3)
446
447/** APGAKeyLo_EL1 register - RW. */
448#define ARMV8_AARCH64_SYSREG_APGAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 0)
449/** APGAKeyHi_EL1 register - RW. */
450#define ARMV8_AARCH64_SYSREG_APGAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 1)
451
452/** SPSR_EL1 register - RW. */
453#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
454/** ELR_EL1 register - RW. */
455#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
456
457/** SP_EL0 register - RW. */
458#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
459
460/** PSTATE.SPSel value. */
461#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
462/** PSTATE.CurrentEL value. */
463#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
464/** PSTATE.PAN value. */
465#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
466/** PSTATE.UAO value. */
467#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
468
469/** PSTATE.ALLINT value. */
470#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
471
472/** ICC_PMR_EL1 register - RW. */
473#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
474
475/** AFSR0_EL1 register - RW. */
476#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
477/** AFSR1_EL1 register - RW. */
478#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
479
480/** ESR_EL1 register - RW. */
481#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
482
483/** ERRIDR_EL1 register - RO. */
484#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
485/** ERRSELR_EL1 register - RW. */
486#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
487
488/** FAR_EL1 register - RW. */
489#define ARMV8_AARCH64_SYSREG_FAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 6, 0, 0)
490
491/** PAR_EL1 register - RW. */
492#define ARMV8_AARCH64_SYSREG_PAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 7, 4, 0)
493
494/** PMINTENCLR_EL1 register - RW. */
495#define ARMV8_AARCH64_SYSREG_PMINTENCLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 9, 14, 2)
496
497/** MAIR_EL1 register - RW. */
498#define ARMV8_AARCH64_SYSREG_MAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 2, 0)
499
500/** AMAIR_EL1 register - RW. */
501#define ARMV8_AARCH64_SYSREG_AMAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 3, 0)
502
503/** VBAR_EL1 register - RW. */
504#define ARMV8_AARCH64_SYSREG_VBAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 0, 0)
505
506/** ICC_IAR0_EL1 register - RO. */
507#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
508/** ICC_EOIR0_EL1 register - WO. */
509#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
510/** ICC_HPPIR0_EL1 register - WO. */
511#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
512/** ICC_BPR0_EL1 register - RW. */
513#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
514/** ICC_AP0R0_EL1 register - RW. */
515#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
516/** ICC_AP0R1_EL1 register - RW. */
517#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
518/** ICC_AP0R2_EL1 register - RW. */
519#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
520/** ICC_AP0R3_EL1 register - RW. */
521#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
522
523/** ICC_AP1R0_EL1 register - RW. */
524#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
525/** ICC_AP1R1_EL1 register - RW. */
526#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
527/** ICC_AP1R2_EL1 register - RW. */
528#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
529/** ICC_AP1R3_EL1 register - RW. */
530#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
531/** ICC_NMIAR1_EL1 register - RO. */
532#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
533
534/** ICC_DIR_EL1 register - WO. */
535#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
536/** ICC_RPR_EL1 register - RO. */
537#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
538/** ICC_SGI1R_EL1 register - WO. */
539#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
540/** ICC_ASGI1R_EL1 register - WO. */
541#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
542/** ICC_SGI0R_EL1 register - WO. */
543#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
544
545/** ICC_IAR1_EL1 register - RO. */
546#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
547/** ICC_EOIR1_EL1 register - WO. */
548#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
549/** ICC_HPPIR1_EL1 register - RO. */
550#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
551/** ICC_BPR1_EL1 register - RW. */
552#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
553/** ICC_CTLR_EL1 register - RW. */
554#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
555/** ICC_SRE_EL1 register - RW. */
556#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
557/** ICC_IGRPEN0_EL1 register - RW. */
558#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
559/** ICC_IGRPEN1_EL1 register - RW. */
560#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
561
562/** CONTEXTIDR_EL1 register - RW. */
563#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 1)
564/** TPIDR_EL1 register - RW. */
565#define ARMV8_AARCH64_SYSREG_TPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 4)
566
567/** CNTKCTL_EL1 register - RW. */
568#define ARMV8_AARCH64_SYSREG_CNTKCTL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 14, 1, 0)
569
570/** CSSELR_EL1 register - RW. */
571#define ARMV8_AARCH64_SYSREG_CSSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 2, 0, 0, 0)
572
573/** CTR_EL0 - Cache Type Register - RO. */
574#define ARMV8_AARCH64_SYSREG_CTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 0, 0, 1)
575/** DCZID_EL0 - Data Cache Zero ID Register - RO. */
576#define ARMV8_AARCH64_SYSREG_DCZID_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 0, 0, 7)
577
578
579/** NZCV - Status Flags - ??. */
580#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
581/** DAIF - Interrupt Mask Bits - ??. */
582#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
583/** SVCR - Streaming Vector Control Register - ??. */
584#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
585/** DIT - Data Independent Timing - ??. */
586#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
587/** SSBS - Speculative Store Bypass Safe - ??. */
588#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
589/** TCO - Tag Check Override - ??. */
590#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
591
592/** FPCR register - RW. */
593#define ARMV8_AARCH64_SYSREG_FPCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 0)
594/** FPSR register - RW. */
595#define ARMV8_AARCH64_SYSREG_FPSR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 1)
596
597/** PMCR_EL0 register - RW. */
598#define ARMV8_AARCH64_SYSREG_PMCR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 0)
599/** PMCNTENSET_EL0 register - RW. */
600#define ARMV8_AARCH64_SYSREG_PMCNTENSET_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 1)
601/** PMCNTENCLR_EL0 register - RW. */
602#define ARMV8_AARCH64_SYSREG_PMCNTENCLR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 2)
603/** PMOVSCLR_EL0 register - RW. */
604#define ARMV8_AARCH64_SYSREG_PMOVSCLR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 3)
605
606/** PMCCNTR_EL0 register - RW. */
607#define ARMV8_AARCH64_SYSREG_PMCCNTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 13, 0)
608
609/** PMUSERENR_EL0 register - RW. */
610#define ARMV8_AARCH64_SYSREG_PMUSERENR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 14, 0)
611
612/** PMCCFILTR_EL0 register - RW. */
613#define ARMV8_AARCH64_SYSREG_PMCCFILTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 15, 7)
614
615/** ICC_SRE_EL2 register - RW. */
616#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 9, 5)
617
618/** TPIDR_EL0 register - RW. */
619#define ARMV8_AARCH64_SYSREG_TPIDR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 2)
620/** TPIDRRO_EL0 register - RO. */
621#define ARMV8_AARCH64_SYSREG_TPIDRRO_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 3)
622
623/** CNTFRQ_EL0 register - RW. */
624#define ARMV8_AARCH64_SYSREG_CNTFRQ_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 0)
625/** CNTVCT_EL0 register - RW. */
626#define ARMV8_AARCH64_SYSREG_CNTVCT_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 2)
627
628/** CNTP_TVAL_EL0 register - RW. */
629#define ARMV8_AARCH64_SYSREG_CNTP_TVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 0)
630/** CNTP_CTL_EL0 register - RW. */
631#define ARMV8_AARCH64_SYSREG_CNTP_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 1)
632/** CNTP_CVAL_EL0 register - RW. */
633#define ARMV8_AARCH64_SYSREG_CNTP_CVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 2)
634
635/** CNTV_CTL_EL0 register - RW. */
636#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
637
638/** VPIDR_EL2 register - RW. */
639#define ARMV8_AARCH64_SYSREG_VPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 0)
640/** VMPIDR_EL2 register - RW. */
641#define ARMV8_AARCH64_SYSREG_VMPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 5)
642
643/** SCTLR_EL2 register - RW. */
644#define ARMV8_AARCH64_SYSREG_SCTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 0)
645/** ACTLR_EL2 register - RW. */
646#define ARMV8_AARCH64_SYSREG_ACTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 1)
647
648/** HCR_EL2 register - RW. */
649#define ARMV8_AARCH64_SYSREG_HCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 0)
650/** MDCR_EL2 register - RW. */
651#define ARMV8_AARCH64_SYSREG_MDCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 1)
652/** CPTR_EL2 register - RW. */
653#define ARMV8_AARCH64_SYSREG_CPTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 2)
654/** HSTR_EL2 register - RW. */
655#define ARMV8_AARCH64_SYSREG_HSTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 3)
656/** HFGRTR_EL2 register - RW. */
657#define ARMV8_AARCH64_SYSREG_HFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 4)
658/** HFGWTR_EL2 register - RW. */
659#define ARMV8_AARCH64_SYSREG_HFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 5)
660/** HFGITR_EL2 register - RW. */
661#define ARMV8_AARCH64_SYSREG_HFGITR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 6)
662/** HACR_EL2 register - RW. */
663#define ARMV8_AARCH64_SYSREG_HACR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 7)
664
665/** ZCR_EL2 register - RW. */
666#define ARMV8_AARCH64_SYSREG_ZCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 0)
667/** TRFCR_EL2 register - RW. */
668#define ARMV8_AARCH64_SYSREG_TRFCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 1)
669/** HCRX_EL2 register - RW. */
670#define ARMV8_AARCH64_SYSREG_HCRX_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 2)
671
672/** SDER32_EL2 register - RW. */
673#define ARMV8_AARCH64_SYSREG_SDER32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 3, 0)
674
675/** TTBR0_EL2 register - RW. */
676#define ARMV8_AARCH64_SYSREG_TTBR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 0)
677/** TTBR1_EL2 register - RW. */
678#define ARMV8_AARCH64_SYSREG_TTBR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 1)
679/** TCR_EL2 register - RW. */
680#define ARMV8_AARCH64_SYSREG_TCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 2)
681
682/** VTTBR_EL2 register - RW. */
683#define ARMV8_AARCH64_SYSREG_VTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 0)
684/** VTCR_EL2 register - RW. */
685#define ARMV8_AARCH64_SYSREG_VTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 2)
686
687/** VNCR_EL2 register - RW. */
688#define ARMV8_AARCH64_SYSREG_VNCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 2, 0)
689
690/** VSTTBR_EL2 register - RW. */
691#define ARMV8_AARCH64_SYSREG_VSTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 0)
692/** VSTCR_EL2 register - RW. */
693#define ARMV8_AARCH64_SYSREG_VSTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 2)
694
695/** DACR32_EL2 register - RW. */
696#define ARMV8_AARCH64_SYSREG_DACR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 0, 0)
697
698/** HDFGRTR_EL2 register - RW. */
699#define ARMV8_AARCH64_SYSREG_HDFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 4)
700/** HDFGWTR_EL2 register - RW. */
701#define ARMV8_AARCH64_SYSREG_HDFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 5)
702/** HAFGRTR_EL2 register - RW. */
703#define ARMV8_AARCH64_SYSREG_HAFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 6)
704
705/** SPSR_EL2 register - RW. */
706#define ARMV8_AARCH64_SYSREG_SPSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 0)
707/** ELR_EL2 register - RW. */
708#define ARMV8_AARCH64_SYSREG_ELR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 1)
709
710/** SP_EL1 register - RW. */
711#define ARMV8_AARCH64_SYSREG_SP_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 1, 0)
712
713/** IFSR32_EL2 register - RW. */
714#define ARMV8_AARCH64_SYSREG_IFSR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 0, 1)
715
716/** AFSR0_EL2 register - RW. */
717#define ARMV8_AARCH64_SYSREG_AFSR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 0)
718/** AFSR1_EL2 register - RW. */
719#define ARMV8_AARCH64_SYSREG_AFSR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 1)
720
721/** ESR_EL2 register - RW. */
722#define ARMV8_AARCH64_SYSREG_ESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 0)
723/** VSESR_EL2 register - RW. */
724#define ARMV8_AARCH64_SYSREG_VSESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 3)
725
726/** FPEXC32_EL2 register - RW. */
727#define ARMV8_AARCH64_SYSREG_FPEXC32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 3, 0)
728
729/** TFSR_EL2 register - RW. */
730#define ARMV8_AARCH64_SYSREG_TFSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 6, 0)
731
732/** FAR_EL2 register - RW. */
733#define ARMV8_AARCH64_SYSREG_FAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 0)
734/** HPFAR_EL2 register - RW. */
735#define ARMV8_AARCH64_SYSREG_HPFAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 4)
736
737/** PMSCR_EL2 register - RW. */
738#define ARMV8_AARCH64_SYSREG_PMSCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 9, 9, 0)
739
740/** MAIR_EL2 register - RW. */
741#define ARMV8_AARCH64_SYSREG_MAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 2, 0)
742
743/** AMAIR_EL2 register - RW. */
744#define ARMV8_AARCH64_SYSREG_AMAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 3, 0)
745
746/** MPAMHCR_EL2 register - RW. */
747#define ARMV8_AARCH64_SYSREG_MPAMHCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 0)
748/** MPAMVPMV_EL2 register - RW. */
749#define ARMV8_AARCH64_SYSREG_MPAMVPMV_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 1)
750
751/** MPAM2_EL2 register - RW. */
752#define ARMV8_AARCH64_SYSREG_MPAM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 5, 0)
753
754/** MPAMVPM0_EL2 register - RW. */
755#define ARMV8_AARCH64_SYSREG_MPAMVPM0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 0)
756/** MPAMVPM1_EL2 register - RW. */
757#define ARMV8_AARCH64_SYSREG_MPAMVPM1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 1)
758/** MPAMVPM2_EL2 register - RW. */
759#define ARMV8_AARCH64_SYSREG_MPAMVPM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 2)
760/** MPAMVPM3_EL2 register - RW. */
761#define ARMV8_AARCH64_SYSREG_MPAMVPM3_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 3)
762/** MPAMVPM4_EL2 register - RW. */
763#define ARMV8_AARCH64_SYSREG_MPAMVPM4_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 4)
764/** MPAMVPM5_EL2 register - RW. */
765#define ARMV8_AARCH64_SYSREG_MPAMVPM5_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 5)
766/** MPAMVPM6_EL2 register - RW. */
767#define ARMV8_AARCH64_SYSREG_MPAMVPM6_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 6)
768/** MPAMVPM7_EL2 register - RW. */
769#define ARMV8_AARCH64_SYSREG_MPAMVPM7_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 7)
770
771/** VBAR_EL2 register - RW. */
772#define ARMV8_AARCH64_SYSREG_VBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 0)
773/** RVBAR_EL2 register - RW. */
774#define ARMV8_AARCH64_SYSREG_RVBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 1)
775/** RMR_EL2 register - RW. */
776#define ARMV8_AARCH64_SYSREG_RMR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 2)
777
778/** VDISR_EL2 register - RW. */
779#define ARMV8_AARCH64_SYSREG_VDISR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 1, 1)
780
781/** CONTEXTIDR_EL2 register - RW. */
782#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 1)
783/** TPIDR_EL2 register - RW. */
784#define ARMV8_AARCH64_SYSREG_TPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 2)
785/** SCXTNUM_EL2 register - RW. */
786#define ARMV8_AARCH64_SYSREG_SCXTNUM_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 7)
787
788/** CNTVOFF_EL2 register - RW. */
789#define ARMV8_AARCH64_SYSREG_CNTVOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 3)
790/** CNTPOFF_EL2 register - RW. */
791#define ARMV8_AARCH64_SYSREG_CNTPOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 6)
792
793/** CNTHCTL_EL2 register - RW. */
794#define ARMV8_AARCH64_SYSREG_CNTHCTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 1, 0)
795
796/** CNTHP_TVAL_EL2 register - RW. */
797#define ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 0)
798/** CNTHP_CTL_EL2 register - RW. */
799#define ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 1)
800/** CNTHP_CVAL_EL2 register - RW. */
801#define ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 2)
802
803/** CNTHV_TVAL_EL2 register - RW. */
804#define ARMV8_AARCH64_SYSREG_CNTHV_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 0)
805/** CNTHV_CTL_EL2 register - RW. */
806#define ARMV8_AARCH64_SYSREG_CNTHV_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 1)
807/** CNTHV_CVAL_EL2 register - RW. */
808#define ARMV8_AARCH64_SYSREG_CNTHV_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 2)
809
810/** CNTHVS_TVAL_EL2 register - RW. */
811#define ARMV8_AARCH64_SYSREG_CNTHVS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 0)
812/** CNTHVS_CTL_EL2 register - RW. */
813#define ARMV8_AARCH64_SYSREG_CNTHVS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 1)
814/** CNTHVS_CVAL_EL2 register - RW. */
815#define ARMV8_AARCH64_SYSREG_CNTHVS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 2)
816
817/** CNTHPS_TVAL_EL2 register - RW. */
818#define ARMV8_AARCH64_SYSREG_CNTHPS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 0)
819/** CNTHPS_CTL_EL2 register - RW. */
820#define ARMV8_AARCH64_SYSREG_CNTHPS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 1)
821/** CNTHPS_CVAL_EL2 register - RW. */
822#define ARMV8_AARCH64_SYSREG_CNTHPS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 2)
823
824/** SP_EL2 register - RW. */
825#define ARMV8_AARCH64_SYSREG_SP_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 6, 4, 1, 0)
826
827/** SP_EL2 register - RW. */
828#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL3 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 6, 12, 12, 5)
829/** @} */
830
831
832#ifndef RT_IN_ASSEMBLER
833/**
834 * SPSR_EL2 (according to chapter C5.2.19)
835 */
836typedef union ARMV8SPSREL2
837{
838 /** The plain unsigned view. */
839 uint64_t u;
840 /** The 8-bit view. */
841 uint8_t au8[8];
842 /** The 16-bit view. */
843 uint16_t au16[4];
844 /** The 32-bit view. */
845 uint32_t au32[2];
846 /** The 64-bit view. */
847 uint64_t u64;
848} ARMV8SPSREL2;
849/** Pointer to SPSR_EL2. */
850typedef ARMV8SPSREL2 *PARMV8SPSREL2;
851/** Pointer to const SPSR_EL2. */
852typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
853#endif /* !RT_IN_ASSEMBLER */
854
855
856/** @name SPSR_EL2 (When exception is taken from AArch64 state)
857 * @{
858 */
859/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
860#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
861#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
862/** Bit 0 - SP - Selected stack pointer. */
863#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
864#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
865/** Bit 1 - Reserved (read as zero). */
866#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
867/** Bit 2 - 3 - EL - Exception level. */
868#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
869#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
870#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
871#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
872/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
873#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
874#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
875/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
876#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
877#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
878/** Bit 6 - I - FIQ interrupt mask. */
879#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
880#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
881/** Bit 7 - I - IRQ interrupt mask. */
882#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
883#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
884/** Bit 8 - A - SError interrupt mask. */
885#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
886#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
887/** Bit 9 - D - Debug Exception mask. */
888#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
889#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
890/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
891#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
892#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
893#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
894/** Bit 12 - SSBS - Speculative Store Bypass. */
895#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
896#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
897/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
898#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
899#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
900/** Bit 14 - 19 - Reserved (read as zero). */
901#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
902 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
903/** Bit 20 - IL - Illegal Execution State flag. */
904#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
905#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
906/** Bit 21 - SS - Software Step flag. */
907#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
908#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
909/** Bit 22 - PAN - Privileged Access Never flag. */
910#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
911#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
912/** Bit 23 - UAO - User Access Override flag. */
913#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
914#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
915/** Bit 24 - DIT - Data Independent Timing flag. */
916#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
917#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
918/** Bit 25 - TCO - Tag Check Override flag. */
919#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
920#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
921/** Bit 26 - 27 - Reserved (read as zero). */
922#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
923/** Bit 28 - V - Overflow condition flag. */
924#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
925#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
926/** Bit 29 - C - Carry condition flag. */
927#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
928#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
929/** Bit 30 - Z - Zero condition flag. */
930#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
931#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
932/** Bit 31 - N - Negative condition flag. */
933#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
934#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
935/** Bit 32 - 63 - Reserved (read as zero). */
936#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
937/** Checks whether the given SPSR value contains a AARCH64 execution state. */
938#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
939/** @} */
940
941/** @name Aarch64 Exception levels
942 * @{ */
943/** Exception Level 0 - User mode. */
944#define ARMV8_AARCH64_EL_0 0
945/** Exception Level 1 - Supervisor mode. */
946#define ARMV8_AARCH64_EL_1 1
947/** Exception Level 2 - Hypervisor mode. */
948#define ARMV8_AARCH64_EL_2 2
949/** @} */
950
951
952/** @name ESR_EL2 (Exception Syndrome Register, EL2)
953 * @{
954 */
955/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
956#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
957#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
958/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
959#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
960#define ARMV8_ESR_EL2_IL_BIT 25
961#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
962#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
963/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
964#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
965 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
966#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
967/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
968#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
969 | RT_BIT_64(35) | RT_BIT_64(36))
970#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
971/** @} */
972
973
974/** @name ESR_EL2 Exception Classes (EC)
975 * @{ */
976/** Unknown exception reason. */
977#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
978/** Trapped WF* instruction. */
979#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
980/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
981#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
982/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
983#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
984/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
985#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
986/** AArch32 - Trapped LDC or STC access. */
987#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
988/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
989#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
990/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
991#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
992/** AArch32 - Trapped pointer authentication instruction. */
993#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
994/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
995#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
996/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
997#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
998/** FEAT_BTI - Branch Target Exception. */
999#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
1000/** Illegal Execution State. */
1001#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
1002/** AArch32 - SVC instruction execution. */
1003#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
1004/** AArch32 - HVC instruction execution. */
1005#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
1006/** AArch32 - SMC instruction execution. */
1007#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
1008/** AArch64 - SVC instruction execution. */
1009#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
1010/** AArch64 - HVC instruction execution. */
1011#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
1012/** AArch64 - SMC instruction execution. */
1013#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
1014/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
1015#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
1016/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
1017#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
1018/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
1019#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
1020/** FEAT_TME - Exception from TSTART instruction. */
1021#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
1022/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
1023#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
1024/** FEAT_SME - Access to SME functionality trapped. */
1025#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
1026/** FEAT_RME - Exception from Granule Protection Check. */
1027#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
1028/** Instruction Abort from a lower Exception level. */
1029#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
1030/** Instruction Abort from the same Exception level. */
1031#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
1032/** PC alignment fault exception. */
1033#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
1034/** Data Abort from a lower Exception level. */
1035#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
1036/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
1037#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
1038/** SP alignment fault exception. */
1039#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
1040/** FEAT_MOPS - Memory Operation Exception. */
1041#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
1042/** AArch32 - Trapped floating point exception. */
1043#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
1044/** AArch64 - Trapped floating point exception. */
1045#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
1046/** SError interrupt. */
1047#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
1048/** Breakpoint Exception from a lower Exception level. */
1049#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
1050/** Breakpoint Exception from the same Exception level. */
1051#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
1052/** Software Step Exception from a lower Exception level. */
1053#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
1054/** Software Step Exception from the same Exception level. */
1055#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
1056/** Watchpoint Exception from a lower Exception level. */
1057#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
1058/** Watchpoint Exception from the same Exception level. */
1059#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
1060/** AArch32 - BKPT instruction execution. */
1061#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
1062/** AArch32 - Vector Catch exception. */
1063#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
1064/** AArch64 - BRK instruction execution. */
1065#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
1066/** @} */
1067
1068
1069/** @name ISS encoding for Data Abort exceptions.
1070 * @{ */
1071/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
1072#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
1073 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
1074#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
1075/** Bit 6 - WnR - Write not Read. */
1076#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
1077#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
1078/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
1079#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
1080#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
1081/** Bit 8 - CM - Cache maintenance instruction. */
1082#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
1083#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
1084/** Bit 9 - EA - External abort type. */
1085#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
1086#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
1087/** Bit 10 - FnV - FAR not Valid. */
1088#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
1089#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
1090/** Bit 11 - 12 - LST - Load/Store Type. */
1091#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
1092#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
1093/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
1094#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
1095#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
1096/** Bit 14 - AR - Acquire/Release semantics. */
1097#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
1098#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
1099/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
1100#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
1101#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
1102/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
1103#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
1104 | RT_BIT_32(19) | RT_BIT_32(20))
1105#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
1106/** Bit 21 - SSE - Syndrome Sign Extend. */
1107#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
1108#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
1109/** Bit 22 - 23 - SAS - Syndrome Access Size. */
1110#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
1111#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
1112/** Bit 24 - ISV - Instruction Syndrome Valid. */
1113#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
1114#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
1115/** @} */
1116
1117
1118/** @name Data Fault Status Code (DFSC).
1119 * @{ */
1120/** Address size fault, level 0 of translation or translation table base register. */
1121#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
1122/** Address size fault, level 1. */
1123#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
1124/** Address size fault, level 2. */
1125#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
1126/** Address size fault, level 3. */
1127#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
1128/** Translation fault, level 0. */
1129#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
1130/** Translation fault, level 1. */
1131#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
1132/** Translation fault, level 2. */
1133#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
1134/** Translation fault, level 3. */
1135#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
1136/** FEAT_LPA2 - Access flag fault, level 0. */
1137#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
1138/** Access flag fault, level 1. */
1139#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
1140/** Access flag fault, level 2. */
1141#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
1142/** Access flag fault, level 3. */
1143#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
1144/** FEAT_LPA2 - Permission fault, level 0. */
1145#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
1146/** Permission fault, level 1. */
1147#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
1148/** Permission fault, level 2. */
1149#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
1150/** Permission fault, level 3. */
1151#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
1152/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
1153#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
1154/** FEAT_MTE2 - Synchronous Tag Check Fault. */
1155#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
1156/** @todo Do the rest (lazy developer). */
1157/** @} */
1158
1159
1160/** @name SAS encoding.
1161 * @{ */
1162/** Byte access. */
1163#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
1164/** Halfword access (uint16_t). */
1165#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
1166/** Word access (uint32_t). */
1167#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
1168/** Doubleword access (uint64_t). */
1169#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
1170/** @} */
1171
1172
1173/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
1174 * @{ */
1175/** Bit 0 - Direction flag. */
1176#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
1177#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
1178/** Bit 1 - 4 - CRm value from the instruction. */
1179#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
1180 | RT_BIT_32(4))
1181#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
1182/** Bit 5 - 9 - Rt value from the instruction. */
1183#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
1184 | RT_BIT_32(8) | RT_BIT_32(9))
1185#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
1186/** Bit 10 - 13 - CRn value from the instruction. */
1187#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
1188 | RT_BIT_32(13))
1189#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
1190/** Bit 14 - 16 - Op2 value from the instruction. */
1191#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
1192#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
1193/** Bit 17 - 19 - Op2 value from the instruction. */
1194#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
1195#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
1196/** Bit 20 - 21 - Op0 value from the instruction. */
1197#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
1198#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
1199/** Bit 22 - 24 - Reserved. */
1200#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
1201/** @} */
1202
1203
1204/** @name ISS encoding for trapped HVC instruction exceptions.
1205 * @{ */
1206/** Bit 0 - 15 - imm16 value of the instruction. */
1207#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
1208#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
1209/** @} */
1210
1211
1212/** @name TCR_EL1 - Translation Control Register (EL1)
1213 * @{
1214 */
1215/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
1216#define ARMV8_TCR_EL1_AARCH64_T0SZ_MASK ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
1217 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
1218#define ARMV8_TCR_EL1_AARCH64_T0SZ_SHIFT 0
1219#define ARMV8_TCR_EL1_AARCH64_T0SZ ARMV8_TCR_EL1_AARCH64_T0SZ_MASK
1220#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
1221/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
1222#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
1223#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
1224/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1225#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
1226#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
1227/** Non cacheable. */
1228# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
1229/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1230# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
1231/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1232# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
1233/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1234# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
1235/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1236#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
1237#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
1238/** Non cacheable. */
1239# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
1240/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1241# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
1242/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1243# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
1244/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1245# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
1246/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
1247#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
1248#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
1249/** Non shareable. */
1250# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
1251/** Invalid value. */
1252# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
1253/** Outer Shareable. */
1254# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
1255/** Inner Shareable. */
1256# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
1257/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
1258#define ARMV8_TCR_EL1_AARCH64_TG0_MASK (RT_BIT_64(14) | RT_BIT_64(15))
1259#define ARMV8_TCR_EL1_AARCH64_TG0_SHIFT 14
1260#define ARMV8_TCR_EL1_AARCH64_TG0 ARMV8_TCR_EL1_AARCH64_TG0_MASK
1261#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> ARMV8_TCR_EL1_AARCH64_TG0_SHIFT)
1262/** Invalid granule size. */
1263# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
1264/** 16KiB granule size (shifted down). */
1265# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
1266/** 4KiB granule size (shifted down). */
1267# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
1268/** 64KiB granule size (shifted down). */
1269# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
1270/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
1271#define ARMV8_TCR_EL1_AARCH64_T1SZ_MASK ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
1272 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
1273#define ARMV8_TCR_EL1_AARCH64_T1SZ_SHIFT 16
1274#define ARMV8_TCR_EL1_AARCH64_T1SZ ARMV8_TCR_EL1_AARCH64_T1SZ_MASK
1275#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> ARMV8_TCR_EL1_AARCH64_T1SZ_SHIFT)
1276/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
1277#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
1278#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
1279/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
1280#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
1281#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
1282/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1283#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
1284#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
1285/** Non cacheable. */
1286# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
1287/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1288# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
1289/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1290# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
1291/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1292# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
1293/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1294#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
1295#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
1296/** Non cacheable. */
1297# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
1298/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1299# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
1300/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1301# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
1302/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1303# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
1304/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
1305#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
1306#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
1307/** Non shareable. */
1308# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
1309/** Invalid value. */
1310# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
1311/** Outer Shareable. */
1312# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
1313/** Inner Shareable. */
1314# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
1315/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
1316#define ARMV8_TCR_EL1_AARCH64_TG1_MASK (RT_BIT_64(30) | RT_BIT_64(31))
1317#define ARMV8_TCR_EL1_AARCH64_TG1_SHIFT 30
1318#define ARMV8_TCR_EL1_AARCH64_TG1 ARMV8_TCR_EL1_AARCH64_TG1_MASK
1319#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
1320/** Invalid granule size. */
1321# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
1322/** 16KiB granule size. */
1323# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
1324/** 4KiB granule size. */
1325# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
1326/** 64KiB granule size. */
1327# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
1328/** Bit 32 - 34 - Intermediate Physical Address Size. */
1329#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
1330#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
1331/** IPA - 32 bits, 4GiB. */
1332# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
1333/** IPA - 36 bits, 64GiB. */
1334# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
1335/** IPA - 40 bits, 1TiB. */
1336# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
1337/** IPA - 42 bits, 4TiB. */
1338# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
1339/** IPA - 44 bits, 16TiB. */
1340# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
1341/** IPA - 48 bits, 256TiB. */
1342# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
1343/** IPA - 52 bits, 4PiB. */
1344# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
1345/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
1346#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
1347#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
1348/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
1349#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
1350#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
1351/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
1352#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
1353#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
1354/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
1355#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
1356#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
1357/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
1358#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
1359#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
1360/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
1361#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
1362#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
1363/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
1364#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
1365#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
1366/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
1367#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
1368#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
1369/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
1370#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
1371#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
1372/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
1373#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
1374#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
1375/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
1376#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
1377#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
1378/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
1379#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
1380#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
1381/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
1382#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
1383#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
1384/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
1385#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1386#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1387/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1388#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1389#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1390/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1391#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1392#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1393/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1394#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1395#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1396/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1397#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1398#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1399/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1400#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1401#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1402/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1403#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1404#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1405/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1406#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1407#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1408/** Bit 57 - TCMA0 */
1409#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1410#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1411/** Bit 58 - TCMA1 */
1412#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1413#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1414/** Bit 59 - Data Sharing(?). */
1415#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1416#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1417/** @} */
1418
1419
1420/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1421 * @{
1422 */
1423/** Bit 0 - Common not Private (FEAT_TTCNP). */
1424#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1425#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1426/** Bit 1 - 47 - Translation table base address. */
1427#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1428#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) ((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR)
1429/** Bit 48 - 63 - ASID. */
1430#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1431#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1432/** @} */
1433
1434
1435/** @name MDSCR_EL1 - MOnitor Debug System Control Register (EL1).
1436 * @{ */
1437/** Bit 0 - SS - Software step control bit. */
1438#define ARMV8_MDSCR_EL1_AARCH64_SS RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_SS_BIT)
1439#define ARMV8_MDSCR_EL1_AARCH64_SS_BIT 0
1440/** Bit 6 - ERR. */
1441#define ARMV8_MDSCR_EL1_AARCH64_ERR RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_ERR_BIT)
1442#define ARMV8_MDSCR_EL1_AARCH64_ERR_BIT 6
1443/** Bit 12 - TDCC. */
1444#define ARMV8_MDSCR_EL1_AARCH64_TDCC RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TDCC_BIT)
1445#define ARMV8_MDSCR_EL1_AARCH64_TDCC_BIT 12
1446/** Bit 13 - KDE - Kernel Debugging Enabled. */
1447#define ARMV8_MDSCR_EL1_AARCH64_KDE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_KDE_BIT)
1448#define ARMV8_MDSCR_EL1_AARCH64_KDE_BIT 13
1449/** Bit 14 - HDE. */
1450#define ARMV8_MDSCR_EL1_AARCH64_HDE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_HDE_BIT)
1451#define ARMV8_MDSCR_EL1_AARCH64_HDE_BIT 14
1452/** Bit 15 - MDE. */
1453#define ARMV8_MDSCR_EL1_AARCH64_MDE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_MDE_BIT)
1454#define ARMV8_MDSCR_EL1_AARCH64_MDE_BIT 15
1455/** Bit 19 - SC2. */
1456#define ARMV8_MDSCR_EL1_AARCH64_SC2 RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_SC2_BIT)
1457#define ARMV8_MDSCR_EL1_AARCH64_SC2_BIT 19
1458/** Bit 21 - TDA. */
1459#define ARMV8_MDSCR_EL1_AARCH64_TDA RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TDA_BIT)
1460#define ARMV8_MDSCR_EL1_AARCH64_TDA_BIT 21
1461/** Bits 23:22 - INTdis. */
1462#define ARMV8_MDSCR_EL1_AARCH64_INTDIS_MASK UINT64_C(0x00c00000)
1463#define ARMV8_MDSCR_EL1_AARCH64_INTDIS_SHIFT 22
1464/** Bit 26 - TXU. */
1465#define ARMV8_MDSCR_EL1_AARCH64_TXU RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TXU_BIT)
1466#define ARMV8_MDSCR_EL1_AARCH64_TXU_BIT 26
1467/** Bit 29 - TXfull. */
1468#define ARMV8_MDSCR_EL1_AARCH64_TXFULL RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TXFULL_BIT)
1469#define ARMV8_MDSCR_EL1_AARCH64_TXFULL_BIT 29
1470/** Bit 30 - RXfull. */
1471#define ARMV8_MDSCR_EL1_AARCH64_RXFULL RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_RXFULL_BIT)
1472#define ARMV8_MDSCR_EL1_AARCH64_RXFULL_BIT 30
1473/** Bit 31 - TFO. */
1474#define ARMV8_MDSCR_EL1_AARCH64_TFO RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TFO_BIT)
1475#define ARMV8_MDSCR_EL1_AARCH64_TFO_BIT 31
1476/** Bit 32 - EMBWE. */
1477#define ARMV8_MDSCR_EL1_AARCH64_EMBWE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_EMBWE_BIT)
1478#define ARMV8_MDSCR_EL1_AARCH64_EMBWE_BIT 32
1479/** Bit 33 - TTA. */
1480#define ARMV8_MDSCR_EL1_AARCH64_TTA RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TTA_BIT)
1481#define ARMV8_MDSCR_EL1_AARCH64_TTA_BIT 33
1482/** Bit 34 - EnSPM. */
1483#define ARMV8_MDSCR_EL1_AARCH64_ENSPM RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_ENSPM_BIT)
1484#define ARMV8_MDSCR_EL1_AARCH64_ENSPM_BIT 34
1485/** Bit 35 - EHBWE. */
1486#define ARMV8_MDSCR_EL1_AARCH64_EHBWE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_EHBWE_BIT)
1487#define ARMV8_MDSCR_EL1_AARCH64_EHBWE_BIT 35
1488/** Bit 50 - EnSTEPOP. */
1489#define ARMV8_MDSCR_EL1_AARCH64_ENSTEPOP RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_ENSTEPOP_BIT)
1490#define ARMV8_MDSCR_EL1_AARCH64_ENSTEPOP_BIT 50
1491/** @} */
1492
1493
1494/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1495 * @{ */
1496/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1497#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1498#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1499#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1500/** @} */
1501
1502
1503/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1504 * @{ */
1505/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1506#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1507#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1508#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1509/** @} */
1510
1511
1512/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1513 * @{ */
1514/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1515#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1516#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1517#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1518/** @} */
1519
1520
1521/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1522 * @{ */
1523/** Bit 0 - Common Binary Pointer Register - RW. */
1524#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1525#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1526/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1527#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1528#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1529/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1530#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1531#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1532/** Bit 8 - 10 - Priority bits - RO. */
1533#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1534#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1535/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1536#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1537#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1538/** INTIDS are 16-bit wide. */
1539# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1540/** INTIDS are 24-bit wide. */
1541# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1542/** Bit 14 - SEI Supported - RO. */
1543#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1544#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1545/** Bit 15 - Affinity 3 Valid - RO. */
1546#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1547#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1548/** Bit 18 - Range Selector Support - RO. */
1549#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1550#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1551/** Bit 19 - Extended INTID range supported - RO. */
1552#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1553#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1554/** All RW bits. */
1555#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1556/** All RO bits (including Res0). */
1557#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1558/** @} */
1559
1560
1561/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1562 * @{ */
1563/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1564#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1565#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1566/** @} */
1567
1568
1569/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1570 * @{ */
1571/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1572#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1573#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1574/** @} */
1575
1576
1577/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1578 * @{ */
1579/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1580#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1581#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1582/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1583#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1584#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1585/** Bit 24 - 27 - The INTID of the SGI. */
1586#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1587#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1588/* Bit 28 - 31 - Reserved. */
1589/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1590#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1591#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1592/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1593#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1594#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1595/* Bit 41 - 43 - Reserved. */
1596/** Bit 44 - 47 - Range selector. */
1597#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1598#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1599/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1600#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1601#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1602/* Bit 56 - 63 - Reserved. */
1603/** @} */
1604
1605
1606/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1607 * @{ */
1608/** Bit 0 - Enables the timer. */
1609#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1610#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1611/** Bit 1 - Timer interrupt mask bit. */
1612#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1613#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1614/** Bit 2 - Timer status bit. */
1615#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1616#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1617/** @} */
1618
1619
1620/** @name OSLAR_EL1 - OS Lock Access Register.
1621 * @{ */
1622/** Bit 0 - The OS Lock status bit. */
1623#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1624#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1625/** @} */
1626
1627
1628/** @name OSLSR_EL1 - OS Lock Status Register.
1629 * @{ */
1630/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1631#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1632#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1633/** Bit 1 - The OS Lock status bit. */
1634#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1635#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1636/** Bit 2 - Not 32-bit access. */
1637#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1638#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1639/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1640#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1641#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1642/** @} */
1643
1644
1645/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1646 * @{ */
1647/* Bit 0 - 3 - Reserved. */
1648/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1649#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1650#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1651/** No AES instructions implemented. */
1652# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1653/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1654# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1655/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1656# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1657/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1658#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1659#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1660/** No SHA1 instructions implemented. */
1661# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1662/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1663# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1664/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1665#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1666#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1667/** No SHA2 instructions implemented. */
1668# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1669/** SHA256 instructions implemented (FEAT_SHA256). */
1670# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1671/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1672# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1673/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1674#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1675#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1676/** No CRC32 instructions implemented. */
1677# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1678/** CRC32 instructions implemented (FEAT_CRC32). */
1679# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1680/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1681#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1682#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1683/** No Atomic instructions implemented. */
1684# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1685/** Atomic instructions implemented (FEAT_LSE). */
1686# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1687/** Bit 24 - 27 - Indicates support for TME instructions. */
1688#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1689#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1690/** TME instructions are not implemented. */
1691# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1692/** TME instructions are implemented. */
1693# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1694/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1695#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1696#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1697/** No RDMA instructions implemented. */
1698# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1699/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1700# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1701/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1702#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1703#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1704/** No SHA3 instructions implemented. */
1705# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1706/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1707# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1708/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1709#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1710#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1711/** No SM3 instructions implemented. */
1712# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1713/** SM3 instructions implemented (FEAT_SM3). */
1714# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1715/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1716#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1717#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1718/** No SM4 instructions implemented. */
1719# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1720/** SM4 instructions implemented (FEAT_SM4). */
1721# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1722/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1723#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1724#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1725/** No Dot Product instructions implemented. */
1726# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1727/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1728# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1729/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1730#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1731#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1732/** FMLAL and FMLSL instructions are not implemented. */
1733# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1734/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1735# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1736/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1737#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1738#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1739/** No flag manipulation instructions implemented. */
1740# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1741/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1742# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1743/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1744# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1745/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1746#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1747#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1748/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1749# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1750/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1751# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1752/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1753# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1754/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1755#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1756#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1757/** No Random Number instructions implemented. */
1758# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1759/** RNDR and RDNRRS registers are implemented . */
1760# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1761/** @} */
1762
1763
1764/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1765 * @{ */
1766/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1767#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1768#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1769/** DC CVAP not supported. */
1770# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1771/** DC CVAP supported (FEAT_DPB). */
1772# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1773/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1774# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1775/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1776#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1777#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1778/** Address Authentication using the QARMA5 algorithm is not implemented. */
1779# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1780/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1781# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1782/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1783# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1784/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1785# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1786/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1787# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1788/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1789# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1790/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1791#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1792#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1793/** Address Authentication using the QARMA5 algorithm is not implemented. */
1794# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1795/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1796# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1797/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1798# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1799/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1800# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1801/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1802# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1803/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1804# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1805/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1806#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1807#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1808/** No FJCVTZS instruction implemented. */
1809# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1810/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1811# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1812/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1813#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1814#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1815/** No FCMLA and FCADD instructions implemented. */
1816# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1817/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1818# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1819/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1820#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1821#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1822/** No RCpc instructions implemented. */
1823# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1824/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1825# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1826/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1827# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1828/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1829#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1830#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1831/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1832# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1833/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1834# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1835/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1836#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1837#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1838/** Generic Authentication using an implementation defined algorithm is not implemented. */
1839# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1840/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1841# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1842/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1843#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1844#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1845/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1846# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1847/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1848# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1849/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1850#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1851#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1852/** No SB instructions implemented. */
1853# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1854/** SB instructions implemented (FEAT_SB). */
1855# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1856/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1857#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1858#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1859/** Prediction invalidation instructions are not implemented. */
1860# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1861/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1862# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1863/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1864#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1865#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1866/** BFloat16 instructions are not implemented. */
1867# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1868/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1869# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1870/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1871# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1872/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1873#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1874#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1875/** Data Gathering Hint instructions are not implemented. */
1876# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1877/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1878# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1879/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1880#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1881#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1882/** No Int8 matrix multiplication instructions implemented. */
1883# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1884/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1885# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1886/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1887#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1888#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1889/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1890# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1891/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1892# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1893/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1894#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1895#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1896/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1897# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1898/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1899# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1900/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1901# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1902/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1903# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1904/** @} */
1905
1906
1907/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1908 * @{ */
1909/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1910#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1911#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1912/** WFET and WFIT are not supported. */
1913# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1914/** WFET and WFIT are supported (FEAT_WFxT). */
1915# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1916/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1917#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1918#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1919/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1920# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1921/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1922# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1923/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1924#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1925#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1926/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1927# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1928/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1929# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1930/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1931#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1932#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1933/** Address Authentication using the QARMA3 algorithm is not implemented. */
1934# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1935/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1936# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1937/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1938# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1939/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1940# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1941/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1942# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1943/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1944# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1945/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1946#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1947#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1948/** No Memory Copy and Memory Set instructions implemented. */
1949# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1950/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1951# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1952/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1953#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1954#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1955/** BC instruction is not implemented. */
1956# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1957/** BC instruction is implemented (FEAT_HBC). */
1958# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1959/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1960#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1961#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1962/** ConstPACField() returns FALSE. */
1963# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1964/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1965# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1966/* Bit 28 - 63 - Reserved. */
1967/** @} */
1968
1969
1970/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1971 * @{ */
1972/** Bit 0 - 3 - EL0 Exception level handling. */
1973#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1974#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1975/** EL0 can be executed in AArch64 state only. */
1976# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1977/** EL0 can be executed in AArch64 and AArch32 state. */
1978# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1979/** Bit 4 - 7 - EL1 Exception level handling. */
1980#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1981#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1982/** EL1 can be executed in AArch64 state only. */
1983# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1984/** EL1 can be executed in AArch64 and AArch32 state. */
1985# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1986/** Bit 8 - 11 - EL2 Exception level handling. */
1987#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1988#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1989/** EL2 is not implemented. */
1990# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1991/** EL2 can be executed in AArch64 state only. */
1992# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1993/** EL2 can be executed in AArch64 and AArch32 state. */
1994# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1995/** Bit 12 - 15 - EL3 Exception level handling. */
1996#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1997#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1998/** EL3 is not implemented. */
1999# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
2000/** EL3 can be executed in AArch64 state only. */
2001# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
2002/** EL3 can be executed in AArch64 and AArch32 state. */
2003# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
2004/** Bit 16 - 19 - Floating-point support. */
2005#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2006#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
2007/** Floating-point is implemented and support single and double precision. */
2008# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
2009/** Floating-point is implemented and support single, double and half precision. */
2010# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
2011/** Floating-point is not implemented. */
2012# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
2013/** Bit 20 - 23 - Advanced SIMD support. */
2014#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2015#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
2016/** Advanced SIMD is implemented and support single and double precision. */
2017# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
2018/** Advanced SIMD is implemented and support single, double and half precision. */
2019# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
2020/** Advanced SIMD is not implemented. */
2021# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
2022/** Bit 24 - 27 - System register GIC CPU interface support. */
2023#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2024#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
2025/** GIC CPU interface system registers are not implemented. */
2026# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
2027/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
2028# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
2029/** System register interface to version 4.1 of the GIC CPU interface is supported. */
2030# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
2031/** Bit 28 - 31 - RAS Extension version. */
2032#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2033#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
2034/** No RAS extension. */
2035# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
2036/** RAS Extension implemented. */
2037# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
2038/** FEAT_RASv1p1 implemented. */
2039# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
2040/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
2041#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2042#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
2043/** SVE is not supported. */
2044# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
2045/** SVE is supported. */
2046# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
2047/** Bit 36 - 39 - Secure EL2 support. */
2048#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2049#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
2050/** Secure EL2 is not supported. */
2051# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
2052/** Secure EL2 is implemented. */
2053# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
2054/** Bit 40 - 43 - MPAM support. */
2055#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2056#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
2057/** MPAM extension major version number is 0. */
2058# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
2059/** MPAM extension major version number is 1. */
2060# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
2061/** Bit 44 - 47 - Activity Monitor Extension support. */
2062#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2063#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
2064/** Activity Monitor extension is not implemented. */
2065# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
2066/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
2067# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
2068/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
2069# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
2070/** Bit 48 - 51 - Data Independent Timing support. */
2071#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2072#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
2073/** AArch64 does not guarantee constant execution time of any instructions. */
2074# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
2075/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
2076# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
2077/** Bit 52 - 55 - Realm Management Extension support. */
2078#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2079#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
2080/** Realm Management Extension not implemented. */
2081# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
2082/** RMEv1 is implemented (FEAT_RME). */
2083# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
2084/** Bit 56 - 59 - Speculative use out of context branch targets support. */
2085#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2086#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
2087/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
2088# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
2089/** FEAT_CSV2 is implemented. */
2090# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
2091/** FEAT_CSV2_2 is implemented. */
2092# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
2093/** FEAT_CSV2_3 is implemented. */
2094# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
2095/** Bit 60 - 63 - Speculative use of faulting data support. */
2096#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2097#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
2098/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
2099# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
2100/** FEAT_CSV3 is supported . */
2101# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
2102/** @} */
2103
2104
2105/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
2106 * @{ */
2107/** Bit 0 - 3 - Branch Target Identification support. */
2108#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2109#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
2110/** The Branch Target Identification mechanism is not implemented. */
2111# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
2112/** The Branch Target Identifcation mechanism is implemented. */
2113# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
2114/** Bit 4 - 7 - Speculative Store Bypassing control support. */
2115#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2116#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
2117/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
2118# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
2119/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
2120# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
2121/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
2122 * to directly read and write the PSTATE.SSBS field. */
2123# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
2124/** Bit 8 - 11 - Memory Tagging Extension support. */
2125#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2126#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
2127/** MTE is not implemented. */
2128# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
2129/** Instruction only Memory Tagging Extensions implemented. */
2130# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
2131/** Full Memory Tagging Extension implemented. */
2132# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
2133/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
2134# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
2135/** Bit 12 - 15 - RAS Extension fractional field. */
2136#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2137#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
2138/** RAS Extension is implemented. */
2139# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
2140/** FEAT_RASv1p1 is implemented. */
2141# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
2142/** Bit 16 - 19 - MPAM minor version number. */
2143#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2144#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
2145/** The minor version of number of the MPAM extension is 0. */
2146# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
2147/** The minor version of number of the MPAM extension is 1. */
2148# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
2149/* Bit 20 - 23 - Reserved. */
2150/** Bit 24 - 27 - Scalable Matrix Extension support. */
2151#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2152#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
2153/** Scalable Matrix Extensions are not implemented. */
2154# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
2155/** Scalable Matrix Extensions are implemented (FEAT_SME). */
2156# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
2157/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
2158# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
2159/** Bit 28 - 31 - Random Number trap to EL3 support. */
2160#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2161#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
2162/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
2163# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
2164/** Trapping of RNDR and RDNRRS to EL3 is supported. */
2165# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
2166/** Bit 32 - 35 - CSV2 fractional field. */
2167#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2168#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
2169/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
2170# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
2171/** FEAT_CSV2_1p1 is implemented. */
2172# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
2173/** FEAT_CSV2_1p2 is implemented. */
2174# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
2175/** Bit 36 - 39 - Non-maskable Interrupt support. */
2176#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2177#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
2178/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
2179# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
2180/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
2181# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
2182/** @} */
2183
2184
2185/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
2186 * @{ */
2187/** Bit 0 - 3 - Physical Address range supported. */
2188#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2189#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
2190/** Physical Address range is 32 bits, 4GiB. */
2191# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
2192/** Physical Address range is 36 bits, 64GiB. */
2193# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
2194/** Physical Address range is 40 bits, 1TiB. */
2195# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
2196/** Physical Address range is 42 bits, 4TiB. */
2197# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
2198/** Physical Address range is 44 bits, 16TiB. */
2199# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
2200/** Physical Address range is 48 bits, 256TiB. */
2201# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
2202/** Physical Address range is 52 bits, 4PiB. */
2203# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
2204/** Bit 4 - 7 - Number of ASID bits. */
2205#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2206#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
2207/** ASID bits is 8. */
2208# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
2209/** ASID bits is 16. */
2210# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
2211/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
2212#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2213#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
2214/** No mixed-endian support. */
2215# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
2216/** Mixed-endian supported. */
2217# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
2218/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
2219#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2220#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
2221/** No distinction between Secure and Non-secure Memory supported. */
2222# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
2223/** Distinction between Secure and Non-secure Memory supported. */
2224# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
2225/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
2226#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2227#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
2228/** No mixed-endian support at EL0. */
2229# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
2230/** Mixed-endian support at EL0. */
2231# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
2232/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
2233#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2234#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
2235/** 16KiB granule size not supported. */
2236# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
2237/** 16KiB granule size is supported. */
2238# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
2239/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2240# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
2241/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
2242#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2243#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
2244/** 64KiB granule supported. */
2245# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
2246/** 64KiB granule not supported. */
2247# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
2248/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
2249#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2250#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
2251/** 4KiB granule supported. */
2252# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
2253/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2254# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
2255/** 4KiB granule not supported. */
2256# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
2257/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
2258#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2259#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
2260/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
2261# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
2262/** 16KiB granule not supported at stage 2. */
2263# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
2264/** 16KiB granule supported at stage 2. */
2265# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
2266/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2267# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
2268/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
2269#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2270#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
2271/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
2272# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
2273/** 64KiB granule not supported at stage 2. */
2274# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
2275/** 64KiB granule supported at stage 2. */
2276# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
2277/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2278#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2279#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
2280/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
2281# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
2282/** 4KiB granule not supported at stage 2. */
2283# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
2284/** 4KiB granule supported at stage 2. */
2285# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
2286/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2287# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
2288/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
2289#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2290#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
2291/** All exception entries and exits are context synchronization events. */
2292# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
2293/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
2294# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
2295/* Bit 48 - 55 - Reserved. */
2296/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
2297#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2298#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
2299/** Fine-grained trap controls are not implemented. */
2300# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
2301/** Fine-grained trap controls are implemented (FEAT_FGT). */
2302# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
2303/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
2304#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2305#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
2306/** Enhanced Counter Virtualization is not implemented. */
2307# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
2308/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
2309# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
2310/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
2311# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
2312/** @} */
2313
2314
2315/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
2316 * @{ */
2317/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
2318#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2319#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
2320/** Hardware update of the Access flag and dirty state are not supported. */
2321# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
2322/** Support for hardware update of the Access flag for Block and Page descriptors. */
2323# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
2324/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
2325# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
2326/** Bit 4 - 7 - EL1 Exception level handling. */
2327#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2328#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
2329/** VMID bits is 8. */
2330# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
2331/** VMID bits is 16 (FEAT_VMID16). */
2332# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
2333/** Bit 8 - 11 - Virtualization Host Extensions support. */
2334#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2335#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
2336/** Virtualization Host Extensions are not supported. */
2337# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
2338/** Virtualization Host Extensions are supported. */
2339# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
2340/** Bit 12 - 15 - Hierarchical Permission Disables. */
2341#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2342#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
2343/** Disabling of hierarchical controls not supported. */
2344# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
2345/** Disabling of hierarchical controls supported (FEAT_HPDS). */
2346# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
2347/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
2348# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
2349/** Bit 16 - 19 - LORegions support. */
2350#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2351#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
2352/** LORegions not supported. */
2353# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
2354/** LORegions supported. */
2355# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
2356/** Bit 20 - 23 - Privileged Access Never support. */
2357#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2358#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
2359/** PAN not supported. */
2360# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
2361/** PAN supported (FEAT_PAN). */
2362# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
2363/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
2364# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
2365/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
2366# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
2367/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
2368#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2369#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
2370/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
2371# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
2372/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
2373# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
2374/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
2375#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2376#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
2377/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
2378# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
2379/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
2380# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
2381/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
2382#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2383#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
2384/** Configurable delayed trapping of WFE is not supported. */
2385# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
2386/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
2387# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
2388/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
2389#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2390#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
2391/** Enhanced Translation Synchronization is not supported. */
2392# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
2393/** Enhanced Translation Synchronization is implemented. */
2394# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
2395/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2396#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2397#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
2398/** HCRX_EL2 and its associated EL3 trap are not supported. */
2399# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
2400/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
2401# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
2402/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
2403#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2404#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
2405/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
2406# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
2407/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
2408# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
2409/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
2410#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2411#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
2412/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
2413# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
2414/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
2415# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
2416/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
2417#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2418#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
2419/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
2420# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
2421/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
2422# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
2423/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
2424#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2425#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
2426/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
2427# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
2428/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
2429# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
2430/* Bit 60 - 63 - Reserved. */
2431/** @} */
2432
2433
2434/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
2435 * @{ */
2436/** Bit 0 - 3 - Indicates support for Common not Private translations. */
2437#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2438#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
2439/** Common not Private translations are not supported. */
2440# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
2441/** Support for Common not Private translations (FEAT_TTNCP). */
2442# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
2443/** Bit 4 - 7 - Indicates support for User Access Override. */
2444#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2445#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2446/** User Access Override is not supported. */
2447# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2448/** User Access Override is supported (FEAT_UAO). */
2449# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2450/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2451#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2452#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2453/** LSMAOE and nTLSMD bits are not supported. */
2454# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2455/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2456# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2457/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2458#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2459#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2460/** IESB bit is not supported. */
2461# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2462/** IESB bit is supported (FEAT_IESB). */
2463# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2464/** Bit 16 - 19 - Indicates support for larger virtual address. */
2465#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2466#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2467/** Virtual address range is 48 bits. */
2468# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2469/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2470# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2471/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2472#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2473#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2474/** CCSIDR_EL1 register format is 32-bit. */
2475# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2476/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2477# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2478/** Bit 24 - 27 - Indicates support for nested virtualization. */
2479#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2480#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2481/** Nested virtualization is not supported. */
2482# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2483/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2484# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2485/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2486# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2487/** Bit 28 - 31 - Indicates support for small translation tables. */
2488#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2489#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2490/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2491# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2492/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2493# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2494/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2495#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2496#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2497/** Unaligned single-copy atomicity and atomic functions are not supported. */
2498# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2499/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2500# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2501/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2502#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2503#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2504/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2505# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2506/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2507# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2508/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2509#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2510#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2511/** HCR_EL2.FWB bit is not supported. */
2512# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2513/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2514# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2515/* Bit 44 - 47 - Reserved. */
2516/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2517#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2518#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2519/** TLB maintenance instructions by address have bits [47:44] Res0. */
2520# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2521/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2522# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2523/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2524 * changing block size for a translation. */
2525#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2526#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2527/** Level 0 support for changing block size is supported (FEAT_BBM). */
2528# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2529/** Level 1 support for changing block size is supported (FEAT_BBM). */
2530# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2531/** Level 2 support for changing block size is supported (FEAT_BBM). */
2532# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2533/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2534#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2535#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2536/** Enhanced Virtualization Traps are not supported. */
2537# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2538/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2539# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2540/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2541# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2542/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2543#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2544#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2545/** E0PDx mechanism is not supported. */
2546# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2547/** E0PDx mechanism is supported (FEAT_E0PD). */
2548# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2549/** @} */
2550
2551
2552/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2553 * @{ */
2554/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2555#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2556#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2557/** Armv8 debug architecture version. */
2558# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2559/** Armv8 debug architecture version with virtualization host extensions. */
2560# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2561/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2562# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2563/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2564# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2565/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2566# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2567/** Bit 4 - 7 - Indicates trace support. */
2568#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2569#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2570/** Trace unit System registers not implemented. */
2571# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2572/** Trace unit System registers supported. */
2573# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2574/** Bit 8 - 11 - Performance Monitors Extension version. */
2575#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2576#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2577/** Performance Monitors Extension not supported. */
2578# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2579/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2580# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2581/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2582# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2583/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2584# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2585/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2586# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2587/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2588# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2589/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2590# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2591/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2592#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2593#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2594/* Bit 16 - 19 - Reserved 0. */
2595/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2596#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2597#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2598/* Bit 24 - 27 - Reserved 0. */
2599/** Bit 28 - 31 - Number of context-aware breakpoints. */
2600#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2601#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2602/** Bit 32 - 35 - Statistical Profiling Extension version. */
2603#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2604#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2605/** Statistical Profiling Extension not implemented. */
2606# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2607/** Statistical Profiling Extension supported (FEAT_SPE). */
2608# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2609/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2610# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2611/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2612# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2613/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2614# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2615/** Bit 36 - 39 - OS Double Lock implemented. */
2616#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2617#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2618/** OS Double Lock is not implemented. */
2619# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2620/** OS Double Lock is supported (FEAT_DoubleLock). */
2621# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2622/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2623#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2624#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2625/** Armv8.4 self-hosted Trace Extension not implemented. */
2626# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2627/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2628# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2629/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2630#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2631#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2632/** Trace Buffer Extension is not implemented. */
2633# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2634/** Trace Buffer Extension is supported (FEAT_TRBE). */
2635# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2636/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2637#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2638#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2639/** Multi-threaded PMU extension is not implemented. */
2640# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2641/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2642# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2643/** Multi-threaded PMU extension is not implemented. */
2644# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2645/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2646#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2647#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2648/** Branch Record Buffer extension is not implemented. */
2649# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2650/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2651# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2652/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2653# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2654/* Bit 56 - 59 - Reserved. */
2655/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2656#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2657#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2658/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2659# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2660/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2661# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2662/** @} */
2663
2664
2665/** @name FPCR - AArch64 Floating Point Control Register.
2666 * @{ */
2667/** Bit 0 - Flush Inputs to Zero when FEAT_AFP is supported. */
2668#define ARMV8_FPCR_FIZ RT_BIT_64(0)
2669#define ARMV8_FPCR_FIZ_BIT 0
2670/** Bit 1 - Alternate Handling of floating-point numbers when FEAT_AFP is supported. */
2671#define ARMV8_FPCR_AH RT_BIT_64(1)
2672#define ARMV8_FPCR_AH_BIT 1
2673/** Bit 2 - Controls how the output elements other than the lowest element of the vector are determined for
2674 * Advanced SIMD scalar instructions, when FEAT_AFP is supported. */
2675#define ARMV8_FPCR_NEP RT_BIT_64(2)
2676#define ARMV8_FPCR_NEP_BIT 2
2677/* Bit 3 - 7 - Reserved.*/
2678/** Bit 8 - Invalid Operation floating-point exception trap enable. */
2679#define ARMV8_FPCR_IOE RT_BIT_64(8)
2680#define ARMV8_FPCR_IOE_BIT 8
2681/** Bit 9 - Divide by Zero floating-point exception trap enable. */
2682#define ARMV8_FPCR_DZE RT_BIT_64(9)
2683#define ARMV8_FPCR_DZE_BIT 9
2684/** Bit 10 - Overflow floating-point exception trap enable. */
2685#define ARMV8_FPCR_OFE RT_BIT_64(10)
2686#define ARMV8_FPCR_OFE_BIT 10
2687/** Bit 11 - Underflow floating-point exception trap enable. */
2688#define ARMV8_FPCR_UFE RT_BIT_64(11)
2689#define ARMV8_FPCR_UFE_BIT 11
2690/** Bit 12 - Inexact floating-point exception trap enable. */
2691#define ARMV8_FPCR_IXE RT_BIT_64(12)
2692#define ARMV8_FPCR_IXE_BIT 12
2693/** Bit 13 - Controls numeric behavior of BFloat16 dot productions calculations performed,
2694 * supported when FEAT_EBF16 is supported. */
2695#define ARMV8_FPCR_EBF RT_BIT_64(13)
2696#define ARMV8_FPCR_EBF_BIT 13
2697/* Bit 14 - Reserved */
2698/** Bit 15 - Input Denormal floating-point exception trap enable. */
2699#define ARMV8_FPCR_IDE RT_BIT_64(15)
2700#define ARMV8_FPCR_IDE_BIT 15
2701/* Bit 16 - 18 - Reserved for AArch64 (Len field for AArch32). */
2702/** Bit 19 - Flushing denormalized numbers to zero control bit on half-precision data-processing instructions,
2703 * available when FEAT_FP16 is supported. */
2704#define ARMV8_FPCR_FZ16 RT_BIT_64(19)
2705#define ARMV8_FPCR_FZ16_BIT 19
2706/* Bit 20 - 21 - Reserved for AArch64 (Stride field dor AArch32). */
2707/** Bit 22 - 23 - Rounding Mode control field. */
2708#define ARMV8_FPCR_RMODE_MASK (RT_BIT_64(22) | RT_BIT_64(23))
2709#define ARMV8_FPCR_RMODE_SHIFT 22
2710/** Round to Nearest (RN) mode. */
2711# define ARMV8_FPCR_RMODE_RN 0
2712/** Round towards Plus Infinity (RP) mode. */
2713# define ARMV8_FPCR_RMODE_RP 1
2714/** Round towards Minus Infinity (RM) mode. */
2715# define ARMV8_FPCR_RMODE_RM 2
2716/** Round towards Zero (RZ) mode. */
2717# define ARMV8_FPCR_RMODE_RZ 3
2718/** Bit 24 - Flushing denormalized numbers to zero control bit. */
2719#define ARMV8_FPCR_FZ RT_BIT_64(24)
2720#define ARMV8_FPCR_FZ_BIT 24
2721/** Bit 25 - Default NaN use for NaN propagation. */
2722#define ARMV8_FPCR_DN RT_BIT_64(25)
2723#define ARMV8_FPCR_DN_BIT 25
2724/** Bit 26 - Alternative half-precision control bit. */
2725#define ARMV8_FPCR_AHP RT_BIT_64(26)
2726#define ARMV8_FPCR_AHP_BIT 26
2727/* Bit 27 - 63 - Reserved. */
2728/** @} */
2729
2730
2731/** @name FPSR - AArch64 Floating Point Status Register.
2732 * @{ */
2733/** Bit 0 - Invalid Operation cumulative floating-point exception bit. */
2734#define ARMV8_FPSR_IOC RT_BIT_64(0)
2735/** Bit 1 - Divide by Zero cumulative floating-point exception bit. */
2736#define ARMV8_FPSR_DZC RT_BIT_64(1)
2737/** Bit 2 - Overflow cumulative floating-point exception bit. */
2738#define ARMV8_FPSR_OFC RT_BIT_64(2)
2739/** Bit 3 - Underflow cumulative floating-point exception bit. */
2740#define ARMV8_FPSR_UFC RT_BIT_64(3)
2741/** Bit 4 - Inexact cumulative floating-point exception bit. */
2742#define ARMV8_FPSR_IXC RT_BIT_64(4)
2743/* Bit 5 - 6 - Reserved. */
2744/** Bit 7 - Input Denormal cumulative floating-point exception bit. */
2745#define ARMV8_FPSR_IDC RT_BIT_64(7)
2746/* Bit 8 - 26 - Reserved. */
2747/** Bit 27 - Cumulative saturation bit, Advanced SIMD only. */
2748#define ARMV8_FPSR_QC RT_BIT_64(27)
2749/* Bit 28 - 31 - NZCV bits for AArch32 floating point operations. */
2750/* Bit 32 - 63 - Reserved. */
2751/** @} */
2752
2753
2754
2755/** @name SCTLR_EL1 - AArch64 System Control Register (EL1).
2756 * @{ */
2757/** Bit 0 - MMU enable for EL1 and EL0 stage 1 address translation. */
2758#define ARMV8_SCTLR_EL1_M RT_BIT_64(0)
2759/** Bit 1 - Alignment check enable for EL1 and EL0. */
2760#define ARMV8_SCTLR_EL1_A RT_BIT_64(1)
2761/** Bit 2 - Stage 1 cacheability control, for data accesses. */
2762#define ARMV8_SCTLR_EL1_C RT_BIT_64(2)
2763/** Bit 3 - SP alignment check enable. */
2764#define ARMV8_SCTLR_EL1_SA RT_BIT_64(3)
2765/** Bit 4 - SP alignment check enable for EL0. */
2766#define ARMV8_SCTLR_EL1_SA0 RT_BIT_64(4)
2767/** Bit 5 - System instruction memory barrier enable from AArch32 EL0. */
2768#define ARMV8_SCTLR_EL1_CP15BEN RT_BIT_64(5)
2769/** Bit 6 - Non-aligned access enable. */
2770#define ARMV8_SCTLR_EL1_NAA RT_BIT_64(6)
2771#define ARMV8_SCTLR_EL1_nAA RT_BIT_64(6)
2772/** Bit 7 - IT disable, disables some uses of IT instructions at EL0 using AArch32. */
2773#define ARMV8_SCTLR_EL1_ITD RT_BIT_64(7)
2774/** Bit 8 - SETEND instruction disable, disables SETEND instructions at EL0 using AArch32. */
2775#define ARMV8_SCTLR_EL1_SED RT_BIT_64(8)
2776/** Bit 9 - User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D,A,I,F} masks to EL1. */
2777#define ARMV8_SCTLR_EL1_UMA RT_BIT_64(9)
2778/** Bit 10 - Enable EL0 acccess to the CFP*, DVP* and CPP* instructions if FEAT_SPECRES is supported. */
2779#define ARMV8_SCTLR_EL1_ENRCTX RT_BIT_64(10)
2780#define ARMV8_SCTLR_EL1_EnRCTX ARMV8_SCTLR_EL1_ENRCTX
2781/** Bit 11 - Exception Exit is Context Synchronizing (FEAT_ExS required). */
2782#define ARMV8_SCTLR_EL1_EOS RT_BIT_64(11)
2783/** Bit 12 - Stage 1 instruction access cacheability control, for access at EL0 and EL1. */
2784#define ARMV8_SCTLR_EL1_I RT_BIT_64(12)
2785/** @todo Finish (lazy developer). */
2786/** @} */
2787
2788
2789/** @name SCTLR_EL2 - AArch64 System Control Register (EL2).
2790 * @{ */
2791/** Bit 0 - MMU enable for EL2. */
2792#define ARMV8_SCTLR_EL2_M RT_BIT_64(0)
2793/** Bit 1 - Alignment check enable. */
2794#define ARMV8_SCTLR_EL2_A RT_BIT_64(1)
2795/** Bit 2 - Global enable for data and unified caches. */
2796#define ARMV8_SCTLR_EL2_C RT_BIT_64(2)
2797/** Bit 3 - SP alignment check enable. */
2798#define ARMV8_SCTLR_EL2_SA RT_BIT_64(3)
2799/** Bit 4 - SA0. */
2800#define ARMV8_SCTLR_EL2_SA0 RT_BIT_64(4)
2801/** Bit 5 - CP15BEN. */
2802#define ARMV8_SCTLR_EL2_CP15BEN RT_BIT_64(5)
2803/** Bit 6 - nAA. */
2804#define ARMV8_SCTLR_EL2_NAA RT_BIT_64(6)
2805/** Bit 7 - IDT. */
2806#define ARMV8_SCTLR_EL2_IDT RT_BIT_64(7)
2807/** Bit 8 - SED. */
2808#define ARMV8_SCTLR_EL2_SED RT_BIT_64(8)
2809/* Bit 9 - RES0 (2024-12). */
2810/** Bit 10 - EnRCTX. */
2811#define ARMV8_SCTLR_EL2_ENRCTX RT_BIT_64(10)
2812/** Bit 11 - EOS. */
2813#define ARMV8_SCTLR_EL2_EOS RT_BIT_64(11)
2814/** Bit 12 - Instruction cache enable. */
2815#define ARMV8_SCTLR_EL2_I RT_BIT_64(12)
2816/** Bit 13 - EnDB. */
2817#define ARMV8_SCTLR_EL2_ENDB RT_BIT_64(13)
2818/** Bit 14 - DZE. */
2819#define ARMV8_SCTLR_EL2_DZE RT_BIT_64(14)
2820/** Bit 15 - UCT. */
2821#define ARMV8_SCTLR_EL2_UCT RT_BIT_64(15)
2822/** Bit 16 - nTWI. */
2823#define ARMV8_SCTLR_EL2_NTWI RT_BIT_64(16)
2824/* Bit 17 - RES0 (2024-12). */
2825/** Bit 18 - nTWE. */
2826#define ARMV8_SCTLR_EL2_NTWE RT_BIT_64(18)
2827/** Bit 19 - Force treatment of all memory regions with write permissions as XN. */
2828#define ARMV8_SCTLR_EL2_WXN RT_BIT_64(19)
2829/** Bit 20 - TSCXT. */
2830#define ARMV8_SCTLR_EL2_TSCXT RT_BIT_64(20)
2831/** Bit 21 - IESB. */
2832#define ARMV8_SCTLR_EL2_IESB RT_BIT_64(21)
2833/** Bit 22 - EIS. */
2834#define ARMV8_SCTLR_EL2_EIS RT_BIT_64(22)
2835/** Bit 23 - SPAN. */
2836#define ARMV8_SCTLR_EL2_SPAN RT_BIT_64(23)
2837/** Bit 24 - E0E. */
2838#define ARMV8_SCTLR_EL2_E0E RT_BIT_64(24)
2839/** Bit 25 - Exception endianess - set means big endian, clear little endian. */
2840#define ARMV8_SCTLR_EL2_EE RT_BIT_64(25)
2841/** @todo Finish (lazy developer). */
2842/** @} */
2843
2844
2845/** @name HCR_EL2 - AArch64 Hypervisor Configuration Register (EL2).
2846 * @{ */
2847#define ARMV8_HCR_EL2_VM RT_BIT_64(0)
2848#define ARMV8_HCR_EL2_SWIO RT_BIT_64(1)
2849#define ARMV8_HCR_EL2_PTW RT_BIT_64(2)
2850#define ARMV8_HCR_EL2_FMO RT_BIT_64(3)
2851#define ARMV8_HCR_EL2_IMO RT_BIT_64(4)
2852#define ARMV8_HCR_EL2_AMO RT_BIT_64(5)
2853#define ARMV8_HCR_EL2_VF RT_BIT_64(6)
2854#define ARMV8_HCR_EL2_VI RT_BIT_64(7)
2855#define ARMV8_HCR_EL2_VSE RT_BIT_64(8)
2856#define ARMV8_HCR_EL2_FB RT_BIT_64(9)
2857#define ARMV8_HCR_EL2_BSU_MASK (RT_BIT_64(10) | RT_BIT_64(11))
2858#define ARMV8_HCR_EL2_DC RT_BIT_64(12)
2859#define ARMV8_HCR_EL2_TWI RT_BIT_64(13)
2860#define ARMV8_HCR_EL2_TWE RT_BIT_64(14)
2861#define ARMV8_HCR_EL2_TID0 RT_BIT_64(15)
2862#define ARMV8_HCR_EL2_TID1 RT_BIT_64(16)
2863#define ARMV8_HCR_EL2_TID2 RT_BIT_64(17)
2864#define ARMV8_HCR_EL2_TID3 RT_BIT_64(18)
2865#define ARMV8_HCR_EL2_TSC RT_BIT_64(19)
2866#define ARMV8_HCR_EL2_TIDCP RT_BIT_64(20)
2867#define ARMV8_HCR_EL2_TACR RT_BIT_64(21)
2868#define ARMV8_HCR_EL2_TSW RT_BIT_64(22)
2869#define ARMV8_HCR_EL2_TDCP RT_BIT_64(23)
2870#define ARMV8_HCR_EL2_TPU RT_BIT_64(24)
2871#define ARMV8_HCR_EL2_TTLB RT_BIT_64(25)
2872#define ARMV8_HCR_EL2_TVM RT_BIT_64(26)
2873#define ARMV8_HCR_EL2_TGE RT_BIT_64(27)
2874#define ARMV8_HCR_EL2_TDZ RT_BIT_64(28)
2875#define ARMV8_HCR_EL2_HCD RT_BIT_64(29)
2876#define ARMV8_HCR_EL2_TRVM RT_BIT_64(30)
2877#define ARMV8_HCR_EL2_RW RT_BIT_64(31)
2878#define ARMV8_HCR_EL2_CD RT_BIT_64(32)
2879#define ARMV8_HCR_EL2_IC RT_BIT_64(33)
2880#define ARMV8_HCR_EL2_E2H RT_BIT_64(34)
2881#define ARMV8_HCR_EL2_TLOR RT_BIT_64(35)
2882#define ARMV8_HCR_EL2_TERR RT_BIT_64(36)
2883#define ARMV8_HCR_EL2_TEA RT_BIT_64(37)
2884#define ARMV8_HCR_EL2_MIOCNCE RT_BIT_64(38)
2885#define ARMV8_HCR_EL2_TME RT_BIT_64(39)
2886#define ARMV8_HCR_EL2_APK RT_BIT_64(40)
2887#define ARMV8_HCR_EL2_API RT_BIT_64(41)
2888#define ARMV8_HCR_EL2_NV RT_BIT_64(42)
2889#define ARMV8_HCR_EL2_NV1 RT_BIT_64(43)
2890#define ARMV8_HCR_EL2_AT RT_BIT_64(44)
2891#define ARMV8_HCR_EL2_NV2 RT_BIT_64(45)
2892#define ARMV8_HCR_EL2_FWB RT_BIT_64(46)
2893#define ARMV8_HCR_EL2_FIEN RT_BIT_64(47)
2894#define ARMV8_HCR_EL2_GPF RT_BIT_64(48)
2895#define ARMV8_HCR_EL2_TID4 RT_BIT_64(49)
2896#define ARMV8_HCR_EL2_TICAB RT_BIT_64(50)
2897#define ARMV8_HCR_EL2_AMVOFFEN RT_BIT_64(51)
2898#define ARMV8_HCR_EL2_TOCU RT_BIT_64(52)
2899#define ARMV8_HCR_EL2_ENSCXT RT_BIT_64(53)
2900#define ARMV8_HCR_EL2_TTLBIS RT_BIT_64(54)
2901#define ARMV8_HCR_EL2_TTLBOS RT_BIT_64(55)
2902#define ARMV8_HCR_EL2_ATA RT_BIT_64(56)
2903#define ARMV8_HCR_EL2_DCT RT_BIT_64(57)
2904#define ARMV8_HCR_EL2_TID5 RT_BIT_64(58)
2905#define ARMV8_HCR_EL2_TWEDEN RT_BIT_64(59)
2906#define ARMV8_HCR_EL2_TWEDL_MASK UINT64_C(0xf000000000000000)
2907/** @} */
2908
2909
2910/** @name MDCR_EL2 - AArch64 Monitor Debug Configuration Register (EL2).
2911 * @{ */
2912#define ARMV8_MDCR_EL2_HPMN_MASK UINT64_C(0x1f)
2913#define ARMV8_MDCR_EL2_TPMCR RT_BIT_64(5)
2914#define ARMV8_MDCR_EL2_TPM RT_BIT_64(6)
2915#define ARMV8_MDCR_EL2_HPME RT_BIT_64(7)
2916#define ARMV8_MDCR_EL2_TDE RT_BIT_64(8)
2917#define ARMV8_MDCR_EL2_TDA RT_BIT_64(9)
2918#define ARMV8_MDCR_EL2_TDOSA RT_BIT_64(10)
2919#define ARMV8_MDCR_EL2_TDRA RT_BIT_64(11)
2920#define ARMV8_MDCR_EL2_E2PB_MASK (RT_BIT_64(12) | RT_BIT_64(13))
2921#define ARMV8_MDCR_EL2_TPMS RT_BIT_64(14)
2922#define ARMV8_MDCR_EL2_ENSPM RT_BIT_64(15)
2923/* Bit 16 - RES0 (2024-12) */
2924#define ARMV8_MDCR_EL2_HPMD RT_BIT_64(17)
2925/* Bit 18 - RES0 (2024-12) */
2926#define ARMV8_MDCR_EL2_TTRF RT_BIT_64(19)
2927/* Bits 22:20 - RES0 (2024-12) */
2928#define ARMV8_MDCR_EL2_HCCD RT_BIT_64(23)
2929#define ARMV8_MDCR_EL2_E2TB_MASK (RT_BIT_64(24) | RT_BIT_64(25))
2930#define ARMV8_MDCR_EL2_HLP RT_BIT_64(26)
2931#define ARMV8_MDCR_EL2_TDCC RT_BIT_64(27)
2932#define ARMV8_MDCR_EL2_MTPME RT_BIT_64(28)
2933#define ARMV8_MDCR_EL2_HPMFZO RT_BIT_64(29)
2934#define ARMV8_MDCR_EL2_PMSSE_MASK (RT_BIT_64(30) | RT_BIT_64(31))
2935/* Bits 35:32 - RES0 (2024-12) */
2936#define ARMV8_MDCR_EL2_HPMFZS RT_BIT_64(36)
2937/* Bits 39:37 - RES0 (2024-12) */
2938#define ARMV8_MDCR_EL2_PMEE_MASK (RT_BIT_64(40) | RT_BIT_64(41))
2939/* Bit 42 - RES0 (2024-12) */
2940#define ARMV8_MDCR_EL2_EBWE RT_BIT_64(43)
2941/* Bits 49:44 - RES0 (2024-12) */
2942#define ARMV8_MDCR_EL2_ENSTEPOP RT_BIT_64(50)
2943/* Bits 63:51 - RES0 (2024-12) */
2944/** @} */
2945
2946
2947/** @defgrp grp_rt_armv8_vmsav864 VMSAv8-64 related definitions
2948 * @ingroup grp_rt_armv8
2949 * @{ */
2950
2951#ifndef __ASSEMBLER__
2952/** A VMSAv8-64 descriptor. */
2953typedef uint64_t ARMV8VMSA64DESC;
2954/** Pointer to a VMSAv8-64 descriptor. */
2955typedef ARMV8VMSA64DESC *PARMV8VMSA64DESC;
2956/** Pointer to a const VMSAv8-64 descriptor. */
2957typedef const ARMV8VMSA64DESC *PCARMV8VMSA64DESC;
2958#endif
2959
2960
2961/** Bit 0 - Flag whether the table entry is valid. */
2962#define ARMV8_VMSA64_TBL_ENTRY_F_VALID RT_BIT_64(0)
2963#define ARMV8_VMSA64_TBL_ENTRY_F_VALID_BIT 0
2964/** Bit 1 - Indicates the descriptor type depending on the current lookup level.
2965 * Basically when set it indicates to continue the lookup at the next level, or at the last level
2966 * that it is a page (not setting it at the last level is treated as an invalid descriptor).
2967 * If clear and not at the last lookup level the result will either be a large or gigantic page,
2968 * depending on the lookup level. */
2969#define ARMV8_VMSA64_TBL_ENTRY_F_TBL_OR_PG RT_BIT_64(1)
2970#define ARMV8_VMSA64_TBL_ENTRY_F_TBL_OR_PG_BIT 1
2971
2972/** @} */
2973
2974#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
2975/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2976 * @ingroup grp_rt_armv8
2977 *
2978 * A few inlined functions and macros for assiting in encoding common ARMv8
2979 * instructions.
2980 *
2981 * @{ */
2982
2983/** A64: Official NOP instruction. */
2984#define ARMV8_A64_INSTR_NOP UINT32_C(0xd503201f)
2985/** A64: Return instruction. */
2986#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2987/** A64: Return instruction with LR pointer authentication using SP and key A. */
2988#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2989/** A64: Return instruction with LR pointer authentication using SP and key B. */
2990#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2991/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2992#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2993/** A64: Insert pointer authentication code into LR using SP and key B. */
2994#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2995/** A64: Insert pointer authentication code into LR using XZR and key B. */
2996#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2997/** A64: Invert the carry flag (PSTATE.C). */
2998#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
2999
3000
3001/** Memory barrier: Shareability domain. */
3002typedef enum
3003{
3004 kArm64InstMbReqDomain_OuterShareable = 0,
3005 kArm64InstMbReqDomain_Nonshareable,
3006 kArm64InstMbReqDomain_InnerShareable,
3007 kArm64InstMbReqDomain_FullSystem
3008} ARM64INSTRMBREQDOMAIN;
3009
3010/** Memory barrier: Access type. */
3011typedef enum
3012{
3013 kArm64InstMbReqType_All0 = 0, /**< Special. Only used with PSSBB and SSBB. */
3014 kArm64InstMbReqType_Reads,
3015 kArm64InstMbReqType_Writes,
3016 kArm64InstMbReqType_All
3017} ARM64INSTRMBREQTYPE;
3018
3019/**
3020 * A64: DMB option
3021 */
3022DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDmb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
3023 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
3024{
3025 return UINT32_C(0xd50330bf)
3026 | ((uint32_t)enmDomain << 8)
3027 | ((uint32_t)enmType << 10);
3028}
3029
3030
3031/**
3032 * A64: DSB option
3033 */
3034DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
3035 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
3036{
3037 return UINT32_C(0xd503309f)
3038 | ((uint32_t)enmDomain << 8)
3039 | ((uint32_t)enmType << 10);
3040}
3041
3042
3043/**
3044 * A64: SSBB
3045 */
3046DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSsbb(void)
3047{
3048 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_OuterShareable, kArm64InstMbReqType_All0);
3049}
3050
3051
3052/**
3053 * A64: PSSBB
3054 */
3055DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPSsbb(void)
3056{
3057 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_Nonshareable, kArm64InstMbReqType_All0);
3058}
3059
3060
3061/**
3062 * A64: ISB option
3063 *
3064 * @note Only the default option selection is supported, all others are
3065 * currently reserved.
3066 */
3067DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
3068 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
3069{
3070 return UINT32_C(0xd50330df)
3071 | ((uint32_t)enmDomain << 8)
3072 | ((uint32_t)enmType << 10);
3073}
3074
3075
3076typedef enum
3077{
3078 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
3079 * and update the register. */
3080 kArm64InstrStLdPairType_PostIndex = 1,
3081 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
3082 * but don't update the register. */
3083 kArm64InstrStLdPairType_Signed = 2,
3084 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
3085 * and update the register. */
3086 kArm64InstrStLdPairType_PreIndex = 3
3087} ARM64INSTRSTLDPAIRTYPE;
3088
3089/**
3090 * A64: Encodes either stp (store register pair) or ldp (load register pair).
3091 *
3092 * @returns The encoded instruction.
3093 * @param fLoad true for ldp, false of stp.
3094 * @param u2Opc When @a fSimdFp is @c false:
3095 * - 0 for 32-bit GPRs (Wt).
3096 * - 1 for encoding stgp or ldpsw.
3097 * - 2 for 64-bit GRPs (Xt).
3098 * - 3 illegal.
3099 * When @a fSimdFp is @c true:
3100 * - 0 for 32-bit SIMD&FP registers (St).
3101 * - 1 for 64-bit SIMD&FP registers (Dt).
3102 * - 2 for 128-bit SIMD&FP regsiters (Qt).
3103 * @param enmType The instruction variant wrt addressing and updating of the
3104 * addressing register.
3105 * @param iReg1 The first register to store/load.
3106 * @param iReg2 The second register to store/load.
3107 * @param iBaseReg The base register to use when addressing. SP is allowed.
3108 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
3109 * will be multiplied by the register size.
3110 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
3111 * stgp/ldpsw instructions.
3112 */
3113DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
3114 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
3115 bool fSimdFp = false)
3116{
3117 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
3118 return (u2Opc << 30)
3119 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
3120 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
3121 | ((uint32_t)enmType << 23)
3122 | ((uint32_t)fLoad << 22)
3123 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
3124 | (iReg2 << 10)
3125 | (iBaseReg << 5)
3126 | iReg1;
3127}
3128
3129
3130/** A64: ldp x1, x2, [x3] */
3131DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
3132 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
3133 bool f64Bit = true)
3134{
3135 return Armv8A64MkInstrStLdPair(true /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
3136}
3137
3138
3139/** A64: stp x1, x2, [x3] */
3140DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
3141 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
3142 bool f64Bit = true)
3143{
3144 return Armv8A64MkInstrStLdPair(false /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
3145}
3146
3147
3148typedef enum /* Size VR Opc */
3149{ /* \ | / */
3150 kArmv8A64InstrLdStType_Mask_Size = 0x300,
3151 kArmv8A64InstrLdStType_Mask_VR = 0x010,
3152 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
3153 kArmv8A64InstrLdStType_Shift_Size = 8,
3154 kArmv8A64InstrLdStType_Shift_VR = 4,
3155 kArmv8A64InstrLdStType_Shift_Opc = 0,
3156
3157 kArmv8A64InstrLdStType_St_Byte = 0x000,
3158 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
3159 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
3160 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
3161
3162 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
3163 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
3164 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
3165 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
3166
3167 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
3168 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
3169 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
3170
3171 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
3172 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
3173
3174 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
3175
3176 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
3177 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
3178 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
3179 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
3180
3181 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
3182 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
3183
3184 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
3185 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
3186
3187 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
3188 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
3189
3190} ARMV8A64INSTRLDSTTYPE;
3191/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
3192#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
3193
3194
3195/**
3196 * A64: Encodes load/store with unscaled 9-bit signed immediate.
3197 *
3198 * @returns The encoded instruction.
3199 * @param u32Opcode The base opcode value.
3200 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3201 * @param iReg The register to load into / store.
3202 * @param iBaseReg The base register to use when addressing. SP is allowed.
3203 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3204 */
3205DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
3206 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3207{
3208 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
3209 return u32Opcode
3210 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3211 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3212 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3213 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
3214 | (iBaseReg << 5)
3215 | iReg;
3216}
3217
3218
3219/**
3220 * A64: Encodes load/store with unscaled 9-bit signed immediate.
3221 *
3222 * @returns The encoded instruction.
3223 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3224 * @param iReg The register to load into / store.
3225 * @param iBaseReg The base register to use when addressing. SP is allowed.
3226 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3227 */
3228DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
3229 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3230{
3231 /* 3 2 1 0 */
3232 /* 10987654321098765432109876543210 */
3233 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
3234 enmType, iReg, iBaseReg, i9ImmDisp);
3235}
3236
3237/**
3238 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
3239 *
3240 * @returns The encoded instruction.
3241 * @param enmType The load/store instruction type. Prefech not valid.
3242 * @param iReg The register to load into / store.
3243 * @param iBaseReg The base register to use when addressing. SP is allowed.
3244 * Written back.
3245 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3246 */
3247DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3248 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3249{
3250 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3251 /* 10987654321098765432109876543210 */
3252 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
3253 enmType, iReg, iBaseReg, i9ImmDisp);
3254}
3255
3256/**
3257 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
3258 *
3259 * @returns The encoded instruction.
3260 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3261 * @param iReg The register to load into / store.
3262 * @param iBaseReg The base register to use when addressing. SP is allowed.
3263 * Written back.
3264 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3265 */
3266DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3267 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3268{
3269 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3270 /* 10987654321098765432109876543210 */
3271 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
3272 enmType, iReg, iBaseReg, i9ImmDisp);
3273}
3274
3275/**
3276 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
3277 *
3278 * @returns The encoded instruction.
3279 * @param enmType The load/store instruction type. Prefech not valid,
3280 * nor any SIMD&FP variants.
3281 * @param iReg The register to load into / store.
3282 * @param iBaseReg The base register to use when addressing. SP is allowed.
3283 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3284 */
3285DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
3286 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3287{
3288 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
3289 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
3290 /* 3 2 1 0 */
3291 /* 10987654321098765432109876543210 */
3292 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
3293 enmType, iReg, iBaseReg, i9ImmDisp);
3294}
3295
3296
3297/**
3298 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
3299 *
3300 * @returns The encoded instruction.
3301 * @param enmType The load/store instruction type. Prefech not valid,
3302 * nor any SIMD&FP variants.
3303 * @param iReg The register to load into / store.
3304 * @param iBaseReg The base register to use when addressing. SP is allowed.
3305 * @param u12ImmDisp Addressing displacement, scaled by size.
3306 */
3307DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
3308 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
3309{
3310 Assert(u12ImmDisp < 4096U);
3311 Assert(iReg < 32); /* 3 2 1 0 */
3312 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3313 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
3314 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3315 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3316 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3317 | (u12ImmDisp << 10)
3318 | (iBaseReg << 5)
3319 | iReg;
3320}
3321
3322typedef enum
3323{
3324 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
3325 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
3326 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
3327 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
3328} ARMV8A64INSTRLDSTEXTEND;
3329
3330/**
3331 * A64: Encodes load/store w/ index register.
3332 *
3333 * @returns The encoded instruction.
3334 * @param enmType The load/store instruction type.
3335 * @param iReg The register to load into / store.
3336 * @param iBaseReg The base register to use when addressing. SP is allowed.
3337 * @param iRegIndex The index register.
3338 * @param enmExtend The extending to apply to @a iRegIndex.
3339 * @param fShifted Whether to shift the index. The shift amount corresponds
3340 * to the access size (thus irrelevant for byte accesses).
3341 */
3342DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
3343 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
3344 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
3345 bool fShifted = false)
3346{
3347 Assert(iRegIndex < 32);
3348 Assert(iReg < 32); /* 3 2 1 0 */
3349 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3350 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
3351 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3352 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3353 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3354 | (iRegIndex << 16)
3355 | ((uint32_t)enmExtend << 13)
3356 | ((uint32_t)fShifted << 12)
3357 | (iBaseReg << 5)
3358 | iReg;
3359}
3360
3361typedef enum /* VR Opc */
3362{ /* \ | */
3363 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
3364 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
3365 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
3366 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
3367
3368 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
3369 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
3370 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
3371 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
3372
3373 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
3374 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
3375 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
3376} ARMV8A64INSTRLDRLITTERAL;
3377
3378
3379/**
3380 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
3381 *
3382 * @returns The encoded instruction.
3383 * @param enmType The load instruction type.
3384 * @param iReg The register to load into.
3385 * @param i19Imm The signed immediate value, multiplied by 4 regardless
3386 * of access size.
3387 */
3388DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
3389{
3390 Assert(i19Imm >= -262144 && i19Imm < 262144);
3391 Assert(iReg < 32); /* 3 2 1 0 */
3392 /* 10987654321098765432109876543210 */
3393 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
3394 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
3395 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
3396 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
3397 | iReg;
3398}
3399
3400
3401typedef enum
3402{
3403 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
3404 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
3405 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
3406} ARMV8A64INSTRMOVWIDE;
3407
3408/**
3409 * A64: Encode a move wide immediate instruction.
3410 *
3411 * @returns The encoded instruction.
3412 * @param enmType The load instruction type.
3413 * @param iRegDst The register to mov the immediate into.
3414 * @param uImm16 The immediate value.
3415 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
3416 * half-words to target:
3417 * - 0 for bits 15:00,
3418 * - 1 for bits 31:16,
3419 * - 2 for bits 47:32 (f64Bit=true only),
3420 * - 3 for bits 63:48 (f64Bit=true only).
3421 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
3422 */
3423DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
3424 uint32_t iHalfWord = 0, bool f64Bit = true)
3425{
3426 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
3427 return ((uint32_t)f64Bit << 31)
3428 | ((uint32_t)enmType << 29)
3429 | UINT32_C(0x12800000)
3430 | (iHalfWord << 21)
3431 | (uImm16 << 5)
3432 | iRegDst;
3433}
3434
3435/** A64: Encodes a MOVN instruction.
3436 * @see Armv8A64MkInstrMovWide for parameter details. */
3437DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3438{
3439 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
3440}
3441
3442/** A64: Encodes a MOVZ instruction.
3443 * @see Armv8A64MkInstrMovWide for parameter details. */
3444DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3445{
3446 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
3447}
3448
3449/** A64: Encodes a MOVK instruction.
3450 * @see Armv8A64MkInstrMovWide for parameter details. */
3451DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3452{
3453 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
3454}
3455
3456
3457typedef enum
3458{
3459 kArmv8A64InstrShift_Lsl = 0,
3460 kArmv8A64InstrShift_Lsr,
3461 kArmv8A64InstrShift_Asr,
3462 kArmv8A64InstrShift_Ror
3463} ARMV8A64INSTRSHIFT;
3464
3465
3466/**
3467 * A64: Encodes a logical instruction with a shifted 2nd register operand.
3468 *
3469 * @returns The encoded instruction.
3470 * @param u2Opc The logical operation to perform.
3471 * @param fNot Whether to complement the 2nd operand.
3472 * @param iRegResult The output register.
3473 * @param iReg1 The 1st register operand.
3474 * @param iReg2Shifted The 2nd register operand, to which the optional
3475 * shifting is applied.
3476 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
3477 * GPRs.
3478 * @param offShift6 The shift amount (default: none).
3479 * @param enmShift The shift operation (default: LSL).
3480 */
3481DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
3482 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
3483 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
3484{
3485 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
3486 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
3487 return ((uint32_t)f64Bit << 31)
3488 | (u2Opc << 29)
3489 | UINT32_C(0x0a000000)
3490 | ((uint32_t)enmShift << 22)
3491 | ((uint32_t)fNot << 21)
3492 | (iReg2Shifted << 16)
3493 | (offShift6 << 10)
3494 | (iReg1 << 5)
3495 | iRegResult;
3496}
3497
3498
3499/** A64: Encodes an AND instruction.
3500 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3501DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3502 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3503{
3504 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3505}
3506
3507
3508/** A64: Encodes an BIC instruction.
3509 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3510DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3511 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3512{
3513 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3514}
3515
3516
3517/** A64: Encodes an ORR instruction.
3518 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3519DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3520 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3521{
3522 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3523}
3524
3525
3526/** A64: Encodes an MOV instruction.
3527 * This is an alias for "orr dst, xzr, src". */
3528DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
3529{
3530 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
3531}
3532
3533
3534/** A64: Encodes an ORN instruction.
3535 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3536DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3537 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3538{
3539 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3540}
3541
3542
3543/** A64: Encodes an EOR instruction.
3544 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3545DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3546 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3547{
3548 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3549}
3550
3551
3552/** A64: Encodes an EON instruction.
3553 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3554DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3555 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3556{
3557 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3558}
3559
3560
3561/** A64: Encodes an ANDS instruction.
3562 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3563DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3564 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3565{
3566 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3567}
3568
3569
3570/** A64: Encodes an BICS instruction.
3571 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3572DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3573 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3574{
3575 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3576}
3577
3578
3579
3580/*
3581 * Data processing instructions with two source register operands.
3582 */
3583
3584
3585/** A64: Encodes an SUBP instruction. */
3586DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3587{
3588 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3589 return UINT32_C(0x80000000)
3590 | UINT32_C(0x1ac00000)
3591 | (UINT32_C(0) << 10)
3592 | (iRegSubtrahend << 16)
3593 | (iRegMinuend << 5)
3594 | iRegResult;
3595}
3596
3597
3598/** A64: Encodes an SUBPS instruction. */
3599DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3600{
3601 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3602 return UINT32_C(0x80000000)
3603 | UINT32_C(0x20000000)
3604 | UINT32_C(0x1ac00000)
3605 | (UINT32_C(0) << 10)
3606 | (iRegSubtrahend << 16)
3607 | (iRegMinuend << 5)
3608 | iRegResult;
3609}
3610
3611
3612/** A64: Encodes an UDIV instruction. */
3613DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3614{
3615 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3616 return ((uint32_t)f64Bit << 31)
3617 | UINT32_C(0x1ac00000)
3618 | (UINT32_C(2) << 10)
3619 | (iRegDivisor << 16)
3620 | (iRegDividend << 5)
3621 | iRegResult;
3622}
3623
3624
3625/** A64: Encodes an SDIV instruction. */
3626DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3627{
3628 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3629 return ((uint32_t)f64Bit << 31)
3630 | UINT32_C(0x1ac00000)
3631 | (UINT32_C(3) << 10)
3632 | (iRegDivisor << 16)
3633 | (iRegDividend << 5)
3634 | iRegResult;
3635}
3636
3637
3638/** A64: Encodes an IRG instruction. */
3639DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3640{
3641 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3642 return UINT32_C(0x80000000)
3643 | UINT32_C(0x1ac00000)
3644 | (UINT32_C(4) << 10)
3645 | (iRegSrc2 << 16)
3646 | (iRegSrc1 << 5)
3647 | iRegResult;
3648}
3649
3650
3651/** A64: Encodes a GMI instruction. */
3652DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3653{
3654 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3655 return UINT32_C(0x80000000)
3656 | UINT32_C(0x1ac00000)
3657 | (UINT32_C(5) << 10)
3658 | (iRegSrc2 << 16)
3659 | (iRegSrc1 << 5)
3660 | iRegResult;
3661}
3662
3663
3664/** A64: Encodes an LSLV instruction. */
3665DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3666{
3667 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3668 return ((uint32_t)f64Bit << 31)
3669 | UINT32_C(0x1ac00000)
3670 | (UINT32_C(8) << 10)
3671 | (iRegCount << 16)
3672 | (iRegSrc << 5)
3673 | iRegResult;
3674}
3675
3676
3677/** A64: Encodes an LSRV instruction. */
3678DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3679{
3680 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3681 return ((uint32_t)f64Bit << 31)
3682 | UINT32_C(0x1ac00000)
3683 | (UINT32_C(9) << 10)
3684 | (iRegCount << 16)
3685 | (iRegSrc << 5)
3686 | iRegResult;
3687}
3688
3689
3690/** A64: Encodes an ASRV instruction. */
3691DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3692{
3693 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3694 return ((uint32_t)f64Bit << 31)
3695 | UINT32_C(0x1ac00000)
3696 | (UINT32_C(10) << 10)
3697 | (iRegCount << 16)
3698 | (iRegSrc << 5)
3699 | iRegResult;
3700}
3701
3702
3703/** A64: Encodes a RORV instruction. */
3704DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3705{
3706 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3707 return ((uint32_t)f64Bit << 31)
3708 | UINT32_C(0x1ac00000)
3709 | (UINT32_C(11) << 10)
3710 | (iRegCount << 16)
3711 | (iRegSrc << 5)
3712 | iRegResult;
3713}
3714
3715
3716/** A64: Encodes a PACGA instruction. */
3717DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3718{
3719 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3720 return UINT32_C(0x80000000)
3721 | UINT32_C(0x1ac00000)
3722 | (UINT32_C(12) << 10)
3723 | (iRegSrc2 << 16)
3724 | (iRegSrc1 << 5)
3725 | iRegResult;
3726}
3727
3728
3729/** A64: Encodes a CRC32* instruction. */
3730DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3731{
3732 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3733 return ((uint32_t)(uSize == 3) << 31)
3734 | UINT32_C(0x1ac00000)
3735 | (UINT32_C(16) << 10)
3736 | (uSize << 10)
3737 | (iRegValue << 16)
3738 | (iRegCrc << 5)
3739 | iRegResult;
3740}
3741
3742
3743/** A64: Encodes a CRC32B instruction. */
3744DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3745{
3746 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
3747}
3748
3749
3750/** A64: Encodes a CRC32H instruction. */
3751DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3752{
3753 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
3754}
3755
3756
3757/** A64: Encodes a CRC32W instruction. */
3758DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3759{
3760 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
3761}
3762
3763
3764/** A64: Encodes a CRC32X instruction. */
3765DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3766{
3767 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
3768}
3769
3770
3771/** A64: Encodes a CRC32C* instruction. */
3772DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3773{
3774 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3775 return ((uint32_t)(uSize == 3) << 31)
3776 | UINT32_C(0x1ac00000)
3777 | (UINT32_C(20) << 10)
3778 | (uSize << 10)
3779 | (iRegValue << 16)
3780 | (iRegCrc << 5)
3781 | iRegResult;
3782}
3783
3784
3785/** A64: Encodes a CRC32B instruction. */
3786DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3787{
3788 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
3789}
3790
3791
3792/** A64: Encodes a CRC32CH instruction. */
3793DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3794{
3795 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
3796}
3797
3798
3799/** A64: Encodes a CRC32CW instruction. */
3800DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3801{
3802 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
3803}
3804
3805
3806/** A64: Encodes a CRC32CX instruction. */
3807DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3808{
3809 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
3810}
3811
3812
3813/** A64: Encodes an SMAX instruction. */
3814DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3815{
3816 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3817 return ((uint32_t)f64Bit << 31)
3818 | UINT32_C(0x1ac00000)
3819 | (UINT32_C(24) << 10)
3820 | (iRegSrc2 << 16)
3821 | (iRegSrc1 << 5)
3822 | iRegResult;
3823}
3824
3825
3826/** A64: Encodes an UMAX instruction. */
3827DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3828{
3829 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3830 return ((uint32_t)f64Bit << 31)
3831 | UINT32_C(0x1ac00000)
3832 | (UINT32_C(25) << 10)
3833 | (iRegSrc2 << 16)
3834 | (iRegSrc1 << 5)
3835 | iRegResult;
3836}
3837
3838
3839/** A64: Encodes an SMIN instruction. */
3840DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3841{
3842 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3843 return ((uint32_t)f64Bit << 31)
3844 | UINT32_C(0x1ac00000)
3845 | (UINT32_C(26) << 10)
3846 | (iRegSrc2 << 16)
3847 | (iRegSrc1 << 5)
3848 | iRegResult;
3849}
3850
3851
3852/** A64: Encodes an UMIN instruction. */
3853DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3854{
3855 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3856 return ((uint32_t)f64Bit << 31)
3857 | UINT32_C(0x1ac00000)
3858 | (UINT32_C(27) << 10)
3859 | (iRegSrc2 << 16)
3860 | (iRegSrc1 << 5)
3861 | iRegResult;
3862}
3863
3864
3865# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
3866
3867/**
3868 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
3869 *
3870 * @returns The decoded mask.
3871 * @param uImm6SizeLen The immS value from the instruction. (No N part
3872 * here, as that must be zero for instructions
3873 * operating on 32-bit wide registers.)
3874 * @param uImm6Rotations The immR value from the instruction.
3875 */
3876DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3877{
3878 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
3879
3880 /* Determine the element size. */
3881 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
3882 Assert(cBitsElementLog2 + 1U != 0U);
3883
3884 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3885 Assert(uImm6Rotations < cBitsElement);
3886
3887 /* Extract the number of bits set to 1: */
3888 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
3889 Assert(cBitsSetTo1 < cBitsElement);
3890 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
3891
3892 /* Produce the unrotated pattern. */
3893 static const uint32_t s_auReplicate[]
3894 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3895 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3896
3897 /* Rotate it and return. */
3898 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
3899}
3900
3901
3902/**
3903 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
3904 *
3905 * @returns The decoded mask.
3906 * @param uImm7SizeLen The N:immS value from the instruction.
3907 * @param uImm6Rotations The immR value from the instruction.
3908 */
3909DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
3910{
3911 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
3912
3913 /* Determine the element size. */
3914 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
3915 Assert(cBitsElementLog2 + 1U != 0U);
3916
3917 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3918 Assert(uImm6Rotations < cBitsElement);
3919
3920 /* Extract the number of bits set to 1: */
3921 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
3922 Assert(cBitsSetTo1 < cBitsElement);
3923 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
3924
3925 /* Produce the unrotated pattern. */
3926 static const uint64_t s_auReplicate[]
3927 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3928 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3929
3930 /* Rotate it and return. */
3931 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
3932}
3933
3934
3935/**
3936 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
3937 * the immS value.
3938 */
3939DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3940{
3941 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
3942}
3943
3944
3945/**
3946 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3947 * 32-bit bitmask to a set of immediates for those instructions.
3948 *
3949 * @returns true if successful, false if not.
3950 * @param fMask The mask value to convert.
3951 * @param puImm6SizeLen Where to return the immS part (N is always zero for
3952 * 32-bit wide masks).
3953 * @param puImm6Rotations Where to return the immR.
3954 */
3955DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
3956{
3957 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
3958 if ((uint32_t)(fMask + 1U) <= 1)
3959 return false;
3960
3961 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3962 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
3963 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
3964 if (cRor)
3965 fMask = ASMRotateRightU32(fMask, cRor);
3966 else
3967 fMask = ASMRotateLeftU32(fMask, cRol);
3968 Assert(fMask & RT_BIT_32(0));
3969 Assert(!(fMask & RT_BIT_32(31)));
3970
3971 /* Count the trailing ones and leading zeros. */
3972 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
3973 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
3974
3975 /* The potential element length is then the sum of the two above. */
3976 unsigned const cBitsElement = cOnes + cZeros;
3977 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3978 return false;
3979
3980 /* Special case: 32 bits element size. Since we're done here. */
3981 if (cBitsElement == 32)
3982 *puImm6SizeLen = cOnes - 1;
3983 else
3984 {
3985 /* Extract the element bits and check that these are replicated in the whole pattern. */
3986 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
3987 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
3988
3989 static const uint32_t s_auReplicate[]
3990 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3991 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3992 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3993 else
3994 return false;
3995 }
3996 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3997
3998 return true;
3999}
4000
4001
4002/**
4003 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
4004 * 64-bit bitmask to a set of immediates for those instructions.
4005 *
4006 * @returns true if successful, false if not.
4007 * @param fMask The mask value to convert.
4008 * @param puImm7SizeLen Where to return the N:immS part.
4009 * @param puImm6Rotations Where to return the immR.
4010 */
4011DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
4012{
4013 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
4014 if ((uint64_t)(fMask + 1U) <= 1)
4015 return false;
4016
4017 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
4018 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
4019 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
4020 if (cRor)
4021 fMask = ASMRotateRightU64(fMask, cRor);
4022 else
4023 fMask = ASMRotateLeftU64(fMask, cRol);
4024 Assert(fMask & RT_BIT_64(0));
4025 Assert(!(fMask & RT_BIT_64(63)));
4026
4027 /* Count the trailing ones and leading zeros. */
4028 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
4029 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
4030
4031 /* The potential element length is then the sum of the two above. */
4032 unsigned const cBitsElement = cOnes + cZeros;
4033 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
4034 return false;
4035
4036 /* Special case: 64 bits element size. Since we're done here. */
4037 if (cBitsElement == 64)
4038 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
4039 else
4040 {
4041 /* Extract the element bits and check that these are replicated in the whole pattern. */
4042 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
4043 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
4044
4045 static const uint64_t s_auReplicate[]
4046 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
4047 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
4048 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
4049 else
4050 return false;
4051 }
4052 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
4053
4054 return true;
4055}
4056
4057# endif /* IPRT_INCLUDED_asm_h */
4058
4059/**
4060 * A64: Encodes a logical instruction with an complicated immediate mask.
4061 *
4062 * The @a uImm7SizeLen parameter specifies two things:
4063 * 1. the element size and
4064 * 2. the number of bits set to 1 in the pattern.
4065 *
4066 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
4067 * top) and using the position of the first bit set as a power of two.
4068 *
4069 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
4070 * |---|---|---|---|---|---|---|--------------|
4071 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
4072 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
4073 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
4074 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
4075 * | 0 | 0 | x | x | x | x | x | 32 bits |
4076 * | 1 | x | x | x | x | x | x | 64 bits |
4077 *
4078 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
4079 * there is always one zero bit in the pattern).
4080 *
4081 * The @a uImm6Rotations parameter specifies how many bits to the right,
4082 * the element pattern is rotated. The rotation count must be less than the
4083 * element bit count (size).
4084 *
4085 * @returns The encoded instruction.
4086 * @param u2Opc The logical operation to perform.
4087 * @param iRegResult The output register.
4088 * @param iRegSrc The 1st register operand.
4089 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
4090 * field at the top of the 6-bit 'imms' field.
4091 *
4092 * @param uImm6Rotations The rotation count.
4093 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
4094 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
4095 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
4096 */
4097DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
4098 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
4099{
4100 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x3f)));
4101 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
4102 return ((uint32_t)f64Bit << 31)
4103 | (u2Opc << 29)
4104 | UINT32_C(0x12000000)
4105 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
4106 | (uImm6Rotations << 16)
4107 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
4108 | (iRegSrc << 5)
4109 | iRegResult;
4110}
4111
4112
4113/** A64: Encodes an AND instruction w/ complicated immediate mask.
4114 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4115DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
4116 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4117{
4118 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4119}
4120
4121
4122/** A64: Encodes an ORR instruction w/ complicated immediate mask.
4123 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4124DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
4125 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4126{
4127 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4128}
4129
4130
4131/** A64: Encodes an EOR instruction w/ complicated immediate mask.
4132 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4133DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
4134 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4135{
4136 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4137}
4138
4139
4140/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
4141 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4142DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
4143 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4144{
4145 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4146}
4147
4148
4149/** A64: Encodes an TST instruction w/ complicated immediate mask.
4150 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4151DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
4152 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4153{
4154 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4155}
4156
4157
4158/**
4159 * A64: Encodes a bitfield instruction.
4160 *
4161 * @returns The encoded instruction.
4162 * @param u2Opc The bitfield operation to perform.
4163 * @param iRegResult The output register.
4164 * @param iRegSrc The 1st register operand.
4165 * @param cImm6Ror The right rotation count.
4166 * @param uImm6S The leftmost bit to be moved.
4167 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
4168 * @param uN1 This must match @a f64Bit for all instructions
4169 * currently specified.
4170 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
4171 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
4172 */
4173DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
4174 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
4175{
4176 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
4177 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
4178 return ((uint32_t)f64Bit << 31)
4179 | (u2Opc << 29)
4180 | UINT32_C(0x13000000)
4181 | (uN1 << 22)
4182 | (cImm6Ror << 16)
4183 | (uImm6S << 10)
4184 | (iRegSrc << 5)
4185 | iRegResult;
4186}
4187
4188
4189/** A64: Encodes a SBFM instruction.
4190 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4191DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4192 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4193{
4194 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4195}
4196
4197
4198/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
4199 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4200DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
4201{
4202 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
4203}
4204
4205
4206/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
4207 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4208DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
4209{
4210 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
4211}
4212
4213
4214/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
4215 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4216DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
4217{
4218 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
4219}
4220
4221
4222/** A64: Encodes an ASR instruction w/ immediate shift value.
4223 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4224DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4225{
4226 uint32_t const cWidth = f64Bit ? 63 : 31;
4227 Assert(cShift > 0); Assert(cShift <= cWidth);
4228 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
4229}
4230
4231
4232/** A64: Encodes a BFM instruction.
4233 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4234DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4235 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4236{
4237 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4238}
4239
4240
4241/** A64: Encodes a BFI instruction (insert).
4242 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4243DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
4244 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4245{
4246 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4247 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
4248 cBitsWidth - 1, f64Bit);
4249}
4250
4251
4252/** A64: Encodes a BFC instruction (clear).
4253 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4254DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfc(uint32_t iRegResult,
4255 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4256{
4257 return Armv8A64MkInstrBfi(iRegResult, ARMV8_A64_REG_XZR, offFirstBit, cBitsWidth, f64Bit);
4258}
4259
4260
4261/** A64: Encodes a BFXIL instruction (insert low).
4262 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4263DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfxil(uint32_t iRegResult, uint32_t iRegSrc,
4264 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4265{
4266 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4267 Assert(offFirstBit + cBitsWidth <= (f64Bit ? 64U : 32U));
4268 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4269}
4270
4271
4272/** A64: Encodes an UBFM instruction.
4273 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4274DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4275 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4276{
4277 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4278}
4279
4280
4281/** A64: Encodes an UBFX instruction (zero extending extract).
4282 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4283DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
4284 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4285{
4286 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4287}
4288
4289
4290/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
4291 * shifted into destination).
4292 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4293DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
4294 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
4295{
4296 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
4297 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
4298}
4299
4300
4301/** A64: Encodes an LSL instruction w/ immediate shift value.
4302 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4303DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4304{
4305 uint32_t const cWidth = f64Bit ? 63 : 31;
4306 Assert(cShift > 0); Assert(cShift <= cWidth);
4307 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
4308 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
4309}
4310
4311
4312/** A64: Encodes an LSR instruction w/ immediate shift value.
4313 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4314DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4315{
4316 uint32_t const cWidth = f64Bit ? 63 : 31;
4317 Assert(cShift > 0); Assert(cShift <= cWidth);
4318 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
4319}
4320
4321
4322/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
4323 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4324DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4325{
4326 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
4327}
4328
4329
4330/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
4331 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4332DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4333{
4334 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
4335}
4336
4337
4338/**
4339 * A64: Encodes an EXTR instruction with an immediate.
4340 *
4341 * @returns The encoded instruction.
4342 * @param iRegResult The register to store the result in. ZR is valid.
4343 * @param iRegLow The register holding the least significant bits in the
4344 * extraction. ZR is valid.
4345 * @param iRegHigh The register holding the most significant bits in the
4346 * extraction. ZR is valid.
4347 * @param uLsb The bit number of the least significant bit, or where in
4348 * @a iRegLow to start the
4349 * extraction.
4350 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4351 */
4352DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
4353 bool f64Bit = true)
4354{
4355 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
4356 return ((uint32_t)f64Bit << 31)
4357 | UINT32_C(0x13800000)
4358 | ((uint32_t)f64Bit << 22) /*N*/
4359 | (iRegHigh << 16)
4360 | (uLsb << 10)
4361 | (iRegLow << 5)
4362 | iRegResult;
4363}
4364
4365
4366/** A64: Rotates the value of a register (alias for EXTR). */
4367DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4368{
4369 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
4370}
4371
4372
4373/**
4374 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
4375 *
4376 * @returns The encoded instruction.
4377 * @param fSub true for sub and subs, false for add and
4378 * adds.
4379 * @param iRegResult The register to store the result in.
4380 * SP is valid when @a fSetFlags = false,
4381 * and ZR is valid otherwise.
4382 * @param iRegSrc The register containing the augend (@a fSub
4383 * = false) or minuend (@a fSub = true). SP is
4384 * a valid registers for all variations.
4385 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
4386 * (@a fSub = true).
4387 * @param f64Bit true for 64-bit GRPs (default), false for
4388 * 32-bit GPRs.
4389 * @param fSetFlags Whether to set flags (adds / subs) or not
4390 * (add / sub - default).
4391 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
4392 * bits to the left, or not (default).
4393 */
4394DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
4395 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
4396 bool fSetFlags = false, bool fShift12 = false)
4397{
4398 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
4399 return ((uint32_t)f64Bit << 31)
4400 | ((uint32_t)fSub << 30)
4401 | ((uint32_t)fSetFlags << 29)
4402 | UINT32_C(0x11000000)
4403 | ((uint32_t)fShift12 << 22)
4404 | (uImm12AddendSubtrahend << 10)
4405 | (iRegSrc << 5)
4406 | iRegResult;
4407}
4408
4409
4410/** Alias for sub zxr, reg, \#uimm12. */
4411DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
4412 bool f64Bit = true, bool fShift12 = false)
4413{
4414 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
4415 f64Bit, true /*fSetFlags*/, fShift12);
4416}
4417
4418
4419/** ADD dst, src, \#uimm12 */
4420DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
4421 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4422{
4423 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
4424}
4425
4426
4427/** SUB dst, src, \#uimm12 */
4428DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
4429 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4430{
4431 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
4432}
4433
4434
4435/**
4436 * A64: Encodes either add, adds, sub or subs with shifted register.
4437 *
4438 * @returns The encoded instruction.
4439 * @param fSub true for sub and subs, false for add and
4440 * adds.
4441 * @param iRegResult The register to store the result in.
4442 * SP is NOT valid, but ZR is.
4443 * @param iRegSrc1 The register containing the augend (@a fSub
4444 * = false) or minuend (@a fSub = true).
4445 * SP is NOT valid, but ZR is.
4446 * @param iRegSrc2 The register containing the addened (@a fSub
4447 * = false) or subtrahend (@a fSub = true).
4448 * SP is NOT valid, but ZR is.
4449 * @param f64Bit true for 64-bit GRPs (default), false for
4450 * 32-bit GPRs.
4451 * @param fSetFlags Whether to set flags (adds / subs) or not
4452 * (add / sub - default).
4453 * @param cShift The shift count to apply to @a iRegSrc2.
4454 * @param enmShift The shift type to apply to the @a iRegSrc2
4455 * register. kArmv8A64InstrShift_Ror is
4456 * reserved.
4457 */
4458DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4459 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4460 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4461{
4462 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4463 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
4464
4465 return ((uint32_t)f64Bit << 31)
4466 | ((uint32_t)fSub << 30)
4467 | ((uint32_t)fSetFlags << 29)
4468 | UINT32_C(0x0b000000)
4469 | ((uint32_t)enmShift << 22)
4470 | (iRegSrc2 << 16)
4471 | (cShift << 10)
4472 | (iRegSrc1 << 5)
4473 | iRegResult;
4474}
4475
4476
4477/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
4478DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
4479 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4480{
4481 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
4482 f64Bit, true /*fSetFlags*/, cShift, enmShift);
4483}
4484
4485
4486/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4487DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4488 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4489 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4490{
4491 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4492}
4493
4494
4495/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4496DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4497 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4498 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4499{
4500 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4501}
4502
4503
4504/** NEG dst */
4505DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
4506{
4507 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
4508}
4509
4510
4511/** Extension option for 'extended register' instructions. */
4512typedef enum ARMV8A64INSTREXTEND
4513{
4514 kArmv8A64InstrExtend_UxtB = 0,
4515 kArmv8A64InstrExtend_UxtH,
4516 kArmv8A64InstrExtend_UxtW,
4517 kArmv8A64InstrExtend_UxtX,
4518 kArmv8A64InstrExtend_SxtB,
4519 kArmv8A64InstrExtend_SxtH,
4520 kArmv8A64InstrExtend_SxtW,
4521 kArmv8A64InstrExtend_SxtX,
4522 /** The default is either UXTW or UXTX depending on whether the instruction
4523 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
4524 * to the f64Bit value. */
4525 kArmv8A64InstrExtend_Default
4526} ARMV8A64INSTREXTEND;
4527
4528
4529/**
4530 * A64: Encodes either add, adds, sub or subs with extended register encoding.
4531 *
4532 * @returns The encoded instruction.
4533 * @param fSub true for sub and subs, false for add and
4534 * adds.
4535 * @param iRegResult The register to store the result in.
4536 * SP is NOT valid, but ZR is.
4537 * @param iRegSrc1 The register containing the augend (@a fSub
4538 * = false) or minuend (@a fSub = true).
4539 * SP is valid, but ZR is NOT.
4540 * @param iRegSrc2 The register containing the addened (@a fSub
4541 * = false) or subtrahend (@a fSub = true).
4542 * SP is NOT valid, but ZR is.
4543 * @param f64Bit true for 64-bit GRPs (default), false for
4544 * 32-bit GPRs.
4545 * @param fSetFlags Whether to set flags (adds / subs) or not
4546 * (add / sub - default).
4547 * @param enmExtend The type of extension to apply to @a
4548 * iRegSrc2.
4549 * @param cShift The left shift count to apply to @a iRegSrc2
4550 * after enmExtend processing is done.
4551 * Max shift is 4 for some reason.
4552 */
4553DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4554 bool f64Bit = true, bool fSetFlags = false,
4555 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
4556 uint32_t cShift = 0)
4557{
4558 if (enmExtend == kArmv8A64InstrExtend_Default)
4559 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
4560 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
4561
4562 return ((uint32_t)f64Bit << 31)
4563 | ((uint32_t)fSub << 30)
4564 | ((uint32_t)fSetFlags << 29)
4565 | UINT32_C(0x0b200000)
4566 | (iRegSrc2 << 16)
4567 | ((uint32_t)enmExtend << 13)
4568 | (cShift << 10)
4569 | (iRegSrc1 << 5)
4570 | iRegResult;
4571}
4572
4573
4574/**
4575 * A64: Encodes either adc, adcs, sbc or sbcs with two source registers.
4576 *
4577 * @returns The encoded instruction.
4578 * @param fSub true for sbc and sbcs, false for adc and
4579 * adcs.
4580 * @param iRegResult The register to store the result in. SP is
4581 * NOT valid, but ZR is.
4582 * @param iRegSrc1 The register containing the augend (@a fSub
4583 * = false) or minuend (@a fSub = true).
4584 * SP is NOT valid, but ZR is.
4585 * @param iRegSrc2 The register containing the addened (@a fSub
4586 * = false) or subtrahend (@a fSub = true).
4587 * SP is NOT valid, but ZR is.
4588 * @param f64Bit true for 64-bit GRPs (default), false for
4589 * 32-bit GPRs.
4590 * @param fSetFlags Whether to set flags (adds / subs) or not
4591 * (add / sub - default).
4592 */
4593DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcSbc(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4594 bool f64Bit = true, bool fSetFlags = false)
4595{
4596 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4597
4598 return ((uint32_t)f64Bit << 31)
4599 | ((uint32_t)fSub << 30)
4600 | ((uint32_t)fSetFlags << 29)
4601 | UINT32_C(0x1a000000)
4602 | (iRegSrc2 << 16)
4603 | (iRegSrc1 << 5)
4604 | iRegResult;
4605}
4606
4607
4608/** ADC dst, reg1, reg2 */
4609DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4610 bool f64Bit = true, bool fSetFlags = false)
4611{
4612 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4613}
4614
4615
4616/** ADCS dst, reg1, reg2 */
4617DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4618{
4619 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4620}
4621
4622
4623/** SBC dst, reg1, reg2 */
4624DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4625 bool f64Bit = true, bool fSetFlags = false)
4626{
4627 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4628}
4629
4630
4631/** SBCS dst, reg1, reg2 */
4632DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4633{
4634 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4635}
4636
4637
4638/**
4639 * A64: Encodes a B (unconditional branch w/ imm) instruction.
4640 *
4641 * @returns The encoded instruction.
4642 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4643 */
4644DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
4645{
4646 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
4647 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
4648}
4649
4650
4651/**
4652 * A64: Encodes a BL (unconditional call w/ imm) instruction.
4653 *
4654 * @returns The encoded instruction.
4655 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4656 */
4657DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
4658{
4659 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
4660}
4661
4662
4663/**
4664 * A64: Encodes a BR (unconditional branch w/ register) instruction.
4665 *
4666 * @returns The encoded instruction.
4667 * @param iReg The register containing the target address.
4668 */
4669DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
4670{
4671 Assert(iReg < 32);
4672 return UINT32_C(0xd61f0000) | (iReg << 5);
4673}
4674
4675
4676/**
4677 * A64: Encodes a BLR instruction.
4678 *
4679 * @returns The encoded instruction.
4680 * @param iReg The register containing the target address.
4681 */
4682DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
4683{
4684 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
4685}
4686
4687
4688/**
4689 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
4690 *
4691 * @returns The encoded instruction.
4692 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4693 * its not zero.
4694 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4695 * @param iReg The GPR to check for zero / non-zero value.
4696 * @param f64Bit true for 64-bit register, false for 32-bit.
4697 */
4698DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4699{
4700 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
4701 return ((uint32_t)f64Bit << 31)
4702 | UINT32_C(0x34000000)
4703 | ((uint32_t)fJmpIfNotZero << 24)
4704 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4705 | iReg;
4706}
4707
4708
4709/** A64: Encodes the CBZ instructions. */
4710DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4711{
4712 return Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4713}
4714
4715
4716/** A64: Encodes the CBNZ instructions. */
4717DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbnz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4718{
4719 return Armv8A64MkInstrCbzCbnz(true /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4720}
4721
4722
4723/**
4724 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
4725 *
4726 * @returns The encoded instruction.
4727 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4728 * its not zero.
4729 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4730 * @param iReg The GPR to check for zero / non-zero value.
4731 * @param iBitNo The bit to test for.
4732 */
4733DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4734{
4735 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
4736 return ((uint32_t)(iBitNo & 0x20) << (31-5))
4737 | UINT32_C(0x36000000)
4738 | ((uint32_t)fJmpIfNotZero << 24)
4739 | ((iBitNo & 0x1f) << 19)
4740 | (((uint32_t)iImm14 & 0x3fff) << 5)
4741 | iReg;
4742}
4743
4744
4745/**
4746 * A64: Encodes TBZ (conditional branch w/ immediate) instructions.
4747 *
4748 * @returns The encoded instruction.
4749 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4750 * @param iReg The GPR to check for zero / non-zero value.
4751 * @param iBitNo The bit to test for.
4752 */
4753DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4754{
4755 return Armv8A64MkInstrTbzTbnz(false /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4756}
4757
4758
4759/**
4760 * A64: Encodes TBNZ (conditional branch w/ immediate) instructions.
4761 *
4762 * @returns The encoded instruction.
4763 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4764 * @param iReg The GPR to check for zero / non-zero value.
4765 * @param iBitNo The bit to test for.
4766 */
4767DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbnz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4768{
4769 return Armv8A64MkInstrTbzTbnz(true /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4770}
4771
4772
4773
4774/** Armv8 Condition codes. */
4775typedef enum ARMV8INSTRCOND
4776{
4777 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
4778 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
4779
4780 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
4781 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
4782 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
4783 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
4784
4785 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
4786 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
4787
4788 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
4789 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
4790
4791 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
4792 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
4793
4794 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
4795 kArmv8InstrCond_Lt, /**< b - Signed less than. */
4796
4797 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
4798 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
4799
4800 kArmv8InstrCond_Al, /**< e - Condition is always true. */
4801 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
4802} ARMV8INSTRCOND;
4803
4804/**
4805 * A64: Encodes conditional branch instruction w/ immediate target.
4806 *
4807 * @returns The encoded instruction.
4808 * @param enmCond The branch condition.
4809 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4810 */
4811DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
4812{
4813 Assert((unsigned)enmCond < 16);
4814 return UINT32_C(0x54000000)
4815 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4816 | (uint32_t)enmCond;
4817}
4818
4819
4820/**
4821 * A64: Encodes the BRK instruction.
4822 *
4823 * @returns The encoded instruction.
4824 * @param uImm16 Unsigned immediate value.
4825 */
4826DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
4827{
4828 Assert(uImm16 < _64K);
4829 return UINT32_C(0xd4200000)
4830 | (uImm16 << 5);
4831}
4832
4833/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
4834 * @{ */
4835#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
4836#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
4837#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
4838#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
4839#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
4840#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
4841#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
4842#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
4843
4844#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
4845#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
4846#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
4847#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
4848#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
4849#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
4850#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
4851#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
4852/** @} */
4853
4854/**
4855 * A64: Encodes CCMP or CCMN with two register operands.
4856 *
4857 * @returns The encoded instruction.
4858 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
4859 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
4860 * @param fNzcv The N, Z, C & V flags values to load if the condition
4861 * does not match. See RMA64_NZCV_F_XXX.
4862 * @param enmCond The condition guarding the compare.
4863 * @param fCCmp Set for CCMP (default), clear for CCMN.
4864 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4865 */
4866DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4867 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
4868{
4869 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
4870
4871 return ((uint32_t)f64Bit << 31)
4872 | ((uint32_t)fCCmp << 30)
4873 | UINT32_C(0x3a400000)
4874 | (iRegSrc2 << 16)
4875 | ((uint32_t)enmCond << 12)
4876 | (iRegSrc1 << 5)
4877 | fNzcv;
4878}
4879
4880/** CCMP w/ reg. */
4881DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4882 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4883{
4884 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4885}
4886
4887
4888/** CCMN w/ reg. */
4889DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4890 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4891{
4892 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4893}
4894
4895
4896/**
4897 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
4898 *
4899 * @returns The encoded instruction.
4900 * @param iRegSrc The register. SP is NOT valid, but ZR is.
4901 * @param uImm5 The immediate, to compare iRegSrc with.
4902 * @param fNzcv The N, Z, C & V flags values to load if the condition
4903 * does not match. See RMA64_NZCV_F_XXX.
4904 * @param enmCond The condition guarding the compare.
4905 * @param fCCmp Set for CCMP (default), clear for CCMN.
4906 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4907 */
4908DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
4909 bool fCCmp = true, bool f64Bit = true)
4910{
4911 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
4912
4913 return ((uint32_t)f64Bit << 31)
4914 | ((uint32_t)fCCmp << 30)
4915 | UINT32_C(0x3a400800)
4916 | (uImm5 << 16)
4917 | ((uint32_t)enmCond << 12)
4918 | (iRegSrc << 5)
4919 | fNzcv;
4920}
4921
4922/** CCMP w/ immediate. */
4923DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4924 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4925{
4926 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4927}
4928
4929
4930/** CCMN w/ immediate. */
4931DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4932 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4933{
4934 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4935}
4936
4937
4938/**
4939 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
4940 *
4941 * @returns The encoded instruction.
4942 * @param uOp Opcode bit 30.
4943 * @param uOp2 Opcode bits 11:10.
4944 * @param iRegResult The result register. SP is NOT valid, but ZR is.
4945 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
4946 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
4947 * @param enmCond The condition guarding the compare.
4948 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4949 */
4950DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
4951 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4952{
4953 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4954
4955 return ((uint32_t)f64Bit << 31)
4956 | (uOp << 30)
4957 | UINT32_C(0x1a800000)
4958 | (iRegSrc2 << 16)
4959 | ((uint32_t)enmCond << 12)
4960 | (uOp2 << 10)
4961 | (iRegSrc1 << 5)
4962 | iRegResult;
4963}
4964
4965
4966/** A64: Encodes CSEL.
4967 * @see Armv8A64MkInstrCondSelect for details. */
4968DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4969 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4970{
4971 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4972}
4973
4974
4975/** A64: Encodes CSINC.
4976 * @see Armv8A64MkInstrCondSelect for details. */
4977DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4978 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4979{
4980 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4981}
4982
4983
4984/** A64: Encodes CSET.
4985 * @see Armv8A64MkInstrCondSelect for details. */
4986DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4987{
4988 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4989 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4990 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4991}
4992
4993
4994/** A64: Encodes CSINV.
4995 * @see Armv8A64MkInstrCondSelect for details. */
4996DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4997 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4998{
4999 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
5000}
5001
5002/** A64: Encodes CSETM.
5003 * @see Armv8A64MkInstrCondSelect for details. */
5004DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
5005{
5006 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
5007 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
5008 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
5009}
5010
5011
5012/** A64: Encodes CSNEG.
5013 * @see Armv8A64MkInstrCondSelect for details. */
5014DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
5015 ARMV8INSTRCOND enmCond, bool f64Bit = true)
5016{
5017 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
5018}
5019
5020
5021/**
5022 * A64: Encodes REV instruction.
5023 *
5024 * @returns The encoded instruction.
5025 * @param iRegDst The destination register. SP is NOT valid.
5026 * @param iRegSrc The source register. SP is NOT valid, but ZR is
5027 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
5028 */
5029DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
5030{
5031 Assert(iRegDst < 32); Assert(iRegSrc < 32);
5032
5033 return ((uint32_t)f64Bit << 31)
5034 | UINT32_C(0x5ac00800)
5035 | ((uint32_t)f64Bit << 10)
5036 | (iRegSrc << 5)
5037 | iRegDst;
5038}
5039
5040
5041/**
5042 * A64: Encodes REV16 instruction.
5043 *
5044 * @returns The encoded instruction.
5045 * @param iRegDst The destination register. SP is NOT valid.
5046 * @param iRegSrc The source register. SP is NOT valid, but ZR is
5047 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
5048 */
5049DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
5050{
5051 Assert(iRegDst < 32); Assert(iRegSrc < 32);
5052
5053 return ((uint32_t)f64Bit << 31)
5054 | UINT32_C(0x5ac00400)
5055 | (iRegSrc << 5)
5056 | iRegDst;
5057}
5058
5059
5060/**
5061 * A64: Encodes SETF8 & SETF16.
5062 *
5063 * @returns The encoded instruction.
5064 * @param iRegResult The register holding the result. SP is NOT valid.
5065 * @param f16Bit Set for SETF16, clear for SETF8.
5066 */
5067DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
5068{
5069 Assert(iRegResult < 32);
5070
5071 return UINT32_C(0x3a00080d)
5072 | ((uint32_t)f16Bit << 14)
5073 | (iRegResult << 5);
5074}
5075
5076
5077/**
5078 * A64: Encodes RMIF.
5079 *
5080 * @returns The encoded instruction.
5081 * @param iRegSrc The source register to get flags from.
5082 * @param cRotateRight The right rotate count (LSB bit offset).
5083 * @param fMask Mask of which flag bits to set:
5084 * - bit 0: V
5085 * - bit 1: C
5086 * - bit 2: Z
5087 * - bit 3: N
5088 */
5089DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRmif(uint32_t iRegSrc, uint32_t cRotateRight, uint32_t fMask)
5090{
5091 Assert(iRegSrc < 32); Assert(cRotateRight < 64); Assert(fMask <= 0xf);
5092
5093 return UINT32_C(0xba000400)
5094 | (cRotateRight << 15)
5095 | (iRegSrc << 5)
5096 | fMask;
5097}
5098
5099
5100/**
5101 * A64: Encodes MRS (for reading a system register into a GPR).
5102 *
5103 * @returns The encoded instruction.
5104 * @param iRegDst The register to put the result into. SP is NOT valid.
5105 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
5106 * IPRT specific format, of the register to read.
5107 */
5108DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
5109{
5110 Assert(iRegDst < 32);
5111 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
5112
5113 /* Note. The top bit of idSysReg must always be set and is also set in
5114 0xd5300000, otherwise we'll be encoding a different instruction. */
5115 return UINT32_C(0xd5300000)
5116 | (idSysReg << 5)
5117 | iRegDst;
5118}
5119
5120
5121/**
5122 * A64: Encodes MSR (for writing a GPR to a system register).
5123 *
5124 * @returns The encoded instruction.
5125 * @param iRegSrc The register which value to write. SP is NOT valid.
5126 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
5127 * IPRT specific format, of the register to write.
5128 */
5129DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
5130{
5131 Assert(iRegSrc < 32);
5132 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
5133
5134 /* Note. The top bit of idSysReg must always be set and is also set in
5135 0xd5100000, otherwise we'll be encoding a different instruction. */
5136 return UINT32_C(0xd5100000)
5137 | (idSysReg << 5)
5138 | iRegSrc;
5139}
5140
5141
5142/** @} */
5143
5144
5145/** @defgroup grp_rt_armv8_mkinstr_vec Vector Instruction Encoding Helpers
5146 * @ingroup grp_rt_armv8_mkinstr
5147 *
5148 * A few inlined functions and macros for assisting in encoding common ARMv8
5149 * Neon/SIMD instructions.
5150 *
5151 * @{ */
5152
5153/** Armv8 vector logical operation. */
5154typedef enum
5155{
5156 kArmv8VecInstrLogicOp_And = 0, /**< AND */
5157 kArmv8VecInstrLogicOp_Bic = RT_BIT_32(22), /**< BIC */
5158 kArmv8VecInstrLogicOp_Orr = RT_BIT_32(23), /**< ORR */
5159 kArmv8VecInstrLogicOp_Orn = RT_BIT_32(23) | RT_BIT_32(22), /**< ORN */
5160 kArmv8VecInstrLogicOp_Eor = RT_BIT_32(29), /**< EOR */
5161 kArmv8VecInstrLogicOp_Bsl = RT_BIT_32(29) | RT_BIT_32(22), /**< BSL */
5162 kArmv8VecInstrLogicOp_Bit = RT_BIT_32(29) | RT_BIT_32(23), /**< BIT */
5163 kArmv8VecInstrLogicOp_Bif = RT_BIT_32(29) | RT_BIT_32(23) | RT_BIT_32(22) /**< BIF */
5164} ARMV8INSTRVECLOGICOP;
5165
5166
5167/**
5168 * A64: Encodes logical instruction (vector, register).
5169 *
5170 * @returns The encoded instruction.
5171 * @param enmOp The operation to encode.
5172 * @param iVecRegDst The vector register to put the result into.
5173 * @param iVecRegSrc1 The 1st source register.
5174 * @param iVecRegSrc2 The 2nd source register.
5175 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5176 * or just the low 64-bit (false).
5177 */
5178DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrLogical(ARMV8INSTRVECLOGICOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5179 bool f128Bit = true)
5180{
5181 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5182
5183 return UINT32_C(0x0e201c00)
5184 | (uint32_t)enmOp
5185 | ((uint32_t)f128Bit << 30)
5186 | (iVecRegSrc2 << 16)
5187 | (iVecRegSrc1 << 5)
5188 | iVecRegDst;
5189}
5190
5191
5192/**
5193 * A64: Encodes ORR (vector, register).
5194 *
5195 * @returns The encoded instruction.
5196 * @param iVecRegDst The vector register to put the result into.
5197 * @param iVecRegSrc1 The 1st source register.
5198 * @param iVecRegSrc2 The 2nd source register.
5199 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5200 * or just the low 64-bit (false).
5201 */
5202DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrOrr(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5203 bool f128Bit = true)
5204{
5205 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Orr, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5206}
5207
5208
5209/**
5210 * A64: Encodes EOR (vector, register).
5211 *
5212 * @returns The encoded instruction.
5213 * @param iVecRegDst The vector register to put the result into.
5214 * @param iVecRegSrc1 The 1st source register.
5215 * @param iVecRegSrc2 The 2nd source register.
5216 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5217 * or just the low 64-bit (false).
5218 */
5219DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrEor(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5220 bool f128Bit = true)
5221{
5222 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Eor, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5223}
5224
5225
5226/**
5227 * A64: Encodes AND (vector, register).
5228 *
5229 * @returns The encoded instruction.
5230 * @param iVecRegDst The vector register to put the result into.
5231 * @param iVecRegSrc1 The 1st source register.
5232 * @param iVecRegSrc2 The 2nd source register.
5233 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5234 * or just the low 64-bit (false).
5235 */
5236DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAnd(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5237 bool f128Bit = true)
5238{
5239 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_And, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5240}
5241
5242
5243/** Armv8 UMOV/INS vector element size. */
5244typedef enum ARMV8INSTRUMOVINSSZ
5245{
5246 kArmv8InstrUmovInsSz_U8 = 0, /**< Byte. */
5247 kArmv8InstrUmovInsSz_U16 = 1, /**< Halfword. */
5248 kArmv8InstrUmovInsSz_U32 = 2, /**< 32-bit. */
5249 kArmv8InstrUmovInsSz_U64 = 3 /**< 64-bit (only valid when the destination is a 64-bit register. */
5250} ARMV8INSTRUMOVINSSZ;
5251
5252
5253/**
5254 * A64: Encodes UMOV (vector, register).
5255 *
5256 * @returns The encoded instruction.
5257 * @param iRegDst The register to put the result into.
5258 * @param iVecRegSrc The vector source register.
5259 * @param idxElem The element index.
5260 * @param enmSz Element size of the source vector register.
5261 * @param fDst64Bit Flag whether the destination register is 64-bit (true) or 32-bit (false).
5262 */
5263DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUmov(uint32_t iRegDst, uint32_t iVecRegSrc, uint8_t idxElem,
5264 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64, bool fDst64Bit = true)
5265{
5266 Assert(iRegDst < 32); Assert(iVecRegSrc < 32);
5267 Assert((fDst64Bit && enmSz == kArmv8InstrUmovInsSz_U64) || (!fDst64Bit && enmSz != kArmv8InstrUmovInsSz_U64));
5268 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5269 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5270 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5271 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5272
5273 return UINT32_C(0x0e003c00)
5274 | ((uint32_t)fDst64Bit << 30)
5275 | ((uint32_t)idxElem << (16 + enmSz + 1))
5276 | (RT_BIT_32(enmSz) << 16)
5277 | (iVecRegSrc << 5)
5278 | iRegDst;
5279}
5280
5281
5282/**
5283 * A64: Encodes INS (vector, register).
5284 *
5285 * @returns The encoded instruction.
5286 * @param iVecRegDst The vector register to put the result into.
5287 * @param iRegSrc The source register.
5288 * @param idxElem The element index for the destination.
5289 * @param enmSz Element size of the source vector register.
5290 *
5291 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5292 */
5293DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrIns(uint32_t iVecRegDst, uint32_t iRegSrc, uint8_t idxElem,
5294 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64)
5295{
5296 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5297 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5298 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5299 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5300 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5301
5302 return UINT32_C(0x4e001c00)
5303 | ((uint32_t)idxElem << (16 + enmSz + 1))
5304 | (RT_BIT_32(enmSz) << 16)
5305 | (iRegSrc << 5)
5306 | iVecRegDst;
5307}
5308
5309
5310/**
5311 * A64: Encodes DUP (vector, register).
5312 *
5313 * @returns The encoded instruction.
5314 * @param iVecRegDst The vector register to put the result into.
5315 * @param iRegSrc The source register (ZR is valid).
5316 * @param enmSz Element size of the source vector register.
5317 * @param f128Bit Flag whether the instruction operates on the whole 128-bit of the vector register (true) or
5318 * just the low 64-bit (false).
5319 *
5320 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5321 */
5322DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrDup(uint32_t iVecRegDst, uint32_t iRegSrc, ARMV8INSTRUMOVINSSZ enmSz,
5323 bool f128Bit = true)
5324{
5325 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5326 Assert( (enmSz == kArmv8InstrUmovInsSz_U8)
5327 || (enmSz == kArmv8InstrUmovInsSz_U16)
5328 || (enmSz == kArmv8InstrUmovInsSz_U32)
5329 || (enmSz == kArmv8InstrUmovInsSz_U64));
5330
5331 return UINT32_C(0x0e000c00)
5332 | ((uint32_t)f128Bit << 30)
5333 | (RT_BIT_32(enmSz) << 16)
5334 | (iRegSrc << 5)
5335 | iVecRegDst;
5336}
5337
5338
5339/** Armv8 vector compare to zero vector element size. */
5340typedef enum ARMV8INSTRVECCMPZEROSZ
5341{
5342 kArmv8InstrCmpZeroSz_S8 = 0, /**< Byte. */
5343 kArmv8InstrCmpZeroSz_S16 = 1, /**< Halfword. */
5344 kArmv8InstrCmpZeroSz_S32 = 2, /**< 32-bit. */
5345 kArmv8InstrCmpZeroSz_S64 = 3 /**< 64-bit. */
5346} ARMV8INSTRVECCMPZEROSZ;
5347
5348
5349/** Armv8 vector compare to zero vector operation. */
5350typedef enum ARMV8INSTRVECCMPZEROOP
5351{
5352 kArmv8InstrCmpZeroOp_Gt = 0, /**< Greater than. */
5353 kArmv8InstrCmpZeroOp_Ge = RT_BIT_32(29), /**< Greater than or equal to. */
5354 kArmv8InstrCmpZeroOp_Eq = RT_BIT_32(12), /**< Equal to. */
5355 kArmv8InstrCmpZeroOp_Le = RT_BIT_32(29) | RT_BIT_32(12) /**< Lower than or equal to. */
5356} ARMV8INSTRVECCMPZEROOP;
5357
5358
5359/**
5360 * A64: Encodes CMGT, CMGE, CMEQ or CMLE against zero (vector, register).
5361 *
5362 * @returns The encoded instruction.
5363 * @param iVecRegDst The vector register to put the result into.
5364 * @param iVecRegSrc The vector source register.
5365 * @param enmSz Vector element size.
5366 * @param enmOp The compare operation against to encode.
5367 */
5368DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpToZero(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECCMPZEROSZ enmSz,
5369 ARMV8INSTRVECCMPZEROOP enmOp)
5370{
5371 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5372
5373 return UINT32_C(0x5e208800)
5374 | ((uint32_t)enmSz << 22)
5375 | (RT_BIT_32(enmSz) << 16)
5376 | (iVecRegSrc << 5)
5377 | iVecRegDst
5378 | (uint32_t)enmOp;
5379}
5380
5381
5382/**
5383 * A64: Encodes CNT (vector, register).
5384 *
5385 * @returns The encoded instruction.
5386 * @param iVecRegDst The vector register to put the result into.
5387 * @param iVecRegSrc The vector source register.
5388 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5389 * or just the low 64-bit (false).
5390 */
5391DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCnt(uint32_t iVecRegDst, uint32_t iVecRegSrc, bool f128Bit = true)
5392{
5393 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5394
5395 return UINT32_C(0x0e205800)
5396 | ((uint32_t)f128Bit << 30)
5397 | (iVecRegSrc << 5)
5398 | iVecRegDst;
5399}
5400
5401
5402/** Armv8 vector unsigned sum long across vector element size. */
5403typedef enum ARMV8INSTRVECUADDLVSZ
5404{
5405 kArmv8InstrUAddLVSz_8B = 0, /**< 8 x 8-bit. */
5406 kArmv8InstrUAddLVSz_16B = RT_BIT_32(30), /**< 16 x 8-bit. */
5407 kArmv8InstrUAddLVSz_4H = 1, /**< 4 x 16-bit. */
5408 kArmv8InstrUAddLVSz_8H = RT_BIT_32(30) | 1, /**< 8 x 16-bit. */
5409 kArmv8InstrUAddLVSz_4S = RT_BIT_32(30) | 2 /**< 4 x 32-bit. */
5410} ARMV8INSTRVECUADDLVSZ;
5411
5412
5413/**
5414 * A64: Encodes UADDLV (vector, register).
5415 *
5416 * @returns The encoded instruction.
5417 * @param iVecRegDst The vector register to put the result into.
5418 * @param iVecRegSrc The vector source register.
5419 * @param enmSz Element size.
5420 */
5421DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUAddLV(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECUADDLVSZ enmSz)
5422{
5423 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5424
5425 return UINT32_C(0x2e303800)
5426 | ((uint32_t)enmSz)
5427 | (iVecRegSrc << 5)
5428 | iVecRegDst;
5429}
5430
5431
5432/** Armv8 USHR/USRA/URSRA/SSHR/SRSA/SSHR vector element size. */
5433typedef enum ARMV8INSTRUSHIFTSZ
5434{
5435 kArmv8InstrShiftSz_U8 = 8, /**< Byte. */
5436 kArmv8InstrShiftSz_U16 = 16, /**< Halfword. */
5437 kArmv8InstrShiftSz_U32 = 32, /**< 32-bit. */
5438 kArmv8InstrShiftSz_U64 = 64 /**< 64-bit. */
5439} ARMV8INSTRUSHIFTSZ;
5440
5441/**
5442 * A64: Encodes USHR/USRA/URSRA/SSHR/SRSA/SSHR (vector, register).
5443 *
5444 * @returns The encoded instruction.
5445 * @param iVecRegDst The vector register to put the result into.
5446 * @param iVecRegSrc The vector source register.
5447 * @param cShift Number of bits to shift.
5448 * @param enmSz Element size.
5449 * @param fUnsigned Flag whether this a signed or unsigned shift,
5450 * @param fRound Flag whether this is the rounding shift variant.
5451 * @param fAccum Flag whether this is the accumulate shift variant.
5452 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5453 * or just the low 64-bit (false).
5454 */
5455DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShrImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5456 bool fUnsigned = true, bool fRound = false, bool fAccum = false, bool f128Bit = true)
5457{
5458 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5459 Assert( cShift >= 1
5460 && ( (enmSz == kArmv8InstrShiftSz_U8 && cShift <= 8)
5461 || (enmSz == kArmv8InstrShiftSz_U16 && cShift <= 16)
5462 || (enmSz == kArmv8InstrShiftSz_U32 && cShift <= 32)
5463 || (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
5464
5465 return UINT32_C(0x0f000400)
5466 | ((uint32_t)f128Bit << 30)
5467 | ((uint32_t)fUnsigned << 29)
5468 | ((((uint32_t)enmSz << 1) - cShift) << 16)
5469 | ((uint32_t)fRound << 13)
5470 | ((uint32_t)fAccum << 12)
5471 | (iVecRegSrc << 5)
5472 | iVecRegDst;
5473}
5474
5475
5476/**
5477 * A64: Encodes SHL (vector, register).
5478 *
5479 * @returns The encoded instruction.
5480 * @param iVecRegDst The vector register to put the result into.
5481 * @param iVecRegSrc The vector source register.
5482 * @param cShift Number of bits to shift.
5483 * @param enmSz Element size.
5484 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5485 * or just the low 64-bit (false).
5486 */
5487DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5488 bool f128Bit = true)
5489{
5490 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5491 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5492 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5493 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
5494 || (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
5495
5496 return UINT32_C(0x0f005400)
5497 | ((uint32_t)f128Bit << 30)
5498 | (((uint32_t)enmSz | cShift) << 16)
5499 | (iVecRegSrc << 5)
5500 | iVecRegDst;
5501}
5502
5503
5504/**
5505 * A64: Encodes SHLL/SHLL2/USHLL/USHLL2 (vector, register).
5506 *
5507 * @returns The encoded instruction.
5508 * @param iVecRegDst The vector register to put the result into.
5509 * @param iVecRegSrc The vector source register.
5510 * @param cShift Number of bits to shift.
5511 * @param enmSz Element size of the source vector register, the destination vector register
5512 * element size is twice as large, kArmv8InstrShiftSz_U64 is invalid.
5513 * @param fUnsigned Flag whether this is an unsigned shift left (true, default) or signed (false).
5514 * @param fUpper Flag whether this operates on the lower half (false, default) of the source vector register
5515 * or the upper half (true).
5516 */
5517DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUShll(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5518 bool fUnsigned = true, bool fUpper = false)
5519{
5520 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5521 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5522 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5523 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32));
5524
5525 return UINT32_C(0x0f00a400)
5526 | ((uint32_t)fUpper << 30)
5527 | ((uint32_t)fUnsigned << 29)
5528 | (((uint32_t)enmSz | cShift) << 16)
5529 | (iVecRegSrc << 5)
5530 | iVecRegDst;
5531}
5532
5533
5534/** Armv8 vector arith ops element size. */
5535typedef enum ARMV8INSTRVECARITHSZ
5536{
5537 kArmv8VecInstrArithSz_8 = 0, /**< 8-bit. */
5538 kArmv8VecInstrArithSz_16 = 1, /**< 16-bit. */
5539 kArmv8VecInstrArithSz_32 = 2, /**< 32-bit. */
5540 kArmv8VecInstrArithSz_64 = 3 /**< 64-bit. */
5541} ARMV8INSTRVECARITHSZ;
5542
5543
5544/** Armv8 vector arithmetic operation. */
5545typedef enum
5546{
5547 kArmv8VecInstrArithOp_Add = RT_BIT_32(15), /**< ADD */
5548 kArmv8VecInstrArithOp_Sub = RT_BIT_32(29) | RT_BIT_32(15), /**< SUB */
5549 kArmv8VecInstrArithOp_UnsignSat_Add = RT_BIT_32(29) | RT_BIT_32(11), /**< UQADD */
5550 kArmv8VecInstrArithOp_UnsignSat_Sub = RT_BIT_32(29) | RT_BIT_32(13) | RT_BIT_32(11), /**< UQSUB */
5551 kArmv8VecInstrArithOp_SignSat_Add = RT_BIT_32(11), /**< SQADD */
5552 kArmv8VecInstrArithOp_SignSat_Sub = RT_BIT_32(13) | RT_BIT_32(11), /**< SQSUB */
5553 kArmv8VecInstrArithOp_Mul = RT_BIT_32(15) | RT_BIT_32(12) | RT_BIT_32(11) /**< MUL */
5554} ARMV8INSTRVECARITHOP;
5555
5556
5557/**
5558 * A64: Encodes an arithmetic operation (vector, register).
5559 *
5560 * @returns The encoded instruction.
5561 * @param enmOp The operation to encode.
5562 * @param iVecRegDst The vector register to put the result into.
5563 * @param iVecRegSrc1 The first vector source register.
5564 * @param iVecRegSrc2 The second vector source register.
5565 * @param enmSz Element size.
5566 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5567 * or just the low 64-bit (false).
5568 */
5569DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrArithOp(ARMV8INSTRVECARITHOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5570 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5571{
5572 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5573
5574 return UINT32_C(0x0e200400)
5575 | (uint32_t)enmOp
5576 | ((uint32_t)f128Bit << 30)
5577 | ((uint32_t)enmSz << 22)
5578 | (iVecRegSrc2 << 16)
5579 | (iVecRegSrc1 << 5)
5580 | iVecRegDst;
5581}
5582
5583
5584/** Armv8 vector compare operation. */
5585typedef enum ARMV8VECINSTRCMPOP
5586{
5587 /* U insn[15:10] */
5588 kArmv8VecInstrCmpOp_Gt = UINT32_C(0x3400), /**< Greater than (>) (signed) */
5589 kArmv8VecInstrCmpOp_Ge = UINT32_C(0x3c00), /**< Greater or equal (>=) (signed) */
5590 kArmv8VecInstrCmpOp_Hi = RT_BIT_32(29) | UINT32_C(0x3400), /**< Greater than (>) (unsigned) */
5591 kArmv8VecInstrCmpOp_Hs = RT_BIT_32(29) | UINT32_C(0x3c00), /**< Greater or equal (>=) (unsigned) */
5592 kArmv8VecInstrCmpOp_Eq = RT_BIT_32(29) | UINT32_C(0x8c00) /**< Equal (==) (unsigned) */
5593} ARMV8VECINSTRCMPOP;
5594
5595/**
5596 * A64: Encodes CMEQ/CMGE/CMGT/CMHI/CMHS (register variant) (vector, register).
5597 *
5598 * @returns The encoded instruction.
5599 * @param enmOp The operation to perform.
5600 * @param iVecRegDst The vector register to put the result into.
5601 * @param iVecRegSrc1 The first vector source register.
5602 * @param iVecRegSrc2 The second vector source register.
5603 * @param enmSz Element size.
5604 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5605 * or just the low 64-bit (false).
5606 */
5607DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmp(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5608 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5609{
5610 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5611
5612 return UINT32_C(0x0e200000)
5613 | ((uint32_t)f128Bit << 30)
5614 | ((uint32_t)enmSz << 22)
5615 | (iVecRegSrc2 << 16)
5616 | ((uint32_t)enmOp)
5617 | (iVecRegSrc1 << 5)
5618 | iVecRegDst;
5619}
5620
5621
5622/** Armv8 vector compare against zero operation. */
5623typedef enum ARMV8VECINSTRCMPZEROOP
5624{
5625 /* U insn[15:10] */
5626 kArmv8VecInstrCmpZeroOp_Gt = UINT32_C(0x8800), /**< Greater than zero (>) (signed) */
5627 kArmv8VecInstrCmpZeroOp_Eq = UINT32_C(0x9800), /**< Equal to zero (==) */
5628 kArmv8VecInstrCmpZeroOp_Lt = UINT32_C(0xa800), /**< Lower than zero (>=) (signed) */
5629 kArmv8VecInstrCmpZeroOp_Ge = RT_BIT_32(29) | UINT32_C(0x8800), /**< Greater or equal to zero (>=) (signed) */
5630 kArmv8VecInstrCmpZeroOp_Le = RT_BIT_32(29) | UINT32_C(0x9800) /**< Lower or equal to zero (<=) (signed) */
5631} ARMV8VECINSTRCMPZEROOP;
5632
5633/**
5634 * A64: Encodes CMEQ/CMGE/CMGT/CMLE/CMLT (zero variant) (vector, register).
5635 *
5636 * @returns The encoded instruction.
5637 * @param enmOp The operation to perform.
5638 * @param iVecRegDst The vector register to put the result into.
5639 * @param iVecRegSrc The first vector source register.
5640 * @param enmSz Element size.
5641 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5642 * or just the low 64-bit (false).
5643 */
5644DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpAgainstZero(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc,
5645 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5646{
5647 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5648
5649 return UINT32_C(0x0e200000)
5650 | ((uint32_t)f128Bit << 30)
5651 | ((uint32_t)enmSz << 22)
5652 | ((uint32_t)enmOp)
5653 | (iVecRegSrc << 5)
5654 | iVecRegDst;
5655}
5656
5657
5658/** Armv8 [Signed,Unsigned] Extract {Unsigned} operation. */
5659typedef enum
5660{
5661 kArmv8VecInstrQxtnOp_Sqxtn = RT_BIT_32(14), /**< SQXTN */
5662 kArmv8VecInstrQxtnOp_Sqxtun = RT_BIT_32(29) | RT_BIT_32(13), /**< SQXTUN */
5663 kArmv8VecInstrQxtnOp_Uqxtn = RT_BIT_32(29) | RT_BIT_32(14) /**< UQXTN */
5664} ARMV8INSTRVECQXTNOP;
5665
5666/**
5667 * A64: Encodes SQXTN/SQXTN2/UQXTN/UQXTN2/SQXTUN/SQXTUN2 (vector, register).
5668 *
5669 * @returns The encoded instruction.
5670 * @param enmOp The operation to perform.
5671 * @param fUpper Flag whether to write the result to the lower (false) or upper (true) half of the destinatiom register.
5672 * @param iVecRegDst The vector register to put the result into.
5673 * @param iVecRegSrc The first vector source register.
5674 * @param enmSz Element size.
5675 */
5676DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrQxtn(ARMV8INSTRVECQXTNOP enmOp, bool fUpper, uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECARITHSZ enmSz)
5677{
5678 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5679
5680 return UINT32_C(0x0e210800)
5681 | ((uint32_t)enmOp)
5682 | ((uint32_t)fUpper << 30)
5683 | ((uint32_t)enmSz << 22)
5684 | (iVecRegSrc << 5)
5685 | iVecRegDst;
5686}
5687
5688
5689/** Armv8 floating point size. */
5690typedef enum
5691{
5692 kArmv8VecInstrFpSz_2x_Single = 0, /**< 2x single precision values in the low 64-bit of the 128-bit register. */
5693 kArmv8VecInstrFpSz_4x_Single = RT_BIT_32(30), /**< 4x single precision values in the 128-bit register. */
5694 kArmv8VecInstrFpSz_2x_Double = RT_BIT_32(30) | RT_BIT_32(22) /**< 2x double precision values in the 128-bit register. */
5695} ARMV8INSTRVECFPSZ;
5696
5697
5698/** Armv8 3 operand floating point operation. */
5699typedef enum
5700{
5701 /* insn[29] insn[23] insn[15:11] */
5702 kArmv8VecInstrFpOp_Add = UINT32_C(0xd000), /**< FADD */
5703 kArmv8VecInstrFpOp_Sub = RT_BIT_32(23) | UINT32_C(0xd000), /**< FADD */
5704 kArmv8VecInstrFpOp_AddPairwise = RT_BIT_32(29) | UINT32_C(0xd000), /**< FADDP */
5705 kArmv8VecInstrFpOp_Mul = RT_BIT_32(29) | UINT32_C(0xd800), /**< FMUL */
5706 kArmv8VecInstrFpOp_Div = RT_BIT_32(29) | UINT32_C(0xf800), /**< FDIV */
5707
5708 kArmv8VecInstrFpOp_Max = UINT32_C(0xf000), /**< FMAX */
5709 kArmv8VecInstrFpOp_MaxNumber = UINT32_C(0xc000), /**< FMAXNM */
5710 kArmv8VecInstrFpOp_MaxNumberPairwise = RT_BIT_32(29) | UINT32_C(0xc000), /**< FMAXNMP */
5711 kArmv8VecInstrFpOp_MaxPairwise = RT_BIT_32(29) | UINT32_C(0xf000), /**< FMAXP */
5712
5713 kArmv8VecInstrFpOp_Min = RT_BIT_32(23) | UINT32_C(0xf000), /**< FMIN */
5714 kArmv8VecInstrFpOp_MinNumber = RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNM */
5715 kArmv8VecInstrFpOp_MinNumberPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNMP */
5716 kArmv8VecInstrFpOp_MinPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xf000), /**< FMINP */
5717
5718 kArmv8VecInstrFpOp_Fmla = UINT32_C(0xc800), /**< FMLA */
5719 kArmv8VecInstrFpOp_Fmls = RT_BIT_32(23) | UINT32_C(0xc800) /**< FMLS */
5720} ARMV8INSTRVECFPOP;
5721
5722/**
5723 * A64: Encodes a 3 operand floating point operation (vector, register).
5724 *
5725 * @returns The encoded instruction.
5726 * @param enmOp The operation to perform.
5727 * @param enmSz The size to operate on.
5728 * @param iVecRegDst The vector register to put the result into.
5729 * @param iVecRegSrc1 The first vector source register.
5730 * @param iVecRegSrc2 The second vector source register.
5731 */
5732DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrFp3Op(ARMV8INSTRVECFPOP enmOp, ARMV8INSTRVECFPSZ enmSz, uint32_t iVecRegDst,
5733 uint32_t iVecRegSrc1, uint32_t iVecRegSrc2)
5734{
5735 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5736
5737 return UINT32_C(0x0e200400)
5738 | ((uint32_t)enmOp)
5739 | ((uint32_t)enmSz)
5740 | (iVecRegSrc2 << 16)
5741 | (iVecRegSrc1 << 5)
5742 | iVecRegDst;
5743}
5744
5745
5746/** @} */
5747
5748#endif /* !dtrace && __cplusplus */
5749
5750/** @} */
5751
5752#endif /* !IPRT_INCLUDED_armv8_h */
5753
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