armv8.h@ 99380

Last change on this file since 99380 was 99380, checked in by vboxsync, 20 months ago
include/iprt/armv8.h: Fix retrieving the CRm value from the ESR_EL2.ISS field for the ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN exception class, bugref:10385
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1	/** @file
2	* IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef IPRT_INCLUDED_armv8_h
37	#define IPRT_INCLUDED_armv8_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/types.h>
44	# include <iprt/assert.h>
45	#else
46	# pragma D depends_on library vbox-types.d
47	#endif
48
49	/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
50	* @ingroup grp_rt
51	* @{
52	*/
53
54	/** @name The AArch64 register encoding.
55	* @{ */
56	#define ARMV8_AARCH64_REG_X0 0
57	#define ARMV8_AARCH64_REG_W0 ARMV8_AARCH64_REG_X0
58	#define ARMV8_AARCH64_REG_X1 1
59	#define ARMV8_AARCH64_REG_W1 ARMV8_AARCH64_REG_X1
60	#define ARMV8_AARCH64_REG_X2 2
61	#define ARMV8_AARCH64_REG_W2 ARMV8_AARCH64_REG_X2
62	#define ARMV8_AARCH64_REG_X3 3
63	#define ARMV8_AARCH64_REG_W3 ARMV8_AARCH64_REG_X3
64	#define ARMV8_AARCH64_REG_X4 4
65	#define ARMV8_AARCH64_REG_W4 ARMV8_AARCH64_REG_X4
66	#define ARMV8_AARCH64_REG_X5 5
67	#define ARMV8_AARCH64_REG_W5 ARMV8_AARCH64_REG_X5
68	#define ARMV8_AARCH64_REG_X6 6
69	#define ARMV8_AARCH64_REG_W6 ARMV8_AARCH64_REG_X6
70	#define ARMV8_AARCH64_REG_X7 7
71	#define ARMV8_AARCH64_REG_W7 ARMV8_AARCH64_REG_X7
72	#define ARMV8_AARCH64_REG_X8 8
73	#define ARMV8_AARCH64_REG_W8 ARMV8_AARCH64_REG_X8
74	#define ARMV8_AARCH64_REG_X9 9
75	#define ARMV8_AARCH64_REG_W9 ARMV8_AARCH64_REG_X9
76	#define ARMV8_AARCH64_REG_X10 10
77	#define ARMV8_AARCH64_REG_W10 ARMV8_AARCH64_REG_X10
78	#define ARMV8_AARCH64_REG_X11 11
79	#define ARMV8_AARCH64_REG_W11 ARMV8_AARCH64_REG_X11
80	#define ARMV8_AARCH64_REG_X12 12
81	#define ARMV8_AARCH64_REG_W12 ARMV8_AARCH64_REG_X12
82	#define ARMV8_AARCH64_REG_X13 13
83	#define ARMV8_AARCH64_REG_W13 ARMV8_AARCH64_REG_X13
84	#define ARMV8_AARCH64_REG_X14 14
85	#define ARMV8_AARCH64_REG_W14 ARMV8_AARCH64_REG_X14
86	#define ARMV8_AARCH64_REG_X15 15
87	#define ARMV8_AARCH64_REG_W15 ARMV8_AARCH64_REG_X15
88	#define ARMV8_AARCH64_REG_X16 16
89	#define ARMV8_AARCH64_REG_W16 ARMV8_AARCH64_REG_X16
90	#define ARMV8_AARCH64_REG_X17 17
91	#define ARMV8_AARCH64_REG_W17 ARMV8_AARCH64_REG_X17
92	#define ARMV8_AARCH64_REG_X18 18
93	#define ARMV8_AARCH64_REG_W18 ARMV8_AARCH64_REG_X18
94	#define ARMV8_AARCH64_REG_X19 19
95	#define ARMV8_AARCH64_REG_W19 ARMV8_AARCH64_REG_X19
96	#define ARMV8_AARCH64_REG_X20 20
97	#define ARMV8_AARCH64_REG_W20 ARMV8_AARCH64_REG_X20
98	#define ARMV8_AARCH64_REG_X21 21
99	#define ARMV8_AARCH64_REG_W21 ARMV8_AARCH64_REG_X21
100	#define ARMV8_AARCH64_REG_X22 22
101	#define ARMV8_AARCH64_REG_W22 ARMV8_AARCH64_REG_X22
102	#define ARMV8_AARCH64_REG_X23 23
103	#define ARMV8_AARCH64_REG_W23 ARMV8_AARCH64_REG_X23
104	#define ARMV8_AARCH64_REG_X24 24
105	#define ARMV8_AARCH64_REG_W24 ARMV8_AARCH64_REG_X24
106	#define ARMV8_AARCH64_REG_X25 25
107	#define ARMV8_AARCH64_REG_W25 ARMV8_AARCH64_REG_X25
108	#define ARMV8_AARCH64_REG_X26 26
109	#define ARMV8_AARCH64_REG_W26 ARMV8_AARCH64_REG_X26
110	#define ARMV8_AARCH64_REG_X27 27
111	#define ARMV8_AARCH64_REG_W27 ARMV8_AARCH64_REG_X27
112	#define ARMV8_AARCH64_REG_X28 28
113	#define ARMV8_AARCH64_REG_W28 ARMV8_AARCH64_REG_X28
114	#define ARMV8_AARCH64_REG_X29 29
115	#define ARMV8_AARCH64_REG_W29 ARMV8_AARCH64_REG_X29
116	#define ARMV8_AARCH64_REG_X30 30
117	#define ARMV8_AARCH64_REG_W30 ARMV8_AARCH64_REG_X30
118	/** The zero register. */
119	#define ARMV8_AARCH64_REG_ZR 31
120	/** @} */
121
122
123	/** @name System register encoding.
124	* @{
125	*/
126	/** Mask for the op0 part of an MSR/MRS instruction */
127	#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) \| RT_BIT_32(20))
128	/** Shift for the op0 part of an MSR/MRS instruction */
129	#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
130	/** Returns the op0 part of the given MRS/MSR instruction. */
131	#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
132	/** Mask for the op1 part of an MSR/MRS instruction */
133	#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18))
134	/** Shift for the op1 part of an MSR/MRS instruction */
135	#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
136	/** Returns the op1 part of the given MRS/MSR instruction. */
137	#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
138	/** Mask for the CRn part of an MSR/MRS instruction */
139	#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \
140	\| RT_BIT_32(15) )
141	/** Shift for the CRn part of an MSR/MRS instruction */
142	#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
143	/** Returns the CRn part of the given MRS/MSR instruction. */
144	#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
145	/** Mask for the CRm part of an MSR/MRS instruction */
146	#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \
147	\| RT_BIT_32(11) )
148	/** Shift for the CRm part of an MSR/MRS instruction */
149	#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
150	/** Returns the CRn part of the given MRS/MSR instruction. */
151	#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
152	/** Mask for the op2 part of an MSR/MRS instruction */
153	#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7))
154	/** Shift for the op2 part of an MSR/MRS instruction */
155	#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
156	/** Returns the op2 part of the given MRS/MSR instruction. */
157	#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
158	/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
159	#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK \| ARMV8_AARCH64_SYSREG_OP1_MASK \
160	\| ARMV8_AARCH64_SYSREG_CRN_MASK \| ARMV8_AARCH64_SYSREG_CRN_MASK \
161	\| ARMV8_AARCH64_SYSREG_OP2_MASK)
162
163	/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
164	* IPRT specific and not part of the ARMv8 specification. */
165	#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
166	UINT16_C( (((a_Op1) & 0x3) << 15) \
167	\| (((a_Op1) & 0x7) << 12) \
168	\| (((a_CRn) & 0xf) << 7) \
169	\| (((a_CRm) & 0xf) << 3) \
170	\| ((a_Op2) & 0x7))
171	/** Returns the internal system register ID from the given MRS/MSR instruction. */
172	#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
173	ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
174	ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
175	ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
176	ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
177	ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
178	/** Encodes the given system register ID in the given MSR/MRS instruction. */
179	#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
180	((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) \| (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
181	/** @} */
182
183
184	/** @name System register IDs.
185	* @{ */
186	/** MIDR_EL1 register - RO. */
187	#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
188	/** MIPDR_EL1 register - RO. */
189	#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
190	/** REVIDR_EL1 register - RO. */
191	#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
192	/** ID_PFR0_EL1 register - RO. */
193	#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
194	/** ID_PFR1_EL1 register - RO. */
195	#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
196	/** ID_DFR0_EL1 register - RO. */
197	#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
198	/** ID_AFR0_EL1 register - RO. */
199	#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
200	/** ID_MMFR0_EL1 register - RO. */
201	#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
202	/** ID_MMFR1_EL1 register - RO. */
203	#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
204	/** ID_MMFR2_EL1 register - RO. */
205	#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
206	/** ID_MMFR3_EL1 register - RO. */
207	#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
208
209	/** ID_ISAR0_EL1 register - RO. */
210	#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
211	/** ID_ISAR1_EL1 register - RO. */
212	#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
213	/** ID_ISAR2_EL1 register - RO. */
214	#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
215	/** ID_ISAR3_EL1 register - RO. */
216	#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
217	/** ID_ISAR4_EL1 register - RO. */
218	#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
219	/** ID_ISAR5_EL1 register - RO. */
220	#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
221	/** ID_MMFR4_EL1 register - RO. */
222	#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
223	/** ID_ISAR6_EL1 register - RO. */
224	#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
225
226	/** MVFR0_EL1 register - RO. */
227	#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
228	/** MVFR1_EL1 register - RO. */
229	#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
230	/** MVFR2_EL1 register - RO. */
231	#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
232	/** ID_PFR2_EL1 register - RO. */
233	#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
234	/** ID_DFR1_EL1 register - RO. */
235	#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
236	/** ID_MMFR5_EL1 register - RO. */
237	#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
238
239	/** ID_AA64PFR0_EL1 register - RO. */
240	#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
241	/** ID_AA64PFR0_EL1 register - RO. */
242	#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
243	/** ID_AA64ZFR0_EL1 register - RO. */
244	#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
245	/** ID_AA64SMFR0_EL1 register - RO. */
246	#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
247
248	/** ID_AA64DFR0_EL1 register - RO. */
249	#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
250	/** ID_AA64DFR0_EL1 register - RO. */
251	#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
252	/** ID_AA64AFR0_EL1 register - RO. */
253	#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
254	/** ID_AA64AFR1_EL1 register - RO. */
255	#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
256
257	/** ID_AA64ISAR0_EL1 register - RO. */
258	#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
259	/** ID_AA64ISAR1_EL1 register - RO. */
260	#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
261	/** ID_AA64ISAR2_EL1 register - RO. */
262	#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
263
264	/** ID_AA64MMFR0_EL1 register - RO. */
265	#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
266	/** ID_AA64MMFR1_EL1 register - RO. */
267	#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
268	/** ID_AA64MMFR2_EL1 register - RO. */
269	#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
270
271	/** SCTRL_EL1 register - RW. */
272	#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
273	/** ACTRL_EL1 register - RW. */
274	#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
275	/** CPACR_EL1 register - RW. */
276	#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
277	/** RGSR_EL1 register - RW. */
278	#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
279	/** GCR_EL1 register - RW. */
280	#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
281
282	/** ZCR_EL1 register - RW. */
283	#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
284	/** TRFCR_EL1 register - RW. */
285	#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
286	/** SMPRI_EL1 register - RW. */
287	#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
288	/** SMCR_EL1 register - RW. */
289	#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
290
291	/** TTBR0_EL1 register - RW. */
292	#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
293	/** TTBR1_EL1 register - RW. */
294	#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
295	/** TCR_EL1 register - RW. */
296	#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
297
298	/** @todo APIA,APIB,APDA,APDB,APGA registers. */
299
300	/** SPSR_EL1 register - RW. */
301	#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
302	/** ELR_EL1 register - RW. */
303	#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
304
305	/** SP_EL0 register - RW. */
306	#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
307
308	/** PSTATE.SPSel value. */
309	#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
310	/** PSTATE.CurrentEL value. */
311	#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
312	/** PSTATE.PAN value. */
313	#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
314	/** PSTATE.UAO value. */
315	#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
316
317	/** PSTATE.ALLINT value. */
318	#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
319
320
321	/** AFSR0_EL1 register - RW. */
322	#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
323	/** AFSR1_EL1 register - RW. */
324	#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
325
326	/** ESR_EL1 register - RW. */
327	#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
328
329	/** ERRIDR_EL1 register - RO. */
330	#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
331	/** ERRSELR_EL1 register - RW. */
332	#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
333
334	/** @} */
335
336	/** @} */
337
338
339	/**
340	* SPSR_EL2 (according to chapter C5.2.19)
341	*/
342	typedef union ARMV8SPSREL2
343	{
344	/** The plain unsigned view. */
345	uint64_t u;
346	/** The 8-bit view. */
347	uint8_t au8[8];
348	/** The 16-bit view. */
349	uint16_t au16[4];
350	/** The 32-bit view. */
351	uint32_t au32[2];
352	/** The 64-bit view. */
353	uint64_t u64;
354	} ARMV8SPSREL2;
355	/** Pointer to SPSR_EL2. */
356	typedef ARMV8SPSREL2 *PARMV8SPSREL2;
357	/** Pointer to const SPSR_EL2. */
358	typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
359
360
361	/** @name SPSR_EL2 (When exception is taken from AArch64 state)
362	* @{
363	*/
364	/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
365	#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
366	#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
367	/** Bit 0 - SP - Selected stack pointer. */
368	#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
369	#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
370	/** Bit 1 - Reserved (read as zero). */
371	#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
372	/** Bit 2 - 3 - EL - Exception level. */
373	#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) \| RT_BIT_64(3))
374	#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
375	#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
376	#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
377	/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
378	#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
379	#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
380	/** Bit 5 - Reserved (read as zero). */
381	#define ARMV8_SPSR_EL2_AARCH64_RSVD_5 RT_BIT_64(5)
382	/** Bit 6 - I - FIQ interrupt mask. */
383	#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
384	#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
385	/** Bit 7 - I - IRQ interrupt mask. */
386	#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
387	#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
388	/** Bit 8 - A - SError interrupt mask. */
389	#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
390	#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
391	/** Bit 9 - D - Debug Exception mask. */
392	#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
393	#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
394	/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
395	#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) \| RT_BIT_64(11))
396	#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
397	#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
398	/** Bit 12 - SSBS - Speculative Store Bypass. */
399	#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
400	#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
401	/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
402	#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
403	#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
404	/** Bit 14 - 19 - Reserved (read as zero). */
405	#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) \| RT_BIT_64(15) \| RT_BIT_64(16) \
406	\| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
407	/** Bit 20 - IL - Illegal Execution State flag. */
408	#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
409	#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
410	/** Bit 21 - SS - Software Step flag. */
411	#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
412	#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
413	/** Bit 22 - PAN - Privileged Access Never flag. */
414	#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
415	#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
416	/** Bit 23 - UAO - User Access Override flag. */
417	#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
418	#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
419	/** Bit 24 - DIT - Data Independent Timing flag. */
420	#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
421	#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
422	/** Bit 25 - TCO - Tag Check Override flag. */
423	#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
424	#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
425	/** Bit 26 - 27 - Reserved (read as zero). */
426	#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) \| RT_BIT_64(27))
427	/** Bit 28 - V - Overflow condition flag. */
428	#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
429	#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
430	/** Bit 29 - C - Carry condition flag. */
431	#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
432	#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
433	/** Bit 30 - Z - Zero condition flag. */
434	#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
435	#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
436	/** Bit 31 - N - Negative condition flag. */
437	#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
438	#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
439	/** Bit 32 - 63 - Reserved (read as zero). */
440	#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
441	/** Checks whether the given SPSR value contains a AARCH64 execution state. */
442	#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
443	/** @} */
444
445	/** @name Aarch64 Exception levels
446	* @{ */
447	/** Exception Level 0 - User mode. */
448	#define ARMV8_AARCH64_EL_0 0
449	/** Exception Level 1 - Supervisor mode. */
450	#define ARMV8_AARCH64_EL_1 1
451	/** Exception Level 2 - Hypervisor mode. */
452	#define ARMV8_AARCH64_EL_2 2
453	/** @} */
454
455
456	/** @name ESR_EL2 (Exception Syndrome Register, EL2)
457	* @{
458	*/
459	/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
460	#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
461	#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
462	/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
463	#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
464	#define ARMV8_ESR_EL2_IL_BIT 25
465	#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
466	#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
467	/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
468	#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) \| RT_BIT_64(27) \| RT_BIT_64(28) \
469	\| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
470	#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
471	/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
472	#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \
473	\| RT_BIT_64(35) \| RT_BIT_64(36))
474	#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
475	/+ @} /
476
477
478	/** @name ESR_EL2 Exception Classes (EC)
479	* @{ */
480	/** Unknown exception reason. */
481	#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
482	/** Trapped WF* instruction. */
483	#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
484	/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
485	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
486	/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
487	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
488	/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
489	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
490	/** AArch32 - Trapped LDC or STC access. */
491	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
492	/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
493	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
494	/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
495	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
496	/** AArch32 - Trapped pointer authentication instruction. */
497	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
498	/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
499	#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
500	/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
501	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
502	/** FEAT_BTI - Branch Target Exception. */
503	#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
504	/** Illegal Execution State. */
505	#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
506	/** AArch32 - SVC instruction execution. */
507	#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
508	/** AArch32 - HVC instruction execution. */
509	#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
510	/** AArch32 - SMC instruction execution. */
511	#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
512	/** AArch64 - SVC instruction execution. */
513	#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
514	/** AArch64 - HVC instruction execution. */
515	#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
516	/** AArch64 - SMC instruction execution. */
517	#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
518	/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
519	#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
520	/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
521	#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
522	/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
523	#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
524	/** FEAT_TME - Exception from TSTART instruction. */
525	#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
526	/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
527	#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
528	/** FEAT_SME - Access to SME functionality trapped. */
529	#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
530	/** FEAT_RME - Exception from Granule Protection Check. */
531	#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
532	/** Instruction Abort from a lower Exception level. */
533	#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
534	/** Instruction Abort from the same Exception level. */
535	#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
536	/** PC alignment fault exception. */
537	#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
538	/** Data Abort from a lower Exception level. */
539	#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
540	/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
541	#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
542	/** SP alignment fault exception. */
543	#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
544	/** FEAT_MOPS - Memory Operation Exception. */
545	#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
546	/** AArch32 - Trapped floating point exception. */
547	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
548	/** AArch64 - Trapped floating point exception. */
549	#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
550	/** SError interrupt. */
551	#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
552	/** Breakpoint Exception from a lower Exception level. */
553	#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
554	/** Breakpoint Exception from the same Exception level. */
555	#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
556	/** Software Step Exception from a lower Exception level. */
557	#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
558	/** Software Step Exception from the same Exception level. */
559	#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
560	/** Watchpoint Exception from a lower Exception level. */
561	#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
562	/** Watchpoint Exception from the same Exception level. */
563	#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
564	/** AArch32 - BKPT instruction execution. */
565	#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
566	/** AArch32 - Vector Catch exception. */
567	#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
568	/** AArch64 - BRK instruction execution. */
569	#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
570	/** @} */
571
572
573	/** @name ISS encoding for Data Abort exceptions.
574	* @{ */
575	/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
576	#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) \| RT_BIT_32(1) \| RT_BIT_32(2) \
577	\| RT_BIT_32(3) \| RT_BIT_32(4) \| RT_BIT_32(5))
578	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
579	/** Bit 6 - WnR - Write not Read. */
580	#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
581	#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
582	/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
583	#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
584	#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
585	/** Bit 8 - CM - Cache maintenance instruction. */
586	#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
587	#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
588	/** Bit 9 - EA - External abort type. */
589	#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
590	#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
591	/** Bit 10 - FnV - FAR not Valid. */
592	#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
593	#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
594	/** Bit 11 - 12 - LST - Load/Store Type. */
595	#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) \| RT_BIT_32(12))
596	#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
597	/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
598	#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
599	#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
600	/** Bit 14 - AR - Acquire/Release semantics. */
601	#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
602	#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
603	/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
604	#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
605	#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
606	/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
607	#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18) \
608	\| RT_BIT_32(19) \| RT_BIT_32(20))
609	#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
610	/** Bit 21 - SSE - Syndrome Sign Extend. */
611	#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
612	#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
613	/** Bit 22 - 23 - SAS - Syndrome Access Size. */
614	#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) \| RT_BIT_32(23))
615	#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
616	/** Bit 24 - ISV - Instruction Syndrome Valid. */
617	#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
618	#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
619
620
621	/** @name Data Fault Status Code (DFSC).
622	* @{ */
623	/** Address size fault, level 0 of translation or translation table base register. */
624	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
625	/** Address size fault, level 1. */
626	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
627	/** Address size fault, level 2. */
628	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
629	/** Address size fault, level 3. */
630	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
631	/** Translation fault, level 0. */
632	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
633	/** Translation fault, level 1. */
634	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
635	/** Translation fault, level 2. */
636	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
637	/** Translation fault, level 3. */
638	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
639	/** FEAT_LPA2 - Access flag fault, level 0. */
640	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
641	/** Access flag fault, level 1. */
642	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
643	/** Access flag fault, level 2. */
644	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
645	/** Access flag fault, level 3. */
646	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
647	/** FEAT_LPA2 - Permission fault, level 0. */
648	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
649	/** Permission fault, level 1. */
650	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
651	/** Permission fault, level 2. */
652	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
653	/** Permission fault, level 3. */
654	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
655	/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
656	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
657	/** FEAT_MTE2 - Synchronous Tag Check Fault. */
658	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
659	/** @todo Do the rest (lazy developer). */
660	/** @} */
661
662
663	/** @name SAS encoding. */
664	/** Byte access. */
665	#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
666	/** Halfword access (uint16_t). */
667	#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
668	/** Word access (uint32_t). */
669	#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
670	/** Doubleword access (uint64_t). */
671	#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
672	/** @} */
673
674	/** @} */
675
676
677	/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
678	* @{ */
679	/** Bit 0 - Direction flag. */
680	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
681	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
682	/** Bit 1 - 4 - CRm value from the instruction. */
683	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) \| RT_BIT_32(2) \| RT_BIT_32(3) \
684	\| RT_BIT_32(4))
685	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
686	/** Bit 5 - 9 - Rt value from the instruction. */
687	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7) \
688	\| RT_BIT_32(8) \| RT_BIT_32(9))
689	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
690	/** Bit 10 - 13 - CRn value from the instruction. */
691	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \
692	\| RT_BIT_32(13))
693	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
694	/** Bit 14 - 16 - Op2 value from the instruction. */
695	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(16))
696	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
697	/** Bit 17 - 19 - Op2 value from the instruction. */
698	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) \| RT_BIT_32(18) \| RT_BIT_32(19))
699	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
700	/** Bit 20 - 21 - Op0 value from the instruction. */
701	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) \| RT_BIT_32(21))
702	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
703	/** Bit 22 - 24 - Reserved. */
704	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24))
705	/** @} */
706
707	/** @} */
708
709	#endif /* !IPRT_INCLUDED_armv8_h */
710

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source: vbox/trunk/include/iprt/armv8.h@ 99380

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