| 1 | /** @file
|
|---|
| 2 | * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
|
|---|
| 3 | */
|
|---|
| 4 |
|
|---|
| 5 | /*
|
|---|
| 6 | * Copyright (C) 2023 Oracle and/or its affiliates.
|
|---|
| 7 | *
|
|---|
| 8 | * This file is part of VirtualBox base platform packages, as
|
|---|
| 9 | * available from https://www.virtualbox.org.
|
|---|
| 10 | *
|
|---|
| 11 | * This program is free software; you can redistribute it and/or
|
|---|
| 12 | * modify it under the terms of the GNU General Public License
|
|---|
| 13 | * as published by the Free Software Foundation, in version 3 of the
|
|---|
| 14 | * License.
|
|---|
| 15 | *
|
|---|
| 16 | * This program is distributed in the hope that it will be useful, but
|
|---|
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of
|
|---|
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|---|
| 19 | * General Public License for more details.
|
|---|
| 20 | *
|
|---|
| 21 | * You should have received a copy of the GNU General Public License
|
|---|
| 22 | * along with this program; if not, see <https://www.gnu.org/licenses>.
|
|---|
| 23 | *
|
|---|
| 24 | * The contents of this file may alternatively be used under the terms
|
|---|
| 25 | * of the Common Development and Distribution License Version 1.0
|
|---|
| 26 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
|
|---|
| 27 | * in the VirtualBox distribution, in which case the provisions of the
|
|---|
| 28 | * CDDL are applicable instead of those of the GPL.
|
|---|
| 29 | *
|
|---|
| 30 | * You may elect to license modified versions of this file under the
|
|---|
| 31 | * terms and conditions of either the GPL or the CDDL or both.
|
|---|
| 32 | *
|
|---|
| 33 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
|
|---|
| 34 | */
|
|---|
| 35 |
|
|---|
| 36 | #ifndef IPRT_INCLUDED_armv8_h
|
|---|
| 37 | #define IPRT_INCLUDED_armv8_h
|
|---|
| 38 | #ifndef RT_WITHOUT_PRAGMA_ONCE
|
|---|
| 39 | # pragma once
|
|---|
| 40 | #endif
|
|---|
| 41 |
|
|---|
| 42 | #ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 43 | # include <iprt/types.h>
|
|---|
| 44 | # include <iprt/assert.h>
|
|---|
| 45 | #else
|
|---|
| 46 | # pragma D depends_on library vbox-types.d
|
|---|
| 47 | #endif
|
|---|
| 48 |
|
|---|
| 49 | /** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
|
|---|
| 50 | * @ingroup grp_rt
|
|---|
| 51 | * @{
|
|---|
| 52 | */
|
|---|
| 53 |
|
|---|
| 54 | /** @name The AArch64 register encoding.
|
|---|
| 55 | * @{ */
|
|---|
| 56 | #define ARMV8_AARCH64_REG_X0 0
|
|---|
| 57 | #define ARMV8_AARCH64_REG_W0 ARMV8_AARCH64_REG_X0
|
|---|
| 58 | #define ARMV8_AARCH64_REG_X1 1
|
|---|
| 59 | #define ARMV8_AARCH64_REG_W1 ARMV8_AARCH64_REG_X1
|
|---|
| 60 | #define ARMV8_AARCH64_REG_X2 2
|
|---|
| 61 | #define ARMV8_AARCH64_REG_W2 ARMV8_AARCH64_REG_X2
|
|---|
| 62 | #define ARMV8_AARCH64_REG_X3 3
|
|---|
| 63 | #define ARMV8_AARCH64_REG_W3 ARMV8_AARCH64_REG_X3
|
|---|
| 64 | #define ARMV8_AARCH64_REG_X4 4
|
|---|
| 65 | #define ARMV8_AARCH64_REG_W4 ARMV8_AARCH64_REG_X4
|
|---|
| 66 | #define ARMV8_AARCH64_REG_X5 5
|
|---|
| 67 | #define ARMV8_AARCH64_REG_W5 ARMV8_AARCH64_REG_X5
|
|---|
| 68 | #define ARMV8_AARCH64_REG_X6 6
|
|---|
| 69 | #define ARMV8_AARCH64_REG_W6 ARMV8_AARCH64_REG_X6
|
|---|
| 70 | #define ARMV8_AARCH64_REG_X7 7
|
|---|
| 71 | #define ARMV8_AARCH64_REG_W7 ARMV8_AARCH64_REG_X7
|
|---|
| 72 | #define ARMV8_AARCH64_REG_X8 8
|
|---|
| 73 | #define ARMV8_AARCH64_REG_W8 ARMV8_AARCH64_REG_X8
|
|---|
| 74 | #define ARMV8_AARCH64_REG_X9 9
|
|---|
| 75 | #define ARMV8_AARCH64_REG_W9 ARMV8_AARCH64_REG_X9
|
|---|
| 76 | #define ARMV8_AARCH64_REG_X10 10
|
|---|
| 77 | #define ARMV8_AARCH64_REG_W10 ARMV8_AARCH64_REG_X10
|
|---|
| 78 | #define ARMV8_AARCH64_REG_X11 11
|
|---|
| 79 | #define ARMV8_AARCH64_REG_W11 ARMV8_AARCH64_REG_X11
|
|---|
| 80 | #define ARMV8_AARCH64_REG_X12 12
|
|---|
| 81 | #define ARMV8_AARCH64_REG_W12 ARMV8_AARCH64_REG_X12
|
|---|
| 82 | #define ARMV8_AARCH64_REG_X13 13
|
|---|
| 83 | #define ARMV8_AARCH64_REG_W13 ARMV8_AARCH64_REG_X13
|
|---|
| 84 | #define ARMV8_AARCH64_REG_X14 14
|
|---|
| 85 | #define ARMV8_AARCH64_REG_W14 ARMV8_AARCH64_REG_X14
|
|---|
| 86 | #define ARMV8_AARCH64_REG_X15 15
|
|---|
| 87 | #define ARMV8_AARCH64_REG_W15 ARMV8_AARCH64_REG_X15
|
|---|
| 88 | #define ARMV8_AARCH64_REG_X16 16
|
|---|
| 89 | #define ARMV8_AARCH64_REG_W16 ARMV8_AARCH64_REG_X16
|
|---|
| 90 | #define ARMV8_AARCH64_REG_X17 17
|
|---|
| 91 | #define ARMV8_AARCH64_REG_W17 ARMV8_AARCH64_REG_X17
|
|---|
| 92 | #define ARMV8_AARCH64_REG_X18 18
|
|---|
| 93 | #define ARMV8_AARCH64_REG_W18 ARMV8_AARCH64_REG_X18
|
|---|
| 94 | #define ARMV8_AARCH64_REG_X19 19
|
|---|
| 95 | #define ARMV8_AARCH64_REG_W19 ARMV8_AARCH64_REG_X19
|
|---|
| 96 | #define ARMV8_AARCH64_REG_X20 20
|
|---|
| 97 | #define ARMV8_AARCH64_REG_W20 ARMV8_AARCH64_REG_X20
|
|---|
| 98 | #define ARMV8_AARCH64_REG_X21 21
|
|---|
| 99 | #define ARMV8_AARCH64_REG_W21 ARMV8_AARCH64_REG_X21
|
|---|
| 100 | #define ARMV8_AARCH64_REG_X22 22
|
|---|
| 101 | #define ARMV8_AARCH64_REG_W22 ARMV8_AARCH64_REG_X22
|
|---|
| 102 | #define ARMV8_AARCH64_REG_X23 23
|
|---|
| 103 | #define ARMV8_AARCH64_REG_W23 ARMV8_AARCH64_REG_X23
|
|---|
| 104 | #define ARMV8_AARCH64_REG_X24 24
|
|---|
| 105 | #define ARMV8_AARCH64_REG_W24 ARMV8_AARCH64_REG_X24
|
|---|
| 106 | #define ARMV8_AARCH64_REG_X25 25
|
|---|
| 107 | #define ARMV8_AARCH64_REG_W25 ARMV8_AARCH64_REG_X25
|
|---|
| 108 | #define ARMV8_AARCH64_REG_X26 26
|
|---|
| 109 | #define ARMV8_AARCH64_REG_W26 ARMV8_AARCH64_REG_X26
|
|---|
| 110 | #define ARMV8_AARCH64_REG_X27 27
|
|---|
| 111 | #define ARMV8_AARCH64_REG_W27 ARMV8_AARCH64_REG_X27
|
|---|
| 112 | #define ARMV8_AARCH64_REG_X28 28
|
|---|
| 113 | #define ARMV8_AARCH64_REG_W28 ARMV8_AARCH64_REG_X28
|
|---|
| 114 | #define ARMV8_AARCH64_REG_X29 29
|
|---|
| 115 | #define ARMV8_AARCH64_REG_W29 ARMV8_AARCH64_REG_X29
|
|---|
| 116 | #define ARMV8_AARCH64_REG_X30 30
|
|---|
| 117 | #define ARMV8_AARCH64_REG_W30 ARMV8_AARCH64_REG_X30
|
|---|
| 118 | /** The zero register. */
|
|---|
| 119 | #define ARMV8_AARCH64_REG_ZR 31
|
|---|
| 120 | /** @} */
|
|---|
| 121 |
|
|---|
| 122 |
|
|---|
| 123 | /** @name System register encoding.
|
|---|
| 124 | * @{
|
|---|
| 125 | */
|
|---|
| 126 | /** Mask for the op0 part of an MSR/MRS instruction */
|
|---|
| 127 | #define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
|
|---|
| 128 | /** Shift for the op0 part of an MSR/MRS instruction */
|
|---|
| 129 | #define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
|
|---|
| 130 | /** Returns the op0 part of the given MRS/MSR instruction. */
|
|---|
| 131 | #define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
|
|---|
| 132 | /** Mask for the op1 part of an MSR/MRS instruction */
|
|---|
| 133 | #define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
|
|---|
| 134 | /** Shift for the op1 part of an MSR/MRS instruction */
|
|---|
| 135 | #define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
|
|---|
| 136 | /** Returns the op1 part of the given MRS/MSR instruction. */
|
|---|
| 137 | #define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
|
|---|
| 138 | /** Mask for the CRn part of an MSR/MRS instruction */
|
|---|
| 139 | #define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
|
|---|
| 140 | | RT_BIT_32(15) )
|
|---|
| 141 | /** Shift for the CRn part of an MSR/MRS instruction */
|
|---|
| 142 | #define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
|
|---|
| 143 | /** Returns the CRn part of the given MRS/MSR instruction. */
|
|---|
| 144 | #define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
|
|---|
| 145 | /** Mask for the CRm part of an MSR/MRS instruction */
|
|---|
| 146 | #define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
|
|---|
| 147 | | RT_BIT_32(11) )
|
|---|
| 148 | /** Shift for the CRm part of an MSR/MRS instruction */
|
|---|
| 149 | #define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
|
|---|
| 150 | /** Returns the CRn part of the given MRS/MSR instruction. */
|
|---|
| 151 | #define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
|
|---|
| 152 | /** Mask for the op2 part of an MSR/MRS instruction */
|
|---|
| 153 | #define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
|
|---|
| 154 | /** Shift for the op2 part of an MSR/MRS instruction */
|
|---|
| 155 | #define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
|
|---|
| 156 | /** Returns the op2 part of the given MRS/MSR instruction. */
|
|---|
| 157 | #define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
|
|---|
| 158 | /** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
|
|---|
| 159 | #define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
|
|---|
| 160 | | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
|
|---|
| 161 | | ARMV8_AARCH64_SYSREG_OP2_MASK)
|
|---|
| 162 |
|
|---|
| 163 | /** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
|
|---|
| 164 | * IPRT specific and not part of the ARMv8 specification. */
|
|---|
| 165 | #define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
|
|---|
| 166 | UINT16_C( (((a_Op1) & 0x3) << 15) \
|
|---|
| 167 | | (((a_Op1) & 0x7) << 12) \
|
|---|
| 168 | | (((a_CRn) & 0xf) << 7) \
|
|---|
| 169 | | (((a_CRm) & 0xf) << 3) \
|
|---|
| 170 | | ((a_Op2) & 0x7))
|
|---|
| 171 | /** Returns the internal system register ID from the given MRS/MSR instruction. */
|
|---|
| 172 | #define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
|
|---|
| 173 | ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
|
|---|
| 174 | ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
|
|---|
| 175 | ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
|
|---|
| 176 | ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
|
|---|
| 177 | ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
|
|---|
| 178 | /** Encodes the given system register ID in the given MSR/MRS instruction. */
|
|---|
| 179 | #define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
|
|---|
| 180 | ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
|
|---|
| 181 | /** @} */
|
|---|
| 182 |
|
|---|
| 183 |
|
|---|
| 184 | /** @name System register IDs.
|
|---|
| 185 | * @{ */
|
|---|
| 186 | /** MIDR_EL1 register - RO. */
|
|---|
| 187 | #define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
|
|---|
| 188 | /** MIPDR_EL1 register - RO. */
|
|---|
| 189 | #define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
|
|---|
| 190 | /** REVIDR_EL1 register - RO. */
|
|---|
| 191 | #define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
|
|---|
| 192 | /** ID_PFR0_EL1 register - RO. */
|
|---|
| 193 | #define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
|
|---|
| 194 | /** ID_PFR1_EL1 register - RO. */
|
|---|
| 195 | #define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
|
|---|
| 196 | /** ID_DFR0_EL1 register - RO. */
|
|---|
| 197 | #define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
|
|---|
| 198 | /** ID_AFR0_EL1 register - RO. */
|
|---|
| 199 | #define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
|
|---|
| 200 | /** ID_MMFR0_EL1 register - RO. */
|
|---|
| 201 | #define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
|
|---|
| 202 | /** ID_MMFR1_EL1 register - RO. */
|
|---|
| 203 | #define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
|
|---|
| 204 | /** ID_MMFR2_EL1 register - RO. */
|
|---|
| 205 | #define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
|
|---|
| 206 | /** ID_MMFR3_EL1 register - RO. */
|
|---|
| 207 | #define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
|
|---|
| 208 |
|
|---|
| 209 | /** ID_ISAR0_EL1 register - RO. */
|
|---|
| 210 | #define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
|
|---|
| 211 | /** ID_ISAR1_EL1 register - RO. */
|
|---|
| 212 | #define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
|
|---|
| 213 | /** ID_ISAR2_EL1 register - RO. */
|
|---|
| 214 | #define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
|
|---|
| 215 | /** ID_ISAR3_EL1 register - RO. */
|
|---|
| 216 | #define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
|
|---|
| 217 | /** ID_ISAR4_EL1 register - RO. */
|
|---|
| 218 | #define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
|
|---|
| 219 | /** ID_ISAR5_EL1 register - RO. */
|
|---|
| 220 | #define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
|
|---|
| 221 | /** ID_MMFR4_EL1 register - RO. */
|
|---|
| 222 | #define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
|
|---|
| 223 | /** ID_ISAR6_EL1 register - RO. */
|
|---|
| 224 | #define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
|
|---|
| 225 |
|
|---|
| 226 | /** MVFR0_EL1 register - RO. */
|
|---|
| 227 | #define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
|
|---|
| 228 | /** MVFR1_EL1 register - RO. */
|
|---|
| 229 | #define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
|
|---|
| 230 | /** MVFR2_EL1 register - RO. */
|
|---|
| 231 | #define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
|
|---|
| 232 | /** ID_PFR2_EL1 register - RO. */
|
|---|
| 233 | #define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
|
|---|
| 234 | /** ID_DFR1_EL1 register - RO. */
|
|---|
| 235 | #define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
|
|---|
| 236 | /** ID_MMFR5_EL1 register - RO. */
|
|---|
| 237 | #define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
|
|---|
| 238 |
|
|---|
| 239 | /** ID_AA64PFR0_EL1 register - RO. */
|
|---|
| 240 | #define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
|
|---|
| 241 | /** ID_AA64PFR0_EL1 register - RO. */
|
|---|
| 242 | #define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
|
|---|
| 243 | /** ID_AA64ZFR0_EL1 register - RO. */
|
|---|
| 244 | #define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
|
|---|
| 245 | /** ID_AA64SMFR0_EL1 register - RO. */
|
|---|
| 246 | #define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
|
|---|
| 247 |
|
|---|
| 248 | /** ID_AA64DFR0_EL1 register - RO. */
|
|---|
| 249 | #define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
|
|---|
| 250 | /** ID_AA64DFR0_EL1 register - RO. */
|
|---|
| 251 | #define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
|
|---|
| 252 | /** ID_AA64AFR0_EL1 register - RO. */
|
|---|
| 253 | #define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
|
|---|
| 254 | /** ID_AA64AFR1_EL1 register - RO. */
|
|---|
| 255 | #define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
|
|---|
| 256 |
|
|---|
| 257 | /** ID_AA64ISAR0_EL1 register - RO. */
|
|---|
| 258 | #define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
|
|---|
| 259 | /** ID_AA64ISAR1_EL1 register - RO. */
|
|---|
| 260 | #define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
|
|---|
| 261 | /** ID_AA64ISAR2_EL1 register - RO. */
|
|---|
| 262 | #define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
|
|---|
| 263 |
|
|---|
| 264 | /** ID_AA64MMFR0_EL1 register - RO. */
|
|---|
| 265 | #define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
|
|---|
| 266 | /** ID_AA64MMFR1_EL1 register - RO. */
|
|---|
| 267 | #define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
|
|---|
| 268 | /** ID_AA64MMFR2_EL1 register - RO. */
|
|---|
| 269 | #define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
|
|---|
| 270 |
|
|---|
| 271 | /** SCTRL_EL1 register - RW. */
|
|---|
| 272 | #define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
|
|---|
| 273 | /** ACTRL_EL1 register - RW. */
|
|---|
| 274 | #define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
|
|---|
| 275 | /** CPACR_EL1 register - RW. */
|
|---|
| 276 | #define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
|
|---|
| 277 | /** RGSR_EL1 register - RW. */
|
|---|
| 278 | #define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
|
|---|
| 279 | /** GCR_EL1 register - RW. */
|
|---|
| 280 | #define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
|
|---|
| 281 |
|
|---|
| 282 | /** ZCR_EL1 register - RW. */
|
|---|
| 283 | #define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
|
|---|
| 284 | /** TRFCR_EL1 register - RW. */
|
|---|
| 285 | #define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
|
|---|
| 286 | /** SMPRI_EL1 register - RW. */
|
|---|
| 287 | #define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
|
|---|
| 288 | /** SMCR_EL1 register - RW. */
|
|---|
| 289 | #define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
|
|---|
| 290 |
|
|---|
| 291 | /** TTBR0_EL1 register - RW. */
|
|---|
| 292 | #define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
|
|---|
| 293 | /** TTBR1_EL1 register - RW. */
|
|---|
| 294 | #define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
|
|---|
| 295 | /** TCR_EL1 register - RW. */
|
|---|
| 296 | #define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
|
|---|
| 297 |
|
|---|
| 298 | /** @todo APIA,APIB,APDA,APDB,APGA registers. */
|
|---|
| 299 |
|
|---|
| 300 | /** SPSR_EL1 register - RW. */
|
|---|
| 301 | #define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
|
|---|
| 302 | /** ELR_EL1 register - RW. */
|
|---|
| 303 | #define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
|
|---|
| 304 |
|
|---|
| 305 | /** SP_EL0 register - RW. */
|
|---|
| 306 | #define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
|
|---|
| 307 |
|
|---|
| 308 | /** PSTATE.SPSel value. */
|
|---|
| 309 | #define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
|
|---|
| 310 | /** PSTATE.CurrentEL value. */
|
|---|
| 311 | #define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
|
|---|
| 312 | /** PSTATE.PAN value. */
|
|---|
| 313 | #define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
|
|---|
| 314 | /** PSTATE.UAO value. */
|
|---|
| 315 | #define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
|
|---|
| 316 |
|
|---|
| 317 | /** PSTATE.ALLINT value. */
|
|---|
| 318 | #define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
|
|---|
| 319 |
|
|---|
| 320 | /** ICC_PMR_EL1 register - RW. */
|
|---|
| 321 | #define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
|
|---|
| 322 |
|
|---|
| 323 | /** AFSR0_EL1 register - RW. */
|
|---|
| 324 | #define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
|
|---|
| 325 | /** AFSR1_EL1 register - RW. */
|
|---|
| 326 | #define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
|
|---|
| 327 |
|
|---|
| 328 | /** ESR_EL1 register - RW. */
|
|---|
| 329 | #define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
|
|---|
| 330 |
|
|---|
| 331 | /** ERRIDR_EL1 register - RO. */
|
|---|
| 332 | #define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
|
|---|
| 333 | /** ERRSELR_EL1 register - RW. */
|
|---|
| 334 | #define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
|
|---|
| 335 |
|
|---|
| 336 | /** ICC_IAR0_EL1 register - RO. */
|
|---|
| 337 | #define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
|
|---|
| 338 | /** ICC_EOIR0_EL1 register - WO. */
|
|---|
| 339 | #define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
|
|---|
| 340 | /** ICC_HPPIR0_EL1 register - WO. */
|
|---|
| 341 | #define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
|
|---|
| 342 | /** ICC_BPR0_EL1 register - RW. */
|
|---|
| 343 | #define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
|
|---|
| 344 | /** ICC_AP0R0_EL1 register - RW. */
|
|---|
| 345 | #define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
|
|---|
| 346 | /** ICC_AP0R1_EL1 register - RW. */
|
|---|
| 347 | #define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
|
|---|
| 348 | /** ICC_AP0R2_EL1 register - RW. */
|
|---|
| 349 | #define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
|
|---|
| 350 | /** ICC_AP0R3_EL1 register - RW. */
|
|---|
| 351 | #define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
|
|---|
| 352 |
|
|---|
| 353 | /** ICC_AP1R0_EL1 register - RW. */
|
|---|
| 354 | #define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
|
|---|
| 355 | /** ICC_AP1R1_EL1 register - RW. */
|
|---|
| 356 | #define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
|
|---|
| 357 | /** ICC_AP1R2_EL1 register - RW. */
|
|---|
| 358 | #define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
|
|---|
| 359 | /** ICC_AP1R3_EL1 register - RW. */
|
|---|
| 360 | #define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
|
|---|
| 361 | /** ICC_NMIAR1_EL1 register - RO. */
|
|---|
| 362 | #define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
|
|---|
| 363 |
|
|---|
| 364 | /** ICC_DIR_EL1 register - WO. */
|
|---|
| 365 | #define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
|
|---|
| 366 | /** ICC_RPR_EL1 register - RO. */
|
|---|
| 367 | #define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
|
|---|
| 368 | /** ICC_SGI1R_EL1 register - WO. */
|
|---|
| 369 | #define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
|
|---|
| 370 | /** ICC_ASGI1R_EL1 register - WO. */
|
|---|
| 371 | #define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
|
|---|
| 372 | /** ICC_SGI0R_EL1 register - WO. */
|
|---|
| 373 | #define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
|
|---|
| 374 |
|
|---|
| 375 | /** ICC_IAR1_EL1 register - RO. */
|
|---|
| 376 | #define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
|
|---|
| 377 | /** ICC_EOIR1_EL1 register - WO. */
|
|---|
| 378 | #define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
|
|---|
| 379 | /** ICC_HPPIR1_EL1 register - RO. */
|
|---|
| 380 | #define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
|
|---|
| 381 | /** ICC_BPR1_EL1 register - RW. */
|
|---|
| 382 | #define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
|
|---|
| 383 | /** ICC_CTLR_EL1 register - RW. */
|
|---|
| 384 | #define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
|
|---|
| 385 | /** ICC_SRE_EL1 register - RW. */
|
|---|
| 386 | #define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
|
|---|
| 387 | /** ICC_IGRPEN0_EL1 register - RW. */
|
|---|
| 388 | #define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
|
|---|
| 389 | /** ICC_IGRPEN1_EL1 register - RW. */
|
|---|
| 390 | #define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
|
|---|
| 391 | /** @} */
|
|---|
| 392 |
|
|---|
| 393 | /** @} */
|
|---|
| 394 |
|
|---|
| 395 |
|
|---|
| 396 | /**
|
|---|
| 397 | * SPSR_EL2 (according to chapter C5.2.19)
|
|---|
| 398 | */
|
|---|
| 399 | typedef union ARMV8SPSREL2
|
|---|
| 400 | {
|
|---|
| 401 | /** The plain unsigned view. */
|
|---|
| 402 | uint64_t u;
|
|---|
| 403 | /** The 8-bit view. */
|
|---|
| 404 | uint8_t au8[8];
|
|---|
| 405 | /** The 16-bit view. */
|
|---|
| 406 | uint16_t au16[4];
|
|---|
| 407 | /** The 32-bit view. */
|
|---|
| 408 | uint32_t au32[2];
|
|---|
| 409 | /** The 64-bit view. */
|
|---|
| 410 | uint64_t u64;
|
|---|
| 411 | } ARMV8SPSREL2;
|
|---|
| 412 | /** Pointer to SPSR_EL2. */
|
|---|
| 413 | typedef ARMV8SPSREL2 *PARMV8SPSREL2;
|
|---|
| 414 | /** Pointer to const SPSR_EL2. */
|
|---|
| 415 | typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
|
|---|
| 416 |
|
|---|
| 417 |
|
|---|
| 418 | /** @name SPSR_EL2 (When exception is taken from AArch64 state)
|
|---|
| 419 | * @{
|
|---|
| 420 | */
|
|---|
| 421 | /** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
|
|---|
| 422 | #define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
|
|---|
| 423 | #define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
|
|---|
| 424 | /** Bit 0 - SP - Selected stack pointer. */
|
|---|
| 425 | #define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
|
|---|
| 426 | #define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
|
|---|
| 427 | /** Bit 1 - Reserved (read as zero). */
|
|---|
| 428 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
|
|---|
| 429 | /** Bit 2 - 3 - EL - Exception level. */
|
|---|
| 430 | #define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
|
|---|
| 431 | #define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
|
|---|
| 432 | #define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
|
|---|
| 433 | #define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
|
|---|
| 434 | /** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
|
|---|
| 435 | #define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
|
|---|
| 436 | #define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
|
|---|
| 437 | /** Bit 5 - Reserved (read as zero). */
|
|---|
| 438 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_5 RT_BIT_64(5)
|
|---|
| 439 | /** Bit 6 - I - FIQ interrupt mask. */
|
|---|
| 440 | #define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
|
|---|
| 441 | #define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
|
|---|
| 442 | /** Bit 7 - I - IRQ interrupt mask. */
|
|---|
| 443 | #define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
|
|---|
| 444 | #define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
|
|---|
| 445 | /** Bit 8 - A - SError interrupt mask. */
|
|---|
| 446 | #define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
|
|---|
| 447 | #define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
|
|---|
| 448 | /** Bit 9 - D - Debug Exception mask. */
|
|---|
| 449 | #define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
|
|---|
| 450 | #define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
|
|---|
| 451 | /** Bit 10 - 11 - BTYPE - Branch Type indicator. */
|
|---|
| 452 | #define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
|
|---|
| 453 | #define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
|
|---|
| 454 | #define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
|
|---|
| 455 | /** Bit 12 - SSBS - Speculative Store Bypass. */
|
|---|
| 456 | #define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
|
|---|
| 457 | #define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
|
|---|
| 458 | /** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
|
|---|
| 459 | #define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
|
|---|
| 460 | #define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
|
|---|
| 461 | /** Bit 14 - 19 - Reserved (read as zero). */
|
|---|
| 462 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
|
|---|
| 463 | | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
|
|---|
| 464 | /** Bit 20 - IL - Illegal Execution State flag. */
|
|---|
| 465 | #define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
|
|---|
| 466 | #define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
|
|---|
| 467 | /** Bit 21 - SS - Software Step flag. */
|
|---|
| 468 | #define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
|
|---|
| 469 | #define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
|
|---|
| 470 | /** Bit 22 - PAN - Privileged Access Never flag. */
|
|---|
| 471 | #define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
|
|---|
| 472 | #define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
|
|---|
| 473 | /** Bit 23 - UAO - User Access Override flag. */
|
|---|
| 474 | #define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
|
|---|
| 475 | #define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
|
|---|
| 476 | /** Bit 24 - DIT - Data Independent Timing flag. */
|
|---|
| 477 | #define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
|
|---|
| 478 | #define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
|
|---|
| 479 | /** Bit 25 - TCO - Tag Check Override flag. */
|
|---|
| 480 | #define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
|
|---|
| 481 | #define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
|
|---|
| 482 | /** Bit 26 - 27 - Reserved (read as zero). */
|
|---|
| 483 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
|
|---|
| 484 | /** Bit 28 - V - Overflow condition flag. */
|
|---|
| 485 | #define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
|
|---|
| 486 | #define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
|
|---|
| 487 | /** Bit 29 - C - Carry condition flag. */
|
|---|
| 488 | #define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
|
|---|
| 489 | #define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
|
|---|
| 490 | /** Bit 30 - Z - Zero condition flag. */
|
|---|
| 491 | #define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
|
|---|
| 492 | #define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
|
|---|
| 493 | /** Bit 31 - N - Negative condition flag. */
|
|---|
| 494 | #define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
|
|---|
| 495 | #define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
|
|---|
| 496 | /** Bit 32 - 63 - Reserved (read as zero). */
|
|---|
| 497 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
|
|---|
| 498 | /** Checks whether the given SPSR value contains a AARCH64 execution state. */
|
|---|
| 499 | #define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
|
|---|
| 500 | /** @} */
|
|---|
| 501 |
|
|---|
| 502 | /** @name Aarch64 Exception levels
|
|---|
| 503 | * @{ */
|
|---|
| 504 | /** Exception Level 0 - User mode. */
|
|---|
| 505 | #define ARMV8_AARCH64_EL_0 0
|
|---|
| 506 | /** Exception Level 1 - Supervisor mode. */
|
|---|
| 507 | #define ARMV8_AARCH64_EL_1 1
|
|---|
| 508 | /** Exception Level 2 - Hypervisor mode. */
|
|---|
| 509 | #define ARMV8_AARCH64_EL_2 2
|
|---|
| 510 | /** @} */
|
|---|
| 511 |
|
|---|
| 512 |
|
|---|
| 513 | /** @name ESR_EL2 (Exception Syndrome Register, EL2)
|
|---|
| 514 | * @{
|
|---|
| 515 | */
|
|---|
| 516 | /** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
|
|---|
| 517 | #define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
|
|---|
| 518 | #define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
|
|---|
| 519 | /** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
|
|---|
| 520 | #define ARMV8_ESR_EL2_IL RT_BIT_64(25)
|
|---|
| 521 | #define ARMV8_ESR_EL2_IL_BIT 25
|
|---|
| 522 | #define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
|
|---|
| 523 | #define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
|
|---|
| 524 | /** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
|
|---|
| 525 | #define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
|
|---|
| 526 | | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
|
|---|
| 527 | #define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
|
|---|
| 528 | /** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
|
|---|
| 529 | #define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
|
|---|
| 530 | | RT_BIT_64(35) | RT_BIT_64(36))
|
|---|
| 531 | #define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
|
|---|
| 532 | /*+ @} */
|
|---|
| 533 |
|
|---|
| 534 |
|
|---|
| 535 | /** @name ESR_EL2 Exception Classes (EC)
|
|---|
| 536 | * @{ */
|
|---|
| 537 | /** Unknown exception reason. */
|
|---|
| 538 | #define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
|
|---|
| 539 | /** Trapped WF* instruction. */
|
|---|
| 540 | #define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
|
|---|
| 541 | /** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
|
|---|
| 542 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
|
|---|
| 543 | /** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
|
|---|
| 544 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
|
|---|
| 545 | /** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
|
|---|
| 546 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
|
|---|
| 547 | /** AArch32 - Trapped LDC or STC access. */
|
|---|
| 548 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
|
|---|
| 549 | /** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
|
|---|
| 550 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
|
|---|
| 551 | /** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
|
|---|
| 552 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
|
|---|
| 553 | /** AArch32 - Trapped pointer authentication instruction. */
|
|---|
| 554 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
|
|---|
| 555 | /** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
|
|---|
| 556 | #define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
|
|---|
| 557 | /** AArch32 - Trapped MRRC access (coproc == 0b1110). */
|
|---|
| 558 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
|
|---|
| 559 | /** FEAT_BTI - Branch Target Exception. */
|
|---|
| 560 | #define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
|
|---|
| 561 | /** Illegal Execution State. */
|
|---|
| 562 | #define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
|
|---|
| 563 | /** AArch32 - SVC instruction execution. */
|
|---|
| 564 | #define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
|
|---|
| 565 | /** AArch32 - HVC instruction execution. */
|
|---|
| 566 | #define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
|
|---|
| 567 | /** AArch32 - SMC instruction execution. */
|
|---|
| 568 | #define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
|
|---|
| 569 | /** AArch64 - SVC instruction execution. */
|
|---|
| 570 | #define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
|
|---|
| 571 | /** AArch64 - HVC instruction execution. */
|
|---|
| 572 | #define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
|
|---|
| 573 | /** AArch64 - SMC instruction execution. */
|
|---|
| 574 | #define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
|
|---|
| 575 | /** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
|
|---|
| 576 | #define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
|
|---|
| 577 | /** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
|
|---|
| 578 | #define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
|
|---|
| 579 | /** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
|
|---|
| 580 | #define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
|
|---|
| 581 | /** FEAT_TME - Exception from TSTART instruction. */
|
|---|
| 582 | #define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
|
|---|
| 583 | /** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
|
|---|
| 584 | #define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
|
|---|
| 585 | /** FEAT_SME - Access to SME functionality trapped. */
|
|---|
| 586 | #define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
|
|---|
| 587 | /** FEAT_RME - Exception from Granule Protection Check. */
|
|---|
| 588 | #define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
|
|---|
| 589 | /** Instruction Abort from a lower Exception level. */
|
|---|
| 590 | #define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
|
|---|
| 591 | /** Instruction Abort from the same Exception level. */
|
|---|
| 592 | #define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
|
|---|
| 593 | /** PC alignment fault exception. */
|
|---|
| 594 | #define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
|
|---|
| 595 | /** Data Abort from a lower Exception level. */
|
|---|
| 596 | #define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
|
|---|
| 597 | /** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
|
|---|
| 598 | #define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
|
|---|
| 599 | /** SP alignment fault exception. */
|
|---|
| 600 | #define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
|
|---|
| 601 | /** FEAT_MOPS - Memory Operation Exception. */
|
|---|
| 602 | #define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
|
|---|
| 603 | /** AArch32 - Trapped floating point exception. */
|
|---|
| 604 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
|
|---|
| 605 | /** AArch64 - Trapped floating point exception. */
|
|---|
| 606 | #define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
|
|---|
| 607 | /** SError interrupt. */
|
|---|
| 608 | #define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
|
|---|
| 609 | /** Breakpoint Exception from a lower Exception level. */
|
|---|
| 610 | #define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
|
|---|
| 611 | /** Breakpoint Exception from the same Exception level. */
|
|---|
| 612 | #define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
|
|---|
| 613 | /** Software Step Exception from a lower Exception level. */
|
|---|
| 614 | #define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
|
|---|
| 615 | /** Software Step Exception from the same Exception level. */
|
|---|
| 616 | #define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
|
|---|
| 617 | /** Watchpoint Exception from a lower Exception level. */
|
|---|
| 618 | #define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
|
|---|
| 619 | /** Watchpoint Exception from the same Exception level. */
|
|---|
| 620 | #define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
|
|---|
| 621 | /** AArch32 - BKPT instruction execution. */
|
|---|
| 622 | #define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
|
|---|
| 623 | /** AArch32 - Vector Catch exception. */
|
|---|
| 624 | #define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
|
|---|
| 625 | /** AArch64 - BRK instruction execution. */
|
|---|
| 626 | #define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
|
|---|
| 627 | /** @} */
|
|---|
| 628 |
|
|---|
| 629 |
|
|---|
| 630 | /** @name ISS encoding for Data Abort exceptions.
|
|---|
| 631 | * @{ */
|
|---|
| 632 | /** Bit 0 - 5 - DFSC - Data Fault Status Code. */
|
|---|
| 633 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
|
|---|
| 634 | | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
|
|---|
| 635 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
|
|---|
| 636 | /** Bit 6 - WnR - Write not Read. */
|
|---|
| 637 | #define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
|
|---|
| 638 | #define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
|
|---|
| 639 | /** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
|
|---|
| 640 | #define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
|
|---|
| 641 | #define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
|
|---|
| 642 | /** Bit 8 - CM - Cache maintenance instruction. */
|
|---|
| 643 | #define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
|
|---|
| 644 | #define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
|
|---|
| 645 | /** Bit 9 - EA - External abort type. */
|
|---|
| 646 | #define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
|
|---|
| 647 | #define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
|
|---|
| 648 | /** Bit 10 - FnV - FAR not Valid. */
|
|---|
| 649 | #define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
|
|---|
| 650 | #define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
|
|---|
| 651 | /** Bit 11 - 12 - LST - Load/Store Type. */
|
|---|
| 652 | #define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
|
|---|
| 653 | #define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
|
|---|
| 654 | /** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
|
|---|
| 655 | #define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
|
|---|
| 656 | #define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
|
|---|
| 657 | /** Bit 14 - AR - Acquire/Release semantics. */
|
|---|
| 658 | #define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
|
|---|
| 659 | #define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
|
|---|
| 660 | /** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
|
|---|
| 661 | #define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
|
|---|
| 662 | #define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
|
|---|
| 663 | /** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
|
|---|
| 664 | #define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
|
|---|
| 665 | | RT_BIT_32(19) | RT_BIT_32(20))
|
|---|
| 666 | #define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
|
|---|
| 667 | /** Bit 21 - SSE - Syndrome Sign Extend. */
|
|---|
| 668 | #define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
|
|---|
| 669 | #define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
|
|---|
| 670 | /** Bit 22 - 23 - SAS - Syndrome Access Size. */
|
|---|
| 671 | #define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
|
|---|
| 672 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
|
|---|
| 673 | /** Bit 24 - ISV - Instruction Syndrome Valid. */
|
|---|
| 674 | #define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
|
|---|
| 675 | #define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
|
|---|
| 676 |
|
|---|
| 677 |
|
|---|
| 678 | /** @name Data Fault Status Code (DFSC).
|
|---|
| 679 | * @{ */
|
|---|
| 680 | /** Address size fault, level 0 of translation or translation table base register. */
|
|---|
| 681 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
|
|---|
| 682 | /** Address size fault, level 1. */
|
|---|
| 683 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
|
|---|
| 684 | /** Address size fault, level 2. */
|
|---|
| 685 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
|
|---|
| 686 | /** Address size fault, level 3. */
|
|---|
| 687 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
|
|---|
| 688 | /** Translation fault, level 0. */
|
|---|
| 689 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
|
|---|
| 690 | /** Translation fault, level 1. */
|
|---|
| 691 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
|
|---|
| 692 | /** Translation fault, level 2. */
|
|---|
| 693 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
|
|---|
| 694 | /** Translation fault, level 3. */
|
|---|
| 695 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
|
|---|
| 696 | /** FEAT_LPA2 - Access flag fault, level 0. */
|
|---|
| 697 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
|
|---|
| 698 | /** Access flag fault, level 1. */
|
|---|
| 699 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
|
|---|
| 700 | /** Access flag fault, level 2. */
|
|---|
| 701 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
|
|---|
| 702 | /** Access flag fault, level 3. */
|
|---|
| 703 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
|
|---|
| 704 | /** FEAT_LPA2 - Permission fault, level 0. */
|
|---|
| 705 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
|
|---|
| 706 | /** Permission fault, level 1. */
|
|---|
| 707 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
|
|---|
| 708 | /** Permission fault, level 2. */
|
|---|
| 709 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
|
|---|
| 710 | /** Permission fault, level 3. */
|
|---|
| 711 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
|
|---|
| 712 | /** Synchronous External abort, not a translation table walk or hardware update of translation table. */
|
|---|
| 713 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
|
|---|
| 714 | /** FEAT_MTE2 - Synchronous Tag Check Fault. */
|
|---|
| 715 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
|
|---|
| 716 | /** @todo Do the rest (lazy developer). */
|
|---|
| 717 | /** @} */
|
|---|
| 718 |
|
|---|
| 719 |
|
|---|
| 720 | /** @name SAS encoding. */
|
|---|
| 721 | /** Byte access. */
|
|---|
| 722 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
|
|---|
| 723 | /** Halfword access (uint16_t). */
|
|---|
| 724 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
|
|---|
| 725 | /** Word access (uint32_t). */
|
|---|
| 726 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
|
|---|
| 727 | /** Doubleword access (uint64_t). */
|
|---|
| 728 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
|
|---|
| 729 | /** @} */
|
|---|
| 730 |
|
|---|
| 731 | /** @} */
|
|---|
| 732 |
|
|---|
| 733 |
|
|---|
| 734 | /** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
|
|---|
| 735 | * @{ */
|
|---|
| 736 | /** Bit 0 - Direction flag. */
|
|---|
| 737 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
|
|---|
| 738 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
|
|---|
| 739 | /** Bit 1 - 4 - CRm value from the instruction. */
|
|---|
| 740 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
|
|---|
| 741 | | RT_BIT_32(4))
|
|---|
| 742 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
|
|---|
| 743 | /** Bit 5 - 9 - Rt value from the instruction. */
|
|---|
| 744 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
|
|---|
| 745 | | RT_BIT_32(8) | RT_BIT_32(9))
|
|---|
| 746 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
|
|---|
| 747 | /** Bit 10 - 13 - CRn value from the instruction. */
|
|---|
| 748 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
|
|---|
| 749 | | RT_BIT_32(13))
|
|---|
| 750 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
|
|---|
| 751 | /** Bit 14 - 16 - Op2 value from the instruction. */
|
|---|
| 752 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
|
|---|
| 753 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
|
|---|
| 754 | /** Bit 17 - 19 - Op2 value from the instruction. */
|
|---|
| 755 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
|
|---|
| 756 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
|
|---|
| 757 | /** Bit 20 - 21 - Op0 value from the instruction. */
|
|---|
| 758 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
|
|---|
| 759 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
|
|---|
| 760 | /** Bit 22 - 24 - Reserved. */
|
|---|
| 761 | #define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
|
|---|
| 762 | /** @} */
|
|---|
| 763 |
|
|---|
| 764 | /** @} */
|
|---|
| 765 |
|
|---|
| 766 | #endif /* !IPRT_INCLUDED_armv8_h */
|
|---|
| 767 |
|
|---|
