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source: vbox/trunk/include/iprt/asm-amd64-x86.h@ 29567

Last change on this file since 29567 was 29270, checked in by vboxsync, 15 years ago

iprt/asm-amd64-x86.h: Don't allow this header to be included on other arch.
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1/** @file
2 * IPRT - AMD64 and x86 Specific Assembly Functions.
3 */
4
5/*
6 * Copyright (C) 2006-2010 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___iprt_asm_amd64_x86_h
27#define ___iprt_asm_amd64_x86_h
28
29#include <iprt/types.h>
30#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
31# error "Not on AMD64 or x86"
32#endif
33
34#if defined(_MSC_VER) && RT_INLINE_ASM_USES_INTRIN
35# include <intrin.h>
36 /* Emit the intrinsics at all optimization levels. */
37# pragma intrinsic(_ReadWriteBarrier)
38# pragma intrinsic(__cpuid)
39# pragma intrinsic(_enable)
40# pragma intrinsic(_disable)
41# pragma intrinsic(__rdtsc)
42# pragma intrinsic(__readmsr)
43# pragma intrinsic(__writemsr)
44# pragma intrinsic(__outbyte)
45# pragma intrinsic(__outbytestring)
46# pragma intrinsic(__outword)
47# pragma intrinsic(__outwordstring)
48# pragma intrinsic(__outdword)
49# pragma intrinsic(__outdwordstring)
50# pragma intrinsic(__inbyte)
51# pragma intrinsic(__inbytestring)
52# pragma intrinsic(__inword)
53# pragma intrinsic(__inwordstring)
54# pragma intrinsic(__indword)
55# pragma intrinsic(__indwordstring)
56# pragma intrinsic(__invlpg)
57# pragma intrinsic(__wbinvd)
58# pragma intrinsic(__readcr0)
59# pragma intrinsic(__readcr2)
60# pragma intrinsic(__readcr3)
61# pragma intrinsic(__readcr4)
62# pragma intrinsic(__writecr0)
63# pragma intrinsic(__writecr3)
64# pragma intrinsic(__writecr4)
65# pragma intrinsic(__readdr)
66# pragma intrinsic(__writedr)
67# ifdef RT_ARCH_AMD64
68# pragma intrinsic(__readcr8)
69# pragma intrinsic(__writecr8)
70# endif
71#endif
72
73
74
75/** @defgroup grp_rt_asm_amd64_x86 AMD64 and x86 Specific ASM Routines
76 * @ingroup grp_rt_asm
77 * @{
78 */
79
80/** @todo find a more proper place for this structure? */
81#pragma pack(1)
82/** IDTR */
83typedef struct RTIDTR
84{
85 /** Size of the IDT. */
86 uint16_t cbIdt;
87 /** Address of the IDT. */
88 uintptr_t pIdt;
89} RTIDTR, *PRTIDTR;
90#pragma pack()
91
92#pragma pack(1)
93/** GDTR */
94typedef struct RTGDTR
95{
96 /** Size of the GDT. */
97 uint16_t cbGdt;
98 /** Address of the GDT. */
99 uintptr_t pGdt;
100} RTGDTR, *PRTGDTR;
101#pragma pack()
102
103
104/**
105 * Gets the content of the IDTR CPU register.
106 * @param pIdtr Where to store the IDTR contents.
107 */
108#if RT_INLINE_ASM_EXTERNAL
109DECLASM(void) ASMGetIDTR(PRTIDTR pIdtr);
110#else
111DECLINLINE(void) ASMGetIDTR(PRTIDTR pIdtr)
112{
113# if RT_INLINE_ASM_GNU_STYLE
114 __asm__ __volatile__("sidt %0" : "=m" (*pIdtr));
115# else
116 __asm
117 {
118# ifdef RT_ARCH_AMD64
119 mov rax, [pIdtr]
120 sidt [rax]
121# else
122 mov eax, [pIdtr]
123 sidt [eax]
124# endif
125 }
126# endif
127}
128#endif
129
130
131/**
132 * Sets the content of the IDTR CPU register.
133 * @param pIdtr Where to load the IDTR contents from
134 */
135#if RT_INLINE_ASM_EXTERNAL
136DECLASM(void) ASMSetIDTR(const RTIDTR *pIdtr);
137#else
138DECLINLINE(void) ASMSetIDTR(const RTIDTR *pIdtr)
139{
140# if RT_INLINE_ASM_GNU_STYLE
141 __asm__ __volatile__("lidt %0" : : "m" (*pIdtr));
142# else
143 __asm
144 {
145# ifdef RT_ARCH_AMD64
146 mov rax, [pIdtr]
147 lidt [rax]
148# else
149 mov eax, [pIdtr]
150 lidt [eax]
151# endif
152 }
153# endif
154}
155#endif
156
157
158/**
159 * Gets the content of the GDTR CPU register.
160 * @param pGdtr Where to store the GDTR contents.
161 */
162#if RT_INLINE_ASM_EXTERNAL
163DECLASM(void) ASMGetGDTR(PRTGDTR pGdtr);
164#else
165DECLINLINE(void) ASMGetGDTR(PRTGDTR pGdtr)
166{
167# if RT_INLINE_ASM_GNU_STYLE
168 __asm__ __volatile__("sgdt %0" : "=m" (*pGdtr));
169# else
170 __asm
171 {
172# ifdef RT_ARCH_AMD64
173 mov rax, [pGdtr]
174 sgdt [rax]
175# else
176 mov eax, [pGdtr]
177 sgdt [eax]
178# endif
179 }
180# endif
181}
182#endif
183
184/**
185 * Get the cs register.
186 * @returns cs.
187 */
188#if RT_INLINE_ASM_EXTERNAL
189DECLASM(RTSEL) ASMGetCS(void);
190#else
191DECLINLINE(RTSEL) ASMGetCS(void)
192{
193 RTSEL SelCS;
194# if RT_INLINE_ASM_GNU_STYLE
195 __asm__ __volatile__("movw %%cs, %0\n\t" : "=r" (SelCS));
196# else
197 __asm
198 {
199 mov ax, cs
200 mov [SelCS], ax
201 }
202# endif
203 return SelCS;
204}
205#endif
206
207
208/**
209 * Get the DS register.
210 * @returns DS.
211 */
212#if RT_INLINE_ASM_EXTERNAL
213DECLASM(RTSEL) ASMGetDS(void);
214#else
215DECLINLINE(RTSEL) ASMGetDS(void)
216{
217 RTSEL SelDS;
218# if RT_INLINE_ASM_GNU_STYLE
219 __asm__ __volatile__("movw %%ds, %0\n\t" : "=r" (SelDS));
220# else
221 __asm
222 {
223 mov ax, ds
224 mov [SelDS], ax
225 }
226# endif
227 return SelDS;
228}
229#endif
230
231
232/**
233 * Get the ES register.
234 * @returns ES.
235 */
236#if RT_INLINE_ASM_EXTERNAL
237DECLASM(RTSEL) ASMGetES(void);
238#else
239DECLINLINE(RTSEL) ASMGetES(void)
240{
241 RTSEL SelES;
242# if RT_INLINE_ASM_GNU_STYLE
243 __asm__ __volatile__("movw %%es, %0\n\t" : "=r" (SelES));
244# else
245 __asm
246 {
247 mov ax, es
248 mov [SelES], ax
249 }
250# endif
251 return SelES;
252}
253#endif
254
255
256/**
257 * Get the FS register.
258 * @returns FS.
259 */
260#if RT_INLINE_ASM_EXTERNAL
261DECLASM(RTSEL) ASMGetFS(void);
262#else
263DECLINLINE(RTSEL) ASMGetFS(void)
264{
265 RTSEL SelFS;
266# if RT_INLINE_ASM_GNU_STYLE
267 __asm__ __volatile__("movw %%fs, %0\n\t" : "=r" (SelFS));
268# else
269 __asm
270 {
271 mov ax, fs
272 mov [SelFS], ax
273 }
274# endif
275 return SelFS;
276}
277# endif
278
279
280/**
281 * Get the GS register.
282 * @returns GS.
283 */
284#if RT_INLINE_ASM_EXTERNAL
285DECLASM(RTSEL) ASMGetGS(void);
286#else
287DECLINLINE(RTSEL) ASMGetGS(void)
288{
289 RTSEL SelGS;
290# if RT_INLINE_ASM_GNU_STYLE
291 __asm__ __volatile__("movw %%gs, %0\n\t" : "=r" (SelGS));
292# else
293 __asm
294 {
295 mov ax, gs
296 mov [SelGS], ax
297 }
298# endif
299 return SelGS;
300}
301#endif
302
303
304/**
305 * Get the SS register.
306 * @returns SS.
307 */
308#if RT_INLINE_ASM_EXTERNAL
309DECLASM(RTSEL) ASMGetSS(void);
310#else
311DECLINLINE(RTSEL) ASMGetSS(void)
312{
313 RTSEL SelSS;
314# if RT_INLINE_ASM_GNU_STYLE
315 __asm__ __volatile__("movw %%ss, %0\n\t" : "=r" (SelSS));
316# else
317 __asm
318 {
319 mov ax, ss
320 mov [SelSS], ax
321 }
322# endif
323 return SelSS;
324}
325#endif
326
327
328/**
329 * Get the TR register.
330 * @returns TR.
331 */
332#if RT_INLINE_ASM_EXTERNAL
333DECLASM(RTSEL) ASMGetTR(void);
334#else
335DECLINLINE(RTSEL) ASMGetTR(void)
336{
337 RTSEL SelTR;
338# if RT_INLINE_ASM_GNU_STYLE
339 __asm__ __volatile__("str %w0\n\t" : "=r" (SelTR));
340# else
341 __asm
342 {
343 str ax
344 mov [SelTR], ax
345 }
346# endif
347 return SelTR;
348}
349#endif
350
351
352/**
353 * Get the [RE]FLAGS register.
354 * @returns [RE]FLAGS.
355 */
356#if RT_INLINE_ASM_EXTERNAL
357DECLASM(RTCCUINTREG) ASMGetFlags(void);
358#else
359DECLINLINE(RTCCUINTREG) ASMGetFlags(void)
360{
361 RTCCUINTREG uFlags;
362# if RT_INLINE_ASM_GNU_STYLE
363# ifdef RT_ARCH_AMD64
364 __asm__ __volatile__("pushfq\n\t"
365 "popq %0\n\t"
366 : "=r" (uFlags));
367# else
368 __asm__ __volatile__("pushfl\n\t"
369 "popl %0\n\t"
370 : "=r" (uFlags));
371# endif
372# else
373 __asm
374 {
375# ifdef RT_ARCH_AMD64
376 pushfq
377 pop [uFlags]
378# else
379 pushfd
380 pop [uFlags]
381# endif
382 }
383# endif
384 return uFlags;
385}
386#endif
387
388
389/**
390 * Set the [RE]FLAGS register.
391 * @param uFlags The new [RE]FLAGS value.
392 */
393#if RT_INLINE_ASM_EXTERNAL
394DECLASM(void) ASMSetFlags(RTCCUINTREG uFlags);
395#else
396DECLINLINE(void) ASMSetFlags(RTCCUINTREG uFlags)
397{
398# if RT_INLINE_ASM_GNU_STYLE
399# ifdef RT_ARCH_AMD64
400 __asm__ __volatile__("pushq %0\n\t"
401 "popfq\n\t"
402 : : "g" (uFlags));
403# else
404 __asm__ __volatile__("pushl %0\n\t"
405 "popfl\n\t"
406 : : "g" (uFlags));
407# endif
408# else
409 __asm
410 {
411# ifdef RT_ARCH_AMD64
412 push [uFlags]
413 popfq
414# else
415 push [uFlags]
416 popfd
417# endif
418 }
419# endif
420}
421#endif
422
423
424/**
425 * Gets the content of the CPU timestamp counter register.
426 *
427 * @returns TSC.
428 */
429#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
430DECLASM(uint64_t) ASMReadTSC(void);
431#else
432DECLINLINE(uint64_t) ASMReadTSC(void)
433{
434 RTUINT64U u;
435# if RT_INLINE_ASM_GNU_STYLE
436 __asm__ __volatile__("rdtsc\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi));
437# else
438# if RT_INLINE_ASM_USES_INTRIN
439 u.u = __rdtsc();
440# else
441 __asm
442 {
443 rdtsc
444 mov [u.s.Lo], eax
445 mov [u.s.Hi], edx
446 }
447# endif
448# endif
449 return u.u;
450}
451#endif
452
453
454/**
455 * Performs the cpuid instruction returning all registers.
456 *
457 * @param uOperator CPUID operation (eax).
458 * @param pvEAX Where to store eax.
459 * @param pvEBX Where to store ebx.
460 * @param pvECX Where to store ecx.
461 * @param pvEDX Where to store edx.
462 * @remark We're using void pointers to ease the use of special bitfield structures and such.
463 */
464#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
465DECLASM(void) ASMCpuId(uint32_t uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
466#else
467DECLINLINE(void) ASMCpuId(uint32_t uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
468{
469# if RT_INLINE_ASM_GNU_STYLE
470# ifdef RT_ARCH_AMD64
471 RTCCUINTREG uRAX, uRBX, uRCX, uRDX;
472 __asm__ ("cpuid\n\t"
473 : "=a" (uRAX),
474 "=b" (uRBX),
475 "=c" (uRCX),
476 "=d" (uRDX)
477 : "0" (uOperator));
478 *(uint32_t *)pvEAX = (uint32_t)uRAX;
479 *(uint32_t *)pvEBX = (uint32_t)uRBX;
480 *(uint32_t *)pvECX = (uint32_t)uRCX;
481 *(uint32_t *)pvEDX = (uint32_t)uRDX;
482# else
483 __asm__ ("xchgl %%ebx, %1\n\t"
484 "cpuid\n\t"
485 "xchgl %%ebx, %1\n\t"
486 : "=a" (*(uint32_t *)pvEAX),
487 "=r" (*(uint32_t *)pvEBX),
488 "=c" (*(uint32_t *)pvECX),
489 "=d" (*(uint32_t *)pvEDX)
490 : "0" (uOperator));
491# endif
492
493# elif RT_INLINE_ASM_USES_INTRIN
494 int aInfo[4];
495 __cpuid(aInfo, uOperator);
496 *(uint32_t *)pvEAX = aInfo[0];
497 *(uint32_t *)pvEBX = aInfo[1];
498 *(uint32_t *)pvECX = aInfo[2];
499 *(uint32_t *)pvEDX = aInfo[3];
500
501# else
502 uint32_t uEAX;
503 uint32_t uEBX;
504 uint32_t uECX;
505 uint32_t uEDX;
506 __asm
507 {
508 push ebx
509 mov eax, [uOperator]
510 cpuid
511 mov [uEAX], eax
512 mov [uEBX], ebx
513 mov [uECX], ecx
514 mov [uEDX], edx
515 pop ebx
516 }
517 *(uint32_t *)pvEAX = uEAX;
518 *(uint32_t *)pvEBX = uEBX;
519 *(uint32_t *)pvECX = uECX;
520 *(uint32_t *)pvEDX = uEDX;
521# endif
522}
523#endif
524
525
526/**
527 * Performs the cpuid instruction returning all registers.
528 * Some subfunctions of cpuid take ECX as additional parameter (currently known for EAX=4)
529 *
530 * @param uOperator CPUID operation (eax).
531 * @param uIdxECX ecx index
532 * @param pvEAX Where to store eax.
533 * @param pvEBX Where to store ebx.
534 * @param pvECX Where to store ecx.
535 * @param pvEDX Where to store edx.
536 * @remark We're using void pointers to ease the use of special bitfield structures and such.
537 */
538#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
539DECLASM(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
540#else
541DECLINLINE(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
542{
543# if RT_INLINE_ASM_GNU_STYLE
544# ifdef RT_ARCH_AMD64
545 RTCCUINTREG uRAX, uRBX, uRCX, uRDX;
546 __asm__ ("cpuid\n\t"
547 : "=a" (uRAX),
548 "=b" (uRBX),
549 "=c" (uRCX),
550 "=d" (uRDX)
551 : "0" (uOperator),
552 "2" (uIdxECX));
553 *(uint32_t *)pvEAX = (uint32_t)uRAX;
554 *(uint32_t *)pvEBX = (uint32_t)uRBX;
555 *(uint32_t *)pvECX = (uint32_t)uRCX;
556 *(uint32_t *)pvEDX = (uint32_t)uRDX;
557# else
558 __asm__ ("xchgl %%ebx, %1\n\t"
559 "cpuid\n\t"
560 "xchgl %%ebx, %1\n\t"
561 : "=a" (*(uint32_t *)pvEAX),
562 "=r" (*(uint32_t *)pvEBX),
563 "=c" (*(uint32_t *)pvECX),
564 "=d" (*(uint32_t *)pvEDX)
565 : "0" (uOperator),
566 "2" (uIdxECX));
567# endif
568
569# elif RT_INLINE_ASM_USES_INTRIN
570 int aInfo[4];
571 /* ??? another intrinsic ??? */
572 __cpuid(aInfo, uOperator);
573 *(uint32_t *)pvEAX = aInfo[0];
574 *(uint32_t *)pvEBX = aInfo[1];
575 *(uint32_t *)pvECX = aInfo[2];
576 *(uint32_t *)pvEDX = aInfo[3];
577
578# else
579 uint32_t uEAX;
580 uint32_t uEBX;
581 uint32_t uECX;
582 uint32_t uEDX;
583 __asm
584 {
585 push ebx
586 mov eax, [uOperator]
587 mov ecx, [uIdxECX]
588 cpuid
589 mov [uEAX], eax
590 mov [uEBX], ebx
591 mov [uECX], ecx
592 mov [uEDX], edx
593 pop ebx
594 }
595 *(uint32_t *)pvEAX = uEAX;
596 *(uint32_t *)pvEBX = uEBX;
597 *(uint32_t *)pvECX = uECX;
598 *(uint32_t *)pvEDX = uEDX;
599# endif
600}
601#endif
602
603
604/**
605 * Performs the cpuid instruction returning ecx and edx.
606 *
607 * @param uOperator CPUID operation (eax).
608 * @param pvECX Where to store ecx.
609 * @param pvEDX Where to store edx.
610 * @remark We're using void pointers to ease the use of special bitfield structures and such.
611 */
612#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
613DECLASM(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void *pvECX, void *pvEDX);
614#else
615DECLINLINE(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void *pvECX, void *pvEDX)
616{
617 uint32_t uEBX;
618 ASMCpuId(uOperator, &uOperator, &uEBX, pvECX, pvEDX);
619}
620#endif
621
622
623/**
624 * Performs the cpuid instruction returning edx.
625 *
626 * @param uOperator CPUID operation (eax).
627 * @returns EDX after cpuid operation.
628 */
629#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
630DECLASM(uint32_t) ASMCpuId_EDX(uint32_t uOperator);
631#else
632DECLINLINE(uint32_t) ASMCpuId_EDX(uint32_t uOperator)
633{
634 RTCCUINTREG xDX;
635# if RT_INLINE_ASM_GNU_STYLE
636# ifdef RT_ARCH_AMD64
637 RTCCUINTREG uSpill;
638 __asm__ ("cpuid"
639 : "=a" (uSpill),
640 "=d" (xDX)
641 : "0" (uOperator)
642 : "rbx", "rcx");
643# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
644 __asm__ ("push %%ebx\n\t"
645 "cpuid\n\t"
646 "pop %%ebx\n\t"
647 : "=a" (uOperator),
648 "=d" (xDX)
649 : "0" (uOperator)
650 : "ecx");
651# else
652 __asm__ ("cpuid"
653 : "=a" (uOperator),
654 "=d" (xDX)
655 : "0" (uOperator)
656 : "ebx", "ecx");
657# endif
658
659# elif RT_INLINE_ASM_USES_INTRIN
660 int aInfo[4];
661 __cpuid(aInfo, uOperator);
662 xDX = aInfo[3];
663
664# else
665 __asm
666 {
667 push ebx
668 mov eax, [uOperator]
669 cpuid
670 mov [xDX], edx
671 pop ebx
672 }
673# endif
674 return (uint32_t)xDX;
675}
676#endif
677
678
679/**
680 * Performs the cpuid instruction returning ecx.
681 *
682 * @param uOperator CPUID operation (eax).
683 * @returns ECX after cpuid operation.
684 */
685#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
686DECLASM(uint32_t) ASMCpuId_ECX(uint32_t uOperator);
687#else
688DECLINLINE(uint32_t) ASMCpuId_ECX(uint32_t uOperator)
689{
690 RTCCUINTREG xCX;
691# if RT_INLINE_ASM_GNU_STYLE
692# ifdef RT_ARCH_AMD64
693 RTCCUINTREG uSpill;
694 __asm__ ("cpuid"
695 : "=a" (uSpill),
696 "=c" (xCX)
697 : "0" (uOperator)
698 : "rbx", "rdx");
699# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
700 __asm__ ("push %%ebx\n\t"
701 "cpuid\n\t"
702 "pop %%ebx\n\t"
703 : "=a" (uOperator),
704 "=c" (xCX)
705 : "0" (uOperator)
706 : "edx");
707# else
708 __asm__ ("cpuid"
709 : "=a" (uOperator),
710 "=c" (xCX)
711 : "0" (uOperator)
712 : "ebx", "edx");
713
714# endif
715
716# elif RT_INLINE_ASM_USES_INTRIN
717 int aInfo[4];
718 __cpuid(aInfo, uOperator);
719 xCX = aInfo[2];
720
721# else
722 __asm
723 {
724 push ebx
725 mov eax, [uOperator]
726 cpuid
727 mov [xCX], ecx
728 pop ebx
729 }
730# endif
731 return (uint32_t)xCX;
732}
733#endif
734
735
736/**
737 * Checks if the current CPU supports CPUID.
738 *
739 * @returns true if CPUID is supported.
740 */
741DECLINLINE(bool) ASMHasCpuId(void)
742{
743#ifdef RT_ARCH_AMD64
744 return true; /* ASSUME that all amd64 compatible CPUs have cpuid. */
745#else /* !RT_ARCH_AMD64 */
746 bool fRet = false;
747# if RT_INLINE_ASM_GNU_STYLE
748 uint32_t u1;
749 uint32_t u2;
750 __asm__ ("pushf\n\t"
751 "pop %1\n\t"
752 "mov %1, %2\n\t"
753 "xorl $0x200000, %1\n\t"
754 "push %1\n\t"
755 "popf\n\t"
756 "pushf\n\t"
757 "pop %1\n\t"
758 "cmpl %1, %2\n\t"
759 "setne %0\n\t"
760 "push %2\n\t"
761 "popf\n\t"
762 : "=m" (fRet), "=r" (u1), "=r" (u2));
763# else
764 __asm
765 {
766 pushfd
767 pop eax
768 mov ebx, eax
769 xor eax, 0200000h
770 push eax
771 popfd
772 pushfd
773 pop eax
774 cmp eax, ebx
775 setne fRet
776 push ebx
777 popfd
778 }
779# endif
780 return fRet;
781#endif /* !RT_ARCH_AMD64 */
782}
783
784
785/**
786 * Gets the APIC ID of the current CPU.
787 *
788 * @returns the APIC ID.
789 */
790#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
791DECLASM(uint8_t) ASMGetApicId(void);
792#else
793DECLINLINE(uint8_t) ASMGetApicId(void)
794{
795 RTCCUINTREG xBX;
796# if RT_INLINE_ASM_GNU_STYLE
797# ifdef RT_ARCH_AMD64
798 RTCCUINTREG uSpill;
799 __asm__ ("cpuid"
800 : "=a" (uSpill),
801 "=b" (xBX)
802 : "0" (1)
803 : "rcx", "rdx");
804# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
805 RTCCUINTREG uSpill;
806 __asm__ ("mov %%ebx,%1\n\t"
807 "cpuid\n\t"
808 "xchgl %%ebx,%1\n\t"
809 : "=a" (uSpill),
810 "=r" (xBX)
811 : "0" (1)
812 : "ecx", "edx");
813# else
814 RTCCUINTREG uSpill;
815 __asm__ ("cpuid"
816 : "=a" (uSpill),
817 "=b" (xBX)
818 : "0" (1)
819 : "ecx", "edx");
820# endif
821
822# elif RT_INLINE_ASM_USES_INTRIN
823 int aInfo[4];
824 __cpuid(aInfo, 1);
825 xBX = aInfo[1];
826
827# else
828 __asm
829 {
830 push ebx
831 mov eax, 1
832 cpuid
833 mov [xBX], ebx
834 pop ebx
835 }
836# endif
837 return (uint8_t)(xBX >> 24);
838}
839#endif
840
841
842/**
843 * Tests if it a genuine Intel CPU based on the ASMCpuId(0) output.
844 *
845 * @returns true/false.
846 * @param uEBX EBX return from ASMCpuId(0)
847 * @param uECX ECX return from ASMCpuId(0)
848 * @param uEDX EDX return from ASMCpuId(0)
849 */
850DECLINLINE(bool) ASMIsIntelCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
851{
852 return uEBX == UINT32_C(0x756e6547)
853 && uECX == UINT32_C(0x6c65746e)
854 && uEDX == UINT32_C(0x49656e69);
855}
856
857
858/**
859 * Tests if this is a genuine Intel CPU.
860 *
861 * @returns true/false.
862 * @remarks ASSUMES that cpuid is supported by the CPU.
863 */
864DECLINLINE(bool) ASMIsIntelCpu(void)
865{
866 uint32_t uEAX, uEBX, uECX, uEDX;
867 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
868 return ASMIsIntelCpuEx(uEBX, uECX, uEDX);
869}
870
871
872/**
873 * Tests if it a authentic AMD CPU based on the ASMCpuId(0) output.
874 *
875 * @returns true/false.
876 * @param uEBX EBX return from ASMCpuId(0)
877 * @param uECX ECX return from ASMCpuId(0)
878 * @param uEDX EDX return from ASMCpuId(0)
879 */
880DECLINLINE(bool) ASMIsAmdCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
881{
882 return uEBX == UINT32_C(0x68747541)
883 && uECX == UINT32_C(0x444d4163)
884 && uEDX == UINT32_C(0x69746e65);
885}
886
887
888/**
889 * Tests if this is an authentic AMD CPU.
890 *
891 * @returns true/false.
892 * @remarks ASSUMES that cpuid is supported by the CPU.
893 */
894DECLINLINE(bool) ASMIsAmdCpu(void)
895{
896 uint32_t uEAX, uEBX, uECX, uEDX;
897 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
898 return ASMIsAmdCpuEx(uEBX, uECX, uEDX);
899}
900
901
902/**
903 * Extracts the CPU family from ASMCpuId(1) or ASMCpuId(0x80000001)
904 *
905 * @returns Family.
906 * @param uEAX EAX return from ASMCpuId(1) or ASMCpuId(0x80000001).
907 */
908DECLINLINE(uint32_t) ASMGetCpuFamily(uint32_t uEAX)
909{
910 return ((uEAX >> 8) & 0xf) == 0xf
911 ? ((uEAX >> 20) & 0x7f) + 0xf
912 : ((uEAX >> 8) & 0xf);
913}
914
915
916/**
917 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), Intel variant.
918 *
919 * @returns Model.
920 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
921 */
922DECLINLINE(uint32_t) ASMGetCpuModelIntel(uint32_t uEAX)
923{
924 return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6) /* family! */
925 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
926 : ((uEAX >> 4) & 0xf);
927}
928
929
930/**
931 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), AMD variant.
932 *
933 * @returns Model.
934 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
935 */
936DECLINLINE(uint32_t) ASMGetCpuModelAMD(uint32_t uEAX)
937{
938 return ((uEAX >> 8) & 0xf) == 0xf
939 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
940 : ((uEAX >> 4) & 0xf);
941}
942
943
944/**
945 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001)
946 *
947 * @returns Model.
948 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
949 * @param fIntel Whether it's an intel CPU. Use ASMIsIntelCpuEx() or ASMIsIntelCpu().
950 */
951DECLINLINE(uint32_t) ASMGetCpuModel(uint32_t uEAX, bool fIntel)
952{
953 return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6 && fIntel) /* family! */
954 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
955 : ((uEAX >> 4) & 0xf);
956}
957
958
959/**
960 * Extracts the CPU stepping from ASMCpuId(1) or ASMCpuId(0x80000001)
961 *
962 * @returns Model.
963 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
964 */
965DECLINLINE(uint32_t) ASMGetCpuStepping(uint32_t uEAX)
966{
967 return uEAX & 0xf;
968}
969
970
971/**
972 * Get cr0.
973 * @returns cr0.
974 */
975#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
976DECLASM(RTCCUINTREG) ASMGetCR0(void);
977#else
978DECLINLINE(RTCCUINTREG) ASMGetCR0(void)
979{
980 RTCCUINTREG uCR0;
981# if RT_INLINE_ASM_USES_INTRIN
982 uCR0 = __readcr0();
983
984# elif RT_INLINE_ASM_GNU_STYLE
985# ifdef RT_ARCH_AMD64
986 __asm__ __volatile__("movq %%cr0, %0\t\n" : "=r" (uCR0));
987# else
988 __asm__ __volatile__("movl %%cr0, %0\t\n" : "=r" (uCR0));
989# endif
990# else
991 __asm
992 {
993# ifdef RT_ARCH_AMD64
994 mov rax, cr0
995 mov [uCR0], rax
996# else
997 mov eax, cr0
998 mov [uCR0], eax
999# endif
1000 }
1001# endif
1002 return uCR0;
1003}
1004#endif
1005
1006
1007/**
1008 * Sets the CR0 register.
1009 * @param uCR0 The new CR0 value.
1010 */
1011#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1012DECLASM(void) ASMSetCR0(RTCCUINTREG uCR0);
1013#else
1014DECLINLINE(void) ASMSetCR0(RTCCUINTREG uCR0)
1015{
1016# if RT_INLINE_ASM_USES_INTRIN
1017 __writecr0(uCR0);
1018
1019# elif RT_INLINE_ASM_GNU_STYLE
1020# ifdef RT_ARCH_AMD64
1021 __asm__ __volatile__("movq %0, %%cr0\n\t" :: "r" (uCR0));
1022# else
1023 __asm__ __volatile__("movl %0, %%cr0\n\t" :: "r" (uCR0));
1024# endif
1025# else
1026 __asm
1027 {
1028# ifdef RT_ARCH_AMD64
1029 mov rax, [uCR0]
1030 mov cr0, rax
1031# else
1032 mov eax, [uCR0]
1033 mov cr0, eax
1034# endif
1035 }
1036# endif
1037}
1038#endif
1039
1040
1041/**
1042 * Get cr2.
1043 * @returns cr2.
1044 */
1045#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1046DECLASM(RTCCUINTREG) ASMGetCR2(void);
1047#else
1048DECLINLINE(RTCCUINTREG) ASMGetCR2(void)
1049{
1050 RTCCUINTREG uCR2;
1051# if RT_INLINE_ASM_USES_INTRIN
1052 uCR2 = __readcr2();
1053
1054# elif RT_INLINE_ASM_GNU_STYLE
1055# ifdef RT_ARCH_AMD64
1056 __asm__ __volatile__("movq %%cr2, %0\t\n" : "=r" (uCR2));
1057# else
1058 __asm__ __volatile__("movl %%cr2, %0\t\n" : "=r" (uCR2));
1059# endif
1060# else
1061 __asm
1062 {
1063# ifdef RT_ARCH_AMD64
1064 mov rax, cr2
1065 mov [uCR2], rax
1066# else
1067 mov eax, cr2
1068 mov [uCR2], eax
1069# endif
1070 }
1071# endif
1072 return uCR2;
1073}
1074#endif
1075
1076
1077/**
1078 * Sets the CR2 register.
1079 * @param uCR2 The new CR0 value.
1080 */
1081#if RT_INLINE_ASM_EXTERNAL
1082DECLASM(void) ASMSetCR2(RTCCUINTREG uCR2);
1083#else
1084DECLINLINE(void) ASMSetCR2(RTCCUINTREG uCR2)
1085{
1086# if RT_INLINE_ASM_GNU_STYLE
1087# ifdef RT_ARCH_AMD64
1088 __asm__ __volatile__("movq %0, %%cr2\n\t" :: "r" (uCR2));
1089# else
1090 __asm__ __volatile__("movl %0, %%cr2\n\t" :: "r" (uCR2));
1091# endif
1092# else
1093 __asm
1094 {
1095# ifdef RT_ARCH_AMD64
1096 mov rax, [uCR2]
1097 mov cr2, rax
1098# else
1099 mov eax, [uCR2]
1100 mov cr2, eax
1101# endif
1102 }
1103# endif
1104}
1105#endif
1106
1107
1108/**
1109 * Get cr3.
1110 * @returns cr3.
1111 */
1112#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1113DECLASM(RTCCUINTREG) ASMGetCR3(void);
1114#else
1115DECLINLINE(RTCCUINTREG) ASMGetCR3(void)
1116{
1117 RTCCUINTREG uCR3;
1118# if RT_INLINE_ASM_USES_INTRIN
1119 uCR3 = __readcr3();
1120
1121# elif RT_INLINE_ASM_GNU_STYLE
1122# ifdef RT_ARCH_AMD64
1123 __asm__ __volatile__("movq %%cr3, %0\t\n" : "=r" (uCR3));
1124# else
1125 __asm__ __volatile__("movl %%cr3, %0\t\n" : "=r" (uCR3));
1126# endif
1127# else
1128 __asm
1129 {
1130# ifdef RT_ARCH_AMD64
1131 mov rax, cr3
1132 mov [uCR3], rax
1133# else
1134 mov eax, cr3
1135 mov [uCR3], eax
1136# endif
1137 }
1138# endif
1139 return uCR3;
1140}
1141#endif
1142
1143
1144/**
1145 * Sets the CR3 register.
1146 *
1147 * @param uCR3 New CR3 value.
1148 */
1149#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1150DECLASM(void) ASMSetCR3(RTCCUINTREG uCR3);
1151#else
1152DECLINLINE(void) ASMSetCR3(RTCCUINTREG uCR3)
1153{
1154# if RT_INLINE_ASM_USES_INTRIN
1155 __writecr3(uCR3);
1156
1157# elif RT_INLINE_ASM_GNU_STYLE
1158# ifdef RT_ARCH_AMD64
1159 __asm__ __volatile__("movq %0, %%cr3\n\t" : : "r" (uCR3));
1160# else
1161 __asm__ __volatile__("movl %0, %%cr3\n\t" : : "r" (uCR3));
1162# endif
1163# else
1164 __asm
1165 {
1166# ifdef RT_ARCH_AMD64
1167 mov rax, [uCR3]
1168 mov cr3, rax
1169# else
1170 mov eax, [uCR3]
1171 mov cr3, eax
1172# endif
1173 }
1174# endif
1175}
1176#endif
1177
1178
1179/**
1180 * Reloads the CR3 register.
1181 */
1182#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1183DECLASM(void) ASMReloadCR3(void);
1184#else
1185DECLINLINE(void) ASMReloadCR3(void)
1186{
1187# if RT_INLINE_ASM_USES_INTRIN
1188 __writecr3(__readcr3());
1189
1190# elif RT_INLINE_ASM_GNU_STYLE
1191 RTCCUINTREG u;
1192# ifdef RT_ARCH_AMD64
1193 __asm__ __volatile__("movq %%cr3, %0\n\t"
1194 "movq %0, %%cr3\n\t"
1195 : "=r" (u));
1196# else
1197 __asm__ __volatile__("movl %%cr3, %0\n\t"
1198 "movl %0, %%cr3\n\t"
1199 : "=r" (u));
1200# endif
1201# else
1202 __asm
1203 {
1204# ifdef RT_ARCH_AMD64
1205 mov rax, cr3
1206 mov cr3, rax
1207# else
1208 mov eax, cr3
1209 mov cr3, eax
1210# endif
1211 }
1212# endif
1213}
1214#endif
1215
1216
1217/**
1218 * Get cr4.
1219 * @returns cr4.
1220 */
1221#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1222DECLASM(RTCCUINTREG) ASMGetCR4(void);
1223#else
1224DECLINLINE(RTCCUINTREG) ASMGetCR4(void)
1225{
1226 RTCCUINTREG uCR4;
1227# if RT_INLINE_ASM_USES_INTRIN
1228 uCR4 = __readcr4();
1229
1230# elif RT_INLINE_ASM_GNU_STYLE
1231# ifdef RT_ARCH_AMD64
1232 __asm__ __volatile__("movq %%cr4, %0\t\n" : "=r" (uCR4));
1233# else
1234 __asm__ __volatile__("movl %%cr4, %0\t\n" : "=r" (uCR4));
1235# endif
1236# else
1237 __asm
1238 {
1239# ifdef RT_ARCH_AMD64
1240 mov rax, cr4
1241 mov [uCR4], rax
1242# else
1243 push eax /* just in case */
1244 /*mov eax, cr4*/
1245 _emit 0x0f
1246 _emit 0x20
1247 _emit 0xe0
1248 mov [uCR4], eax
1249 pop eax
1250# endif
1251 }
1252# endif
1253 return uCR4;
1254}
1255#endif
1256
1257
1258/**
1259 * Sets the CR4 register.
1260 *
1261 * @param uCR4 New CR4 value.
1262 */
1263#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1264DECLASM(void) ASMSetCR4(RTCCUINTREG uCR4);
1265#else
1266DECLINLINE(void) ASMSetCR4(RTCCUINTREG uCR4)
1267{
1268# if RT_INLINE_ASM_USES_INTRIN
1269 __writecr4(uCR4);
1270
1271# elif RT_INLINE_ASM_GNU_STYLE
1272# ifdef RT_ARCH_AMD64
1273 __asm__ __volatile__("movq %0, %%cr4\n\t" : : "r" (uCR4));
1274# else
1275 __asm__ __volatile__("movl %0, %%cr4\n\t" : : "r" (uCR4));
1276# endif
1277# else
1278 __asm
1279 {
1280# ifdef RT_ARCH_AMD64
1281 mov rax, [uCR4]
1282 mov cr4, rax
1283# else
1284 mov eax, [uCR4]
1285 _emit 0x0F
1286 _emit 0x22
1287 _emit 0xE0 /* mov cr4, eax */
1288# endif
1289 }
1290# endif
1291}
1292#endif
1293
1294
1295/**
1296 * Get cr8.
1297 * @returns cr8.
1298 * @remark The lock prefix hack for access from non-64-bit modes is NOT used and 0 is returned.
1299 */
1300#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1301DECLASM(RTCCUINTREG) ASMGetCR8(void);
1302#else
1303DECLINLINE(RTCCUINTREG) ASMGetCR8(void)
1304{
1305# ifdef RT_ARCH_AMD64
1306 RTCCUINTREG uCR8;
1307# if RT_INLINE_ASM_USES_INTRIN
1308 uCR8 = __readcr8();
1309
1310# elif RT_INLINE_ASM_GNU_STYLE
1311 __asm__ __volatile__("movq %%cr8, %0\t\n" : "=r" (uCR8));
1312# else
1313 __asm
1314 {
1315 mov rax, cr8
1316 mov [uCR8], rax
1317 }
1318# endif
1319 return uCR8;
1320# else /* !RT_ARCH_AMD64 */
1321 return 0;
1322# endif /* !RT_ARCH_AMD64 */
1323}
1324#endif
1325
1326
1327/**
1328 * Enables interrupts (EFLAGS.IF).
1329 */
1330#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1331DECLASM(void) ASMIntEnable(void);
1332#else
1333DECLINLINE(void) ASMIntEnable(void)
1334{
1335# if RT_INLINE_ASM_GNU_STYLE
1336 __asm("sti\n");
1337# elif RT_INLINE_ASM_USES_INTRIN
1338 _enable();
1339# else
1340 __asm sti
1341# endif
1342}
1343#endif
1344
1345
1346/**
1347 * Disables interrupts (!EFLAGS.IF).
1348 */
1349#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1350DECLASM(void) ASMIntDisable(void);
1351#else
1352DECLINLINE(void) ASMIntDisable(void)
1353{
1354# if RT_INLINE_ASM_GNU_STYLE
1355 __asm("cli\n");
1356# elif RT_INLINE_ASM_USES_INTRIN
1357 _disable();
1358# else
1359 __asm cli
1360# endif
1361}
1362#endif
1363
1364
1365/**
1366 * Disables interrupts and returns previous xFLAGS.
1367 */
1368#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1369DECLASM(RTCCUINTREG) ASMIntDisableFlags(void);
1370#else
1371DECLINLINE(RTCCUINTREG) ASMIntDisableFlags(void)
1372{
1373 RTCCUINTREG xFlags;
1374# if RT_INLINE_ASM_GNU_STYLE
1375# ifdef RT_ARCH_AMD64
1376 __asm__ __volatile__("pushfq\n\t"
1377 "cli\n\t"
1378 "popq %0\n\t"
1379 : "=r" (xFlags));
1380# else
1381 __asm__ __volatile__("pushfl\n\t"
1382 "cli\n\t"
1383 "popl %0\n\t"
1384 : "=r" (xFlags));
1385# endif
1386# elif RT_INLINE_ASM_USES_INTRIN && !defined(RT_ARCH_X86)
1387 xFlags = ASMGetFlags();
1388 _disable();
1389# else
1390 __asm {
1391 pushfd
1392 cli
1393 pop [xFlags]
1394 }
1395# endif
1396 return xFlags;
1397}
1398#endif
1399
1400
1401/**
1402 * Are interrupts enabled?
1403 *
1404 * @returns true / false.
1405 */
1406DECLINLINE(RTCCUINTREG) ASMIntAreEnabled(void)
1407{
1408 RTCCUINTREG uFlags = ASMGetFlags();
1409 return uFlags & 0x200 /* X86_EFL_IF */ ? true : false;
1410}
1411
1412
1413/**
1414 * Halts the CPU until interrupted.
1415 */
1416#if RT_INLINE_ASM_EXTERNAL
1417DECLASM(void) ASMHalt(void);
1418#else
1419DECLINLINE(void) ASMHalt(void)
1420{
1421# if RT_INLINE_ASM_GNU_STYLE
1422 __asm__ __volatile__("hlt\n\t");
1423# else
1424 __asm {
1425 hlt
1426 }
1427# endif
1428}
1429#endif
1430
1431
1432/**
1433 * Reads a machine specific register.
1434 *
1435 * @returns Register content.
1436 * @param uRegister Register to read.
1437 */
1438#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1439DECLASM(uint64_t) ASMRdMsr(uint32_t uRegister);
1440#else
1441DECLINLINE(uint64_t) ASMRdMsr(uint32_t uRegister)
1442{
1443 RTUINT64U u;
1444# if RT_INLINE_ASM_GNU_STYLE
1445 __asm__ __volatile__("rdmsr\n\t"
1446 : "=a" (u.s.Lo),
1447 "=d" (u.s.Hi)
1448 : "c" (uRegister));
1449
1450# elif RT_INLINE_ASM_USES_INTRIN
1451 u.u = __readmsr(uRegister);
1452
1453# else
1454 __asm
1455 {
1456 mov ecx, [uRegister]
1457 rdmsr
1458 mov [u.s.Lo], eax
1459 mov [u.s.Hi], edx
1460 }
1461# endif
1462
1463 return u.u;
1464}
1465#endif
1466
1467
1468/**
1469 * Writes a machine specific register.
1470 *
1471 * @returns Register content.
1472 * @param uRegister Register to write to.
1473 * @param u64Val Value to write.
1474 */
1475#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1476DECLASM(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val);
1477#else
1478DECLINLINE(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val)
1479{
1480 RTUINT64U u;
1481
1482 u.u = u64Val;
1483# if RT_INLINE_ASM_GNU_STYLE
1484 __asm__ __volatile__("wrmsr\n\t"
1485 ::"a" (u.s.Lo),
1486 "d" (u.s.Hi),
1487 "c" (uRegister));
1488
1489# elif RT_INLINE_ASM_USES_INTRIN
1490 __writemsr(uRegister, u.u);
1491
1492# else
1493 __asm
1494 {
1495 mov ecx, [uRegister]
1496 mov edx, [u.s.Hi]
1497 mov eax, [u.s.Lo]
1498 wrmsr
1499 }
1500# endif
1501}
1502#endif
1503
1504
1505/**
1506 * Reads low part of a machine specific register.
1507 *
1508 * @returns Register content.
1509 * @param uRegister Register to read.
1510 */
1511#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1512DECLASM(uint32_t) ASMRdMsr_Low(uint32_t uRegister);
1513#else
1514DECLINLINE(uint32_t) ASMRdMsr_Low(uint32_t uRegister)
1515{
1516 uint32_t u32;
1517# if RT_INLINE_ASM_GNU_STYLE
1518 __asm__ __volatile__("rdmsr\n\t"
1519 : "=a" (u32)
1520 : "c" (uRegister)
1521 : "edx");
1522
1523# elif RT_INLINE_ASM_USES_INTRIN
1524 u32 = (uint32_t)__readmsr(uRegister);
1525
1526#else
1527 __asm
1528 {
1529 mov ecx, [uRegister]
1530 rdmsr
1531 mov [u32], eax
1532 }
1533# endif
1534
1535 return u32;
1536}
1537#endif
1538
1539
1540/**
1541 * Reads high part of a machine specific register.
1542 *
1543 * @returns Register content.
1544 * @param uRegister Register to read.
1545 */
1546#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1547DECLASM(uint32_t) ASMRdMsr_High(uint32_t uRegister);
1548#else
1549DECLINLINE(uint32_t) ASMRdMsr_High(uint32_t uRegister)
1550{
1551 uint32_t u32;
1552# if RT_INLINE_ASM_GNU_STYLE
1553 __asm__ __volatile__("rdmsr\n\t"
1554 : "=d" (u32)
1555 : "c" (uRegister)
1556 : "eax");
1557
1558# elif RT_INLINE_ASM_USES_INTRIN
1559 u32 = (uint32_t)(__readmsr(uRegister) >> 32);
1560
1561# else
1562 __asm
1563 {
1564 mov ecx, [uRegister]
1565 rdmsr
1566 mov [u32], edx
1567 }
1568# endif
1569
1570 return u32;
1571}
1572#endif
1573
1574
1575/**
1576 * Gets dr0.
1577 *
1578 * @returns dr0.
1579 */
1580#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1581DECLASM(RTCCUINTREG) ASMGetDR0(void);
1582#else
1583DECLINLINE(RTCCUINTREG) ASMGetDR0(void)
1584{
1585 RTCCUINTREG uDR0;
1586# if RT_INLINE_ASM_USES_INTRIN
1587 uDR0 = __readdr(0);
1588# elif RT_INLINE_ASM_GNU_STYLE
1589# ifdef RT_ARCH_AMD64
1590 __asm__ __volatile__("movq %%dr0, %0\n\t" : "=r" (uDR0));
1591# else
1592 __asm__ __volatile__("movl %%dr0, %0\n\t" : "=r" (uDR0));
1593# endif
1594# else
1595 __asm
1596 {
1597# ifdef RT_ARCH_AMD64
1598 mov rax, dr0
1599 mov [uDR0], rax
1600# else
1601 mov eax, dr0
1602 mov [uDR0], eax
1603# endif
1604 }
1605# endif
1606 return uDR0;
1607}
1608#endif
1609
1610
1611/**
1612 * Gets dr1.
1613 *
1614 * @returns dr1.
1615 */
1616#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1617DECLASM(RTCCUINTREG) ASMGetDR1(void);
1618#else
1619DECLINLINE(RTCCUINTREG) ASMGetDR1(void)
1620{
1621 RTCCUINTREG uDR1;
1622# if RT_INLINE_ASM_USES_INTRIN
1623 uDR1 = __readdr(1);
1624# elif RT_INLINE_ASM_GNU_STYLE
1625# ifdef RT_ARCH_AMD64
1626 __asm__ __volatile__("movq %%dr1, %0\n\t" : "=r" (uDR1));
1627# else
1628 __asm__ __volatile__("movl %%dr1, %0\n\t" : "=r" (uDR1));
1629# endif
1630# else
1631 __asm
1632 {
1633# ifdef RT_ARCH_AMD64
1634 mov rax, dr1
1635 mov [uDR1], rax
1636# else
1637 mov eax, dr1
1638 mov [uDR1], eax
1639# endif
1640 }
1641# endif
1642 return uDR1;
1643}
1644#endif
1645
1646
1647/**
1648 * Gets dr2.
1649 *
1650 * @returns dr2.
1651 */
1652#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1653DECLASM(RTCCUINTREG) ASMGetDR2(void);
1654#else
1655DECLINLINE(RTCCUINTREG) ASMGetDR2(void)
1656{
1657 RTCCUINTREG uDR2;
1658# if RT_INLINE_ASM_USES_INTRIN
1659 uDR2 = __readdr(2);
1660# elif RT_INLINE_ASM_GNU_STYLE
1661# ifdef RT_ARCH_AMD64
1662 __asm__ __volatile__("movq %%dr2, %0\n\t" : "=r" (uDR2));
1663# else
1664 __asm__ __volatile__("movl %%dr2, %0\n\t" : "=r" (uDR2));
1665# endif
1666# else
1667 __asm
1668 {
1669# ifdef RT_ARCH_AMD64
1670 mov rax, dr2
1671 mov [uDR2], rax
1672# else
1673 mov eax, dr2
1674 mov [uDR2], eax
1675# endif
1676 }
1677# endif
1678 return uDR2;
1679}
1680#endif
1681
1682
1683/**
1684 * Gets dr3.
1685 *
1686 * @returns dr3.
1687 */
1688#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1689DECLASM(RTCCUINTREG) ASMGetDR3(void);
1690#else
1691DECLINLINE(RTCCUINTREG) ASMGetDR3(void)
1692{
1693 RTCCUINTREG uDR3;
1694# if RT_INLINE_ASM_USES_INTRIN
1695 uDR3 = __readdr(3);
1696# elif RT_INLINE_ASM_GNU_STYLE
1697# ifdef RT_ARCH_AMD64
1698 __asm__ __volatile__("movq %%dr3, %0\n\t" : "=r" (uDR3));
1699# else
1700 __asm__ __volatile__("movl %%dr3, %0\n\t" : "=r" (uDR3));
1701# endif
1702# else
1703 __asm
1704 {
1705# ifdef RT_ARCH_AMD64
1706 mov rax, dr3
1707 mov [uDR3], rax
1708# else
1709 mov eax, dr3
1710 mov [uDR3], eax
1711# endif
1712 }
1713# endif
1714 return uDR3;
1715}
1716#endif
1717
1718
1719/**
1720 * Gets dr6.
1721 *
1722 * @returns dr6.
1723 */
1724#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1725DECLASM(RTCCUINTREG) ASMGetDR6(void);
1726#else
1727DECLINLINE(RTCCUINTREG) ASMGetDR6(void)
1728{
1729 RTCCUINTREG uDR6;
1730# if RT_INLINE_ASM_USES_INTRIN
1731 uDR6 = __readdr(6);
1732# elif RT_INLINE_ASM_GNU_STYLE
1733# ifdef RT_ARCH_AMD64
1734 __asm__ __volatile__("movq %%dr6, %0\n\t" : "=r" (uDR6));
1735# else
1736 __asm__ __volatile__("movl %%dr6, %0\n\t" : "=r" (uDR6));
1737# endif
1738# else
1739 __asm
1740 {
1741# ifdef RT_ARCH_AMD64
1742 mov rax, dr6
1743 mov [uDR6], rax
1744# else
1745 mov eax, dr6
1746 mov [uDR6], eax
1747# endif
1748 }
1749# endif
1750 return uDR6;
1751}
1752#endif
1753
1754
1755/**
1756 * Reads and clears DR6.
1757 *
1758 * @returns DR6.
1759 */
1760#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1761DECLASM(RTCCUINTREG) ASMGetAndClearDR6(void);
1762#else
1763DECLINLINE(RTCCUINTREG) ASMGetAndClearDR6(void)
1764{
1765 RTCCUINTREG uDR6;
1766# if RT_INLINE_ASM_USES_INTRIN
1767 uDR6 = __readdr(6);
1768 __writedr(6, 0xffff0ff0U); /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
1769# elif RT_INLINE_ASM_GNU_STYLE
1770 RTCCUINTREG uNewValue = 0xffff0ff0U;/* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
1771# ifdef RT_ARCH_AMD64
1772 __asm__ __volatile__("movq %%dr6, %0\n\t"
1773 "movq %1, %%dr6\n\t"
1774 : "=r" (uDR6)
1775 : "r" (uNewValue));
1776# else
1777 __asm__ __volatile__("movl %%dr6, %0\n\t"
1778 "movl %1, %%dr6\n\t"
1779 : "=r" (uDR6)
1780 : "r" (uNewValue));
1781# endif
1782# else
1783 __asm
1784 {
1785# ifdef RT_ARCH_AMD64
1786 mov rax, dr6
1787 mov [uDR6], rax
1788 mov rcx, rax
1789 mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
1790 mov dr6, rcx
1791# else
1792 mov eax, dr6
1793 mov [uDR6], eax
1794 mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 is zero. */
1795 mov dr6, ecx
1796# endif
1797 }
1798# endif
1799 return uDR6;
1800}
1801#endif
1802
1803
1804/**
1805 * Gets dr7.
1806 *
1807 * @returns dr7.
1808 */
1809#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1810DECLASM(RTCCUINTREG) ASMGetDR7(void);
1811#else
1812DECLINLINE(RTCCUINTREG) ASMGetDR7(void)
1813{
1814 RTCCUINTREG uDR7;
1815# if RT_INLINE_ASM_USES_INTRIN
1816 uDR7 = __readdr(7);
1817# elif RT_INLINE_ASM_GNU_STYLE
1818# ifdef RT_ARCH_AMD64
1819 __asm__ __volatile__("movq %%dr7, %0\n\t" : "=r" (uDR7));
1820# else
1821 __asm__ __volatile__("movl %%dr7, %0\n\t" : "=r" (uDR7));
1822# endif
1823# else
1824 __asm
1825 {
1826# ifdef RT_ARCH_AMD64
1827 mov rax, dr7
1828 mov [uDR7], rax
1829# else
1830 mov eax, dr7
1831 mov [uDR7], eax
1832# endif
1833 }
1834# endif
1835 return uDR7;
1836}
1837#endif
1838
1839
1840/**
1841 * Sets dr0.
1842 *
1843 * @param uDRVal Debug register value to write
1844 */
1845#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1846DECLASM(void) ASMSetDR0(RTCCUINTREG uDRVal);
1847#else
1848DECLINLINE(void) ASMSetDR0(RTCCUINTREG uDRVal)
1849{
1850# if RT_INLINE_ASM_USES_INTRIN
1851 __writedr(0, uDRVal);
1852# elif RT_INLINE_ASM_GNU_STYLE
1853# ifdef RT_ARCH_AMD64
1854 __asm__ __volatile__("movq %0, %%dr0\n\t" : : "r" (uDRVal));
1855# else
1856 __asm__ __volatile__("movl %0, %%dr0\n\t" : : "r" (uDRVal));
1857# endif
1858# else
1859 __asm
1860 {
1861# ifdef RT_ARCH_AMD64
1862 mov rax, [uDRVal]
1863 mov dr0, rax
1864# else
1865 mov eax, [uDRVal]
1866 mov dr0, eax
1867# endif
1868 }
1869# endif
1870}
1871#endif
1872
1873
1874/**
1875 * Sets dr1.
1876 *
1877 * @param uDRVal Debug register value to write
1878 */
1879#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1880DECLASM(void) ASMSetDR1(RTCCUINTREG uDRVal);
1881#else
1882DECLINLINE(void) ASMSetDR1(RTCCUINTREG uDRVal)
1883{
1884# if RT_INLINE_ASM_USES_INTRIN
1885 __writedr(1, uDRVal);
1886# elif RT_INLINE_ASM_GNU_STYLE
1887# ifdef RT_ARCH_AMD64
1888 __asm__ __volatile__("movq %0, %%dr1\n\t" : : "r" (uDRVal));
1889# else
1890 __asm__ __volatile__("movl %0, %%dr1\n\t" : : "r" (uDRVal));
1891# endif
1892# else
1893 __asm
1894 {
1895# ifdef RT_ARCH_AMD64
1896 mov rax, [uDRVal]
1897 mov dr1, rax
1898# else
1899 mov eax, [uDRVal]
1900 mov dr1, eax
1901# endif
1902 }
1903# endif
1904}
1905#endif
1906
1907
1908/**
1909 * Sets dr2.
1910 *
1911 * @param uDRVal Debug register value to write
1912 */
1913#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1914DECLASM(void) ASMSetDR2(RTCCUINTREG uDRVal);
1915#else
1916DECLINLINE(void) ASMSetDR2(RTCCUINTREG uDRVal)
1917{
1918# if RT_INLINE_ASM_USES_INTRIN
1919 __writedr(2, uDRVal);
1920# elif RT_INLINE_ASM_GNU_STYLE
1921# ifdef RT_ARCH_AMD64
1922 __asm__ __volatile__("movq %0, %%dr2\n\t" : : "r" (uDRVal));
1923# else
1924 __asm__ __volatile__("movl %0, %%dr2\n\t" : : "r" (uDRVal));
1925# endif
1926# else
1927 __asm
1928 {
1929# ifdef RT_ARCH_AMD64
1930 mov rax, [uDRVal]
1931 mov dr2, rax
1932# else
1933 mov eax, [uDRVal]
1934 mov dr2, eax
1935# endif
1936 }
1937# endif
1938}
1939#endif
1940
1941
1942/**
1943 * Sets dr3.
1944 *
1945 * @param uDRVal Debug register value to write
1946 */
1947#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1948DECLASM(void) ASMSetDR3(RTCCUINTREG uDRVal);
1949#else
1950DECLINLINE(void) ASMSetDR3(RTCCUINTREG uDRVal)
1951{
1952# if RT_INLINE_ASM_USES_INTRIN
1953 __writedr(3, uDRVal);
1954# elif RT_INLINE_ASM_GNU_STYLE
1955# ifdef RT_ARCH_AMD64
1956 __asm__ __volatile__("movq %0, %%dr3\n\t" : : "r" (uDRVal));
1957# else
1958 __asm__ __volatile__("movl %0, %%dr3\n\t" : : "r" (uDRVal));
1959# endif
1960# else
1961 __asm
1962 {
1963# ifdef RT_ARCH_AMD64
1964 mov rax, [uDRVal]
1965 mov dr3, rax
1966# else
1967 mov eax, [uDRVal]
1968 mov dr3, eax
1969# endif
1970 }
1971# endif
1972}
1973#endif
1974
1975
1976/**
1977 * Sets dr6.
1978 *
1979 * @param uDRVal Debug register value to write
1980 */
1981#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1982DECLASM(void) ASMSetDR6(RTCCUINTREG uDRVal);
1983#else
1984DECLINLINE(void) ASMSetDR6(RTCCUINTREG uDRVal)
1985{
1986# if RT_INLINE_ASM_USES_INTRIN
1987 __writedr(6, uDRVal);
1988# elif RT_INLINE_ASM_GNU_STYLE
1989# ifdef RT_ARCH_AMD64
1990 __asm__ __volatile__("movq %0, %%dr6\n\t" : : "r" (uDRVal));
1991# else
1992 __asm__ __volatile__("movl %0, %%dr6\n\t" : : "r" (uDRVal));
1993# endif
1994# else
1995 __asm
1996 {
1997# ifdef RT_ARCH_AMD64
1998 mov rax, [uDRVal]
1999 mov dr6, rax
2000# else
2001 mov eax, [uDRVal]
2002 mov dr6, eax
2003# endif
2004 }
2005# endif
2006}
2007#endif
2008
2009
2010/**
2011 * Sets dr7.
2012 *
2013 * @param uDRVal Debug register value to write
2014 */
2015#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2016DECLASM(void) ASMSetDR7(RTCCUINTREG uDRVal);
2017#else
2018DECLINLINE(void) ASMSetDR7(RTCCUINTREG uDRVal)
2019{
2020# if RT_INLINE_ASM_USES_INTRIN
2021 __writedr(7, uDRVal);
2022# elif RT_INLINE_ASM_GNU_STYLE
2023# ifdef RT_ARCH_AMD64
2024 __asm__ __volatile__("movq %0, %%dr7\n\t" : : "r" (uDRVal));
2025# else
2026 __asm__ __volatile__("movl %0, %%dr7\n\t" : : "r" (uDRVal));
2027# endif
2028# else
2029 __asm
2030 {
2031# ifdef RT_ARCH_AMD64
2032 mov rax, [uDRVal]
2033 mov dr7, rax
2034# else
2035 mov eax, [uDRVal]
2036 mov dr7, eax
2037# endif
2038 }
2039# endif
2040}
2041#endif
2042
2043
2044/**
2045 * Writes a 8-bit unsigned integer to an I/O port, ordered.
2046 *
2047 * @param Port I/O port to write to.
2048 * @param u8 8-bit integer to write.
2049 */
2050#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2051DECLASM(void) ASMOutU8(RTIOPORT Port, uint8_t u8);
2052#else
2053DECLINLINE(void) ASMOutU8(RTIOPORT Port, uint8_t u8)
2054{
2055# if RT_INLINE_ASM_GNU_STYLE
2056 __asm__ __volatile__("outb %b1, %w0\n\t"
2057 :: "Nd" (Port),
2058 "a" (u8));
2059
2060# elif RT_INLINE_ASM_USES_INTRIN
2061 __outbyte(Port, u8);
2062
2063# else
2064 __asm
2065 {
2066 mov dx, [Port]
2067 mov al, [u8]
2068 out dx, al
2069 }
2070# endif
2071}
2072#endif
2073
2074
2075/**
2076 * Reads a 8-bit unsigned integer from an I/O port, ordered.
2077 *
2078 * @returns 8-bit integer.
2079 * @param Port I/O port to read from.
2080 */
2081#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2082DECLASM(uint8_t) ASMInU8(RTIOPORT Port);
2083#else
2084DECLINLINE(uint8_t) ASMInU8(RTIOPORT Port)
2085{
2086 uint8_t u8;
2087# if RT_INLINE_ASM_GNU_STYLE
2088 __asm__ __volatile__("inb %w1, %b0\n\t"
2089 : "=a" (u8)
2090 : "Nd" (Port));
2091
2092# elif RT_INLINE_ASM_USES_INTRIN
2093 u8 = __inbyte(Port);
2094
2095# else
2096 __asm
2097 {
2098 mov dx, [Port]
2099 in al, dx
2100 mov [u8], al
2101 }
2102# endif
2103 return u8;
2104}
2105#endif
2106
2107
2108/**
2109 * Writes a 16-bit unsigned integer to an I/O port, ordered.
2110 *
2111 * @param Port I/O port to write to.
2112 * @param u16 16-bit integer to write.
2113 */
2114#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2115DECLASM(void) ASMOutU16(RTIOPORT Port, uint16_t u16);
2116#else
2117DECLINLINE(void) ASMOutU16(RTIOPORT Port, uint16_t u16)
2118{
2119# if RT_INLINE_ASM_GNU_STYLE
2120 __asm__ __volatile__("outw %w1, %w0\n\t"
2121 :: "Nd" (Port),
2122 "a" (u16));
2123
2124# elif RT_INLINE_ASM_USES_INTRIN
2125 __outword(Port, u16);
2126
2127# else
2128 __asm
2129 {
2130 mov dx, [Port]
2131 mov ax, [u16]
2132 out dx, ax
2133 }
2134# endif
2135}
2136#endif
2137
2138
2139/**
2140 * Reads a 16-bit unsigned integer from an I/O port, ordered.
2141 *
2142 * @returns 16-bit integer.
2143 * @param Port I/O port to read from.
2144 */
2145#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2146DECLASM(uint16_t) ASMInU16(RTIOPORT Port);
2147#else
2148DECLINLINE(uint16_t) ASMInU16(RTIOPORT Port)
2149{
2150 uint16_t u16;
2151# if RT_INLINE_ASM_GNU_STYLE
2152 __asm__ __volatile__("inw %w1, %w0\n\t"
2153 : "=a" (u16)
2154 : "Nd" (Port));
2155
2156# elif RT_INLINE_ASM_USES_INTRIN
2157 u16 = __inword(Port);
2158
2159# else
2160 __asm
2161 {
2162 mov dx, [Port]
2163 in ax, dx
2164 mov [u16], ax
2165 }
2166# endif
2167 return u16;
2168}
2169#endif
2170
2171
2172/**
2173 * Writes a 32-bit unsigned integer to an I/O port, ordered.
2174 *
2175 * @param Port I/O port to write to.
2176 * @param u32 32-bit integer to write.
2177 */
2178#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2179DECLASM(void) ASMOutU32(RTIOPORT Port, uint32_t u32);
2180#else
2181DECLINLINE(void) ASMOutU32(RTIOPORT Port, uint32_t u32)
2182{
2183# if RT_INLINE_ASM_GNU_STYLE
2184 __asm__ __volatile__("outl %1, %w0\n\t"
2185 :: "Nd" (Port),
2186 "a" (u32));
2187
2188# elif RT_INLINE_ASM_USES_INTRIN
2189 __outdword(Port, u32);
2190
2191# else
2192 __asm
2193 {
2194 mov dx, [Port]
2195 mov eax, [u32]
2196 out dx, eax
2197 }
2198# endif
2199}
2200#endif
2201
2202
2203/**
2204 * Reads a 32-bit unsigned integer from an I/O port, ordered.
2205 *
2206 * @returns 32-bit integer.
2207 * @param Port I/O port to read from.
2208 */
2209#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2210DECLASM(uint32_t) ASMInU32(RTIOPORT Port);
2211#else
2212DECLINLINE(uint32_t) ASMInU32(RTIOPORT Port)
2213{
2214 uint32_t u32;
2215# if RT_INLINE_ASM_GNU_STYLE
2216 __asm__ __volatile__("inl %w1, %0\n\t"
2217 : "=a" (u32)
2218 : "Nd" (Port));
2219
2220# elif RT_INLINE_ASM_USES_INTRIN
2221 u32 = __indword(Port);
2222
2223# else
2224 __asm
2225 {
2226 mov dx, [Port]
2227 in eax, dx
2228 mov [u32], eax
2229 }
2230# endif
2231 return u32;
2232}
2233#endif
2234
2235
2236/**
2237 * Writes a string of 8-bit unsigned integer items to an I/O port, ordered.
2238 *
2239 * @param Port I/O port to write to.
2240 * @param pau8 Pointer to the string buffer.
2241 * @param c The number of items to write.
2242 */
2243#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2244DECLASM(void) ASMOutStrU8(RTIOPORT Port, uint8_t const *pau8, size_t c);
2245#else
2246DECLINLINE(void) ASMOutStrU8(RTIOPORT Port, uint8_t const *pau8, size_t c)
2247{
2248# if RT_INLINE_ASM_GNU_STYLE
2249 __asm__ __volatile__("rep; outsb\n\t"
2250 : "+S" (pau8),
2251 "+c" (c)
2252 : "d" (Port));
2253
2254# elif RT_INLINE_ASM_USES_INTRIN
2255 __outbytestring(Port, (unsigned char *)pau8, (unsigned long)c);
2256
2257# else
2258 __asm
2259 {
2260 mov dx, [Port]
2261 mov ecx, [c]
2262 mov eax, [pau8]
2263 xchg esi, eax
2264 rep outsb
2265 xchg esi, eax
2266 }
2267# endif
2268}
2269#endif
2270
2271
2272/**
2273 * Reads a string of 8-bit unsigned integer items from an I/O port, ordered.
2274 *
2275 * @param Port I/O port to read from.
2276 * @param pau8 Pointer to the string buffer (output).
2277 * @param c The number of items to read.
2278 */
2279#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2280DECLASM(void) ASMInStrU8(RTIOPORT Port, uint8_t *pau8, size_t c);
2281#else
2282DECLINLINE(void) ASMInStrU8(RTIOPORT Port, uint8_t *pau8, size_t c)
2283{
2284# if RT_INLINE_ASM_GNU_STYLE
2285 __asm__ __volatile__("rep; insb\n\t"
2286 : "+D" (pau8),
2287 "+c" (c)
2288 : "d" (Port));
2289
2290# elif RT_INLINE_ASM_USES_INTRIN
2291 __inbytestring(Port, pau8, (unsigned long)c);
2292
2293# else
2294 __asm
2295 {
2296 mov dx, [Port]
2297 mov ecx, [c]
2298 mov eax, [pau8]
2299 xchg edi, eax
2300 rep insb
2301 xchg edi, eax
2302 }
2303# endif
2304}
2305#endif
2306
2307
2308/**
2309 * Writes a string of 16-bit unsigned integer items to an I/O port, ordered.
2310 *
2311 * @param Port I/O port to write to.
2312 * @param pau16 Pointer to the string buffer.
2313 * @param c The number of items to write.
2314 */
2315#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2316DECLASM(void) ASMOutStrU16(RTIOPORT Port, uint16_t const *pau16, size_t c);
2317#else
2318DECLINLINE(void) ASMOutStrU16(RTIOPORT Port, uint16_t const *pau16, size_t c)
2319{
2320# if RT_INLINE_ASM_GNU_STYLE
2321 __asm__ __volatile__("rep; outsw\n\t"
2322 : "+S" (pau16),
2323 "+c" (c)
2324 : "d" (Port));
2325
2326# elif RT_INLINE_ASM_USES_INTRIN
2327 __outwordstring(Port, (unsigned short *)pau16, (unsigned long)c);
2328
2329# else
2330 __asm
2331 {
2332 mov dx, [Port]
2333 mov ecx, [c]
2334 mov eax, [pau16]
2335 xchg esi, eax
2336 rep outsw
2337 xchg esi, eax
2338 }
2339# endif
2340}
2341#endif
2342
2343
2344/**
2345 * Reads a string of 16-bit unsigned integer items from an I/O port, ordered.
2346 *
2347 * @param Port I/O port to read from.
2348 * @param pau16 Pointer to the string buffer (output).
2349 * @param c The number of items to read.
2350 */
2351#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2352DECLASM(void) ASMInStrU16(RTIOPORT Port, uint16_t *pau16, size_t c);
2353#else
2354DECLINLINE(void) ASMInStrU16(RTIOPORT Port, uint16_t *pau16, size_t c)
2355{
2356# if RT_INLINE_ASM_GNU_STYLE
2357 __asm__ __volatile__("rep; insw\n\t"
2358 : "+D" (pau16),
2359 "+c" (c)
2360 : "d" (Port));
2361
2362# elif RT_INLINE_ASM_USES_INTRIN
2363 __inwordstring(Port, pau16, (unsigned long)c);
2364
2365# else
2366 __asm
2367 {
2368 mov dx, [Port]
2369 mov ecx, [c]
2370 mov eax, [pau16]
2371 xchg edi, eax
2372 rep insw
2373 xchg edi, eax
2374 }
2375# endif
2376}
2377#endif
2378
2379
2380/**
2381 * Writes a string of 32-bit unsigned integer items to an I/O port, ordered.
2382 *
2383 * @param Port I/O port to write to.
2384 * @param pau32 Pointer to the string buffer.
2385 * @param c The number of items to write.
2386 */
2387#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2388DECLASM(void) ASMOutStrU32(RTIOPORT Port, uint32_t const *pau32, size_t c);
2389#else
2390DECLINLINE(void) ASMOutStrU32(RTIOPORT Port, uint32_t const *pau32, size_t c)
2391{
2392# if RT_INLINE_ASM_GNU_STYLE
2393 __asm__ __volatile__("rep; outsl\n\t"
2394 : "+S" (pau32),
2395 "+c" (c)
2396 : "d" (Port));
2397
2398# elif RT_INLINE_ASM_USES_INTRIN
2399 __outdwordstring(Port, (unsigned long *)pau32, (unsigned long)c);
2400
2401# else
2402 __asm
2403 {
2404 mov dx, [Port]
2405 mov ecx, [c]
2406 mov eax, [pau32]
2407 xchg esi, eax
2408 rep outsd
2409 xchg esi, eax
2410 }
2411# endif
2412}
2413#endif
2414
2415
2416/**
2417 * Reads a string of 32-bit unsigned integer items from an I/O port, ordered.
2418 *
2419 * @param Port I/O port to read from.
2420 * @param pau32 Pointer to the string buffer (output).
2421 * @param c The number of items to read.
2422 */
2423#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2424DECLASM(void) ASMInStrU32(RTIOPORT Port, uint32_t *pau32, size_t c);
2425#else
2426DECLINLINE(void) ASMInStrU32(RTIOPORT Port, uint32_t *pau32, size_t c)
2427{
2428# if RT_INLINE_ASM_GNU_STYLE
2429 __asm__ __volatile__("rep; insl\n\t"
2430 : "+D" (pau32),
2431 "+c" (c)
2432 : "d" (Port));
2433
2434# elif RT_INLINE_ASM_USES_INTRIN
2435 __indwordstring(Port, (unsigned long *)pau32, (unsigned long)c);
2436
2437# else
2438 __asm
2439 {
2440 mov dx, [Port]
2441 mov ecx, [c]
2442 mov eax, [pau32]
2443 xchg edi, eax
2444 rep insd
2445 xchg edi, eax
2446 }
2447# endif
2448}
2449#endif
2450
2451
2452/**
2453 * Invalidate page.
2454 *
2455 * @param pv Address of the page to invalidate.
2456 */
2457#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2458DECLASM(void) ASMInvalidatePage(void *pv);
2459#else
2460DECLINLINE(void) ASMInvalidatePage(void *pv)
2461{
2462# if RT_INLINE_ASM_USES_INTRIN
2463 __invlpg(pv);
2464
2465# elif RT_INLINE_ASM_GNU_STYLE
2466 __asm__ __volatile__("invlpg %0\n\t"
2467 : : "m" (*(uint8_t *)pv));
2468# else
2469 __asm
2470 {
2471# ifdef RT_ARCH_AMD64
2472 mov rax, [pv]
2473 invlpg [rax]
2474# else
2475 mov eax, [pv]
2476 invlpg [eax]
2477# endif
2478 }
2479# endif
2480}
2481#endif
2482
2483
2484/**
2485 * Write back the internal caches and invalidate them.
2486 */
2487#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2488DECLASM(void) ASMWriteBackAndInvalidateCaches(void);
2489#else
2490DECLINLINE(void) ASMWriteBackAndInvalidateCaches(void)
2491{
2492# if RT_INLINE_ASM_USES_INTRIN
2493 __wbinvd();
2494
2495# elif RT_INLINE_ASM_GNU_STYLE
2496 __asm__ __volatile__("wbinvd");
2497# else
2498 __asm
2499 {
2500 wbinvd
2501 }
2502# endif
2503}
2504#endif
2505
2506
2507/**
2508 * Invalidate internal and (perhaps) external caches without first
2509 * flushing dirty cache lines. Use with extreme care.
2510 */
2511#if RT_INLINE_ASM_EXTERNAL
2512DECLASM(void) ASMInvalidateInternalCaches(void);
2513#else
2514DECLINLINE(void) ASMInvalidateInternalCaches(void)
2515{
2516# if RT_INLINE_ASM_GNU_STYLE
2517 __asm__ __volatile__("invd");
2518# else
2519 __asm
2520 {
2521 invd
2522 }
2523# endif
2524}
2525#endif
2526
2527
2528/**
2529 * Memory load/store fence, waits for any pending writes and reads to complete.
2530 * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.
2531 */
2532DECLINLINE(void) ASMMemoryFenceSSE2(void)
2533{
2534#if RT_INLINE_ASM_GNU_STYLE
2535 __asm__ __volatile__ (".byte 0x0f,0xae,0xf0\n\t");
2536#elif RT_INLINE_ASM_USES_INTRIN
2537 _mm_mfence();
2538#else
2539 __asm
2540 {
2541 _emit 0x0f
2542 _emit 0xae
2543 _emit 0xf0
2544 }
2545#endif
2546}
2547
2548
2549/**
2550 * Memory store fence, waits for any writes to complete.
2551 * Requires the X86_CPUID_FEATURE_EDX_SSE CPUID bit set.
2552 */
2553DECLINLINE(void) ASMWriteFenceSSE(void)
2554{
2555#if RT_INLINE_ASM_GNU_STYLE
2556 __asm__ __volatile__ (".byte 0x0f,0xae,0xf8\n\t");
2557#elif RT_INLINE_ASM_USES_INTRIN
2558 _mm_sfence();
2559#else
2560 __asm
2561 {
2562 _emit 0x0f
2563 _emit 0xae
2564 _emit 0xf8
2565 }
2566#endif
2567}
2568
2569
2570/**
2571 * Memory load fence, waits for any pending reads to complete.
2572 * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.
2573 */
2574DECLINLINE(void) ASMReadFenceSSE2(void)
2575{
2576#if RT_INLINE_ASM_GNU_STYLE
2577 __asm__ __volatile__ (".byte 0x0f,0xae,0xe8\n\t");
2578#elif RT_INLINE_ASM_USES_INTRIN
2579 _mm_lfence();
2580#else
2581 __asm
2582 {
2583 _emit 0x0f
2584 _emit 0xae
2585 _emit 0xe8
2586 }
2587#endif
2588}
2589
2590/** @} */
2591#endif
2592
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