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source: vbox/trunk/include/iprt/asm-amd64-x86.h@ 50003

Last change on this file since 50003 was 49845, checked in by vboxsync, 11 years ago

Adding ASMWrMsrEx and ASMRdMSrEx.
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File size: 63.3 KB
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1/** @file
2 * IPRT - AMD64 and x86 Specific Assembly Functions.
3 */
4
5/*
6 * Copyright (C) 2006-2013 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___iprt_asm_amd64_x86_h
27#define ___iprt_asm_amd64_x86_h
28
29#include <iprt/types.h>
30#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
31# error "Not on AMD64 or x86"
32#endif
33
34#if defined(_MSC_VER) && RT_INLINE_ASM_USES_INTRIN
35# include <intrin.h>
36 /* Emit the intrinsics at all optimization levels. */
37# pragma intrinsic(_ReadWriteBarrier)
38# pragma intrinsic(__cpuid)
39# pragma intrinsic(_enable)
40# pragma intrinsic(_disable)
41# pragma intrinsic(__rdtsc)
42# pragma intrinsic(__readmsr)
43# pragma intrinsic(__writemsr)
44# pragma intrinsic(__outbyte)
45# pragma intrinsic(__outbytestring)
46# pragma intrinsic(__outword)
47# pragma intrinsic(__outwordstring)
48# pragma intrinsic(__outdword)
49# pragma intrinsic(__outdwordstring)
50# pragma intrinsic(__inbyte)
51# pragma intrinsic(__inbytestring)
52# pragma intrinsic(__inword)
53# pragma intrinsic(__inwordstring)
54# pragma intrinsic(__indword)
55# pragma intrinsic(__indwordstring)
56# pragma intrinsic(__invlpg)
57# pragma intrinsic(__wbinvd)
58# pragma intrinsic(__readcr0)
59# pragma intrinsic(__readcr2)
60# pragma intrinsic(__readcr3)
61# pragma intrinsic(__readcr4)
62# pragma intrinsic(__writecr0)
63# pragma intrinsic(__writecr3)
64# pragma intrinsic(__writecr4)
65# pragma intrinsic(__readdr)
66# pragma intrinsic(__writedr)
67# ifdef RT_ARCH_AMD64
68# pragma intrinsic(__readcr8)
69# pragma intrinsic(__writecr8)
70# endif
71# if RT_INLINE_ASM_USES_INTRIN >= 15
72# pragma intrinsic(__readeflags)
73# pragma intrinsic(__writeeflags)
74# endif
75#endif
76
77
78
79/** @defgroup grp_rt_asm_amd64_x86 AMD64 and x86 Specific ASM Routines
80 * @ingroup grp_rt_asm
81 * @{
82 */
83
84/** @todo find a more proper place for this structure? */
85#pragma pack(1)
86/** IDTR */
87typedef struct RTIDTR
88{
89 /** Size of the IDT. */
90 uint16_t cbIdt;
91 /** Address of the IDT. */
92 uintptr_t pIdt;
93} RTIDTR, *PRTIDTR;
94#pragma pack()
95
96#pragma pack(1)
97/** GDTR */
98typedef struct RTGDTR
99{
100 /** Size of the GDT. */
101 uint16_t cbGdt;
102 /** Address of the GDT. */
103 uintptr_t pGdt;
104} RTGDTR, *PRTGDTR;
105#pragma pack()
106
107
108/**
109 * Gets the content of the IDTR CPU register.
110 * @param pIdtr Where to store the IDTR contents.
111 */
112#if RT_INLINE_ASM_EXTERNAL
113DECLASM(void) ASMGetIDTR(PRTIDTR pIdtr);
114#else
115DECLINLINE(void) ASMGetIDTR(PRTIDTR pIdtr)
116{
117# if RT_INLINE_ASM_GNU_STYLE
118 __asm__ __volatile__("sidt %0" : "=m" (*pIdtr));
119# else
120 __asm
121 {
122# ifdef RT_ARCH_AMD64
123 mov rax, [pIdtr]
124 sidt [rax]
125# else
126 mov eax, [pIdtr]
127 sidt [eax]
128# endif
129 }
130# endif
131}
132#endif
133
134
135/**
136 * Sets the content of the IDTR CPU register.
137 * @param pIdtr Where to load the IDTR contents from
138 */
139#if RT_INLINE_ASM_EXTERNAL
140DECLASM(void) ASMSetIDTR(const RTIDTR *pIdtr);
141#else
142DECLINLINE(void) ASMSetIDTR(const RTIDTR *pIdtr)
143{
144# if RT_INLINE_ASM_GNU_STYLE
145 __asm__ __volatile__("lidt %0" : : "m" (*pIdtr));
146# else
147 __asm
148 {
149# ifdef RT_ARCH_AMD64
150 mov rax, [pIdtr]
151 lidt [rax]
152# else
153 mov eax, [pIdtr]
154 lidt [eax]
155# endif
156 }
157# endif
158}
159#endif
160
161
162/**
163 * Gets the content of the GDTR CPU register.
164 * @param pGdtr Where to store the GDTR contents.
165 */
166#if RT_INLINE_ASM_EXTERNAL
167DECLASM(void) ASMGetGDTR(PRTGDTR pGdtr);
168#else
169DECLINLINE(void) ASMGetGDTR(PRTGDTR pGdtr)
170{
171# if RT_INLINE_ASM_GNU_STYLE
172 __asm__ __volatile__("sgdt %0" : "=m" (*pGdtr));
173# else
174 __asm
175 {
176# ifdef RT_ARCH_AMD64
177 mov rax, [pGdtr]
178 sgdt [rax]
179# else
180 mov eax, [pGdtr]
181 sgdt [eax]
182# endif
183 }
184# endif
185}
186#endif
187
188/**
189 * Get the cs register.
190 * @returns cs.
191 */
192#if RT_INLINE_ASM_EXTERNAL
193DECLASM(RTSEL) ASMGetCS(void);
194#else
195DECLINLINE(RTSEL) ASMGetCS(void)
196{
197 RTSEL SelCS;
198# if RT_INLINE_ASM_GNU_STYLE
199 __asm__ __volatile__("movw %%cs, %0\n\t" : "=r" (SelCS));
200# else
201 __asm
202 {
203 mov ax, cs
204 mov [SelCS], ax
205 }
206# endif
207 return SelCS;
208}
209#endif
210
211
212/**
213 * Get the DS register.
214 * @returns DS.
215 */
216#if RT_INLINE_ASM_EXTERNAL
217DECLASM(RTSEL) ASMGetDS(void);
218#else
219DECLINLINE(RTSEL) ASMGetDS(void)
220{
221 RTSEL SelDS;
222# if RT_INLINE_ASM_GNU_STYLE
223 __asm__ __volatile__("movw %%ds, %0\n\t" : "=r" (SelDS));
224# else
225 __asm
226 {
227 mov ax, ds
228 mov [SelDS], ax
229 }
230# endif
231 return SelDS;
232}
233#endif
234
235
236/**
237 * Get the ES register.
238 * @returns ES.
239 */
240#if RT_INLINE_ASM_EXTERNAL
241DECLASM(RTSEL) ASMGetES(void);
242#else
243DECLINLINE(RTSEL) ASMGetES(void)
244{
245 RTSEL SelES;
246# if RT_INLINE_ASM_GNU_STYLE
247 __asm__ __volatile__("movw %%es, %0\n\t" : "=r" (SelES));
248# else
249 __asm
250 {
251 mov ax, es
252 mov [SelES], ax
253 }
254# endif
255 return SelES;
256}
257#endif
258
259
260/**
261 * Get the FS register.
262 * @returns FS.
263 */
264#if RT_INLINE_ASM_EXTERNAL
265DECLASM(RTSEL) ASMGetFS(void);
266#else
267DECLINLINE(RTSEL) ASMGetFS(void)
268{
269 RTSEL SelFS;
270# if RT_INLINE_ASM_GNU_STYLE
271 __asm__ __volatile__("movw %%fs, %0\n\t" : "=r" (SelFS));
272# else
273 __asm
274 {
275 mov ax, fs
276 mov [SelFS], ax
277 }
278# endif
279 return SelFS;
280}
281# endif
282
283
284/**
285 * Get the GS register.
286 * @returns GS.
287 */
288#if RT_INLINE_ASM_EXTERNAL
289DECLASM(RTSEL) ASMGetGS(void);
290#else
291DECLINLINE(RTSEL) ASMGetGS(void)
292{
293 RTSEL SelGS;
294# if RT_INLINE_ASM_GNU_STYLE
295 __asm__ __volatile__("movw %%gs, %0\n\t" : "=r" (SelGS));
296# else
297 __asm
298 {
299 mov ax, gs
300 mov [SelGS], ax
301 }
302# endif
303 return SelGS;
304}
305#endif
306
307
308/**
309 * Get the SS register.
310 * @returns SS.
311 */
312#if RT_INLINE_ASM_EXTERNAL
313DECLASM(RTSEL) ASMGetSS(void);
314#else
315DECLINLINE(RTSEL) ASMGetSS(void)
316{
317 RTSEL SelSS;
318# if RT_INLINE_ASM_GNU_STYLE
319 __asm__ __volatile__("movw %%ss, %0\n\t" : "=r" (SelSS));
320# else
321 __asm
322 {
323 mov ax, ss
324 mov [SelSS], ax
325 }
326# endif
327 return SelSS;
328}
329#endif
330
331
332/**
333 * Get the TR register.
334 * @returns TR.
335 */
336#if RT_INLINE_ASM_EXTERNAL
337DECLASM(RTSEL) ASMGetTR(void);
338#else
339DECLINLINE(RTSEL) ASMGetTR(void)
340{
341 RTSEL SelTR;
342# if RT_INLINE_ASM_GNU_STYLE
343 __asm__ __volatile__("str %w0\n\t" : "=r" (SelTR));
344# else
345 __asm
346 {
347 str ax
348 mov [SelTR], ax
349 }
350# endif
351 return SelTR;
352}
353#endif
354
355
356/**
357 * Get the LDTR register.
358 * @returns LDTR.
359 */
360#if RT_INLINE_ASM_EXTERNAL
361DECLASM(RTSEL) ASMGetLDTR(void);
362#else
363DECLINLINE(RTSEL) ASMGetLDTR(void)
364{
365 RTSEL SelLDTR;
366# if RT_INLINE_ASM_GNU_STYLE
367 __asm__ __volatile__("sldt %w0\n\t" : "=r" (SelLDTR));
368# else
369 __asm
370 {
371 sldt ax
372 mov [SelLDTR], ax
373 }
374# endif
375 return SelLDTR;
376}
377#endif
378
379
380/**
381 * Get the access rights for the segment selector.
382 *
383 * @returns The access rights on success or ~0U on failure.
384 * @param uSel The selector value.
385 *
386 * @remarks Using ~0U for failure is chosen because valid access rights always
387 * have bits 0:7 as 0 (on both Intel & AMD).
388 */
389#if RT_INLINE_ASM_EXTERNAL
390DECLASM(uint32_t) ASMGetSegAttr(uint32_t uSel);
391#else
392DECLINLINE(uint32_t) ASMGetSegAttr(uint32_t uSel)
393{
394 uint32_t uAttr;
395 /* LAR only accesses 16-bit of the source operand, but eax for the
396 destination operand is required for getting the full 32-bit access rights. */
397# if RT_INLINE_ASM_GNU_STYLE
398 __asm__ __volatile__("lar %1, %%eax\n\t"
399 "jz done%=\n\t"
400 "movl $0xffffffff, %%eax\n\t"
401 "done%=:\n\t"
402 "movl %%eax, %0\n\t"
403 : "=r" (uAttr)
404 : "r" (uSel)
405 : "cc", "%eax");
406# else
407 __asm
408 {
409 lar eax, [uSel]
410 jz done
411 mov eax, 0ffffffffh
412 done:
413 mov [uAttr], eax
414 }
415# endif
416 return uAttr;
417}
418#endif
419
420
421/**
422 * Get the [RE]FLAGS register.
423 * @returns [RE]FLAGS.
424 */
425#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
426DECLASM(RTCCUINTREG) ASMGetFlags(void);
427#else
428DECLINLINE(RTCCUINTREG) ASMGetFlags(void)
429{
430 RTCCUINTREG uFlags;
431# if RT_INLINE_ASM_GNU_STYLE
432# ifdef RT_ARCH_AMD64
433 __asm__ __volatile__("pushfq\n\t"
434 "popq %0\n\t"
435 : "=r" (uFlags));
436# else
437 __asm__ __volatile__("pushfl\n\t"
438 "popl %0\n\t"
439 : "=r" (uFlags));
440# endif
441# elif RT_INLINE_ASM_USES_INTRIN >= 15
442 uFlags = __readeflags();
443# else
444 __asm
445 {
446# ifdef RT_ARCH_AMD64
447 pushfq
448 pop [uFlags]
449# else
450 pushfd
451 pop [uFlags]
452# endif
453 }
454# endif
455 return uFlags;
456}
457#endif
458
459
460/**
461 * Set the [RE]FLAGS register.
462 * @param uFlags The new [RE]FLAGS value.
463 */
464#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
465DECLASM(void) ASMSetFlags(RTCCUINTREG uFlags);
466#else
467DECLINLINE(void) ASMSetFlags(RTCCUINTREG uFlags)
468{
469# if RT_INLINE_ASM_GNU_STYLE
470# ifdef RT_ARCH_AMD64
471 __asm__ __volatile__("pushq %0\n\t"
472 "popfq\n\t"
473 : : "g" (uFlags));
474# else
475 __asm__ __volatile__("pushl %0\n\t"
476 "popfl\n\t"
477 : : "g" (uFlags));
478# endif
479# elif RT_INLINE_ASM_USES_INTRIN >= 15
480 __writeeflags(uFlags);
481# else
482 __asm
483 {
484# ifdef RT_ARCH_AMD64
485 push [uFlags]
486 popfq
487# else
488 push [uFlags]
489 popfd
490# endif
491 }
492# endif
493}
494#endif
495
496
497/**
498 * Gets the content of the CPU timestamp counter register.
499 *
500 * @returns TSC.
501 */
502#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
503DECLASM(uint64_t) ASMReadTSC(void);
504#else
505DECLINLINE(uint64_t) ASMReadTSC(void)
506{
507 RTUINT64U u;
508# if RT_INLINE_ASM_GNU_STYLE
509 __asm__ __volatile__("rdtsc\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi));
510# else
511# if RT_INLINE_ASM_USES_INTRIN
512 u.u = __rdtsc();
513# else
514 __asm
515 {
516 rdtsc
517 mov [u.s.Lo], eax
518 mov [u.s.Hi], edx
519 }
520# endif
521# endif
522 return u.u;
523}
524#endif
525
526
527/**
528 * Performs the cpuid instruction returning all registers.
529 *
530 * @param uOperator CPUID operation (eax).
531 * @param pvEAX Where to store eax.
532 * @param pvEBX Where to store ebx.
533 * @param pvECX Where to store ecx.
534 * @param pvEDX Where to store edx.
535 * @remark We're using void pointers to ease the use of special bitfield structures and such.
536 */
537#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
538DECLASM(void) ASMCpuId(uint32_t uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
539#else
540DECLINLINE(void) ASMCpuId(uint32_t uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
541{
542# if RT_INLINE_ASM_GNU_STYLE
543# ifdef RT_ARCH_AMD64
544 RTCCUINTREG uRAX, uRBX, uRCX, uRDX;
545 __asm__ __volatile__ ("cpuid\n\t"
546 : "=a" (uRAX),
547 "=b" (uRBX),
548 "=c" (uRCX),
549 "=d" (uRDX)
550 : "0" (uOperator), "2" (0));
551 *(uint32_t *)pvEAX = (uint32_t)uRAX;
552 *(uint32_t *)pvEBX = (uint32_t)uRBX;
553 *(uint32_t *)pvECX = (uint32_t)uRCX;
554 *(uint32_t *)pvEDX = (uint32_t)uRDX;
555# else
556 __asm__ __volatile__ ("xchgl %%ebx, %1\n\t"
557 "cpuid\n\t"
558 "xchgl %%ebx, %1\n\t"
559 : "=a" (*(uint32_t *)pvEAX),
560 "=r" (*(uint32_t *)pvEBX),
561 "=c" (*(uint32_t *)pvECX),
562 "=d" (*(uint32_t *)pvEDX)
563 : "0" (uOperator), "2" (0));
564# endif
565
566# elif RT_INLINE_ASM_USES_INTRIN
567 int aInfo[4];
568 __cpuid(aInfo, uOperator);
569 *(uint32_t *)pvEAX = aInfo[0];
570 *(uint32_t *)pvEBX = aInfo[1];
571 *(uint32_t *)pvECX = aInfo[2];
572 *(uint32_t *)pvEDX = aInfo[3];
573
574# else
575 uint32_t uEAX;
576 uint32_t uEBX;
577 uint32_t uECX;
578 uint32_t uEDX;
579 __asm
580 {
581 push ebx
582 mov eax, [uOperator]
583 cpuid
584 mov [uEAX], eax
585 mov [uEBX], ebx
586 mov [uECX], ecx
587 mov [uEDX], edx
588 pop ebx
589 }
590 *(uint32_t *)pvEAX = uEAX;
591 *(uint32_t *)pvEBX = uEBX;
592 *(uint32_t *)pvECX = uECX;
593 *(uint32_t *)pvEDX = uEDX;
594# endif
595}
596#endif
597
598
599/**
600 * Performs the CPUID instruction with EAX and ECX input returning ALL output
601 * registers.
602 *
603 * @param uOperator CPUID operation (eax).
604 * @param uIdxECX ecx index
605 * @param pvEAX Where to store eax.
606 * @param pvEBX Where to store ebx.
607 * @param pvECX Where to store ecx.
608 * @param pvEDX Where to store edx.
609 * @remark We're using void pointers to ease the use of special bitfield structures and such.
610 */
611#if RT_INLINE_ASM_EXTERNAL || RT_INLINE_ASM_USES_INTRIN
612DECLASM(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
613#else
614DECLINLINE(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
615{
616# if RT_INLINE_ASM_GNU_STYLE
617# ifdef RT_ARCH_AMD64
618 RTCCUINTREG uRAX, uRBX, uRCX, uRDX;
619 __asm__ ("cpuid\n\t"
620 : "=a" (uRAX),
621 "=b" (uRBX),
622 "=c" (uRCX),
623 "=d" (uRDX)
624 : "0" (uOperator),
625 "2" (uIdxECX));
626 *(uint32_t *)pvEAX = (uint32_t)uRAX;
627 *(uint32_t *)pvEBX = (uint32_t)uRBX;
628 *(uint32_t *)pvECX = (uint32_t)uRCX;
629 *(uint32_t *)pvEDX = (uint32_t)uRDX;
630# else
631 __asm__ ("xchgl %%ebx, %1\n\t"
632 "cpuid\n\t"
633 "xchgl %%ebx, %1\n\t"
634 : "=a" (*(uint32_t *)pvEAX),
635 "=r" (*(uint32_t *)pvEBX),
636 "=c" (*(uint32_t *)pvECX),
637 "=d" (*(uint32_t *)pvEDX)
638 : "0" (uOperator),
639 "2" (uIdxECX));
640# endif
641
642# elif RT_INLINE_ASM_USES_INTRIN
643 int aInfo[4];
644 __cpuidex(aInfo, uOperator, uIdxECX);
645 *(uint32_t *)pvEAX = aInfo[0];
646 *(uint32_t *)pvEBX = aInfo[1];
647 *(uint32_t *)pvECX = aInfo[2];
648 *(uint32_t *)pvEDX = aInfo[3];
649
650# else
651 uint32_t uEAX;
652 uint32_t uEBX;
653 uint32_t uECX;
654 uint32_t uEDX;
655 __asm
656 {
657 push ebx
658 mov eax, [uOperator]
659 mov ecx, [uIdxECX]
660 cpuid
661 mov [uEAX], eax
662 mov [uEBX], ebx
663 mov [uECX], ecx
664 mov [uEDX], edx
665 pop ebx
666 }
667 *(uint32_t *)pvEAX = uEAX;
668 *(uint32_t *)pvEBX = uEBX;
669 *(uint32_t *)pvECX = uECX;
670 *(uint32_t *)pvEDX = uEDX;
671# endif
672}
673#endif
674
675
676/**
677 * CPUID variant that initializes all 4 registers before the CPUID instruction.
678 *
679 * @returns The EAX result value.
680 * @param uOperator CPUID operation (eax).
681 * @param uInitEBX The value to assign EBX prior to the CPUID instruction.
682 * @param uInitECX The value to assign ECX prior to the CPUID instruction.
683 * @param uInitEDX The value to assign EDX prior to the CPUID instruction.
684 * @param pvEAX Where to store eax. Optional.
685 * @param pvEBX Where to store ebx. Optional.
686 * @param pvECX Where to store ecx. Optional.
687 * @param pvEDX Where to store edx. Optional.
688 */
689DECLASM(uint32_t) ASMCpuIdExSlow(uint32_t uOperator, uint32_t uInitEBX, uint32_t uInitECX, uint32_t uInitEDX,
690 void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
691
692
693/**
694 * Performs the cpuid instruction returning ecx and edx.
695 *
696 * @param uOperator CPUID operation (eax).
697 * @param pvECX Where to store ecx.
698 * @param pvEDX Where to store edx.
699 * @remark We're using void pointers to ease the use of special bitfield structures and such.
700 */
701#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
702DECLASM(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void *pvECX, void *pvEDX);
703#else
704DECLINLINE(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void *pvECX, void *pvEDX)
705{
706 uint32_t uEBX;
707 ASMCpuId(uOperator, &uOperator, &uEBX, pvECX, pvEDX);
708}
709#endif
710
711
712/**
713 * Performs the cpuid instruction returning eax.
714 *
715 * @param uOperator CPUID operation (eax).
716 * @returns EAX after cpuid operation.
717 */
718#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
719DECLASM(uint32_t) ASMCpuId_EAX(uint32_t uOperator);
720#else
721DECLINLINE(uint32_t) ASMCpuId_EAX(uint32_t uOperator)
722{
723 RTCCUINTREG xAX;
724# if RT_INLINE_ASM_GNU_STYLE
725# ifdef RT_ARCH_AMD64
726 __asm__ ("cpuid"
727 : "=a" (xAX)
728 : "0" (uOperator)
729 : "rbx", "rcx", "rdx");
730# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
731 __asm__ ("push %%ebx\n\t"
732 "cpuid\n\t"
733 "pop %%ebx\n\t"
734 : "=a" (xAX)
735 : "0" (uOperator)
736 : "ecx", "edx");
737# else
738 __asm__ ("cpuid"
739 : "=a" (xAX)
740 : "0" (uOperator)
741 : "edx", "ecx", "ebx");
742# endif
743
744# elif RT_INLINE_ASM_USES_INTRIN
745 int aInfo[4];
746 __cpuid(aInfo, uOperator);
747 xAX = aInfo[0];
748
749# else
750 __asm
751 {
752 push ebx
753 mov eax, [uOperator]
754 cpuid
755 mov [xAX], eax
756 pop ebx
757 }
758# endif
759 return (uint32_t)xAX;
760}
761#endif
762
763
764/**
765 * Performs the cpuid instruction returning ebx.
766 *
767 * @param uOperator CPUID operation (eax).
768 * @returns EBX after cpuid operation.
769 */
770#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
771DECLASM(uint32_t) ASMCpuId_EBX(uint32_t uOperator);
772#else
773DECLINLINE(uint32_t) ASMCpuId_EBX(uint32_t uOperator)
774{
775 RTCCUINTREG xBX;
776# if RT_INLINE_ASM_GNU_STYLE
777# ifdef RT_ARCH_AMD64
778 RTCCUINTREG uSpill;
779 __asm__ ("cpuid"
780 : "=a" (uSpill),
781 "=b" (xBX)
782 : "0" (uOperator)
783 : "rdx", "rcx");
784# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
785 __asm__ ("push %%ebx\n\t"
786 "cpuid\n\t"
787 "mov %%ebx, %%edx\n\t"
788 "pop %%ebx\n\t"
789 : "=a" (uOperator),
790 "=d" (xBX)
791 : "0" (uOperator)
792 : "ecx");
793# else
794 __asm__ ("cpuid"
795 : "=a" (uOperator),
796 "=b" (xBX)
797 : "0" (uOperator)
798 : "edx", "ecx");
799# endif
800
801# elif RT_INLINE_ASM_USES_INTRIN
802 int aInfo[4];
803 __cpuid(aInfo, uOperator);
804 xBX = aInfo[1];
805
806# else
807 __asm
808 {
809 push ebx
810 mov eax, [uOperator]
811 cpuid
812 mov [xBX], ebx
813 pop ebx
814 }
815# endif
816 return (uint32_t)xBX;
817}
818#endif
819
820
821/**
822 * Performs the cpuid instruction returning ecx.
823 *
824 * @param uOperator CPUID operation (eax).
825 * @returns ECX after cpuid operation.
826 */
827#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
828DECLASM(uint32_t) ASMCpuId_ECX(uint32_t uOperator);
829#else
830DECLINLINE(uint32_t) ASMCpuId_ECX(uint32_t uOperator)
831{
832 RTCCUINTREG xCX;
833# if RT_INLINE_ASM_GNU_STYLE
834# ifdef RT_ARCH_AMD64
835 RTCCUINTREG uSpill;
836 __asm__ ("cpuid"
837 : "=a" (uSpill),
838 "=c" (xCX)
839 : "0" (uOperator)
840 : "rbx", "rdx");
841# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
842 __asm__ ("push %%ebx\n\t"
843 "cpuid\n\t"
844 "pop %%ebx\n\t"
845 : "=a" (uOperator),
846 "=c" (xCX)
847 : "0" (uOperator)
848 : "edx");
849# else
850 __asm__ ("cpuid"
851 : "=a" (uOperator),
852 "=c" (xCX)
853 : "0" (uOperator)
854 : "ebx", "edx");
855
856# endif
857
858# elif RT_INLINE_ASM_USES_INTRIN
859 int aInfo[4];
860 __cpuid(aInfo, uOperator);
861 xCX = aInfo[2];
862
863# else
864 __asm
865 {
866 push ebx
867 mov eax, [uOperator]
868 cpuid
869 mov [xCX], ecx
870 pop ebx
871 }
872# endif
873 return (uint32_t)xCX;
874}
875#endif
876
877
878/**
879 * Performs the cpuid instruction returning edx.
880 *
881 * @param uOperator CPUID operation (eax).
882 * @returns EDX after cpuid operation.
883 */
884#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
885DECLASM(uint32_t) ASMCpuId_EDX(uint32_t uOperator);
886#else
887DECLINLINE(uint32_t) ASMCpuId_EDX(uint32_t uOperator)
888{
889 RTCCUINTREG xDX;
890# if RT_INLINE_ASM_GNU_STYLE
891# ifdef RT_ARCH_AMD64
892 RTCCUINTREG uSpill;
893 __asm__ ("cpuid"
894 : "=a" (uSpill),
895 "=d" (xDX)
896 : "0" (uOperator)
897 : "rbx", "rcx");
898# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
899 __asm__ ("push %%ebx\n\t"
900 "cpuid\n\t"
901 "pop %%ebx\n\t"
902 : "=a" (uOperator),
903 "=d" (xDX)
904 : "0" (uOperator)
905 : "ecx");
906# else
907 __asm__ ("cpuid"
908 : "=a" (uOperator),
909 "=d" (xDX)
910 : "0" (uOperator)
911 : "ebx", "ecx");
912# endif
913
914# elif RT_INLINE_ASM_USES_INTRIN
915 int aInfo[4];
916 __cpuid(aInfo, uOperator);
917 xDX = aInfo[3];
918
919# else
920 __asm
921 {
922 push ebx
923 mov eax, [uOperator]
924 cpuid
925 mov [xDX], edx
926 pop ebx
927 }
928# endif
929 return (uint32_t)xDX;
930}
931#endif
932
933
934/**
935 * Checks if the current CPU supports CPUID.
936 *
937 * @returns true if CPUID is supported.
938 */
939DECLINLINE(bool) ASMHasCpuId(void)
940{
941#ifdef RT_ARCH_AMD64
942 return true; /* ASSUME that all amd64 compatible CPUs have cpuid. */
943#else /* !RT_ARCH_AMD64 */
944 bool fRet = false;
945# if RT_INLINE_ASM_GNU_STYLE
946 uint32_t u1;
947 uint32_t u2;
948 __asm__ ("pushf\n\t"
949 "pop %1\n\t"
950 "mov %1, %2\n\t"
951 "xorl $0x200000, %1\n\t"
952 "push %1\n\t"
953 "popf\n\t"
954 "pushf\n\t"
955 "pop %1\n\t"
956 "cmpl %1, %2\n\t"
957 "setne %0\n\t"
958 "push %2\n\t"
959 "popf\n\t"
960 : "=m" (fRet), "=r" (u1), "=r" (u2));
961# else
962 __asm
963 {
964 pushfd
965 pop eax
966 mov ebx, eax
967 xor eax, 0200000h
968 push eax
969 popfd
970 pushfd
971 pop eax
972 cmp eax, ebx
973 setne fRet
974 push ebx
975 popfd
976 }
977# endif
978 return fRet;
979#endif /* !RT_ARCH_AMD64 */
980}
981
982
983/**
984 * Gets the APIC ID of the current CPU.
985 *
986 * @returns the APIC ID.
987 */
988#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
989DECLASM(uint8_t) ASMGetApicId(void);
990#else
991DECLINLINE(uint8_t) ASMGetApicId(void)
992{
993 RTCCUINTREG xBX;
994# if RT_INLINE_ASM_GNU_STYLE
995# ifdef RT_ARCH_AMD64
996 RTCCUINTREG uSpill;
997 __asm__ __volatile__ ("cpuid"
998 : "=a" (uSpill),
999 "=b" (xBX)
1000 : "0" (1)
1001 : "rcx", "rdx");
1002# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1003 RTCCUINTREG uSpill;
1004 __asm__ __volatile__ ("mov %%ebx,%1\n\t"
1005 "cpuid\n\t"
1006 "xchgl %%ebx,%1\n\t"
1007 : "=a" (uSpill),
1008 "=rm" (xBX)
1009 : "0" (1)
1010 : "ecx", "edx");
1011# else
1012 RTCCUINTREG uSpill;
1013 __asm__ __volatile__ ("cpuid"
1014 : "=a" (uSpill),
1015 "=b" (xBX)
1016 : "0" (1)
1017 : "ecx", "edx");
1018# endif
1019
1020# elif RT_INLINE_ASM_USES_INTRIN
1021 int aInfo[4];
1022 __cpuid(aInfo, 1);
1023 xBX = aInfo[1];
1024
1025# else
1026 __asm
1027 {
1028 push ebx
1029 mov eax, 1
1030 cpuid
1031 mov [xBX], ebx
1032 pop ebx
1033 }
1034# endif
1035 return (uint8_t)(xBX >> 24);
1036}
1037#endif
1038
1039
1040/**
1041 * Tests if it a genuine Intel CPU based on the ASMCpuId(0) output.
1042 *
1043 * @returns true/false.
1044 * @param uEBX EBX return from ASMCpuId(0)
1045 * @param uECX ECX return from ASMCpuId(0)
1046 * @param uEDX EDX return from ASMCpuId(0)
1047 */
1048DECLINLINE(bool) ASMIsIntelCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1049{
1050 return uEBX == UINT32_C(0x756e6547)
1051 && uECX == UINT32_C(0x6c65746e)
1052 && uEDX == UINT32_C(0x49656e69);
1053}
1054
1055
1056/**
1057 * Tests if this is a genuine Intel CPU.
1058 *
1059 * @returns true/false.
1060 * @remarks ASSUMES that cpuid is supported by the CPU.
1061 */
1062DECLINLINE(bool) ASMIsIntelCpu(void)
1063{
1064 uint32_t uEAX, uEBX, uECX, uEDX;
1065 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1066 return ASMIsIntelCpuEx(uEBX, uECX, uEDX);
1067}
1068
1069
1070/**
1071 * Tests if it an authentic AMD CPU based on the ASMCpuId(0) output.
1072 *
1073 * @returns true/false.
1074 * @param uEBX EBX return from ASMCpuId(0)
1075 * @param uECX ECX return from ASMCpuId(0)
1076 * @param uEDX EDX return from ASMCpuId(0)
1077 */
1078DECLINLINE(bool) ASMIsAmdCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1079{
1080 return uEBX == UINT32_C(0x68747541)
1081 && uECX == UINT32_C(0x444d4163)
1082 && uEDX == UINT32_C(0x69746e65);
1083}
1084
1085
1086/**
1087 * Tests if this is an authentic AMD CPU.
1088 *
1089 * @returns true/false.
1090 * @remarks ASSUMES that cpuid is supported by the CPU.
1091 */
1092DECLINLINE(bool) ASMIsAmdCpu(void)
1093{
1094 uint32_t uEAX, uEBX, uECX, uEDX;
1095 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1096 return ASMIsAmdCpuEx(uEBX, uECX, uEDX);
1097}
1098
1099
1100/**
1101 * Tests if it a centaur hauling VIA CPU based on the ASMCpuId(0) output.
1102 *
1103 * @returns true/false.
1104 * @param uEBX EBX return from ASMCpuId(0).
1105 * @param uECX ECX return from ASMCpuId(0).
1106 * @param uEDX EDX return from ASMCpuId(0).
1107 */
1108DECLINLINE(bool) ASMIsViaCentaurCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1109{
1110 return uEBX == UINT32_C(0x746e6543)
1111 && uECX == UINT32_C(0x736c7561)
1112 && uEDX == UINT32_C(0x48727561);
1113}
1114
1115
1116/**
1117 * Tests if this is a centaur hauling VIA CPU.
1118 *
1119 * @returns true/false.
1120 * @remarks ASSUMES that cpuid is supported by the CPU.
1121 */
1122DECLINLINE(bool) ASMIsViaCentaurCpu(void)
1123{
1124 uint32_t uEAX, uEBX, uECX, uEDX;
1125 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1126 return ASMIsAmdCpuEx(uEBX, uECX, uEDX);
1127}
1128
1129
1130/**
1131 * Checks whether ASMCpuId_EAX(0x00000000) indicates a valid range.
1132 *
1133 *
1134 * @returns true/false.
1135 * @param uEAX The EAX value of CPUID leaf 0x00000000.
1136 *
1137 * @note This only succeeds if there are at least two leaves in the range.
1138 * @remarks The upper range limit is just some half reasonable value we've
1139 * picked out of thin air.
1140 */
1141DECLINLINE(bool) ASMIsValidStdRange(uint32_t uEAX)
1142{
1143 return uEAX >= UINT32_C(0x00000001) && uEAX <= UINT32_C(0x000fffff);
1144}
1145
1146
1147/**
1148 * Checks whether ASMCpuId_EAX(0x80000000) indicates a valid range.
1149 *
1150 * This only succeeds if there are at least two leaves in the range.
1151 *
1152 * @returns true/false.
1153 * @param uEAX The EAX value of CPUID leaf 0x80000000.
1154 *
1155 * @note This only succeeds if there are at least two leaves in the range.
1156 * @remarks The upper range limit is just some half reasonable value we've
1157 * picked out of thin air.
1158 */
1159DECLINLINE(bool) ASMIsValidExtRange(uint32_t uEAX)
1160{
1161 return uEAX >= UINT32_C(0x80000001) && uEAX <= UINT32_C(0x800fffff);
1162}
1163
1164
1165/**
1166 * Extracts the CPU family from ASMCpuId(1) or ASMCpuId(0x80000001)
1167 *
1168 * @returns Family.
1169 * @param uEAX EAX return from ASMCpuId(1) or ASMCpuId(0x80000001).
1170 */
1171DECLINLINE(uint32_t) ASMGetCpuFamily(uint32_t uEAX)
1172{
1173 return ((uEAX >> 8) & 0xf) == 0xf
1174 ? ((uEAX >> 20) & 0x7f) + 0xf
1175 : ((uEAX >> 8) & 0xf);
1176}
1177
1178
1179/**
1180 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), Intel variant.
1181 *
1182 * @returns Model.
1183 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1184 */
1185DECLINLINE(uint32_t) ASMGetCpuModelIntel(uint32_t uEAX)
1186{
1187 return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6) /* family! */
1188 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
1189 : ((uEAX >> 4) & 0xf);
1190}
1191
1192
1193/**
1194 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), AMD variant.
1195 *
1196 * @returns Model.
1197 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1198 */
1199DECLINLINE(uint32_t) ASMGetCpuModelAMD(uint32_t uEAX)
1200{
1201 return ((uEAX >> 8) & 0xf) == 0xf
1202 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
1203 : ((uEAX >> 4) & 0xf);
1204}
1205
1206
1207/**
1208 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001)
1209 *
1210 * @returns Model.
1211 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1212 * @param fIntel Whether it's an intel CPU. Use ASMIsIntelCpuEx() or ASMIsIntelCpu().
1213 */
1214DECLINLINE(uint32_t) ASMGetCpuModel(uint32_t uEAX, bool fIntel)
1215{
1216 return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6 && fIntel) /* family! */
1217 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
1218 : ((uEAX >> 4) & 0xf);
1219}
1220
1221
1222/**
1223 * Extracts the CPU stepping from ASMCpuId(1) or ASMCpuId(0x80000001)
1224 *
1225 * @returns Model.
1226 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1227 */
1228DECLINLINE(uint32_t) ASMGetCpuStepping(uint32_t uEAX)
1229{
1230 return uEAX & 0xf;
1231}
1232
1233
1234/**
1235 * Get cr0.
1236 * @returns cr0.
1237 */
1238#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1239DECLASM(RTCCUINTREG) ASMGetCR0(void);
1240#else
1241DECLINLINE(RTCCUINTREG) ASMGetCR0(void)
1242{
1243 RTCCUINTREG uCR0;
1244# if RT_INLINE_ASM_USES_INTRIN
1245 uCR0 = __readcr0();
1246
1247# elif RT_INLINE_ASM_GNU_STYLE
1248# ifdef RT_ARCH_AMD64
1249 __asm__ __volatile__("movq %%cr0, %0\t\n" : "=r" (uCR0));
1250# else
1251 __asm__ __volatile__("movl %%cr0, %0\t\n" : "=r" (uCR0));
1252# endif
1253# else
1254 __asm
1255 {
1256# ifdef RT_ARCH_AMD64
1257 mov rax, cr0
1258 mov [uCR0], rax
1259# else
1260 mov eax, cr0
1261 mov [uCR0], eax
1262# endif
1263 }
1264# endif
1265 return uCR0;
1266}
1267#endif
1268
1269
1270/**
1271 * Sets the CR0 register.
1272 * @param uCR0 The new CR0 value.
1273 */
1274#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1275DECLASM(void) ASMSetCR0(RTCCUINTREG uCR0);
1276#else
1277DECLINLINE(void) ASMSetCR0(RTCCUINTREG uCR0)
1278{
1279# if RT_INLINE_ASM_USES_INTRIN
1280 __writecr0(uCR0);
1281
1282# elif RT_INLINE_ASM_GNU_STYLE
1283# ifdef RT_ARCH_AMD64
1284 __asm__ __volatile__("movq %0, %%cr0\n\t" :: "r" (uCR0));
1285# else
1286 __asm__ __volatile__("movl %0, %%cr0\n\t" :: "r" (uCR0));
1287# endif
1288# else
1289 __asm
1290 {
1291# ifdef RT_ARCH_AMD64
1292 mov rax, [uCR0]
1293 mov cr0, rax
1294# else
1295 mov eax, [uCR0]
1296 mov cr0, eax
1297# endif
1298 }
1299# endif
1300}
1301#endif
1302
1303
1304/**
1305 * Get cr2.
1306 * @returns cr2.
1307 */
1308#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1309DECLASM(RTCCUINTREG) ASMGetCR2(void);
1310#else
1311DECLINLINE(RTCCUINTREG) ASMGetCR2(void)
1312{
1313 RTCCUINTREG uCR2;
1314# if RT_INLINE_ASM_USES_INTRIN
1315 uCR2 = __readcr2();
1316
1317# elif RT_INLINE_ASM_GNU_STYLE
1318# ifdef RT_ARCH_AMD64
1319 __asm__ __volatile__("movq %%cr2, %0\t\n" : "=r" (uCR2));
1320# else
1321 __asm__ __volatile__("movl %%cr2, %0\t\n" : "=r" (uCR2));
1322# endif
1323# else
1324 __asm
1325 {
1326# ifdef RT_ARCH_AMD64
1327 mov rax, cr2
1328 mov [uCR2], rax
1329# else
1330 mov eax, cr2
1331 mov [uCR2], eax
1332# endif
1333 }
1334# endif
1335 return uCR2;
1336}
1337#endif
1338
1339
1340/**
1341 * Sets the CR2 register.
1342 * @param uCR2 The new CR0 value.
1343 */
1344#if RT_INLINE_ASM_EXTERNAL
1345DECLASM(void) ASMSetCR2(RTCCUINTREG uCR2);
1346#else
1347DECLINLINE(void) ASMSetCR2(RTCCUINTREG uCR2)
1348{
1349# if RT_INLINE_ASM_GNU_STYLE
1350# ifdef RT_ARCH_AMD64
1351 __asm__ __volatile__("movq %0, %%cr2\n\t" :: "r" (uCR2));
1352# else
1353 __asm__ __volatile__("movl %0, %%cr2\n\t" :: "r" (uCR2));
1354# endif
1355# else
1356 __asm
1357 {
1358# ifdef RT_ARCH_AMD64
1359 mov rax, [uCR2]
1360 mov cr2, rax
1361# else
1362 mov eax, [uCR2]
1363 mov cr2, eax
1364# endif
1365 }
1366# endif
1367}
1368#endif
1369
1370
1371/**
1372 * Get cr3.
1373 * @returns cr3.
1374 */
1375#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1376DECLASM(RTCCUINTREG) ASMGetCR3(void);
1377#else
1378DECLINLINE(RTCCUINTREG) ASMGetCR3(void)
1379{
1380 RTCCUINTREG uCR3;
1381# if RT_INLINE_ASM_USES_INTRIN
1382 uCR3 = __readcr3();
1383
1384# elif RT_INLINE_ASM_GNU_STYLE
1385# ifdef RT_ARCH_AMD64
1386 __asm__ __volatile__("movq %%cr3, %0\t\n" : "=r" (uCR3));
1387# else
1388 __asm__ __volatile__("movl %%cr3, %0\t\n" : "=r" (uCR3));
1389# endif
1390# else
1391 __asm
1392 {
1393# ifdef RT_ARCH_AMD64
1394 mov rax, cr3
1395 mov [uCR3], rax
1396# else
1397 mov eax, cr3
1398 mov [uCR3], eax
1399# endif
1400 }
1401# endif
1402 return uCR3;
1403}
1404#endif
1405
1406
1407/**
1408 * Sets the CR3 register.
1409 *
1410 * @param uCR3 New CR3 value.
1411 */
1412#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1413DECLASM(void) ASMSetCR3(RTCCUINTREG uCR3);
1414#else
1415DECLINLINE(void) ASMSetCR3(RTCCUINTREG uCR3)
1416{
1417# if RT_INLINE_ASM_USES_INTRIN
1418 __writecr3(uCR3);
1419
1420# elif RT_INLINE_ASM_GNU_STYLE
1421# ifdef RT_ARCH_AMD64
1422 __asm__ __volatile__("movq %0, %%cr3\n\t" : : "r" (uCR3));
1423# else
1424 __asm__ __volatile__("movl %0, %%cr3\n\t" : : "r" (uCR3));
1425# endif
1426# else
1427 __asm
1428 {
1429# ifdef RT_ARCH_AMD64
1430 mov rax, [uCR3]
1431 mov cr3, rax
1432# else
1433 mov eax, [uCR3]
1434 mov cr3, eax
1435# endif
1436 }
1437# endif
1438}
1439#endif
1440
1441
1442/**
1443 * Reloads the CR3 register.
1444 */
1445#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1446DECLASM(void) ASMReloadCR3(void);
1447#else
1448DECLINLINE(void) ASMReloadCR3(void)
1449{
1450# if RT_INLINE_ASM_USES_INTRIN
1451 __writecr3(__readcr3());
1452
1453# elif RT_INLINE_ASM_GNU_STYLE
1454 RTCCUINTREG u;
1455# ifdef RT_ARCH_AMD64
1456 __asm__ __volatile__("movq %%cr3, %0\n\t"
1457 "movq %0, %%cr3\n\t"
1458 : "=r" (u));
1459# else
1460 __asm__ __volatile__("movl %%cr3, %0\n\t"
1461 "movl %0, %%cr3\n\t"
1462 : "=r" (u));
1463# endif
1464# else
1465 __asm
1466 {
1467# ifdef RT_ARCH_AMD64
1468 mov rax, cr3
1469 mov cr3, rax
1470# else
1471 mov eax, cr3
1472 mov cr3, eax
1473# endif
1474 }
1475# endif
1476}
1477#endif
1478
1479
1480/**
1481 * Get cr4.
1482 * @returns cr4.
1483 */
1484#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1485DECLASM(RTCCUINTREG) ASMGetCR4(void);
1486#else
1487DECLINLINE(RTCCUINTREG) ASMGetCR4(void)
1488{
1489 RTCCUINTREG uCR4;
1490# if RT_INLINE_ASM_USES_INTRIN
1491 uCR4 = __readcr4();
1492
1493# elif RT_INLINE_ASM_GNU_STYLE
1494# ifdef RT_ARCH_AMD64
1495 __asm__ __volatile__("movq %%cr4, %0\t\n" : "=r" (uCR4));
1496# else
1497 __asm__ __volatile__("movl %%cr4, %0\t\n" : "=r" (uCR4));
1498# endif
1499# else
1500 __asm
1501 {
1502# ifdef RT_ARCH_AMD64
1503 mov rax, cr4
1504 mov [uCR4], rax
1505# else
1506 push eax /* just in case */
1507 /*mov eax, cr4*/
1508 _emit 0x0f
1509 _emit 0x20
1510 _emit 0xe0
1511 mov [uCR4], eax
1512 pop eax
1513# endif
1514 }
1515# endif
1516 return uCR4;
1517}
1518#endif
1519
1520
1521/**
1522 * Sets the CR4 register.
1523 *
1524 * @param uCR4 New CR4 value.
1525 */
1526#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1527DECLASM(void) ASMSetCR4(RTCCUINTREG uCR4);
1528#else
1529DECLINLINE(void) ASMSetCR4(RTCCUINTREG uCR4)
1530{
1531# if RT_INLINE_ASM_USES_INTRIN
1532 __writecr4(uCR4);
1533
1534# elif RT_INLINE_ASM_GNU_STYLE
1535# ifdef RT_ARCH_AMD64
1536 __asm__ __volatile__("movq %0, %%cr4\n\t" : : "r" (uCR4));
1537# else
1538 __asm__ __volatile__("movl %0, %%cr4\n\t" : : "r" (uCR4));
1539# endif
1540# else
1541 __asm
1542 {
1543# ifdef RT_ARCH_AMD64
1544 mov rax, [uCR4]
1545 mov cr4, rax
1546# else
1547 mov eax, [uCR4]
1548 _emit 0x0F
1549 _emit 0x22
1550 _emit 0xE0 /* mov cr4, eax */
1551# endif
1552 }
1553# endif
1554}
1555#endif
1556
1557
1558/**
1559 * Get cr8.
1560 * @returns cr8.
1561 * @remark The lock prefix hack for access from non-64-bit modes is NOT used and 0 is returned.
1562 */
1563#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1564DECLASM(RTCCUINTREG) ASMGetCR8(void);
1565#else
1566DECLINLINE(RTCCUINTREG) ASMGetCR8(void)
1567{
1568# ifdef RT_ARCH_AMD64
1569 RTCCUINTREG uCR8;
1570# if RT_INLINE_ASM_USES_INTRIN
1571 uCR8 = __readcr8();
1572
1573# elif RT_INLINE_ASM_GNU_STYLE
1574 __asm__ __volatile__("movq %%cr8, %0\t\n" : "=r" (uCR8));
1575# else
1576 __asm
1577 {
1578 mov rax, cr8
1579 mov [uCR8], rax
1580 }
1581# endif
1582 return uCR8;
1583# else /* !RT_ARCH_AMD64 */
1584 return 0;
1585# endif /* !RT_ARCH_AMD64 */
1586}
1587#endif
1588
1589
1590/**
1591 * Enables interrupts (EFLAGS.IF).
1592 */
1593#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1594DECLASM(void) ASMIntEnable(void);
1595#else
1596DECLINLINE(void) ASMIntEnable(void)
1597{
1598# if RT_INLINE_ASM_GNU_STYLE
1599 __asm("sti\n");
1600# elif RT_INLINE_ASM_USES_INTRIN
1601 _enable();
1602# else
1603 __asm sti
1604# endif
1605}
1606#endif
1607
1608
1609/**
1610 * Disables interrupts (!EFLAGS.IF).
1611 */
1612#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1613DECLASM(void) ASMIntDisable(void);
1614#else
1615DECLINLINE(void) ASMIntDisable(void)
1616{
1617# if RT_INLINE_ASM_GNU_STYLE
1618 __asm("cli\n");
1619# elif RT_INLINE_ASM_USES_INTRIN
1620 _disable();
1621# else
1622 __asm cli
1623# endif
1624}
1625#endif
1626
1627
1628/**
1629 * Disables interrupts and returns previous xFLAGS.
1630 */
1631#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1632DECLASM(RTCCUINTREG) ASMIntDisableFlags(void);
1633#else
1634DECLINLINE(RTCCUINTREG) ASMIntDisableFlags(void)
1635{
1636 RTCCUINTREG xFlags;
1637# if RT_INLINE_ASM_GNU_STYLE
1638# ifdef RT_ARCH_AMD64
1639 __asm__ __volatile__("pushfq\n\t"
1640 "cli\n\t"
1641 "popq %0\n\t"
1642 : "=r" (xFlags));
1643# else
1644 __asm__ __volatile__("pushfl\n\t"
1645 "cli\n\t"
1646 "popl %0\n\t"
1647 : "=r" (xFlags));
1648# endif
1649# elif RT_INLINE_ASM_USES_INTRIN && !defined(RT_ARCH_X86)
1650 xFlags = ASMGetFlags();
1651 _disable();
1652# else
1653 __asm {
1654 pushfd
1655 cli
1656 pop [xFlags]
1657 }
1658# endif
1659 return xFlags;
1660}
1661#endif
1662
1663
1664/**
1665 * Are interrupts enabled?
1666 *
1667 * @returns true / false.
1668 */
1669DECLINLINE(RTCCUINTREG) ASMIntAreEnabled(void)
1670{
1671 RTCCUINTREG uFlags = ASMGetFlags();
1672 return uFlags & 0x200 /* X86_EFL_IF */ ? true : false;
1673}
1674
1675
1676/**
1677 * Halts the CPU until interrupted.
1678 */
1679#if RT_INLINE_ASM_EXTERNAL
1680DECLASM(void) ASMHalt(void);
1681#else
1682DECLINLINE(void) ASMHalt(void)
1683{
1684# if RT_INLINE_ASM_GNU_STYLE
1685 __asm__ __volatile__("hlt\n\t");
1686# else
1687 __asm {
1688 hlt
1689 }
1690# endif
1691}
1692#endif
1693
1694
1695/**
1696 * Reads a machine specific register.
1697 *
1698 * @returns Register content.
1699 * @param uRegister Register to read.
1700 */
1701#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1702DECLASM(uint64_t) ASMRdMsr(uint32_t uRegister);
1703#else
1704DECLINLINE(uint64_t) ASMRdMsr(uint32_t uRegister)
1705{
1706 RTUINT64U u;
1707# if RT_INLINE_ASM_GNU_STYLE
1708 __asm__ __volatile__("rdmsr\n\t"
1709 : "=a" (u.s.Lo),
1710 "=d" (u.s.Hi)
1711 : "c" (uRegister));
1712
1713# elif RT_INLINE_ASM_USES_INTRIN
1714 u.u = __readmsr(uRegister);
1715
1716# else
1717 __asm
1718 {
1719 mov ecx, [uRegister]
1720 rdmsr
1721 mov [u.s.Lo], eax
1722 mov [u.s.Hi], edx
1723 }
1724# endif
1725
1726 return u.u;
1727}
1728#endif
1729
1730
1731/**
1732 * Writes a machine specific register.
1733 *
1734 * @returns Register content.
1735 * @param uRegister Register to write to.
1736 * @param u64Val Value to write.
1737 */
1738#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1739DECLASM(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val);
1740#else
1741DECLINLINE(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val)
1742{
1743 RTUINT64U u;
1744
1745 u.u = u64Val;
1746# if RT_INLINE_ASM_GNU_STYLE
1747 __asm__ __volatile__("wrmsr\n\t"
1748 ::"a" (u.s.Lo),
1749 "d" (u.s.Hi),
1750 "c" (uRegister));
1751
1752# elif RT_INLINE_ASM_USES_INTRIN
1753 __writemsr(uRegister, u.u);
1754
1755# else
1756 __asm
1757 {
1758 mov ecx, [uRegister]
1759 mov edx, [u.s.Hi]
1760 mov eax, [u.s.Lo]
1761 wrmsr
1762 }
1763# endif
1764}
1765#endif
1766
1767
1768/**
1769 * Reads a machine specific register, extended version (for AMD).
1770 *
1771 * @returns Register content.
1772 * @param uRegister Register to read.
1773 * @param uXDI RDI/EDI value.
1774 */
1775#if RT_INLINE_ASM_EXTERNAL
1776DECLASM(uint64_t) ASMRdMsrEx(uint32_t uRegister, RTCCUINTREG uXDI);
1777#else
1778DECLINLINE(uint64_t) ASMRdMsrEx(uint32_t uRegister, RTCCUINTREG uXDI)
1779{
1780 RTUINT64U u;
1781# if RT_INLINE_ASM_GNU_STYLE
1782 __asm__ __volatile__("rdmsr\n\t"
1783 : "=a" (u.s.Lo),
1784 "=d" (u.s.Hi)
1785 : "c" (uRegister),
1786 "D" (uXDI));
1787
1788# else
1789 __asm
1790 {
1791 mov ecx, [uRegister]
1792 xchg edi, [uXDI]
1793 rdmsr
1794 mov [u.s.Lo], eax
1795 mov [u.s.Hi], edx
1796 xchg edi, [uXDI]
1797 }
1798# endif
1799
1800 return u.u;
1801}
1802#endif
1803
1804
1805/**
1806 * Writes a machine specific register, extended version (for AMD).
1807 *
1808 * @returns Register content.
1809 * @param uRegister Register to write to.
1810 * @param uXDI RDI/EDI value.
1811 * @param u64Val Value to write.
1812 */
1813#if RT_INLINE_ASM_EXTERNAL
1814DECLASM(void) ASMWrMsrEx(uint32_t uRegister, RTCCUINTREG uXDI, uint64_t u64Val);
1815#else
1816DECLINLINE(void) ASMWrMsrEx(uint32_t uRegister, RTCCUINTREG uXDI, uint64_t u64Val)
1817{
1818 RTUINT64U u;
1819
1820 u.u = u64Val;
1821# if RT_INLINE_ASM_GNU_STYLE
1822 __asm__ __volatile__("wrmsr\n\t"
1823 ::"a" (u.s.Lo),
1824 "d" (u.s.Hi),
1825 "c" (uRegister),
1826 "D" (uXDI));
1827
1828# else
1829 __asm
1830 {
1831 mov ecx, [uRegister]
1832 xchg edi, [uXDI]
1833 mov edx, [u.s.Hi]
1834 mov eax, [u.s.Lo]
1835 wrmsr
1836 xchg edi, [uXDI]
1837 }
1838# endif
1839}
1840#endif
1841
1842
1843
1844/**
1845 * Reads low part of a machine specific register.
1846 *
1847 * @returns Register content.
1848 * @param uRegister Register to read.
1849 */
1850#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1851DECLASM(uint32_t) ASMRdMsr_Low(uint32_t uRegister);
1852#else
1853DECLINLINE(uint32_t) ASMRdMsr_Low(uint32_t uRegister)
1854{
1855 uint32_t u32;
1856# if RT_INLINE_ASM_GNU_STYLE
1857 __asm__ __volatile__("rdmsr\n\t"
1858 : "=a" (u32)
1859 : "c" (uRegister)
1860 : "edx");
1861
1862# elif RT_INLINE_ASM_USES_INTRIN
1863 u32 = (uint32_t)__readmsr(uRegister);
1864
1865#else
1866 __asm
1867 {
1868 mov ecx, [uRegister]
1869 rdmsr
1870 mov [u32], eax
1871 }
1872# endif
1873
1874 return u32;
1875}
1876#endif
1877
1878
1879/**
1880 * Reads high part of a machine specific register.
1881 *
1882 * @returns Register content.
1883 * @param uRegister Register to read.
1884 */
1885#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1886DECLASM(uint32_t) ASMRdMsr_High(uint32_t uRegister);
1887#else
1888DECLINLINE(uint32_t) ASMRdMsr_High(uint32_t uRegister)
1889{
1890 uint32_t u32;
1891# if RT_INLINE_ASM_GNU_STYLE
1892 __asm__ __volatile__("rdmsr\n\t"
1893 : "=d" (u32)
1894 : "c" (uRegister)
1895 : "eax");
1896
1897# elif RT_INLINE_ASM_USES_INTRIN
1898 u32 = (uint32_t)(__readmsr(uRegister) >> 32);
1899
1900# else
1901 __asm
1902 {
1903 mov ecx, [uRegister]
1904 rdmsr
1905 mov [u32], edx
1906 }
1907# endif
1908
1909 return u32;
1910}
1911#endif
1912
1913
1914/**
1915 * Gets dr0.
1916 *
1917 * @returns dr0.
1918 */
1919#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1920DECLASM(RTCCUINTREG) ASMGetDR0(void);
1921#else
1922DECLINLINE(RTCCUINTREG) ASMGetDR0(void)
1923{
1924 RTCCUINTREG uDR0;
1925# if RT_INLINE_ASM_USES_INTRIN
1926 uDR0 = __readdr(0);
1927# elif RT_INLINE_ASM_GNU_STYLE
1928# ifdef RT_ARCH_AMD64
1929 __asm__ __volatile__("movq %%dr0, %0\n\t" : "=r" (uDR0));
1930# else
1931 __asm__ __volatile__("movl %%dr0, %0\n\t" : "=r" (uDR0));
1932# endif
1933# else
1934 __asm
1935 {
1936# ifdef RT_ARCH_AMD64
1937 mov rax, dr0
1938 mov [uDR0], rax
1939# else
1940 mov eax, dr0
1941 mov [uDR0], eax
1942# endif
1943 }
1944# endif
1945 return uDR0;
1946}
1947#endif
1948
1949
1950/**
1951 * Gets dr1.
1952 *
1953 * @returns dr1.
1954 */
1955#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1956DECLASM(RTCCUINTREG) ASMGetDR1(void);
1957#else
1958DECLINLINE(RTCCUINTREG) ASMGetDR1(void)
1959{
1960 RTCCUINTREG uDR1;
1961# if RT_INLINE_ASM_USES_INTRIN
1962 uDR1 = __readdr(1);
1963# elif RT_INLINE_ASM_GNU_STYLE
1964# ifdef RT_ARCH_AMD64
1965 __asm__ __volatile__("movq %%dr1, %0\n\t" : "=r" (uDR1));
1966# else
1967 __asm__ __volatile__("movl %%dr1, %0\n\t" : "=r" (uDR1));
1968# endif
1969# else
1970 __asm
1971 {
1972# ifdef RT_ARCH_AMD64
1973 mov rax, dr1
1974 mov [uDR1], rax
1975# else
1976 mov eax, dr1
1977 mov [uDR1], eax
1978# endif
1979 }
1980# endif
1981 return uDR1;
1982}
1983#endif
1984
1985
1986/**
1987 * Gets dr2.
1988 *
1989 * @returns dr2.
1990 */
1991#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1992DECLASM(RTCCUINTREG) ASMGetDR2(void);
1993#else
1994DECLINLINE(RTCCUINTREG) ASMGetDR2(void)
1995{
1996 RTCCUINTREG uDR2;
1997# if RT_INLINE_ASM_USES_INTRIN
1998 uDR2 = __readdr(2);
1999# elif RT_INLINE_ASM_GNU_STYLE
2000# ifdef RT_ARCH_AMD64
2001 __asm__ __volatile__("movq %%dr2, %0\n\t" : "=r" (uDR2));
2002# else
2003 __asm__ __volatile__("movl %%dr2, %0\n\t" : "=r" (uDR2));
2004# endif
2005# else
2006 __asm
2007 {
2008# ifdef RT_ARCH_AMD64
2009 mov rax, dr2
2010 mov [uDR2], rax
2011# else
2012 mov eax, dr2
2013 mov [uDR2], eax
2014# endif
2015 }
2016# endif
2017 return uDR2;
2018}
2019#endif
2020
2021
2022/**
2023 * Gets dr3.
2024 *
2025 * @returns dr3.
2026 */
2027#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2028DECLASM(RTCCUINTREG) ASMGetDR3(void);
2029#else
2030DECLINLINE(RTCCUINTREG) ASMGetDR3(void)
2031{
2032 RTCCUINTREG uDR3;
2033# if RT_INLINE_ASM_USES_INTRIN
2034 uDR3 = __readdr(3);
2035# elif RT_INLINE_ASM_GNU_STYLE
2036# ifdef RT_ARCH_AMD64
2037 __asm__ __volatile__("movq %%dr3, %0\n\t" : "=r" (uDR3));
2038# else
2039 __asm__ __volatile__("movl %%dr3, %0\n\t" : "=r" (uDR3));
2040# endif
2041# else
2042 __asm
2043 {
2044# ifdef RT_ARCH_AMD64
2045 mov rax, dr3
2046 mov [uDR3], rax
2047# else
2048 mov eax, dr3
2049 mov [uDR3], eax
2050# endif
2051 }
2052# endif
2053 return uDR3;
2054}
2055#endif
2056
2057
2058/**
2059 * Gets dr6.
2060 *
2061 * @returns dr6.
2062 */
2063#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2064DECLASM(RTCCUINTREG) ASMGetDR6(void);
2065#else
2066DECLINLINE(RTCCUINTREG) ASMGetDR6(void)
2067{
2068 RTCCUINTREG uDR6;
2069# if RT_INLINE_ASM_USES_INTRIN
2070 uDR6 = __readdr(6);
2071# elif RT_INLINE_ASM_GNU_STYLE
2072# ifdef RT_ARCH_AMD64
2073 __asm__ __volatile__("movq %%dr6, %0\n\t" : "=r" (uDR6));
2074# else
2075 __asm__ __volatile__("movl %%dr6, %0\n\t" : "=r" (uDR6));
2076# endif
2077# else
2078 __asm
2079 {
2080# ifdef RT_ARCH_AMD64
2081 mov rax, dr6
2082 mov [uDR6], rax
2083# else
2084 mov eax, dr6
2085 mov [uDR6], eax
2086# endif
2087 }
2088# endif
2089 return uDR6;
2090}
2091#endif
2092
2093
2094/**
2095 * Reads and clears DR6.
2096 *
2097 * @returns DR6.
2098 */
2099#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2100DECLASM(RTCCUINTREG) ASMGetAndClearDR6(void);
2101#else
2102DECLINLINE(RTCCUINTREG) ASMGetAndClearDR6(void)
2103{
2104 RTCCUINTREG uDR6;
2105# if RT_INLINE_ASM_USES_INTRIN
2106 uDR6 = __readdr(6);
2107 __writedr(6, 0xffff0ff0U); /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
2108# elif RT_INLINE_ASM_GNU_STYLE
2109 RTCCUINTREG uNewValue = 0xffff0ff0U;/* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
2110# ifdef RT_ARCH_AMD64
2111 __asm__ __volatile__("movq %%dr6, %0\n\t"
2112 "movq %1, %%dr6\n\t"
2113 : "=r" (uDR6)
2114 : "r" (uNewValue));
2115# else
2116 __asm__ __volatile__("movl %%dr6, %0\n\t"
2117 "movl %1, %%dr6\n\t"
2118 : "=r" (uDR6)
2119 : "r" (uNewValue));
2120# endif
2121# else
2122 __asm
2123 {
2124# ifdef RT_ARCH_AMD64
2125 mov rax, dr6
2126 mov [uDR6], rax
2127 mov rcx, rax
2128 mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
2129 mov dr6, rcx
2130# else
2131 mov eax, dr6
2132 mov [uDR6], eax
2133 mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 is zero. */
2134 mov dr6, ecx
2135# endif
2136 }
2137# endif
2138 return uDR6;
2139}
2140#endif
2141
2142
2143/**
2144 * Gets dr7.
2145 *
2146 * @returns dr7.
2147 */
2148#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2149DECLASM(RTCCUINTREG) ASMGetDR7(void);
2150#else
2151DECLINLINE(RTCCUINTREG) ASMGetDR7(void)
2152{
2153 RTCCUINTREG uDR7;
2154# if RT_INLINE_ASM_USES_INTRIN
2155 uDR7 = __readdr(7);
2156# elif RT_INLINE_ASM_GNU_STYLE
2157# ifdef RT_ARCH_AMD64
2158 __asm__ __volatile__("movq %%dr7, %0\n\t" : "=r" (uDR7));
2159# else
2160 __asm__ __volatile__("movl %%dr7, %0\n\t" : "=r" (uDR7));
2161# endif
2162# else
2163 __asm
2164 {
2165# ifdef RT_ARCH_AMD64
2166 mov rax, dr7
2167 mov [uDR7], rax
2168# else
2169 mov eax, dr7
2170 mov [uDR7], eax
2171# endif
2172 }
2173# endif
2174 return uDR7;
2175}
2176#endif
2177
2178
2179/**
2180 * Sets dr0.
2181 *
2182 * @param uDRVal Debug register value to write
2183 */
2184#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2185DECLASM(void) ASMSetDR0(RTCCUINTREG uDRVal);
2186#else
2187DECLINLINE(void) ASMSetDR0(RTCCUINTREG uDRVal)
2188{
2189# if RT_INLINE_ASM_USES_INTRIN
2190 __writedr(0, uDRVal);
2191# elif RT_INLINE_ASM_GNU_STYLE
2192# ifdef RT_ARCH_AMD64
2193 __asm__ __volatile__("movq %0, %%dr0\n\t" : : "r" (uDRVal));
2194# else
2195 __asm__ __volatile__("movl %0, %%dr0\n\t" : : "r" (uDRVal));
2196# endif
2197# else
2198 __asm
2199 {
2200# ifdef RT_ARCH_AMD64
2201 mov rax, [uDRVal]
2202 mov dr0, rax
2203# else
2204 mov eax, [uDRVal]
2205 mov dr0, eax
2206# endif
2207 }
2208# endif
2209}
2210#endif
2211
2212
2213/**
2214 * Sets dr1.
2215 *
2216 * @param uDRVal Debug register value to write
2217 */
2218#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2219DECLASM(void) ASMSetDR1(RTCCUINTREG uDRVal);
2220#else
2221DECLINLINE(void) ASMSetDR1(RTCCUINTREG uDRVal)
2222{
2223# if RT_INLINE_ASM_USES_INTRIN
2224 __writedr(1, uDRVal);
2225# elif RT_INLINE_ASM_GNU_STYLE
2226# ifdef RT_ARCH_AMD64
2227 __asm__ __volatile__("movq %0, %%dr1\n\t" : : "r" (uDRVal));
2228# else
2229 __asm__ __volatile__("movl %0, %%dr1\n\t" : : "r" (uDRVal));
2230# endif
2231# else
2232 __asm
2233 {
2234# ifdef RT_ARCH_AMD64
2235 mov rax, [uDRVal]
2236 mov dr1, rax
2237# else
2238 mov eax, [uDRVal]
2239 mov dr1, eax
2240# endif
2241 }
2242# endif
2243}
2244#endif
2245
2246
2247/**
2248 * Sets dr2.
2249 *
2250 * @param uDRVal Debug register value to write
2251 */
2252#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2253DECLASM(void) ASMSetDR2(RTCCUINTREG uDRVal);
2254#else
2255DECLINLINE(void) ASMSetDR2(RTCCUINTREG uDRVal)
2256{
2257# if RT_INLINE_ASM_USES_INTRIN
2258 __writedr(2, uDRVal);
2259# elif RT_INLINE_ASM_GNU_STYLE
2260# ifdef RT_ARCH_AMD64
2261 __asm__ __volatile__("movq %0, %%dr2\n\t" : : "r" (uDRVal));
2262# else
2263 __asm__ __volatile__("movl %0, %%dr2\n\t" : : "r" (uDRVal));
2264# endif
2265# else
2266 __asm
2267 {
2268# ifdef RT_ARCH_AMD64
2269 mov rax, [uDRVal]
2270 mov dr2, rax
2271# else
2272 mov eax, [uDRVal]
2273 mov dr2, eax
2274# endif
2275 }
2276# endif
2277}
2278#endif
2279
2280
2281/**
2282 * Sets dr3.
2283 *
2284 * @param uDRVal Debug register value to write
2285 */
2286#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2287DECLASM(void) ASMSetDR3(RTCCUINTREG uDRVal);
2288#else
2289DECLINLINE(void) ASMSetDR3(RTCCUINTREG uDRVal)
2290{
2291# if RT_INLINE_ASM_USES_INTRIN
2292 __writedr(3, uDRVal);
2293# elif RT_INLINE_ASM_GNU_STYLE
2294# ifdef RT_ARCH_AMD64
2295 __asm__ __volatile__("movq %0, %%dr3\n\t" : : "r" (uDRVal));
2296# else
2297 __asm__ __volatile__("movl %0, %%dr3\n\t" : : "r" (uDRVal));
2298# endif
2299# else
2300 __asm
2301 {
2302# ifdef RT_ARCH_AMD64
2303 mov rax, [uDRVal]
2304 mov dr3, rax
2305# else
2306 mov eax, [uDRVal]
2307 mov dr3, eax
2308# endif
2309 }
2310# endif
2311}
2312#endif
2313
2314
2315/**
2316 * Sets dr6.
2317 *
2318 * @param uDRVal Debug register value to write
2319 */
2320#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2321DECLASM(void) ASMSetDR6(RTCCUINTREG uDRVal);
2322#else
2323DECLINLINE(void) ASMSetDR6(RTCCUINTREG uDRVal)
2324{
2325# if RT_INLINE_ASM_USES_INTRIN
2326 __writedr(6, uDRVal);
2327# elif RT_INLINE_ASM_GNU_STYLE
2328# ifdef RT_ARCH_AMD64
2329 __asm__ __volatile__("movq %0, %%dr6\n\t" : : "r" (uDRVal));
2330# else
2331 __asm__ __volatile__("movl %0, %%dr6\n\t" : : "r" (uDRVal));
2332# endif
2333# else
2334 __asm
2335 {
2336# ifdef RT_ARCH_AMD64
2337 mov rax, [uDRVal]
2338 mov dr6, rax
2339# else
2340 mov eax, [uDRVal]
2341 mov dr6, eax
2342# endif
2343 }
2344# endif
2345}
2346#endif
2347
2348
2349/**
2350 * Sets dr7.
2351 *
2352 * @param uDRVal Debug register value to write
2353 */
2354#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2355DECLASM(void) ASMSetDR7(RTCCUINTREG uDRVal);
2356#else
2357DECLINLINE(void) ASMSetDR7(RTCCUINTREG uDRVal)
2358{
2359# if RT_INLINE_ASM_USES_INTRIN
2360 __writedr(7, uDRVal);
2361# elif RT_INLINE_ASM_GNU_STYLE
2362# ifdef RT_ARCH_AMD64
2363 __asm__ __volatile__("movq %0, %%dr7\n\t" : : "r" (uDRVal));
2364# else
2365 __asm__ __volatile__("movl %0, %%dr7\n\t" : : "r" (uDRVal));
2366# endif
2367# else
2368 __asm
2369 {
2370# ifdef RT_ARCH_AMD64
2371 mov rax, [uDRVal]
2372 mov dr7, rax
2373# else
2374 mov eax, [uDRVal]
2375 mov dr7, eax
2376# endif
2377 }
2378# endif
2379}
2380#endif
2381
2382
2383/**
2384 * Writes a 8-bit unsigned integer to an I/O port, ordered.
2385 *
2386 * @param Port I/O port to write to.
2387 * @param u8 8-bit integer to write.
2388 */
2389#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2390DECLASM(void) ASMOutU8(RTIOPORT Port, uint8_t u8);
2391#else
2392DECLINLINE(void) ASMOutU8(RTIOPORT Port, uint8_t u8)
2393{
2394# if RT_INLINE_ASM_GNU_STYLE
2395 __asm__ __volatile__("outb %b1, %w0\n\t"
2396 :: "Nd" (Port),
2397 "a" (u8));
2398
2399# elif RT_INLINE_ASM_USES_INTRIN
2400 __outbyte(Port, u8);
2401
2402# else
2403 __asm
2404 {
2405 mov dx, [Port]
2406 mov al, [u8]
2407 out dx, al
2408 }
2409# endif
2410}
2411#endif
2412
2413
2414/**
2415 * Reads a 8-bit unsigned integer from an I/O port, ordered.
2416 *
2417 * @returns 8-bit integer.
2418 * @param Port I/O port to read from.
2419 */
2420#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2421DECLASM(uint8_t) ASMInU8(RTIOPORT Port);
2422#else
2423DECLINLINE(uint8_t) ASMInU8(RTIOPORT Port)
2424{
2425 uint8_t u8;
2426# if RT_INLINE_ASM_GNU_STYLE
2427 __asm__ __volatile__("inb %w1, %b0\n\t"
2428 : "=a" (u8)
2429 : "Nd" (Port));
2430
2431# elif RT_INLINE_ASM_USES_INTRIN
2432 u8 = __inbyte(Port);
2433
2434# else
2435 __asm
2436 {
2437 mov dx, [Port]
2438 in al, dx
2439 mov [u8], al
2440 }
2441# endif
2442 return u8;
2443}
2444#endif
2445
2446
2447/**
2448 * Writes a 16-bit unsigned integer to an I/O port, ordered.
2449 *
2450 * @param Port I/O port to write to.
2451 * @param u16 16-bit integer to write.
2452 */
2453#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2454DECLASM(void) ASMOutU16(RTIOPORT Port, uint16_t u16);
2455#else
2456DECLINLINE(void) ASMOutU16(RTIOPORT Port, uint16_t u16)
2457{
2458# if RT_INLINE_ASM_GNU_STYLE
2459 __asm__ __volatile__("outw %w1, %w0\n\t"
2460 :: "Nd" (Port),
2461 "a" (u16));
2462
2463# elif RT_INLINE_ASM_USES_INTRIN
2464 __outword(Port, u16);
2465
2466# else
2467 __asm
2468 {
2469 mov dx, [Port]
2470 mov ax, [u16]
2471 out dx, ax
2472 }
2473# endif
2474}
2475#endif
2476
2477
2478/**
2479 * Reads a 16-bit unsigned integer from an I/O port, ordered.
2480 *
2481 * @returns 16-bit integer.
2482 * @param Port I/O port to read from.
2483 */
2484#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2485DECLASM(uint16_t) ASMInU16(RTIOPORT Port);
2486#else
2487DECLINLINE(uint16_t) ASMInU16(RTIOPORT Port)
2488{
2489 uint16_t u16;
2490# if RT_INLINE_ASM_GNU_STYLE
2491 __asm__ __volatile__("inw %w1, %w0\n\t"
2492 : "=a" (u16)
2493 : "Nd" (Port));
2494
2495# elif RT_INLINE_ASM_USES_INTRIN
2496 u16 = __inword(Port);
2497
2498# else
2499 __asm
2500 {
2501 mov dx, [Port]
2502 in ax, dx
2503 mov [u16], ax
2504 }
2505# endif
2506 return u16;
2507}
2508#endif
2509
2510
2511/**
2512 * Writes a 32-bit unsigned integer to an I/O port, ordered.
2513 *
2514 * @param Port I/O port to write to.
2515 * @param u32 32-bit integer to write.
2516 */
2517#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2518DECLASM(void) ASMOutU32(RTIOPORT Port, uint32_t u32);
2519#else
2520DECLINLINE(void) ASMOutU32(RTIOPORT Port, uint32_t u32)
2521{
2522# if RT_INLINE_ASM_GNU_STYLE
2523 __asm__ __volatile__("outl %1, %w0\n\t"
2524 :: "Nd" (Port),
2525 "a" (u32));
2526
2527# elif RT_INLINE_ASM_USES_INTRIN
2528 __outdword(Port, u32);
2529
2530# else
2531 __asm
2532 {
2533 mov dx, [Port]
2534 mov eax, [u32]
2535 out dx, eax
2536 }
2537# endif
2538}
2539#endif
2540
2541
2542/**
2543 * Reads a 32-bit unsigned integer from an I/O port, ordered.
2544 *
2545 * @returns 32-bit integer.
2546 * @param Port I/O port to read from.
2547 */
2548#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2549DECLASM(uint32_t) ASMInU32(RTIOPORT Port);
2550#else
2551DECLINLINE(uint32_t) ASMInU32(RTIOPORT Port)
2552{
2553 uint32_t u32;
2554# if RT_INLINE_ASM_GNU_STYLE
2555 __asm__ __volatile__("inl %w1, %0\n\t"
2556 : "=a" (u32)
2557 : "Nd" (Port));
2558
2559# elif RT_INLINE_ASM_USES_INTRIN
2560 u32 = __indword(Port);
2561
2562# else
2563 __asm
2564 {
2565 mov dx, [Port]
2566 in eax, dx
2567 mov [u32], eax
2568 }
2569# endif
2570 return u32;
2571}
2572#endif
2573
2574
2575/**
2576 * Writes a string of 8-bit unsigned integer items to an I/O port, ordered.
2577 *
2578 * @param Port I/O port to write to.
2579 * @param pau8 Pointer to the string buffer.
2580 * @param c The number of items to write.
2581 */
2582#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2583DECLASM(void) ASMOutStrU8(RTIOPORT Port, uint8_t const *pau8, size_t c);
2584#else
2585DECLINLINE(void) ASMOutStrU8(RTIOPORT Port, uint8_t const *pau8, size_t c)
2586{
2587# if RT_INLINE_ASM_GNU_STYLE
2588 __asm__ __volatile__("rep; outsb\n\t"
2589 : "+S" (pau8),
2590 "+c" (c)
2591 : "d" (Port));
2592
2593# elif RT_INLINE_ASM_USES_INTRIN
2594 __outbytestring(Port, (unsigned char *)pau8, (unsigned long)c);
2595
2596# else
2597 __asm
2598 {
2599 mov dx, [Port]
2600 mov ecx, [c]
2601 mov eax, [pau8]
2602 xchg esi, eax
2603 rep outsb
2604 xchg esi, eax
2605 }
2606# endif
2607}
2608#endif
2609
2610
2611/**
2612 * Reads a string of 8-bit unsigned integer items from an I/O port, ordered.
2613 *
2614 * @param Port I/O port to read from.
2615 * @param pau8 Pointer to the string buffer (output).
2616 * @param c The number of items to read.
2617 */
2618#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2619DECLASM(void) ASMInStrU8(RTIOPORT Port, uint8_t *pau8, size_t c);
2620#else
2621DECLINLINE(void) ASMInStrU8(RTIOPORT Port, uint8_t *pau8, size_t c)
2622{
2623# if RT_INLINE_ASM_GNU_STYLE
2624 __asm__ __volatile__("rep; insb\n\t"
2625 : "+D" (pau8),
2626 "+c" (c)
2627 : "d" (Port));
2628
2629# elif RT_INLINE_ASM_USES_INTRIN
2630 __inbytestring(Port, pau8, (unsigned long)c);
2631
2632# else
2633 __asm
2634 {
2635 mov dx, [Port]
2636 mov ecx, [c]
2637 mov eax, [pau8]
2638 xchg edi, eax
2639 rep insb
2640 xchg edi, eax
2641 }
2642# endif
2643}
2644#endif
2645
2646
2647/**
2648 * Writes a string of 16-bit unsigned integer items to an I/O port, ordered.
2649 *
2650 * @param Port I/O port to write to.
2651 * @param pau16 Pointer to the string buffer.
2652 * @param c The number of items to write.
2653 */
2654#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2655DECLASM(void) ASMOutStrU16(RTIOPORT Port, uint16_t const *pau16, size_t c);
2656#else
2657DECLINLINE(void) ASMOutStrU16(RTIOPORT Port, uint16_t const *pau16, size_t c)
2658{
2659# if RT_INLINE_ASM_GNU_STYLE
2660 __asm__ __volatile__("rep; outsw\n\t"
2661 : "+S" (pau16),
2662 "+c" (c)
2663 : "d" (Port));
2664
2665# elif RT_INLINE_ASM_USES_INTRIN
2666 __outwordstring(Port, (unsigned short *)pau16, (unsigned long)c);
2667
2668# else
2669 __asm
2670 {
2671 mov dx, [Port]
2672 mov ecx, [c]
2673 mov eax, [pau16]
2674 xchg esi, eax
2675 rep outsw
2676 xchg esi, eax
2677 }
2678# endif
2679}
2680#endif
2681
2682
2683/**
2684 * Reads a string of 16-bit unsigned integer items from an I/O port, ordered.
2685 *
2686 * @param Port I/O port to read from.
2687 * @param pau16 Pointer to the string buffer (output).
2688 * @param c The number of items to read.
2689 */
2690#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2691DECLASM(void) ASMInStrU16(RTIOPORT Port, uint16_t *pau16, size_t c);
2692#else
2693DECLINLINE(void) ASMInStrU16(RTIOPORT Port, uint16_t *pau16, size_t c)
2694{
2695# if RT_INLINE_ASM_GNU_STYLE
2696 __asm__ __volatile__("rep; insw\n\t"
2697 : "+D" (pau16),
2698 "+c" (c)
2699 : "d" (Port));
2700
2701# elif RT_INLINE_ASM_USES_INTRIN
2702 __inwordstring(Port, pau16, (unsigned long)c);
2703
2704# else
2705 __asm
2706 {
2707 mov dx, [Port]
2708 mov ecx, [c]
2709 mov eax, [pau16]
2710 xchg edi, eax
2711 rep insw
2712 xchg edi, eax
2713 }
2714# endif
2715}
2716#endif
2717
2718
2719/**
2720 * Writes a string of 32-bit unsigned integer items to an I/O port, ordered.
2721 *
2722 * @param Port I/O port to write to.
2723 * @param pau32 Pointer to the string buffer.
2724 * @param c The number of items to write.
2725 */
2726#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2727DECLASM(void) ASMOutStrU32(RTIOPORT Port, uint32_t const *pau32, size_t c);
2728#else
2729DECLINLINE(void) ASMOutStrU32(RTIOPORT Port, uint32_t const *pau32, size_t c)
2730{
2731# if RT_INLINE_ASM_GNU_STYLE
2732 __asm__ __volatile__("rep; outsl\n\t"
2733 : "+S" (pau32),
2734 "+c" (c)
2735 : "d" (Port));
2736
2737# elif RT_INLINE_ASM_USES_INTRIN
2738 __outdwordstring(Port, (unsigned long *)pau32, (unsigned long)c);
2739
2740# else
2741 __asm
2742 {
2743 mov dx, [Port]
2744 mov ecx, [c]
2745 mov eax, [pau32]
2746 xchg esi, eax
2747 rep outsd
2748 xchg esi, eax
2749 }
2750# endif
2751}
2752#endif
2753
2754
2755/**
2756 * Reads a string of 32-bit unsigned integer items from an I/O port, ordered.
2757 *
2758 * @param Port I/O port to read from.
2759 * @param pau32 Pointer to the string buffer (output).
2760 * @param c The number of items to read.
2761 */
2762#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2763DECLASM(void) ASMInStrU32(RTIOPORT Port, uint32_t *pau32, size_t c);
2764#else
2765DECLINLINE(void) ASMInStrU32(RTIOPORT Port, uint32_t *pau32, size_t c)
2766{
2767# if RT_INLINE_ASM_GNU_STYLE
2768 __asm__ __volatile__("rep; insl\n\t"
2769 : "+D" (pau32),
2770 "+c" (c)
2771 : "d" (Port));
2772
2773# elif RT_INLINE_ASM_USES_INTRIN
2774 __indwordstring(Port, (unsigned long *)pau32, (unsigned long)c);
2775
2776# else
2777 __asm
2778 {
2779 mov dx, [Port]
2780 mov ecx, [c]
2781 mov eax, [pau32]
2782 xchg edi, eax
2783 rep insd
2784 xchg edi, eax
2785 }
2786# endif
2787}
2788#endif
2789
2790
2791/**
2792 * Invalidate page.
2793 *
2794 * @param pv Address of the page to invalidate.
2795 */
2796#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2797DECLASM(void) ASMInvalidatePage(void *pv);
2798#else
2799DECLINLINE(void) ASMInvalidatePage(void *pv)
2800{
2801# if RT_INLINE_ASM_USES_INTRIN
2802 __invlpg(pv);
2803
2804# elif RT_INLINE_ASM_GNU_STYLE
2805 __asm__ __volatile__("invlpg %0\n\t"
2806 : : "m" (*(uint8_t *)pv));
2807# else
2808 __asm
2809 {
2810# ifdef RT_ARCH_AMD64
2811 mov rax, [pv]
2812 invlpg [rax]
2813# else
2814 mov eax, [pv]
2815 invlpg [eax]
2816# endif
2817 }
2818# endif
2819}
2820#endif
2821
2822
2823/**
2824 * Write back the internal caches and invalidate them.
2825 */
2826#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2827DECLASM(void) ASMWriteBackAndInvalidateCaches(void);
2828#else
2829DECLINLINE(void) ASMWriteBackAndInvalidateCaches(void)
2830{
2831# if RT_INLINE_ASM_USES_INTRIN
2832 __wbinvd();
2833
2834# elif RT_INLINE_ASM_GNU_STYLE
2835 __asm__ __volatile__("wbinvd");
2836# else
2837 __asm
2838 {
2839 wbinvd
2840 }
2841# endif
2842}
2843#endif
2844
2845
2846/**
2847 * Invalidate internal and (perhaps) external caches without first
2848 * flushing dirty cache lines. Use with extreme care.
2849 */
2850#if RT_INLINE_ASM_EXTERNAL
2851DECLASM(void) ASMInvalidateInternalCaches(void);
2852#else
2853DECLINLINE(void) ASMInvalidateInternalCaches(void)
2854{
2855# if RT_INLINE_ASM_GNU_STYLE
2856 __asm__ __volatile__("invd");
2857# else
2858 __asm
2859 {
2860 invd
2861 }
2862# endif
2863}
2864#endif
2865
2866
2867/**
2868 * Memory load/store fence, waits for any pending writes and reads to complete.
2869 * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.
2870 */
2871DECLINLINE(void) ASMMemoryFenceSSE2(void)
2872{
2873#if RT_INLINE_ASM_GNU_STYLE
2874 __asm__ __volatile__ (".byte 0x0f,0xae,0xf0\n\t");
2875#elif RT_INLINE_ASM_USES_INTRIN
2876 _mm_mfence();
2877#else
2878 __asm
2879 {
2880 _emit 0x0f
2881 _emit 0xae
2882 _emit 0xf0
2883 }
2884#endif
2885}
2886
2887
2888/**
2889 * Memory store fence, waits for any writes to complete.
2890 * Requires the X86_CPUID_FEATURE_EDX_SSE CPUID bit set.
2891 */
2892DECLINLINE(void) ASMWriteFenceSSE(void)
2893{
2894#if RT_INLINE_ASM_GNU_STYLE
2895 __asm__ __volatile__ (".byte 0x0f,0xae,0xf8\n\t");
2896#elif RT_INLINE_ASM_USES_INTRIN
2897 _mm_sfence();
2898#else
2899 __asm
2900 {
2901 _emit 0x0f
2902 _emit 0xae
2903 _emit 0xf8
2904 }
2905#endif
2906}
2907
2908
2909/**
2910 * Memory load fence, waits for any pending reads to complete.
2911 * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.
2912 */
2913DECLINLINE(void) ASMReadFenceSSE2(void)
2914{
2915#if RT_INLINE_ASM_GNU_STYLE
2916 __asm__ __volatile__ (".byte 0x0f,0xae,0xe8\n\t");
2917#elif RT_INLINE_ASM_USES_INTRIN
2918 _mm_lfence();
2919#else
2920 __asm
2921 {
2922 _emit 0x0f
2923 _emit 0xae
2924 _emit 0xe8
2925 }
2926#endif
2927}
2928
2929/** @} */
2930#endif
2931
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