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source: vbox/trunk/include/iprt/asm-amd64-x86.h@ 86303

Last change on this file since 86303 was 86303, checked in by vboxsync, 4 years ago

iprt/asm-amd64-x86.h: Corrected return type for non-inline ASMGetApicIdExt0B.
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1/** @file
2 * IPRT - AMD64 and x86 Specific Assembly Functions.
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef IPRT_INCLUDED_asm_amd64_x86_h
27#define IPRT_INCLUDED_asm_amd64_x86_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/types.h>
33#include <iprt/assert.h>
34#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
35# error "Not on AMD64 or x86"
36#endif
37
38#if defined(_MSC_VER) && RT_INLINE_ASM_USES_INTRIN
39/* Emit the intrinsics at all optimization levels. */
40# include <iprt/sanitized/intrin.h>
41# pragma intrinsic(_ReadWriteBarrier)
42# pragma intrinsic(__cpuid)
43# if RT_INLINE_ASM_USES_INTRIN >= 16 /*?*/
44# pragma intrinsic(__cpuidex)
45# endif
46# pragma intrinsic(_enable)
47# pragma intrinsic(_disable)
48# pragma intrinsic(__rdtsc)
49# pragma intrinsic(__readmsr)
50# pragma intrinsic(__writemsr)
51# pragma intrinsic(__outbyte)
52# pragma intrinsic(__outbytestring)
53# pragma intrinsic(__outword)
54# pragma intrinsic(__outwordstring)
55# pragma intrinsic(__outdword)
56# pragma intrinsic(__outdwordstring)
57# pragma intrinsic(__inbyte)
58# pragma intrinsic(__inbytestring)
59# pragma intrinsic(__inword)
60# pragma intrinsic(__inwordstring)
61# pragma intrinsic(__indword)
62# pragma intrinsic(__indwordstring)
63# pragma intrinsic(__invlpg)
64# pragma intrinsic(__wbinvd)
65# pragma intrinsic(__readcr0)
66# pragma intrinsic(__readcr2)
67# pragma intrinsic(__readcr3)
68# pragma intrinsic(__readcr4)
69# pragma intrinsic(__writecr0)
70# pragma intrinsic(__writecr3)
71# pragma intrinsic(__writecr4)
72# pragma intrinsic(__readdr)
73# pragma intrinsic(__writedr)
74# ifdef RT_ARCH_AMD64
75# pragma intrinsic(__readcr8)
76# pragma intrinsic(__writecr8)
77# endif
78# if RT_INLINE_ASM_USES_INTRIN >= 14
79# pragma intrinsic(__halt)
80# endif
81# if RT_INLINE_ASM_USES_INTRIN >= 15
82/*# pragma intrinsic(__readeflags) - buggy intrinsics in VC++ 2010, reordering/optimizers issues
83# pragma intrinsic(__writeeflags) */
84# pragma intrinsic(__rdtscp)
85# endif
86#endif
87
88
89/*
90 * Undefine all symbols we have Watcom C/C++ #pragma aux'es for.
91 */
92#if defined(__WATCOMC__) && ARCH_BITS == 16
93# include "asm-amd64-x86-watcom-16.h"
94#elif defined(__WATCOMC__) && ARCH_BITS == 32
95# include "asm-amd64-x86-watcom-32.h"
96#endif
97
98
99/** @defgroup grp_rt_asm_amd64_x86 AMD64 and x86 Specific ASM Routines
100 * @ingroup grp_rt_asm
101 * @{
102 */
103
104/** @todo find a more proper place for these structures? */
105
106#pragma pack(1)
107/** IDTR */
108typedef struct RTIDTR
109{
110 /** Size of the IDT. */
111 uint16_t cbIdt;
112 /** Address of the IDT. */
113#if ARCH_BITS != 64
114 uint32_t pIdt;
115#else
116 uint64_t pIdt;
117#endif
118} RTIDTR, RT_FAR *PRTIDTR;
119#pragma pack()
120
121#pragma pack(1)
122/** @internal */
123typedef struct RTIDTRALIGNEDINT
124{
125 /** Alignment padding. */
126 uint16_t au16Padding[ARCH_BITS == 64 ? 3 : 1];
127 /** The IDTR structure. */
128 RTIDTR Idtr;
129} RTIDTRALIGNEDINT;
130#pragma pack()
131
132/** Wrapped RTIDTR for preventing misalignment exceptions. */
133typedef union RTIDTRALIGNED
134{
135 /** Try make sure this structure has optimal alignment. */
136 uint64_t auAlignmentHack[ARCH_BITS == 64 ? 2 : 1];
137 /** Aligned structure. */
138 RTIDTRALIGNEDINT s;
139} RTIDTRALIGNED;
140AssertCompileSize(RTIDTRALIGNED, ((ARCH_BITS == 64) + 1) * 8);
141/** Pointer to a an RTIDTR alignment wrapper. */
142typedef RTIDTRALIGNED RT_FAR *PRIDTRALIGNED;
143
144
145#pragma pack(1)
146/** GDTR */
147typedef struct RTGDTR
148{
149 /** Size of the GDT. */
150 uint16_t cbGdt;
151 /** Address of the GDT. */
152#if ARCH_BITS != 64
153 uint32_t pGdt;
154#else
155 uint64_t pGdt;
156#endif
157} RTGDTR, RT_FAR *PRTGDTR;
158#pragma pack()
159
160#pragma pack(1)
161/** @internal */
162typedef struct RTGDTRALIGNEDINT
163{
164 /** Alignment padding. */
165 uint16_t au16Padding[ARCH_BITS == 64 ? 3 : 1];
166 /** The GDTR structure. */
167 RTGDTR Gdtr;
168} RTGDTRALIGNEDINT;
169#pragma pack()
170
171/** Wrapped RTGDTR for preventing misalignment exceptions. */
172typedef union RTGDTRALIGNED
173{
174 /** Try make sure this structure has optimal alignment. */
175 uint64_t auAlignmentHack[ARCH_BITS == 64 ? 2 : 1];
176 /** Aligned structure. */
177 RTGDTRALIGNEDINT s;
178} RTGDTRALIGNED;
179AssertCompileSize(RTIDTRALIGNED, ((ARCH_BITS == 64) + 1) * 8);
180/** Pointer to a an RTGDTR alignment wrapper. */
181typedef RTGDTRALIGNED RT_FAR *PRGDTRALIGNED;
182
183
184/**
185 * Gets the content of the IDTR CPU register.
186 * @param pIdtr Where to store the IDTR contents.
187 */
188#if RT_INLINE_ASM_EXTERNAL
189RT_ASM_DECL_PRAGMA_WATCOM(void) ASMGetIDTR(PRTIDTR pIdtr);
190#else
191DECLINLINE(void) ASMGetIDTR(PRTIDTR pIdtr)
192{
193# if RT_INLINE_ASM_GNU_STYLE
194 __asm__ __volatile__("sidt %0" : "=m" (*pIdtr));
195# else
196 __asm
197 {
198# ifdef RT_ARCH_AMD64
199 mov rax, [pIdtr]
200 sidt [rax]
201# else
202 mov eax, [pIdtr]
203 sidt [eax]
204# endif
205 }
206# endif
207}
208#endif
209
210
211/**
212 * Gets the content of the IDTR.LIMIT CPU register.
213 * @returns IDTR limit.
214 */
215#if RT_INLINE_ASM_EXTERNAL
216RT_ASM_DECL_PRAGMA_WATCOM(uint16_t) ASMGetIdtrLimit(void);
217#else
218DECLINLINE(uint16_t) ASMGetIdtrLimit(void)
219{
220 RTIDTRALIGNED TmpIdtr;
221# if RT_INLINE_ASM_GNU_STYLE
222 __asm__ __volatile__("sidt %0" : "=m" (TmpIdtr.s.Idtr));
223# else
224 __asm
225 {
226 sidt [TmpIdtr.s.Idtr]
227 }
228# endif
229 return TmpIdtr.s.Idtr.cbIdt;
230}
231#endif
232
233
234/**
235 * Sets the content of the IDTR CPU register.
236 * @param pIdtr Where to load the IDTR contents from
237 */
238#if RT_INLINE_ASM_EXTERNAL
239RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetIDTR(const RTIDTR RT_FAR *pIdtr);
240#else
241DECLINLINE(void) ASMSetIDTR(const RTIDTR RT_FAR *pIdtr)
242{
243# if RT_INLINE_ASM_GNU_STYLE
244 __asm__ __volatile__("lidt %0" : : "m" (*pIdtr));
245# else
246 __asm
247 {
248# ifdef RT_ARCH_AMD64
249 mov rax, [pIdtr]
250 lidt [rax]
251# else
252 mov eax, [pIdtr]
253 lidt [eax]
254# endif
255 }
256# endif
257}
258#endif
259
260
261/**
262 * Gets the content of the GDTR CPU register.
263 * @param pGdtr Where to store the GDTR contents.
264 */
265#if RT_INLINE_ASM_EXTERNAL
266RT_ASM_DECL_PRAGMA_WATCOM(void) ASMGetGDTR(PRTGDTR pGdtr);
267#else
268DECLINLINE(void) ASMGetGDTR(PRTGDTR pGdtr)
269{
270# if RT_INLINE_ASM_GNU_STYLE
271 __asm__ __volatile__("sgdt %0" : "=m" (*pGdtr));
272# else
273 __asm
274 {
275# ifdef RT_ARCH_AMD64
276 mov rax, [pGdtr]
277 sgdt [rax]
278# else
279 mov eax, [pGdtr]
280 sgdt [eax]
281# endif
282 }
283# endif
284}
285#endif
286
287
288/**
289 * Sets the content of the GDTR CPU register.
290 * @param pGdtr Where to load the GDTR contents from
291 */
292#if RT_INLINE_ASM_EXTERNAL
293RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetGDTR(const RTGDTR RT_FAR *pGdtr);
294#else
295DECLINLINE(void) ASMSetGDTR(const RTGDTR RT_FAR *pGdtr)
296{
297# if RT_INLINE_ASM_GNU_STYLE
298 __asm__ __volatile__("lgdt %0" : : "m" (*pGdtr));
299# else
300 __asm
301 {
302# ifdef RT_ARCH_AMD64
303 mov rax, [pGdtr]
304 lgdt [rax]
305# else
306 mov eax, [pGdtr]
307 lgdt [eax]
308# endif
309 }
310# endif
311}
312#endif
313
314
315
316/**
317 * Get the cs register.
318 * @returns cs.
319 */
320#if RT_INLINE_ASM_EXTERNAL
321RT_ASM_DECL_PRAGMA_WATCOM(RTSEL) ASMGetCS(void);
322#else
323DECLINLINE(RTSEL) ASMGetCS(void)
324{
325 RTSEL SelCS;
326# if RT_INLINE_ASM_GNU_STYLE
327 __asm__ __volatile__("movw %%cs, %0\n\t" : "=r" (SelCS));
328# else
329 __asm
330 {
331 mov ax, cs
332 mov [SelCS], ax
333 }
334# endif
335 return SelCS;
336}
337#endif
338
339
340/**
341 * Get the DS register.
342 * @returns DS.
343 */
344#if RT_INLINE_ASM_EXTERNAL
345RT_ASM_DECL_PRAGMA_WATCOM(RTSEL) ASMGetDS(void);
346#else
347DECLINLINE(RTSEL) ASMGetDS(void)
348{
349 RTSEL SelDS;
350# if RT_INLINE_ASM_GNU_STYLE
351 __asm__ __volatile__("movw %%ds, %0\n\t" : "=r" (SelDS));
352# else
353 __asm
354 {
355 mov ax, ds
356 mov [SelDS], ax
357 }
358# endif
359 return SelDS;
360}
361#endif
362
363
364/**
365 * Get the ES register.
366 * @returns ES.
367 */
368#if RT_INLINE_ASM_EXTERNAL
369RT_ASM_DECL_PRAGMA_WATCOM(RTSEL) ASMGetES(void);
370#else
371DECLINLINE(RTSEL) ASMGetES(void)
372{
373 RTSEL SelES;
374# if RT_INLINE_ASM_GNU_STYLE
375 __asm__ __volatile__("movw %%es, %0\n\t" : "=r" (SelES));
376# else
377 __asm
378 {
379 mov ax, es
380 mov [SelES], ax
381 }
382# endif
383 return SelES;
384}
385#endif
386
387
388/**
389 * Get the FS register.
390 * @returns FS.
391 */
392#if RT_INLINE_ASM_EXTERNAL
393RT_ASM_DECL_PRAGMA_WATCOM(RTSEL) ASMGetFS(void);
394#else
395DECLINLINE(RTSEL) ASMGetFS(void)
396{
397 RTSEL SelFS;
398# if RT_INLINE_ASM_GNU_STYLE
399 __asm__ __volatile__("movw %%fs, %0\n\t" : "=r" (SelFS));
400# else
401 __asm
402 {
403 mov ax, fs
404 mov [SelFS], ax
405 }
406# endif
407 return SelFS;
408}
409# endif
410
411
412/**
413 * Get the GS register.
414 * @returns GS.
415 */
416#if RT_INLINE_ASM_EXTERNAL
417RT_ASM_DECL_PRAGMA_WATCOM(RTSEL) ASMGetGS(void);
418#else
419DECLINLINE(RTSEL) ASMGetGS(void)
420{
421 RTSEL SelGS;
422# if RT_INLINE_ASM_GNU_STYLE
423 __asm__ __volatile__("movw %%gs, %0\n\t" : "=r" (SelGS));
424# else
425 __asm
426 {
427 mov ax, gs
428 mov [SelGS], ax
429 }
430# endif
431 return SelGS;
432}
433#endif
434
435
436/**
437 * Get the SS register.
438 * @returns SS.
439 */
440#if RT_INLINE_ASM_EXTERNAL
441RT_ASM_DECL_PRAGMA_WATCOM(RTSEL) ASMGetSS(void);
442#else
443DECLINLINE(RTSEL) ASMGetSS(void)
444{
445 RTSEL SelSS;
446# if RT_INLINE_ASM_GNU_STYLE
447 __asm__ __volatile__("movw %%ss, %0\n\t" : "=r" (SelSS));
448# else
449 __asm
450 {
451 mov ax, ss
452 mov [SelSS], ax
453 }
454# endif
455 return SelSS;
456}
457#endif
458
459
460/**
461 * Get the TR register.
462 * @returns TR.
463 */
464#if RT_INLINE_ASM_EXTERNAL
465RT_ASM_DECL_PRAGMA_WATCOM(RTSEL) ASMGetTR(void);
466#else
467DECLINLINE(RTSEL) ASMGetTR(void)
468{
469 RTSEL SelTR;
470# if RT_INLINE_ASM_GNU_STYLE
471 __asm__ __volatile__("str %w0\n\t" : "=r" (SelTR));
472# else
473 __asm
474 {
475 str ax
476 mov [SelTR], ax
477 }
478# endif
479 return SelTR;
480}
481#endif
482
483
484/**
485 * Get the LDTR register.
486 * @returns LDTR.
487 */
488#if RT_INLINE_ASM_EXTERNAL
489RT_ASM_DECL_PRAGMA_WATCOM(RTSEL) ASMGetLDTR(void);
490#else
491DECLINLINE(RTSEL) ASMGetLDTR(void)
492{
493 RTSEL SelLDTR;
494# if RT_INLINE_ASM_GNU_STYLE
495 __asm__ __volatile__("sldt %w0\n\t" : "=r" (SelLDTR));
496# else
497 __asm
498 {
499 sldt ax
500 mov [SelLDTR], ax
501 }
502# endif
503 return SelLDTR;
504}
505#endif
506
507
508/**
509 * Get the access rights for the segment selector.
510 *
511 * @returns The access rights on success or UINT32_MAX on failure.
512 * @param uSel The selector value.
513 *
514 * @remarks Using UINT32_MAX for failure is chosen because valid access rights
515 * always have bits 0:7 as 0 (on both Intel & AMD).
516 */
517#if RT_INLINE_ASM_EXTERNAL
518RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMGetSegAttr(uint32_t uSel);
519#else
520DECLINLINE(uint32_t) ASMGetSegAttr(uint32_t uSel)
521{
522 uint32_t uAttr;
523 /* LAR only accesses 16-bit of the source operand, but eax for the
524 destination operand is required for getting the full 32-bit access rights. */
525# if RT_INLINE_ASM_GNU_STYLE
526 __asm__ __volatile__("lar %1, %%eax\n\t"
527 "jz done%=\n\t"
528 "movl $0xffffffff, %%eax\n\t"
529 "done%=:\n\t"
530 "movl %%eax, %0\n\t"
531 : "=r" (uAttr)
532 : "r" (uSel)
533 : "cc", "%eax");
534# else
535 __asm
536 {
537 lar eax, [uSel]
538 jz done
539 mov eax, 0ffffffffh
540 done:
541 mov [uAttr], eax
542 }
543# endif
544 return uAttr;
545}
546#endif
547
548
549/**
550 * Get the [RE]FLAGS register.
551 * @returns [RE]FLAGS.
552 */
553#if RT_INLINE_ASM_EXTERNAL /*&& RT_INLINE_ASM_USES_INTRIN < 15 - buggy intrinsics in VC++ 2010, reordering/optimizers issues. */
554RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTREG) ASMGetFlags(void);
555#else
556DECLINLINE(RTCCUINTREG) ASMGetFlags(void)
557{
558 RTCCUINTREG uFlags;
559# if RT_INLINE_ASM_GNU_STYLE
560# ifdef RT_ARCH_AMD64
561 __asm__ __volatile__("pushfq\n\t"
562 "popq %0\n\t"
563 : "=r" (uFlags));
564# else
565 __asm__ __volatile__("pushfl\n\t"
566 "popl %0\n\t"
567 : "=r" (uFlags));
568# endif
569# elif RT_INLINE_ASM_USES_INTRIN >= 15
570 uFlags = __readeflags();
571# else
572 __asm
573 {
574# ifdef RT_ARCH_AMD64
575 pushfq
576 pop [uFlags]
577# else
578 pushfd
579 pop [uFlags]
580# endif
581 }
582# endif
583 return uFlags;
584}
585#endif
586
587
588/**
589 * Set the [RE]FLAGS register.
590 * @param uFlags The new [RE]FLAGS value.
591 */
592#if RT_INLINE_ASM_EXTERNAL /*&& RT_INLINE_ASM_USES_INTRIN < 15 - see __readeflags() above. */
593RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetFlags(RTCCUINTREG uFlags);
594#else
595DECLINLINE(void) ASMSetFlags(RTCCUINTREG uFlags)
596{
597# if RT_INLINE_ASM_GNU_STYLE
598# ifdef RT_ARCH_AMD64
599 __asm__ __volatile__("pushq %0\n\t"
600 "popfq\n\t"
601 : : "g" (uFlags));
602# else
603 __asm__ __volatile__("pushl %0\n\t"
604 "popfl\n\t"
605 : : "g" (uFlags));
606# endif
607# elif RT_INLINE_ASM_USES_INTRIN >= 15
608 __writeeflags(uFlags);
609# else
610 __asm
611 {
612# ifdef RT_ARCH_AMD64
613 push [uFlags]
614 popfq
615# else
616 push [uFlags]
617 popfd
618# endif
619 }
620# endif
621}
622#endif
623
624
625/**
626 * Modifies the [RE]FLAGS register.
627 * @returns Original value.
628 * @param fAndEfl Flags to keep (applied first).
629 * @param fOrEfl Flags to be set.
630 */
631#if RT_INLINE_ASM_EXTERNAL /*&& RT_INLINE_ASM_USES_INTRIN < 15 - buggy intrinsics in VC++ 2010, reordering/optimizers issues. */
632RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTREG) ASMChangeFlags(RTCCUINTREG fAndEfl, RTCCUINTREG fOrEfl);
633#else
634DECLINLINE(RTCCUINTREG) ASMChangeFlags(RTCCUINTREG fAndEfl, RTCCUINTREG fOrEfl)
635{
636 RTCCUINTREG fOldEfl;
637# if RT_INLINE_ASM_GNU_STYLE
638# ifdef RT_ARCH_AMD64
639 __asm__ __volatile__("pushfq\n\t"
640 "movq (%%rsp), %0\n\t"
641 "andq %0, %1\n\t"
642 "orq %3, %1\n\t"
643 "mov %1, (%%rsp)\n\t"
644 "popfq\n\t"
645 : "=&r" (fOldEfl),
646 "=r" (fAndEfl)
647 : "1" (fAndEfl),
648 "rn" (fOrEfl) );
649# else
650 __asm__ __volatile__("pushfl\n\t"
651 "movl (%%esp), %0\n\t"
652 "andl %1, (%%esp)\n\t"
653 "orl %2, (%%esp)\n\t"
654 "popfl\n\t"
655 : "=&r" (fOldEfl)
656 : "rn" (fAndEfl),
657 "rn" (fOrEfl) );
658# endif
659# elif RT_INLINE_ASM_USES_INTRIN >= 15
660 fOldEfl = __readeflags();
661 __writeeflags((fOldEfl & fAndEfl) | fOrEfl);
662# else
663 __asm
664 {
665# ifdef RT_ARCH_AMD64
666 mov rdx, [fAndEfl]
667 mov rcx, [fOrEfl]
668 pushfq
669 mov rax, [rsp]
670 and rdx, rax
671 or rdx, rcx
672 mov [rsp], rdx
673 popfq
674 mov [fOldEfl], rax
675# else
676 mov edx, [fAndEfl]
677 mov ecx, [fOrEfl]
678 pushfd
679 mov eax, [esp]
680 and edx, eax
681 or edx, ecx
682 mov [esp], edx
683 popfd
684 mov [fOldEfl], eax
685# endif
686 }
687# endif
688 return fOldEfl;
689}
690#endif
691
692
693/**
694 * Modifies the [RE]FLAGS register by ORing in one or more flags.
695 * @returns Original value.
696 * @param fOrEfl The flags to be set (ORed in).
697 */
698#if RT_INLINE_ASM_EXTERNAL /*&& RT_INLINE_ASM_USES_INTRIN < 15 - buggy intrinsics in VC++ 2010, reordering/optimizers issues. */
699RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTREG) ASMAddFlags(RTCCUINTREG fOrEfl);
700#else
701DECLINLINE(RTCCUINTREG) ASMAddFlags(RTCCUINTREG fOrEfl)
702{
703 RTCCUINTREG fOldEfl;
704# if RT_INLINE_ASM_GNU_STYLE
705# ifdef RT_ARCH_AMD64
706 __asm__ __volatile__("pushfq\n\t"
707 "movq (%%rsp), %0\n\t"
708 "orq %1, (%%rsp)\n\t"
709 "popfq\n\t"
710 : "=&r" (fOldEfl)
711 : "rn" (fOrEfl) );
712# else
713 __asm__ __volatile__("pushfl\n\t"
714 "movl (%%esp), %0\n\t"
715 "orl %1, (%%esp)\n\t"
716 "popfl\n\t"
717 : "=&r" (fOldEfl)
718 : "rn" (fOrEfl) );
719# endif
720# elif RT_INLINE_ASM_USES_INTRIN >= 15
721 fOldEfl = __readeflags();
722 __writeeflags(fOldEfl | fOrEfl);
723# else
724 __asm
725 {
726# ifdef RT_ARCH_AMD64
727 mov rcx, [fOrEfl]
728 pushfq
729 mov rdx, [rsp]
730 or [rsp], rcx
731 popfq
732 mov [fOldEfl], rax
733# else
734 mov ecx, [fOrEfl]
735 pushfd
736 mov edx, [esp]
737 or [esp], ecx
738 popfd
739 mov [fOldEfl], eax
740# endif
741 }
742# endif
743 return fOldEfl;
744}
745#endif
746
747
748/**
749 * Modifies the [RE]FLAGS register by AND'ing out one or more flags.
750 * @returns Original value.
751 * @param fAndEfl The flags to keep.
752 */
753#if RT_INLINE_ASM_EXTERNAL /*&& RT_INLINE_ASM_USES_INTRIN < 15 - buggy intrinsics in VC++ 2010, reordering/optimizers issues. */
754RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTREG) ASMClearFlags(RTCCUINTREG fAndEfl);
755#else
756DECLINLINE(RTCCUINTREG) ASMClearFlags(RTCCUINTREG fAndEfl)
757{
758 RTCCUINTREG fOldEfl;
759# if RT_INLINE_ASM_GNU_STYLE
760# ifdef RT_ARCH_AMD64
761 __asm__ __volatile__("pushfq\n\t"
762 "movq (%%rsp), %0\n\t"
763 "andq %1, (%%rsp)\n\t"
764 "popfq\n\t"
765 : "=&r" (fOldEfl)
766 : "rn" (fAndEfl) );
767# else
768 __asm__ __volatile__("pushfl\n\t"
769 "movl (%%esp), %0\n\t"
770 "andl %1, (%%esp)\n\t"
771 "popfl\n\t"
772 : "=&r" (fOldEfl)
773 : "rn" (fAndEfl) );
774# endif
775# elif RT_INLINE_ASM_USES_INTRIN >= 15
776 fOldEfl = __readeflags();
777 __writeeflags(fOldEfl & fAndEfl);
778# else
779 __asm
780 {
781# ifdef RT_ARCH_AMD64
782 mov rdx, [fAndEfl]
783 pushfq
784 mov rdx, [rsp]
785 and [rsp], rdx
786 popfq
787 mov [fOldEfl], rax
788# else
789 mov edx, [fAndEfl]
790 pushfd
791 mov edx, [esp]
792 and [esp], edx
793 popfd
794 mov [fOldEfl], eax
795# endif
796 }
797# endif
798 return fOldEfl;
799}
800#endif
801
802
803/**
804 * Gets the content of the CPU timestamp counter register.
805 *
806 * @returns TSC.
807 */
808#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
809RT_ASM_DECL_PRAGMA_WATCOM(uint64_t) ASMReadTSC(void);
810#else
811DECLINLINE(uint64_t) ASMReadTSC(void)
812{
813 RTUINT64U u;
814# if RT_INLINE_ASM_GNU_STYLE
815 __asm__ __volatile__("rdtsc\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi));
816# else
817# if RT_INLINE_ASM_USES_INTRIN
818 u.u = __rdtsc();
819# else
820 __asm
821 {
822 rdtsc
823 mov [u.s.Lo], eax
824 mov [u.s.Hi], edx
825 }
826# endif
827# endif
828 return u.u;
829}
830#endif
831
832
833/**
834 * Gets the content of the CPU timestamp counter register and the
835 * assoicated AUX value.
836 *
837 * @returns TSC.
838 * @param puAux Where to store the AUX value.
839 */
840#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
841RT_ASM_DECL_PRAGMA_WATCOM(uint64_t) ASMReadTscWithAux(uint32_t RT_FAR *puAux);
842#else
843DECLINLINE(uint64_t) ASMReadTscWithAux(uint32_t RT_FAR *puAux)
844{
845 RTUINT64U u;
846# if RT_INLINE_ASM_GNU_STYLE
847 /* rdtscp is not supported by ancient linux build VM of course :-( */
848 /*__asm__ __volatile__("rdtscp\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi), "=c" (*puAux)); */
849 __asm__ __volatile__(".byte 0x0f,0x01,0xf9\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi), "=c" (*puAux));
850# else
851# if RT_INLINE_ASM_USES_INTRIN >= 15
852 u.u = __rdtscp(puAux);
853# else
854 __asm
855 {
856 rdtscp
857 mov [u.s.Lo], eax
858 mov [u.s.Hi], edx
859 mov eax, [puAux]
860 mov [eax], ecx
861 }
862# endif
863# endif
864 return u.u;
865}
866#endif
867
868
869/**
870 * Performs the cpuid instruction returning all registers.
871 *
872 * @param uOperator CPUID operation (eax).
873 * @param pvEAX Where to store eax.
874 * @param pvEBX Where to store ebx.
875 * @param pvECX Where to store ecx.
876 * @param pvEDX Where to store edx.
877 * @remark We're using void pointers to ease the use of special bitfield structures and such.
878 */
879#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
880DECLASM(void) ASMCpuId(uint32_t uOperator, void RT_FAR *pvEAX, void RT_FAR *pvEBX, void RT_FAR *pvECX, void RT_FAR *pvEDX);
881#else
882DECLINLINE(void) ASMCpuId(uint32_t uOperator, void RT_FAR *pvEAX, void RT_FAR *pvEBX, void RT_FAR *pvECX, void RT_FAR *pvEDX)
883{
884# if RT_INLINE_ASM_GNU_STYLE
885# ifdef RT_ARCH_AMD64
886 RTCCUINTREG uRAX, uRBX, uRCX, uRDX;
887 __asm__ __volatile__ ("cpuid\n\t"
888 : "=a" (uRAX),
889 "=b" (uRBX),
890 "=c" (uRCX),
891 "=d" (uRDX)
892 : "0" (uOperator), "2" (0));
893 *(uint32_t RT_FAR *)pvEAX = (uint32_t)uRAX;
894 *(uint32_t RT_FAR *)pvEBX = (uint32_t)uRBX;
895 *(uint32_t RT_FAR *)pvECX = (uint32_t)uRCX;
896 *(uint32_t RT_FAR *)pvEDX = (uint32_t)uRDX;
897# else
898 __asm__ __volatile__ ("xchgl %%ebx, %1\n\t"
899 "cpuid\n\t"
900 "xchgl %%ebx, %1\n\t"
901 : "=a" (*(uint32_t *)pvEAX),
902 "=r" (*(uint32_t *)pvEBX),
903 "=c" (*(uint32_t *)pvECX),
904 "=d" (*(uint32_t *)pvEDX)
905 : "0" (uOperator), "2" (0));
906# endif
907
908# elif RT_INLINE_ASM_USES_INTRIN
909 int aInfo[4];
910 __cpuid(aInfo, uOperator);
911 *(uint32_t RT_FAR *)pvEAX = aInfo[0];
912 *(uint32_t RT_FAR *)pvEBX = aInfo[1];
913 *(uint32_t RT_FAR *)pvECX = aInfo[2];
914 *(uint32_t RT_FAR *)pvEDX = aInfo[3];
915
916# else
917 uint32_t uEAX;
918 uint32_t uEBX;
919 uint32_t uECX;
920 uint32_t uEDX;
921 __asm
922 {
923 push ebx
924 mov eax, [uOperator]
925 cpuid
926 mov [uEAX], eax
927 mov [uEBX], ebx
928 mov [uECX], ecx
929 mov [uEDX], edx
930 pop ebx
931 }
932 *(uint32_t RT_FAR *)pvEAX = uEAX;
933 *(uint32_t RT_FAR *)pvEBX = uEBX;
934 *(uint32_t RT_FAR *)pvECX = uECX;
935 *(uint32_t RT_FAR *)pvEDX = uEDX;
936# endif
937}
938#endif
939
940
941/**
942 * Performs the CPUID instruction with EAX and ECX input returning ALL output
943 * registers.
944 *
945 * @param uOperator CPUID operation (eax).
946 * @param uIdxECX ecx index
947 * @param pvEAX Where to store eax.
948 * @param pvEBX Where to store ebx.
949 * @param pvECX Where to store ecx.
950 * @param pvEDX Where to store edx.
951 * @remark We're using void pointers to ease the use of special bitfield structures and such.
952 */
953#if RT_INLINE_ASM_EXTERNAL || RT_INLINE_ASM_USES_INTRIN
954DECLASM(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void RT_FAR *pvEAX, void RT_FAR *pvEBX, void RT_FAR *pvECX, void RT_FAR *pvEDX);
955#else
956DECLINLINE(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void RT_FAR *pvEAX, void RT_FAR *pvEBX, void RT_FAR *pvECX, void RT_FAR *pvEDX)
957{
958# if RT_INLINE_ASM_GNU_STYLE
959# ifdef RT_ARCH_AMD64
960 RTCCUINTREG uRAX, uRBX, uRCX, uRDX;
961 __asm__ ("cpuid\n\t"
962 : "=a" (uRAX),
963 "=b" (uRBX),
964 "=c" (uRCX),
965 "=d" (uRDX)
966 : "0" (uOperator),
967 "2" (uIdxECX));
968 *(uint32_t RT_FAR *)pvEAX = (uint32_t)uRAX;
969 *(uint32_t RT_FAR *)pvEBX = (uint32_t)uRBX;
970 *(uint32_t RT_FAR *)pvECX = (uint32_t)uRCX;
971 *(uint32_t RT_FAR *)pvEDX = (uint32_t)uRDX;
972# else
973 __asm__ ("xchgl %%ebx, %1\n\t"
974 "cpuid\n\t"
975 "xchgl %%ebx, %1\n\t"
976 : "=a" (*(uint32_t *)pvEAX),
977 "=r" (*(uint32_t *)pvEBX),
978 "=c" (*(uint32_t *)pvECX),
979 "=d" (*(uint32_t *)pvEDX)
980 : "0" (uOperator),
981 "2" (uIdxECX));
982# endif
983
984# elif RT_INLINE_ASM_USES_INTRIN
985 int aInfo[4];
986 __cpuidex(aInfo, uOperator, uIdxECX);
987 *(uint32_t RT_FAR *)pvEAX = aInfo[0];
988 *(uint32_t RT_FAR *)pvEBX = aInfo[1];
989 *(uint32_t RT_FAR *)pvECX = aInfo[2];
990 *(uint32_t RT_FAR *)pvEDX = aInfo[3];
991
992# else
993 uint32_t uEAX;
994 uint32_t uEBX;
995 uint32_t uECX;
996 uint32_t uEDX;
997 __asm
998 {
999 push ebx
1000 mov eax, [uOperator]
1001 mov ecx, [uIdxECX]
1002 cpuid
1003 mov [uEAX], eax
1004 mov [uEBX], ebx
1005 mov [uECX], ecx
1006 mov [uEDX], edx
1007 pop ebx
1008 }
1009 *(uint32_t RT_FAR *)pvEAX = uEAX;
1010 *(uint32_t RT_FAR *)pvEBX = uEBX;
1011 *(uint32_t RT_FAR *)pvECX = uECX;
1012 *(uint32_t RT_FAR *)pvEDX = uEDX;
1013# endif
1014}
1015#endif
1016
1017
1018/**
1019 * CPUID variant that initializes all 4 registers before the CPUID instruction.
1020 *
1021 * @returns The EAX result value.
1022 * @param uOperator CPUID operation (eax).
1023 * @param uInitEBX The value to assign EBX prior to the CPUID instruction.
1024 * @param uInitECX The value to assign ECX prior to the CPUID instruction.
1025 * @param uInitEDX The value to assign EDX prior to the CPUID instruction.
1026 * @param pvEAX Where to store eax. Optional.
1027 * @param pvEBX Where to store ebx. Optional.
1028 * @param pvECX Where to store ecx. Optional.
1029 * @param pvEDX Where to store edx. Optional.
1030 */
1031DECLASM(uint32_t) ASMCpuIdExSlow(uint32_t uOperator, uint32_t uInitEBX, uint32_t uInitECX, uint32_t uInitEDX,
1032 void RT_FAR *pvEAX, void RT_FAR *pvEBX, void RT_FAR *pvECX, void RT_FAR *pvEDX);
1033
1034
1035/**
1036 * Performs the cpuid instruction returning ecx and edx.
1037 *
1038 * @param uOperator CPUID operation (eax).
1039 * @param pvECX Where to store ecx.
1040 * @param pvEDX Where to store edx.
1041 * @remark We're using void pointers to ease the use of special bitfield structures and such.
1042 */
1043#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1044RT_ASM_DECL_PRAGMA_WATCOM(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void RT_FAR *pvECX, void RT_FAR *pvEDX);
1045#else
1046DECLINLINE(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void RT_FAR *pvECX, void RT_FAR *pvEDX)
1047{
1048 uint32_t uEBX;
1049 ASMCpuId(uOperator, &uOperator, &uEBX, pvECX, pvEDX);
1050}
1051#endif
1052
1053
1054/**
1055 * Performs the cpuid instruction returning eax.
1056 *
1057 * @param uOperator CPUID operation (eax).
1058 * @returns EAX after cpuid operation.
1059 */
1060#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1061RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMCpuId_EAX(uint32_t uOperator);
1062#else
1063DECLINLINE(uint32_t) ASMCpuId_EAX(uint32_t uOperator)
1064{
1065 RTCCUINTREG xAX;
1066# if RT_INLINE_ASM_GNU_STYLE
1067# ifdef RT_ARCH_AMD64
1068 __asm__ ("cpuid"
1069 : "=a" (xAX)
1070 : "0" (uOperator)
1071 : "rbx", "rcx", "rdx");
1072# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1073 __asm__ ("push %%ebx\n\t"
1074 "cpuid\n\t"
1075 "pop %%ebx\n\t"
1076 : "=a" (xAX)
1077 : "0" (uOperator)
1078 : "ecx", "edx");
1079# else
1080 __asm__ ("cpuid"
1081 : "=a" (xAX)
1082 : "0" (uOperator)
1083 : "edx", "ecx", "ebx");
1084# endif
1085
1086# elif RT_INLINE_ASM_USES_INTRIN
1087 int aInfo[4];
1088 __cpuid(aInfo, uOperator);
1089 xAX = aInfo[0];
1090
1091# else
1092 __asm
1093 {
1094 push ebx
1095 mov eax, [uOperator]
1096 cpuid
1097 mov [xAX], eax
1098 pop ebx
1099 }
1100# endif
1101 return (uint32_t)xAX;
1102}
1103#endif
1104
1105
1106/**
1107 * Performs the cpuid instruction returning ebx.
1108 *
1109 * @param uOperator CPUID operation (eax).
1110 * @returns EBX after cpuid operation.
1111 */
1112#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1113RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMCpuId_EBX(uint32_t uOperator);
1114#else
1115DECLINLINE(uint32_t) ASMCpuId_EBX(uint32_t uOperator)
1116{
1117 RTCCUINTREG xBX;
1118# if RT_INLINE_ASM_GNU_STYLE
1119# ifdef RT_ARCH_AMD64
1120 RTCCUINTREG uSpill;
1121 __asm__ ("cpuid"
1122 : "=a" (uSpill),
1123 "=b" (xBX)
1124 : "0" (uOperator)
1125 : "rdx", "rcx");
1126# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1127 __asm__ ("push %%ebx\n\t"
1128 "cpuid\n\t"
1129 "mov %%ebx, %%edx\n\t"
1130 "pop %%ebx\n\t"
1131 : "=a" (uOperator),
1132 "=d" (xBX)
1133 : "0" (uOperator)
1134 : "ecx");
1135# else
1136 __asm__ ("cpuid"
1137 : "=a" (uOperator),
1138 "=b" (xBX)
1139 : "0" (uOperator)
1140 : "edx", "ecx");
1141# endif
1142
1143# elif RT_INLINE_ASM_USES_INTRIN
1144 int aInfo[4];
1145 __cpuid(aInfo, uOperator);
1146 xBX = aInfo[1];
1147
1148# else
1149 __asm
1150 {
1151 push ebx
1152 mov eax, [uOperator]
1153 cpuid
1154 mov [xBX], ebx
1155 pop ebx
1156 }
1157# endif
1158 return (uint32_t)xBX;
1159}
1160#endif
1161
1162
1163/**
1164 * Performs the cpuid instruction returning ecx.
1165 *
1166 * @param uOperator CPUID operation (eax).
1167 * @returns ECX after cpuid operation.
1168 */
1169#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1170RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMCpuId_ECX(uint32_t uOperator);
1171#else
1172DECLINLINE(uint32_t) ASMCpuId_ECX(uint32_t uOperator)
1173{
1174 RTCCUINTREG xCX;
1175# if RT_INLINE_ASM_GNU_STYLE
1176# ifdef RT_ARCH_AMD64
1177 RTCCUINTREG uSpill;
1178 __asm__ ("cpuid"
1179 : "=a" (uSpill),
1180 "=c" (xCX)
1181 : "0" (uOperator)
1182 : "rbx", "rdx");
1183# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1184 __asm__ ("push %%ebx\n\t"
1185 "cpuid\n\t"
1186 "pop %%ebx\n\t"
1187 : "=a" (uOperator),
1188 "=c" (xCX)
1189 : "0" (uOperator)
1190 : "edx");
1191# else
1192 __asm__ ("cpuid"
1193 : "=a" (uOperator),
1194 "=c" (xCX)
1195 : "0" (uOperator)
1196 : "ebx", "edx");
1197
1198# endif
1199
1200# elif RT_INLINE_ASM_USES_INTRIN
1201 int aInfo[4];
1202 __cpuid(aInfo, uOperator);
1203 xCX = aInfo[2];
1204
1205# else
1206 __asm
1207 {
1208 push ebx
1209 mov eax, [uOperator]
1210 cpuid
1211 mov [xCX], ecx
1212 pop ebx
1213 }
1214# endif
1215 return (uint32_t)xCX;
1216}
1217#endif
1218
1219
1220/**
1221 * Performs the cpuid instruction returning edx.
1222 *
1223 * @param uOperator CPUID operation (eax).
1224 * @returns EDX after cpuid operation.
1225 */
1226#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1227RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMCpuId_EDX(uint32_t uOperator);
1228#else
1229DECLINLINE(uint32_t) ASMCpuId_EDX(uint32_t uOperator)
1230{
1231 RTCCUINTREG xDX;
1232# if RT_INLINE_ASM_GNU_STYLE
1233# ifdef RT_ARCH_AMD64
1234 RTCCUINTREG uSpill;
1235 __asm__ ("cpuid"
1236 : "=a" (uSpill),
1237 "=d" (xDX)
1238 : "0" (uOperator)
1239 : "rbx", "rcx");
1240# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1241 __asm__ ("push %%ebx\n\t"
1242 "cpuid\n\t"
1243 "pop %%ebx\n\t"
1244 : "=a" (uOperator),
1245 "=d" (xDX)
1246 : "0" (uOperator)
1247 : "ecx");
1248# else
1249 __asm__ ("cpuid"
1250 : "=a" (uOperator),
1251 "=d" (xDX)
1252 : "0" (uOperator)
1253 : "ebx", "ecx");
1254# endif
1255
1256# elif RT_INLINE_ASM_USES_INTRIN
1257 int aInfo[4];
1258 __cpuid(aInfo, uOperator);
1259 xDX = aInfo[3];
1260
1261# else
1262 __asm
1263 {
1264 push ebx
1265 mov eax, [uOperator]
1266 cpuid
1267 mov [xDX], edx
1268 pop ebx
1269 }
1270# endif
1271 return (uint32_t)xDX;
1272}
1273#endif
1274
1275
1276/**
1277 * Checks if the current CPU supports CPUID.
1278 *
1279 * @returns true if CPUID is supported.
1280 */
1281#ifdef __WATCOMC__
1282DECLASM(bool) ASMHasCpuId(void);
1283#else
1284DECLINLINE(bool) ASMHasCpuId(void)
1285{
1286# ifdef RT_ARCH_AMD64
1287 return true; /* ASSUME that all amd64 compatible CPUs have cpuid. */
1288# else /* !RT_ARCH_AMD64 */
1289 bool fRet = false;
1290# if RT_INLINE_ASM_GNU_STYLE
1291 uint32_t u1;
1292 uint32_t u2;
1293 __asm__ ("pushf\n\t"
1294 "pop %1\n\t"
1295 "mov %1, %2\n\t"
1296 "xorl $0x200000, %1\n\t"
1297 "push %1\n\t"
1298 "popf\n\t"
1299 "pushf\n\t"
1300 "pop %1\n\t"
1301 "cmpl %1, %2\n\t"
1302 "setne %0\n\t"
1303 "push %2\n\t"
1304 "popf\n\t"
1305 : "=m" (fRet), "=r" (u1), "=r" (u2));
1306# else
1307 __asm
1308 {
1309 pushfd
1310 pop eax
1311 mov ebx, eax
1312 xor eax, 0200000h
1313 push eax
1314 popfd
1315 pushfd
1316 pop eax
1317 cmp eax, ebx
1318 setne fRet
1319 push ebx
1320 popfd
1321 }
1322# endif
1323 return fRet;
1324# endif /* !RT_ARCH_AMD64 */
1325}
1326#endif
1327
1328
1329/**
1330 * Gets the APIC ID of the current CPU.
1331 *
1332 * @returns the APIC ID.
1333 */
1334#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1335RT_ASM_DECL_PRAGMA_WATCOM(uint8_t) ASMGetApicId(void);
1336#else
1337DECLINLINE(uint8_t) ASMGetApicId(void)
1338{
1339 RTCCUINTREG xBX;
1340# if RT_INLINE_ASM_GNU_STYLE
1341# ifdef RT_ARCH_AMD64
1342 RTCCUINTREG uSpill;
1343 __asm__ __volatile__ ("cpuid"
1344 : "=a" (uSpill),
1345 "=b" (xBX)
1346 : "0" (1)
1347 : "rcx", "rdx");
1348# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1349 RTCCUINTREG uSpill;
1350 __asm__ __volatile__ ("mov %%ebx,%1\n\t"
1351 "cpuid\n\t"
1352 "xchgl %%ebx,%1\n\t"
1353 : "=a" (uSpill),
1354 "=rm" (xBX)
1355 : "0" (1)
1356 : "ecx", "edx");
1357# else
1358 RTCCUINTREG uSpill;
1359 __asm__ __volatile__ ("cpuid"
1360 : "=a" (uSpill),
1361 "=b" (xBX)
1362 : "0" (1)
1363 : "ecx", "edx");
1364# endif
1365
1366# elif RT_INLINE_ASM_USES_INTRIN
1367 int aInfo[4];
1368 __cpuid(aInfo, 1);
1369 xBX = aInfo[1];
1370
1371# else
1372 __asm
1373 {
1374 push ebx
1375 mov eax, 1
1376 cpuid
1377 mov [xBX], ebx
1378 pop ebx
1379 }
1380# endif
1381 return (uint8_t)(xBX >> 24);
1382}
1383#endif
1384
1385
1386/**
1387 * Gets the APIC ID of the current CPU using leaf 0xb.
1388 *
1389 * @returns the APIC ID.
1390 */
1391#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 16 /*?*/
1392RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMGetApicIdExt0B(void);
1393#else
1394DECLINLINE(uint32_t) ASMGetApicIdExt0B(void)
1395{
1396# if RT_INLINE_ASM_GNU_STYLE
1397 RTCCUINTREG xDX;
1398# ifdef RT_ARCH_AMD64
1399 RTCCUINTREG uSpillEax, uSpillEcx;
1400 __asm__ __volatile__ ("cpuid"
1401 : "=a" (uSpillEax),
1402 "=c" (uSpillEcx),
1403 "=d" (xDX)
1404 : "0" (0xb),
1405 "1" (0)
1406 : "rbx");
1407# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1408 RTCCUINTREG uSpillEax, uSpillEcx, uSpillEbx;
1409 __asm__ __volatile__ ("mov %%ebx,%2\n\t"
1410 "cpuid\n\t"
1411 "xchgl %%ebx,%2\n\t"
1412 : "=a" (uSpillEax),
1413 "=c" (uSpillEcx),
1414 "=rm" (uSpillEbx),
1415 "=d" (xDX)
1416 : "0" (0xb),
1417 "1" (0));
1418# else
1419 RTCCUINTREG uSpillEax, uSpillEcx;
1420 __asm__ __volatile__ ("cpuid"
1421 : "=a" (uSpillEax),
1422 "=c" (uSpillEcx),
1423 "=d" (xDX)
1424 : "0" (0xb),
1425 "1" (0)
1426 : "ebx");
1427# endif
1428 return (uint32_t)xDX;
1429
1430# elif RT_INLINE_ASM_USES_INTRIN >= 16 /*?*/
1431
1432 int aInfo[4];
1433 __cpuidex(aInfo, 0xb, 0);
1434 return aInfo[3];
1435
1436# else
1437 RTCCUINTREG xDX;
1438 __asm
1439 {
1440 push ebx
1441 mov eax, 0xb
1442 xor ecx, ecx
1443 cpuid
1444 mov [xDX], edx
1445 pop ebx
1446 }
1447 return (uint32_t)xDX;
1448# endif
1449}
1450#endif
1451
1452
1453/**
1454 * Gets the APIC ID of the current CPU using leaf 8000001E.
1455 *
1456 * @returns the APIC ID.
1457 */
1458DECLINLINE(uint32_t) ASMGetApicIdExt8000001E(void)
1459{
1460 return ASMCpuId_EAX(0x8000001e);
1461}
1462
1463
1464/**
1465 * Tests if it a genuine Intel CPU based on the ASMCpuId(0) output.
1466 *
1467 * @returns true/false.
1468 * @param uEBX EBX return from ASMCpuId(0)
1469 * @param uECX ECX return from ASMCpuId(0)
1470 * @param uEDX EDX return from ASMCpuId(0)
1471 */
1472DECLINLINE(bool) ASMIsIntelCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1473{
1474 /* 'GenuineIntel' */
1475 return uEBX == UINT32_C(0x756e6547) /* 'Genu' */
1476 && uEDX == UINT32_C(0x49656e69) /* 'ineI' */
1477 && uECX == UINT32_C(0x6c65746e); /* 'ntel' */
1478}
1479
1480
1481/**
1482 * Tests if this is a genuine Intel CPU.
1483 *
1484 * @returns true/false.
1485 * @remarks ASSUMES that cpuid is supported by the CPU.
1486 */
1487DECLINLINE(bool) ASMIsIntelCpu(void)
1488{
1489 uint32_t uEAX, uEBX, uECX, uEDX;
1490 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1491 return ASMIsIntelCpuEx(uEBX, uECX, uEDX);
1492}
1493
1494
1495/**
1496 * Tests if it an authentic AMD CPU based on the ASMCpuId(0) output.
1497 *
1498 * @returns true/false.
1499 * @param uEBX EBX return from ASMCpuId(0)
1500 * @param uECX ECX return from ASMCpuId(0)
1501 * @param uEDX EDX return from ASMCpuId(0)
1502 */
1503DECLINLINE(bool) ASMIsAmdCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1504{
1505 /* 'AuthenticAMD' */
1506 return uEBX == UINT32_C(0x68747541) /* 'Auth' */
1507 && uEDX == UINT32_C(0x69746e65) /* 'enti' */
1508 && uECX == UINT32_C(0x444d4163); /* 'dAMD' */
1509}
1510
1511
1512/**
1513 * Tests if this is an authentic AMD CPU.
1514 *
1515 * @returns true/false.
1516 * @remarks ASSUMES that cpuid is supported by the CPU.
1517 */
1518DECLINLINE(bool) ASMIsAmdCpu(void)
1519{
1520 uint32_t uEAX, uEBX, uECX, uEDX;
1521 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1522 return ASMIsAmdCpuEx(uEBX, uECX, uEDX);
1523}
1524
1525
1526/**
1527 * Tests if it a centaur hauling VIA CPU based on the ASMCpuId(0) output.
1528 *
1529 * @returns true/false.
1530 * @param uEBX EBX return from ASMCpuId(0).
1531 * @param uECX ECX return from ASMCpuId(0).
1532 * @param uEDX EDX return from ASMCpuId(0).
1533 */
1534DECLINLINE(bool) ASMIsViaCentaurCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1535{
1536 /* 'CentaurHauls' */
1537 return uEBX == UINT32_C(0x746e6543) /* 'Cent' */
1538 && uEDX == UINT32_C(0x48727561) /* 'aurH' */
1539 && uECX == UINT32_C(0x736c7561); /* 'auls' */
1540}
1541
1542
1543/**
1544 * Tests if this is a centaur hauling VIA CPU.
1545 *
1546 * @returns true/false.
1547 * @remarks ASSUMES that cpuid is supported by the CPU.
1548 */
1549DECLINLINE(bool) ASMIsViaCentaurCpu(void)
1550{
1551 uint32_t uEAX, uEBX, uECX, uEDX;
1552 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1553 return ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX);
1554}
1555
1556
1557/**
1558 * Tests if it a Shanghai CPU based on the ASMCpuId(0) output.
1559 *
1560 * @returns true/false.
1561 * @param uEBX EBX return from ASMCpuId(0).
1562 * @param uECX ECX return from ASMCpuId(0).
1563 * @param uEDX EDX return from ASMCpuId(0).
1564 */
1565DECLINLINE(bool) ASMIsShanghaiCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1566{
1567 /* ' Shanghai ' */
1568 return uEBX == UINT32_C(0x68532020) /* ' Sh' */
1569 && uEDX == UINT32_C(0x68676e61) /* 'angh' */
1570 && uECX == UINT32_C(0x20206961); /* 'ai ' */
1571}
1572
1573
1574/**
1575 * Tests if this is a Shanghai CPU.
1576 *
1577 * @returns true/false.
1578 * @remarks ASSUMES that cpuid is supported by the CPU.
1579 */
1580DECLINLINE(bool) ASMIsShanghaiCpu(void)
1581{
1582 uint32_t uEAX, uEBX, uECX, uEDX;
1583 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1584 return ASMIsShanghaiCpuEx(uEBX, uECX, uEDX);
1585}
1586
1587
1588/**
1589 * Tests if it a genuine Hygon CPU based on the ASMCpuId(0) output.
1590 *
1591 * @returns true/false.
1592 * @param uEBX EBX return from ASMCpuId(0)
1593 * @param uECX ECX return from ASMCpuId(0)
1594 * @param uEDX EDX return from ASMCpuId(0)
1595 */
1596DECLINLINE(bool) ASMIsHygonCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1597{
1598 /* 'HygonGenuine' */
1599 return uEBX == UINT32_C(0x6f677948) /* Hygo */
1600 && uECX == UINT32_C(0x656e6975) /* uine */
1601 && uEDX == UINT32_C(0x6e65476e); /* nGen */
1602}
1603
1604
1605/**
1606 * Tests if this is a genuine Hygon CPU.
1607 *
1608 * @returns true/false.
1609 * @remarks ASSUMES that cpuid is supported by the CPU.
1610 */
1611DECLINLINE(bool) ASMIsHygonCpu(void)
1612{
1613 uint32_t uEAX, uEBX, uECX, uEDX;
1614 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1615 return ASMIsHygonCpuEx(uEBX, uECX, uEDX);
1616}
1617
1618
1619/**
1620 * Checks whether ASMCpuId_EAX(0x00000000) indicates a valid range.
1621 *
1622 *
1623 * @returns true/false.
1624 * @param uEAX The EAX value of CPUID leaf 0x00000000.
1625 *
1626 * @note This only succeeds if there are at least two leaves in the range.
1627 * @remarks The upper range limit is just some half reasonable value we've
1628 * picked out of thin air.
1629 */
1630DECLINLINE(bool) ASMIsValidStdRange(uint32_t uEAX)
1631{
1632 return uEAX >= UINT32_C(0x00000001) && uEAX <= UINT32_C(0x000fffff);
1633}
1634
1635
1636/**
1637 * Checks whether ASMCpuId_EAX(0x80000000) indicates a valid range.
1638 *
1639 * This only succeeds if there are at least two leaves in the range.
1640 *
1641 * @returns true/false.
1642 * @param uEAX The EAX value of CPUID leaf 0x80000000.
1643 *
1644 * @note This only succeeds if there are at least two leaves in the range.
1645 * @remarks The upper range limit is just some half reasonable value we've
1646 * picked out of thin air.
1647 */
1648DECLINLINE(bool) ASMIsValidExtRange(uint32_t uEAX)
1649{
1650 return uEAX >= UINT32_C(0x80000001) && uEAX <= UINT32_C(0x800fffff);
1651}
1652
1653
1654/**
1655 * Checks whether ASMCpuId_EAX(0x40000000) indicates a valid range.
1656 *
1657 * This only succeeds if there are at least two leaves in the range.
1658 *
1659 * @returns true/false.
1660 * @param uEAX The EAX value of CPUID leaf 0x40000000.
1661 *
1662 * @note Unlike ASMIsValidStdRange() and ASMIsValidExtRange(), a single leaf
1663 * is okay here. So, you always need to check the range.
1664 * @remarks The upper range limit is take from the intel docs.
1665 */
1666DECLINLINE(bool) ASMIsValidHypervisorRange(uint32_t uEAX)
1667{
1668 return uEAX >= UINT32_C(0x40000000) && uEAX <= UINT32_C(0x4fffffff);
1669}
1670
1671
1672/**
1673 * Extracts the CPU family from ASMCpuId(1) or ASMCpuId(0x80000001)
1674 *
1675 * @returns Family.
1676 * @param uEAX EAX return from ASMCpuId(1) or ASMCpuId(0x80000001).
1677 */
1678DECLINLINE(uint32_t) ASMGetCpuFamily(uint32_t uEAX)
1679{
1680 return ((uEAX >> 8) & 0xf) == 0xf
1681 ? ((uEAX >> 20) & 0x7f) + 0xf
1682 : ((uEAX >> 8) & 0xf);
1683}
1684
1685
1686/**
1687 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), Intel variant.
1688 *
1689 * @returns Model.
1690 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1691 */
1692DECLINLINE(uint32_t) ASMGetCpuModelIntel(uint32_t uEAX)
1693{
1694 return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6) /* family! */
1695 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
1696 : ((uEAX >> 4) & 0xf);
1697}
1698
1699
1700/**
1701 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), AMD variant.
1702 *
1703 * @returns Model.
1704 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1705 */
1706DECLINLINE(uint32_t) ASMGetCpuModelAMD(uint32_t uEAX)
1707{
1708 return ((uEAX >> 8) & 0xf) == 0xf
1709 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
1710 : ((uEAX >> 4) & 0xf);
1711}
1712
1713
1714/**
1715 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001)
1716 *
1717 * @returns Model.
1718 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1719 * @param fIntel Whether it's an intel CPU. Use ASMIsIntelCpuEx() or ASMIsIntelCpu().
1720 */
1721DECLINLINE(uint32_t) ASMGetCpuModel(uint32_t uEAX, bool fIntel)
1722{
1723 return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6 && fIntel) /* family! */
1724 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
1725 : ((uEAX >> 4) & 0xf);
1726}
1727
1728
1729/**
1730 * Extracts the CPU stepping from ASMCpuId(1) or ASMCpuId(0x80000001)
1731 *
1732 * @returns Model.
1733 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1734 */
1735DECLINLINE(uint32_t) ASMGetCpuStepping(uint32_t uEAX)
1736{
1737 return uEAX & 0xf;
1738}
1739
1740
1741/**
1742 * Get cr0.
1743 * @returns cr0.
1744 */
1745#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1746RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetCR0(void);
1747#else
1748DECLINLINE(RTCCUINTXREG) ASMGetCR0(void)
1749{
1750 RTCCUINTXREG uCR0;
1751# if RT_INLINE_ASM_USES_INTRIN
1752 uCR0 = __readcr0();
1753
1754# elif RT_INLINE_ASM_GNU_STYLE
1755# ifdef RT_ARCH_AMD64
1756 __asm__ __volatile__("movq %%cr0, %0\t\n" : "=r" (uCR0));
1757# else
1758 __asm__ __volatile__("movl %%cr0, %0\t\n" : "=r" (uCR0));
1759# endif
1760# else
1761 __asm
1762 {
1763# ifdef RT_ARCH_AMD64
1764 mov rax, cr0
1765 mov [uCR0], rax
1766# else
1767 mov eax, cr0
1768 mov [uCR0], eax
1769# endif
1770 }
1771# endif
1772 return uCR0;
1773}
1774#endif
1775
1776
1777/**
1778 * Sets the CR0 register.
1779 * @param uCR0 The new CR0 value.
1780 */
1781#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1782RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetCR0(RTCCUINTXREG uCR0);
1783#else
1784DECLINLINE(void) ASMSetCR0(RTCCUINTXREG uCR0)
1785{
1786# if RT_INLINE_ASM_USES_INTRIN
1787 __writecr0(uCR0);
1788
1789# elif RT_INLINE_ASM_GNU_STYLE
1790# ifdef RT_ARCH_AMD64
1791 __asm__ __volatile__("movq %0, %%cr0\n\t" :: "r" (uCR0));
1792# else
1793 __asm__ __volatile__("movl %0, %%cr0\n\t" :: "r" (uCR0));
1794# endif
1795# else
1796 __asm
1797 {
1798# ifdef RT_ARCH_AMD64
1799 mov rax, [uCR0]
1800 mov cr0, rax
1801# else
1802 mov eax, [uCR0]
1803 mov cr0, eax
1804# endif
1805 }
1806# endif
1807}
1808#endif
1809
1810
1811/**
1812 * Get cr2.
1813 * @returns cr2.
1814 */
1815#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1816RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetCR2(void);
1817#else
1818DECLINLINE(RTCCUINTXREG) ASMGetCR2(void)
1819{
1820 RTCCUINTXREG uCR2;
1821# if RT_INLINE_ASM_USES_INTRIN
1822 uCR2 = __readcr2();
1823
1824# elif RT_INLINE_ASM_GNU_STYLE
1825# ifdef RT_ARCH_AMD64
1826 __asm__ __volatile__("movq %%cr2, %0\t\n" : "=r" (uCR2));
1827# else
1828 __asm__ __volatile__("movl %%cr2, %0\t\n" : "=r" (uCR2));
1829# endif
1830# else
1831 __asm
1832 {
1833# ifdef RT_ARCH_AMD64
1834 mov rax, cr2
1835 mov [uCR2], rax
1836# else
1837 mov eax, cr2
1838 mov [uCR2], eax
1839# endif
1840 }
1841# endif
1842 return uCR2;
1843}
1844#endif
1845
1846
1847/**
1848 * Sets the CR2 register.
1849 * @param uCR2 The new CR0 value.
1850 */
1851#if RT_INLINE_ASM_EXTERNAL
1852RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetCR2(RTCCUINTXREG uCR2);
1853#else
1854DECLINLINE(void) ASMSetCR2(RTCCUINTXREG uCR2)
1855{
1856# if RT_INLINE_ASM_GNU_STYLE
1857# ifdef RT_ARCH_AMD64
1858 __asm__ __volatile__("movq %0, %%cr2\n\t" :: "r" (uCR2));
1859# else
1860 __asm__ __volatile__("movl %0, %%cr2\n\t" :: "r" (uCR2));
1861# endif
1862# else
1863 __asm
1864 {
1865# ifdef RT_ARCH_AMD64
1866 mov rax, [uCR2]
1867 mov cr2, rax
1868# else
1869 mov eax, [uCR2]
1870 mov cr2, eax
1871# endif
1872 }
1873# endif
1874}
1875#endif
1876
1877
1878/**
1879 * Get cr3.
1880 * @returns cr3.
1881 */
1882#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1883RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetCR3(void);
1884#else
1885DECLINLINE(RTCCUINTXREG) ASMGetCR3(void)
1886{
1887 RTCCUINTXREG uCR3;
1888# if RT_INLINE_ASM_USES_INTRIN
1889 uCR3 = __readcr3();
1890
1891# elif RT_INLINE_ASM_GNU_STYLE
1892# ifdef RT_ARCH_AMD64
1893 __asm__ __volatile__("movq %%cr3, %0\t\n" : "=r" (uCR3));
1894# else
1895 __asm__ __volatile__("movl %%cr3, %0\t\n" : "=r" (uCR3));
1896# endif
1897# else
1898 __asm
1899 {
1900# ifdef RT_ARCH_AMD64
1901 mov rax, cr3
1902 mov [uCR3], rax
1903# else
1904 mov eax, cr3
1905 mov [uCR3], eax
1906# endif
1907 }
1908# endif
1909 return uCR3;
1910}
1911#endif
1912
1913
1914/**
1915 * Sets the CR3 register.
1916 *
1917 * @param uCR3 New CR3 value.
1918 */
1919#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1920RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetCR3(RTCCUINTXREG uCR3);
1921#else
1922DECLINLINE(void) ASMSetCR3(RTCCUINTXREG uCR3)
1923{
1924# if RT_INLINE_ASM_USES_INTRIN
1925 __writecr3(uCR3);
1926
1927# elif RT_INLINE_ASM_GNU_STYLE
1928# ifdef RT_ARCH_AMD64
1929 __asm__ __volatile__("movq %0, %%cr3\n\t" : : "r" (uCR3));
1930# else
1931 __asm__ __volatile__("movl %0, %%cr3\n\t" : : "r" (uCR3));
1932# endif
1933# else
1934 __asm
1935 {
1936# ifdef RT_ARCH_AMD64
1937 mov rax, [uCR3]
1938 mov cr3, rax
1939# else
1940 mov eax, [uCR3]
1941 mov cr3, eax
1942# endif
1943 }
1944# endif
1945}
1946#endif
1947
1948
1949/**
1950 * Reloads the CR3 register.
1951 */
1952#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1953RT_ASM_DECL_PRAGMA_WATCOM(void) ASMReloadCR3(void);
1954#else
1955DECLINLINE(void) ASMReloadCR3(void)
1956{
1957# if RT_INLINE_ASM_USES_INTRIN
1958 __writecr3(__readcr3());
1959
1960# elif RT_INLINE_ASM_GNU_STYLE
1961 RTCCUINTXREG u;
1962# ifdef RT_ARCH_AMD64
1963 __asm__ __volatile__("movq %%cr3, %0\n\t"
1964 "movq %0, %%cr3\n\t"
1965 : "=r" (u));
1966# else
1967 __asm__ __volatile__("movl %%cr3, %0\n\t"
1968 "movl %0, %%cr3\n\t"
1969 : "=r" (u));
1970# endif
1971# else
1972 __asm
1973 {
1974# ifdef RT_ARCH_AMD64
1975 mov rax, cr3
1976 mov cr3, rax
1977# else
1978 mov eax, cr3
1979 mov cr3, eax
1980# endif
1981 }
1982# endif
1983}
1984#endif
1985
1986
1987/**
1988 * Get cr4.
1989 * @returns cr4.
1990 */
1991#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1992RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetCR4(void);
1993#else
1994DECLINLINE(RTCCUINTXREG) ASMGetCR4(void)
1995{
1996 RTCCUINTXREG uCR4;
1997# if RT_INLINE_ASM_USES_INTRIN
1998 uCR4 = __readcr4();
1999
2000# elif RT_INLINE_ASM_GNU_STYLE
2001# ifdef RT_ARCH_AMD64
2002 __asm__ __volatile__("movq %%cr4, %0\t\n" : "=r" (uCR4));
2003# else
2004 __asm__ __volatile__("movl %%cr4, %0\t\n" : "=r" (uCR4));
2005# endif
2006# else
2007 __asm
2008 {
2009# ifdef RT_ARCH_AMD64
2010 mov rax, cr4
2011 mov [uCR4], rax
2012# else
2013 push eax /* just in case */
2014 /*mov eax, cr4*/
2015 _emit 0x0f
2016 _emit 0x20
2017 _emit 0xe0
2018 mov [uCR4], eax
2019 pop eax
2020# endif
2021 }
2022# endif
2023 return uCR4;
2024}
2025#endif
2026
2027
2028/**
2029 * Sets the CR4 register.
2030 *
2031 * @param uCR4 New CR4 value.
2032 */
2033#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2034RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetCR4(RTCCUINTXREG uCR4);
2035#else
2036DECLINLINE(void) ASMSetCR4(RTCCUINTXREG uCR4)
2037{
2038# if RT_INLINE_ASM_USES_INTRIN
2039 __writecr4(uCR4);
2040
2041# elif RT_INLINE_ASM_GNU_STYLE
2042# ifdef RT_ARCH_AMD64
2043 __asm__ __volatile__("movq %0, %%cr4\n\t" : : "r" (uCR4));
2044# else
2045 __asm__ __volatile__("movl %0, %%cr4\n\t" : : "r" (uCR4));
2046# endif
2047# else
2048 __asm
2049 {
2050# ifdef RT_ARCH_AMD64
2051 mov rax, [uCR4]
2052 mov cr4, rax
2053# else
2054 mov eax, [uCR4]
2055 _emit 0x0F
2056 _emit 0x22
2057 _emit 0xE0 /* mov cr4, eax */
2058# endif
2059 }
2060# endif
2061}
2062#endif
2063
2064
2065/**
2066 * Get cr8.
2067 * @returns cr8.
2068 * @remark The lock prefix hack for access from non-64-bit modes is NOT used and 0 is returned.
2069 */
2070#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2071DECLASM(RTCCUINTXREG) ASMGetCR8(void);
2072#else
2073DECLINLINE(RTCCUINTXREG) ASMGetCR8(void)
2074{
2075# ifdef RT_ARCH_AMD64
2076 RTCCUINTXREG uCR8;
2077# if RT_INLINE_ASM_USES_INTRIN
2078 uCR8 = __readcr8();
2079
2080# elif RT_INLINE_ASM_GNU_STYLE
2081 __asm__ __volatile__("movq %%cr8, %0\t\n" : "=r" (uCR8));
2082# else
2083 __asm
2084 {
2085 mov rax, cr8
2086 mov [uCR8], rax
2087 }
2088# endif
2089 return uCR8;
2090# else /* !RT_ARCH_AMD64 */
2091 return 0;
2092# endif /* !RT_ARCH_AMD64 */
2093}
2094#endif
2095
2096
2097/**
2098 * Get XCR0 (eXtended feature Control Register 0).
2099 * @returns xcr0.
2100 */
2101DECLASM(uint64_t) ASMGetXcr0(void);
2102
2103/**
2104 * Sets the XCR0 register.
2105 * @param uXcr0 The new XCR0 value.
2106 */
2107DECLASM(void) ASMSetXcr0(uint64_t uXcr0);
2108
2109struct X86XSAVEAREA;
2110/**
2111 * Save extended CPU state.
2112 * @param pXStateArea Where to save the state.
2113 * @param fComponents Which state components to save.
2114 */
2115DECLASM(void) ASMXSave(struct X86XSAVEAREA RT_FAR *pXStateArea, uint64_t fComponents);
2116
2117/**
2118 * Loads extended CPU state.
2119 * @param pXStateArea Where to load the state from.
2120 * @param fComponents Which state components to load.
2121 */
2122DECLASM(void) ASMXRstor(struct X86XSAVEAREA const RT_FAR *pXStateArea, uint64_t fComponents);
2123
2124
2125struct X86FXSTATE;
2126/**
2127 * Save FPU and SSE CPU state.
2128 * @param pXStateArea Where to save the state.
2129 */
2130DECLASM(void) ASMFxSave(struct X86FXSTATE RT_FAR *pXStateArea);
2131
2132/**
2133 * Load FPU and SSE CPU state.
2134 * @param pXStateArea Where to load the state from.
2135 */
2136DECLASM(void) ASMFxRstor(struct X86FXSTATE const RT_FAR *pXStateArea);
2137
2138
2139/**
2140 * Enables interrupts (EFLAGS.IF).
2141 */
2142#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2143RT_ASM_DECL_PRAGMA_WATCOM(void) ASMIntEnable(void);
2144#else
2145DECLINLINE(void) ASMIntEnable(void)
2146{
2147# if RT_INLINE_ASM_GNU_STYLE
2148 __asm("sti\n");
2149# elif RT_INLINE_ASM_USES_INTRIN
2150 _enable();
2151# else
2152 __asm sti
2153# endif
2154}
2155#endif
2156
2157
2158/**
2159 * Disables interrupts (!EFLAGS.IF).
2160 */
2161#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2162RT_ASM_DECL_PRAGMA_WATCOM(void) ASMIntDisable(void);
2163#else
2164DECLINLINE(void) ASMIntDisable(void)
2165{
2166# if RT_INLINE_ASM_GNU_STYLE
2167 __asm("cli\n");
2168# elif RT_INLINE_ASM_USES_INTRIN
2169 _disable();
2170# else
2171 __asm cli
2172# endif
2173}
2174#endif
2175
2176
2177/**
2178 * Disables interrupts and returns previous xFLAGS.
2179 */
2180#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2181RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTREG) ASMIntDisableFlags(void);
2182#else
2183DECLINLINE(RTCCUINTREG) ASMIntDisableFlags(void)
2184{
2185 RTCCUINTREG xFlags;
2186# if RT_INLINE_ASM_GNU_STYLE
2187# ifdef RT_ARCH_AMD64
2188 __asm__ __volatile__("pushfq\n\t"
2189 "cli\n\t"
2190 "popq %0\n\t"
2191 : "=r" (xFlags));
2192# else
2193 __asm__ __volatile__("pushfl\n\t"
2194 "cli\n\t"
2195 "popl %0\n\t"
2196 : "=r" (xFlags));
2197# endif
2198# elif RT_INLINE_ASM_USES_INTRIN && !defined(RT_ARCH_X86)
2199 xFlags = ASMGetFlags();
2200 _disable();
2201# else
2202 __asm {
2203 pushfd
2204 cli
2205 pop [xFlags]
2206 }
2207# endif
2208 return xFlags;
2209}
2210#endif
2211
2212
2213/**
2214 * Are interrupts enabled?
2215 *
2216 * @returns true / false.
2217 */
2218DECLINLINE(bool) ASMIntAreEnabled(void)
2219{
2220 RTCCUINTREG uFlags = ASMGetFlags();
2221 return uFlags & 0x200 /* X86_EFL_IF */ ? true : false;
2222}
2223
2224
2225/**
2226 * Halts the CPU until interrupted.
2227 */
2228#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 14
2229RT_ASM_DECL_PRAGMA_WATCOM(void) ASMHalt(void);
2230#else
2231DECLINLINE(void) ASMHalt(void)
2232{
2233# if RT_INLINE_ASM_GNU_STYLE
2234 __asm__ __volatile__("hlt\n\t");
2235# elif RT_INLINE_ASM_USES_INTRIN
2236 __halt();
2237# else
2238 __asm {
2239 hlt
2240 }
2241# endif
2242}
2243#endif
2244
2245
2246/**
2247 * Reads a machine specific register.
2248 *
2249 * @returns Register content.
2250 * @param uRegister Register to read.
2251 */
2252#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2253RT_ASM_DECL_PRAGMA_WATCOM(uint64_t) ASMRdMsr(uint32_t uRegister);
2254#else
2255DECLINLINE(uint64_t) ASMRdMsr(uint32_t uRegister)
2256{
2257 RTUINT64U u;
2258# if RT_INLINE_ASM_GNU_STYLE
2259 __asm__ __volatile__("rdmsr\n\t"
2260 : "=a" (u.s.Lo),
2261 "=d" (u.s.Hi)
2262 : "c" (uRegister));
2263
2264# elif RT_INLINE_ASM_USES_INTRIN
2265 u.u = __readmsr(uRegister);
2266
2267# else
2268 __asm
2269 {
2270 mov ecx, [uRegister]
2271 rdmsr
2272 mov [u.s.Lo], eax
2273 mov [u.s.Hi], edx
2274 }
2275# endif
2276
2277 return u.u;
2278}
2279#endif
2280
2281
2282/**
2283 * Writes a machine specific register.
2284 *
2285 * @returns Register content.
2286 * @param uRegister Register to write to.
2287 * @param u64Val Value to write.
2288 */
2289#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2290RT_ASM_DECL_PRAGMA_WATCOM(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val);
2291#else
2292DECLINLINE(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val)
2293{
2294 RTUINT64U u;
2295
2296 u.u = u64Val;
2297# if RT_INLINE_ASM_GNU_STYLE
2298 __asm__ __volatile__("wrmsr\n\t"
2299 ::"a" (u.s.Lo),
2300 "d" (u.s.Hi),
2301 "c" (uRegister));
2302
2303# elif RT_INLINE_ASM_USES_INTRIN
2304 __writemsr(uRegister, u.u);
2305
2306# else
2307 __asm
2308 {
2309 mov ecx, [uRegister]
2310 mov edx, [u.s.Hi]
2311 mov eax, [u.s.Lo]
2312 wrmsr
2313 }
2314# endif
2315}
2316#endif
2317
2318
2319/**
2320 * Reads a machine specific register, extended version (for AMD).
2321 *
2322 * @returns Register content.
2323 * @param uRegister Register to read.
2324 * @param uXDI RDI/EDI value.
2325 */
2326#if RT_INLINE_ASM_EXTERNAL
2327RT_ASM_DECL_PRAGMA_WATCOM(uint64_t) ASMRdMsrEx(uint32_t uRegister, RTCCUINTXREG uXDI);
2328#else
2329DECLINLINE(uint64_t) ASMRdMsrEx(uint32_t uRegister, RTCCUINTXREG uXDI)
2330{
2331 RTUINT64U u;
2332# if RT_INLINE_ASM_GNU_STYLE
2333 __asm__ __volatile__("rdmsr\n\t"
2334 : "=a" (u.s.Lo),
2335 "=d" (u.s.Hi)
2336 : "c" (uRegister),
2337 "D" (uXDI));
2338
2339# else
2340 __asm
2341 {
2342 mov ecx, [uRegister]
2343 xchg edi, [uXDI]
2344 rdmsr
2345 mov [u.s.Lo], eax
2346 mov [u.s.Hi], edx
2347 xchg edi, [uXDI]
2348 }
2349# endif
2350
2351 return u.u;
2352}
2353#endif
2354
2355
2356/**
2357 * Writes a machine specific register, extended version (for AMD).
2358 *
2359 * @returns Register content.
2360 * @param uRegister Register to write to.
2361 * @param uXDI RDI/EDI value.
2362 * @param u64Val Value to write.
2363 */
2364#if RT_INLINE_ASM_EXTERNAL
2365RT_ASM_DECL_PRAGMA_WATCOM(void) ASMWrMsrEx(uint32_t uRegister, RTCCUINTXREG uXDI, uint64_t u64Val);
2366#else
2367DECLINLINE(void) ASMWrMsrEx(uint32_t uRegister, RTCCUINTXREG uXDI, uint64_t u64Val)
2368{
2369 RTUINT64U u;
2370
2371 u.u = u64Val;
2372# if RT_INLINE_ASM_GNU_STYLE
2373 __asm__ __volatile__("wrmsr\n\t"
2374 ::"a" (u.s.Lo),
2375 "d" (u.s.Hi),
2376 "c" (uRegister),
2377 "D" (uXDI));
2378
2379# else
2380 __asm
2381 {
2382 mov ecx, [uRegister]
2383 xchg edi, [uXDI]
2384 mov edx, [u.s.Hi]
2385 mov eax, [u.s.Lo]
2386 wrmsr
2387 xchg edi, [uXDI]
2388 }
2389# endif
2390}
2391#endif
2392
2393
2394
2395/**
2396 * Reads low part of a machine specific register.
2397 *
2398 * @returns Register content.
2399 * @param uRegister Register to read.
2400 */
2401#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2402RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMRdMsr_Low(uint32_t uRegister);
2403#else
2404DECLINLINE(uint32_t) ASMRdMsr_Low(uint32_t uRegister)
2405{
2406 uint32_t u32;
2407# if RT_INLINE_ASM_GNU_STYLE
2408 __asm__ __volatile__("rdmsr\n\t"
2409 : "=a" (u32)
2410 : "c" (uRegister)
2411 : "edx");
2412
2413# elif RT_INLINE_ASM_USES_INTRIN
2414 u32 = (uint32_t)__readmsr(uRegister);
2415
2416#else
2417 __asm
2418 {
2419 mov ecx, [uRegister]
2420 rdmsr
2421 mov [u32], eax
2422 }
2423# endif
2424
2425 return u32;
2426}
2427#endif
2428
2429
2430/**
2431 * Reads high part of a machine specific register.
2432 *
2433 * @returns Register content.
2434 * @param uRegister Register to read.
2435 */
2436#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2437RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMRdMsr_High(uint32_t uRegister);
2438#else
2439DECLINLINE(uint32_t) ASMRdMsr_High(uint32_t uRegister)
2440{
2441 uint32_t u32;
2442# if RT_INLINE_ASM_GNU_STYLE
2443 __asm__ __volatile__("rdmsr\n\t"
2444 : "=d" (u32)
2445 : "c" (uRegister)
2446 : "eax");
2447
2448# elif RT_INLINE_ASM_USES_INTRIN
2449 u32 = (uint32_t)(__readmsr(uRegister) >> 32);
2450
2451# else
2452 __asm
2453 {
2454 mov ecx, [uRegister]
2455 rdmsr
2456 mov [u32], edx
2457 }
2458# endif
2459
2460 return u32;
2461}
2462#endif
2463
2464
2465/**
2466 * Gets dr0.
2467 *
2468 * @returns dr0.
2469 */
2470#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2471RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetDR0(void);
2472#else
2473DECLINLINE(RTCCUINTXREG) ASMGetDR0(void)
2474{
2475 RTCCUINTXREG uDR0;
2476# if RT_INLINE_ASM_USES_INTRIN
2477 uDR0 = __readdr(0);
2478# elif RT_INLINE_ASM_GNU_STYLE
2479# ifdef RT_ARCH_AMD64
2480 __asm__ __volatile__("movq %%dr0, %0\n\t" : "=r" (uDR0));
2481# else
2482 __asm__ __volatile__("movl %%dr0, %0\n\t" : "=r" (uDR0));
2483# endif
2484# else
2485 __asm
2486 {
2487# ifdef RT_ARCH_AMD64
2488 mov rax, dr0
2489 mov [uDR0], rax
2490# else
2491 mov eax, dr0
2492 mov [uDR0], eax
2493# endif
2494 }
2495# endif
2496 return uDR0;
2497}
2498#endif
2499
2500
2501/**
2502 * Gets dr1.
2503 *
2504 * @returns dr1.
2505 */
2506#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2507RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetDR1(void);
2508#else
2509DECLINLINE(RTCCUINTXREG) ASMGetDR1(void)
2510{
2511 RTCCUINTXREG uDR1;
2512# if RT_INLINE_ASM_USES_INTRIN
2513 uDR1 = __readdr(1);
2514# elif RT_INLINE_ASM_GNU_STYLE
2515# ifdef RT_ARCH_AMD64
2516 __asm__ __volatile__("movq %%dr1, %0\n\t" : "=r" (uDR1));
2517# else
2518 __asm__ __volatile__("movl %%dr1, %0\n\t" : "=r" (uDR1));
2519# endif
2520# else
2521 __asm
2522 {
2523# ifdef RT_ARCH_AMD64
2524 mov rax, dr1
2525 mov [uDR1], rax
2526# else
2527 mov eax, dr1
2528 mov [uDR1], eax
2529# endif
2530 }
2531# endif
2532 return uDR1;
2533}
2534#endif
2535
2536
2537/**
2538 * Gets dr2.
2539 *
2540 * @returns dr2.
2541 */
2542#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2543RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetDR2(void);
2544#else
2545DECLINLINE(RTCCUINTXREG) ASMGetDR2(void)
2546{
2547 RTCCUINTXREG uDR2;
2548# if RT_INLINE_ASM_USES_INTRIN
2549 uDR2 = __readdr(2);
2550# elif RT_INLINE_ASM_GNU_STYLE
2551# ifdef RT_ARCH_AMD64
2552 __asm__ __volatile__("movq %%dr2, %0\n\t" : "=r" (uDR2));
2553# else
2554 __asm__ __volatile__("movl %%dr2, %0\n\t" : "=r" (uDR2));
2555# endif
2556# else
2557 __asm
2558 {
2559# ifdef RT_ARCH_AMD64
2560 mov rax, dr2
2561 mov [uDR2], rax
2562# else
2563 mov eax, dr2
2564 mov [uDR2], eax
2565# endif
2566 }
2567# endif
2568 return uDR2;
2569}
2570#endif
2571
2572
2573/**
2574 * Gets dr3.
2575 *
2576 * @returns dr3.
2577 */
2578#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2579RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetDR3(void);
2580#else
2581DECLINLINE(RTCCUINTXREG) ASMGetDR3(void)
2582{
2583 RTCCUINTXREG uDR3;
2584# if RT_INLINE_ASM_USES_INTRIN
2585 uDR3 = __readdr(3);
2586# elif RT_INLINE_ASM_GNU_STYLE
2587# ifdef RT_ARCH_AMD64
2588 __asm__ __volatile__("movq %%dr3, %0\n\t" : "=r" (uDR3));
2589# else
2590 __asm__ __volatile__("movl %%dr3, %0\n\t" : "=r" (uDR3));
2591# endif
2592# else
2593 __asm
2594 {
2595# ifdef RT_ARCH_AMD64
2596 mov rax, dr3
2597 mov [uDR3], rax
2598# else
2599 mov eax, dr3
2600 mov [uDR3], eax
2601# endif
2602 }
2603# endif
2604 return uDR3;
2605}
2606#endif
2607
2608
2609/**
2610 * Gets dr6.
2611 *
2612 * @returns dr6.
2613 */
2614#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2615RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetDR6(void);
2616#else
2617DECLINLINE(RTCCUINTXREG) ASMGetDR6(void)
2618{
2619 RTCCUINTXREG uDR6;
2620# if RT_INLINE_ASM_USES_INTRIN
2621 uDR6 = __readdr(6);
2622# elif RT_INLINE_ASM_GNU_STYLE
2623# ifdef RT_ARCH_AMD64
2624 __asm__ __volatile__("movq %%dr6, %0\n\t" : "=r" (uDR6));
2625# else
2626 __asm__ __volatile__("movl %%dr6, %0\n\t" : "=r" (uDR6));
2627# endif
2628# else
2629 __asm
2630 {
2631# ifdef RT_ARCH_AMD64
2632 mov rax, dr6
2633 mov [uDR6], rax
2634# else
2635 mov eax, dr6
2636 mov [uDR6], eax
2637# endif
2638 }
2639# endif
2640 return uDR6;
2641}
2642#endif
2643
2644
2645/**
2646 * Reads and clears DR6.
2647 *
2648 * @returns DR6.
2649 */
2650#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2651RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetAndClearDR6(void);
2652#else
2653DECLINLINE(RTCCUINTXREG) ASMGetAndClearDR6(void)
2654{
2655 RTCCUINTXREG uDR6;
2656# if RT_INLINE_ASM_USES_INTRIN
2657 uDR6 = __readdr(6);
2658 __writedr(6, 0xffff0ff0U); /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
2659# elif RT_INLINE_ASM_GNU_STYLE
2660 RTCCUINTXREG uNewValue = 0xffff0ff0U;/* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
2661# ifdef RT_ARCH_AMD64
2662 __asm__ __volatile__("movq %%dr6, %0\n\t"
2663 "movq %1, %%dr6\n\t"
2664 : "=r" (uDR6)
2665 : "r" (uNewValue));
2666# else
2667 __asm__ __volatile__("movl %%dr6, %0\n\t"
2668 "movl %1, %%dr6\n\t"
2669 : "=r" (uDR6)
2670 : "r" (uNewValue));
2671# endif
2672# else
2673 __asm
2674 {
2675# ifdef RT_ARCH_AMD64
2676 mov rax, dr6
2677 mov [uDR6], rax
2678 mov rcx, rax
2679 mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
2680 mov dr6, rcx
2681# else
2682 mov eax, dr6
2683 mov [uDR6], eax
2684 mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 is zero. */
2685 mov dr6, ecx
2686# endif
2687 }
2688# endif
2689 return uDR6;
2690}
2691#endif
2692
2693
2694/**
2695 * Gets dr7.
2696 *
2697 * @returns dr7.
2698 */
2699#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2700RT_ASM_DECL_PRAGMA_WATCOM(RTCCUINTXREG) ASMGetDR7(void);
2701#else
2702DECLINLINE(RTCCUINTXREG) ASMGetDR7(void)
2703{
2704 RTCCUINTXREG uDR7;
2705# if RT_INLINE_ASM_USES_INTRIN
2706 uDR7 = __readdr(7);
2707# elif RT_INLINE_ASM_GNU_STYLE
2708# ifdef RT_ARCH_AMD64
2709 __asm__ __volatile__("movq %%dr7, %0\n\t" : "=r" (uDR7));
2710# else
2711 __asm__ __volatile__("movl %%dr7, %0\n\t" : "=r" (uDR7));
2712# endif
2713# else
2714 __asm
2715 {
2716# ifdef RT_ARCH_AMD64
2717 mov rax, dr7
2718 mov [uDR7], rax
2719# else
2720 mov eax, dr7
2721 mov [uDR7], eax
2722# endif
2723 }
2724# endif
2725 return uDR7;
2726}
2727#endif
2728
2729
2730/**
2731 * Sets dr0.
2732 *
2733 * @param uDRVal Debug register value to write
2734 */
2735#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2736RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetDR0(RTCCUINTXREG uDRVal);
2737#else
2738DECLINLINE(void) ASMSetDR0(RTCCUINTXREG uDRVal)
2739{
2740# if RT_INLINE_ASM_USES_INTRIN
2741 __writedr(0, uDRVal);
2742# elif RT_INLINE_ASM_GNU_STYLE
2743# ifdef RT_ARCH_AMD64
2744 __asm__ __volatile__("movq %0, %%dr0\n\t" : : "r" (uDRVal));
2745# else
2746 __asm__ __volatile__("movl %0, %%dr0\n\t" : : "r" (uDRVal));
2747# endif
2748# else
2749 __asm
2750 {
2751# ifdef RT_ARCH_AMD64
2752 mov rax, [uDRVal]
2753 mov dr0, rax
2754# else
2755 mov eax, [uDRVal]
2756 mov dr0, eax
2757# endif
2758 }
2759# endif
2760}
2761#endif
2762
2763
2764/**
2765 * Sets dr1.
2766 *
2767 * @param uDRVal Debug register value to write
2768 */
2769#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2770RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetDR1(RTCCUINTXREG uDRVal);
2771#else
2772DECLINLINE(void) ASMSetDR1(RTCCUINTXREG uDRVal)
2773{
2774# if RT_INLINE_ASM_USES_INTRIN
2775 __writedr(1, uDRVal);
2776# elif RT_INLINE_ASM_GNU_STYLE
2777# ifdef RT_ARCH_AMD64
2778 __asm__ __volatile__("movq %0, %%dr1\n\t" : : "r" (uDRVal));
2779# else
2780 __asm__ __volatile__("movl %0, %%dr1\n\t" : : "r" (uDRVal));
2781# endif
2782# else
2783 __asm
2784 {
2785# ifdef RT_ARCH_AMD64
2786 mov rax, [uDRVal]
2787 mov dr1, rax
2788# else
2789 mov eax, [uDRVal]
2790 mov dr1, eax
2791# endif
2792 }
2793# endif
2794}
2795#endif
2796
2797
2798/**
2799 * Sets dr2.
2800 *
2801 * @param uDRVal Debug register value to write
2802 */
2803#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2804RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetDR2(RTCCUINTXREG uDRVal);
2805#else
2806DECLINLINE(void) ASMSetDR2(RTCCUINTXREG uDRVal)
2807{
2808# if RT_INLINE_ASM_USES_INTRIN
2809 __writedr(2, uDRVal);
2810# elif RT_INLINE_ASM_GNU_STYLE
2811# ifdef RT_ARCH_AMD64
2812 __asm__ __volatile__("movq %0, %%dr2\n\t" : : "r" (uDRVal));
2813# else
2814 __asm__ __volatile__("movl %0, %%dr2\n\t" : : "r" (uDRVal));
2815# endif
2816# else
2817 __asm
2818 {
2819# ifdef RT_ARCH_AMD64
2820 mov rax, [uDRVal]
2821 mov dr2, rax
2822# else
2823 mov eax, [uDRVal]
2824 mov dr2, eax
2825# endif
2826 }
2827# endif
2828}
2829#endif
2830
2831
2832/**
2833 * Sets dr3.
2834 *
2835 * @param uDRVal Debug register value to write
2836 */
2837#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2838RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetDR3(RTCCUINTXREG uDRVal);
2839#else
2840DECLINLINE(void) ASMSetDR3(RTCCUINTXREG uDRVal)
2841{
2842# if RT_INLINE_ASM_USES_INTRIN
2843 __writedr(3, uDRVal);
2844# elif RT_INLINE_ASM_GNU_STYLE
2845# ifdef RT_ARCH_AMD64
2846 __asm__ __volatile__("movq %0, %%dr3\n\t" : : "r" (uDRVal));
2847# else
2848 __asm__ __volatile__("movl %0, %%dr3\n\t" : : "r" (uDRVal));
2849# endif
2850# else
2851 __asm
2852 {
2853# ifdef RT_ARCH_AMD64
2854 mov rax, [uDRVal]
2855 mov dr3, rax
2856# else
2857 mov eax, [uDRVal]
2858 mov dr3, eax
2859# endif
2860 }
2861# endif
2862}
2863#endif
2864
2865
2866/**
2867 * Sets dr6.
2868 *
2869 * @param uDRVal Debug register value to write
2870 */
2871#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2872RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetDR6(RTCCUINTXREG uDRVal);
2873#else
2874DECLINLINE(void) ASMSetDR6(RTCCUINTXREG uDRVal)
2875{
2876# if RT_INLINE_ASM_USES_INTRIN
2877 __writedr(6, uDRVal);
2878# elif RT_INLINE_ASM_GNU_STYLE
2879# ifdef RT_ARCH_AMD64
2880 __asm__ __volatile__("movq %0, %%dr6\n\t" : : "r" (uDRVal));
2881# else
2882 __asm__ __volatile__("movl %0, %%dr6\n\t" : : "r" (uDRVal));
2883# endif
2884# else
2885 __asm
2886 {
2887# ifdef RT_ARCH_AMD64
2888 mov rax, [uDRVal]
2889 mov dr6, rax
2890# else
2891 mov eax, [uDRVal]
2892 mov dr6, eax
2893# endif
2894 }
2895# endif
2896}
2897#endif
2898
2899
2900/**
2901 * Sets dr7.
2902 *
2903 * @param uDRVal Debug register value to write
2904 */
2905#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2906RT_ASM_DECL_PRAGMA_WATCOM(void) ASMSetDR7(RTCCUINTXREG uDRVal);
2907#else
2908DECLINLINE(void) ASMSetDR7(RTCCUINTXREG uDRVal)
2909{
2910# if RT_INLINE_ASM_USES_INTRIN
2911 __writedr(7, uDRVal);
2912# elif RT_INLINE_ASM_GNU_STYLE
2913# ifdef RT_ARCH_AMD64
2914 __asm__ __volatile__("movq %0, %%dr7\n\t" : : "r" (uDRVal));
2915# else
2916 __asm__ __volatile__("movl %0, %%dr7\n\t" : : "r" (uDRVal));
2917# endif
2918# else
2919 __asm
2920 {
2921# ifdef RT_ARCH_AMD64
2922 mov rax, [uDRVal]
2923 mov dr7, rax
2924# else
2925 mov eax, [uDRVal]
2926 mov dr7, eax
2927# endif
2928 }
2929# endif
2930}
2931#endif
2932
2933
2934/**
2935 * Writes a 8-bit unsigned integer to an I/O port, ordered.
2936 *
2937 * @param Port I/O port to write to.
2938 * @param u8 8-bit integer to write.
2939 */
2940#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2941RT_ASM_DECL_PRAGMA_WATCOM(void) ASMOutU8(RTIOPORT Port, uint8_t u8);
2942#else
2943DECLINLINE(void) ASMOutU8(RTIOPORT Port, uint8_t u8)
2944{
2945# if RT_INLINE_ASM_GNU_STYLE
2946 __asm__ __volatile__("outb %b1, %w0\n\t"
2947 :: "Nd" (Port),
2948 "a" (u8));
2949
2950# elif RT_INLINE_ASM_USES_INTRIN
2951 __outbyte(Port, u8);
2952
2953# else
2954 __asm
2955 {
2956 mov dx, [Port]
2957 mov al, [u8]
2958 out dx, al
2959 }
2960# endif
2961}
2962#endif
2963
2964
2965/**
2966 * Reads a 8-bit unsigned integer from an I/O port, ordered.
2967 *
2968 * @returns 8-bit integer.
2969 * @param Port I/O port to read from.
2970 */
2971#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2972RT_ASM_DECL_PRAGMA_WATCOM(uint8_t) ASMInU8(RTIOPORT Port);
2973#else
2974DECLINLINE(uint8_t) ASMInU8(RTIOPORT Port)
2975{
2976 uint8_t u8;
2977# if RT_INLINE_ASM_GNU_STYLE
2978 __asm__ __volatile__("inb %w1, %b0\n\t"
2979 : "=a" (u8)
2980 : "Nd" (Port));
2981
2982# elif RT_INLINE_ASM_USES_INTRIN
2983 u8 = __inbyte(Port);
2984
2985# else
2986 __asm
2987 {
2988 mov dx, [Port]
2989 in al, dx
2990 mov [u8], al
2991 }
2992# endif
2993 return u8;
2994}
2995#endif
2996
2997
2998/**
2999 * Writes a 16-bit unsigned integer to an I/O port, ordered.
3000 *
3001 * @param Port I/O port to write to.
3002 * @param u16 16-bit integer to write.
3003 */
3004#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3005RT_ASM_DECL_PRAGMA_WATCOM(void) ASMOutU16(RTIOPORT Port, uint16_t u16);
3006#else
3007DECLINLINE(void) ASMOutU16(RTIOPORT Port, uint16_t u16)
3008{
3009# if RT_INLINE_ASM_GNU_STYLE
3010 __asm__ __volatile__("outw %w1, %w0\n\t"
3011 :: "Nd" (Port),
3012 "a" (u16));
3013
3014# elif RT_INLINE_ASM_USES_INTRIN
3015 __outword(Port, u16);
3016
3017# else
3018 __asm
3019 {
3020 mov dx, [Port]
3021 mov ax, [u16]
3022 out dx, ax
3023 }
3024# endif
3025}
3026#endif
3027
3028
3029/**
3030 * Reads a 16-bit unsigned integer from an I/O port, ordered.
3031 *
3032 * @returns 16-bit integer.
3033 * @param Port I/O port to read from.
3034 */
3035#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3036RT_ASM_DECL_PRAGMA_WATCOM(uint16_t) ASMInU16(RTIOPORT Port);
3037#else
3038DECLINLINE(uint16_t) ASMInU16(RTIOPORT Port)
3039{
3040 uint16_t u16;
3041# if RT_INLINE_ASM_GNU_STYLE
3042 __asm__ __volatile__("inw %w1, %w0\n\t"
3043 : "=a" (u16)
3044 : "Nd" (Port));
3045
3046# elif RT_INLINE_ASM_USES_INTRIN
3047 u16 = __inword(Port);
3048
3049# else
3050 __asm
3051 {
3052 mov dx, [Port]
3053 in ax, dx
3054 mov [u16], ax
3055 }
3056# endif
3057 return u16;
3058}
3059#endif
3060
3061
3062/**
3063 * Writes a 32-bit unsigned integer to an I/O port, ordered.
3064 *
3065 * @param Port I/O port to write to.
3066 * @param u32 32-bit integer to write.
3067 */
3068#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3069RT_ASM_DECL_PRAGMA_WATCOM(void) ASMOutU32(RTIOPORT Port, uint32_t u32);
3070#else
3071DECLINLINE(void) ASMOutU32(RTIOPORT Port, uint32_t u32)
3072{
3073# if RT_INLINE_ASM_GNU_STYLE
3074 __asm__ __volatile__("outl %1, %w0\n\t"
3075 :: "Nd" (Port),
3076 "a" (u32));
3077
3078# elif RT_INLINE_ASM_USES_INTRIN
3079 __outdword(Port, u32);
3080
3081# else
3082 __asm
3083 {
3084 mov dx, [Port]
3085 mov eax, [u32]
3086 out dx, eax
3087 }
3088# endif
3089}
3090#endif
3091
3092
3093/**
3094 * Reads a 32-bit unsigned integer from an I/O port, ordered.
3095 *
3096 * @returns 32-bit integer.
3097 * @param Port I/O port to read from.
3098 */
3099#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3100RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMInU32(RTIOPORT Port);
3101#else
3102DECLINLINE(uint32_t) ASMInU32(RTIOPORT Port)
3103{
3104 uint32_t u32;
3105# if RT_INLINE_ASM_GNU_STYLE
3106 __asm__ __volatile__("inl %w1, %0\n\t"
3107 : "=a" (u32)
3108 : "Nd" (Port));
3109
3110# elif RT_INLINE_ASM_USES_INTRIN
3111 u32 = __indword(Port);
3112
3113# else
3114 __asm
3115 {
3116 mov dx, [Port]
3117 in eax, dx
3118 mov [u32], eax
3119 }
3120# endif
3121 return u32;
3122}
3123#endif
3124
3125
3126/**
3127 * Writes a string of 8-bit unsigned integer items to an I/O port, ordered.
3128 *
3129 * @param Port I/O port to write to.
3130 * @param pau8 Pointer to the string buffer.
3131 * @param c The number of items to write.
3132 */
3133#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3134RT_ASM_DECL_PRAGMA_WATCOM(void) ASMOutStrU8(RTIOPORT Port, uint8_t const RT_FAR *pau8, size_t c);
3135#else
3136DECLINLINE(void) ASMOutStrU8(RTIOPORT Port, uint8_t const RT_FAR *pau8, size_t c)
3137{
3138# if RT_INLINE_ASM_GNU_STYLE
3139 __asm__ __volatile__("rep; outsb\n\t"
3140 : "+S" (pau8),
3141 "+c" (c)
3142 : "d" (Port));
3143
3144# elif RT_INLINE_ASM_USES_INTRIN
3145 __outbytestring(Port, (unsigned char RT_FAR *)pau8, (unsigned long)c);
3146
3147# else
3148 __asm
3149 {
3150 mov dx, [Port]
3151 mov ecx, [c]
3152 mov eax, [pau8]
3153 xchg esi, eax
3154 rep outsb
3155 xchg esi, eax
3156 }
3157# endif
3158}
3159#endif
3160
3161
3162/**
3163 * Reads a string of 8-bit unsigned integer items from an I/O port, ordered.
3164 *
3165 * @param Port I/O port to read from.
3166 * @param pau8 Pointer to the string buffer (output).
3167 * @param c The number of items to read.
3168 */
3169#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3170RT_ASM_DECL_PRAGMA_WATCOM(void) ASMInStrU8(RTIOPORT Port, uint8_t RT_FAR *pau8, size_t c);
3171#else
3172DECLINLINE(void) ASMInStrU8(RTIOPORT Port, uint8_t RT_FAR *pau8, size_t c)
3173{
3174# if RT_INLINE_ASM_GNU_STYLE
3175 __asm__ __volatile__("rep; insb\n\t"
3176 : "+D" (pau8),
3177 "+c" (c)
3178 : "d" (Port));
3179
3180# elif RT_INLINE_ASM_USES_INTRIN
3181 __inbytestring(Port, pau8, (unsigned long)c);
3182
3183# else
3184 __asm
3185 {
3186 mov dx, [Port]
3187 mov ecx, [c]
3188 mov eax, [pau8]
3189 xchg edi, eax
3190 rep insb
3191 xchg edi, eax
3192 }
3193# endif
3194}
3195#endif
3196
3197
3198/**
3199 * Writes a string of 16-bit unsigned integer items to an I/O port, ordered.
3200 *
3201 * @param Port I/O port to write to.
3202 * @param pau16 Pointer to the string buffer.
3203 * @param c The number of items to write.
3204 */
3205#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3206RT_ASM_DECL_PRAGMA_WATCOM(void) ASMOutStrU16(RTIOPORT Port, uint16_t const RT_FAR *pau16, size_t c);
3207#else
3208DECLINLINE(void) ASMOutStrU16(RTIOPORT Port, uint16_t const RT_FAR *pau16, size_t c)
3209{
3210# if RT_INLINE_ASM_GNU_STYLE
3211 __asm__ __volatile__("rep; outsw\n\t"
3212 : "+S" (pau16),
3213 "+c" (c)
3214 : "d" (Port));
3215
3216# elif RT_INLINE_ASM_USES_INTRIN
3217 __outwordstring(Port, (unsigned short RT_FAR *)pau16, (unsigned long)c);
3218
3219# else
3220 __asm
3221 {
3222 mov dx, [Port]
3223 mov ecx, [c]
3224 mov eax, [pau16]
3225 xchg esi, eax
3226 rep outsw
3227 xchg esi, eax
3228 }
3229# endif
3230}
3231#endif
3232
3233
3234/**
3235 * Reads a string of 16-bit unsigned integer items from an I/O port, ordered.
3236 *
3237 * @param Port I/O port to read from.
3238 * @param pau16 Pointer to the string buffer (output).
3239 * @param c The number of items to read.
3240 */
3241#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3242RT_ASM_DECL_PRAGMA_WATCOM(void) ASMInStrU16(RTIOPORT Port, uint16_t RT_FAR *pau16, size_t c);
3243#else
3244DECLINLINE(void) ASMInStrU16(RTIOPORT Port, uint16_t RT_FAR *pau16, size_t c)
3245{
3246# if RT_INLINE_ASM_GNU_STYLE
3247 __asm__ __volatile__("rep; insw\n\t"
3248 : "+D" (pau16),
3249 "+c" (c)
3250 : "d" (Port));
3251
3252# elif RT_INLINE_ASM_USES_INTRIN
3253 __inwordstring(Port, pau16, (unsigned long)c);
3254
3255# else
3256 __asm
3257 {
3258 mov dx, [Port]
3259 mov ecx, [c]
3260 mov eax, [pau16]
3261 xchg edi, eax
3262 rep insw
3263 xchg edi, eax
3264 }
3265# endif
3266}
3267#endif
3268
3269
3270/**
3271 * Writes a string of 32-bit unsigned integer items to an I/O port, ordered.
3272 *
3273 * @param Port I/O port to write to.
3274 * @param pau32 Pointer to the string buffer.
3275 * @param c The number of items to write.
3276 */
3277#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3278RT_ASM_DECL_PRAGMA_WATCOM(void) ASMOutStrU32(RTIOPORT Port, uint32_t const RT_FAR *pau32, size_t c);
3279#else
3280DECLINLINE(void) ASMOutStrU32(RTIOPORT Port, uint32_t const RT_FAR *pau32, size_t c)
3281{
3282# if RT_INLINE_ASM_GNU_STYLE
3283 __asm__ __volatile__("rep; outsl\n\t"
3284 : "+S" (pau32),
3285 "+c" (c)
3286 : "d" (Port));
3287
3288# elif RT_INLINE_ASM_USES_INTRIN
3289 __outdwordstring(Port, (unsigned long RT_FAR *)pau32, (unsigned long)c);
3290
3291# else
3292 __asm
3293 {
3294 mov dx, [Port]
3295 mov ecx, [c]
3296 mov eax, [pau32]
3297 xchg esi, eax
3298 rep outsd
3299 xchg esi, eax
3300 }
3301# endif
3302}
3303#endif
3304
3305
3306/**
3307 * Reads a string of 32-bit unsigned integer items from an I/O port, ordered.
3308 *
3309 * @param Port I/O port to read from.
3310 * @param pau32 Pointer to the string buffer (output).
3311 * @param c The number of items to read.
3312 */
3313#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3314RT_ASM_DECL_PRAGMA_WATCOM(void) ASMInStrU32(RTIOPORT Port, uint32_t RT_FAR *pau32, size_t c);
3315#else
3316DECLINLINE(void) ASMInStrU32(RTIOPORT Port, uint32_t RT_FAR *pau32, size_t c)
3317{
3318# if RT_INLINE_ASM_GNU_STYLE
3319 __asm__ __volatile__("rep; insl\n\t"
3320 : "+D" (pau32),
3321 "+c" (c)
3322 : "d" (Port));
3323
3324# elif RT_INLINE_ASM_USES_INTRIN
3325 __indwordstring(Port, (unsigned long RT_FAR *)pau32, (unsigned long)c);
3326
3327# else
3328 __asm
3329 {
3330 mov dx, [Port]
3331 mov ecx, [c]
3332 mov eax, [pau32]
3333 xchg edi, eax
3334 rep insd
3335 xchg edi, eax
3336 }
3337# endif
3338}
3339#endif
3340
3341
3342/**
3343 * Invalidate page.
3344 *
3345 * @param uPtr Address of the page to invalidate.
3346 */
3347#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3348RT_ASM_DECL_PRAGMA_WATCOM(void) ASMInvalidatePage(RTCCUINTXREG uPtr);
3349#else
3350DECLINLINE(void) ASMInvalidatePage(RTCCUINTXREG uPtr)
3351{
3352# if RT_INLINE_ASM_USES_INTRIN
3353 __invlpg((void RT_FAR *)uPtr);
3354
3355# elif RT_INLINE_ASM_GNU_STYLE
3356 __asm__ __volatile__("invlpg %0\n\t"
3357 : : "m" (*(uint8_t RT_FAR *)(uintptr_t)uPtr));
3358# else
3359 __asm
3360 {
3361# ifdef RT_ARCH_AMD64
3362 mov rax, [uPtr]
3363 invlpg [rax]
3364# else
3365 mov eax, [uPtr]
3366 invlpg [eax]
3367# endif
3368 }
3369# endif
3370}
3371#endif
3372
3373
3374/**
3375 * Write back the internal caches and invalidate them.
3376 */
3377#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3378RT_ASM_DECL_PRAGMA_WATCOM(void) ASMWriteBackAndInvalidateCaches(void);
3379#else
3380DECLINLINE(void) ASMWriteBackAndInvalidateCaches(void)
3381{
3382# if RT_INLINE_ASM_USES_INTRIN
3383 __wbinvd();
3384
3385# elif RT_INLINE_ASM_GNU_STYLE
3386 __asm__ __volatile__("wbinvd");
3387# else
3388 __asm
3389 {
3390 wbinvd
3391 }
3392# endif
3393}
3394#endif
3395
3396
3397/**
3398 * Invalidate internal and (perhaps) external caches without first
3399 * flushing dirty cache lines. Use with extreme care.
3400 */
3401#if RT_INLINE_ASM_EXTERNAL
3402RT_ASM_DECL_PRAGMA_WATCOM(void) ASMInvalidateInternalCaches(void);
3403#else
3404DECLINLINE(void) ASMInvalidateInternalCaches(void)
3405{
3406# if RT_INLINE_ASM_GNU_STYLE
3407 __asm__ __volatile__("invd");
3408# else
3409 __asm
3410 {
3411 invd
3412 }
3413# endif
3414}
3415#endif
3416
3417
3418/**
3419 * Memory load/store fence, waits for any pending writes and reads to complete.
3420 * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.
3421 */
3422DECLINLINE(void) ASMMemoryFenceSSE2(void)
3423{
3424#if RT_INLINE_ASM_GNU_STYLE
3425 __asm__ __volatile__ (".byte 0x0f,0xae,0xf0\n\t");
3426#elif RT_INLINE_ASM_USES_INTRIN
3427 _mm_mfence();
3428#else
3429 __asm
3430 {
3431 _emit 0x0f
3432 _emit 0xae
3433 _emit 0xf0
3434 }
3435#endif
3436}
3437
3438
3439/**
3440 * Memory store fence, waits for any writes to complete.
3441 * Requires the X86_CPUID_FEATURE_EDX_SSE CPUID bit set.
3442 */
3443DECLINLINE(void) ASMWriteFenceSSE(void)
3444{
3445#if RT_INLINE_ASM_GNU_STYLE
3446 __asm__ __volatile__ (".byte 0x0f,0xae,0xf8\n\t");
3447#elif RT_INLINE_ASM_USES_INTRIN
3448 _mm_sfence();
3449#else
3450 __asm
3451 {
3452 _emit 0x0f
3453 _emit 0xae
3454 _emit 0xf8
3455 }
3456#endif
3457}
3458
3459
3460/**
3461 * Memory load fence, waits for any pending reads to complete.
3462 * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.
3463 */
3464DECLINLINE(void) ASMReadFenceSSE2(void)
3465{
3466#if RT_INLINE_ASM_GNU_STYLE
3467 __asm__ __volatile__ (".byte 0x0f,0xae,0xe8\n\t");
3468#elif RT_INLINE_ASM_USES_INTRIN
3469 _mm_lfence();
3470#else
3471 __asm
3472 {
3473 _emit 0x0f
3474 _emit 0xae
3475 _emit 0xe8
3476 }
3477#endif
3478}
3479
3480#if !defined(_MSC_VER) || !defined(RT_ARCH_AMD64)
3481
3482/*
3483 * Clear the AC bit in the EFLAGS register.
3484 * Requires the X86_CPUID_STEXT_FEATURE_EBX_SMAP CPUID bit set.
3485 * Requires to be executed in R0.
3486 */
3487DECLINLINE(void) ASMClearAC(void)
3488{
3489#if RT_INLINE_ASM_GNU_STYLE
3490 __asm__ __volatile__ (".byte 0x0f,0x01,0xca\n\t");
3491#else
3492 __asm
3493 {
3494 _emit 0x0f
3495 _emit 0x01
3496 _emit 0xca
3497 }
3498#endif
3499}
3500
3501
3502/*
3503 * Set the AC bit in the EFLAGS register.
3504 * Requires the X86_CPUID_STEXT_FEATURE_EBX_SMAP CPUID bit set.
3505 * Requires to be executed in R0.
3506 */
3507DECLINLINE(void) ASMSetAC(void)
3508{
3509#if RT_INLINE_ASM_GNU_STYLE
3510 __asm__ __volatile__ (".byte 0x0f,0x01,0xcb\n\t");
3511#else
3512 __asm
3513 {
3514 _emit 0x0f
3515 _emit 0x01
3516 _emit 0xcb
3517 }
3518#endif
3519}
3520
3521#endif /* !_MSC_VER || !RT_ARCH_AMD64 */
3522
3523
3524/*
3525 * Include #pragma aux definitions for Watcom C/C++.
3526 */
3527#if defined(__WATCOMC__) && ARCH_BITS == 16
3528# define IPRT_ASM_AMD64_X86_WATCOM_16_INSTANTIATE
3529# undef IPRT_INCLUDED_asm_amd64_x86_watcom_16_h
3530# include "asm-amd64-x86-watcom-16.h"
3531#elif defined(__WATCOMC__) && ARCH_BITS == 32
3532# define IPRT_ASM_AMD64_X86_WATCOM_32_INSTANTIATE
3533# undef IPRT_INCLUDED_asm_amd64_x86_watcom_32_h
3534# include "asm-amd64-x86-watcom-32.h"
3535#endif
3536
3537
3538/** @} */
3539#endif /* !IPRT_INCLUDED_asm_amd64_x86_h */
3540
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