| 1 | /** @file
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| 2 | * IPRT - ARM Specific Assembly Functions.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2015-2024 Oracle and/or its affiliates.
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| 7 | *
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| 8 | * This file is part of VirtualBox base platform packages, as
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| 9 | * available from https://www.virtualbox.org.
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| 10 | *
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| 11 | * This program is free software; you can redistribute it and/or
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| 12 | * modify it under the terms of the GNU General Public License
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| 13 | * as published by the Free Software Foundation, in version 3 of the
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| 14 | * License.
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| 15 | *
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| 16 | * This program is distributed in the hope that it will be useful, but
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| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 19 | * General Public License for more details.
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| 20 | *
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| 21 | * You should have received a copy of the GNU General Public License
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| 22 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 23 | *
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| 24 | * The contents of this file may alternatively be used under the terms
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| 25 | * of the Common Development and Distribution License Version 1.0
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| 26 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 27 | * in the VirtualBox distribution, in which case the provisions of the
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| 28 | * CDDL are applicable instead of those of the GPL.
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| 29 | *
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| 30 | * You may elect to license modified versions of this file under the
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| 31 | * terms and conditions of either the GPL or the CDDL or both.
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| 32 | *
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| 33 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 34 | */
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| 35 |
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| 36 | #ifndef IPRT_INCLUDED_asm_arm_h
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| 37 | #define IPRT_INCLUDED_asm_arm_h
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| 38 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 39 | # pragma once
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| 40 | #endif
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| 41 |
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| 42 | #include <iprt/types.h>
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| 43 | #if !defined(RT_ARCH_ARM64) && !defined(RT_ARCH_ARM32)
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| 44 | # error "Not on ARM64 or ARM32"
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| 45 | #endif
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| 46 |
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| 47 | #if defined(_MSC_VER) && RT_INLINE_ASM_USES_INTRIN
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| 48 | /* Emit the intrinsics at all optimization levels. */
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| 49 | # include <iprt/sanitized/intrin.h>
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| 50 | # pragma intrinsic(_ReadStatusReg)
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| 51 | # pragma intrinsic(_WriteStatusReg)
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| 52 | # pragma intrinsic(_disable)
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| 53 | # pragma intrinsic(_enable)
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| 54 | # pragma intrinsic(__hvc)
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| 55 |
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| 56 | /*
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| 57 | * MSVC insists on having these defined using ARM64_SYSREG or it will
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| 58 | * fail to compile with "error C2284: "_ReadStatusReg": invalid argument for internal function, parameter 1"
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| 59 | * if we use our own definitions from iprt/armv8.h
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| 60 | *
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| 61 | * The reason for this, is that ARM64_SYSREG masks off the top bit (bit 15)
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| 62 | * whereas our macro doesn't. So the reason is probably the implicitness
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| 63 | * of the top bit in the MRS/MSR encoding.
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| 64 | */
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| 65 | # define ARM64_SYSREG_DAIF ARM64_SYSREG(3, 3, 4, 2, 1)
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| 66 | # define ARM64_SYSREG_CNTFRQ_EL0 ARM64_SYSREG(3, 3, 14, 0, 0)
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| 67 | # define ARM64_SYSREG_CNTCVT_EL0 ARM64_SYSREG(3, 3, 14, 0, 2)
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| 68 | # define ARM64_SYSREG_TPIDRRO_EL0 ARM64_SYSREG(3, 3, 13, 0, 3)
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| 69 | #endif
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| 70 |
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| 71 | /** @defgroup grp_rt_asm_arm ARM Specific ASM Routines
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| 72 | * @ingroup grp_rt_asm
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| 73 | * @{
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| 74 | */
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| 75 |
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| 76 | /**
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| 77 | * Gets the content of the CNTVCT_EL0 (or CNTPCT) register.
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| 78 | *
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| 79 | * @returns CNTVCT_EL0 value.
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| 80 | * @note We call this TSC to better fit in with existing x86/amd64 based code.
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| 81 | */
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| 82 | #if RT_INLINE_ASM_EXTERNAL
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| 83 | DECLASM(uint64_t) ASMReadTSC(void);
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| 84 | #else
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| 85 | DECLINLINE(uint64_t) ASMReadTSC(void)
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| 86 | {
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| 87 | # if RT_INLINE_ASM_GNU_STYLE
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| 88 | uint64_t u64;
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| 89 | # ifdef RT_ARCH_ARM64
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| 90 | __asm__ __volatile__("Lstart_ASMReadTSC_%=:\n\t"
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| 91 | "isb\n\t"
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| 92 | "mrs %0, CNTVCT_EL0\n\t"
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| 93 | : "=r" (u64));
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| 94 | # else
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| 95 | uint32_t u32Spill;
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| 96 | uint32_t u32Comp;
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| 97 | __asm__ __volatile__("Lstart_ASMReadTSC_%=:\n\t"
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| 98 | "isb\n"
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| 99 | "Ltry_again_ASMReadTSC_%=:\n\t"
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| 100 | "mrrc p15, 0, %[uSpill], %H[uRet], c14\n\t" /* CNTPCT high into uRet.hi */
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| 101 | "mrrc p15, 0, %[uRet], %[uSpill], c14\n\t" /* CNTPCT low into uRet.lo */
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| 102 | "mrrc p15, 0, %[uSpill], %[uHiComp], c14\n\t" /* CNTPCT high into uHiComp */
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| 103 | "cmp %H[uRet], %[uHiComp]\n\t"
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| 104 | "b.eq Ltry_again_ASMReadTSC_%=\n\t" /* Redo if high value changed. */
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| 105 | : [uRet] "=r" (u64)
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| 106 | , "=r" (uHiComp)
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| 107 | , "=r" (uSpill));
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| 108 | # endif
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| 109 | return u64;
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| 110 |
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| 111 | #elif RT_INLINE_ASM_USES_INTRIN
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| 112 | return (uint64_t)_ReadStatusReg(ARM64_SYSREG_CNTCVT_EL0);
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| 113 | # else
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| 114 | # error "Unsupported compiler"
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| 115 | # endif
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| 116 | }
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| 117 | #endif
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| 118 |
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| 119 |
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| 120 | /**
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| 121 | * Gets the content of the CNTFRQ_EL0 register.
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| 122 | *
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| 123 | * @returns CNTFRQ_EL0 value.
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| 124 | */
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| 125 | #if RT_INLINE_ASM_EXTERNAL
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| 126 | DECLASM(uint64_t) ASMReadCntFrqEl0(void);
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| 127 | #else
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| 128 | DECLINLINE(uint64_t) ASMReadCntFrqEl0(void)
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| 129 | {
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| 130 | # if RT_INLINE_ASM_GNU_STYLE
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| 131 | uint64_t u64;
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| 132 | # ifdef RT_ARCH_ARM64
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| 133 | __asm__ __volatile__("Lstart_ASMReadCntFrqEl0_%=:\n\t"
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| 134 | "isb\n\t"
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| 135 | "mrs %0, CNTFRQ_EL0\n\t"
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| 136 | : "=r" (u64));
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| 137 | # else
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| 138 | u64 = 0;
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| 139 | __asm__ __volatile__("Lstart_ASMReadCntFrqEl0_%=:\n\t"
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| 140 | "isb\n\t"
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| 141 | "mrc p15, 0, %[uRet], c14, 0, 0\n\t" /* CNTFRQ */
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| 142 | : [uRet] "=r" (u64));
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| 143 | # endif
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| 144 | return u64;
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| 145 |
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| 146 | #elif RT_INLINE_ASM_USES_INTRIN
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| 147 | return (uint64_t)_ReadStatusReg(ARM64_SYSREG_CNTFRQ_EL0);
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| 148 | # else
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| 149 | # error "Unsupported compiler"
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| 150 | # endif
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| 151 | }
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| 152 | #endif
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| 153 |
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| 154 |
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| 155 | /**
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| 156 | * Enables interrupts (IRQ and FIQ).
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| 157 | */
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| 158 | #if RT_INLINE_ASM_EXTERNAL
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| 159 | DECLASM(void) ASMIntEnable(void);
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| 160 | #else
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| 161 | DECLINLINE(void) ASMIntEnable(void)
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| 162 | {
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| 163 | # if RT_INLINE_ASM_GNU_STYLE
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| 164 | # ifdef RT_ARCH_ARM64
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| 165 | __asm__ __volatile__("Lstart_ASMIntEnable_%=:\n\t"
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| 166 | "msr daifclr, #0xf\n\t");
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| 167 | # else
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| 168 | RTCCUINTREG uFlags;
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| 169 | __asm__ __volatile__("Lstart_ASMIntEnable_%=:\n\t"
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| 170 | "mrs %0, cpsr\n\t"
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| 171 | "bic %0, %0, #0xc0\n\t"
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| 172 | "msr cpsr_c, %0\n\t"
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| 173 | : "=r" (uFlags));
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| 174 | # endif
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| 175 | # elif RT_INLINE_ASM_USES_INTRIN
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| 176 | _enable();
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| 177 | # else
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| 178 | # error "Unsupported compiler"
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| 179 | # endif
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| 180 | }
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| 181 | #endif
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| 182 |
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| 183 |
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| 184 | /**
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| 185 | * Disables interrupts (IRQ and FIQ).
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| 186 | */
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| 187 | #if RT_INLINE_ASM_EXTERNAL
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| 188 | DECLASM(void) ASMIntDisable(void);
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| 189 | #else
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| 190 | DECLINLINE(void) ASMIntDisable(void)
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| 191 | {
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| 192 | # if RT_INLINE_ASM_GNU_STYLE
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| 193 | # ifdef RT_ARCH_ARM64
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| 194 | __asm__ __volatile__("Lstart_ASMIntDisable_%=:\n\t"
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| 195 | "msr daifset, #0xf\n\t");
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| 196 | # else
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| 197 | RTCCUINTREG uFlags;
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| 198 | __asm__ __volatile__("Lstart_ASMIntDisable_%=:\n\t"
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| 199 | "mrs %0, cpsr\n\t"
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| 200 | "orr %0, %0, #0xc0\n\t"
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| 201 | "msr cpsr_c, %0\n\t"
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| 202 | : "=r" (uFlags));
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| 203 | # endif
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| 204 | # elif RT_INLINE_ASM_USES_INTRIN
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| 205 | _disable();
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| 206 | # else
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| 207 | # error "Unsupported compiler"
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| 208 | # endif
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| 209 | }
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| 210 | #endif
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| 211 |
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| 212 |
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| 213 | /**
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| 214 | * Disables interrupts and returns previous uFLAGS.
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| 215 | */
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| 216 | #if RT_INLINE_ASM_EXTERNAL
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| 217 | DECLASM(RTCCUINTREG) ASMIntDisableFlags(void);
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| 218 | #else
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| 219 | DECLINLINE(RTCCUINTREG) ASMIntDisableFlags(void)
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| 220 | {
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| 221 | RTCCUINTREG uFlags;
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| 222 | # if RT_INLINE_ASM_GNU_STYLE
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| 223 | # ifdef RT_ARCH_ARM64
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| 224 | __asm__ __volatile__("Lstart_ASMIntDisableFlags_%=:\n\t"
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| 225 | "mrs %[uRet], daif\n\t"
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| 226 | "msr daifset, #0xf\n\t"
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| 227 | : [uRet] "=r" (uFlags));
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| 228 | # else
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| 229 | RTCCUINTREG uNewFlags;
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| 230 | __asm__ __volatile__("Lstart_ASMIntDisableFlags_%=:\n\t"
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| 231 | "mrs %0, cpsr\n\t"
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| 232 | "orr %1, %0, #0xc0\n\t"
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| 233 | "msr cpsr_c, %1\n\t"
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| 234 | : "=r" (uFlags)
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| 235 | , "=r" (uNewFlags));
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| 236 | # endif
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| 237 | # elif RT_INLINE_ASM_USES_INTRIN
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| 238 | uFlags = _ReadStatusReg(ARM64_SYSREG_DAIF);
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| 239 | _disable();
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| 240 | # else
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| 241 | # error "Unsupported compiler"
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| 242 | # endif
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| 243 | return uFlags;
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| 244 | }
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| 245 | #endif
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| 246 |
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| 247 |
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| 248 | /**
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| 249 | * Get the CPSR/PSTATE register.
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| 250 | * @returns CPSR/PSTATE.
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| 251 | */
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| 252 | #if RT_INLINE_ASM_EXTERNAL
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| 253 | DECLASM(RTCCUINTREG) ASMGetFlags(void);
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| 254 | #else
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| 255 | DECLINLINE(RTCCUINTREG) ASMGetFlags(void)
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| 256 | {
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| 257 | RTCCUINTREG uFlags;
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| 258 | # if RT_INLINE_ASM_GNU_STYLE
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| 259 | # ifdef RT_ARCH_ARM64
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| 260 | __asm__ __volatile__("Lstart_ASMGetFlags_%=:\n\t"
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| 261 | "isb\n\t"
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| 262 | "mrs %0, daif\n\t"
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| 263 | : "=r" (uFlags));
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| 264 | # else
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| 265 | # error "Implementation required for arm32"
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| 266 | # endif
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| 267 | # elif RT_INLINE_ASM_USES_INTRIN
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| 268 | uFlags = _ReadStatusReg(ARM64_SYSREG_DAIF);
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| 269 | # else
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| 270 | # error "Unsupported compiler"
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| 271 | # endif
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| 272 | return uFlags;
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| 273 | }
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| 274 | #endif
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| 275 |
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| 276 |
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| 277 | /**
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| 278 | * Get the CPSR/PSTATE register.
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| 279 | */
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| 280 | #if RT_INLINE_ASM_EXTERNAL
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| 281 | DECLASM(void) ASMSetFlags(RTCCUINTREG uFlags);
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| 282 | #else
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| 283 | DECLINLINE(void) ASMSetFlags(RTCCUINTREG uFlags)
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| 284 | {
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| 285 | # if RT_INLINE_ASM_GNU_STYLE
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| 286 | # ifdef RT_ARCH_ARM64
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| 287 | __asm__ __volatile__("Lstart_ASMSetFlags_%=:\n\t"
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| 288 | "isb\n\t"
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| 289 | "msr daif, %[uFlags]\n\t"
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| 290 | : : [uFlags] "r" (uFlags));
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| 291 | # else
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| 292 | # error "Implementation required for arm32"
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| 293 | # endif
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| 294 | # elif RT_INLINE_ASM_USES_INTRIN
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| 295 | _WriteStatusReg(ARM64_SYSREG_DAIF, uFlags);
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| 296 | # else
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| 297 | # error "Unsupported compiler"
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| 298 | # endif
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| 299 | }
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| 300 | #endif
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| 301 |
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| 302 |
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| 303 | /**
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| 304 | * Are interrupts enabled?
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| 305 | *
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| 306 | * @returns true / false.
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| 307 | */
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| 308 | DECLINLINE(bool) ASMIntAreEnabled(void)
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| 309 | {
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| 310 | return ASMGetFlags() & 0xc0 /* IRQ and FIQ bits */ ? true : false;
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| 311 | }
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| 312 |
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| 313 |
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| 314 | #if 0 /* Later */
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| 315 | /**
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| 316 | * Issue HVC call with a single argument.
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| 317 | */
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| 318 | #if RT_INLINE_ASM_EXTERNAL
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| 319 | DECLASM(void) ASMHvc(uint16_t u16Imm, uint32_t u32Arg0);
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| 320 | #else
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| 321 | DECLINLINE(void) ASMHvc(uint16_t u16Imm, uint32_t u32Arg0)
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| 322 | {
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| 323 | # if RT_INLINE_ASM_GNU_STYLE
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| 324 | # error "Later"
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| 325 | # elif RT_INLINE_ASM_USES_INTRIN
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| 326 | __hvc(u16Imm, u32Val);
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| 327 | # else
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| 328 | # error "Unsupported compiler"
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| 329 | # endif
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| 330 | }
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| 331 | #endif
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| 332 | #endif
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| 333 |
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| 334 |
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| 335 | /**
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| 336 | * Halts the CPU until interrupted.
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| 337 | */
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| 338 | #if RT_INLINE_ASM_EXTERNAL || defined(_MSC_VER)
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| 339 | DECLASM(void) ASMHalt(void);
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| 340 | #else
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| 341 | DECLINLINE(void) ASMHalt(void)
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| 342 | {
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| 343 | # if RT_INLINE_ASM_GNU_STYLE
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| 344 | __asm__ __volatile__ ("Lstart_ASMHalt_%=:\n\t"
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| 345 | "wfi\n\t"); /* wait for interrupt */
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| 346 | # else
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| 347 | # error "Unsupported compiler"
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| 348 | # endif
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| 349 | }
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| 350 | #endif
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| 351 |
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| 352 | #if 0
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| 353 | /**
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| 354 | * Gets the CPU ID of the current CPU.
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| 355 | *
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| 356 | * @returns the CPU ID.
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| 357 | * @note the name of this method is a bit misleading but serves the purpose
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| 358 | * and prevents #ifdef orgies in other places.
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| 359 | */
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| 360 | #if RT_INLINE_ASM_EXTERNAL
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| 361 | DECLASM(uint8_t) ASMGetApicId(void);
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| 362 | #else
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| 363 | DECLINLINE(uint8_t) ASMGetApicId(void)
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| 364 | {
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| 365 | # if RT_INLINE_ASM_GNU_STYLE
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| 366 | RTCCUINTREG uCpuId;
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| 367 | __asm__ ("Lstart_ASMGetApicId_%=:\n\t"
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| 368 | "mrc p15, 0, %0, c0, c0, 5\n\t" /* CPU ID Register, privileged */
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| 369 | : "=r" (uCpuId));
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| 370 | return uCpuId;
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| 371 | # else
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| 372 | # error "Unsupported compiler"
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| 373 | # endif
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| 374 | }
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| 375 | #endif
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| 376 | #endif
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| 377 |
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| 378 | #if 0
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| 379 |
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| 380 | /**
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| 381 | * Invalidate page.
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| 382 | *
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| 383 | * @param pv Address of the page to invalidate.
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| 384 | */
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| 385 | #if RT_INLINE_ASM_EXTERNAL
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| 386 | DECLASM(void) ASMInvalidatePage(void *pv);
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| 387 | #else
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| 388 | DECLINLINE(void) ASMInvalidatePage(void *pv)
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| 389 | {
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| 390 | # if RT_INLINE_ASM_GNU_STYLE
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| 391 |
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| 392 | # else
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| 393 | # error "Unsupported compiler"
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| 394 | # endif
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| 395 | }
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| 396 | #endif
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| 397 |
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| 398 |
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| 399 | /**
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| 400 | * Write back the internal caches and invalidate them.
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| 401 | */
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| 402 | #if RT_INLINE_ASM_EXTERNAL
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| 403 | DECLASM(void) ASMWriteBackAndInvalidateCaches(void);
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| 404 | #else
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| 405 | DECLINLINE(void) ASMWriteBackAndInvalidateCaches(void)
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| 406 | {
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| 407 | # if RT_INLINE_ASM_GNU_STYLE
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| 408 |
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| 409 | # else
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| 410 | # error "Unsupported compiler"
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| 411 | # endif
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| 412 | }
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| 413 | #endif
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| 414 |
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| 415 |
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| 416 | /**
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| 417 | * Invalidate internal and (perhaps) external caches without first
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| 418 | * flushing dirty cache lines. Use with extreme care.
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| 419 | */
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| 420 | #if RT_INLINE_ASM_EXTERNAL
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| 421 | DECLASM(void) ASMInvalidateInternalCaches(void);
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| 422 | #else
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| 423 | DECLINLINE(void) ASMInvalidateInternalCaches(void)
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| 424 | {
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| 425 | # if RT_INLINE_ASM_GNU_STYLE
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| 426 |
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| 427 | # else
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| 428 | # error "Unsupported compiler"
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| 429 | # endif
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| 430 | }
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| 431 | #endif
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| 432 |
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| 433 | #endif
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| 434 |
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| 435 |
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| 436 | /**
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| 437 | * Get the TPIDRRO_EL0 register.
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| 438 | */
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| 439 | #if RT_INLINE_ASM_EXTERNAL
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| 440 | DECLASM(RTCCUINTREG) ASMGetThreadIdRoEL0(void);
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| 441 | #else
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| 442 | DECLINLINE(RTCCUINTREG) ASMGetThreadIdRoEL0(void)
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| 443 | {
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| 444 | # if RT_INLINE_ASM_GNU_STYLE
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| 445 | RTCCUINTREG uRet;
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| 446 | # ifdef RT_ARCH_ARM64
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| 447 | __asm__ __volatile__("Lstart_ASMGetThreadIdEl0_%=:\n\t"
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| 448 | "mrs %[uRet], TPIDRRO_EL0\n\t"
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| 449 | : [uRet] "=r" (uRet));
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| 450 | # else
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| 451 | __asm__ __volatile__("Lstart_ASMGetThreadIdEl0_%=:\n\t"
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| 452 | "mrc p15, 0, %[uRet], c13, c0, 3\n\t" /* TPIDRURO */
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| 453 | : [uRet] "=r" (uRet));
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| 454 | # endif
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| 455 | return uRet;
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| 456 | # elif RT_INLINE_ASM_USES_INTRIN
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| 457 | return _ReadStatusReg(ARM64_SYSREG_TPIDRRO_EL0);
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| 458 | # else
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| 459 | # error "Unsupported compiler"
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| 460 | # endif
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| 461 | }
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| 462 | #endif
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| 463 |
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| 464 |
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| 465 | /** @} */
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| 466 | #endif /* !IPRT_INCLUDED_asm_arm_h */
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| 467 |
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