x86.h@ 102829

Last change on this file since 102829 was 102717, checked in by vboxsync, 13 months ago
VBox/VMM: Outlined native TLB lookup code for IEM_MC_MEM_MAP_XXXX on x86 hosts. Untested+disabled. bugref:10371
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 193.5 KB

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# include <iprt/types.h>
46	# include <iprt/assert.h>
47	#else
48	# pragma D depends_on library vbox-types.d
49	#endif
50
51	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
52	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
53	#ifdef RT_OS_SOLARIS
54	# undef CS
55	# undef DS
56	# undef MSR_IA32_FLUSH_CMD
57	# undef MSR_AMD_VIRT_SPEC_CTL
58	#endif
59
60	/** @defgroup grp_rt_x86 x86 Types and Definitions
61	* @ingroup grp_rt
62	* @{
63	*/
64
65	#ifndef VBOX_FOR_DTRACE_LIB
66	/**
67	* EFLAGS Bits.
68	*/
69	typedef struct X86EFLAGSBITS
70	{
71	/** Bit 0 - CF - Carry flag - Status flag. */
72	unsigned u1CF : 1;
73	/** Bit 1 - 1 - Reserved flag. */
74	unsigned u1Reserved0 : 1;
75	/** Bit 2 - PF - Parity flag - Status flag. */
76	unsigned u1PF : 1;
77	/** Bit 3 - 0 - Reserved flag. */
78	unsigned u1Reserved1 : 1;
79	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
80	unsigned u1AF : 1;
81	/** Bit 5 - 0 - Reserved flag. */
82	unsigned u1Reserved2 : 1;
83	/** Bit 6 - ZF - Zero flag - Status flag. */
84	unsigned u1ZF : 1;
85	/** Bit 7 - SF - Signed flag - Status flag. */
86	unsigned u1SF : 1;
87	/** Bit 8 - TF - Trap flag - System flag. */
88	unsigned u1TF : 1;
89	/** Bit 9 - IF - Interrupt flag - System flag. */
90	unsigned u1IF : 1;
91	/** Bit 10 - DF - Direction flag - Control flag. */
92	unsigned u1DF : 1;
93	/** Bit 11 - OF - Overflow flag - Status flag. */
94	unsigned u1OF : 1;
95	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
96	unsigned u2IOPL : 2;
97	/** Bit 14 - NT - Nested task flag - System flag. */
98	unsigned u1NT : 1;
99	/** Bit 15 - 0 - Reserved flag. */
100	unsigned u1Reserved3 : 1;
101	/** Bit 16 - RF - Resume flag - System flag. */
102	unsigned u1RF : 1;
103	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
104	unsigned u1VM : 1;
105	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
106	unsigned u1AC : 1;
107	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
108	unsigned u1VIF : 1;
109	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
110	unsigned u1VIP : 1;
111	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
112	unsigned u1ID : 1;
113	/** Bit 22-31 - 0 - Reserved flag. */
114	unsigned u10Reserved4 : 10;
115	} X86EFLAGSBITS;
116	/** Pointer to EFLAGS bits. */
117	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
118	/** Pointer to const EFLAGS bits. */
119	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
120	#endif /* !VBOX_FOR_DTRACE_LIB */
121
122	/**
123	* EFLAGS.
124	*/
125	typedef union X86EFLAGS
126	{
127	/** The plain unsigned view. */
128	uint32_t u;
129	#ifndef VBOX_FOR_DTRACE_LIB
130	/** The bitfield view. */
131	X86EFLAGSBITS Bits;
132	#endif
133	/** The 8-bit view. */
134	uint8_t au8[4];
135	/** The 16-bit view. */
136	uint16_t au16[2];
137	/** The 32-bit view. */
138	uint32_t au32[1];
139	/** The 32-bit view. */
140	uint32_t u32;
141	} X86EFLAGS;
142	/** Pointer to EFLAGS. */
143	typedef X86EFLAGS *PX86EFLAGS;
144	/** Pointer to const EFLAGS. */
145	typedef const X86EFLAGS *PCX86EFLAGS;
146
147	/**
148	* RFLAGS (32 upper bits are reserved).
149	*/
150	typedef union X86RFLAGS
151	{
152	/** The plain unsigned view. */
153	uint64_t u;
154	#ifndef VBOX_FOR_DTRACE_LIB
155	/** The bitfield view. */
156	X86EFLAGSBITS Bits;
157	#endif
158	/** The 8-bit view. */
159	uint8_t au8[8];
160	/** The 16-bit view. */
161	uint16_t au16[4];
162	/** The 32-bit view. */
163	uint32_t au32[2];
164	/** The 64-bit view. */
165	uint64_t au64[1];
166	/** The 64-bit view. */
167	uint64_t u64;
168	} X86RFLAGS;
169	/** Pointer to RFLAGS. */
170	typedef X86RFLAGS *PX86RFLAGS;
171	/** Pointer to const RFLAGS. */
172	typedef const X86RFLAGS *PCX86RFLAGS;
173
174
175	/** @name EFLAGS
176	* @{
177	*/
178	/** Bit 0 - CF - Carry flag - Status flag. */
179	#define X86_EFL_CF RT_BIT_32(0)
180	#define X86_EFL_CF_BIT 0
181	/** Bit 1 - Reserved, reads as 1. */
182	#define X86_EFL_1 RT_BIT_32(1)
183	/** Bit 2 - PF - Parity flag - Status flag. */
184	#define X86_EFL_PF RT_BIT_32(2)
185	#define X86_EFL_PF_BIT 2
186	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
187	#define X86_EFL_AF RT_BIT_32(4)
188	#define X86_EFL_AF_BIT 4
189	/** Bit 6 - ZF - Zero flag - Status flag. */
190	#define X86_EFL_ZF RT_BIT_32(6)
191	#define X86_EFL_ZF_BIT 6
192	/** Bit 7 - SF - Signed flag - Status flag. */
193	#define X86_EFL_SF RT_BIT_32(7)
194	#define X86_EFL_SF_BIT 7
195	/** Bit 8 - TF - Trap flag - System flag. */
196	#define X86_EFL_TF RT_BIT_32(8)
197	#define X86_EFL_TF_BIT 8
198	/** Bit 9 - IF - Interrupt flag - System flag. */
199	#define X86_EFL_IF RT_BIT_32(9)
200	#define X86_EFL_IF_BIT 9
201	/** Bit 10 - DF - Direction flag - Control flag. */
202	#define X86_EFL_DF RT_BIT_32(10)
203	#define X86_EFL_DF_BIT 10
204	/** Bit 11 - OF - Overflow flag - Status flag. */
205	#define X86_EFL_OF RT_BIT_32(11)
206	#define X86_EFL_OF_BIT 11
207	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
208	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
209	/** Bit 14 - NT - Nested task flag - System flag. */
210	#define X86_EFL_NT RT_BIT_32(14)
211	#define X86_EFL_NT_BIT 14
212	/** Bit 16 - RF - Resume flag - System flag. */
213	#define X86_EFL_RF RT_BIT_32(16)
214	#define X86_EFL_RF_BIT 16
215	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
216	#define X86_EFL_VM RT_BIT_32(17)
217	#define X86_EFL_VM_BIT 17
218	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
219	#define X86_EFL_AC RT_BIT_32(18)
220	#define X86_EFL_AC_BIT 18
221	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
222	#define X86_EFL_VIF RT_BIT_32(19)
223	#define X86_EFL_VIF_BIT 19
224	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
225	#define X86_EFL_VIP RT_BIT_32(20)
226	#define X86_EFL_VIP_BIT 20
227	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
228	#define X86_EFL_ID RT_BIT_32(21)
229	#define X86_EFL_ID_BIT 21
230	/** All live bits. */
231	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
232	/** Read as 1 bits. */
233	#define X86_EFL_RA1_MASK RT_BIT_32(1)
234	/** Read as 0 bits, excluding bits 31:22.
235	* Bits 3, 5, 15, and 22 thru 31. */
236	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
237	/** Read as 0 bits, excluding bits 31:22.
238	* Bits 3, 5 and 15. */
239	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
240	/** IOPL shift. */
241	#define X86_EFL_IOPL_SHIFT 12
242	/** The IOPL level from the flags. */
243	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
244	/** Bits restored by popf */
245	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
246	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
247	/** Bits restored by popf */
248	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
249	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
250	/** The status bits commonly updated by arithmetic instructions. */
251	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
252	/** @} */
253
254
255	/** CPUID Feature information - ECX.
256	* CPUID query with EAX=1.
257	*/
258	#ifndef VBOX_FOR_DTRACE_LIB
259	typedef struct X86CPUIDFEATECX
260	{
261	/** Bit 0 - SSE3 - Supports SSE3 or not. */
262	unsigned u1SSE3 : 1;
263	/** Bit 1 - PCLMULQDQ. */
264	unsigned u1PCLMULQDQ : 1;
265	/** Bit 2 - DS Area 64-bit layout. */
266	unsigned u1DTE64 : 1;
267	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
268	unsigned u1Monitor : 1;
269	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
270	unsigned u1CPLDS : 1;
271	/** Bit 5 - VMX - Virtual Machine Technology. */
272	unsigned u1VMX : 1;
273	/** Bit 6 - SMX: Safer Mode Extensions. */
274	unsigned u1SMX : 1;
275	/** Bit 7 - EST - Enh. SpeedStep Tech. */
276	unsigned u1EST : 1;
277	/** Bit 8 - TM2 - Terminal Monitor 2. */
278	unsigned u1TM2 : 1;
279	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
280	unsigned u1SSSE3 : 1;
281	/** Bit 10 - CNTX-ID - L1 Context ID. */
282	unsigned u1CNTXID : 1;
283	/** Bit 11 - Reserved. */
284	unsigned u1Reserved1 : 1;
285	/** Bit 12 - FMA. */
286	unsigned u1FMA : 1;
287	/** Bit 13 - CX16 - CMPXCHG16B. */
288	unsigned u1CX16 : 1;
289	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
290	unsigned u1TPRUpdate : 1;
291	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
292	unsigned u1PDCM : 1;
293	/** Bit 16 - Reserved. */
294	unsigned u1Reserved2 : 1;
295	/** Bit 17 - PCID - Process-context identifiers. */
296	unsigned u1PCID : 1;
297	/** Bit 18 - Direct Cache Access. */
298	unsigned u1DCA : 1;
299	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
300	unsigned u1SSE4_1 : 1;
301	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
302	unsigned u1SSE4_2 : 1;
303	/** Bit 21 - x2APIC. */
304	unsigned u1x2APIC : 1;
305	/** Bit 22 - MOVBE - Supports MOVBE. */
306	unsigned u1MOVBE : 1;
307	/** Bit 23 - POPCNT - Supports POPCNT. */
308	unsigned u1POPCNT : 1;
309	/** Bit 24 - TSC-Deadline. */
310	unsigned u1TSCDEADLINE : 1;
311	/** Bit 25 - AES. */
312	unsigned u1AES : 1;
313	/** Bit 26 - XSAVE - Supports XSAVE. */
314	unsigned u1XSAVE : 1;
315	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
316	unsigned u1OSXSAVE : 1;
317	/** Bit 28 - AVX - Supports AVX instruction extensions. */
318	unsigned u1AVX : 1;
319	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
320	unsigned u1F16C : 1;
321	/** Bit 30 - RDRAND - Supports RDRAND. */
322	unsigned u1RDRAND : 1;
323	/** Bit 31 - Hypervisor present (we're a guest). */
324	unsigned u1HVP : 1;
325	} X86CPUIDFEATECX;
326	#else /* VBOX_FOR_DTRACE_LIB */
327	typedef uint32_t X86CPUIDFEATECX;
328	#endif /* VBOX_FOR_DTRACE_LIB */
329	/** Pointer to CPUID Feature Information - ECX. */
330	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
331	/** Pointer to const CPUID Feature Information - ECX. */
332	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
333
334
335	/** CPUID Feature Information - EDX.
336	* CPUID query with EAX=1.
337	*/
338	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
339	typedef struct X86CPUIDFEATEDX
340	{
341	/** Bit 0 - FPU - x87 FPU on Chip. */
342	unsigned u1FPU : 1;
343	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
344	unsigned u1VME : 1;
345	/** Bit 2 - DE - Debugging extensions. */
346	unsigned u1DE : 1;
347	/** Bit 3 - PSE - Page Size Extension. */
348	unsigned u1PSE : 1;
349	/** Bit 4 - TSC - Time Stamp Counter. */
350	unsigned u1TSC : 1;
351	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
352	unsigned u1MSR : 1;
353	/** Bit 6 - PAE - Physical Address Extension. */
354	unsigned u1PAE : 1;
355	/** Bit 7 - MCE - Machine Check Exception. */
356	unsigned u1MCE : 1;
357	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
358	unsigned u1CX8 : 1;
359	/** Bit 9 - APIC - APIC On-Chip. */
360	unsigned u1APIC : 1;
361	/** Bit 10 - Reserved. */
362	unsigned u1Reserved1 : 1;
363	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
364	unsigned u1SEP : 1;
365	/** Bit 12 - MTRR - Memory Type Range Registers. */
366	unsigned u1MTRR : 1;
367	/** Bit 13 - PGE - PTE Global Bit. */
368	unsigned u1PGE : 1;
369	/** Bit 14 - MCA - Machine Check Architecture. */
370	unsigned u1MCA : 1;
371	/** Bit 15 - CMOV - Conditional Move Instructions. */
372	unsigned u1CMOV : 1;
373	/** Bit 16 - PAT - Page Attribute Table. */
374	unsigned u1PAT : 1;
375	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
376	unsigned u1PSE36 : 1;
377	/** Bit 18 - PSN - Processor Serial Number. */
378	unsigned u1PSN : 1;
379	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
380	unsigned u1CLFSH : 1;
381	/** Bit 20 - Reserved. */
382	unsigned u1Reserved2 : 1;
383	/** Bit 21 - DS - Debug Store. */
384	unsigned u1DS : 1;
385	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
386	unsigned u1ACPI : 1;
387	/** Bit 23 - MMX - Intel MMX 'Technology'. */
388	unsigned u1MMX : 1;
389	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
390	unsigned u1FXSR : 1;
391	/** Bit 25 - SSE - SSE Support. */
392	unsigned u1SSE : 1;
393	/** Bit 26 - SSE2 - SSE2 Support. */
394	unsigned u1SSE2 : 1;
395	/** Bit 27 - SS - Self Snoop. */
396	unsigned u1SS : 1;
397	/** Bit 28 - HTT - Hyper-Threading Technology. */
398	unsigned u1HTT : 1;
399	/** Bit 29 - TM - Thermal Monitor. */
400	unsigned u1TM : 1;
401	/** Bit 30 - Reserved - . */
402	unsigned u1Reserved3 : 1;
403	/** Bit 31 - PBE - Pending Break Enabled. */
404	unsigned u1PBE : 1;
405	} X86CPUIDFEATEDX;
406	#else /* VBOX_FOR_DTRACE_LIB */
407	typedef uint32_t X86CPUIDFEATEDX;
408	#endif /* VBOX_FOR_DTRACE_LIB */
409	/** Pointer to CPUID Feature Information - EDX. */
410	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
411	/** Pointer to const CPUID Feature Information - EDX. */
412	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
413
414	/** @name CPUID Vendor information.
415	* CPUID query with EAX=0.
416	* @{
417	*/
418	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
419	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
420	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
421
422	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
423	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
424	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
425
426	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
427	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
428	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
429
430	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
431	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
432	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
433
434	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
435	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
436	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
437	/** @} */
438
439
440	/** @name CPUID Feature information.
441	* CPUID query with EAX=1.
442	* @{
443	*/
444	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
445	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
446	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
447	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
448	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
449	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
450	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
451	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
452	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
453	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
454	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
455	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
456	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
457	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
458	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
459	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
460	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
461	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
462	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
463	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
464	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
465	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
466	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
467	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
468	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
469	/** ECX Bit 12 - FMA. */
470	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
471	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
472	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
473	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
474	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
475	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
476	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
477	/** ECX Bit 17 - PCID - Process-context identifiers. */
478	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
479	/** ECX Bit 18 - DCA - Direct Cache Access. */
480	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
481	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
482	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
483	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
484	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
485	/** ECX Bit 21 - x2APIC support. */
486	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
487	/** ECX Bit 22 - MOVBE instruction. */
488	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
489	/** ECX Bit 23 - POPCNT instruction. */
490	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
491	/** ECX Bir 24 - TSC-Deadline. */
492	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
493	/** ECX Bit 25 - AES instructions. */
494	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
495	/** ECX Bit 26 - XSAVE instruction. */
496	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
497	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
498	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
499	/** ECX Bit 28 - AVX. */
500	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
501	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
502	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
503	/** ECX Bit 30 - RDRAND instruction. */
504	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
505	/** ECX Bit 31 - Hypervisor Present (software only). */
506	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
507
508
509	/** Bit 0 - FPU - x87 FPU on Chip. */
510	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
511	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
512	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
513	/** Bit 2 - DE - Debugging extensions. */
514	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
515	/** Bit 3 - PSE - Page Size Extension. */
516	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
517	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
518	/** Bit 4 - TSC - Time Stamp Counter. */
519	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
520	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
521	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
522	/** Bit 6 - PAE - Physical Address Extension. */
523	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
524	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
525	/** Bit 7 - MCE - Machine Check Exception. */
526	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
527	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
528	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
529	/** Bit 9 - APIC - APIC On-Chip. */
530	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
531	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
532	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
533	/** Bit 12 - MTRR - Memory Type Range Registers. */
534	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
535	/** Bit 13 - PGE - PTE Global Bit. */
536	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
537	/** Bit 14 - MCA - Machine Check Architecture. */
538	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
539	/** Bit 15 - CMOV - Conditional Move Instructions. */
540	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
541	/** Bit 16 - PAT - Page Attribute Table. */
542	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
543	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
544	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
545	/** Bit 18 - PSN - Processor Serial Number. */
546	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
547	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
548	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
549	/** Bit 21 - DS - Debug Store. */
550	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
551	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
552	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
553	/** Bit 23 - MMX - Intel MMX Technology. */
554	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
555	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
556	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
557	/** Bit 25 - SSE - SSE Support. */
558	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
559	/** Bit 26 - SSE2 - SSE2 Support. */
560	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
561	/** Bit 27 - SS - Self Snoop. */
562	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
563	/** Bit 28 - HTT - Hyper-Threading Technology. */
564	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
565	/** Bit 29 - TM - Therm. Monitor. */
566	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
567	/** Bit 31 - PBE - Pending Break Enabled. */
568	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
569	/** @} */
570
571	/** @name CPUID mwait/monitor information.
572	* CPUID query with EAX=5.
573	* @{
574	*/
575	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
576	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
577	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
578	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
579	/** @} */
580
581
582	/** @name CPUID Thermal and Power Management information.
583	* Generally Intel only unless noted otherwise.
584	* CPUID query with EAX=5. @{
585	*/
586	/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
587	#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
588	/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
589	#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
590	/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
591	#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
592	/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
593	#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
594	/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
595	#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
596	/** EAX Bit 6 - PTM - Package Thermal Management supported. */
597	#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
598	/** EAX Bit 7 - HWP - HWP base MSRs supported. */
599	#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
600	/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
601	#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
602	/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
603	#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
604	/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
605	#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
606	/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
607	#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
608	/** EAX Bit 13 - HDC - HDC base MSRs supported. */
609	#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
610	/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
611	#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
612	/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
613	#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
614	/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
615	#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
616	/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
617	#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
618
619	/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
620	#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
621	/** @} */
622
623
624	/** @name CPUID Structured Extended Feature information.
625	* CPUID query with EAX=7.
626	* @{
627	*/
628	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
629	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
630	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
631	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
632	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
633	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
634	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
635	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
636	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
637	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
638	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
639	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
640	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
641	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
642	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
643	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
644	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
645	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
646	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
647	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
648	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
649	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
650	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
651	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
652	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
653	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
654	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
655	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
656	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
657	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
658	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
659	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
660	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
661	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
662	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
663	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
664	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
665	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
666	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
667	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
668	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
669	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
670	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
671	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
672	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
673	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
674	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
675	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
676	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
677	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
678	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
679	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
680
681	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
682	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
683	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
684	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
685	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
686	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
687	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
688	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
689	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
690	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
691	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
692	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
693	/** ECX Bit 22 - RDPID - Support pread process ID. */
694	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
695	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
696	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
697
698	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
699	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
700	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
701	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
702	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
703	* IBPB command in IA32_PRED_CMD. */
704	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
705	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
706	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
707	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
708	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
709	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
710	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
711	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
712	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
713
714	/** @} */
715
716
717	/** @name CPUID Extended Feature information.
718	* CPUID query with EAX=0x80000001.
719	* @{
720	*/
721	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
722	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
723
724	/** EDX Bit 11 - SYSCALL/SYSRET. */
725	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
726	/** EDX Bit 20 - No-Execute/Execute-Disable. */
727	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
728	/** EDX Bit 26 - 1 GB large page. */
729	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
730	/** EDX Bit 27 - RDTSCP. */
731	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
732	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
733	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
734	/** @}*/
735
736	/** @name CPUID AMD Feature information.
737	* CPUID query with EAX=0x80000001.
738	* @{
739	*/
740	/** Bit 0 - FPU - x87 FPU on Chip. */
741	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
742	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
743	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
744	/** Bit 2 - DE - Debugging extensions. */
745	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
746	/** Bit 3 - PSE - Page Size Extension. */
747	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
748	/** Bit 4 - TSC - Time Stamp Counter. */
749	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
750	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
751	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
752	/** Bit 6 - PAE - Physical Address Extension. */
753	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
754	/** Bit 7 - MCE - Machine Check Exception. */
755	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
756	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
757	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
758	/** Bit 9 - APIC - APIC On-Chip. */
759	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
760	/** Bit 12 - MTRR - Memory Type Range Registers. */
761	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
762	/** Bit 13 - PGE - PTE Global Bit. */
763	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
764	/** Bit 14 - MCA - Machine Check Architecture. */
765	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
766	/** Bit 15 - CMOV - Conditional Move Instructions. */
767	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
768	/** Bit 16 - PAT - Page Attribute Table. */
769	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
770	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
771	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
772	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
773	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
774	/** Bit 23 - MMX - Intel MMX Technology. */
775	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
776	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
777	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
778	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
779	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
780	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
781	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
782	/** Bit 31 - 3DNOW - AMD 3DNow. */
783	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
784
785	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
786	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
787	/** Bit 2 - SVM - AMD VM extensions. */
788	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
789	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
790	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
791	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
792	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
793	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
794	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
795	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
796	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
797	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
798	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
799	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
800	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
801	/** Bit 9 - OSVW - AMD OS visible workaround. */
802	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
803	/** Bit 10 - IBS - Instruct based sampling. */
804	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
805	/** Bit 11 - XOP - Extended operation support (see APM6). */
806	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
807	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
808	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
809	/** Bit 13 - WDT - AMD Watchdog timer support. */
810	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
811	/** Bit 15 - LWP - Lightweight profiling support. */
812	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
813	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
814	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
815	/** Bit 19 - NodeId - Indicates support for
816	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
817	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
818	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
819	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
820	/** Bit 22 - TopologyExtensions - . */
821	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
822	/** @} */
823
824
825	/** @name CPUID AMD Feature information.
826	* CPUID query with EAX=0x80000007.
827	* @{
828	*/
829	/** Bit 0 - TS - Temperature Sensor. */
830	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
831	/** Bit 1 - FID - Frequency ID Control. */
832	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
833	/** Bit 2 - VID - Voltage ID Control. */
834	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
835	/** Bit 3 - TTP - THERMTRIP. */
836	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
837	/** Bit 4 - TM - Hardware Thermal Control. */
838	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
839	/** Bit 5 - STC - Software Thermal Control. */
840	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
841	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
842	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
843	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
844	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
845	/** Bit 8 - TSCINVAR - TSC Invariant. */
846	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
847	/** Bit 9 - CPB - TSC Invariant. */
848	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
849	/** Bit 10 - EffFreqRO - MPERF/APERF. */
850	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
851	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
852	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
853	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
854	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
855	/** @} */
856
857
858	/** @name CPUID AMD extended feature extensions ID (EBX).
859	* CPUID query with EAX=0x80000008.
860	* @{
861	*/
862	/** Bit 0 - CLZERO - Clear zero instruction. */
863	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
864	/** Bit 1 - IRPerf - Instructions retired count support. */
865	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
866	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
867	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
868	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
869	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
870	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
871	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
872	/* AMD pipeline length: 9 feature bits ;-) */
873	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
874	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
875	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
876	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
877	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
878	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
879	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
880	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
881	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
882	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
883	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
884	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
885	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
886	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
887	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
888	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
889	/** Bit 26 - Speculative Store Bypass Disable not required. */
890	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
891	/** @} */
892
893
894	/** @name CPUID AMD SVM Feature information.
895	* CPUID query with EAX=0x8000000a.
896	* @{
897	*/
898	/** Bit 0 - NP - Nested Paging supported. */
899	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
900	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
901	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
902	/** Bit 2 - SVML - SVM locking bit supported. */
903	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
904	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
905	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
906	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
907	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
908	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
909	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
910	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
911	* VMCB.TLB_Control is supported. */
912	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
913	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
914	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
915	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
916	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
917	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
918	* intercept filter cycle count threshold. */
919	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
920	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
921	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
922	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
923	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
924	/** Bit 16 - VGIF - Supports virtualized GIF. */
925	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
926	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
927	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
928	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
929	* mode. */
930	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
931	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
932	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
933	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
934	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
935	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
936	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
937	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
938	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
939	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
940	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
941	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
942	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
943	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
944	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
945	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
946	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
947	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
948	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
949	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
950	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
951
952	/** @} */
953
954
955	/** @name CR0
956	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
957	* reserved flags.
958	* @{ */
959	/** Bit 0 - PE - Protection Enabled */
960	#define X86_CR0_PE RT_BIT_32(0)
961	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
962	/** Bit 1 - MP - Monitor Coprocessor */
963	#define X86_CR0_MP RT_BIT_32(1)
964	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
965	/** Bit 2 - EM - Emulation. */
966	#define X86_CR0_EM RT_BIT_32(2)
967	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
968	/** Bit 3 - TS - Task Switch. */
969	#define X86_CR0_TS RT_BIT_32(3)
970	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
971	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
972	#define X86_CR0_ET RT_BIT_32(4)
973	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
974	/** Bit 5 - NE - Numeric error (486+). */
975	#define X86_CR0_NE RT_BIT_32(5)
976	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
977	/** Bit 16 - WP - Write Protect (486+). */
978	#define X86_CR0_WP RT_BIT_32(16)
979	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
980	/** Bit 18 - AM - Alignment Mask (486+). */
981	#define X86_CR0_AM RT_BIT_32(18)
982	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
983	/** Bit 29 - NW - Not Write-though (486+). */
984	#define X86_CR0_NW RT_BIT_32(29)
985	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
986	/** Bit 30 - WP - Cache Disable (486+). */
987	#define X86_CR0_CD RT_BIT_32(30)
988	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
989	/** Bit 31 - PG - Paging. */
990	#define X86_CR0_PG RT_BIT_32(31)
991	#define X86_CR0_PAGING RT_BIT_32(31)
992	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
993	/** @} */
994
995
996	/** @name CR3
997	* @{ */
998	/** Bit 3 - PWT - Page-level Writes Transparent. */
999	#define X86_CR3_PWT RT_BIT_32(3)
1000	/** Bit 4 - PCD - Page-level Cache Disable. */
1001	#define X86_CR3_PCD RT_BIT_32(4)
1002	/** Bits 12-31 - - Page directory page number. */
1003	#define X86_CR3_PAGE_MASK (0xfffff000)
1004	/** Bits 5-31 - - PAE Page directory page number. */
1005	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1006	/** Bits 12-51 - - AMD64 PML4 page number.
1007	* @note This is a maxed out mask, the actual acceptable CR3 value can
1008	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1009	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1010	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1011	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1012	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1013	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1014	/** @} */
1015
1016
1017	/** @name CR4
1018	* @{ */
1019	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1020	#define X86_CR4_VME RT_BIT_32(0)
1021	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1022	#define X86_CR4_PVI RT_BIT_32(1)
1023	/** Bit 2 - TSD - Time Stamp Disable. */
1024	#define X86_CR4_TSD RT_BIT_32(2)
1025	/** Bit 3 - DE - Debugging Extensions. */
1026	#define X86_CR4_DE RT_BIT_32(3)
1027	/** Bit 4 - PSE - Page Size Extension. */
1028	#define X86_CR4_PSE RT_BIT_32(4)
1029	/** Bit 5 - PAE - Physical Address Extension. */
1030	#define X86_CR4_PAE RT_BIT_32(5)
1031	/** Bit 6 - MCE - Machine-Check Enable. */
1032	#define X86_CR4_MCE RT_BIT_32(6)
1033	/** Bit 7 - PGE - Page Global Enable. */
1034	#define X86_CR4_PGE RT_BIT_32(7)
1035	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1036	#define X86_CR4_PCE RT_BIT_32(8)
1037	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1038	#define X86_CR4_OSFXSR RT_BIT_32(9)
1039	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1040	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1041	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1042	#define X86_CR4_UMIP RT_BIT_32(11)
1043	/** Bit 13 - VMXE - VMX mode is enabled. */
1044	#define X86_CR4_VMXE RT_BIT_32(13)
1045	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1046	#define X86_CR4_SMXE RT_BIT_32(14)
1047	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1048	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1049	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1050	#define X86_CR4_PCIDE RT_BIT_32(17)
1051	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1052	* extended states. */
1053	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1054	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1055	#define X86_CR4_SMEP RT_BIT_32(20)
1056	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1057	#define X86_CR4_SMAP RT_BIT_32(21)
1058	/** Bit 22 - PKE - Protection Key Enable. */
1059	#define X86_CR4_PKE RT_BIT_32(22)
1060	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1061	#define X86_CR4_CET RT_BIT_32(23)
1062	/** @} */
1063
1064
1065	/** @name DR6
1066	* @{ */
1067	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1068	#define X86_DR6_B0 RT_BIT_32(0)
1069	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1070	#define X86_DR6_B1 RT_BIT_32(1)
1071	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1072	#define X86_DR6_B2 RT_BIT_32(2)
1073	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1074	#define X86_DR6_B3 RT_BIT_32(3)
1075	/** Mask of all the Bx bits. */
1076	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1077	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1078	#define X86_DR6_BD RT_BIT_32(13)
1079	/** Bit 14 - BS - Single step */
1080	#define X86_DR6_BS RT_BIT_32(14)
1081	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1082	#define X86_DR6_BT RT_BIT_32(15)
1083	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1084	#define X86_DR6_RTM RT_BIT_32(16)
1085	/** Value of DR6 after powerup/reset. */
1086	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1087	/** Bits which must be 1s in DR6. */
1088	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1089	/** Bits which must be 1s in DR6, when RTM is supported. */
1090	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1091	/** Bits which must be 0s in DR6. */
1092	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1093	/** Bits which must be 0s on writes to DR6. */
1094	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1095	/** @} */
1096
1097	/** Get the DR6.Bx bit for a the given breakpoint. */
1098	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1099
1100
1101	/** @name DR7
1102	* @{ */
1103	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1104	#define X86_DR7_L0 RT_BIT_32(0)
1105	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1106	#define X86_DR7_G0 RT_BIT_32(1)
1107	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1108	#define X86_DR7_L1 RT_BIT_32(2)
1109	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1110	#define X86_DR7_G1 RT_BIT_32(3)
1111	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1112	#define X86_DR7_L2 RT_BIT_32(4)
1113	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1114	#define X86_DR7_G2 RT_BIT_32(5)
1115	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1116	#define X86_DR7_L3 RT_BIT_32(6)
1117	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1118	#define X86_DR7_G3 RT_BIT_32(7)
1119	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1120	#define X86_DR7_LE RT_BIT_32(8)
1121	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1122	#define X86_DR7_GE RT_BIT_32(9)
1123
1124	/** L0, L1, L2, and L3. */
1125	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1126	/** L0, L1, L2, and L3. */
1127	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1128
1129	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1130	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1131	#define X86_DR7_RTM RT_BIT_32(11)
1132	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1133	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1134	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1135	* instruction is executed.
1136	* @see http://www.rcollins.org/secrets/DR7.html */
1137	#define X86_DR7_ICE_IR RT_BIT_32(12)
1138	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1139	* any DR register is accessed. */
1140	#define X86_DR7_GD RT_BIT_32(13)
1141	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1142	* Pentium. */
1143	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1144	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1145	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1146	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1147	#define X86_DR7_RW0_MASK (3 << 16)
1148	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1149	#define X86_DR7_LEN0_MASK (3 << 18)
1150	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1151	#define X86_DR7_RW1_MASK (3 << 20)
1152	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1153	#define X86_DR7_LEN1_MASK (3 << 22)
1154	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1155	#define X86_DR7_RW2_MASK (3 << 24)
1156	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1157	#define X86_DR7_LEN2_MASK (3 << 26)
1158	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1159	#define X86_DR7_RW3_MASK (3 << 28)
1160	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1161	#define X86_DR7_LEN3_MASK (3 << 30)
1162
1163	/** Bits which reads as 1s. */
1164	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1165	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1166	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1167	/** Bits which must be 0s when writing to DR7. */
1168	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1169
1170	/** Calcs the L bit of Nth breakpoint.
1171	* @param iBp The breakpoint number [0..3].
1172	*/
1173	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1174
1175	/** Calcs the G bit of Nth breakpoint.
1176	* @param iBp The breakpoint number [0..3].
1177	*/
1178	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1179
1180	/** Calcs the L and G bits of Nth breakpoint.
1181	* @param iBp The breakpoint number [0..3].
1182	*/
1183	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1184
1185	/** @name Read/Write values.
1186	* @{ */
1187	/** Break on instruction fetch only. */
1188	#define X86_DR7_RW_EO UINT32_C(0)
1189	/** Break on write only. */
1190	#define X86_DR7_RW_WO UINT32_C(1)
1191	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1192	#define X86_DR7_RW_IO UINT32_C(2)
1193	/** Break on read or write (but not instruction fetches). */
1194	#define X86_DR7_RW_RW UINT32_C(3)
1195	/** @} */
1196
1197	/** Shifts a X86_DR7_RW_* value to its right place.
1198	* @param iBp The breakpoint number [0..3].
1199	* @param fRw One of the X86_DR7_RW_* value.
1200	*/
1201	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1202
1203	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1204	* one of the X86_DR7_RW_XXX constants).
1205	*
1206	* @returns X86_DR7_RW_XXX
1207	* @param uDR7 DR7 value
1208	* @param iBp The breakpoint number [0..3].
1209	*/
1210	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1211
1212	/** R/W0, R/W1, R/W2, and R/W3. */
1213	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1214
1215	#ifndef VBOX_FOR_DTRACE_LIB
1216	/** Checks the RW and LEN fields are set up for an instruction breakpoint.
1217	* @note This does not check if it's enabled. */
1218	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1219	/** Checks if an instruction breakpoint is enabled and configured correctly.
1220	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1221	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1222	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1223	/** Checks if there are any instruction fetch breakpoint types configured in the
1224	* RW and LEN registers.
1225	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1226	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1227	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1228	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1229	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1230	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1231
1232	/** Checks if there are any I/O breakpoint types configured in the RW
1233	* registers. Does NOT check if these are enabled, sorry. */
1234	# define X86_DR7_ANY_RW_IO(uDR7) \
1235	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1236	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1237	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1238	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1239	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1240	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1241	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1242	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1243	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1244	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1245	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1246
1247	#endif /* !VBOX_FOR_DTRACE_LIB */
1248
1249	/** @name Length values.
1250	* @{ */
1251	#define X86_DR7_LEN_BYTE UINT32_C(0)
1252	#define X86_DR7_LEN_WORD UINT32_C(1)
1253	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1254	#define X86_DR7_LEN_DWORD UINT32_C(3)
1255	/** @} */
1256
1257	/** Shifts a X86_DR7_LEN_* value to its right place.
1258	* @param iBp The breakpoint number [0..3].
1259	* @param cb One of the X86_DR7_LEN_* values.
1260	*/
1261	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1262
1263	/** Fetch the breakpoint length bits from the DR7 value.
1264	* @param uDR7 DR7 value
1265	* @param iBp The breakpoint number [0..3].
1266	*/
1267	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1268
1269	/** Mask used to check if any breakpoints are enabled. */
1270	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1271
1272	/** LEN0, LEN1, LEN2, and LEN3. */
1273	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1274	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1275	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1276
1277	/** Value of DR7 after powerup/reset. */
1278	#define X86_DR7_INIT_VAL 0x400
1279	/** @} */
1280
1281
1282	/** @name Machine Specific Registers
1283	* @{
1284	*/
1285	/** Machine check address register (P5). */
1286	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1287	/** Machine check type register (P5). */
1288	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1289	/** Time Stamp Counter. */
1290	#define MSR_IA32_TSC 0x10
1291	#define MSR_IA32_CESR UINT32_C(0x00000011)
1292	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1293	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1294
1295	#define MSR_IA32_PLATFORM_ID 0x17
1296
1297	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1298	# define MSR_IA32_APICBASE 0x1b
1299	/** Local APIC enabled. */
1300	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1301	/** X2APIC enabled (requires the EN bit to be set). */
1302	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1303	/** The processor is the boot strap processor (BSP). */
1304	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1305	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1306	* width. */
1307	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1308	/** The default physical base address of the APIC. */
1309	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1310	/** Gets the physical base address from the MSR. */
1311	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1312	#endif
1313
1314	/** Undocumented intel MSR for reporting thread and core counts.
1315	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1316	* first 16 bits is the thread count. The next 16 bits the core count, except
1317	* on Westmere where it seems it's only the next 4 bits for some reason. */
1318	#define MSR_CORE_THREAD_COUNT 0x35
1319
1320	/** CPU Feature control. */
1321	#define MSR_IA32_FEATURE_CONTROL 0x3A
1322	/** Feature control - Lock MSR from writes (R/W0). */
1323	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1324	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1325	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1326	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1327	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1328	/** Feature control - SENTER local functions enable (R/WL). */
1329	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1330	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1331	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1332	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1333	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1334	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1335	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1336	/** Feature control - SENTER global enable (R/WL). */
1337	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1338	/** Feature control - SGX launch control enable (R/WL). */
1339	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1340	/** Feature control - SGX global enable (R/WL). */
1341	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1342	/** Feature control - LMCE on (R/WL). */
1343	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1344
1345	/** Per-processor TSC adjust MSR. */
1346	#define MSR_IA32_TSC_ADJUST 0x3B
1347
1348	/** Spectre control register.
1349	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1350	#define MSR_IA32_SPEC_CTRL 0x48
1351	/** IBRS - Indirect branch restricted speculation. */
1352	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1353	/** STIBP - Single thread indirect branch predictors. */
1354	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1355	/** SSBD - Speculative Store Bypass Disable. */
1356	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1357
1358	/** Prediction command register.
1359	* Write only, logical processor scope, no state since write only. */
1360	#define MSR_IA32_PRED_CMD 0x49
1361	/** IBPB - Indirect branch prediction barrie when written as 1. */
1362	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1363
1364	/** BIOS update trigger (microcode update). */
1365	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1366
1367	/** BIOS update signature (microcode). */
1368	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1369
1370	/** SMM monitor control. */
1371	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1372	/** SMM control - Valid. */
1373	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1374	/** SMM control - VMXOFF unblocks SMI. */
1375	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1376	/** SMM control - MSEG base physical address. */
1377	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1378
1379	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1380	#define MSR_IA32_SMBASE 0x9E
1381
1382	/** General performance counter no. 0. */
1383	#define MSR_IA32_PMC0 0xC1
1384	/** General performance counter no. 1. */
1385	#define MSR_IA32_PMC1 0xC2
1386	/** General performance counter no. 2. */
1387	#define MSR_IA32_PMC2 0xC3
1388	/** General performance counter no. 3. */
1389	#define MSR_IA32_PMC3 0xC4
1390	/** General performance counter no. 4. */
1391	#define MSR_IA32_PMC4 0xC5
1392	/** General performance counter no. 5. */
1393	#define MSR_IA32_PMC5 0xC6
1394	/** General performance counter no. 6. */
1395	#define MSR_IA32_PMC6 0xC7
1396	/** General performance counter no. 7. */
1397	#define MSR_IA32_PMC7 0xC8
1398
1399	/** Nehalem power control. */
1400	#define MSR_IA32_PLATFORM_INFO 0xCE
1401
1402	/** Get FSB clock status (Intel-specific). */
1403	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1404
1405	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1406	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1407
1408	/** C0 Maximum Frequency Clock Count */
1409	#define MSR_IA32_MPERF 0xE7
1410	/** C0 Actual Frequency Clock Count */
1411	#define MSR_IA32_APERF 0xE8
1412
1413	/** MTRR Capabilities. */
1414	#define MSR_IA32_MTRR_CAP 0xFE
1415	/** Bits 0-7 - VCNT - Variable range registers count. */
1416	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1417	/** Bit 8 - FIX - Fixed range registers supported. */
1418	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1419	/** Bit 10 - WC - Write-Combining memory type supported. */
1420	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1421	/** Bit 11 - SMRR - System Management Range Register supported. */
1422	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1423	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1424	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1425
1426	/**
1427	* Variable-range MTRR MSR pair.
1428	*/
1429	typedef struct X86MTRRVAR
1430	{
1431	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1432	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1433	} X86MTRRVAR;
1434	#ifndef VBOX_FOR_DTRACE_LIB
1435	AssertCompileSize(X86MTRRVAR, 16);
1436	#endif
1437	/** Pointer to a variable-range MTRR MSR pair. */
1438	typedef X86MTRRVAR *PX86MTRRVAR;
1439	/** Pointer to a const variable-range MTRR MSR pair. */
1440	typedef const X86MTRRVAR *PCX86MTRRVAR;
1441
1442	/** Memory types that can be encoded in MTRRs.
1443	* @{ */
1444	/** Uncacheable. */
1445	#define X86_MTRR_MT_UC 0
1446	/** Write Combining. */
1447	#define X86_MTRR_MT_WC 1
1448	/** Write-through. */
1449	#define X86_MTRR_MT_WT 4
1450	/** Write-protected. */
1451	#define X86_MTRR_MT_WP 5
1452	/** Writeback. */
1453	#define X86_MTRR_MT_WB 6
1454	/** @}*/
1455
1456	/** Architecture capabilities (bugfixes). */
1457	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1458	/** CPU is no subject to meltdown problems. */
1459	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1460	/** CPU has better IBRS and you can leave it on all the time. */
1461	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1462	/** CPU has return stack buffer (RSB) override. */
1463	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1464	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1465	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1466	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1467	/** CPU does not suffer from MDS issues. */
1468	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1469
1470	/** Flush command register. */
1471	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1472	/** Flush the level 1 data cache when this bit is written. */
1473	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1474
1475	/** Cache control/info. */
1476	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1477
1478	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1479	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1480	* R0 SS == CS + 8
1481	* R3 CS == CS + 16
1482	* R3 SS == CS + 24
1483	*/
1484	#define MSR_IA32_SYSENTER_CS 0x174
1485	/** SYSENTER_ESP - the R0 ESP. */
1486	#define MSR_IA32_SYSENTER_ESP 0x175
1487	/** SYSENTER_EIP - the R0 EIP. */
1488	#define MSR_IA32_SYSENTER_EIP 0x176
1489	#endif
1490
1491	/** Machine Check Global Capabilities Register. */
1492	#define MSR_IA32_MCG_CAP 0x179
1493	/** Machine Check Global Status Register. */
1494	#define MSR_IA32_MCG_STATUS 0x17A
1495	/** Machine Check Global Control Register. */
1496	#define MSR_IA32_MCG_CTRL 0x17B
1497
1498	/** Page Attribute Table. */
1499	#define MSR_IA32_CR_PAT 0x277
1500	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1501	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1502	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1503
1504	/** Memory types that can be encoded in the IA32_PAT MSR.
1505	* @{ */
1506	/** Uncacheable. */
1507	#define MSR_IA32_PAT_MT_UC 0
1508	/** Write Combining. */
1509	#define MSR_IA32_PAT_MT_WC 1
1510	/** Reserved value 2. */
1511	#define MSR_IA32_PAT_MT_RSVD_2 2
1512	/** Reserved value 3. */
1513	#define MSR_IA32_PAT_MT_RSVD_3 3
1514	/** Write-through. */
1515	#define MSR_IA32_PAT_MT_WT 4
1516	/** Write-protected. */
1517	#define MSR_IA32_PAT_MT_WP 5
1518	/** Writeback. */
1519	#define MSR_IA32_PAT_MT_WB 6
1520	/** Uncached (UC-). */
1521	#define MSR_IA32_PAT_MT_UCD 7
1522	/** @}*/
1523
1524
1525	/** Performance event select MSRs. (Intel only) */
1526	#define MSR_IA32_PERFEVTSEL0 0x186
1527	#define MSR_IA32_PERFEVTSEL1 0x187
1528	#define MSR_IA32_PERFEVTSEL2 0x188
1529	#define MSR_IA32_PERFEVTSEL3 0x189
1530
1531	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1532	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1533	* holds a ratio that Apple takes for TSC granularity.
1534	*
1535	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1536	#define MSR_FLEX_RATIO 0x194
1537	/** Performance state value and starting with Intel core more.
1538	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1539	#define MSR_IA32_PERF_STATUS 0x198
1540	#define MSR_IA32_PERF_CTL 0x199
1541	#define MSR_IA32_THERM_STATUS 0x19c
1542
1543	/** Offcore response event select registers. */
1544	#define MSR_OFFCORE_RSP_0 0x1a6
1545	#define MSR_OFFCORE_RSP_1 0x1a7
1546
1547	/** Enable misc. processor features (R/W). */
1548	#define MSR_IA32_MISC_ENABLE 0x1A0
1549	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1550	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1551	/** Automatic Thermal Control Circuit Enable (R/W). */
1552	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1553	/** Performance Monitoring Available (R). */
1554	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1555	/** Branch Trace Storage Unavailable (R/O). */
1556	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1557	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1558	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1559	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1560	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1561	/** If MONITOR/MWAIT is supported (R/W). */
1562	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1563	/** Limit CPUID Maxval to 3 leafs (R/W). */
1564	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1565	/** When set to 1, xTPR messages are disabled (R/W). */
1566	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1567	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1568	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1569
1570	/** Trace/Profile Resource Control (R/W) */
1571	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1572	/** Last branch record. */
1573	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1574	/** Branch trace flag (single step on branches). */
1575	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1576	/** Performance monitoring pin control (AMD only). */
1577	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1578	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1579	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1580	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1581	/** Trace message enable (Intel only). */
1582	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1583	/** Branch trace store (Intel only). */
1584	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1585	/** Branch trace interrupt (Intel only). */
1586	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1587	/** Branch trace off in privileged code (Intel only). */
1588	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1589	/** Branch trace off in user code (Intel only). */
1590	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1591	/** Freeze LBR on PMI flag (Intel only). */
1592	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1593	/** Freeze PERFMON on PMI flag (Intel only). */
1594	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1595	/** Freeze while SMM enabled (Intel only). */
1596	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1597	/** Advanced debugging of RTM regions (Intel only). */
1598	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1599	/** Debug control MSR valid bits (Intel only). */
1600	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1601	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1602	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1603	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1604	\| MSR_IA32_DEBUGCTL_RTM)
1605
1606	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1607	* @{ */
1608	#define MSR_P4_LASTBRANCH_0 0x1db
1609	#define MSR_P4_LASTBRANCH_1 0x1dc
1610	#define MSR_P4_LASTBRANCH_2 0x1dd
1611	#define MSR_P4_LASTBRANCH_3 0x1de
1612
1613	/** LBR Top-of-stack MSR (index to most recent record). */
1614	#define MSR_P4_LASTBRANCH_TOS 0x1da
1615	/** @} */
1616
1617	/** @name Last branch registers for Core 2 and related Xeons.
1618	* @{ */
1619	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1620	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1621	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1622	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1623
1624	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1625	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1626	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1627	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1628
1629	/** LBR Top-of-stack MSR (index to most recent record). */
1630	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1631	/** @} */
1632
1633	/** @name Last branch registers.
1634	* @{ */
1635	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1636	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1637	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1638	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1639	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1640	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1641	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1642	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1643	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1644	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1645	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1646	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1647	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1648	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1649	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1650	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1651	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1652	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1653	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1654	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1655	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1656	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1657	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1658	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1659	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1660	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1661	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1662	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1663	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1664	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1665	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1666	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1667
1668	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1669	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1670	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1671	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1672	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1673	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1674	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1675	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1676	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1677	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1678	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1679	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1680	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1681	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1682	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1683	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1684	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1685	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1686	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1687	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1688	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1689	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1690	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1691	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1692	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1693	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1694	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1695	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1696	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1697	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1698	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1699	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1700
1701	#define MSR_LASTBRANCH_0_INFO 0xdc0
1702	#define MSR_LASTBRANCH_1_INFO 0xdc1
1703	#define MSR_LASTBRANCH_2_INFO 0xdc2
1704	#define MSR_LASTBRANCH_3_INFO 0xdc3
1705	#define MSR_LASTBRANCH_4_INFO 0xdc4
1706	#define MSR_LASTBRANCH_5_INFO 0xdc5
1707	#define MSR_LASTBRANCH_6_INFO 0xdc6
1708	#define MSR_LASTBRANCH_7_INFO 0xdc7
1709	#define MSR_LASTBRANCH_8_INFO 0xdc8
1710	#define MSR_LASTBRANCH_9_INFO 0xdc9
1711	#define MSR_LASTBRANCH_10_INFO 0xdca
1712	#define MSR_LASTBRANCH_11_INFO 0xdcb
1713	#define MSR_LASTBRANCH_12_INFO 0xdcc
1714	#define MSR_LASTBRANCH_13_INFO 0xdcd
1715	#define MSR_LASTBRANCH_14_INFO 0xdce
1716	#define MSR_LASTBRANCH_15_INFO 0xdcf
1717	#define MSR_LASTBRANCH_16_INFO 0xdd0
1718	#define MSR_LASTBRANCH_17_INFO 0xdd1
1719	#define MSR_LASTBRANCH_18_INFO 0xdd2
1720	#define MSR_LASTBRANCH_19_INFO 0xdd3
1721	#define MSR_LASTBRANCH_20_INFO 0xdd4
1722	#define MSR_LASTBRANCH_21_INFO 0xdd5
1723	#define MSR_LASTBRANCH_22_INFO 0xdd6
1724	#define MSR_LASTBRANCH_23_INFO 0xdd7
1725	#define MSR_LASTBRANCH_24_INFO 0xdd8
1726	#define MSR_LASTBRANCH_25_INFO 0xdd9
1727	#define MSR_LASTBRANCH_26_INFO 0xdda
1728	#define MSR_LASTBRANCH_27_INFO 0xddb
1729	#define MSR_LASTBRANCH_28_INFO 0xddc
1730	#define MSR_LASTBRANCH_29_INFO 0xddd
1731	#define MSR_LASTBRANCH_30_INFO 0xdde
1732	#define MSR_LASTBRANCH_31_INFO 0xddf
1733
1734	/** LBR branch tracking selection MSR. */
1735	#define MSR_LASTBRANCH_SELECT 0x1c8
1736	/** LBR Top-of-stack MSR (index to most recent record). */
1737	#define MSR_LASTBRANCH_TOS 0x1c9
1738	/** @} */
1739
1740	/** @name Last event record registers.
1741	* @{ */
1742	/** Last event record source IP register. */
1743	#define MSR_LER_FROM_IP 0x1dd
1744	/** Last event record destination IP register. */
1745	#define MSR_LER_TO_IP 0x1de
1746	/** @} */
1747
1748	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1749	#define MSR_IA32_TSX_CTRL 0x122
1750
1751	/** Variable range MTRRs.
1752	* @{ */
1753	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1754	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1755	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1756	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1757	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1758	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1759	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1760	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1761	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1762	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1763	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1764	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1765	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1766	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1767	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1768	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1769	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1770	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1771	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1772	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1773	/** @} */
1774
1775	/** Fixed range MTRRs.
1776	* @{ */
1777	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1778	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1779	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1780	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1781	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1782	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1783	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1784	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1785	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1786	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1787	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1788	/** @} */
1789
1790	/** MTRR Default Type.
1791	* @{ */
1792	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1793	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1794	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1795	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1796	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1797	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1798	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1799	/** @} */
1800
1801	/** Variable-range MTRR physical mask valid. */
1802	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1803
1804	/** Variable-range MTRR memory type mask. */
1805	#define MSR_IA32_MTRR_PHYSBASE_MT_MASK UINT64_C(0xff)
1806
1807	/** Global performance counter control facilities (Intel only). */
1808	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1809	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1810	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1811
1812	/** Precise Event Based sampling (Intel only). */
1813	#define MSR_IA32_PEBS_ENABLE 0x3F1
1814
1815	#define MSR_IA32_MC0_CTL 0x400
1816	#define MSR_IA32_MC0_STATUS 0x401
1817
1818	/** Basic VMX information. */
1819	#define MSR_IA32_VMX_BASIC 0x480
1820	/** Allowed settings for pin-based VM execution controls. */
1821	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1822	/** Allowed settings for proc-based VM execution controls. */
1823	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1824	/** Allowed settings for the VM-exit controls. */
1825	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1826	/** Allowed settings for the VM-entry controls. */
1827	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1828	/** Misc VMX info. */
1829	#define MSR_IA32_VMX_MISC 0x485
1830	/** Fixed cleared bits in CR0. */
1831	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1832	/** Fixed set bits in CR0. */
1833	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1834	/** Fixed cleared bits in CR4. */
1835	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1836	/** Fixed set bits in CR4. */
1837	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1838	/** Information for enumerating fields in the VMCS. */
1839	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1840	/** Allowed settings for secondary processor-based VM-execution controls. */
1841	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1842	/** EPT capabilities. */
1843	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1844	/** Allowed settings of all pin-based VM execution controls. */
1845	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1846	/** Allowed settings of all proc-based VM execution controls. */
1847	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1848	/** Allowed settings of all VMX exit controls. */
1849	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1850	/** Allowed settings of all VMX entry controls. */
1851	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1852	/** Allowed settings for the VM-function controls. */
1853	#define MSR_IA32_VMX_VMFUNC 0x491
1854	/** Tertiary processor-based VM execution controls. */
1855	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1856	/** Secondary VM-exit controls. */
1857	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
1858
1859	/** Intel PT - Enable and control for trace packet generation. */
1860	#define MSR_IA32_RTIT_CTL 0x570
1861
1862	/** DS Save Area (R/W). */
1863	#define MSR_IA32_DS_AREA 0x600
1864	/** Running Average Power Limit (RAPL) power units. */
1865	#define MSR_RAPL_POWER_UNIT 0x606
1866	/** Package C3 Interrupt Response Limit. */
1867	#define MSR_PKGC3_IRTL 0x60a
1868	/** Package C6/C7S Interrupt Response Limit 1. */
1869	#define MSR_PKGC_IRTL1 0x60b
1870	/** Package C6/C7S Interrupt Response Limit 2. */
1871	#define MSR_PKGC_IRTL2 0x60c
1872	/** Package C2 Residency Counter. */
1873	#define MSR_PKG_C2_RESIDENCY 0x60d
1874	/** PKG RAPL Power Limit Control. */
1875	#define MSR_PKG_POWER_LIMIT 0x610
1876	/** PKG Energy Status. */
1877	#define MSR_PKG_ENERGY_STATUS 0x611
1878	/** PKG Perf Status. */
1879	#define MSR_PKG_PERF_STATUS 0x613
1880	/** PKG RAPL Parameters. */
1881	#define MSR_PKG_POWER_INFO 0x614
1882	/** DRAM RAPL Power Limit Control. */
1883	#define MSR_DRAM_POWER_LIMIT 0x618
1884	/** DRAM Energy Status. */
1885	#define MSR_DRAM_ENERGY_STATUS 0x619
1886	/** DRAM Performance Throttling Status. */
1887	#define MSR_DRAM_PERF_STATUS 0x61b
1888	/** DRAM RAPL Parameters. */
1889	#define MSR_DRAM_POWER_INFO 0x61c
1890	/** Package C10 Residency Counter. */
1891	#define MSR_PKG_C10_RESIDENCY 0x632
1892	/** PP0 Energy Status. */
1893	#define MSR_PP0_ENERGY_STATUS 0x639
1894	/** PP1 Energy Status. */
1895	#define MSR_PP1_ENERGY_STATUS 0x641
1896	/** Turbo Activation Ratio. */
1897	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1898	/** Core Performance Limit Reasons. */
1899	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1900
1901	/** Userspace Control flow Enforcement Technology setting. */
1902	#define MSR_IA32_U_CET 0x6a0
1903	/** Supervisor space Control flow Enforcement Technology setting. */
1904	#define MSR_IA32_S_CET 0x6a2
1905	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
1906	* @{ */
1907	/** Enables the Shadow stack. */
1908	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
1909	/** Enables WRSS{D,Q}W instructions. */
1910	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
1911	/** Enables indirect branch tracking. */
1912	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
1913	/** Enable legacy compatibility treatment for indirect branch tracking. */
1914	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
1915	/** Enables the use of no-track prefix for indirect branch tracking. */
1916	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
1917	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
1918	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
1919	/** Suppresses indirect branch tracking. */
1920	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
1921	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
1922	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
1923	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
1924	* on a ENDBRANCH instruction. */
1925	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
1926	/** @} */
1927
1928	/** X2APIC MSR range start. */
1929	#define MSR_IA32_X2APIC_START 0x800
1930	/** X2APIC MSR - APIC ID Register. */
1931	#define MSR_IA32_X2APIC_ID 0x802
1932	/** X2APIC MSR - APIC Version Register. */
1933	#define MSR_IA32_X2APIC_VERSION 0x803
1934	/** X2APIC MSR - Task Priority Register. */
1935	#define MSR_IA32_X2APIC_TPR 0x808
1936	/** X2APIC MSR - Processor Priority register. */
1937	#define MSR_IA32_X2APIC_PPR 0x80A
1938	/** X2APIC MSR - End Of Interrupt register. */
1939	#define MSR_IA32_X2APIC_EOI 0x80B
1940	/** X2APIC MSR - Logical Destination Register. */
1941	#define MSR_IA32_X2APIC_LDR 0x80D
1942	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1943	#define MSR_IA32_X2APIC_SVR 0x80F
1944	/** X2APIC MSR - In-service Register (bits 31:0). */
1945	#define MSR_IA32_X2APIC_ISR0 0x810
1946	/** X2APIC MSR - In-service Register (bits 63:32). */
1947	#define MSR_IA32_X2APIC_ISR1 0x811
1948	/** X2APIC MSR - In-service Register (bits 95:64). */
1949	#define MSR_IA32_X2APIC_ISR2 0x812
1950	/** X2APIC MSR - In-service Register (bits 127:96). */
1951	#define MSR_IA32_X2APIC_ISR3 0x813
1952	/** X2APIC MSR - In-service Register (bits 159:128). */
1953	#define MSR_IA32_X2APIC_ISR4 0x814
1954	/** X2APIC MSR - In-service Register (bits 191:160). */
1955	#define MSR_IA32_X2APIC_ISR5 0x815
1956	/** X2APIC MSR - In-service Register (bits 223:192). */
1957	#define MSR_IA32_X2APIC_ISR6 0x816
1958	/** X2APIC MSR - In-service Register (bits 255:224). */
1959	#define MSR_IA32_X2APIC_ISR7 0x817
1960	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1961	#define MSR_IA32_X2APIC_TMR0 0x818
1962	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1963	#define MSR_IA32_X2APIC_TMR1 0x819
1964	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1965	#define MSR_IA32_X2APIC_TMR2 0x81A
1966	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1967	#define MSR_IA32_X2APIC_TMR3 0x81B
1968	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1969	#define MSR_IA32_X2APIC_TMR4 0x81C
1970	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1971	#define MSR_IA32_X2APIC_TMR5 0x81D
1972	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1973	#define MSR_IA32_X2APIC_TMR6 0x81E
1974	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1975	#define MSR_IA32_X2APIC_TMR7 0x81F
1976	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1977	#define MSR_IA32_X2APIC_IRR0 0x820
1978	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1979	#define MSR_IA32_X2APIC_IRR1 0x821
1980	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1981	#define MSR_IA32_X2APIC_IRR2 0x822
1982	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1983	#define MSR_IA32_X2APIC_IRR3 0x823
1984	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1985	#define MSR_IA32_X2APIC_IRR4 0x824
1986	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1987	#define MSR_IA32_X2APIC_IRR5 0x825
1988	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1989	#define MSR_IA32_X2APIC_IRR6 0x826
1990	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1991	#define MSR_IA32_X2APIC_IRR7 0x827
1992	/** X2APIC MSR - Error Status Register. */
1993	#define MSR_IA32_X2APIC_ESR 0x828
1994	/** X2APIC MSR - LVT CMCI Register. */
1995	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1996	/** X2APIC MSR - Interrupt Command Register. */
1997	#define MSR_IA32_X2APIC_ICR 0x830
1998	/** X2APIC MSR - LVT Timer Register. */
1999	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
2000	/** X2APIC MSR - LVT Thermal Sensor Register. */
2001	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
2002	/** X2APIC MSR - LVT Performance Counter Register. */
2003	#define MSR_IA32_X2APIC_LVT_PERF 0x834
2004	/** X2APIC MSR - LVT LINT0 Register. */
2005	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2006	/** X2APIC MSR - LVT LINT1 Register. */
2007	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2008	/** X2APIC MSR - LVT Error Register . */
2009	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2010	/** X2APIC MSR - Timer Initial Count Register. */
2011	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2012	/** X2APIC MSR - Timer Current Count Register. */
2013	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2014	/** X2APIC MSR - Timer Divide Configuration Register. */
2015	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2016	/** X2APIC MSR - Self IPI. */
2017	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2018	/** X2APIC MSR range end. */
2019	#define MSR_IA32_X2APIC_END 0x8FF
2020	/** X2APIC MSR - LVT start range. */
2021	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2022	/** X2APIC MSR - LVT end range (inclusive). */
2023	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2024
2025	/** K6 EFER - Extended Feature Enable Register. */
2026	#define MSR_K6_EFER UINT32_C(0xc0000080)
2027	/** @todo document EFER */
2028	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2029	#define MSR_K6_EFER_SCE RT_BIT_32(0)
2030	/** Bit 8 - LME - Long mode enabled. (R/W) */
2031	#define MSR_K6_EFER_LME RT_BIT_32(8)
2032	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
2033	/** Bit 10 - LMA - Long mode active. (R) */
2034	#define MSR_K6_EFER_LMA RT_BIT_32(10)
2035	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
2036	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2037	#define MSR_K6_EFER_NXE RT_BIT_32(11)
2038	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
2039	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2040	#define MSR_K6_EFER_SVME RT_BIT_32(12)
2041	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2042	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2043	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
2044	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2045	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2046	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2047	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2048	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2049
2050	/** K6 STAR - SYSCALL/RET targets. */
2051	#define MSR_K6_STAR UINT32_C(0xc0000081)
2052	/** Shift value for getting the SYSRET CS and SS value. */
2053	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2054	/** Shift value for getting the SYSCALL CS and SS value. */
2055	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2056	/** Selector mask for use after shifting. */
2057	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2058	/** The mask which give the SYSCALL EIP. */
2059	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2060	/** K6 WHCR - Write Handling Control Register. */
2061	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2062	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2063	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2064	/** K6 PSOR - Processor State Observability Register. */
2065	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2066	/** K6 PFIR - Page Flush/Invalidate Register. */
2067	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2068
2069	/** Performance counter MSRs. (AMD only) */
2070	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2071	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2072	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2073	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2074	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2075	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2076	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2077	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2078
2079	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2080	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2081	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2082	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2083	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2084	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2085	/** K8 FS.base - The 64-bit base FS register. */
2086	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2087	/** K8 GS.base - The 64-bit base GS register. */
2088	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2089	/** K8 KernelGSbase - Used with SWAPGS. */
2090	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2091	/** K8 TSC_AUX - Used with RDTSCP. */
2092	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2093	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2094	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2095	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2096	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2097	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2098	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2099	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2100	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2101
2102	/** SMM MSRs. */
2103	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2104	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2105	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2106
2107	/** North bridge config? See BIOS & Kernel dev guides for
2108	* details. */
2109	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2110
2111	/** Hypertransport interrupt pending register.
2112	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2113	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2114
2115	/** SVM Control. */
2116	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2117	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2118	* features. */
2119	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2120	/** If set, non-intercepted INIT signals are converted to \#SX
2121	* exceptions. */
2122	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2123	/** Disables A20 masking. */
2124	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2125	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2126	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2127	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2128	* clear, EFER.SVME can be written normally. */
2129	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2130
2131	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2132	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2133	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2134	* host state during world switch. */
2135	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2136
2137	/** Virtualized speculation control for AMD processors.
2138	*
2139	* Unified interface among different CPU generations.
2140	* The VMM will set any architectural MSRs based on the CPU.
2141	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2142	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2143	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2144	/** Speculative Store Bypass Disable. */
2145	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2146
2147	/** @} */
2148
2149
2150	/** @name Page Table / Directory / Directory Pointers / L4.
2151	* @{
2152	*/
2153
2154	/** Page table/directory entry as an unsigned integer. */
2155	typedef uint32_t X86PGUINT;
2156	/** Pointer to a page table/directory table entry as an unsigned integer. */
2157	typedef X86PGUINT *PX86PGUINT;
2158	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2159	typedef X86PGUINT const *PCX86PGUINT;
2160
2161	/** Number of entries in a 32-bit PT/PD. */
2162	#define X86_PG_ENTRIES 1024
2163
2164
2165	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2166	typedef uint64_t X86PGPAEUINT;
2167	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2168	typedef X86PGPAEUINT *PX86PGPAEUINT;
2169	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2170	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2171
2172	/** Number of entries in a PAE PT/PD. */
2173	#define X86_PG_PAE_ENTRIES 512
2174	/** Number of entries in a PAE PDPT. */
2175	#define X86_PG_PAE_PDPE_ENTRIES 4
2176
2177	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2178	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2179	/** Number of entries in an AMD64 PDPT.
2180	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2181	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2182
2183	/** The size of a default page. */
2184	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2185	/** The page shift of a default page. */
2186	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2187	/** The default page offset mask. */
2188	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2189	/** The default page base mask for virtual addresses. */
2190	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2191	/** The default page base mask for virtual addresses - 32bit version. */
2192	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2193
2194	/** The size of a 4KB page. */
2195	#define X86_PAGE_4K_SIZE _4K
2196	/** The page shift of a 4KB page. */
2197	#define X86_PAGE_4K_SHIFT 12
2198	/** The 4KB page offset mask. */
2199	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2200	/** The 4KB page base mask for virtual addresses. */
2201	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2202	/** The 4KB page base mask for virtual addresses - 32bit version. */
2203	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2204
2205	/** The size of a 2MB page. */
2206	#define X86_PAGE_2M_SIZE _2M
2207	/** The page shift of a 2MB page. */
2208	#define X86_PAGE_2M_SHIFT 21
2209	/** The 2MB page offset mask. */
2210	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2211	/** The 2MB page base mask for virtual addresses. */
2212	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2213	/** The 2MB page base mask for virtual addresses - 32bit version. */
2214	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2215
2216	/** The size of a 4MB page. */
2217	#define X86_PAGE_4M_SIZE _4M
2218	/** The page shift of a 4MB page. */
2219	#define X86_PAGE_4M_SHIFT 22
2220	/** The 4MB page offset mask. */
2221	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2222	/** The 4MB page base mask for virtual addresses. */
2223	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2224	/** The 4MB page base mask for virtual addresses - 32bit version. */
2225	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2226
2227	/** The size of a 1GB page. */
2228	#define X86_PAGE_1G_SIZE _1G
2229	/** The page shift of a 1GB page. */
2230	#define X86_PAGE_1G_SHIFT 30
2231	/** The 1GB page offset mask. */
2232	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2233	/** The 1GB page base mask for virtual addresses. */
2234	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2235
2236	/**
2237	* Check if the given address is canonical.
2238	*/
2239	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2240
2241	/**
2242	* Gets the page base mask given the page shift.
2243	*/
2244	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2245
2246	/**
2247	* Gets the page offset mask given the page shift.
2248	*/
2249	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2250
2251
2252	/** @name Page Table Entry
2253	* @{
2254	*/
2255	/** Bit 0 - P - Present bit. */
2256	#define X86_PTE_BIT_P 0
2257	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2258	#define X86_PTE_BIT_RW 1
2259	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2260	#define X86_PTE_BIT_US 2
2261	/** Bit 3 - PWT - Page level write thru bit. */
2262	#define X86_PTE_BIT_PWT 3
2263	/** Bit 4 - PCD - Page level cache disable bit. */
2264	#define X86_PTE_BIT_PCD 4
2265	/** Bit 5 - A - Access bit. */
2266	#define X86_PTE_BIT_A 5
2267	/** Bit 6 - D - Dirty bit. */
2268	#define X86_PTE_BIT_D 6
2269	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2270	#define X86_PTE_BIT_PAT 7
2271	/** Bit 8 - G - Global flag. */
2272	#define X86_PTE_BIT_G 8
2273	/** Bits 63 - NX - PAE/LM - No execution flag. */
2274	#define X86_PTE_PAE_BIT_NX 63
2275
2276	/** Bit 0 - P - Present bit mask. */
2277	#define X86_PTE_P RT_BIT_32(0)
2278	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2279	#define X86_PTE_RW RT_BIT_32(1)
2280	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2281	#define X86_PTE_US RT_BIT_32(2)
2282	/** Bit 3 - PWT - Page level write thru bit mask. */
2283	#define X86_PTE_PWT RT_BIT_32(3)
2284	/** Bit 4 - PCD - Page level cache disable bit mask. */
2285	#define X86_PTE_PCD RT_BIT_32(4)
2286	/** Bit 5 - A - Access bit mask. */
2287	#define X86_PTE_A RT_BIT_32(5)
2288	/** Bit 6 - D - Dirty bit mask. */
2289	#define X86_PTE_D RT_BIT_32(6)
2290	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2291	#define X86_PTE_PAT RT_BIT_32(7)
2292	/** Bit 8 - G - Global bit mask. */
2293	#define X86_PTE_G RT_BIT_32(8)
2294
2295	/** Bits 9-11 - - Available for use to system software. */
2296	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2297	/** Bits 12-31 - - Physical Page number of the next level. */
2298	#define X86_PTE_PG_MASK ( 0xfffff000 )
2299
2300	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2301	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2302	/** Bits 63 - NX - PAE/LM - No execution flag. */
2303	#define X86_PTE_PAE_NX RT_BIT_64(63)
2304	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2305	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2306	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2307	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2308	/** No bits - - LM - MBZ bits when NX is active. */
2309	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2310	/** Bits 63 - - LM - MBZ bits when no NX. */
2311	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2312
2313	/**
2314	* Page table entry.
2315	*/
2316	typedef struct X86PTEBITS
2317	{
2318	/** Flags whether(=1) or not the page is present. */
2319	uint32_t u1Present : 1;
2320	/** Read(=0) / Write(=1) flag. */
2321	uint32_t u1Write : 1;
2322	/** User(=1) / Supervisor (=0) flag. */
2323	uint32_t u1User : 1;
2324	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2325	uint32_t u1WriteThru : 1;
2326	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2327	uint32_t u1CacheDisable : 1;
2328	/** Accessed flag.
2329	* Indicates that the page have been read or written to. */
2330	uint32_t u1Accessed : 1;
2331	/** Dirty flag.
2332	* Indicates that the page has been written to. */
2333	uint32_t u1Dirty : 1;
2334	/** Reserved / If PAT enabled, bit 2 of the index. */
2335	uint32_t u1PAT : 1;
2336	/** Global flag. (Ignored in all but final level.) */
2337	uint32_t u1Global : 1;
2338	/** Available for use to system software. */
2339	uint32_t u3Available : 3;
2340	/** Physical Page number of the next level. */
2341	uint32_t u20PageNo : 20;
2342	} X86PTEBITS;
2343	#ifndef VBOX_FOR_DTRACE_LIB
2344	AssertCompileSize(X86PTEBITS, 4);
2345	#endif
2346	/** Pointer to a page table entry. */
2347	typedef X86PTEBITS *PX86PTEBITS;
2348	/** Pointer to a const page table entry. */
2349	typedef const X86PTEBITS *PCX86PTEBITS;
2350
2351	/**
2352	* Page table entry.
2353	*/
2354	typedef union X86PTE
2355	{
2356	/** Unsigned integer view */
2357	X86PGUINT u;
2358	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2359	/** Bit field view. */
2360	X86PTEBITS n;
2361	#endif
2362	/** 32-bit view. */
2363	uint32_t au32[1];
2364	/** 16-bit view. */
2365	uint16_t au16[2];
2366	/** 8-bit view. */
2367	uint8_t au8[4];
2368	} X86PTE;
2369	#ifndef VBOX_FOR_DTRACE_LIB
2370	AssertCompileSize(X86PTE, 4);
2371	#endif
2372	/** Pointer to a page table entry. */
2373	typedef X86PTE *PX86PTE;
2374	/** Pointer to a const page table entry. */
2375	typedef const X86PTE *PCX86PTE;
2376
2377
2378	/**
2379	* PAE page table entry.
2380	*/
2381	typedef struct X86PTEPAEBITS
2382	{
2383	/** Flags whether(=1) or not the page is present. */
2384	uint32_t u1Present : 1;
2385	/** Read(=0) / Write(=1) flag. */
2386	uint32_t u1Write : 1;
2387	/** User(=1) / Supervisor(=0) flag. */
2388	uint32_t u1User : 1;
2389	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2390	uint32_t u1WriteThru : 1;
2391	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2392	uint32_t u1CacheDisable : 1;
2393	/** Accessed flag.
2394	* Indicates that the page have been read or written to. */
2395	uint32_t u1Accessed : 1;
2396	/** Dirty flag.
2397	* Indicates that the page has been written to. */
2398	uint32_t u1Dirty : 1;
2399	/** Reserved / If PAT enabled, bit 2 of the index. */
2400	uint32_t u1PAT : 1;
2401	/** Global flag. (Ignored in all but final level.) */
2402	uint32_t u1Global : 1;
2403	/** Available for use to system software. */
2404	uint32_t u3Available : 3;
2405	/** Physical Page number of the next level - Low Part. Don't use this. */
2406	uint32_t u20PageNoLow : 20;
2407	/** Physical Page number of the next level - High Part. Don't use this. */
2408	uint32_t u20PageNoHigh : 20;
2409	/** MBZ bits */
2410	uint32_t u11Reserved : 11;
2411	/** No Execute flag. */
2412	uint32_t u1NoExecute : 1;
2413	} X86PTEPAEBITS;
2414	#ifndef VBOX_FOR_DTRACE_LIB
2415	AssertCompileSize(X86PTEPAEBITS, 8);
2416	#endif
2417	/** Pointer to a page table entry. */
2418	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2419	/** Pointer to a page table entry. */
2420	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2421
2422	/**
2423	* PAE Page table entry.
2424	*/
2425	typedef union X86PTEPAE
2426	{
2427	/** Unsigned integer view */
2428	X86PGPAEUINT u;
2429	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2430	/** Bit field view. */
2431	X86PTEPAEBITS n;
2432	#endif
2433	/** 32-bit view. */
2434	uint32_t au32[2];
2435	/** 16-bit view. */
2436	uint16_t au16[4];
2437	/** 8-bit view. */
2438	uint8_t au8[8];
2439	} X86PTEPAE;
2440	#ifndef VBOX_FOR_DTRACE_LIB
2441	AssertCompileSize(X86PTEPAE, 8);
2442	#endif
2443	/** Pointer to a PAE page table entry. */
2444	typedef X86PTEPAE *PX86PTEPAE;
2445	/** Pointer to a const PAE page table entry. */
2446	typedef const X86PTEPAE *PCX86PTEPAE;
2447	/** @} */
2448
2449	/**
2450	* Page table.
2451	*/
2452	typedef struct X86PT
2453	{
2454	/** PTE Array. */
2455	X86PTE a[X86_PG_ENTRIES];
2456	} X86PT;
2457	#ifndef VBOX_FOR_DTRACE_LIB
2458	AssertCompileSize(X86PT, 4096);
2459	#endif
2460	/** Pointer to a page table. */
2461	typedef X86PT *PX86PT;
2462	/** Pointer to a const page table. */
2463	typedef const X86PT *PCX86PT;
2464
2465	/** The page shift to get the PT index. */
2466	#define X86_PT_SHIFT 12
2467	/** The PT index mask (apply to a shifted page address). */
2468	#define X86_PT_MASK 0x3ff
2469
2470
2471	/**
2472	* Page directory.
2473	*/
2474	typedef struct X86PTPAE
2475	{
2476	/** PTE Array. */
2477	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2478	} X86PTPAE;
2479	#ifndef VBOX_FOR_DTRACE_LIB
2480	AssertCompileSize(X86PTPAE, 4096);
2481	#endif
2482	/** Pointer to a page table. */
2483	typedef X86PTPAE *PX86PTPAE;
2484	/** Pointer to a const page table. */
2485	typedef const X86PTPAE *PCX86PTPAE;
2486
2487	/** The page shift to get the PA PTE index. */
2488	#define X86_PT_PAE_SHIFT 12
2489	/** The PAE PT index mask (apply to a shifted page address). */
2490	#define X86_PT_PAE_MASK 0x1ff
2491
2492
2493	/** @name 4KB Page Directory Entry
2494	* @{
2495	*/
2496	/** Bit 0 - P - Present bit. */
2497	#define X86_PDE_P RT_BIT_32(0)
2498	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2499	#define X86_PDE_RW RT_BIT_32(1)
2500	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2501	#define X86_PDE_US RT_BIT_32(2)
2502	/** Bit 3 - PWT - Page level write thru bit. */
2503	#define X86_PDE_PWT RT_BIT_32(3)
2504	/** Bit 4 - PCD - Page level cache disable bit. */
2505	#define X86_PDE_PCD RT_BIT_32(4)
2506	/** Bit 5 - A - Access bit. */
2507	#define X86_PDE_A RT_BIT_32(5)
2508	/** Bit 7 - PS - Page size attribute.
2509	* Clear mean 4KB pages, set means large pages (2/4MB). */
2510	#define X86_PDE_PS RT_BIT_32(7)
2511	/** Bits 9-11 - - Available for use to system software. */
2512	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2513	/** Bits 12-31 - - Physical Page number of the next level. */
2514	#define X86_PDE_PG_MASK ( 0xfffff000 )
2515
2516	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2517	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2518	/** Bits 63 - NX - PAE/LM - No execution flag. */
2519	#define X86_PDE_PAE_NX RT_BIT_64(63)
2520	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2521	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2522	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2523	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2524	/** Bit 7 - - LM - MBZ bits when NX is active. */
2525	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2526	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2527	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2528
2529	/**
2530	* Page directory entry.
2531	*/
2532	typedef struct X86PDEBITS
2533	{
2534	/** Flags whether(=1) or not the page is present. */
2535	uint32_t u1Present : 1;
2536	/** Read(=0) / Write(=1) flag. */
2537	uint32_t u1Write : 1;
2538	/** User(=1) / Supervisor (=0) flag. */
2539	uint32_t u1User : 1;
2540	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2541	uint32_t u1WriteThru : 1;
2542	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2543	uint32_t u1CacheDisable : 1;
2544	/** Accessed flag.
2545	* Indicates that the page has been read or written to. */
2546	uint32_t u1Accessed : 1;
2547	/** Reserved / Ignored (dirty bit). */
2548	uint32_t u1Reserved0 : 1;
2549	/** Size bit if PSE is enabled - in any event it's 0. */
2550	uint32_t u1Size : 1;
2551	/** Reserved / Ignored (global bit). */
2552	uint32_t u1Reserved1 : 1;
2553	/** Available for use to system software. */
2554	uint32_t u3Available : 3;
2555	/** Physical Page number of the next level. */
2556	uint32_t u20PageNo : 20;
2557	} X86PDEBITS;
2558	#ifndef VBOX_FOR_DTRACE_LIB
2559	AssertCompileSize(X86PDEBITS, 4);
2560	#endif
2561	/** Pointer to a page directory entry. */
2562	typedef X86PDEBITS *PX86PDEBITS;
2563	/** Pointer to a const page directory entry. */
2564	typedef const X86PDEBITS *PCX86PDEBITS;
2565
2566
2567	/**
2568	* PAE page directory entry.
2569	*/
2570	typedef struct X86PDEPAEBITS
2571	{
2572	/** Flags whether(=1) or not the page is present. */
2573	uint32_t u1Present : 1;
2574	/** Read(=0) / Write(=1) flag. */
2575	uint32_t u1Write : 1;
2576	/** User(=1) / Supervisor (=0) flag. */
2577	uint32_t u1User : 1;
2578	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2579	uint32_t u1WriteThru : 1;
2580	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2581	uint32_t u1CacheDisable : 1;
2582	/** Accessed flag.
2583	* Indicates that the page has been read or written to. */
2584	uint32_t u1Accessed : 1;
2585	/** Reserved / Ignored (dirty bit). */
2586	uint32_t u1Reserved0 : 1;
2587	/** Size bit if PSE is enabled - in any event it's 0. */
2588	uint32_t u1Size : 1;
2589	/** Reserved / Ignored (global bit). / */
2590	uint32_t u1Reserved1 : 1;
2591	/** Available for use to system software. */
2592	uint32_t u3Available : 3;
2593	/** Physical Page number of the next level - Low Part. Don't use! */
2594	uint32_t u20PageNoLow : 20;
2595	/** Physical Page number of the next level - High Part. Don't use! */
2596	uint32_t u20PageNoHigh : 20;
2597	/** MBZ bits */
2598	uint32_t u11Reserved : 11;
2599	/** No Execute flag. */
2600	uint32_t u1NoExecute : 1;
2601	} X86PDEPAEBITS;
2602	#ifndef VBOX_FOR_DTRACE_LIB
2603	AssertCompileSize(X86PDEPAEBITS, 8);
2604	#endif
2605	/** Pointer to a page directory entry. */
2606	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2607	/** Pointer to a const page directory entry. */
2608	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2609
2610	/** @} */
2611
2612
2613	/** @name 2/4MB Page Directory Entry
2614	* @{
2615	*/
2616	/** Bit 0 - P - Present bit. */
2617	#define X86_PDE4M_P RT_BIT_32(0)
2618	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2619	#define X86_PDE4M_RW RT_BIT_32(1)
2620	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2621	#define X86_PDE4M_US RT_BIT_32(2)
2622	/** Bit 3 - PWT - Page level write thru bit. */
2623	#define X86_PDE4M_PWT RT_BIT_32(3)
2624	/** Bit 4 - PCD - Page level cache disable bit. */
2625	#define X86_PDE4M_PCD RT_BIT_32(4)
2626	/** Bit 5 - A - Access bit. */
2627	#define X86_PDE4M_A RT_BIT_32(5)
2628	/** Bit 6 - D - Dirty bit. */
2629	#define X86_PDE4M_D RT_BIT_32(6)
2630	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2631	#define X86_PDE4M_PS RT_BIT_32(7)
2632	/** Bit 8 - G - Global flag. */
2633	#define X86_PDE4M_G RT_BIT_32(8)
2634	/** Bits 9-11 - AVL - Available for use to system software. */
2635	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2636	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2637	#define X86_PDE4M_PAT RT_BIT_32(12)
2638	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2639	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2640	/** Bits 22-31 - - Physical Page number. */
2641	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2642	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2643	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2644	/** The number of bits to the high part of the page number. */
2645	#define X86_PDE4M_PG_HIGH_SHIFT 19
2646	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2647	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2648
2649	/** Bits 21-51 - - PAE/LM - Physical Page number.
2650	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2651	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2652	/** Bits 63 - NX - PAE/LM - No execution flag. */
2653	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2654	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2655	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2656	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2657	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2658	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2659	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2660	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2661	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2662
2663	/**
2664	* 4MB page directory entry.
2665	*/
2666	typedef struct X86PDE4MBITS
2667	{
2668	/** Flags whether(=1) or not the page is present. */
2669	uint32_t u1Present : 1;
2670	/** Read(=0) / Write(=1) flag. */
2671	uint32_t u1Write : 1;
2672	/** User(=1) / Supervisor (=0) flag. */
2673	uint32_t u1User : 1;
2674	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2675	uint32_t u1WriteThru : 1;
2676	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2677	uint32_t u1CacheDisable : 1;
2678	/** Accessed flag.
2679	* Indicates that the page have been read or written to. */
2680	uint32_t u1Accessed : 1;
2681	/** Dirty flag.
2682	* Indicates that the page has been written to. */
2683	uint32_t u1Dirty : 1;
2684	/** Page size flag - always 1 for 4MB entries. */
2685	uint32_t u1Size : 1;
2686	/** Global flag. */
2687	uint32_t u1Global : 1;
2688	/** Available for use to system software. */
2689	uint32_t u3Available : 3;
2690	/** Reserved / If PAT enabled, bit 2 of the index. */
2691	uint32_t u1PAT : 1;
2692	/** Bits 32-39 of the page number on AMD64.
2693	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2694	uint32_t u8PageNoHigh : 8;
2695	/** Reserved. */
2696	uint32_t u1Reserved : 1;
2697	/** Physical Page number of the page. */
2698	uint32_t u10PageNo : 10;
2699	} X86PDE4MBITS;
2700	#ifndef VBOX_FOR_DTRACE_LIB
2701	AssertCompileSize(X86PDE4MBITS, 4);
2702	#endif
2703	/** Pointer to a page table entry. */
2704	typedef X86PDE4MBITS *PX86PDE4MBITS;
2705	/** Pointer to a const page table entry. */
2706	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2707
2708
2709	/**
2710	* 2MB PAE page directory entry.
2711	*/
2712	typedef struct X86PDE2MPAEBITS
2713	{
2714	/** Flags whether(=1) or not the page is present. */
2715	uint32_t u1Present : 1;
2716	/** Read(=0) / Write(=1) flag. */
2717	uint32_t u1Write : 1;
2718	/** User(=1) / Supervisor(=0) flag. */
2719	uint32_t u1User : 1;
2720	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2721	uint32_t u1WriteThru : 1;
2722	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2723	uint32_t u1CacheDisable : 1;
2724	/** Accessed flag.
2725	* Indicates that the page have been read or written to. */
2726	uint32_t u1Accessed : 1;
2727	/** Dirty flag.
2728	* Indicates that the page has been written to. */
2729	uint32_t u1Dirty : 1;
2730	/** Page size flag - always 1 for 2MB entries. */
2731	uint32_t u1Size : 1;
2732	/** Global flag. */
2733	uint32_t u1Global : 1;
2734	/** Available for use to system software. */
2735	uint32_t u3Available : 3;
2736	/** Reserved / If PAT enabled, bit 2 of the index. */
2737	uint32_t u1PAT : 1;
2738	/** Reserved. */
2739	uint32_t u9Reserved : 9;
2740	/** Physical Page number of the next level - Low part. Don't use! */
2741	uint32_t u10PageNoLow : 10;
2742	/** Physical Page number of the next level - High part. Don't use! */
2743	uint32_t u20PageNoHigh : 20;
2744	/** MBZ bits */
2745	uint32_t u11Reserved : 11;
2746	/** No Execute flag. */
2747	uint32_t u1NoExecute : 1;
2748	} X86PDE2MPAEBITS;
2749	#ifndef VBOX_FOR_DTRACE_LIB
2750	AssertCompileSize(X86PDE2MPAEBITS, 8);
2751	#endif
2752	/** Pointer to a 2MB PAE page table entry. */
2753	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2754	/** Pointer to a 2MB PAE page table entry. */
2755	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2756
2757	/** @} */
2758
2759	/**
2760	* Page directory entry.
2761	*/
2762	typedef union X86PDE
2763	{
2764	/** Unsigned integer view. */
2765	X86PGUINT u;
2766	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2767	/** Normal view. */
2768	X86PDEBITS n;
2769	/** 4MB view (big). */
2770	X86PDE4MBITS b;
2771	#endif
2772	/** 8 bit unsigned integer view. */
2773	uint8_t au8[4];
2774	/** 16 bit unsigned integer view. */
2775	uint16_t au16[2];
2776	/** 32 bit unsigned integer view. */
2777	uint32_t au32[1];
2778	} X86PDE;
2779	#ifndef VBOX_FOR_DTRACE_LIB
2780	AssertCompileSize(X86PDE, 4);
2781	#endif
2782	/** Pointer to a page directory entry. */
2783	typedef X86PDE *PX86PDE;
2784	/** Pointer to a const page directory entry. */
2785	typedef const X86PDE *PCX86PDE;
2786
2787	/**
2788	* PAE page directory entry.
2789	*/
2790	typedef union X86PDEPAE
2791	{
2792	/** Unsigned integer view. */
2793	X86PGPAEUINT u;
2794	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2795	/** Normal view. */
2796	X86PDEPAEBITS n;
2797	/** 2MB page view (big). */
2798	X86PDE2MPAEBITS b;
2799	#endif
2800	/** 8 bit unsigned integer view. */
2801	uint8_t au8[8];
2802	/** 16 bit unsigned integer view. */
2803	uint16_t au16[4];
2804	/** 32 bit unsigned integer view. */
2805	uint32_t au32[2];
2806	} X86PDEPAE;
2807	#ifndef VBOX_FOR_DTRACE_LIB
2808	AssertCompileSize(X86PDEPAE, 8);
2809	#endif
2810	/** Pointer to a page directory entry. */
2811	typedef X86PDEPAE *PX86PDEPAE;
2812	/** Pointer to a const page directory entry. */
2813	typedef const X86PDEPAE *PCX86PDEPAE;
2814
2815	/**
2816	* Page directory.
2817	*/
2818	typedef struct X86PD
2819	{
2820	/** PDE Array. */
2821	X86PDE a[X86_PG_ENTRIES];
2822	} X86PD;
2823	#ifndef VBOX_FOR_DTRACE_LIB
2824	AssertCompileSize(X86PD, 4096);
2825	#endif
2826	/** Pointer to a page directory. */
2827	typedef X86PD *PX86PD;
2828	/** Pointer to a const page directory. */
2829	typedef const X86PD *PCX86PD;
2830
2831	/** The page shift to get the PD index. */
2832	#define X86_PD_SHIFT 22
2833	/** The PD index mask (apply to a shifted page address). */
2834	#define X86_PD_MASK 0x3ff
2835
2836
2837	/**
2838	* PAE page directory.
2839	*/
2840	typedef struct X86PDPAE
2841	{
2842	/** PDE Array. */
2843	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2844	} X86PDPAE;
2845	#ifndef VBOX_FOR_DTRACE_LIB
2846	AssertCompileSize(X86PDPAE, 4096);
2847	#endif
2848	/** Pointer to a PAE page directory. */
2849	typedef X86PDPAE *PX86PDPAE;
2850	/** Pointer to a const PAE page directory. */
2851	typedef const X86PDPAE *PCX86PDPAE;
2852
2853	/** The page shift to get the PAE PD index. */
2854	#define X86_PD_PAE_SHIFT 21
2855	/** The PAE PD index mask (apply to a shifted page address). */
2856	#define X86_PD_PAE_MASK 0x1ff
2857
2858
2859	/** @name Page Directory Pointer Table Entry (PAE)
2860	* @{
2861	*/
2862	/** Bit 0 - P - Present bit. */
2863	#define X86_PDPE_P RT_BIT_32(0)
2864	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2865	#define X86_PDPE_RW RT_BIT_32(1)
2866	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2867	#define X86_PDPE_US RT_BIT_32(2)
2868	/** Bit 3 - PWT - Page level write thru bit. */
2869	#define X86_PDPE_PWT RT_BIT_32(3)
2870	/** Bit 4 - PCD - Page level cache disable bit. */
2871	#define X86_PDPE_PCD RT_BIT_32(4)
2872	/** Bit 5 - A - Access bit. Long Mode only. */
2873	#define X86_PDPE_A RT_BIT_32(5)
2874	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2875	#define X86_PDPE_LM_PS RT_BIT_32(7)
2876	/** Bits 9-11 - - Available for use to system software. */
2877	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2878	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2879	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2880	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2881	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2882	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2883	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2884	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2885	#define X86_PDPE_LM_NX RT_BIT_64(63)
2886	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2887	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2888	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2889	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2890	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2891	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2892	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2893	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2894
2895
2896	/**
2897	* Page directory pointer table entry.
2898	*/
2899	typedef struct X86PDPEBITS
2900	{
2901	/** Flags whether(=1) or not the page is present. */
2902	uint32_t u1Present : 1;
2903	/** Chunk of reserved bits. */
2904	uint32_t u2Reserved : 2;
2905	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2906	uint32_t u1WriteThru : 1;
2907	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2908	uint32_t u1CacheDisable : 1;
2909	/** Chunk of reserved bits. */
2910	uint32_t u4Reserved : 4;
2911	/** Available for use to system software. */
2912	uint32_t u3Available : 3;
2913	/** Physical Page number of the next level - Low Part. Don't use! */
2914	uint32_t u20PageNoLow : 20;
2915	/** Physical Page number of the next level - High Part. Don't use! */
2916	uint32_t u20PageNoHigh : 20;
2917	/** MBZ bits */
2918	uint32_t u12Reserved : 12;
2919	} X86PDPEBITS;
2920	#ifndef VBOX_FOR_DTRACE_LIB
2921	AssertCompileSize(X86PDPEBITS, 8);
2922	#endif
2923	/** Pointer to a page directory pointer table entry. */
2924	typedef X86PDPEBITS *PX86PTPEBITS;
2925	/** Pointer to a const page directory pointer table entry. */
2926	typedef const X86PDPEBITS *PCX86PTPEBITS;
2927
2928	/**
2929	* Page directory pointer table entry. AMD64 version
2930	*/
2931	typedef struct X86PDPEAMD64BITS
2932	{
2933	/** Flags whether(=1) or not the page is present. */
2934	uint32_t u1Present : 1;
2935	/** Read(=0) / Write(=1) flag. */
2936	uint32_t u1Write : 1;
2937	/** User(=1) / Supervisor (=0) flag. */
2938	uint32_t u1User : 1;
2939	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2940	uint32_t u1WriteThru : 1;
2941	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2942	uint32_t u1CacheDisable : 1;
2943	/** Accessed flag.
2944	* Indicates that the page have been read or written to. */
2945	uint32_t u1Accessed : 1;
2946	/** Chunk of reserved bits. */
2947	uint32_t u3Reserved : 3;
2948	/** Available for use to system software. */
2949	uint32_t u3Available : 3;
2950	/** Physical Page number of the next level - Low Part. Don't use! */
2951	uint32_t u20PageNoLow : 20;
2952	/** Physical Page number of the next level - High Part. Don't use! */
2953	uint32_t u20PageNoHigh : 20;
2954	/** MBZ bits */
2955	uint32_t u11Reserved : 11;
2956	/** No Execute flag. */
2957	uint32_t u1NoExecute : 1;
2958	} X86PDPEAMD64BITS;
2959	#ifndef VBOX_FOR_DTRACE_LIB
2960	AssertCompileSize(X86PDPEAMD64BITS, 8);
2961	#endif
2962	/** Pointer to a page directory pointer table entry. */
2963	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2964	/** Pointer to a const page directory pointer table entry. */
2965	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2966
2967	/**
2968	* Page directory pointer table entry for 1GB page. (AMD64 only)
2969	*/
2970	typedef struct X86PDPE1GB
2971	{
2972	/** 0: Flags whether(=1) or not the page is present. */
2973	uint32_t u1Present : 1;
2974	/** 1: Read(=0) / Write(=1) flag. */
2975	uint32_t u1Write : 1;
2976	/** 2: User(=1) / Supervisor (=0) flag. */
2977	uint32_t u1User : 1;
2978	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2979	uint32_t u1WriteThru : 1;
2980	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2981	uint32_t u1CacheDisable : 1;
2982	/** 5: Accessed flag.
2983	* Indicates that the page have been read or written to. */
2984	uint32_t u1Accessed : 1;
2985	/** 6: Dirty flag for 1GB pages. */
2986	uint32_t u1Dirty : 1;
2987	/** 7: Indicates 1GB page if set. */
2988	uint32_t u1Size : 1;
2989	/** 8: Global 1GB page. */
2990	uint32_t u1Global: 1;
2991	/** 9-11: Available for use to system software. */
2992	uint32_t u3Available : 3;
2993	/** 12: PAT bit for 1GB page. */
2994	uint32_t u1PAT : 1;
2995	/** 13-29: MBZ bits. */
2996	uint32_t u17Reserved : 17;
2997	/** 30-31: Physical page number - Low Part. Don't use! */
2998	uint32_t u2PageNoLow : 2;
2999	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
3000	uint32_t u20PageNoHigh : 20;
3001	/** 52-62: MBZ bits */
3002	uint32_t u11Reserved : 11;
3003	/** 63: No Execute flag. */
3004	uint32_t u1NoExecute : 1;
3005	} X86PDPE1GB;
3006	#ifndef VBOX_FOR_DTRACE_LIB
3007	AssertCompileSize(X86PDPE1GB, 8);
3008	#endif
3009	/** Pointer to a page directory pointer table entry for a 1GB page. */
3010	typedef X86PDPE1GB *PX86PDPE1GB;
3011	/** Pointer to a const page directory pointer table entry for a 1GB page. */
3012	typedef const X86PDPE1GB *PCX86PDPE1GB;
3013
3014	/**
3015	* Page directory pointer table entry.
3016	*/
3017	typedef union X86PDPE
3018	{
3019	/** Unsigned integer view. */
3020	X86PGPAEUINT u;
3021	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3022	/** Normal view. */
3023	X86PDPEBITS n;
3024	/** AMD64 view. */
3025	X86PDPEAMD64BITS lm;
3026	/** AMD64 big view. */
3027	X86PDPE1GB b;
3028	#endif
3029	/** 8 bit unsigned integer view. */
3030	uint8_t au8[8];
3031	/** 16 bit unsigned integer view. */
3032	uint16_t au16[4];
3033	/** 32 bit unsigned integer view. */
3034	uint32_t au32[2];
3035	} X86PDPE;
3036	#ifndef VBOX_FOR_DTRACE_LIB
3037	AssertCompileSize(X86PDPE, 8);
3038	#endif
3039	/** Pointer to a page directory pointer table entry. */
3040	typedef X86PDPE *PX86PDPE;
3041	/** Pointer to a const page directory pointer table entry. */
3042	typedef const X86PDPE *PCX86PDPE;
3043
3044
3045	/**
3046	* Page directory pointer table.
3047	*/
3048	typedef struct X86PDPT
3049	{
3050	/** PDE Array. */
3051	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3052	} X86PDPT;
3053	#ifndef VBOX_FOR_DTRACE_LIB
3054	AssertCompileSize(X86PDPT, 4096);
3055	#endif
3056	/** Pointer to a page directory pointer table. */
3057	typedef X86PDPT *PX86PDPT;
3058	/** Pointer to a const page directory pointer table. */
3059	typedef const X86PDPT *PCX86PDPT;
3060
3061	/** The page shift to get the PDPT index. */
3062	#define X86_PDPT_SHIFT 30
3063	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3064	#define X86_PDPT_MASK_PAE 0x3
3065	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3066	#define X86_PDPT_MASK_AMD64 0x1ff
3067
3068	/** @} */
3069
3070
3071	/** @name Page Map Level-4 Entry (Long Mode PAE)
3072	* @{
3073	*/
3074	/** Bit 0 - P - Present bit. */
3075	#define X86_PML4E_P RT_BIT_32(0)
3076	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3077	#define X86_PML4E_RW RT_BIT_32(1)
3078	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3079	#define X86_PML4E_US RT_BIT_32(2)
3080	/** Bit 3 - PWT - Page level write thru bit. */
3081	#define X86_PML4E_PWT RT_BIT_32(3)
3082	/** Bit 4 - PCD - Page level cache disable bit. */
3083	#define X86_PML4E_PCD RT_BIT_32(4)
3084	/** Bit 5 - A - Access bit. */
3085	#define X86_PML4E_A RT_BIT_32(5)
3086	/** Bits 9-11 - - Available for use to system software. */
3087	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3088	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3089	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3090	/** Bits 8, 7 - - MBZ bits when NX is active. */
3091	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3092	/** Bits 63, 7 - - MBZ bits when no NX. */
3093	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3094	/** Bits 63 - NX - PAE - No execution flag. */
3095	#define X86_PML4E_NX RT_BIT_64(63)
3096
3097	/**
3098	* Page Map Level-4 Entry
3099	*/
3100	typedef struct X86PML4EBITS
3101	{
3102	/** Flags whether(=1) or not the page is present. */
3103	uint32_t u1Present : 1;
3104	/** Read(=0) / Write(=1) flag. */
3105	uint32_t u1Write : 1;
3106	/** User(=1) / Supervisor (=0) flag. */
3107	uint32_t u1User : 1;
3108	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3109	uint32_t u1WriteThru : 1;
3110	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3111	uint32_t u1CacheDisable : 1;
3112	/** Accessed flag.
3113	* Indicates that the page have been read or written to. */
3114	uint32_t u1Accessed : 1;
3115	/** Chunk of reserved bits. */
3116	uint32_t u3Reserved : 3;
3117	/** Available for use to system software. */
3118	uint32_t u3Available : 3;
3119	/** Physical Page number of the next level - Low Part. Don't use! */
3120	uint32_t u20PageNoLow : 20;
3121	/** Physical Page number of the next level - High Part. Don't use! */
3122	uint32_t u20PageNoHigh : 20;
3123	/** MBZ bits */
3124	uint32_t u11Reserved : 11;
3125	/** No Execute flag. */
3126	uint32_t u1NoExecute : 1;
3127	} X86PML4EBITS;
3128	#ifndef VBOX_FOR_DTRACE_LIB
3129	AssertCompileSize(X86PML4EBITS, 8);
3130	#endif
3131	/** Pointer to a page map level-4 entry. */
3132	typedef X86PML4EBITS *PX86PML4EBITS;
3133	/** Pointer to a const page map level-4 entry. */
3134	typedef const X86PML4EBITS *PCX86PML4EBITS;
3135
3136	/**
3137	* Page Map Level-4 Entry.
3138	*/
3139	typedef union X86PML4E
3140	{
3141	/** Unsigned integer view. */
3142	X86PGPAEUINT u;
3143	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3144	/** Normal view. */
3145	X86PML4EBITS n;
3146	#endif
3147	/** 8 bit unsigned integer view. */
3148	uint8_t au8[8];
3149	/** 16 bit unsigned integer view. */
3150	uint16_t au16[4];
3151	/** 32 bit unsigned integer view. */
3152	uint32_t au32[2];
3153	} X86PML4E;
3154	#ifndef VBOX_FOR_DTRACE_LIB
3155	AssertCompileSize(X86PML4E, 8);
3156	#endif
3157	/** Pointer to a page map level-4 entry. */
3158	typedef X86PML4E *PX86PML4E;
3159	/** Pointer to a const page map level-4 entry. */
3160	typedef const X86PML4E *PCX86PML4E;
3161
3162
3163	/**
3164	* Page Map Level-4.
3165	*/
3166	typedef struct X86PML4
3167	{
3168	/** PDE Array. */
3169	X86PML4E a[X86_PG_PAE_ENTRIES];
3170	} X86PML4;
3171	#ifndef VBOX_FOR_DTRACE_LIB
3172	AssertCompileSize(X86PML4, 4096);
3173	#endif
3174	/** Pointer to a page map level-4. */
3175	typedef X86PML4 *PX86PML4;
3176	/** Pointer to a const page map level-4. */
3177	typedef const X86PML4 *PCX86PML4;
3178
3179	/** The page shift to get the PML4 index. */
3180	#define X86_PML4_SHIFT 39
3181	/** The PML4 index mask (apply to a shifted page address). */
3182	#define X86_PML4_MASK 0x1ff
3183
3184	/** @} */
3185
3186	/** @} */
3187
3188	/**
3189	* Intel PCID invalidation types.
3190	*/
3191	/** Individual address invalidation. */
3192	#define X86_INVPCID_TYPE_INDV_ADDR 0
3193	/** Single-context invalidation. */
3194	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3195	/** All-context including globals invalidation. */
3196	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3197	/** All-context excluding globals invalidation. */
3198	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3199	/** The maximum valid invalidation type value. */
3200	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3201
3202
3203	/** @name Special FPU integer values.
3204	* @{ */
3205	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3206	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3207	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3208	/** @} */
3209
3210	/**
3211	* 32-bit protected mode FSTENV image.
3212	*/
3213	typedef struct X86FSTENV32P
3214	{
3215	uint16_t FCW; /*< 0x00 /
3216	uint16_t padding1; /*< 0x02 /
3217	uint16_t FSW; /*< 0x04 /
3218	uint16_t padding2; /*< 0x06 /
3219	uint16_t FTW; /*< 0x08 /
3220	uint16_t padding3; /*< 0x0a /
3221	uint32_t FPUIP; /*< 0x0c /
3222	uint16_t FPUCS; /*< 0x10 /
3223	uint16_t FOP; /*< 0x12 /
3224	uint32_t FPUDP; /*< 0x14 /
3225	uint16_t FPUDS; /*< 0x18 /
3226	uint16_t padding4; /*< 0x1a /
3227	} X86FSTENV32P;
3228	#ifndef VBOX_FOR_DTRACE_LIB
3229	AssertCompileSize(X86FSTENV32P, 0x1c);
3230	#endif
3231	/** Pointer to a 32-bit protected mode FSTENV image. */
3232	typedef X86FSTENV32P *PX86FSTENV32P;
3233	/** Pointer to a const 32-bit protected mode FSTENV image. */
3234	typedef X86FSTENV32P const *PCX86FSTENV32P;
3235
3236
3237	/**
3238	* 80-bit MMX/FPU register type.
3239	*/
3240	typedef struct X86FPUMMX
3241	{
3242	uint8_t reg[10];
3243	} X86FPUMMX;
3244	#ifndef VBOX_FOR_DTRACE_LIB
3245	AssertCompileSize(X86FPUMMX, 10);
3246	#endif
3247	/** Pointer to a 80-bit MMX/FPU register type. */
3248	typedef X86FPUMMX *PX86FPUMMX;
3249	/** Pointer to a const 80-bit MMX/FPU register type. */
3250	typedef const X86FPUMMX *PCX86FPUMMX;
3251
3252	/** FPU (x87) register. */
3253	typedef union X86FPUREG
3254	{
3255	/** MMX view. */
3256	uint64_t mmx;
3257	/** FPU view - todo. */
3258	X86FPUMMX fpu;
3259	/** Extended precision floating point view. */
3260	RTFLOAT80U r80;
3261	/** Extended precision floating point view v2 */
3262	RTFLOAT80U2 r80Ex;
3263	/** 8-bit view. */
3264	uint8_t au8[16];
3265	/** 16-bit view. */
3266	uint16_t au16[8];
3267	/** 32-bit view. */
3268	uint32_t au32[4];
3269	/** 64-bit view. */
3270	uint64_t au64[2];
3271	/** 128-bit view. (yeah, very helpful) */
3272	uint128_t au128[1];
3273	} X86FPUREG;
3274	#ifndef VBOX_FOR_DTRACE_LIB
3275	AssertCompileSize(X86FPUREG, 16);
3276	#endif
3277	/** Pointer to a FPU register. */
3278	typedef X86FPUREG *PX86FPUREG;
3279	/** Pointer to a const FPU register. */
3280	typedef X86FPUREG const *PCX86FPUREG;
3281
3282	/** FPU (x87) register - v2 with correct size. */
3283	#pragma pack(1)
3284	typedef union X86FPUREG2
3285	{
3286	/** MMX view. */
3287	uint64_t mmx;
3288	/** FPU view - todo. */
3289	X86FPUMMX fpu;
3290	/** Extended precision floating point view. */
3291	RTFLOAT80U r80;
3292	/** 8-bit view. */
3293	uint8_t au8[10];
3294	/** 16-bit view. */
3295	uint16_t au16[5];
3296	/** 32-bit view. */
3297	uint32_t au32[2];
3298	/** 64-bit view. */
3299	uint64_t au64[1];
3300	} X86FPUREG2;
3301	#pragma pack()
3302	#ifndef VBOX_FOR_DTRACE_LIB
3303	AssertCompileSize(X86FPUREG2, 10);
3304	#endif
3305	/** Pointer to a FPU register - v2. */
3306	typedef X86FPUREG2 *PX86FPUREG2;
3307	/** Pointer to a const FPU register - v2. */
3308	typedef X86FPUREG2 const *PCX86FPUREG2;
3309
3310	/**
3311	* XMM register union.
3312	*/
3313	typedef union X86XMMREG
3314	{
3315	/** XMM Register view. */
3316	uint128_t xmm;
3317	/** 8-bit view. */
3318	uint8_t au8[16];
3319	/** 16-bit view. */
3320	uint16_t au16[8];
3321	/** 32-bit view. */
3322	uint32_t au32[4];
3323	/** 64-bit view. */
3324	uint64_t au64[2];
3325	/** Signed 8-bit view. */
3326	int8_t ai8[16];
3327	/** Signed 16-bit view. */
3328	int16_t ai16[8];
3329	/** Signed 32-bit view. */
3330	int32_t ai32[4];
3331	/** Signed 64-bit view. */
3332	int64_t ai64[2];
3333	/** 128-bit view. (yeah, very helpful) */
3334	uint128_t au128[1];
3335	/** Single precision floating point view. */
3336	RTFLOAT32U ar32[4];
3337	/** Double precision floating point view. */
3338	RTFLOAT64U ar64[2];
3339	#ifndef VBOX_FOR_DTRACE_LIB
3340	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3341	RTUINT128U uXmm;
3342	#endif
3343	} X86XMMREG;
3344	#ifndef VBOX_FOR_DTRACE_LIB
3345	AssertCompileSize(X86XMMREG, 16);
3346	#endif
3347	/** Pointer to an XMM register state. */
3348	typedef X86XMMREG *PX86XMMREG;
3349	/** Pointer to a const XMM register state. */
3350	typedef X86XMMREG const *PCX86XMMREG;
3351
3352	/**
3353	* YMM register union.
3354	*/
3355	typedef union X86YMMREG
3356	{
3357	/** YMM register view. */
3358	RTUINT256U ymm;
3359	/** 8-bit view. */
3360	uint8_t au8[32];
3361	/** 16-bit view. */
3362	uint16_t au16[16];
3363	/** 32-bit view. */
3364	uint32_t au32[8];
3365	/** 64-bit view. */
3366	uint64_t au64[4];
3367	/** 128-bit view. (yeah, very helpful) */
3368	uint128_t au128[2];
3369	/** Single precision floating point view. */
3370	RTFLOAT32U ar32[8];
3371	/** Double precision floating point view. */
3372	RTFLOAT64U ar64[4];
3373	/** XMM sub register view. */
3374	X86XMMREG aXmm[2];
3375	} X86YMMREG;
3376	#ifndef VBOX_FOR_DTRACE_LIB
3377	AssertCompileSize(X86YMMREG, 32);
3378	#endif
3379	/** Pointer to an YMM register state. */
3380	typedef X86YMMREG *PX86YMMREG;
3381	/** Pointer to a const YMM register state. */
3382	typedef X86YMMREG const *PCX86YMMREG;
3383
3384	/**
3385	* ZMM register union.
3386	*/
3387	typedef union X86ZMMREG
3388	{
3389	/** 8-bit view. */
3390	uint8_t au8[64];
3391	/** 16-bit view. */
3392	uint16_t au16[32];
3393	/** 32-bit view. */
3394	uint32_t au32[16];
3395	/** 64-bit view. */
3396	uint64_t au64[8];
3397	/** 128-bit view. (yeah, very helpful) */
3398	uint128_t au128[4];
3399	/** Single precision floating point view. */
3400	RTFLOAT32U ar32[16];
3401	/** Double precision floating point view. */
3402	RTFLOAT64U ar64[8];
3403	/** XMM sub register view. */
3404	X86XMMREG aXmm[4];
3405	/** YMM sub register view. */
3406	X86YMMREG aYmm[2];
3407	} X86ZMMREG;
3408	#ifndef VBOX_FOR_DTRACE_LIB
3409	AssertCompileSize(X86ZMMREG, 64);
3410	#endif
3411	/** Pointer to an ZMM register state. */
3412	typedef X86ZMMREG *PX86ZMMREG;
3413	/** Pointer to a const ZMM register state. */
3414	typedef X86ZMMREG const *PCX86ZMMREG;
3415
3416
3417	/**
3418	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3419	*/
3420	#pragma pack(1)
3421	typedef struct X86FPUSTATE
3422	{
3423	/** 0x00 - Control word. */
3424	uint16_t FCW;
3425	/** 0x02 - Alignment word */
3426	uint16_t Dummy1;
3427	/** 0x04 - Status word. */
3428	uint16_t FSW;
3429	/** 0x06 - Alignment word */
3430	uint16_t Dummy2;
3431	/** 0x08 - Tag word */
3432	uint16_t FTW;
3433	/** 0x0a - Alignment word */
3434	uint16_t Dummy3;
3435
3436	/** 0x0c - Instruction pointer. */
3437	uint32_t FPUIP;
3438	/** 0x10 - Code selector. */
3439	uint16_t CS;
3440	/** 0x12 - Opcode. */
3441	uint16_t FOP;
3442	/** 0x14 - Data pointer. */
3443	uint32_t FPUOO;
3444	/** 0x18 - FOS. */
3445	uint16_t FPUOS;
3446	/** 0x0a - Alignment word */
3447	uint16_t Dummy4;
3448	/** 0x1c - FPU register. */
3449	X86FPUREG2 regs[8];
3450	} X86FPUSTATE;
3451	#pragma pack()
3452	AssertCompileSize(X86FPUSTATE, 108);
3453	/** Pointer to a FPU state. */
3454	typedef X86FPUSTATE *PX86FPUSTATE;
3455	/** Pointer to a const FPU state. */
3456	typedef const X86FPUSTATE *PCX86FPUSTATE;
3457
3458	/**
3459	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3460	*/
3461	#pragma pack(1)
3462	typedef struct X86FXSTATE
3463	{
3464	/** 0x00 - Control word. */
3465	uint16_t FCW;
3466	/** 0x02 - Status word. */
3467	uint16_t FSW;
3468	/** 0x04 - Tag word. (The upper byte is always zero.) */
3469	uint16_t FTW;
3470	/** 0x06 - Opcode. */
3471	uint16_t FOP;
3472	/** 0x08 - Instruction pointer. */
3473	uint32_t FPUIP;
3474	/** 0x0c - Code selector. */
3475	uint16_t CS;
3476	uint16_t Rsrvd1;
3477	/** 0x10 - Data pointer. */
3478	uint32_t FPUDP;
3479	/** 0x14 - Data segment */
3480	uint16_t DS;
3481	/** 0x16 */
3482	uint16_t Rsrvd2;
3483	/** 0x18 */
3484	uint32_t MXCSR;
3485	/** 0x1c */
3486	uint32_t MXCSR_MASK;
3487	/** 0x20 - FPU registers. */
3488	X86FPUREG aRegs[8];
3489	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3490	X86XMMREG aXMM[16];
3491	/* - offset 416 - */
3492	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3493	/* - offset 464 - Software usable reserved bits. */
3494	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3495	} X86FXSTATE;
3496	#pragma pack()
3497	/** Pointer to a FPU Extended state. */
3498	typedef X86FXSTATE *PX86FXSTATE;
3499	/** Pointer to a const FPU Extended state. */
3500	typedef const X86FXSTATE *PCX86FXSTATE;
3501
3502	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3503	* magic. Don't forget to update x86.mac if you change this! */
3504	#define X86_OFF_FXSTATE_RSVD 0x1d0
3505	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3506	* forget to update x86.mac if you change this!
3507	* @todo r=bird: This has nothing what-so-ever to do here.... */
3508	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3509	#ifndef VBOX_FOR_DTRACE_LIB
3510	AssertCompileSize(X86FXSTATE, 512);
3511	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3512	#endif
3513
3514	/** @name FPU status word flags.
3515	* @{ */
3516	/** Exception Flag: Invalid operation. */
3517	#define X86_FSW_IE RT_BIT_32(0)
3518	#define X86_FSW_IE_BIT 0
3519	/** Exception Flag: Denormalized operand. */
3520	#define X86_FSW_DE RT_BIT_32(1)
3521	#define X86_FSW_DE_BIT 1
3522	/** Exception Flag: Zero divide. */
3523	#define X86_FSW_ZE RT_BIT_32(2)
3524	#define X86_FSW_ZE_BIT 2
3525	/** Exception Flag: Overflow. */
3526	#define X86_FSW_OE RT_BIT_32(3)
3527	#define X86_FSW_OE_BIT 3
3528	/** Exception Flag: Underflow. */
3529	#define X86_FSW_UE RT_BIT_32(4)
3530	#define X86_FSW_UE_BIT 4
3531	/** Exception Flag: Precision. */
3532	#define X86_FSW_PE RT_BIT_32(5)
3533	#define X86_FSW_PE_BIT 5
3534	/** Stack fault. */
3535	#define X86_FSW_SF RT_BIT_32(6)
3536	#define X86_FSW_SF_BIT 6
3537	/** Error summary status. */
3538	#define X86_FSW_ES RT_BIT_32(7)
3539	#define X86_FSW_ES_BIT 7
3540	/** Mask of exceptions flags, excluding the summary bit. */
3541	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3542	/** Mask of exceptions flags, including the summary bit. */
3543	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3544	/** Condition code 0. */
3545	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3546	#define X86_FSW_C0_BIT 8
3547	/** Condition code 1. */
3548	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3549	#define X86_FSW_C1_BIT 9
3550	/** Condition code 2. */
3551	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3552	#define X86_FSW_C2_BIT 10
3553	/** Top of the stack mask. */
3554	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3555	/** TOP shift value. */
3556	#define X86_FSW_TOP_SHIFT 11
3557	/** Mask for getting TOP value after shifting it right. */
3558	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3559	/** Get the TOP value. */
3560	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3561	/** Get the TOP value offsetted by a_iSt (0-7). */
3562	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3563	/** Condition code 3. */
3564	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3565	#define X86_FSW_C3_BIT 14
3566	/** Mask of exceptions flags, including the summary bit. */
3567	#define X86_FSW_C_MASK UINT16_C(0x4700)
3568	/** FPU busy. */
3569	#define X86_FSW_B RT_BIT_32(15)
3570	/** For use with FPREM and FPREM1. */
3571	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3572	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3573	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3574	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3575	/** For use with FPREM and FPREM1. */
3576	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3577	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3578	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3579	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3580	/** @} */
3581
3582
3583	/** @name FPU control word flags.
3584	* @{ */
3585	/** Exception Mask: Invalid operation. */
3586	#define X86_FCW_IM RT_BIT_32(0)
3587	#define X86_FCW_IM_BIT 0
3588	/** Exception Mask: Denormalized operand. */
3589	#define X86_FCW_DM RT_BIT_32(1)
3590	#define X86_FCW_DM_BIT 1
3591	/** Exception Mask: Zero divide. */
3592	#define X86_FCW_ZM RT_BIT_32(2)
3593	#define X86_FCW_ZM_BIT 2
3594	/** Exception Mask: Overflow. */
3595	#define X86_FCW_OM RT_BIT_32(3)
3596	#define X86_FCW_OM_BIT 3
3597	/** Exception Mask: Underflow. */
3598	#define X86_FCW_UM RT_BIT_32(4)
3599	#define X86_FCW_UM_BIT 4
3600	/** Exception Mask: Precision. */
3601	#define X86_FCW_PM RT_BIT_32(5)
3602	#define X86_FCW_PM_BIT 5
3603	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3604	* @remarks This includes reserved bit 6. */
3605	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3606	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3607	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3608	/** Precision control mask. */
3609	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3610	/** Precision control shift. */
3611	#define X86_FCW_PC_SHIFT 8
3612	/** Precision control: 24-bit. */
3613	#define X86_FCW_PC_24 UINT16_C(0x0000)
3614	/** Precision control: Reserved. */
3615	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3616	/** Precision control: 53-bit. */
3617	#define X86_FCW_PC_53 UINT16_C(0x0200)
3618	/** Precision control: 64-bit. */
3619	#define X86_FCW_PC_64 UINT16_C(0x0300)
3620	/** Rounding control mask. */
3621	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3622	/** Rounding control shift. */
3623	#define X86_FCW_RC_SHIFT 10
3624	/** Rounding control: To nearest. */
3625	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3626	/** Rounding control: Down. */
3627	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3628	/** Rounding control: Up. */
3629	#define X86_FCW_RC_UP UINT16_C(0x0800)
3630	/** Rounding control: Towards zero. */
3631	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3632	/** Infinity control mask - obsolete, 8087 & 287 only. */
3633	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3634	/** Infinity control: Affine - positive infinity is distictly different from
3635	* negative infinity.
3636	* @note 8087, 287 only */
3637	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3638	/** Infinity control: Projective - positive and negative infinity are the
3639	* same (sign ignored).
3640	* @note 8087, 287 only */
3641	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3642	/** Bits which should be zero, apparently. */
3643	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3644	/** @} */
3645
3646	/** @name SSE MXCSR
3647	* @{ */
3648	/** Exception Flag: Invalid operation. */
3649	#define X86_MXCSR_IE RT_BIT_32(0)
3650	/** Exception Flag: Denormalized operand. */
3651	#define X86_MXCSR_DE RT_BIT_32(1)
3652	/** Exception Flag: Zero divide. */
3653	#define X86_MXCSR_ZE RT_BIT_32(2)
3654	/** Exception Flag: Overflow. */
3655	#define X86_MXCSR_OE RT_BIT_32(3)
3656	/** Exception Flag: Underflow. */
3657	#define X86_MXCSR_UE RT_BIT_32(4)
3658	/** Exception Flag: Precision. */
3659	#define X86_MXCSR_PE RT_BIT_32(5)
3660	/** Exception Flags: mask */
3661	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3662
3663	/** Denormals are zero. */
3664	#define X86_MXCSR_DAZ RT_BIT_32(6)
3665
3666	/** Exception Mask: Invalid operation. */
3667	#define X86_MXCSR_IM RT_BIT_32(7)
3668	/** Exception Mask: Denormalized operand. */
3669	#define X86_MXCSR_DM RT_BIT_32(8)
3670	/** Exception Mask: Zero divide. */
3671	#define X86_MXCSR_ZM RT_BIT_32(9)
3672	/** Exception Mask: Overflow. */
3673	#define X86_MXCSR_OM RT_BIT_32(10)
3674	/** Exception Mask: Underflow. */
3675	#define X86_MXCSR_UM RT_BIT_32(11)
3676	/** Exception Mask: Precision. */
3677	#define X86_MXCSR_PM RT_BIT_32(12)
3678	/** Exception Mask: mask. */
3679	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3680	/** Exception Mask: shift. */
3681	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3682
3683	/** Rounding control mask. */
3684	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3685	/** Rounding control shift. */
3686	#define X86_MXCSR_RC_SHIFT 13
3687	/** Rounding control: To nearest. */
3688	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3689	/** Rounding control: Down. */
3690	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3691	/** Rounding control: Up. */
3692	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3693	/** Rounding control: Towards zero. */
3694	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3695
3696	/** Flush-to-zero for masked underflow. */
3697	#define X86_MXCSR_FZ RT_BIT_32(15)
3698
3699	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3700	#define X86_MXCSR_MM RT_BIT_32(17)
3701	/** Bits which should be zero, apparently. */
3702	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3703	/** @} */
3704
3705	/**
3706	* XSAVE header.
3707	*/
3708	typedef struct X86XSAVEHDR
3709	{
3710	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3711	uint64_t bmXState;
3712	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3713	uint64_t bmXComp;
3714	/** Reserved for furture extensions, probably MBZ. */
3715	uint64_t au64Reserved[6];
3716	} X86XSAVEHDR;
3717	#ifndef VBOX_FOR_DTRACE_LIB
3718	AssertCompileSize(X86XSAVEHDR, 64);
3719	#endif
3720	/** Pointer to an XSAVE header. */
3721	typedef X86XSAVEHDR *PX86XSAVEHDR;
3722	/** Pointer to a const XSAVE header. */
3723	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3724
3725
3726	/**
3727	* The high 128-bit YMM register state (XSAVE_C_YMM).
3728	* (The lower 128-bits being in X86FXSTATE.)
3729	*/
3730	typedef struct X86XSAVEYMMHI
3731	{
3732	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3733	X86XMMREG aYmmHi[16];
3734	} X86XSAVEYMMHI;
3735	#ifndef VBOX_FOR_DTRACE_LIB
3736	AssertCompileSize(X86XSAVEYMMHI, 256);
3737	#endif
3738	/** Pointer to a high 128-bit YMM register state. */
3739	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3740	/** Pointer to a const high 128-bit YMM register state. */
3741	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3742
3743	/**
3744	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3745	*/
3746	typedef struct X86XSAVEBNDREGS
3747	{
3748	/** Array of registers (BND0...BND3). */
3749	struct
3750	{
3751	/** Lower bound. */
3752	uint64_t uLowerBound;
3753	/** Upper bound. */
3754	uint64_t uUpperBound;
3755	} aRegs[4];
3756	} X86XSAVEBNDREGS;
3757	#ifndef VBOX_FOR_DTRACE_LIB
3758	AssertCompileSize(X86XSAVEBNDREGS, 64);
3759	#endif
3760	/** Pointer to a MPX bound register state. */
3761	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3762	/** Pointer to a const MPX bound register state. */
3763	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3764
3765	/**
3766	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3767	*/
3768	typedef struct X86XSAVEBNDCFG
3769	{
3770	uint64_t fConfig;
3771	uint64_t fStatus;
3772	} X86XSAVEBNDCFG;
3773	#ifndef VBOX_FOR_DTRACE_LIB
3774	AssertCompileSize(X86XSAVEBNDCFG, 16);
3775	#endif
3776	/** Pointer to a MPX bound config and status register state. */
3777	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3778	/** Pointer to a const MPX bound config and status register state. */
3779	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3780
3781	/**
3782	* AVX-512 opmask state (XSAVE_C_OPMASK).
3783	*/
3784	typedef struct X86XSAVEOPMASK
3785	{
3786	/** The K0..K7 values. */
3787	uint64_t aKRegs[8];
3788	} X86XSAVEOPMASK;
3789	#ifndef VBOX_FOR_DTRACE_LIB
3790	AssertCompileSize(X86XSAVEOPMASK, 64);
3791	#endif
3792	/** Pointer to a AVX-512 opmask state. */
3793	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3794	/** Pointer to a const AVX-512 opmask state. */
3795	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3796
3797	/**
3798	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3799	*/
3800	typedef struct X86XSAVEZMMHI256
3801	{
3802	/** Upper 256-bits of ZMM0-15. */
3803	X86YMMREG aHi256Regs[16];
3804	} X86XSAVEZMMHI256;
3805	#ifndef VBOX_FOR_DTRACE_LIB
3806	AssertCompileSize(X86XSAVEZMMHI256, 512);
3807	#endif
3808	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3809	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3810	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3811	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3812
3813	/**
3814	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3815	*/
3816	typedef struct X86XSAVEZMM16HI
3817	{
3818	/** ZMM16 thru ZMM31. */
3819	X86ZMMREG aRegs[16];
3820	} X86XSAVEZMM16HI;
3821	#ifndef VBOX_FOR_DTRACE_LIB
3822	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3823	#endif
3824	/** Pointer to a state comprising ZMM16-32. */
3825	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3826	/** Pointer to a const state comprising ZMM16-32. */
3827	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3828
3829	/**
3830	* AMD Light weight profiling state (XSAVE_C_LWP).
3831	*
3832	* We probably won't play with this as AMD seems to be dropping from their "zen"
3833	* processor micro architecture.
3834	*/
3835	typedef struct X86XSAVELWP
3836	{
3837	/** Details when needed. */
3838	uint64_t auLater[128/8];
3839	} X86XSAVELWP;
3840	#ifndef VBOX_FOR_DTRACE_LIB
3841	AssertCompileSize(X86XSAVELWP, 128);
3842	#endif
3843
3844
3845	/**
3846	* x86 FPU/SSE/AVX/XXXX state.
3847	*
3848	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3849	* changes to this structure.
3850	*/
3851	typedef struct X86XSAVEAREA
3852	{
3853	/** The x87 and SSE region (or legacy region if you like). */
3854	X86FXSTATE x87;
3855	/** The XSAVE header. */
3856	X86XSAVEHDR Hdr;
3857	/** Beyond the header, there isn't really a fixed layout, but we can
3858	generally assume the YMM (AVX) register extensions are present and
3859	follows immediately. */
3860	union
3861	{
3862	/** The high 128-bit AVX registers for easy access by IEM.
3863	* @note This ASSUMES they will always be here... */
3864	X86XSAVEYMMHI YmmHi;
3865
3866	/** This is a typical layout on intel CPUs (good for debuggers). */
3867	struct
3868	{
3869	X86XSAVEYMMHI YmmHi;
3870	X86XSAVEBNDREGS BndRegs;
3871	X86XSAVEBNDCFG BndCfg;
3872	uint8_t abFudgeToMatchDocs[0xB0];
3873	X86XSAVEOPMASK Opmask;
3874	X86XSAVEZMMHI256 ZmmHi256;
3875	X86XSAVEZMM16HI Zmm16Hi;
3876	} Intel;
3877
3878	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3879	struct
3880	{
3881	X86XSAVEYMMHI YmmHi;
3882	X86XSAVELWP Lwp;
3883	} AmdBd;
3884
3885	/** To enbling static deployments that have a reasonable chance of working for
3886	* the next 3-6 CPU generations without running short on space, we allocate a
3887	* lot of extra space here, making the structure a round 8KB in size. This
3888	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3889	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3890	uint8_t ab[8192 - 512 - 64];
3891	} u;
3892	} X86XSAVEAREA;
3893	#ifndef VBOX_FOR_DTRACE_LIB
3894	AssertCompileSize(X86XSAVEAREA, 8192);
3895	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3896	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3897	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3898	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3899	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3900	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3901	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3902	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3903	#endif
3904	/** Pointer to a XSAVE area. */
3905	typedef X86XSAVEAREA *PX86XSAVEAREA;
3906	/** Pointer to a const XSAVE area. */
3907	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3908
3909
3910	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3911	* @{ */
3912	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3913	#define XSAVE_C_X87_BIT 0
3914	/** Bit 0 - x87 - Legacy FPU state. */
3915	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3916	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3917	#define XSAVE_C_SSE_BIT 1
3918	/** Bit 1 - SSE - 128-bit SSE state. */
3919	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3920	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3921	#define XSAVE_C_YMM_BIT 2
3922	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3923	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3924	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3925	#define XSAVE_C_BNDREGS_BIT 3
3926	/** Bit 3 - BNDREGS - MPX bound register state. */
3927	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3928	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3929	#define XSAVE_C_BNDCSR_BIT 4
3930	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3931	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3932	/** Bit 5 - Opmask - opmask state (bit number). */
3933	#define XSAVE_C_OPMASK_BIT 5
3934	/** Bit 5 - Opmask - opmask state. */
3935	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3936	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3937	#define XSAVE_C_ZMM_HI256_BIT 6
3938	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3939	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3940	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3941	#define XSAVE_C_ZMM_16HI_BIT 7
3942	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3943	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3944	/** Bit 9 - PKRU - Protection-key state (bit number). */
3945	#define XSAVE_C_PKRU_BIT 9
3946	/** Bit 9 - PKRU - Protection-key state. */
3947	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3948	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3949	#define XSAVE_C_LWP_BIT 62
3950	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3951	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3952	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3953	#define XSAVE_C_X_BIT 63
3954	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3955	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3956	/** @} */
3957
3958
3959
3960	/** @name Selector Descriptor
3961	* @{
3962	*/
3963
3964	#ifndef VBOX_FOR_DTRACE_LIB
3965	/**
3966	* Descriptor attributes (as seen by VT-x).
3967	*/
3968	typedef struct X86DESCATTRBITS
3969	{
3970	/** 00 - Segment Type. */
3971	unsigned u4Type : 4;
3972	/** 04 - Descriptor Type. System(=0) or code/data selector */
3973	unsigned u1DescType : 1;
3974	/** 05 - Descriptor Privilege level. */
3975	unsigned u2Dpl : 2;
3976	/** 07 - Flags selector present(=1) or not. */
3977	unsigned u1Present : 1;
3978	/** 08 - Segment limit 16-19. */
3979	unsigned u4LimitHigh : 4;
3980	/** 0c - Available for system software. */
3981	unsigned u1Available : 1;
3982	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3983	unsigned u1Long : 1;
3984	/** 0e - This flags meaning depends on the segment type. Try make sense out
3985	* of the intel manual yourself. */
3986	unsigned u1DefBig : 1;
3987	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3988	* clear byte. */
3989	unsigned u1Granularity : 1;
3990	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3991	unsigned u1Unusable : 1;
3992	} X86DESCATTRBITS;
3993	#endif /* !VBOX_FOR_DTRACE_LIB */
3994
3995	/** @name X86DESCATTR masks
3996	* Fields X86DESCGENERIC::u4Type thru X86DESCGENERIC::u1Granularity (or
3997	* bits[55:40] if you like). The X86DESCATTR_UNUSABLE bit is an Intel addition.
3998	* @{ */
3999	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
4000	#define X86DESCATTR_DT UINT32_C(0x00000010) /*< Descriptor type: 0=system, 1=code/data /
4001	#define X86DESCATTR_DPL UINT32_C(0x00000060)
4002	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL bitfield. /
4003	#define X86DESCATTR_P UINT32_C(0x00000080)
4004	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4005	#define X86DESCATTR_AVL UINT32_C(0x00001000)
4006	#define X86DESCATTR_L UINT32_C(0x00002000)
4007	#define X86DESCATTR_D UINT32_C(0x00004000)
4008	#define X86DESCATTR_G UINT32_C(0x00008000)
4009	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4010	/** @} */
4011
4012	#pragma pack(1)
4013	typedef union X86DESCATTR
4014	{
4015	/** Unsigned integer view. */
4016	uint32_t u;
4017	#ifndef VBOX_FOR_DTRACE_LIB
4018	/** Normal view. */
4019	X86DESCATTRBITS n;
4020	#endif
4021	} X86DESCATTR;
4022	#pragma pack()
4023	/** Pointer to descriptor attributes. */
4024	typedef X86DESCATTR *PX86DESCATTR;
4025	/** Pointer to const descriptor attributes. */
4026	typedef const X86DESCATTR *PCX86DESCATTR;
4027
4028	#ifndef VBOX_FOR_DTRACE_LIB
4029
4030	/**
4031	* Generic descriptor table entry
4032	*/
4033	#pragma pack(1)
4034	typedef struct X86DESCGENERIC
4035	{
4036	/** 00 - Limit - Low word. */
4037	unsigned u16LimitLow : 16;
4038	/** 10 - Base address - low word.
4039	* Don't try set this to 24 because MSC is doing stupid things then. */
4040	unsigned u16BaseLow : 16;
4041	/** 20 - Base address - first 8 bits of high word. */
4042	unsigned u8BaseHigh1 : 8;
4043	/** 28 - Segment Type. */
4044	unsigned u4Type : 4;
4045	/** 2c - Descriptor Type. System(=0) or code/data selector */
4046	unsigned u1DescType : 1;
4047	/** 2d - Descriptor Privilege level. */
4048	unsigned u2Dpl : 2;
4049	/** 2f - Flags selector present(=1) or not. */
4050	unsigned u1Present : 1;
4051	/** 30 - Segment limit 16-19. */
4052	unsigned u4LimitHigh : 4;
4053	/** 34 - Available for system software. */
4054	unsigned u1Available : 1;
4055	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4056	unsigned u1Long : 1;
4057	/** 36 - This flags meaning depends on the segment type. Try make sense out
4058	* of the intel manual yourself. */
4059	unsigned u1DefBig : 1;
4060	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4061	* clear byte. */
4062	unsigned u1Granularity : 1;
4063	/** 38 - Base address - highest 8 bits. */
4064	unsigned u8BaseHigh2 : 8;
4065	} X86DESCGENERIC;
4066	#pragma pack()
4067	/** Pointer to a generic descriptor entry. */
4068	typedef X86DESCGENERIC *PX86DESCGENERIC;
4069	/** Pointer to a const generic descriptor entry. */
4070	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4071
4072	/** @name Bit offsets of X86DESCGENERIC members.
4073	* @{*/
4074	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4075	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4076	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4077	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4078	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4079	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4080	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4081	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4082	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4083	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4084	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4085	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4086	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4087	/** @} */
4088
4089
4090	/** @name LAR mask
4091	* @{ */
4092	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
4093	#define X86LAR_F_DT UINT16_C( 0x1000)
4094	#define X86LAR_F_DPL UINT16_C( 0x6000)
4095	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4096	#define X86LAR_F_P UINT16_C( 0x8000)
4097	#define X86LAR_F_AVL UINT32_C(0x00100000)
4098	#define X86LAR_F_L UINT32_C(0x00200000)
4099	#define X86LAR_F_D UINT32_C(0x00400000)
4100	#define X86LAR_F_G UINT32_C(0x00800000)
4101	/** @} */
4102
4103
4104	/**
4105	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4106	*/
4107	typedef struct X86DESCGATE
4108	{
4109	/** 00 - Target code segment offset - Low word.
4110	* Ignored if task-gate. */
4111	unsigned u16OffsetLow : 16;
4112	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4113	* TSS selector if task-gate. */
4114	unsigned u16Sel : 16;
4115	/** 20 - Number of parameters for a call-gate.
4116	* Ignored if interrupt-, trap- or task-gate. */
4117	unsigned u5ParmCount : 5;
4118	/** 25 - Reserved / ignored. */
4119	unsigned u3Reserved : 3;
4120	/** 28 - Segment Type. */
4121	unsigned u4Type : 4;
4122	/** 2c - Descriptor Type (0 = system). */
4123	unsigned u1DescType : 1;
4124	/** 2d - Descriptor Privilege level. */
4125	unsigned u2Dpl : 2;
4126	/** 2f - Flags selector present(=1) or not. */
4127	unsigned u1Present : 1;
4128	/** 30 - Target code segment offset - High word.
4129	* Ignored if task-gate. */
4130	unsigned u16OffsetHigh : 16;
4131	} X86DESCGATE;
4132	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4133	typedef X86DESCGATE *PX86DESCGATE;
4134	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4135	typedef const X86DESCGATE *PCX86DESCGATE;
4136
4137	#endif /* VBOX_FOR_DTRACE_LIB */
4138
4139	/**
4140	* Descriptor table entry.
4141	*/
4142	#pragma pack(1)
4143	typedef union X86DESC
4144	{
4145	#ifndef VBOX_FOR_DTRACE_LIB
4146	/** Generic descriptor view. */
4147	X86DESCGENERIC Gen;
4148	/** Gate descriptor view. */
4149	X86DESCGATE Gate;
4150	#endif
4151
4152	/** 8 bit unsigned integer view. */
4153	uint8_t au8[8];
4154	/** 16 bit unsigned integer view. */
4155	uint16_t au16[4];
4156	/** 32 bit unsigned integer view. */
4157	uint32_t au32[2];
4158	/** 64 bit unsigned integer view. */
4159	uint64_t au64[1];
4160	/** Unsigned integer view. */
4161	uint64_t u;
4162	} X86DESC;
4163	#ifndef VBOX_FOR_DTRACE_LIB
4164	AssertCompileSize(X86DESC, 8);
4165	#endif
4166	#pragma pack()
4167	/** Pointer to descriptor table entry. */
4168	typedef X86DESC *PX86DESC;
4169	/** Pointer to const descriptor table entry. */
4170	typedef const X86DESC *PCX86DESC;
4171
4172	/** @def X86DESC_BASE
4173	* Return the base address of a descriptor.
4174	*/
4175	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4176	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4177	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4178	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4179
4180	/** @def X86DESC_LIMIT
4181	* Return the limit of a descriptor.
4182	*/
4183	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4184	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4185	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4186
4187	/** @def X86DESC_LIMIT_G
4188	* Return the limit of a descriptor with the granularity bit taken into account.
4189	* @returns Selector limit (uint32_t).
4190	* @param a_pDesc Pointer to the descriptor.
4191	*/
4192	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4193	( (a_pDesc)->Gen.u1Granularity \
4194	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4195	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4196	)
4197
4198	/** @def X86DESC_GET_HID_ATTR
4199	* Get the descriptor attributes for the hidden register.
4200	*/
4201	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4202	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4203
4204	#ifndef VBOX_FOR_DTRACE_LIB
4205
4206	/**
4207	* 64 bits generic descriptor table entry
4208	* Note: most of these bits have no meaning in long mode.
4209	*/
4210	#pragma pack(1)
4211	typedef struct X86DESC64GENERIC
4212	{
4213	/** Limit - Low word - IGNORED. */
4214	uint32_t u16LimitLow : 16;
4215	/** Base address - low word. - IGNORED
4216	* Don't try set this to 24 because MSC is doing stupid things then. */
4217	uint32_t u16BaseLow : 16;
4218	/** Base address - first 8 bits of high word. - IGNORED */
4219	uint32_t u8BaseHigh1 : 8;
4220	/** Segment Type. */
4221	uint32_t u4Type : 4;
4222	/** Descriptor Type. System(=0) or code/data selector */
4223	uint32_t u1DescType : 1;
4224	/** Descriptor Privilege level. */
4225	uint32_t u2Dpl : 2;
4226	/** Flags selector present(=1) or not. */
4227	uint32_t u1Present : 1;
4228	/** Segment limit 16-19. - IGNORED */
4229	uint32_t u4LimitHigh : 4;
4230	/** Available for system software. - IGNORED */
4231	uint32_t u1Available : 1;
4232	/** Long mode flag. */
4233	uint32_t u1Long : 1;
4234	/** This flags meaning depends on the segment type. Try make sense out
4235	* of the intel manual yourself. */
4236	uint32_t u1DefBig : 1;
4237	/** Granularity of the limit. If set 4KB granularity is used, if
4238	* clear byte. - IGNORED */
4239	uint32_t u1Granularity : 1;
4240	/** Base address - highest 8 bits. - IGNORED */
4241	uint32_t u8BaseHigh2 : 8;
4242	/** Base address - bits 63-32. */
4243	uint32_t u32BaseHigh3 : 32;
4244	uint32_t u8Reserved : 8;
4245	uint32_t u5Zeros : 5;
4246	uint32_t u19Reserved : 19;
4247	} X86DESC64GENERIC;
4248	#pragma pack()
4249	/** Pointer to a generic descriptor entry. */
4250	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4251	/** Pointer to a const generic descriptor entry. */
4252	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4253
4254	/**
4255	* System descriptor table entry (64 bits)
4256	*
4257	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4258	*/
4259	#pragma pack(1)
4260	typedef struct X86DESC64SYSTEM
4261	{
4262	/** Limit - Low word. */
4263	uint32_t u16LimitLow : 16;
4264	/** Base address - low word.
4265	* Don't try set this to 24 because MSC is doing stupid things then. */
4266	uint32_t u16BaseLow : 16;
4267	/** Base address - first 8 bits of high word. */
4268	uint32_t u8BaseHigh1 : 8;
4269	/** Segment Type. */
4270	uint32_t u4Type : 4;
4271	/** Descriptor Type. System(=0) or code/data selector */
4272	uint32_t u1DescType : 1;
4273	/** Descriptor Privilege level. */
4274	uint32_t u2Dpl : 2;
4275	/** Flags selector present(=1) or not. */
4276	uint32_t u1Present : 1;
4277	/** Segment limit 16-19. */
4278	uint32_t u4LimitHigh : 4;
4279	/** Available for system software. */
4280	uint32_t u1Available : 1;
4281	/** Reserved - 0. */
4282	uint32_t u1Reserved : 1;
4283	/** This flags meaning depends on the segment type. Try make sense out
4284	* of the intel manual yourself. */
4285	uint32_t u1DefBig : 1;
4286	/** Granularity of the limit. If set 4KB granularity is used, if
4287	* clear byte. */
4288	uint32_t u1Granularity : 1;
4289	/** Base address - bits 31-24. */
4290	uint32_t u8BaseHigh2 : 8;
4291	/** Base address - bits 63-32. */
4292	uint32_t u32BaseHigh3 : 32;
4293	uint32_t u8Reserved : 8;
4294	uint32_t u5Zeros : 5;
4295	uint32_t u19Reserved : 19;
4296	} X86DESC64SYSTEM;
4297	#pragma pack()
4298	/** Pointer to a system descriptor entry. */
4299	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4300	/** Pointer to a const system descriptor entry. */
4301	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4302
4303	/**
4304	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4305	*/
4306	typedef struct X86DESC64GATE
4307	{
4308	/** Target code segment offset - Low word. */
4309	uint32_t u16OffsetLow : 16;
4310	/** Target code segment selector. */
4311	uint32_t u16Sel : 16;
4312	/** Interrupt stack table for interrupt- and trap-gates.
4313	* Ignored by call-gates. */
4314	uint32_t u3IST : 3;
4315	/** Reserved / ignored. */
4316	uint32_t u5Reserved : 5;
4317	/** Segment Type. */
4318	uint32_t u4Type : 4;
4319	/** Descriptor Type (0 = system). */
4320	uint32_t u1DescType : 1;
4321	/** Descriptor Privilege level. */
4322	uint32_t u2Dpl : 2;
4323	/** Flags selector present(=1) or not. */
4324	uint32_t u1Present : 1;
4325	/** Target code segment offset - High word.
4326	* Ignored if task-gate. */
4327	uint32_t u16OffsetHigh : 16;
4328	/** Target code segment offset - Top dword.
4329	* Ignored if task-gate. */
4330	uint32_t u32OffsetTop : 32;
4331	/** Reserved / ignored / must be zero.
4332	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4333	uint32_t u32Reserved : 32;
4334	} X86DESC64GATE;
4335	AssertCompileSize(X86DESC64GATE, 16);
4336	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4337	typedef X86DESC64GATE *PX86DESC64GATE;
4338	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4339	typedef const X86DESC64GATE *PCX86DESC64GATE;
4340
4341	#endif /* VBOX_FOR_DTRACE_LIB */
4342
4343	/**
4344	* Descriptor table entry.
4345	*/
4346	#pragma pack(1)
4347	typedef union X86DESC64
4348	{
4349	#ifndef VBOX_FOR_DTRACE_LIB
4350	/** Generic descriptor view. */
4351	X86DESC64GENERIC Gen;
4352	/** System descriptor view. */
4353	X86DESC64SYSTEM System;
4354	/** Gate descriptor view. */
4355	X86DESC64GATE Gate;
4356	#endif
4357
4358	/** 8 bit unsigned integer view. */
4359	uint8_t au8[16];
4360	/** 16 bit unsigned integer view. */
4361	uint16_t au16[8];
4362	/** 32 bit unsigned integer view. */
4363	uint32_t au32[4];
4364	/** 64 bit unsigned integer view. */
4365	uint64_t au64[2];
4366	} X86DESC64;
4367	#ifndef VBOX_FOR_DTRACE_LIB
4368	AssertCompileSize(X86DESC64, 16);
4369	#endif
4370	#pragma pack()
4371	/** Pointer to descriptor table entry. */
4372	typedef X86DESC64 *PX86DESC64;
4373	/** Pointer to const descriptor table entry. */
4374	typedef const X86DESC64 *PCX86DESC64;
4375
4376	/** @def X86DESC64_BASE
4377	* Return the base of a 64-bit descriptor.
4378	*/
4379	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4380	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4381	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4382	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4383	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4384
4385
4386
4387	/** @name Host system descriptor table entry - Use with care!
4388	* @{ */
4389	/** Host system descriptor table entry. */
4390	#if HC_ARCH_BITS == 64
4391	typedef X86DESC64 X86DESCHC;
4392	#else
4393	typedef X86DESC X86DESCHC;
4394	#endif
4395	/** Pointer to a host system descriptor table entry. */
4396	#if HC_ARCH_BITS == 64
4397	typedef PX86DESC64 PX86DESCHC;
4398	#else
4399	typedef PX86DESC PX86DESCHC;
4400	#endif
4401	/** Pointer to a const host system descriptor table entry. */
4402	#if HC_ARCH_BITS == 64
4403	typedef PCX86DESC64 PCX86DESCHC;
4404	#else
4405	typedef PCX86DESC PCX86DESCHC;
4406	#endif
4407	/** @} */
4408
4409
4410	/** @name Selector Descriptor Types.
4411	* @{
4412	*/
4413
4414	/** @name Non-System Selector Types.
4415	* @{ */
4416	/** Code(=set)/Data(=clear) bit. */
4417	#define X86_SEL_TYPE_CODE 8
4418	/** Memory(=set)/System(=clear) bit. */
4419	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4420	/** Accessed bit. */
4421	#define X86_SEL_TYPE_ACCESSED 1
4422	/** Expand down bit (for data selectors only). */
4423	#define X86_SEL_TYPE_DOWN 4
4424	/** Conforming bit (for code selectors only). */
4425	#define X86_SEL_TYPE_CONF 4
4426	/** Write bit (for data selectors only). */
4427	#define X86_SEL_TYPE_WRITE 2
4428	/** Read bit (for code selectors only). */
4429	#define X86_SEL_TYPE_READ 2
4430	/** The bit number of the code segment read bit (relative to u4Type). */
4431	#define X86_SEL_TYPE_READ_BIT 1
4432
4433	/** Read only selector type. */
4434	#define X86_SEL_TYPE_RO 0
4435	/** Accessed read only selector type. */
4436	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4437	/** Read write selector type. */
4438	#define X86_SEL_TYPE_RW 2
4439	/** Accessed read write selector type. */
4440	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4441	/** Expand down read only selector type. */
4442	#define X86_SEL_TYPE_RO_DOWN 4
4443	/** Accessed expand down read only selector type. */
4444	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4445	/** Expand down read write selector type. */
4446	#define X86_SEL_TYPE_RW_DOWN 6
4447	/** Accessed expand down read write selector type. */
4448	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4449	/** Execute only selector type. */
4450	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4451	/** Accessed execute only selector type. */
4452	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4453	/** Execute and read selector type. */
4454	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4455	/** Accessed execute and read selector type. */
4456	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4457	/** Conforming execute only selector type. */
4458	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4459	/** Accessed Conforming execute only selector type. */
4460	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4461	/** Conforming execute and write selector type. */
4462	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4463	/** Accessed Conforming execute and write selector type. */
4464	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4465	/** @} */
4466
4467
4468	/** @name System Selector Types.
4469	* @{ */
4470	/** The TSS busy bit mask. */
4471	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4472
4473	/** Undefined system selector type. */
4474	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4475	/** 286 TSS selector. */
4476	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4477	/** LDT selector. */
4478	#define X86_SEL_TYPE_SYS_LDT 2
4479	/** 286 TSS selector - Busy. */
4480	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4481	/** 286 Callgate selector. */
4482	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4483	/** Taskgate selector. */
4484	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4485	/** 286 Interrupt gate selector. */
4486	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4487	/** 286 Trapgate selector. */
4488	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4489	/** Undefined system selector. */
4490	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4491	/** 386 TSS selector. */
4492	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4493	/** Undefined system selector. */
4494	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4495	/** 386 TSS selector - Busy. */
4496	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4497	/** 386 Callgate selector. */
4498	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4499	/** Undefined system selector. */
4500	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4501	/** 386 Interruptgate selector. */
4502	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4503	/** 386 Trapgate selector. */
4504	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4505	/** @} */
4506
4507	/** @name AMD64 System Selector Types.
4508	* @{ */
4509	/** LDT selector. */
4510	#define AMD64_SEL_TYPE_SYS_LDT 2
4511	/** TSS selector - Busy. */
4512	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4513	/** TSS selector - Busy. */
4514	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4515	/** Callgate selector. */
4516	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4517	/** Interruptgate selector. */
4518	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4519	/** Trapgate selector. */
4520	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4521	/** @} */
4522
4523	/** @} */
4524
4525
4526	/** @name Descriptor Table Entry Flag Masks.
4527	* These are for the 2nd 32-bit word of a descriptor.
4528	* @{ */
4529	/** Bits 8-11 - TYPE - Descriptor type mask. */
4530	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4531	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4532	#define X86_DESC_S RT_BIT_32(12)
4533	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4534	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4535	/** Bit 15 - P - Present. */
4536	#define X86_DESC_P RT_BIT_32(15)
4537	/** Bit 20 - AVL - Available for system software. */
4538	#define X86_DESC_AVL RT_BIT_32(20)
4539	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4540	#define X86_DESC_DB RT_BIT_32(22)
4541	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4542	* used, if clear byte. */
4543	#define X86_DESC_G RT_BIT_32(23)
4544	/** @} */
4545
4546	/** @} */
4547
4548
4549	/** @name Task Segments.
4550	* @{
4551	*/
4552
4553	/**
4554	* The minimum TSS descriptor limit for 286 tasks.
4555	*/
4556	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4557
4558	/**
4559	* The minimum TSS descriptor segment limit for 386 tasks.
4560	*/
4561	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4562
4563	/**
4564	* 16-bit Task Segment (TSS).
4565	*/
4566	#pragma pack(1)
4567	typedef struct X86TSS16
4568	{
4569	/** Back link to previous task. (static) */
4570	RTSEL selPrev;
4571	/** Ring-0 stack pointer. (static) */
4572	uint16_t sp0;
4573	/** Ring-0 stack segment. (static) */
4574	RTSEL ss0;
4575	/** Ring-1 stack pointer. (static) */
4576	uint16_t sp1;
4577	/** Ring-1 stack segment. (static) */
4578	RTSEL ss1;
4579	/** Ring-2 stack pointer. (static) */
4580	uint16_t sp2;
4581	/** Ring-2 stack segment. (static) */
4582	RTSEL ss2;
4583	/** IP before task switch. */
4584	uint16_t ip;
4585	/** FLAGS before task switch. */
4586	uint16_t flags;
4587	/** AX before task switch. */
4588	uint16_t ax;
4589	/** CX before task switch. */
4590	uint16_t cx;
4591	/** DX before task switch. */
4592	uint16_t dx;
4593	/** BX before task switch. */
4594	uint16_t bx;
4595	/** SP before task switch. */
4596	uint16_t sp;
4597	/** BP before task switch. */
4598	uint16_t bp;
4599	/** SI before task switch. */
4600	uint16_t si;
4601	/** DI before task switch. */
4602	uint16_t di;
4603	/** ES before task switch. */
4604	RTSEL es;
4605	/** CS before task switch. */
4606	RTSEL cs;
4607	/** SS before task switch. */
4608	RTSEL ss;
4609	/** DS before task switch. */
4610	RTSEL ds;
4611	/** LDTR before task switch. */
4612	RTSEL selLdt;
4613	} X86TSS16;
4614	#ifndef VBOX_FOR_DTRACE_LIB
4615	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4616	#endif
4617	#pragma pack()
4618	/** Pointer to a 16-bit task segment. */
4619	typedef X86TSS16 *PX86TSS16;
4620	/** Pointer to a const 16-bit task segment. */
4621	typedef const X86TSS16 *PCX86TSS16;
4622
4623
4624	/**
4625	* 32-bit Task Segment (TSS).
4626	*/
4627	#pragma pack(1)
4628	typedef struct X86TSS32
4629	{
4630	/** Back link to previous task. (static) */
4631	RTSEL selPrev;
4632	uint16_t padding1;
4633	/** Ring-0 stack pointer. (static) */
4634	uint32_t esp0;
4635	/** Ring-0 stack segment. (static) */
4636	RTSEL ss0;
4637	uint16_t padding_ss0;
4638	/** Ring-1 stack pointer. (static) */
4639	uint32_t esp1;
4640	/** Ring-1 stack segment. (static) */
4641	RTSEL ss1;
4642	uint16_t padding_ss1;
4643	/** Ring-2 stack pointer. (static) */
4644	uint32_t esp2;
4645	/** Ring-2 stack segment. (static) */
4646	RTSEL ss2;
4647	uint16_t padding_ss2;
4648	/** Page directory for the task. (static) */
4649	uint32_t cr3;
4650	/** EIP before task switch. */
4651	uint32_t eip;
4652	/** EFLAGS before task switch. */
4653	uint32_t eflags;
4654	/** EAX before task switch. */
4655	uint32_t eax;
4656	/** ECX before task switch. */
4657	uint32_t ecx;
4658	/** EDX before task switch. */
4659	uint32_t edx;
4660	/** EBX before task switch. */
4661	uint32_t ebx;
4662	/** ESP before task switch. */
4663	uint32_t esp;
4664	/** EBP before task switch. */
4665	uint32_t ebp;
4666	/** ESI before task switch. */
4667	uint32_t esi;
4668	/** EDI before task switch. */
4669	uint32_t edi;
4670	/** ES before task switch. */
4671	RTSEL es;
4672	uint16_t padding_es;
4673	/** CS before task switch. */
4674	RTSEL cs;
4675	uint16_t padding_cs;
4676	/** SS before task switch. */
4677	RTSEL ss;
4678	uint16_t padding_ss;
4679	/** DS before task switch. */
4680	RTSEL ds;
4681	uint16_t padding_ds;
4682	/** FS before task switch. */
4683	RTSEL fs;
4684	uint16_t padding_fs;
4685	/** GS before task switch. */
4686	RTSEL gs;
4687	uint16_t padding_gs;
4688	/** LDTR before task switch. */
4689	RTSEL selLdt;
4690	uint16_t padding_ldt;
4691	/** Debug trap flag */
4692	uint16_t fDebugTrap;
4693	/** Offset relative to the TSS of the start of the I/O Bitmap
4694	* and the end of the interrupt redirection bitmap. */
4695	uint16_t offIoBitmap;
4696	} X86TSS32;
4697	#pragma pack()
4698	/** Pointer to task segment. */
4699	typedef X86TSS32 *PX86TSS32;
4700	/** Pointer to const task segment. */
4701	typedef const X86TSS32 *PCX86TSS32;
4702	#ifndef VBOX_FOR_DTRACE_LIB
4703	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4704	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4705	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4706	#endif
4707
4708	/**
4709	* 64-bit Task segment.
4710	*/
4711	#pragma pack(1)
4712	typedef struct X86TSS64
4713	{
4714	/** Reserved. */
4715	uint32_t u32Reserved;
4716	/** Ring-0 stack pointer. (static) */
4717	uint64_t rsp0;
4718	/** Ring-1 stack pointer. (static) */
4719	uint64_t rsp1;
4720	/** Ring-2 stack pointer. (static) */
4721	uint64_t rsp2;
4722	/** Reserved. */
4723	uint32_t u32Reserved2[2];
4724	/* IST */
4725	uint64_t ist1;
4726	uint64_t ist2;
4727	uint64_t ist3;
4728	uint64_t ist4;
4729	uint64_t ist5;
4730	uint64_t ist6;
4731	uint64_t ist7;
4732	/* Reserved. */
4733	uint16_t u16Reserved[5];
4734	/** Offset relative to the TSS of the start of the I/O Bitmap
4735	* and the end of the interrupt redirection bitmap. */
4736	uint16_t offIoBitmap;
4737	} X86TSS64;
4738	#pragma pack()
4739	/** Pointer to a 64-bit task segment. */
4740	typedef X86TSS64 *PX86TSS64;
4741	/** Pointer to a const 64-bit task segment. */
4742	typedef const X86TSS64 *PCX86TSS64;
4743	#ifndef VBOX_FOR_DTRACE_LIB
4744	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4745	#endif
4746
4747	/** @} */
4748
4749
4750	/** @name Selectors.
4751	* @{
4752	*/
4753
4754	/**
4755	* The shift used to convert a selector from and to index an index (C).
4756	*/
4757	#define X86_SEL_SHIFT 3
4758
4759	/**
4760	* The mask used to mask off the table indicator and RPL of an selector.
4761	*/
4762	#define X86_SEL_MASK 0xfff8U
4763
4764	/**
4765	* The mask used to mask off the RPL of an selector.
4766	* This is suitable for checking for NULL selectors.
4767	*/
4768	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4769
4770	/**
4771	* The bit indicating that a selector is in the LDT and not in the GDT.
4772	*/
4773	#define X86_SEL_LDT 0x0004U
4774
4775	/**
4776	* The bit mask for getting the RPL of a selector.
4777	*/
4778	#define X86_SEL_RPL 0x0003U
4779
4780	/**
4781	* The mask covering both RPL and LDT.
4782	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4783	* checks.
4784	*/
4785	#define X86_SEL_RPL_LDT 0x0007U
4786
4787	/** @} */
4788
4789
4790	/**
4791	* x86 Exceptions/Faults/Traps.
4792	*/
4793	typedef enum X86XCPT
4794	{
4795	/** \#DE - Divide error. */
4796	X86_XCPT_DE = 0x00,
4797	/** \#DB - Debug event (single step, DRx, ..) */
4798	X86_XCPT_DB = 0x01,
4799	/** NMI - Non-Maskable Interrupt */
4800	X86_XCPT_NMI = 0x02,
4801	/** \#BP - Breakpoint (INT3). */
4802	X86_XCPT_BP = 0x03,
4803	/** \#OF - Overflow (INTO). */
4804	X86_XCPT_OF = 0x04,
4805	/** \#BR - Bound range exceeded (BOUND). */
4806	X86_XCPT_BR = 0x05,
4807	/** \#UD - Undefined opcode. */
4808	X86_XCPT_UD = 0x06,
4809	/** \#NM - Device not available (math coprocessor device). */
4810	X86_XCPT_NM = 0x07,
4811	/** \#DF - Double fault. */
4812	X86_XCPT_DF = 0x08,
4813	/** ??? - Coprocessor segment overrun (obsolete). */
4814	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4815	/** \#TS - Taskswitch (TSS). */
4816	X86_XCPT_TS = 0x0a,
4817	/** \#NP - Segment no present. */
4818	X86_XCPT_NP = 0x0b,
4819	/** \#SS - Stack segment fault. */
4820	X86_XCPT_SS = 0x0c,
4821	/** \#GP - General protection fault. */
4822	X86_XCPT_GP = 0x0d,
4823	/** \#PF - Page fault. */
4824	X86_XCPT_PF = 0x0e,
4825	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4826	/** \#MF - Math fault (FPU). */
4827	X86_XCPT_MF = 0x10,
4828	/** \#AC - Alignment check. */
4829	X86_XCPT_AC = 0x11,
4830	/** \#MC - Machine check. */
4831	X86_XCPT_MC = 0x12,
4832	/** \#XF - SIMD Floating-Point Exception. */
4833	X86_XCPT_XF = 0x13,
4834	/** \#VE - Virtualization Exception (Intel only). */
4835	X86_XCPT_VE = 0x14,
4836	/** \#CP - Control Protection Exception. */
4837	X86_XCPT_CP = 0x15,
4838	/** \#VC - VMM Communication Exception (AMD only). */
4839	X86_XCPT_VC = 0x1d,
4840	/** \#SX - Security Exception (AMD only). */
4841	X86_XCPT_SX = 0x1e
4842	} X86XCPT;
4843	/** Pointer to a x86 exception code. */
4844	typedef X86XCPT *PX86XCPT;
4845	/** Pointer to a const x86 exception code. */
4846	typedef const X86XCPT *PCX86XCPT;
4847	/** The last valid (currently reserved) exception value. */
4848	#define X86_XCPT_LAST 0x1f
4849
4850
4851	/** @name Trap Error Codes
4852	* @{
4853	*/
4854	/** External indicator. */
4855	#define X86_TRAP_ERR_EXTERNAL 1
4856	/** IDT indicator. */
4857	#define X86_TRAP_ERR_IDT 2
4858	/** Descriptor table indicator - If set LDT, if clear GDT. */
4859	#define X86_TRAP_ERR_TI 4
4860	/** Mask for getting the selector. */
4861	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4862	/** Shift for getting the selector table index (C type index). */
4863	#define X86_TRAP_ERR_SEL_SHIFT 3
4864	/** @} */
4865
4866
4867	/** @name \#PF Trap Error Codes
4868	* @{
4869	*/
4870	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4871	#define X86_TRAP_PF_P RT_BIT_32(0)
4872	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4873	#define X86_TRAP_PF_RW RT_BIT_32(1)
4874	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4875	#define X86_TRAP_PF_US RT_BIT_32(2)
4876	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4877	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4878	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4879	#define X86_TRAP_PF_ID RT_BIT_32(4)
4880	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4881	#define X86_TRAP_PF_PK RT_BIT_32(5)
4882	/** @} */
4883
4884	#pragma pack(1)
4885	/**
4886	* 16-bit IDTR.
4887	*/
4888	typedef struct X86IDTR16
4889	{
4890	/** Offset. */
4891	uint16_t offSel;
4892	/** Selector. */
4893	uint16_t uSel;
4894	} X86IDTR16, *PX86IDTR16;
4895	#pragma pack()
4896
4897	#pragma pack(1)
4898	/**
4899	* 32-bit IDTR/GDTR.
4900	*/
4901	typedef struct X86XDTR32
4902	{
4903	/** Size of the descriptor table. */
4904	uint16_t cb;
4905	/** Address of the descriptor table. */
4906	#ifndef VBOX_FOR_DTRACE_LIB
4907	uint32_t uAddr;
4908	#else
4909	uint16_t au16Addr[2];
4910	#endif
4911	} X86XDTR32, *PX86XDTR32;
4912	#pragma pack()
4913
4914	#pragma pack(1)
4915	/**
4916	* 64-bit IDTR/GDTR.
4917	*/
4918	typedef struct X86XDTR64
4919	{
4920	/** Size of the descriptor table. */
4921	uint16_t cb;
4922	/** Address of the descriptor table. */
4923	#ifndef VBOX_FOR_DTRACE_LIB
4924	uint64_t uAddr;
4925	#else
4926	uint16_t au16Addr[4];
4927	#endif
4928	} X86XDTR64, *PX86XDTR64;
4929	#pragma pack()
4930
4931
4932	/** @name ModR/M
4933	* @{ */
4934	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4935	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4936	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4937	#define X86_MODRM_REG_SHIFT 3
4938	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4939	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4940	#define X86_MODRM_MOD_SHIFT 6
4941
4942	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
4943	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
4944	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
4945	#define X86_MOD_REG 3 /*< Registers. /
4946
4947	#ifndef VBOX_FOR_DTRACE_LIB
4948	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4949	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4950	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4951	/** @def X86_MODRM_MAKE
4952	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
4953	* @param a_Reg The register value (0..7).
4954	* @param a_RegMem The register or memory value (0..7). */
4955	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4956	#endif
4957
4958	/** @} */
4959
4960	/** @name SIB
4961	* @{ */
4962	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4963	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4964	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4965	#define X86_SIB_INDEX_SHIFT 3
4966	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4967	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4968	#define X86_SIB_SCALE_SHIFT 6
4969	#ifndef VBOX_FOR_DTRACE_LIB
4970	/** @def X86_SIB_MAKE
4971	* @param a_BaseReg The base register value (0..7).
4972	* @param a_IndexReg The index register value (0..7).
4973	* @param a_Scale The left shift (0..3) to be applied to the index
4974	* register (0 = none, 1 = x2, 2 = x4, 3 = x8).
4975	* */
4976	# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
4977	(((a_Scale) << X86_SIB_SCALE_SHIFT) \| ((a_IndexReg) << X86_SIB_INDEX_SHIFT) \| (a_BaseReg))
4978
4979	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4980	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4981	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4982	#endif
4983	/** @} */
4984
4985	/** @name General register indexes.
4986	* @{ */
4987	#define X86_GREG_xAX 0
4988	#define X86_GREG_xCX 1
4989	#define X86_GREG_xDX 2
4990	#define X86_GREG_xBX 3
4991	#define X86_GREG_xSP 4
4992	#define X86_GREG_xBP 5
4993	#define X86_GREG_xSI 6
4994	#define X86_GREG_xDI 7
4995	#define X86_GREG_x8 8
4996	#define X86_GREG_x9 9
4997	#define X86_GREG_x10 10
4998	#define X86_GREG_x11 11
4999	#define X86_GREG_x12 12
5000	#define X86_GREG_x13 13
5001	#define X86_GREG_x14 14
5002	#define X86_GREG_x15 15
5003	/** @} */
5004	/** General register count. */
5005	#define X86_GREG_COUNT 16
5006
5007	/** @name X86_SREG_XXX - Segment register indexes.
5008	* @{ */
5009	#define X86_SREG_ES 0
5010	#define X86_SREG_CS 1
5011	#define X86_SREG_SS 2
5012	#define X86_SREG_DS 3
5013	#define X86_SREG_FS 4
5014	#define X86_SREG_GS 5
5015	/** @} */
5016	/** Segment register count. */
5017	#define X86_SREG_COUNT 6
5018
5019
5020	/** @name X86_OP_XXX - Prefixes
5021	* @{ */
5022	#define X86_OP_PRF_CS UINT8_C(0x2e)
5023	#define X86_OP_PRF_SS UINT8_C(0x36)
5024	#define X86_OP_PRF_DS UINT8_C(0x3e)
5025	#define X86_OP_PRF_ES UINT8_C(0x26)
5026	#define X86_OP_PRF_FS UINT8_C(0x64)
5027	#define X86_OP_PRF_GS UINT8_C(0x65)
5028	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5029	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5030	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5031	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5032	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5033	#define X86_OP_REX UINT8_C(0x40)
5034	#define X86_OP_REX_B UINT8_C(0x41)
5035	#define X86_OP_REX_X UINT8_C(0x42)
5036	#define X86_OP_REX_R UINT8_C(0x44)
5037	#define X86_OP_REX_W UINT8_C(0x48)
5038	/** @} */
5039
5040
5041	/** @} */
5042
5043	#endif /* !IPRT_INCLUDED_x86_h */
5044

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