x86.h@ 41343

Last change on this file since 41343 was 41270, checked in by vboxsync, 13 years ago
cleanups
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 110.7 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	/** Bit 1 - Reserved, reads as 1. */
165	#define X86_EFL_1 RT_BIT(1)
166	/** Bit 2 - PF - Parity flag - Status flag. */
167	#define X86_EFL_PF RT_BIT(2)
168	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169	#define X86_EFL_AF RT_BIT(4)
170	/** Bit 6 - ZF - Zero flag - Status flag. */
171	#define X86_EFL_ZF RT_BIT(6)
172	/** Bit 7 - SF - Signed flag - Status flag. */
173	#define X86_EFL_SF RT_BIT(7)
174	/** Bit 8 - TF - Trap flag - System flag. */
175	#define X86_EFL_TF RT_BIT(8)
176	/** Bit 9 - IF - Interrupt flag - System flag. */
177	#define X86_EFL_IF RT_BIT(9)
178	/** Bit 10 - DF - Direction flag - Control flag. */
179	#define X86_EFL_DF RT_BIT(10)
180	/** Bit 11 - OF - Overflow flag - Status flag. */
181	#define X86_EFL_OF RT_BIT(11)
182	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
184	/** Bit 14 - NT - Nested task flag - System flag. */
185	#define X86_EFL_NT RT_BIT(14)
186	/** Bit 16 - RF - Resume flag - System flag. */
187	#define X86_EFL_RF RT_BIT(16)
188	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189	#define X86_EFL_VM RT_BIT(17)
190	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191	#define X86_EFL_AC RT_BIT(18)
192	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193	#define X86_EFL_VIF RT_BIT(19)
194	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195	#define X86_EFL_VIP RT_BIT(20)
196	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197	#define X86_EFL_ID RT_BIT(21)
198	/** IOPL shift. */
199	#define X86_EFL_IOPL_SHIFT 12
200	/** The the IOPL level from the flags. */
201	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
202	/** Bits restored by popf */
203	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
204	/** @} */
205
206
207	/** CPUID Feature information - ECX.
208	* CPUID query with EAX=1.
209	*/
210	#ifndef VBOX_FOR_DTRACE_LIB
211	typedef struct X86CPUIDFEATECX
212	{
213	/** Bit 0 - SSE3 - Supports SSE3 or not. */
214	unsigned u1SSE3 : 1;
215	/** Bit 1 - PCLMULQDQ. */
216	unsigned u1PCLMULQDQ : 1;
217	/** Bit 2 - DS Area 64-bit layout. */
218	unsigned u1DTE64 : 1;
219	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
220	unsigned u1Monitor : 1;
221	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
222	unsigned u1CPLDS : 1;
223	/** Bit 5 - VMX - Virtual Machine Technology. */
224	unsigned u1VMX : 1;
225	/** Bit 6 - SMX: Safer Mode Extensions. */
226	unsigned u1SMX : 1;
227	/** Bit 7 - EST - Enh. SpeedStep Tech. */
228	unsigned u1EST : 1;
229	/** Bit 8 - TM2 - Terminal Monitor 2. */
230	unsigned u1TM2 : 1;
231	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
232	unsigned u1SSSE3 : 1;
233	/** Bit 10 - CNTX-ID - L1 Context ID. */
234	unsigned u1CNTXID : 1;
235	/** Bit 11 - Reserved. */
236	unsigned u1Reserved1 : 1;
237	/** Bit 12 - FMA. */
238	unsigned u1FMA : 1;
239	/** Bit 13 - CX16 - CMPXCHG16B. */
240	unsigned u1CX16 : 1;
241	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
242	unsigned u1TPRUpdate : 1;
243	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
244	unsigned u1PDCM : 1;
245	/** Bit 16 - Reserved. */
246	unsigned u1Reserved2 : 1;
247	/** Bit 17 - PCID - Process-context identifiers. */
248	unsigned u1PCID : 1;
249	/** Bit 18 - Direct Cache Access. */
250	unsigned u1DCA : 1;
251	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
252	unsigned u1SSE4_1 : 1;
253	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
254	unsigned u1SSE4_2 : 1;
255	/** Bit 21 - x2APIC. */
256	unsigned u1x2APIC : 1;
257	/** Bit 22 - MOVBE - Supports MOVBE. */
258	unsigned u1MOVBE : 1;
259	/** Bit 23 - POPCNT - Supports POPCNT. */
260	unsigned u1POPCNT : 1;
261	/** Bit 24 - TSC-Deadline. */
262	unsigned u1TSCDEADLINE : 1;
263	/** Bit 25 - AES. */
264	unsigned u1AES : 1;
265	/** Bit 26 - XSAVE - Supports XSAVE. */
266	unsigned u1XSAVE : 1;
267	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
268	unsigned u1OSXSAVE : 1;
269	/** Bit 28 - AVX - Supports AVX instruction extensions. */
270	unsigned u1AVX : 1;
271	/** Bit 29 - 30 - Reserved */
272	unsigned u2Reserved3 : 2;
273	/** Bit 31 - Hypervisor present (we're a guest). */
274	unsigned u1HVP : 1;
275	} X86CPUIDFEATECX;
276	#else /* VBOX_FOR_DTRACE_LIB */
277	typedef uint32_t X86CPUIDFEATECX;
278	#endif /* VBOX_FOR_DTRACE_LIB */
279	/** Pointer to CPUID Feature Information - ECX. */
280	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
281	/** Pointer to const CPUID Feature Information - ECX. */
282	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
283
284
285	/** CPUID Feature Information - EDX.
286	* CPUID query with EAX=1.
287	*/
288	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
289	typedef struct X86CPUIDFEATEDX
290	{
291	/** Bit 0 - FPU - x87 FPU on Chip. */
292	unsigned u1FPU : 1;
293	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
294	unsigned u1VME : 1;
295	/** Bit 2 - DE - Debugging extensions. */
296	unsigned u1DE : 1;
297	/** Bit 3 - PSE - Page Size Extension. */
298	unsigned u1PSE : 1;
299	/** Bit 4 - TSC - Time Stamp Counter. */
300	unsigned u1TSC : 1;
301	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
302	unsigned u1MSR : 1;
303	/** Bit 6 - PAE - Physical Address Extension. */
304	unsigned u1PAE : 1;
305	/** Bit 7 - MCE - Machine Check Exception. */
306	unsigned u1MCE : 1;
307	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
308	unsigned u1CX8 : 1;
309	/** Bit 9 - APIC - APIC On-Chip. */
310	unsigned u1APIC : 1;
311	/** Bit 10 - Reserved. */
312	unsigned u1Reserved1 : 1;
313	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
314	unsigned u1SEP : 1;
315	/** Bit 12 - MTRR - Memory Type Range Registers. */
316	unsigned u1MTRR : 1;
317	/** Bit 13 - PGE - PTE Global Bit. */
318	unsigned u1PGE : 1;
319	/** Bit 14 - MCA - Machine Check Architecture. */
320	unsigned u1MCA : 1;
321	/** Bit 15 - CMOV - Conditional Move Instructions. */
322	unsigned u1CMOV : 1;
323	/** Bit 16 - PAT - Page Attribute Table. */
324	unsigned u1PAT : 1;
325	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
326	unsigned u1PSE36 : 1;
327	/** Bit 18 - PSN - Processor Serial Number. */
328	unsigned u1PSN : 1;
329	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
330	unsigned u1CLFSH : 1;
331	/** Bit 20 - Reserved. */
332	unsigned u1Reserved2 : 1;
333	/** Bit 21 - DS - Debug Store. */
334	unsigned u1DS : 1;
335	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
336	unsigned u1ACPI : 1;
337	/** Bit 23 - MMX - Intel MMX 'Technology'. */
338	unsigned u1MMX : 1;
339	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
340	unsigned u1FXSR : 1;
341	/** Bit 25 - SSE - SSE Support. */
342	unsigned u1SSE : 1;
343	/** Bit 26 - SSE2 - SSE2 Support. */
344	unsigned u1SSE2 : 1;
345	/** Bit 27 - SS - Self Snoop. */
346	unsigned u1SS : 1;
347	/** Bit 28 - HTT - Hyper-Threading Technology. */
348	unsigned u1HTT : 1;
349	/** Bit 29 - TM - Thermal Monitor. */
350	unsigned u1TM : 1;
351	/** Bit 30 - Reserved - . */
352	unsigned u1Reserved3 : 1;
353	/** Bit 31 - PBE - Pending Break Enabled. */
354	unsigned u1PBE : 1;
355	} X86CPUIDFEATEDX;
356	#else /* VBOX_FOR_DTRACE_LIB */
357	typedef uint32_t X86CPUIDFEATEDX;
358	#endif /* VBOX_FOR_DTRACE_LIB */
359	/** Pointer to CPUID Feature Information - EDX. */
360	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
361	/** Pointer to const CPUID Feature Information - EDX. */
362	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
363
364	/** @name CPUID Vendor information.
365	* CPUID query with EAX=0.
366	* @{
367	*/
368	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
369	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
370	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
371
372	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
373	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
374	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
375	/** @} */
376
377
378	/** @name CPUID Feature information.
379	* CPUID query with EAX=1.
380	* @{
381	*/
382	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
383	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
384	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
385	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
386	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
387	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
388	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
389	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
390	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
391	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
392	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
393	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
394	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
395	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
396	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
397	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
398	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
399	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
400	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
401	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
402	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
403	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
404	/** ECX Bit 12 - FMA. */
405	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
406	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
407	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
408	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
409	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
410	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
411	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
412	/** ECX Bit 17 - PCID - Process-context identifiers. */
413	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
414	/** ECX Bit 18 - DCA - Direct Cache Access. */
415	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
416	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
417	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
418	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
419	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
420	/** ECX Bit 21 - x2APIC support. */
421	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
422	/** ECX Bit 22 - MOVBE instruction. */
423	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
424	/** ECX Bit 23 - POPCNT instruction. */
425	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
426	/** ECX Bir 24 - TSC-Deadline. */
427	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
428	/** ECX Bit 25 - AES instructions. */
429	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
430	/** ECX Bit 26 - XSAVE instruction. */
431	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
432	/** ECX Bit 27 - OSXSAVE instruction. */
433	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
434	/** ECX Bit 28 - AVX. */
435	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
436	/** ECX Bit 31 - Hypervisor Present (software only). */
437	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
438
439
440	/** Bit 0 - FPU - x87 FPU on Chip. */
441	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
442	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
443	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
444	/** Bit 2 - DE - Debugging extensions. */
445	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
446	/** Bit 3 - PSE - Page Size Extension. */
447	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
448	/** Bit 4 - TSC - Time Stamp Counter. */
449	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
450	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
451	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
452	/** Bit 6 - PAE - Physical Address Extension. */
453	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
454	/** Bit 7 - MCE - Machine Check Exception. */
455	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
456	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
457	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
458	/** Bit 9 - APIC - APIC On-Chip. */
459	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
460	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
461	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
462	/** Bit 12 - MTRR - Memory Type Range Registers. */
463	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
464	/** Bit 13 - PGE - PTE Global Bit. */
465	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
466	/** Bit 14 - MCA - Machine Check Architecture. */
467	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
468	/** Bit 15 - CMOV - Conditional Move Instructions. */
469	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
470	/** Bit 16 - PAT - Page Attribute Table. */
471	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
472	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
473	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
474	/** Bit 18 - PSN - Processor Serial Number. */
475	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
476	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
477	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
478	/** Bit 21 - DS - Debug Store. */
479	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
480	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
481	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
482	/** Bit 23 - MMX - Intel MMX Technology. */
483	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
484	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
485	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
486	/** Bit 25 - SSE - SSE Support. */
487	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
488	/** Bit 26 - SSE2 - SSE2 Support. */
489	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
490	/** Bit 27 - SS - Self Snoop. */
491	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
492	/** Bit 28 - HTT - Hyper-Threading Technology. */
493	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
494	/** Bit 29 - TM - Therm. Monitor. */
495	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
496	/** Bit 31 - PBE - Pending Break Enabled. */
497	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
498	/** @} */
499
500	/** @name CPUID mwait/monitor information.
501	* CPUID query with EAX=5.
502	* @{
503	*/
504	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
505	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
506	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
507	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
508	/** @} */
509
510
511	/** @name CPUID AMD Feature information.
512	* CPUID query with EAX=0x80000001.
513	* @{
514	*/
515	/** Bit 0 - FPU - x87 FPU on Chip. */
516	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
517	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
518	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
519	/** Bit 2 - DE - Debugging extensions. */
520	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
521	/** Bit 3 - PSE - Page Size Extension. */
522	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
523	/** Bit 4 - TSC - Time Stamp Counter. */
524	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
525	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
526	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
527	/** Bit 6 - PAE - Physical Address Extension. */
528	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
529	/** Bit 7 - MCE - Machine Check Exception. */
530	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
531	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
532	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
533	/** Bit 9 - APIC - APIC On-Chip. */
534	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
535	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
536	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
537	/** Bit 12 - MTRR - Memory Type Range Registers. */
538	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
539	/** Bit 13 - PGE - PTE Global Bit. */
540	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
541	/** Bit 14 - MCA - Machine Check Architecture. */
542	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
543	/** Bit 15 - CMOV - Conditional Move Instructions. */
544	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
545	/** Bit 16 - PAT - Page Attribute Table. */
546	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
547	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
548	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
549	/** Bit 20 - NX - AMD No-Execute Page Protection. */
550	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
551	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
552	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
553	/** Bit 23 - MMX - Intel MMX Technology. */
554	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
555	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
556	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
557	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
558	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
559	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
560	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
561	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
562	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
563	/** Bit 29 - LM - AMD Long Mode. */
564	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
565	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
566	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
567	/** Bit 31 - 3DNOW - AMD 3DNow. */
568	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
569
570	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
571	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
572	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
573	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
574	/** Bit 2 - SVM - AMD VM extensions. */
575	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
576	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
577	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
578	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
579	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
580	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
581	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
582	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
583	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
584	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
585	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
586	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
587	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
588	/** Bit 9 - OSVW - AMD OS visible workaround. */
589	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
590	/** Bit 10 - IBS - Instruct based sampling. */
591	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
592	/** Bit 11 - SSE5 - SSE5 instruction support. */
593	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
594	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
595	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
596	/** Bit 13 - WDT - AMD Watchdog timer support. */
597	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
598
599	/** @} */
600
601
602	/** @name CPUID AMD Feature information.
603	* CPUID query with EAX=0x80000007.
604	* @{
605	*/
606	/** Bit 0 - TS - Temperature Sensor. */
607	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
608	/** Bit 1 - FID - Frequency ID Control. */
609	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
610	/** Bit 2 - VID - Voltage ID Control. */
611	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
612	/** Bit 3 - TTP - THERMTRIP. */
613	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
614	/** Bit 4 - TM - Hardware Thermal Control. */
615	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
616	/** Bit 5 - STC - Software Thermal Control. */
617	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
618	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
619	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
620	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
621	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
622	/** Bit 8 - TSCINVAR - TSC Invariant. */
623	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
624	/** @} */
625
626
627	/** @name CR0
628	* @{ */
629	/** Bit 0 - PE - Protection Enabled */
630	#define X86_CR0_PE RT_BIT(0)
631	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
632	/** Bit 1 - MP - Monitor Coprocessor */
633	#define X86_CR0_MP RT_BIT(1)
634	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
635	/** Bit 2 - EM - Emulation. */
636	#define X86_CR0_EM RT_BIT(2)
637	#define X86_CR0_EMULATE_FPU RT_BIT(2)
638	/** Bit 3 - TS - Task Switch. */
639	#define X86_CR0_TS RT_BIT(3)
640	#define X86_CR0_TASK_SWITCH RT_BIT(3)
641	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
642	#define X86_CR0_ET RT_BIT(4)
643	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
644	/** Bit 5 - NE - Numeric error. */
645	#define X86_CR0_NE RT_BIT(5)
646	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
647	/** Bit 16 - WP - Write Protect. */
648	#define X86_CR0_WP RT_BIT(16)
649	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
650	/** Bit 18 - AM - Alignment Mask. */
651	#define X86_CR0_AM RT_BIT(18)
652	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
653	/** Bit 29 - NW - Not Write-though. */
654	#define X86_CR0_NW RT_BIT(29)
655	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
656	/** Bit 30 - WP - Cache Disable. */
657	#define X86_CR0_CD RT_BIT(30)
658	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
659	/** Bit 31 - PG - Paging. */
660	#define X86_CR0_PG RT_BIT(31)
661	#define X86_CR0_PAGING RT_BIT(31)
662	/** @} */
663
664
665	/** @name CR3
666	* @{ */
667	/** Bit 3 - PWT - Page-level Writes Transparent. */
668	#define X86_CR3_PWT RT_BIT(3)
669	/** Bit 4 - PCD - Page-level Cache Disable. */
670	#define X86_CR3_PCD RT_BIT(4)
671	/** Bits 12-31 - - Page directory page number. */
672	#define X86_CR3_PAGE_MASK (0xfffff000)
673	/** Bits 5-31 - - PAE Page directory page number. */
674	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
675	/** Bits 12-51 - - AMD64 Page directory page number. */
676	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
677	/** @} */
678
679
680	/** @name CR4
681	* @{ */
682	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
683	#define X86_CR4_VME RT_BIT(0)
684	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
685	#define X86_CR4_PVI RT_BIT(1)
686	/** Bit 2 - TSD - Time Stamp Disable. */
687	#define X86_CR4_TSD RT_BIT(2)
688	/** Bit 3 - DE - Debugging Extensions. */
689	#define X86_CR4_DE RT_BIT(3)
690	/** Bit 4 - PSE - Page Size Extension. */
691	#define X86_CR4_PSE RT_BIT(4)
692	/** Bit 5 - PAE - Physical Address Extension. */
693	#define X86_CR4_PAE RT_BIT(5)
694	/** Bit 6 - MCE - Machine-Check Enable. */
695	#define X86_CR4_MCE RT_BIT(6)
696	/** Bit 7 - PGE - Page Global Enable. */
697	#define X86_CR4_PGE RT_BIT(7)
698	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
699	#define X86_CR4_PCE RT_BIT(8)
700	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
701	#define X86_CR4_OSFSXR RT_BIT(9)
702	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
703	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
704	/** Bit 13 - VMXE - VMX mode is enabled. */
705	#define X86_CR4_VMXE RT_BIT(13)
706	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
707	#define X86_CR4_SMXE RT_BIT(14)
708	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
709	#define X86_CR4_PCIDE RT_BIT(17)
710	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
711	* extended states. */
712	#define X86_CR4_OSXSAVE RT_BIT(18)
713	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
714	#define X86_CR4_SMEP RT_BIT(20)
715	/** @} */
716
717
718	/** @name DR6
719	* @{ */
720	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
721	#define X86_DR6_B0 RT_BIT(0)
722	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
723	#define X86_DR6_B1 RT_BIT(1)
724	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
725	#define X86_DR6_B2 RT_BIT(2)
726	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
727	#define X86_DR6_B3 RT_BIT(3)
728	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
729	#define X86_DR6_BD RT_BIT(13)
730	/** Bit 14 - BS - Single step */
731	#define X86_DR6_BS RT_BIT(14)
732	/** Bit 15 - BT - Task switch. (TSS T bit.) */
733	#define X86_DR6_BT RT_BIT(15)
734	/** Value of DR6 after powerup/reset. */
735	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
736	/** @} */
737
738
739	/** @name DR7
740	* @{ */
741	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
742	#define X86_DR7_L0 RT_BIT(0)
743	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
744	#define X86_DR7_G0 RT_BIT(1)
745	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
746	#define X86_DR7_L1 RT_BIT(2)
747	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
748	#define X86_DR7_G1 RT_BIT(3)
749	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
750	#define X86_DR7_L2 RT_BIT(4)
751	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
752	#define X86_DR7_G2 RT_BIT(5)
753	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
754	#define X86_DR7_L3 RT_BIT(6)
755	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
756	#define X86_DR7_G3 RT_BIT(7)
757	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
758	#define X86_DR7_LE RT_BIT(8)
759	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
760	#define X86_DR7_GE RT_BIT(9)
761
762	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
763	* any DR register is accessed. */
764	#define X86_DR7_GD RT_BIT(13)
765	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
766	#define X86_DR7_RW0_MASK (3 << 16)
767	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
768	#define X86_DR7_LEN0_MASK (3 << 18)
769	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
770	#define X86_DR7_RW1_MASK (3 << 20)
771	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
772	#define X86_DR7_LEN1_MASK (3 << 22)
773	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
774	#define X86_DR7_RW2_MASK (3 << 24)
775	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
776	#define X86_DR7_LEN2_MASK (3 << 26)
777	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
778	#define X86_DR7_RW3_MASK (3 << 28)
779	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
780	#define X86_DR7_LEN3_MASK (3 << 30)
781
782	/** Bits which must be 1s. */
783	#define X86_DR7_MB1_MASK (RT_BIT(10))
784
785	/** Calcs the L bit of Nth breakpoint.
786	* @param iBp The breakpoint number [0..3].
787	*/
788	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
789
790	/** Calcs the G bit of Nth breakpoint.
791	* @param iBp The breakpoint number [0..3].
792	*/
793	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
794
795	/** @name Read/Write values.
796	* @{ */
797	/** Break on instruction fetch only. */
798	#define X86_DR7_RW_EO 0U
799	/** Break on write only. */
800	#define X86_DR7_RW_WO 1U
801	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
802	#define X86_DR7_RW_IO 2U
803	/** Break on read or write (but not instruction fetches). */
804	#define X86_DR7_RW_RW 3U
805	/** @} */
806
807	/** Shifts a X86_DR7_RW_* value to its right place.
808	* @param iBp The breakpoint number [0..3].
809	* @param fRw One of the X86_DR7_RW_* value.
810	*/
811	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
812
813	/** @name Length values.
814	* @{ */
815	#define X86_DR7_LEN_BYTE 0U
816	#define X86_DR7_LEN_WORD 1U
817	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
818	#define X86_DR7_LEN_DWORD 3U
819	/** @} */
820
821	/** Shifts a X86_DR7_LEN_* value to its right place.
822	* @param iBp The breakpoint number [0..3].
823	* @param cb One of the X86_DR7_LEN_* values.
824	*/
825	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
826
827	/** Fetch the breakpoint length bits from the DR7 value.
828	* @param uDR7 DR7 value
829	* @param iBp The breakpoint number [0..3].
830	*/
831	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
832
833	/** Mask used to check if any breakpoints are enabled. */
834	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
835
836	/** Mask used to check if any io breakpoints are set. */
837	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
838
839	/** Value of DR7 after powerup/reset. */
840	#define X86_DR7_INIT_VAL 0x400
841	/** @} */
842
843
844	/** @name Machine Specific Registers
845	* @{
846	*/
847
848	/** Time Stamp Counter. */
849	#define MSR_IA32_TSC 0x10
850
851	#define MSR_IA32_PLATFORM_ID 0x17
852
853	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
854	#define MSR_IA32_APICBASE 0x1b
855	#endif
856
857	/** CPU Feature control. */
858	#define MSR_IA32_FEATURE_CONTROL 0x3A
859	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
860	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
861
862	/** BIOS update trigger (microcode update). */
863	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
864
865	/** BIOS update signature (microcode). */
866	#define MSR_IA32_BIOS_SIGN_ID 0x8B
867
868	/** General performance counter no. 0. */
869	#define MSR_IA32_PMC0 0xC1
870	/** General performance counter no. 1. */
871	#define MSR_IA32_PMC1 0xC2
872	/** General performance counter no. 2. */
873	#define MSR_IA32_PMC2 0xC3
874	/** General performance counter no. 3. */
875	#define MSR_IA32_PMC3 0xC4
876
877	/** Nehalem power control. */
878	#define MSR_IA32_PLATFORM_INFO 0xCE
879
880	/** Get FSB clock status (Intel-specific). */
881	#define MSR_IA32_FSB_CLOCK_STS 0xCD
882
883	/** MTRR Capabilities. */
884	#define MSR_IA32_MTRR_CAP 0xFE
885
886
887	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
888	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
889	* R0 SS == CS + 8
890	* R3 CS == CS + 16
891	* R3 SS == CS + 24
892	*/
893	#define MSR_IA32_SYSENTER_CS 0x174
894	/** SYSENTER_ESP - the R0 ESP. */
895	#define MSR_IA32_SYSENTER_ESP 0x175
896	/** SYSENTER_EIP - the R0 EIP. */
897	#define MSR_IA32_SYSENTER_EIP 0x176
898	#endif
899
900	/** Machine Check Global Capabilities Register. */
901	#define MSR_IA32_MCP_CAP 0x179
902	/** Machine Check Global Status Register. */
903	#define MSR_IA32_MCP_STATUS 0x17A
904	/** Machine Check Global Control Register. */
905	#define MSR_IA32_MCP_CTRL 0x17B
906
907	/** Trace/Profile Resource Control (R/W) */
908	#define MSR_IA32_DEBUGCTL 0x1D9
909
910	/** Page Attribute Table. */
911	#define MSR_IA32_CR_PAT 0x277
912
913	/** Performance counter MSRs. (Intel only) */
914	#define MSR_IA32_PERFEVTSEL0 0x186
915	#define MSR_IA32_PERFEVTSEL1 0x187
916	#define MSR_IA32_FLEX_RATIO 0x194
917	#define MSR_IA32_PERF_STATUS 0x198
918	#define MSR_IA32_PERF_CTL 0x199
919	#define MSR_IA32_THERM_STATUS 0x19c
920
921	/** Enable misc. processor features (R/W). */
922	#define MSR_IA32_MISC_ENABLE 0x1A0
923	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
924	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
925	/** Automatic Thermal Control Circuit Enable (R/W). */
926	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
927	/** Performance Monitoring Available (R). */
928	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
929	/** Branch Trace Storage Unavailable (R/O). */
930	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
931	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
932	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
933	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
934	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
935	/** If MONITOR/MWAIT is supported (R/W). */
936	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
937	/** Limit CPUID Maxval to 3 leafs (R/W). */
938	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
939	/** When set to 1, xTPR messages are disabled (R/W). */
940	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
941	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
942	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
943
944	#define IA32_MTRR_PHYSBASE0 0x200
945	#define IA32_MTRR_PHYSMASK0 0x201
946	#define IA32_MTRR_PHYSBASE1 0x202
947	#define IA32_MTRR_PHYSMASK1 0x203
948	#define IA32_MTRR_PHYSBASE2 0x204
949	#define IA32_MTRR_PHYSMASK2 0x205
950	#define IA32_MTRR_PHYSBASE3 0x206
951	#define IA32_MTRR_PHYSMASK3 0x207
952	#define IA32_MTRR_PHYSBASE4 0x208
953	#define IA32_MTRR_PHYSMASK4 0x209
954	#define IA32_MTRR_PHYSBASE5 0x20a
955	#define IA32_MTRR_PHYSMASK5 0x20b
956	#define IA32_MTRR_PHYSBASE6 0x20c
957	#define IA32_MTRR_PHYSMASK6 0x20d
958	#define IA32_MTRR_PHYSBASE7 0x20e
959	#define IA32_MTRR_PHYSMASK7 0x20f
960	#define IA32_MTRR_PHYSBASE8 0x210
961	#define IA32_MTRR_PHYSMASK8 0x211
962	#define IA32_MTRR_PHYSBASE9 0x212
963	#define IA32_MTRR_PHYSMASK9 0x213
964
965	/** Fixed range MTRRs.
966	* @{ */
967	#define IA32_MTRR_FIX64K_00000 0x250
968	#define IA32_MTRR_FIX16K_80000 0x258
969	#define IA32_MTRR_FIX16K_A0000 0x259
970	#define IA32_MTRR_FIX4K_C0000 0x268
971	#define IA32_MTRR_FIX4K_C8000 0x269
972	#define IA32_MTRR_FIX4K_D0000 0x26a
973	#define IA32_MTRR_FIX4K_D8000 0x26b
974	#define IA32_MTRR_FIX4K_E0000 0x26c
975	#define IA32_MTRR_FIX4K_E8000 0x26d
976	#define IA32_MTRR_FIX4K_F0000 0x26e
977	#define IA32_MTRR_FIX4K_F8000 0x26f
978	/** @} */
979
980	/** MTRR Default Range. */
981	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
982
983	#define MSR_IA32_MC0_CTL 0x400
984	#define MSR_IA32_MC0_STATUS 0x401
985
986	/** Basic VMX information. */
987	#define MSR_IA32_VMX_BASIC_INFO 0x480
988	/** Allowed settings for pin-based VM execution controls */
989	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
990	/** Allowed settings for proc-based VM execution controls */
991	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
992	/** Allowed settings for the VMX exit controls. */
993	#define MSR_IA32_VMX_EXIT_CTLS 0x483
994	/** Allowed settings for the VMX entry controls. */
995	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
996	/** Misc VMX info. */
997	#define MSR_IA32_VMX_MISC 0x485
998	/** Fixed cleared bits in CR0. */
999	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1000	/** Fixed set bits in CR0. */
1001	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1002	/** Fixed cleared bits in CR4. */
1003	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1004	/** Fixed set bits in CR4. */
1005	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1006	/** Information for enumerating fields in the VMCS. */
1007	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1008	/** Allowed settings for secondary proc-based VM execution controls */
1009	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1010	/** EPT capabilities. */
1011	#define MSR_IA32_VMX_EPT_CAPS 0x48C
1012	/** DS Save Area (R/W). */
1013	#define MSR_IA32_DS_AREA 0x600
1014	/** X2APIC MSR ranges. */
1015	#define MSR_IA32_APIC_START 0x800
1016	#define MSR_IA32_APIC_END 0x900
1017
1018	/** K6 EFER - Extended Feature Enable Register. */
1019	#define MSR_K6_EFER 0xc0000080
1020	/** @todo document EFER */
1021	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1022	#define MSR_K6_EFER_SCE RT_BIT(0)
1023	/** Bit 8 - LME - Long mode enabled. (R/W) */
1024	#define MSR_K6_EFER_LME RT_BIT(8)
1025	/** Bit 10 - LMA - Long mode active. (R) */
1026	#define MSR_K6_EFER_LMA RT_BIT(10)
1027	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1028	#define MSR_K6_EFER_NXE RT_BIT(11)
1029	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1030	#define MSR_K6_EFER_SVME RT_BIT(12)
1031	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1032	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1033	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1034	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1035	/** K6 STAR - SYSCALL/RET targets. */
1036	#define MSR_K6_STAR 0xc0000081
1037	/** Shift value for getting the SYSRET CS and SS value. */
1038	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1039	/** Shift value for getting the SYSCALL CS and SS value. */
1040	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1041	/** Selector mask for use after shifting. */
1042	#define MSR_K6_STAR_SEL_MASK 0xffff
1043	/** The mask which give the SYSCALL EIP. */
1044	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1045	/** K6 WHCR - Write Handling Control Register. */
1046	#define MSR_K6_WHCR 0xc0000082
1047	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1048	#define MSR_K6_UWCCR 0xc0000085
1049	/** K6 PSOR - Processor State Observability Register. */
1050	#define MSR_K6_PSOR 0xc0000087
1051	/** K6 PFIR - Page Flush/Invalidate Register. */
1052	#define MSR_K6_PFIR 0xc0000088
1053
1054	/** Performance counter MSRs. (AMD only) */
1055	#define MSR_K7_EVNTSEL0 0xc0010000
1056	#define MSR_K7_EVNTSEL1 0xc0010001
1057	#define MSR_K7_EVNTSEL2 0xc0010002
1058	#define MSR_K7_EVNTSEL3 0xc0010003
1059	#define MSR_K7_PERFCTR0 0xc0010004
1060	#define MSR_K7_PERFCTR1 0xc0010005
1061	#define MSR_K7_PERFCTR2 0xc0010006
1062	#define MSR_K7_PERFCTR3 0xc0010007
1063
1064	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1065	#define MSR_K8_LSTAR 0xc0000082
1066	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1067	#define MSR_K8_CSTAR 0xc0000083
1068	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1069	#define MSR_K8_SF_MASK 0xc0000084
1070	/** K8 FS.base - The 64-bit base FS register. */
1071	#define MSR_K8_FS_BASE 0xc0000100
1072	/** K8 GS.base - The 64-bit base GS register. */
1073	#define MSR_K8_GS_BASE 0xc0000101
1074	/** K8 KernelGSbase - Used with SWAPGS. */
1075	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1076	#define MSR_K8_TSC_AUX 0xc0000103
1077	#define MSR_K8_SYSCFG 0xc0010010
1078	#define MSR_K8_HWCR 0xc0010015
1079	#define MSR_K8_IORRBASE0 0xc0010016
1080	#define MSR_K8_IORRMASK0 0xc0010017
1081	#define MSR_K8_IORRBASE1 0xc0010018
1082	#define MSR_K8_IORRMASK1 0xc0010019
1083	#define MSR_K8_TOP_MEM1 0xc001001a
1084	#define MSR_K8_TOP_MEM2 0xc001001d
1085	#define MSR_K8_VM_CR 0xc0010114
1086	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1087
1088	#define MSR_K8_IGNNE 0xc0010115
1089	#define MSR_K8_SMM_CTL 0xc0010116
1090	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1091	* host state during world switch.
1092	*/
1093	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1094
1095	/** @} */
1096
1097
1098	/** @name Page Table / Directory / Directory Pointers / L4.
1099	* @{
1100	*/
1101
1102	/** Page table/directory entry as an unsigned integer. */
1103	typedef uint32_t X86PGUINT;
1104	/** Pointer to a page table/directory table entry as an unsigned integer. */
1105	typedef X86PGUINT *PX86PGUINT;
1106	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1107	typedef X86PGUINT const *PCX86PGUINT;
1108
1109	/** Number of entries in a 32-bit PT/PD. */
1110	#define X86_PG_ENTRIES 1024
1111
1112
1113	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1114	typedef uint64_t X86PGPAEUINT;
1115	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1116	typedef X86PGPAEUINT *PX86PGPAEUINT;
1117	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1118	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1119
1120	/** Number of entries in a PAE PT/PD. */
1121	#define X86_PG_PAE_ENTRIES 512
1122	/** Number of entries in a PAE PDPT. */
1123	#define X86_PG_PAE_PDPE_ENTRIES 4
1124
1125	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1126	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1127	/** Number of entries in an AMD64 PDPT.
1128	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1129	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1130
1131	/** The size of a 4KB page. */
1132	#define X86_PAGE_4K_SIZE _4K
1133	/** The page shift of a 4KB page. */
1134	#define X86_PAGE_4K_SHIFT 12
1135	/** The 4KB page offset mask. */
1136	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1137	/** The 4KB page base mask for virtual addresses. */
1138	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1139	/** The 4KB page base mask for virtual addresses - 32bit version. */
1140	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1141
1142	/** The size of a 2MB page. */
1143	#define X86_PAGE_2M_SIZE _2M
1144	/** The page shift of a 2MB page. */
1145	#define X86_PAGE_2M_SHIFT 21
1146	/** The 2MB page offset mask. */
1147	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1148	/** The 2MB page base mask for virtual addresses. */
1149	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1150	/** The 2MB page base mask for virtual addresses - 32bit version. */
1151	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1152
1153	/** The size of a 4MB page. */
1154	#define X86_PAGE_4M_SIZE _4M
1155	/** The page shift of a 4MB page. */
1156	#define X86_PAGE_4M_SHIFT 22
1157	/** The 4MB page offset mask. */
1158	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1159	/** The 4MB page base mask for virtual addresses. */
1160	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1161	/** The 4MB page base mask for virtual addresses - 32bit version. */
1162	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1163
1164
1165
1166	/** @name Page Table Entry
1167	* @{
1168	*/
1169	/** Bit 0 - P - Present bit. */
1170	#define X86_PTE_BIT_P 0
1171	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1172	#define X86_PTE_BIT_RW 1
1173	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1174	#define X86_PTE_BIT_US 2
1175	/** Bit 3 - PWT - Page level write thru bit. */
1176	#define X86_PTE_BIT_PWT 3
1177	/** Bit 4 - PCD - Page level cache disable bit. */
1178	#define X86_PTE_BIT_PCD 4
1179	/** Bit 5 - A - Access bit. */
1180	#define X86_PTE_BIT_A 5
1181	/** Bit 6 - D - Dirty bit. */
1182	#define X86_PTE_BIT_D 6
1183	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1184	#define X86_PTE_BIT_PAT 7
1185	/** Bit 8 - G - Global flag. */
1186	#define X86_PTE_BIT_G 8
1187
1188	/** Bit 0 - P - Present bit mask. */
1189	#define X86_PTE_P RT_BIT(0)
1190	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1191	#define X86_PTE_RW RT_BIT(1)
1192	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1193	#define X86_PTE_US RT_BIT(2)
1194	/** Bit 3 - PWT - Page level write thru bit mask. */
1195	#define X86_PTE_PWT RT_BIT(3)
1196	/** Bit 4 - PCD - Page level cache disable bit mask. */
1197	#define X86_PTE_PCD RT_BIT(4)
1198	/** Bit 5 - A - Access bit mask. */
1199	#define X86_PTE_A RT_BIT(5)
1200	/** Bit 6 - D - Dirty bit mask. */
1201	#define X86_PTE_D RT_BIT(6)
1202	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1203	#define X86_PTE_PAT RT_BIT(7)
1204	/** Bit 8 - G - Global bit mask. */
1205	#define X86_PTE_G RT_BIT(8)
1206
1207	/** Bits 9-11 - - Available for use to system software. */
1208	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1209	/** Bits 12-31 - - Physical Page number of the next level. */
1210	#define X86_PTE_PG_MASK ( 0xfffff000 )
1211
1212	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1213	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1214	/** Bits 63 - NX - PAE/LM - No execution flag. */
1215	#define X86_PTE_PAE_NX RT_BIT_64(63)
1216	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1217	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1218	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1219	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1220	/** No bits - - LM - MBZ bits when NX is active. */
1221	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1222	/** Bits 63 - - LM - MBZ bits when no NX. */
1223	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1224
1225	/**
1226	* Page table entry.
1227	*/
1228	typedef struct X86PTEBITS
1229	{
1230	/** Flags whether(=1) or not the page is present. */
1231	unsigned u1Present : 1;
1232	/** Read(=0) / Write(=1) flag. */
1233	unsigned u1Write : 1;
1234	/** User(=1) / Supervisor (=0) flag. */
1235	unsigned u1User : 1;
1236	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1237	unsigned u1WriteThru : 1;
1238	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1239	unsigned u1CacheDisable : 1;
1240	/** Accessed flag.
1241	* Indicates that the page have been read or written to. */
1242	unsigned u1Accessed : 1;
1243	/** Dirty flag.
1244	* Indicates that the page has been written to. */
1245	unsigned u1Dirty : 1;
1246	/** Reserved / If PAT enabled, bit 2 of the index. */
1247	unsigned u1PAT : 1;
1248	/** Global flag. (Ignored in all but final level.) */
1249	unsigned u1Global : 1;
1250	/** Available for use to system software. */
1251	unsigned u3Available : 3;
1252	/** Physical Page number of the next level. */
1253	unsigned u20PageNo : 20;
1254	} X86PTEBITS;
1255	/** Pointer to a page table entry. */
1256	typedef X86PTEBITS *PX86PTEBITS;
1257	/** Pointer to a const page table entry. */
1258	typedef const X86PTEBITS *PCX86PTEBITS;
1259
1260	/**
1261	* Page table entry.
1262	*/
1263	typedef union X86PTE
1264	{
1265	/** Unsigned integer view */
1266	X86PGUINT u;
1267	/** Bit field view. */
1268	X86PTEBITS n;
1269	/** 32-bit view. */
1270	uint32_t au32[1];
1271	/** 16-bit view. */
1272	uint16_t au16[2];
1273	/** 8-bit view. */
1274	uint8_t au8[4];
1275	} X86PTE;
1276	/** Pointer to a page table entry. */
1277	typedef X86PTE *PX86PTE;
1278	/** Pointer to a const page table entry. */
1279	typedef const X86PTE *PCX86PTE;
1280
1281
1282	/**
1283	* PAE page table entry.
1284	*/
1285	typedef struct X86PTEPAEBITS
1286	{
1287	/** Flags whether(=1) or not the page is present. */
1288	uint32_t u1Present : 1;
1289	/** Read(=0) / Write(=1) flag. */
1290	uint32_t u1Write : 1;
1291	/** User(=1) / Supervisor(=0) flag. */
1292	uint32_t u1User : 1;
1293	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1294	uint32_t u1WriteThru : 1;
1295	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1296	uint32_t u1CacheDisable : 1;
1297	/** Accessed flag.
1298	* Indicates that the page have been read or written to. */
1299	uint32_t u1Accessed : 1;
1300	/** Dirty flag.
1301	* Indicates that the page has been written to. */
1302	uint32_t u1Dirty : 1;
1303	/** Reserved / If PAT enabled, bit 2 of the index. */
1304	uint32_t u1PAT : 1;
1305	/** Global flag. (Ignored in all but final level.) */
1306	uint32_t u1Global : 1;
1307	/** Available for use to system software. */
1308	uint32_t u3Available : 3;
1309	/** Physical Page number of the next level - Low Part. Don't use this. */
1310	uint32_t u20PageNoLow : 20;
1311	/** Physical Page number of the next level - High Part. Don't use this. */
1312	uint32_t u20PageNoHigh : 20;
1313	/** MBZ bits */
1314	uint32_t u11Reserved : 11;
1315	/** No Execute flag. */
1316	uint32_t u1NoExecute : 1;
1317	} X86PTEPAEBITS;
1318	/** Pointer to a page table entry. */
1319	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1320	/** Pointer to a page table entry. */
1321	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1322
1323	/**
1324	* PAE Page table entry.
1325	*/
1326	typedef union X86PTEPAE
1327	{
1328	/** Unsigned integer view */
1329	X86PGPAEUINT u;
1330	/** Bit field view. */
1331	X86PTEPAEBITS n;
1332	/** 32-bit view. */
1333	uint32_t au32[2];
1334	/** 16-bit view. */
1335	uint16_t au16[4];
1336	/** 8-bit view. */
1337	uint8_t au8[8];
1338	} X86PTEPAE;
1339	/** Pointer to a PAE page table entry. */
1340	typedef X86PTEPAE *PX86PTEPAE;
1341	/** Pointer to a const PAE page table entry. */
1342	typedef const X86PTEPAE *PCX86PTEPAE;
1343	/** @} */
1344
1345	/**
1346	* Page table.
1347	*/
1348	typedef struct X86PT
1349	{
1350	/** PTE Array. */
1351	X86PTE a[X86_PG_ENTRIES];
1352	} X86PT;
1353	/** Pointer to a page table. */
1354	typedef X86PT *PX86PT;
1355	/** Pointer to a const page table. */
1356	typedef const X86PT *PCX86PT;
1357
1358	/** The page shift to get the PT index. */
1359	#define X86_PT_SHIFT 12
1360	/** The PT index mask (apply to a shifted page address). */
1361	#define X86_PT_MASK 0x3ff
1362
1363
1364	/**
1365	* Page directory.
1366	*/
1367	typedef struct X86PTPAE
1368	{
1369	/** PTE Array. */
1370	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1371	} X86PTPAE;
1372	/** Pointer to a page table. */
1373	typedef X86PTPAE *PX86PTPAE;
1374	/** Pointer to a const page table. */
1375	typedef const X86PTPAE *PCX86PTPAE;
1376
1377	/** The page shift to get the PA PTE index. */
1378	#define X86_PT_PAE_SHIFT 12
1379	/** The PAE PT index mask (apply to a shifted page address). */
1380	#define X86_PT_PAE_MASK 0x1ff
1381
1382
1383	/** @name 4KB Page Directory Entry
1384	* @{
1385	*/
1386	/** Bit 0 - P - Present bit. */
1387	#define X86_PDE_P RT_BIT(0)
1388	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1389	#define X86_PDE_RW RT_BIT(1)
1390	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1391	#define X86_PDE_US RT_BIT(2)
1392	/** Bit 3 - PWT - Page level write thru bit. */
1393	#define X86_PDE_PWT RT_BIT(3)
1394	/** Bit 4 - PCD - Page level cache disable bit. */
1395	#define X86_PDE_PCD RT_BIT(4)
1396	/** Bit 5 - A - Access bit. */
1397	#define X86_PDE_A RT_BIT(5)
1398	/** Bit 7 - PS - Page size attribute.
1399	* Clear mean 4KB pages, set means large pages (2/4MB). */
1400	#define X86_PDE_PS RT_BIT(7)
1401	/** Bits 9-11 - - Available for use to system software. */
1402	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1403	/** Bits 12-31 - - Physical Page number of the next level. */
1404	#define X86_PDE_PG_MASK ( 0xfffff000 )
1405
1406	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1407	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1408	/** Bits 63 - NX - PAE/LM - No execution flag. */
1409	#define X86_PDE_PAE_NX RT_BIT_64(63)
1410	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1411	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1412	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1413	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1414	/** Bit 7 - - LM - MBZ bits when NX is active. */
1415	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1416	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1417	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1418
1419	/**
1420	* Page directory entry.
1421	*/
1422	typedef struct X86PDEBITS
1423	{
1424	/** Flags whether(=1) or not the page is present. */
1425	unsigned u1Present : 1;
1426	/** Read(=0) / Write(=1) flag. */
1427	unsigned u1Write : 1;
1428	/** User(=1) / Supervisor (=0) flag. */
1429	unsigned u1User : 1;
1430	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1431	unsigned u1WriteThru : 1;
1432	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1433	unsigned u1CacheDisable : 1;
1434	/** Accessed flag.
1435	* Indicates that the page has been read or written to. */
1436	unsigned u1Accessed : 1;
1437	/** Reserved / Ignored (dirty bit). */
1438	unsigned u1Reserved0 : 1;
1439	/** Size bit if PSE is enabled - in any event it's 0. */
1440	unsigned u1Size : 1;
1441	/** Reserved / Ignored (global bit). */
1442	unsigned u1Reserved1 : 1;
1443	/** Available for use to system software. */
1444	unsigned u3Available : 3;
1445	/** Physical Page number of the next level. */
1446	unsigned u20PageNo : 20;
1447	} X86PDEBITS;
1448	/** Pointer to a page directory entry. */
1449	typedef X86PDEBITS *PX86PDEBITS;
1450	/** Pointer to a const page directory entry. */
1451	typedef const X86PDEBITS *PCX86PDEBITS;
1452
1453
1454	/**
1455	* PAE page directory entry.
1456	*/
1457	typedef struct X86PDEPAEBITS
1458	{
1459	/** Flags whether(=1) or not the page is present. */
1460	uint32_t u1Present : 1;
1461	/** Read(=0) / Write(=1) flag. */
1462	uint32_t u1Write : 1;
1463	/** User(=1) / Supervisor (=0) flag. */
1464	uint32_t u1User : 1;
1465	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1466	uint32_t u1WriteThru : 1;
1467	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1468	uint32_t u1CacheDisable : 1;
1469	/** Accessed flag.
1470	* Indicates that the page has been read or written to. */
1471	uint32_t u1Accessed : 1;
1472	/** Reserved / Ignored (dirty bit). */
1473	uint32_t u1Reserved0 : 1;
1474	/** Size bit if PSE is enabled - in any event it's 0. */
1475	uint32_t u1Size : 1;
1476	/** Reserved / Ignored (global bit). / */
1477	uint32_t u1Reserved1 : 1;
1478	/** Available for use to system software. */
1479	uint32_t u3Available : 3;
1480	/** Physical Page number of the next level - Low Part. Don't use! */
1481	uint32_t u20PageNoLow : 20;
1482	/** Physical Page number of the next level - High Part. Don't use! */
1483	uint32_t u20PageNoHigh : 20;
1484	/** MBZ bits */
1485	uint32_t u11Reserved : 11;
1486	/** No Execute flag. */
1487	uint32_t u1NoExecute : 1;
1488	} X86PDEPAEBITS;
1489	/** Pointer to a page directory entry. */
1490	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1491	/** Pointer to a const page directory entry. */
1492	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1493
1494	/** @} */
1495
1496
1497	/** @name 2/4MB Page Directory Entry
1498	* @{
1499	*/
1500	/** Bit 0 - P - Present bit. */
1501	#define X86_PDE4M_P RT_BIT(0)
1502	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1503	#define X86_PDE4M_RW RT_BIT(1)
1504	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1505	#define X86_PDE4M_US RT_BIT(2)
1506	/** Bit 3 - PWT - Page level write thru bit. */
1507	#define X86_PDE4M_PWT RT_BIT(3)
1508	/** Bit 4 - PCD - Page level cache disable bit. */
1509	#define X86_PDE4M_PCD RT_BIT(4)
1510	/** Bit 5 - A - Access bit. */
1511	#define X86_PDE4M_A RT_BIT(5)
1512	/** Bit 6 - D - Dirty bit. */
1513	#define X86_PDE4M_D RT_BIT(6)
1514	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1515	#define X86_PDE4M_PS RT_BIT(7)
1516	/** Bit 8 - G - Global flag. */
1517	#define X86_PDE4M_G RT_BIT(8)
1518	/** Bits 9-11 - AVL - Available for use to system software. */
1519	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1520	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1521	#define X86_PDE4M_PAT RT_BIT(12)
1522	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1523	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1524	/** Bits 22-31 - - Physical Page number. */
1525	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1526	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1527	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1528	/** The number of bits to the high part of the page number. */
1529	#define X86_PDE4M_PG_HIGH_SHIFT 19
1530	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1531	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1532
1533	/** Bits 21-51 - - PAE/LM - Physical Page number.
1534	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1535	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1536	/** Bits 63 - NX - PAE/LM - No execution flag. */
1537	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1538	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1539	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1540	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1541	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1542	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1543	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1544	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1545	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1546
1547	/**
1548	* 4MB page directory entry.
1549	*/
1550	typedef struct X86PDE4MBITS
1551	{
1552	/** Flags whether(=1) or not the page is present. */
1553	unsigned u1Present : 1;
1554	/** Read(=0) / Write(=1) flag. */
1555	unsigned u1Write : 1;
1556	/** User(=1) / Supervisor (=0) flag. */
1557	unsigned u1User : 1;
1558	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1559	unsigned u1WriteThru : 1;
1560	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1561	unsigned u1CacheDisable : 1;
1562	/** Accessed flag.
1563	* Indicates that the page have been read or written to. */
1564	unsigned u1Accessed : 1;
1565	/** Dirty flag.
1566	* Indicates that the page has been written to. */
1567	unsigned u1Dirty : 1;
1568	/** Page size flag - always 1 for 4MB entries. */
1569	unsigned u1Size : 1;
1570	/** Global flag. */
1571	unsigned u1Global : 1;
1572	/** Available for use to system software. */
1573	unsigned u3Available : 3;
1574	/** Reserved / If PAT enabled, bit 2 of the index. */
1575	unsigned u1PAT : 1;
1576	/** Bits 32-39 of the page number on AMD64.
1577	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1578	unsigned u8PageNoHigh : 8;
1579	/** Reserved. */
1580	unsigned u1Reserved : 1;
1581	/** Physical Page number of the page. */
1582	unsigned u10PageNo : 10;
1583	} X86PDE4MBITS;
1584	/** Pointer to a page table entry. */
1585	typedef X86PDE4MBITS *PX86PDE4MBITS;
1586	/** Pointer to a const page table entry. */
1587	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1588
1589
1590	/**
1591	* 2MB PAE page directory entry.
1592	*/
1593	typedef struct X86PDE2MPAEBITS
1594	{
1595	/** Flags whether(=1) or not the page is present. */
1596	uint32_t u1Present : 1;
1597	/** Read(=0) / Write(=1) flag. */
1598	uint32_t u1Write : 1;
1599	/** User(=1) / Supervisor(=0) flag. */
1600	uint32_t u1User : 1;
1601	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1602	uint32_t u1WriteThru : 1;
1603	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1604	uint32_t u1CacheDisable : 1;
1605	/** Accessed flag.
1606	* Indicates that the page have been read or written to. */
1607	uint32_t u1Accessed : 1;
1608	/** Dirty flag.
1609	* Indicates that the page has been written to. */
1610	uint32_t u1Dirty : 1;
1611	/** Page size flag - always 1 for 2MB entries. */
1612	uint32_t u1Size : 1;
1613	/** Global flag. */
1614	uint32_t u1Global : 1;
1615	/** Available for use to system software. */
1616	uint32_t u3Available : 3;
1617	/** Reserved / If PAT enabled, bit 2 of the index. */
1618	uint32_t u1PAT : 1;
1619	/** Reserved. */
1620	uint32_t u9Reserved : 9;
1621	/** Physical Page number of the next level - Low part. Don't use! */
1622	uint32_t u10PageNoLow : 10;
1623	/** Physical Page number of the next level - High part. Don't use! */
1624	uint32_t u20PageNoHigh : 20;
1625	/** MBZ bits */
1626	uint32_t u11Reserved : 11;
1627	/** No Execute flag. */
1628	uint32_t u1NoExecute : 1;
1629	} X86PDE2MPAEBITS;
1630	/** Pointer to a 2MB PAE page table entry. */
1631	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1632	/** Pointer to a 2MB PAE page table entry. */
1633	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1634
1635	/** @} */
1636
1637	/**
1638	* Page directory entry.
1639	*/
1640	typedef union X86PDE
1641	{
1642	/** Unsigned integer view. */
1643	X86PGUINT u;
1644	/** Normal view. */
1645	X86PDEBITS n;
1646	/** 4MB view (big). */
1647	X86PDE4MBITS b;
1648	/** 8 bit unsigned integer view. */
1649	uint8_t au8[4];
1650	/** 16 bit unsigned integer view. */
1651	uint16_t au16[2];
1652	/** 32 bit unsigned integer view. */
1653	uint32_t au32[1];
1654	} X86PDE;
1655	/** Pointer to a page directory entry. */
1656	typedef X86PDE *PX86PDE;
1657	/** Pointer to a const page directory entry. */
1658	typedef const X86PDE *PCX86PDE;
1659
1660	/**
1661	* PAE page directory entry.
1662	*/
1663	typedef union X86PDEPAE
1664	{
1665	/** Unsigned integer view. */
1666	X86PGPAEUINT u;
1667	/** Normal view. */
1668	X86PDEPAEBITS n;
1669	/** 2MB page view (big). */
1670	X86PDE2MPAEBITS b;
1671	/** 8 bit unsigned integer view. */
1672	uint8_t au8[8];
1673	/** 16 bit unsigned integer view. */
1674	uint16_t au16[4];
1675	/** 32 bit unsigned integer view. */
1676	uint32_t au32[2];
1677	} X86PDEPAE;
1678	/** Pointer to a page directory entry. */
1679	typedef X86PDEPAE *PX86PDEPAE;
1680	/** Pointer to a const page directory entry. */
1681	typedef const X86PDEPAE *PCX86PDEPAE;
1682
1683	/**
1684	* Page directory.
1685	*/
1686	typedef struct X86PD
1687	{
1688	/** PDE Array. */
1689	X86PDE a[X86_PG_ENTRIES];
1690	} X86PD;
1691	/** Pointer to a page directory. */
1692	typedef X86PD *PX86PD;
1693	/** Pointer to a const page directory. */
1694	typedef const X86PD *PCX86PD;
1695
1696	/** The page shift to get the PD index. */
1697	#define X86_PD_SHIFT 22
1698	/** The PD index mask (apply to a shifted page address). */
1699	#define X86_PD_MASK 0x3ff
1700
1701
1702	/**
1703	* PAE page directory.
1704	*/
1705	typedef struct X86PDPAE
1706	{
1707	/** PDE Array. */
1708	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1709	} X86PDPAE;
1710	/** Pointer to a PAE page directory. */
1711	typedef X86PDPAE *PX86PDPAE;
1712	/** Pointer to a const PAE page directory. */
1713	typedef const X86PDPAE *PCX86PDPAE;
1714
1715	/** The page shift to get the PAE PD index. */
1716	#define X86_PD_PAE_SHIFT 21
1717	/** The PAE PD index mask (apply to a shifted page address). */
1718	#define X86_PD_PAE_MASK 0x1ff
1719
1720
1721	/** @name Page Directory Pointer Table Entry (PAE)
1722	* @{
1723	*/
1724	/** Bit 0 - P - Present bit. */
1725	#define X86_PDPE_P RT_BIT(0)
1726	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1727	#define X86_PDPE_RW RT_BIT(1)
1728	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1729	#define X86_PDPE_US RT_BIT(2)
1730	/** Bit 3 - PWT - Page level write thru bit. */
1731	#define X86_PDPE_PWT RT_BIT(3)
1732	/** Bit 4 - PCD - Page level cache disable bit. */
1733	#define X86_PDPE_PCD RT_BIT(4)
1734	/** Bit 5 - A - Access bit. Long Mode only. */
1735	#define X86_PDPE_A RT_BIT(5)
1736	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1737	#define X86_PDPE_LM_PS RT_BIT(7)
1738	/** Bits 9-11 - - Available for use to system software. */
1739	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1740	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1741	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1742	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1743	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1744	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1745	#define X86_PDPE_LM_NX RT_BIT_64(63)
1746	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1747	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1748	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1749	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1750	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1751	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1752	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1753	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1754
1755
1756	/**
1757	* Page directory pointer table entry.
1758	*/
1759	typedef struct X86PDPEBITS
1760	{
1761	/** Flags whether(=1) or not the page is present. */
1762	uint32_t u1Present : 1;
1763	/** Chunk of reserved bits. */
1764	uint32_t u2Reserved : 2;
1765	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1766	uint32_t u1WriteThru : 1;
1767	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1768	uint32_t u1CacheDisable : 1;
1769	/** Chunk of reserved bits. */
1770	uint32_t u4Reserved : 4;
1771	/** Available for use to system software. */
1772	uint32_t u3Available : 3;
1773	/** Physical Page number of the next level - Low Part. Don't use! */
1774	uint32_t u20PageNoLow : 20;
1775	/** Physical Page number of the next level - High Part. Don't use! */
1776	uint32_t u20PageNoHigh : 20;
1777	/** MBZ bits */
1778	uint32_t u12Reserved : 12;
1779	} X86PDPEBITS;
1780	/** Pointer to a page directory pointer table entry. */
1781	typedef X86PDPEBITS *PX86PTPEBITS;
1782	/** Pointer to a const page directory pointer table entry. */
1783	typedef const X86PDPEBITS *PCX86PTPEBITS;
1784
1785	/**
1786	* Page directory pointer table entry. AMD64 version
1787	*/
1788	typedef struct X86PDPEAMD64BITS
1789	{
1790	/** Flags whether(=1) or not the page is present. */
1791	uint32_t u1Present : 1;
1792	/** Read(=0) / Write(=1) flag. */
1793	uint32_t u1Write : 1;
1794	/** User(=1) / Supervisor (=0) flag. */
1795	uint32_t u1User : 1;
1796	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1797	uint32_t u1WriteThru : 1;
1798	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1799	uint32_t u1CacheDisable : 1;
1800	/** Accessed flag.
1801	* Indicates that the page have been read or written to. */
1802	uint32_t u1Accessed : 1;
1803	/** Chunk of reserved bits. */
1804	uint32_t u3Reserved : 3;
1805	/** Available for use to system software. */
1806	uint32_t u3Available : 3;
1807	/** Physical Page number of the next level - Low Part. Don't use! */
1808	uint32_t u20PageNoLow : 20;
1809	/** Physical Page number of the next level - High Part. Don't use! */
1810	uint32_t u20PageNoHigh : 20;
1811	/** MBZ bits */
1812	uint32_t u11Reserved : 11;
1813	/** No Execute flag. */
1814	uint32_t u1NoExecute : 1;
1815	} X86PDPEAMD64BITS;
1816	/** Pointer to a page directory pointer table entry. */
1817	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1818	/** Pointer to a const page directory pointer table entry. */
1819	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1820
1821	/**
1822	* Page directory pointer table entry.
1823	*/
1824	typedef union X86PDPE
1825	{
1826	/** Unsigned integer view. */
1827	X86PGPAEUINT u;
1828	/** Normal view. */
1829	X86PDPEBITS n;
1830	/** AMD64 view. */
1831	X86PDPEAMD64BITS lm;
1832	/** 8 bit unsigned integer view. */
1833	uint8_t au8[8];
1834	/** 16 bit unsigned integer view. */
1835	uint16_t au16[4];
1836	/** 32 bit unsigned integer view. */
1837	uint32_t au32[2];
1838	} X86PDPE;
1839	/** Pointer to a page directory pointer table entry. */
1840	typedef X86PDPE *PX86PDPE;
1841	/** Pointer to a const page directory pointer table entry. */
1842	typedef const X86PDPE *PCX86PDPE;
1843
1844
1845	/**
1846	* Page directory pointer table.
1847	*/
1848	typedef struct X86PDPT
1849	{
1850	/** PDE Array. */
1851	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1852	} X86PDPT;
1853	/** Pointer to a page directory pointer table. */
1854	typedef X86PDPT *PX86PDPT;
1855	/** Pointer to a const page directory pointer table. */
1856	typedef const X86PDPT *PCX86PDPT;
1857
1858	/** The page shift to get the PDPT index. */
1859	#define X86_PDPT_SHIFT 30
1860	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1861	#define X86_PDPT_MASK_PAE 0x3
1862	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1863	#define X86_PDPT_MASK_AMD64 0x1ff
1864
1865	/** @} */
1866
1867
1868	/** @name Page Map Level-4 Entry (Long Mode PAE)
1869	* @{
1870	*/
1871	/** Bit 0 - P - Present bit. */
1872	#define X86_PML4E_P RT_BIT(0)
1873	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1874	#define X86_PML4E_RW RT_BIT(1)
1875	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1876	#define X86_PML4E_US RT_BIT(2)
1877	/** Bit 3 - PWT - Page level write thru bit. */
1878	#define X86_PML4E_PWT RT_BIT(3)
1879	/** Bit 4 - PCD - Page level cache disable bit. */
1880	#define X86_PML4E_PCD RT_BIT(4)
1881	/** Bit 5 - A - Access bit. */
1882	#define X86_PML4E_A RT_BIT(5)
1883	/** Bits 9-11 - - Available for use to system software. */
1884	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1885	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1886	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1887	/** Bits 8, 7 - - MBZ bits when NX is active. */
1888	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1889	/** Bits 63, 7 - - MBZ bits when no NX. */
1890	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1891	/** Bits 63 - NX - PAE - No execution flag. */
1892	#define X86_PML4E_NX RT_BIT_64(63)
1893
1894	/**
1895	* Page Map Level-4 Entry
1896	*/
1897	typedef struct X86PML4EBITS
1898	{
1899	/** Flags whether(=1) or not the page is present. */
1900	uint32_t u1Present : 1;
1901	/** Read(=0) / Write(=1) flag. */
1902	uint32_t u1Write : 1;
1903	/** User(=1) / Supervisor (=0) flag. */
1904	uint32_t u1User : 1;
1905	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1906	uint32_t u1WriteThru : 1;
1907	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1908	uint32_t u1CacheDisable : 1;
1909	/** Accessed flag.
1910	* Indicates that the page have been read or written to. */
1911	uint32_t u1Accessed : 1;
1912	/** Chunk of reserved bits. */
1913	uint32_t u3Reserved : 3;
1914	/** Available for use to system software. */
1915	uint32_t u3Available : 3;
1916	/** Physical Page number of the next level - Low Part. Don't use! */
1917	uint32_t u20PageNoLow : 20;
1918	/** Physical Page number of the next level - High Part. Don't use! */
1919	uint32_t u20PageNoHigh : 20;
1920	/** MBZ bits */
1921	uint32_t u11Reserved : 11;
1922	/** No Execute flag. */
1923	uint32_t u1NoExecute : 1;
1924	} X86PML4EBITS;
1925	/** Pointer to a page map level-4 entry. */
1926	typedef X86PML4EBITS *PX86PML4EBITS;
1927	/** Pointer to a const page map level-4 entry. */
1928	typedef const X86PML4EBITS *PCX86PML4EBITS;
1929
1930	/**
1931	* Page Map Level-4 Entry.
1932	*/
1933	typedef union X86PML4E
1934	{
1935	/** Unsigned integer view. */
1936	X86PGPAEUINT u;
1937	/** Normal view. */
1938	X86PML4EBITS n;
1939	/** 8 bit unsigned integer view. */
1940	uint8_t au8[8];
1941	/** 16 bit unsigned integer view. */
1942	uint16_t au16[4];
1943	/** 32 bit unsigned integer view. */
1944	uint32_t au32[2];
1945	} X86PML4E;
1946	/** Pointer to a page map level-4 entry. */
1947	typedef X86PML4E *PX86PML4E;
1948	/** Pointer to a const page map level-4 entry. */
1949	typedef const X86PML4E *PCX86PML4E;
1950
1951
1952	/**
1953	* Page Map Level-4.
1954	*/
1955	typedef struct X86PML4
1956	{
1957	/** PDE Array. */
1958	X86PML4E a[X86_PG_PAE_ENTRIES];
1959	} X86PML4;
1960	/** Pointer to a page map level-4. */
1961	typedef X86PML4 *PX86PML4;
1962	/** Pointer to a const page map level-4. */
1963	typedef const X86PML4 *PCX86PML4;
1964
1965	/** The page shift to get the PML4 index. */
1966	#define X86_PML4_SHIFT 39
1967	/** The PML4 index mask (apply to a shifted page address). */
1968	#define X86_PML4_MASK 0x1ff
1969
1970	/** @} */
1971
1972	/** @} */
1973
1974
1975	/**
1976	* 80-bit MMX/FPU register type.
1977	*/
1978	typedef struct X86FPUMMX
1979	{
1980	uint8_t reg[10];
1981	} X86FPUMMX;
1982	/** Pointer to a 80-bit MMX/FPU register type. */
1983	typedef X86FPUMMX *PX86FPUMMX;
1984	/** Pointer to a const 80-bit MMX/FPU register type. */
1985	typedef const X86FPUMMX *PCX86FPUMMX;
1986
1987	/**
1988	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
1989	* @todo verify this...
1990	*/
1991	#pragma pack(1)
1992	typedef struct X86FPUSTATE
1993	{
1994	/** 0x00 - Control word. */
1995	uint16_t FCW;
1996	/** 0x02 - Alignment word */
1997	uint16_t Dummy1;
1998	/** 0x04 - Status word. */
1999	uint16_t FSW;
2000	/** 0x06 - Alignment word */
2001	uint16_t Dummy2;
2002	/** 0x08 - Tag word */
2003	uint16_t FTW;
2004	/** 0x0a - Alignment word */
2005	uint16_t Dummy3;
2006
2007	/** 0x0c - Instruction pointer. */
2008	uint32_t FPUIP;
2009	/** 0x10 - Code selector. */
2010	uint16_t CS;
2011	/** 0x12 - Opcode. */
2012	uint16_t FOP;
2013	/** 0x14 - FOO. */
2014	uint32_t FPUOO;
2015	/** 0x18 - FOS. */
2016	uint32_t FPUOS;
2017	/** 0x1c */
2018	union
2019	{
2020	/** MMX view. */
2021	uint64_t mmx;
2022	/** FPU view - todo. */
2023	X86FPUMMX fpu;
2024	/** Extended precision floating point view. */
2025	RTFLOAT80U r80;
2026	/** Extended precision floating point view v2. */
2027	RTFLOAT80U2 r80Ex;
2028	/** 8-bit view. */
2029	uint8_t au8[16];
2030	/** 16-bit view. */
2031	uint16_t au16[8];
2032	/** 32-bit view. */
2033	uint32_t au32[4];
2034	/** 64-bit view. */
2035	uint64_t au64[2];
2036	/** 128-bit view. (yeah, very helpful) */
2037	uint128_t au128[1];
2038	} regs[8];
2039	} X86FPUSTATE;
2040	#pragma pack()
2041	/** Pointer to a FPU state. */
2042	typedef X86FPUSTATE *PX86FPUSTATE;
2043	/** Pointer to a const FPU state. */
2044	typedef const X86FPUSTATE *PCX86FPUSTATE;
2045
2046	/**
2047	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2048	*/
2049	#pragma pack(1)
2050	typedef struct X86FXSTATE
2051	{
2052	/** 0x00 - Control word. */
2053	uint16_t FCW;
2054	/** 0x02 - Status word. */
2055	uint16_t FSW;
2056	/** 0x04 - Tag word. (The upper byte is always zero.) */
2057	uint16_t FTW;
2058	/** 0x06 - Opcode. */
2059	uint16_t FOP;
2060	/** 0x08 - Instruction pointer. */
2061	uint32_t FPUIP;
2062	/** 0x0c - Code selector. */
2063	uint16_t CS;
2064	uint16_t Rsrvd1;
2065	/** 0x10 - Data pointer. */
2066	uint32_t FPUDP;
2067	/** 0x14 - Data segment */
2068	uint16_t DS;
2069	/** 0x16 */
2070	uint16_t Rsrvd2;
2071	/** 0x18 */
2072	uint32_t MXCSR;
2073	/** 0x1c */
2074	uint32_t MXCSR_MASK;
2075	/** 0x20 */
2076	union
2077	{
2078	/** MMX view. */
2079	uint64_t mmx;
2080	/** FPU view - todo. */
2081	X86FPUMMX fpu;
2082	/** Extended precision floating point view. */
2083	RTFLOAT80U r80;
2084	/** Extended precision floating point view v2 */
2085	RTFLOAT80U2 r80Ex;
2086	/** 8-bit view. */
2087	uint8_t au8[16];
2088	/** 16-bit view. */
2089	uint16_t au16[8];
2090	/** 32-bit view. */
2091	uint32_t au32[4];
2092	/** 64-bit view. */
2093	uint64_t au64[2];
2094	/** 128-bit view. (yeah, very helpful) */
2095	uint128_t au128[1];
2096	} aRegs[8];
2097	/* - offset 160 - */
2098	union
2099	{
2100	/** XMM Register view . /
2101	uint128_t xmm;
2102	/** 8-bit view. */
2103	uint8_t au8[16];
2104	/** 16-bit view. */
2105	uint16_t au16[8];
2106	/** 32-bit view. */
2107	uint32_t au32[4];
2108	/** 64-bit view. */
2109	uint64_t au64[2];
2110	/** 128-bit view. (yeah, very helpful) */
2111	uint128_t au128[1];
2112	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2113	/* - offset 416 - */
2114	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2115	} X86FXSTATE;
2116	#pragma pack()
2117	/** Pointer to a FPU Extended state. */
2118	typedef X86FXSTATE *PX86FXSTATE;
2119	/** Pointer to a const FPU Extended state. */
2120	typedef const X86FXSTATE *PCX86FXSTATE;
2121
2122	/** @name FPU status word flags.
2123	* @{ */
2124	/** Exception Flag: Invalid operation. */
2125	#define X86_FSW_IE RT_BIT(0)
2126	/** Exception Flag: Denormalized operand. */
2127	#define X86_FSW_DE RT_BIT(1)
2128	/** Exception Flag: Zero divide. */
2129	#define X86_FSW_ZE RT_BIT(2)
2130	/** Exception Flag: Overflow. */
2131	#define X86_FSW_OE RT_BIT(3)
2132	/** Exception Flag: Underflow. */
2133	#define X86_FSW_UE RT_BIT(4)
2134	/** Exception Flag: Precision. */
2135	#define X86_FSW_PE RT_BIT(5)
2136	/** Stack fault. */
2137	#define X86_FSW_SF RT_BIT(6)
2138	/** Error summary status. */
2139	#define X86_FSW_ES RT_BIT(7)
2140	/** Mask of exceptions flags, excluding the summary bit. */
2141	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2142	/** Mask of exceptions flags, including the summary bit. */
2143	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2144	/** Condition code 0. */
2145	#define X86_FSW_C0 RT_BIT(8)
2146	/** Condition code 1. */
2147	#define X86_FSW_C1 RT_BIT(9)
2148	/** Condition code 2. */
2149	#define X86_FSW_C2 RT_BIT(10)
2150	/** Top of the stack mask. */
2151	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2152	/** TOP shift value. */
2153	#define X86_FSW_TOP_SHIFT 11
2154	/** Mask for getting TOP value after shifting it right. */
2155	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2156	/** Get the TOP value. */
2157	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2158	/** Condition code 3. */
2159	#define X86_FSW_C3 RT_BIT(14)
2160	/** Mask of exceptions flags, including the summary bit. */
2161	#define X86_FSW_C_MASK UINT16_C(0x4700)
2162	/** FPU busy. */
2163	#define X86_FSW_B RT_BIT(15)
2164	/** @} */
2165
2166
2167	/** @name FPU control word flags.
2168	* @{ */
2169	/** Exception Mask: Invalid operation. */
2170	#define X86_FCW_IM RT_BIT(0)
2171	/** Exception Mask: Denormalized operand. */
2172	#define X86_FCW_DM RT_BIT(1)
2173	/** Exception Mask: Zero divide. */
2174	#define X86_FCW_ZM RT_BIT(2)
2175	/** Exception Mask: Overflow. */
2176	#define X86_FCW_OM RT_BIT(3)
2177	/** Exception Mask: Underflow. */
2178	#define X86_FCW_UM RT_BIT(4)
2179	/** Exception Mask: Precision. */
2180	#define X86_FCW_PM RT_BIT(5)
2181	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2182	* @remarks This includes reserved bit 6. */
2183	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2184	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2185	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2186	/** Precision control mask. */
2187	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2188	/** Precision control: 24-bit. */
2189	#define X86_FCW_PC_24 UINT16_C(0x0000)
2190	/** Precision control: Reserved. */
2191	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2192	/** Precision control: 53-bit. */
2193	#define X86_FCW_PC_53 UINT16_C(0x0200)
2194	/** Precision control: 64-bit. */
2195	#define X86_FCW_PC_64 UINT16_C(0x0300)
2196	/** Rounding control mask. */
2197	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2198	/** Rounding control: To nearest. */
2199	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2200	/** Rounding control: Down. */
2201	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2202	/** Rounding control: Up. */
2203	#define X86_FCW_RC_UP UINT16_C(0x0800)
2204	/** Rounding control: Towards zero. */
2205	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2206	/** Bits which should be zero, apparently. */
2207	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2208	/** @} */
2209
2210
2211	/** @name Selector Descriptor
2212	* @{
2213	*/
2214
2215	#ifndef VBOX_FOR_DTRACE_LIB
2216	/**
2217	* Descriptor attributes.
2218	*/
2219	typedef struct X86DESCATTRBITS
2220	{
2221	/** 00 - Segment Type. */
2222	unsigned u4Type : 4;
2223	/** 04 - Descriptor Type. System(=0) or code/data selector */
2224	unsigned u1DescType : 1;
2225	/** 05 - Descriptor Privelege level. */
2226	unsigned u2Dpl : 2;
2227	/** 07 - Flags selector present(=1) or not. */
2228	unsigned u1Present : 1;
2229	/** 08 - Segment limit 16-19. */
2230	unsigned u4LimitHigh : 4;
2231	/** 0c - Available for system software. */
2232	unsigned u1Available : 1;
2233	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2234	unsigned u1Long : 1;
2235	/** 0e - This flags meaning depends on the segment type. Try make sense out
2236	* of the intel manual yourself. */
2237	unsigned u1DefBig : 1;
2238	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2239	* clear byte. */
2240	unsigned u1Granularity : 1;
2241	} X86DESCATTRBITS;
2242	#endif /* !VBOX_FOR_DTRACE_LIB */
2243
2244	#pragma pack(1)
2245	typedef union X86DESCATTR
2246	{
2247	/** Unsigned integer view. */
2248	uint32_t u;
2249	#ifndef VBOX_FOR_DTRACE_LIB
2250	/** Normal view. */
2251	X86DESCATTRBITS n;
2252	#endif
2253	} X86DESCATTR;
2254	#pragma pack()
2255	/** Pointer to descriptor attributes. */
2256	typedef X86DESCATTR *PX86DESCATTR;
2257	/** Pointer to const descriptor attributes. */
2258	typedef const X86DESCATTR *PCX86DESCATTR;
2259
2260	#ifndef VBOX_FOR_DTRACE_LIB
2261
2262	/**
2263	* Generic descriptor table entry
2264	*/
2265	#pragma pack(1)
2266	typedef struct X86DESCGENERIC
2267	{
2268	/** Limit - Low word. */
2269	unsigned u16LimitLow : 16;
2270	/** Base address - lowe word.
2271	* Don't try set this to 24 because MSC is doing stupid things then. */
2272	unsigned u16BaseLow : 16;
2273	/** Base address - first 8 bits of high word. */
2274	unsigned u8BaseHigh1 : 8;
2275	/** Segment Type. */
2276	unsigned u4Type : 4;
2277	/** Descriptor Type. System(=0) or code/data selector */
2278	unsigned u1DescType : 1;
2279	/** Descriptor Privelege level. */
2280	unsigned u2Dpl : 2;
2281	/** Flags selector present(=1) or not. */
2282	unsigned u1Present : 1;
2283	/** Segment limit 16-19. */
2284	unsigned u4LimitHigh : 4;
2285	/** Available for system software. */
2286	unsigned u1Available : 1;
2287	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2288	unsigned u1Long : 1;
2289	/** This flags meaning depends on the segment type. Try make sense out
2290	* of the intel manual yourself. */
2291	unsigned u1DefBig : 1;
2292	/** Granularity of the limit. If set 4KB granularity is used, if
2293	* clear byte. */
2294	unsigned u1Granularity : 1;
2295	/** Base address - highest 8 bits. */
2296	unsigned u8BaseHigh2 : 8;
2297	} X86DESCGENERIC;
2298	#pragma pack()
2299	/** Pointer to a generic descriptor entry. */
2300	typedef X86DESCGENERIC *PX86DESCGENERIC;
2301	/** Pointer to a const generic descriptor entry. */
2302	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2303
2304	/**
2305	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2306	*/
2307	typedef struct X86DESCGATE
2308	{
2309	/** 00 - Target code segment offset - Low word.
2310	* Ignored if task-gate. */
2311	unsigned u16OffsetLow : 16;
2312	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2313	* TSS selector if task-gate. */
2314	unsigned u16Sel : 16;
2315	/** 20 - Number of parameters for a call-gate.
2316	* Ignored if interrupt-, trap- or task-gate. */
2317	unsigned u4ParmCount : 4;
2318	/** 24 - Reserved / ignored. */
2319	unsigned u4Reserved : 4;
2320	/** 28 - Segment Type. */
2321	unsigned u4Type : 4;
2322	/** 2c - Descriptor Type (0 = system). */
2323	unsigned u1DescType : 1;
2324	/** 2d - Descriptor Privelege level. */
2325	unsigned u2Dpl : 2;
2326	/** 2f - Flags selector present(=1) or not. */
2327	unsigned u1Present : 1;
2328	/** 30 - Target code segment offset - High word.
2329	* Ignored if task-gate. */
2330	unsigned u16OffsetHigh : 16;
2331	} X86DESCGATE;
2332	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2333	typedef X86DESCGATE *PX86DESCGATE;
2334	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2335	typedef const X86DESCGATE *PCX86DESCGATE;
2336
2337	#endif /* VBOX_FOR_DTRACE_LIB */
2338
2339	/**
2340	* Descriptor table entry.
2341	*/
2342	#pragma pack(1)
2343	typedef union X86DESC
2344	{
2345	#ifndef VBOX_FOR_DTRACE_LIB
2346	/** Generic descriptor view. */
2347	X86DESCGENERIC Gen;
2348	/** Gate descriptor view. */
2349	X86DESCGATE Gate;
2350	#endif
2351
2352	/** 8 bit unsigned integer view. */
2353	uint8_t au8[8];
2354	/** 16 bit unsigned integer view. */
2355	uint16_t au16[4];
2356	/** 32 bit unsigned integer view. */
2357	uint32_t au32[2];
2358	/** 64 bit unsigned integer view. */
2359	uint64_t au64[1];
2360	/** Unsigned integer view. */
2361	uint64_t u;
2362	} X86DESC;
2363	#ifndef VBOX_FOR_DTRACE_LIB
2364	AssertCompileSize(X86DESC, 8);
2365	#endif
2366	#pragma pack()
2367	/** Pointer to descriptor table entry. */
2368	typedef X86DESC *PX86DESC;
2369	/** Pointer to const descriptor table entry. */
2370	typedef const X86DESC *PCX86DESC;
2371
2372	/** @def X86DESC_BASE
2373	* Return the base address of a descriptor.
2374	*/
2375	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2376	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2377	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2378	\| ( (desc).Gen.u16BaseLow ) )
2379
2380	/** @def X86DESC_LIMIT
2381	* Return the limit of a descriptor.
2382	*/
2383	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2384	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2385	\| ( (desc).Gen.u16LimitLow ) )
2386
2387	/** @def X86DESC_GET_HID_ATTR
2388	* Get the descriptor attributes for the hidden register.
2389	*/
2390	#define X86DESC_GET_HID_ATTR(desc) /ASM-NOINC/ \
2391	( (desc.u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2392
2393	#ifndef VBOX_FOR_DTRACE_LIB
2394
2395	/**
2396	* 64 bits generic descriptor table entry
2397	* Note: most of these bits have no meaning in long mode.
2398	*/
2399	#pragma pack(1)
2400	typedef struct X86DESC64GENERIC
2401	{
2402	/** Limit - Low word - IGNORED. */
2403	unsigned u16LimitLow : 16;
2404	/** Base address - low word. - IGNORED
2405	* Don't try set this to 24 because MSC is doing stupid things then. */
2406	unsigned u16BaseLow : 16;
2407	/** Base address - first 8 bits of high word. - IGNORED */
2408	unsigned u8BaseHigh1 : 8;
2409	/** Segment Type. */
2410	unsigned u4Type : 4;
2411	/** Descriptor Type. System(=0) or code/data selector */
2412	unsigned u1DescType : 1;
2413	/** Descriptor Privelege level. */
2414	unsigned u2Dpl : 2;
2415	/** Flags selector present(=1) or not. */
2416	unsigned u1Present : 1;
2417	/** Segment limit 16-19. - IGNORED */
2418	unsigned u4LimitHigh : 4;
2419	/** Available for system software. - IGNORED */
2420	unsigned u1Available : 1;
2421	/** Long mode flag. */
2422	unsigned u1Long : 1;
2423	/** This flags meaning depends on the segment type. Try make sense out
2424	* of the intel manual yourself. */
2425	unsigned u1DefBig : 1;
2426	/** Granularity of the limit. If set 4KB granularity is used, if
2427	* clear byte. - IGNORED */
2428	unsigned u1Granularity : 1;
2429	/** Base address - highest 8 bits. - IGNORED */
2430	unsigned u8BaseHigh2 : 8;
2431	/** Base address - bits 63-32. */
2432	unsigned u32BaseHigh3 : 32;
2433	unsigned u8Reserved : 8;
2434	unsigned u5Zeros : 5;
2435	unsigned u19Reserved : 19;
2436	} X86DESC64GENERIC;
2437	#pragma pack()
2438	/** Pointer to a generic descriptor entry. */
2439	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2440	/** Pointer to a const generic descriptor entry. */
2441	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2442
2443	/**
2444	* System descriptor table entry (64 bits)
2445	*
2446	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2447	*/
2448	#pragma pack(1)
2449	typedef struct X86DESC64SYSTEM
2450	{
2451	/** Limit - Low word. */
2452	unsigned u16LimitLow : 16;
2453	/** Base address - lowe word.
2454	* Don't try set this to 24 because MSC is doing stupid things then. */
2455	unsigned u16BaseLow : 16;
2456	/** Base address - first 8 bits of high word. */
2457	unsigned u8BaseHigh1 : 8;
2458	/** Segment Type. */
2459	unsigned u4Type : 4;
2460	/** Descriptor Type. System(=0) or code/data selector */
2461	unsigned u1DescType : 1;
2462	/** Descriptor Privelege level. */
2463	unsigned u2Dpl : 2;
2464	/** Flags selector present(=1) or not. */
2465	unsigned u1Present : 1;
2466	/** Segment limit 16-19. */
2467	unsigned u4LimitHigh : 4;
2468	/** Available for system software. */
2469	unsigned u1Available : 1;
2470	/** Reserved - 0. */
2471	unsigned u1Reserved : 1;
2472	/** This flags meaning depends on the segment type. Try make sense out
2473	* of the intel manual yourself. */
2474	unsigned u1DefBig : 1;
2475	/** Granularity of the limit. If set 4KB granularity is used, if
2476	* clear byte. */
2477	unsigned u1Granularity : 1;
2478	/** Base address - bits 31-24. */
2479	unsigned u8BaseHigh2 : 8;
2480	/** Base address - bits 63-32. */
2481	unsigned u32BaseHigh3 : 32;
2482	unsigned u8Reserved : 8;
2483	unsigned u5Zeros : 5;
2484	unsigned u19Reserved : 19;
2485	} X86DESC64SYSTEM;
2486	#pragma pack()
2487	/** Pointer to a system descriptor entry. */
2488	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2489	/** Pointer to a const system descriptor entry. */
2490	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2491
2492	/**
2493	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2494	*/
2495	typedef struct X86DESC64GATE
2496	{
2497	/** Target code segment offset - Low word. */
2498	unsigned u16OffsetLow : 16;
2499	/** Target code segment selector. */
2500	unsigned u16Sel : 16;
2501	/** Interrupt stack table for interrupt- and trap-gates.
2502	* Ignored by call-gates. */
2503	unsigned u3IST : 3;
2504	/** Reserved / ignored. */
2505	unsigned u5Reserved : 5;
2506	/** Segment Type. */
2507	unsigned u4Type : 4;
2508	/** Descriptor Type (0 = system). */
2509	unsigned u1DescType : 1;
2510	/** Descriptor Privelege level. */
2511	unsigned u2Dpl : 2;
2512	/** Flags selector present(=1) or not. */
2513	unsigned u1Present : 1;
2514	/** Target code segment offset - High word.
2515	* Ignored if task-gate. */
2516	unsigned u16OffsetHigh : 16;
2517	/** Target code segment offset - Top dword.
2518	* Ignored if task-gate. */
2519	unsigned u32OffsetTop : 32;
2520	/** Reserved / ignored / must be zero.
2521	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2522	unsigned u32Reserved : 32;
2523	} X86DESC64GATE;
2524	AssertCompileSize(X86DESC64GATE, 16);
2525	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2526	typedef X86DESC64GATE *PX86DESC64GATE;
2527	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2528	typedef const X86DESC64GATE *PCX86DESC64GATE;
2529
2530	#endif /* VBOX_FOR_DTRACE_LIB */
2531
2532	/**
2533	* Descriptor table entry.
2534	*/
2535	#pragma pack(1)
2536	typedef union X86DESC64
2537	{
2538	#ifndef VBOX_FOR_DTRACE_LIB
2539	/** Generic descriptor view. */
2540	X86DESC64GENERIC Gen;
2541	/** System descriptor view. */
2542	X86DESC64SYSTEM System;
2543	/** Gate descriptor view. */
2544	X86DESC64GATE Gate;
2545	#endif
2546
2547	/** 8 bit unsigned integer view. */
2548	uint8_t au8[16];
2549	/** 16 bit unsigned integer view. */
2550	uint16_t au16[8];
2551	/** 32 bit unsigned integer view. */
2552	uint32_t au32[4];
2553	/** 64 bit unsigned integer view. */
2554	uint64_t au64[2];
2555	} X86DESC64;
2556	#ifndef VBOX_FOR_DTRACE_LIB
2557	AssertCompileSize(X86DESC64, 16);
2558	#endif
2559	#pragma pack()
2560	/** Pointer to descriptor table entry. */
2561	typedef X86DESC64 *PX86DESC64;
2562	/** Pointer to const descriptor table entry. */
2563	typedef const X86DESC64 *PCX86DESC64;
2564
2565	/** @def X86DESC64_BASE
2566	* Return the base of a 64-bit descriptor.
2567	*/
2568	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2569	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2570	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2571	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2572	\| ( (desc).Gen.u16BaseLow ) )
2573
2574
2575
2576	/** @name Host system descriptor table entry - Use with care!
2577	* @{ */
2578	/** Host system descriptor table entry. */
2579	#if HC_ARCH_BITS == 64
2580	typedef X86DESC64 X86DESCHC;
2581	#else
2582	typedef X86DESC X86DESCHC;
2583	#endif
2584	/** Pointer to a host system descriptor table entry. */
2585	#if HC_ARCH_BITS == 64
2586	typedef PX86DESC64 PX86DESCHC;
2587	#else
2588	typedef PX86DESC PX86DESCHC;
2589	#endif
2590	/** Pointer to a const host system descriptor table entry. */
2591	#if HC_ARCH_BITS == 64
2592	typedef PCX86DESC64 PCX86DESCHC;
2593	#else
2594	typedef PCX86DESC PCX86DESCHC;
2595	#endif
2596	/** @} */
2597
2598
2599	/** @name Selector Descriptor Types.
2600	* @{
2601	*/
2602
2603	/** @name Non-System Selector Types.
2604	* @{ */
2605	/** Code(=set)/Data(=clear) bit. */
2606	#define X86_SEL_TYPE_CODE 8
2607	/** Memory(=set)/System(=clear) bit. */
2608	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2609	/** Accessed bit. */
2610	#define X86_SEL_TYPE_ACCESSED 1
2611	/** Expand down bit (for data selectors only). */
2612	#define X86_SEL_TYPE_DOWN 4
2613	/** Conforming bit (for code selectors only). */
2614	#define X86_SEL_TYPE_CONF 4
2615	/** Write bit (for data selectors only). */
2616	#define X86_SEL_TYPE_WRITE 2
2617	/** Read bit (for code selectors only). */
2618	#define X86_SEL_TYPE_READ 2
2619
2620	/** Read only selector type. */
2621	#define X86_SEL_TYPE_RO 0
2622	/** Accessed read only selector type. */
2623	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2624	/** Read write selector type. */
2625	#define X86_SEL_TYPE_RW 2
2626	/** Accessed read write selector type. */
2627	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2628	/** Expand down read only selector type. */
2629	#define X86_SEL_TYPE_RO_DOWN 4
2630	/** Accessed expand down read only selector type. */
2631	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2632	/** Expand down read write selector type. */
2633	#define X86_SEL_TYPE_RW_DOWN 6
2634	/** Accessed expand down read write selector type. */
2635	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2636	/** Execute only selector type. */
2637	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2638	/** Accessed execute only selector type. */
2639	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2640	/** Execute and read selector type. */
2641	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2642	/** Accessed execute and read selector type. */
2643	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2644	/** Conforming execute only selector type. */
2645	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2646	/** Accessed Conforming execute only selector type. */
2647	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2648	/** Conforming execute and write selector type. */
2649	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2650	/** Accessed Conforming execute and write selector type. */
2651	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2652	/** @} */
2653
2654
2655	/** @name System Selector Types.
2656	* @{ */
2657	/** The TSS busy bit mask. */
2658	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2659
2660	/** Undefined system selector type. */
2661	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2662	/** 286 TSS selector. */
2663	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2664	/** LDT selector. */
2665	#define X86_SEL_TYPE_SYS_LDT 2
2666	/** 286 TSS selector - Busy. */
2667	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2668	/** 286 Callgate selector. */
2669	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2670	/** Taskgate selector. */
2671	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2672	/** 286 Interrupt gate selector. */
2673	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2674	/** 286 Trapgate selector. */
2675	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2676	/** Undefined system selector. */
2677	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2678	/** 386 TSS selector. */
2679	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2680	/** Undefined system selector. */
2681	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2682	/** 386 TSS selector - Busy. */
2683	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2684	/** 386 Callgate selector. */
2685	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2686	/** Undefined system selector. */
2687	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2688	/** 386 Interruptgate selector. */
2689	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2690	/** 386 Trapgate selector. */
2691	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2692	/** @} */
2693
2694	/** @name AMD64 System Selector Types.
2695	* @{ */
2696	/** LDT selector. */
2697	#define AMD64_SEL_TYPE_SYS_LDT 2
2698	/** TSS selector - Busy. */
2699	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2700	/** TSS selector - Busy. */
2701	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2702	/** Callgate selector. */
2703	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2704	/** Interruptgate selector. */
2705	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2706	/** Trapgate selector. */
2707	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2708	/** @} */
2709
2710	/** @} */
2711
2712
2713	/** @name Descriptor Table Entry Flag Masks.
2714	* These are for the 2nd 32-bit word of a descriptor.
2715	* @{ */
2716	/** Bits 8-11 - TYPE - Descriptor type mask. */
2717	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2718	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2719	#define X86_DESC_S RT_BIT(12)
2720	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2721	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2722	/** Bit 15 - P - Present. */
2723	#define X86_DESC_P RT_BIT(15)
2724	/** Bit 20 - AVL - Available for system software. */
2725	#define X86_DESC_AVL RT_BIT(20)
2726	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2727	#define X86_DESC_DB RT_BIT(22)
2728	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2729	* used, if clear byte. */
2730	#define X86_DESC_G RT_BIT(23)
2731	/** @} */
2732
2733	/** @} */
2734
2735
2736	/** @name Task Segments.
2737	* @{
2738	*/
2739
2740	/**
2741	* 16-bit Task Segment (TSS).
2742	*/
2743	#pragma pack(1)
2744	typedef struct X86TSS16
2745	{
2746	/** Back link to previous task. (static) */
2747	RTSEL selPrev;
2748	/** Ring-0 stack pointer. (static) */
2749	uint16_t sp0;
2750	/** Ring-0 stack segment. (static) */
2751	RTSEL ss0;
2752	/** Ring-1 stack pointer. (static) */
2753	uint16_t sp1;
2754	/** Ring-1 stack segment. (static) */
2755	RTSEL ss1;
2756	/** Ring-2 stack pointer. (static) */
2757	uint16_t sp2;
2758	/** Ring-2 stack segment. (static) */
2759	RTSEL ss2;
2760	/** IP before task switch. */
2761	uint16_t ip;
2762	/** FLAGS before task switch. */
2763	uint16_t flags;
2764	/** AX before task switch. */
2765	uint16_t ax;
2766	/** CX before task switch. */
2767	uint16_t cx;
2768	/** DX before task switch. */
2769	uint16_t dx;
2770	/** BX before task switch. */
2771	uint16_t bx;
2772	/** SP before task switch. */
2773	uint16_t sp;
2774	/** BP before task switch. */
2775	uint16_t bp;
2776	/** SI before task switch. */
2777	uint16_t si;
2778	/** DI before task switch. */
2779	uint16_t di;
2780	/** ES before task switch. */
2781	RTSEL es;
2782	/** CS before task switch. */
2783	RTSEL cs;
2784	/** SS before task switch. */
2785	RTSEL ss;
2786	/** DS before task switch. */
2787	RTSEL ds;
2788	/** LDTR before task switch. */
2789	RTSEL selLdt;
2790	} X86TSS16;
2791	#ifndef VBOX_FOR_DTRACE_LIB
2792	AssertCompileSize(X86TSS16, 44);
2793	#endif
2794	#pragma pack()
2795	/** Pointer to a 16-bit task segment. */
2796	typedef X86TSS16 *PX86TSS16;
2797	/** Pointer to a const 16-bit task segment. */
2798	typedef const X86TSS16 *PCX86TSS16;
2799
2800
2801	/**
2802	* 32-bit Task Segment (TSS).
2803	*/
2804	#pragma pack(1)
2805	typedef struct X86TSS32
2806	{
2807	/** Back link to previous task. (static) */
2808	RTSEL selPrev;
2809	uint16_t padding1;
2810	/** Ring-0 stack pointer. (static) */
2811	uint32_t esp0;
2812	/** Ring-0 stack segment. (static) */
2813	RTSEL ss0;
2814	uint16_t padding_ss0;
2815	/** Ring-1 stack pointer. (static) */
2816	uint32_t esp1;
2817	/** Ring-1 stack segment. (static) */
2818	RTSEL ss1;
2819	uint16_t padding_ss1;
2820	/** Ring-2 stack pointer. (static) */
2821	uint32_t esp2;
2822	/** Ring-2 stack segment. (static) */
2823	RTSEL ss2;
2824	uint16_t padding_ss2;
2825	/** Page directory for the task. (static) */
2826	uint32_t cr3;
2827	/** EIP before task switch. */
2828	uint32_t eip;
2829	/** EFLAGS before task switch. */
2830	uint32_t eflags;
2831	/** EAX before task switch. */
2832	uint32_t eax;
2833	/** ECX before task switch. */
2834	uint32_t ecx;
2835	/** EDX before task switch. */
2836	uint32_t edx;
2837	/** EBX before task switch. */
2838	uint32_t ebx;
2839	/** ESP before task switch. */
2840	uint32_t esp;
2841	/** EBP before task switch. */
2842	uint32_t ebp;
2843	/** ESI before task switch. */
2844	uint32_t esi;
2845	/** EDI before task switch. */
2846	uint32_t edi;
2847	/** ES before task switch. */
2848	RTSEL es;
2849	uint16_t padding_es;
2850	/** CS before task switch. */
2851	RTSEL cs;
2852	uint16_t padding_cs;
2853	/** SS before task switch. */
2854	RTSEL ss;
2855	uint16_t padding_ss;
2856	/** DS before task switch. */
2857	RTSEL ds;
2858	uint16_t padding_ds;
2859	/** FS before task switch. */
2860	RTSEL fs;
2861	uint16_t padding_fs;
2862	/** GS before task switch. */
2863	RTSEL gs;
2864	uint16_t padding_gs;
2865	/** LDTR before task switch. */
2866	RTSEL selLdt;
2867	uint16_t padding_ldt;
2868	/** Debug trap flag */
2869	uint16_t fDebugTrap;
2870	/** Offset relative to the TSS of the start of the I/O Bitmap
2871	* and the end of the interrupt redirection bitmap. */
2872	uint16_t offIoBitmap;
2873	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2874	uint8_t IntRedirBitmap[32];
2875	} X86TSS32;
2876	#pragma pack()
2877	/** Pointer to task segment. */
2878	typedef X86TSS32 *PX86TSS32;
2879	/** Pointer to const task segment. */
2880	typedef const X86TSS32 *PCX86TSS32;
2881
2882
2883	/**
2884	* 64-bit Task segment.
2885	*/
2886	#pragma pack(1)
2887	typedef struct X86TSS64
2888	{
2889	/** Reserved. */
2890	uint32_t u32Reserved;
2891	/** Ring-0 stack pointer. (static) */
2892	uint64_t rsp0;
2893	/** Ring-1 stack pointer. (static) */
2894	uint64_t rsp1;
2895	/** Ring-2 stack pointer. (static) */
2896	uint64_t rsp2;
2897	/** Reserved. */
2898	uint32_t u32Reserved2[2];
2899	/* IST */
2900	uint64_t ist1;
2901	uint64_t ist2;
2902	uint64_t ist3;
2903	uint64_t ist4;
2904	uint64_t ist5;
2905	uint64_t ist6;
2906	uint64_t ist7;
2907	/* Reserved. */
2908	uint16_t u16Reserved[5];
2909	/** Offset relative to the TSS of the start of the I/O Bitmap
2910	* and the end of the interrupt redirection bitmap. */
2911	uint16_t offIoBitmap;
2912	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2913	uint8_t IntRedirBitmap[32];
2914	} X86TSS64;
2915	#pragma pack()
2916	/** Pointer to a 64-bit task segment. */
2917	typedef X86TSS64 *PX86TSS64;
2918	/** Pointer to a const 64-bit task segment. */
2919	typedef const X86TSS64 *PCX86TSS64;
2920	#ifndef VBOX_FOR_DTRACE_LIB
2921	AssertCompileSize(X86TSS64, 136);
2922	#endif
2923
2924	/** @} */
2925
2926
2927	/** @name Selectors.
2928	* @{
2929	*/
2930
2931	/**
2932	* The shift used to convert a selector from and to index an index (C).
2933	*/
2934	#define X86_SEL_SHIFT 3
2935
2936	/**
2937	* The mask used to mask off the table indicator and CPL of an selector.
2938	*/
2939	#define X86_SEL_MASK 0xfff8U
2940
2941	/**
2942	* The bit indicating that a selector is in the LDT and not in the GDT.
2943	*/
2944	#define X86_SEL_LDT 0x0004U
2945	/**
2946	* The bit mask for getting the RPL of a selector.
2947	*/
2948	#define X86_SEL_RPL 0x0003U
2949
2950	/** @} */
2951
2952
2953	/**
2954	* x86 Exceptions/Faults/Traps.
2955	*/
2956	typedef enum X86XCPT
2957	{
2958	/** \#DE - Divide error. */
2959	X86_XCPT_DE = 0x00,
2960	/** \#DB - Debug event (single step, DRx, ..) */
2961	X86_XCPT_DB = 0x01,
2962	/** NMI - Non-Maskable Interrupt */
2963	X86_XCPT_NMI = 0x02,
2964	/** \#BP - Breakpoint (INT3). */
2965	X86_XCPT_BP = 0x03,
2966	/** \#OF - Overflow (INTO). */
2967	X86_XCPT_OF = 0x04,
2968	/** \#BR - Bound range exceeded (BOUND). */
2969	X86_XCPT_BR = 0x05,
2970	/** \#UD - Undefined opcode. */
2971	X86_XCPT_UD = 0x06,
2972	/** \#NM - Device not available (math coprocessor device). */
2973	X86_XCPT_NM = 0x07,
2974	/** \#DF - Double fault. */
2975	X86_XCPT_DF = 0x08,
2976	/** ??? - Coprocessor segment overrun (obsolete). */
2977	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2978	/** \#TS - Taskswitch (TSS). */
2979	X86_XCPT_TS = 0x0a,
2980	/** \#NP - Segment no present. */
2981	X86_XCPT_NP = 0x0b,
2982	/** \#SS - Stack segment fault. */
2983	X86_XCPT_SS = 0x0c,
2984	/** \#GP - General protection fault. */
2985	X86_XCPT_GP = 0x0d,
2986	/** \#PF - Page fault. */
2987	X86_XCPT_PF = 0x0e,
2988	/* 0x0f is reserved. */
2989	/** \#MF - Math fault (FPU). */
2990	X86_XCPT_MF = 0x10,
2991	/** \#AC - Alignment check. */
2992	X86_XCPT_AC = 0x11,
2993	/** \#MC - Machine check. */
2994	X86_XCPT_MC = 0x12,
2995	/** \#XF - SIMD Floating-Pointer Exception. */
2996	X86_XCPT_XF = 0x13
2997	} X86XCPT;
2998	/** Pointer to a x86 exception code. */
2999	typedef X86XCPT *PX86XCPT;
3000	/** Pointer to a const x86 exception code. */
3001	typedef const X86XCPT *PCX86XCPT;
3002
3003
3004	/** @name Trap Error Codes
3005	* @{
3006	*/
3007	/** External indicator. */
3008	#define X86_TRAP_ERR_EXTERNAL 1
3009	/** IDT indicator. */
3010	#define X86_TRAP_ERR_IDT 2
3011	/** Descriptor table indicator - If set LDT, if clear GDT. */
3012	#define X86_TRAP_ERR_TI 4
3013	/** Mask for getting the selector. */
3014	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3015	/** Shift for getting the selector table index (C type index). */
3016	#define X86_TRAP_ERR_SEL_SHIFT 3
3017	/** @} */
3018
3019
3020	/** @name \#PF Trap Error Codes
3021	* @{
3022	*/
3023	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3024	#define X86_TRAP_PF_P RT_BIT(0)
3025	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3026	#define X86_TRAP_PF_RW RT_BIT(1)
3027	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3028	#define X86_TRAP_PF_US RT_BIT(2)
3029	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3030	#define X86_TRAP_PF_RSVD RT_BIT(3)
3031	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3032	#define X86_TRAP_PF_ID RT_BIT(4)
3033	/** @} */
3034
3035	#pragma pack(1)
3036	/**
3037	* 32-bit IDTR/GDTR.
3038	*/
3039	typedef struct X86XDTR32
3040	{
3041	/** Size of the descriptor table. */
3042	uint16_t cb;
3043	/** Address of the descriptor table. */
3044	#ifndef VBOX_FOR_DTRACE_LIB
3045	uint32_t uAddr;
3046	#else
3047	uint16_t au16Addr[2];
3048	#endif
3049	} X86XDTR32, *PX86XDTR32;
3050	#pragma pack()
3051
3052	#pragma pack(1)
3053	/**
3054	* 64-bit IDTR/GDTR.
3055	*/
3056	typedef struct X86XDTR64
3057	{
3058	/** Size of the descriptor table. */
3059	uint16_t cb;
3060	/** Address of the descriptor table. */
3061	#ifndef VBOX_FOR_DTRACE_LIB
3062	uint64_t uAddr;
3063	#else
3064	uint16_t au16Addr[4];
3065	#endif
3066	} X86XDTR64, *PX86XDTR64;
3067	#pragma pack()
3068
3069
3070	/** @name ModR/M
3071	* @{ */
3072	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3073	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3074	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3075	#define X86_MODRM_REG_SHIFT 3
3076	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3077	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3078	#define X86_MODRM_MOD_SHIFT 6
3079	#ifndef VBOX_FOR_DTRACE_LIB
3080	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3081	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3082	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3083	#endif
3084	/** @} */
3085
3086	/** @name SIB
3087	* @{ */
3088	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3089	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3090	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3091	#define X86_SIB_INDEX_SHIFT 3
3092	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3093	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3094	#define X86_SIB_SCALE_SHIFT 6
3095	#ifndef VBOX_FOR_DTRACE_LIB
3096	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3097	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3098	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3099	#endif
3100	/** @} */
3101
3102	/** @name General register indexes
3103	* @{ */
3104	#define X86_GREG_xAX 0
3105	#define X86_GREG_xCX 1
3106	#define X86_GREG_xDX 2
3107	#define X86_GREG_xBX 3
3108	#define X86_GREG_xSP 4
3109	#define X86_GREG_xBP 5
3110	#define X86_GREG_xSI 6
3111	#define X86_GREG_xDI 7
3112	#define X86_GREG_x8 8
3113	#define X86_GREG_x9 9
3114	#define X86_GREG_x10 10
3115	#define X86_GREG_x11 11
3116	#define X86_GREG_x12 12
3117	#define X86_GREG_x13 13
3118	#define X86_GREG_x14 14
3119	#define X86_GREG_x15 15
3120	/** @} */
3121
3122	/** @name X86_SREG_XXX - Segment register indexes.
3123	* @{ */
3124	#define X86_SREG_ES 0
3125	#define X86_SREG_CS 1
3126	#define X86_SREG_SS 2
3127	#define X86_SREG_DS 3
3128	#define X86_SREG_FS 4
3129	#define X86_SREG_GS 5
3130	/** @} */
3131
3132
3133	/** @} */
3134
3135	#endif
3136

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/iprt/x86.h@ 41343

Download in other formats: