x86.h@ 100997

Last change on this file since 100997 was 100996, checked in by vboxsync, 18 months ago
VMM: bugref:10498 bugref:10318: doxygen typo fix
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# include <iprt/types.h>
46	# include <iprt/assert.h>
47	#else
48	# pragma D depends_on library vbox-types.d
49	#endif
50
51	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
52	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
53	#ifdef RT_OS_SOLARIS
54	# undef CS
55	# undef DS
56	# undef MSR_IA32_FLUSH_CMD
57	# undef MSR_AMD_VIRT_SPEC_CTL
58	#endif
59
60	/** @defgroup grp_rt_x86 x86 Types and Definitions
61	* @ingroup grp_rt
62	* @{
63	*/
64
65	#ifndef VBOX_FOR_DTRACE_LIB
66	/**
67	* EFLAGS Bits.
68	*/
69	typedef struct X86EFLAGSBITS
70	{
71	/** Bit 0 - CF - Carry flag - Status flag. */
72	unsigned u1CF : 1;
73	/** Bit 1 - 1 - Reserved flag. */
74	unsigned u1Reserved0 : 1;
75	/** Bit 2 - PF - Parity flag - Status flag. */
76	unsigned u1PF : 1;
77	/** Bit 3 - 0 - Reserved flag. */
78	unsigned u1Reserved1 : 1;
79	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
80	unsigned u1AF : 1;
81	/** Bit 5 - 0 - Reserved flag. */
82	unsigned u1Reserved2 : 1;
83	/** Bit 6 - ZF - Zero flag - Status flag. */
84	unsigned u1ZF : 1;
85	/** Bit 7 - SF - Signed flag - Status flag. */
86	unsigned u1SF : 1;
87	/** Bit 8 - TF - Trap flag - System flag. */
88	unsigned u1TF : 1;
89	/** Bit 9 - IF - Interrupt flag - System flag. */
90	unsigned u1IF : 1;
91	/** Bit 10 - DF - Direction flag - Control flag. */
92	unsigned u1DF : 1;
93	/** Bit 11 - OF - Overflow flag - Status flag. */
94	unsigned u1OF : 1;
95	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
96	unsigned u2IOPL : 2;
97	/** Bit 14 - NT - Nested task flag - System flag. */
98	unsigned u1NT : 1;
99	/** Bit 15 - 0 - Reserved flag. */
100	unsigned u1Reserved3 : 1;
101	/** Bit 16 - RF - Resume flag - System flag. */
102	unsigned u1RF : 1;
103	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
104	unsigned u1VM : 1;
105	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
106	unsigned u1AC : 1;
107	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
108	unsigned u1VIF : 1;
109	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
110	unsigned u1VIP : 1;
111	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
112	unsigned u1ID : 1;
113	/** Bit 22-31 - 0 - Reserved flag. */
114	unsigned u10Reserved4 : 10;
115	} X86EFLAGSBITS;
116	/** Pointer to EFLAGS bits. */
117	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
118	/** Pointer to const EFLAGS bits. */
119	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
120	#endif /* !VBOX_FOR_DTRACE_LIB */
121
122	/**
123	* EFLAGS.
124	*/
125	typedef union X86EFLAGS
126	{
127	/** The plain unsigned view. */
128	uint32_t u;
129	#ifndef VBOX_FOR_DTRACE_LIB
130	/** The bitfield view. */
131	X86EFLAGSBITS Bits;
132	#endif
133	/** The 8-bit view. */
134	uint8_t au8[4];
135	/** The 16-bit view. */
136	uint16_t au16[2];
137	/** The 32-bit view. */
138	uint32_t au32[1];
139	/** The 32-bit view. */
140	uint32_t u32;
141	} X86EFLAGS;
142	/** Pointer to EFLAGS. */
143	typedef X86EFLAGS *PX86EFLAGS;
144	/** Pointer to const EFLAGS. */
145	typedef const X86EFLAGS *PCX86EFLAGS;
146
147	/**
148	* RFLAGS (32 upper bits are reserved).
149	*/
150	typedef union X86RFLAGS
151	{
152	/** The plain unsigned view. */
153	uint64_t u;
154	#ifndef VBOX_FOR_DTRACE_LIB
155	/** The bitfield view. */
156	X86EFLAGSBITS Bits;
157	#endif
158	/** The 8-bit view. */
159	uint8_t au8[8];
160	/** The 16-bit view. */
161	uint16_t au16[4];
162	/** The 32-bit view. */
163	uint32_t au32[2];
164	/** The 64-bit view. */
165	uint64_t au64[1];
166	/** The 64-bit view. */
167	uint64_t u64;
168	} X86RFLAGS;
169	/** Pointer to RFLAGS. */
170	typedef X86RFLAGS *PX86RFLAGS;
171	/** Pointer to const RFLAGS. */
172	typedef const X86RFLAGS *PCX86RFLAGS;
173
174
175	/** @name EFLAGS
176	* @{
177	*/
178	/** Bit 0 - CF - Carry flag - Status flag. */
179	#define X86_EFL_CF RT_BIT_32(0)
180	#define X86_EFL_CF_BIT 0
181	/** Bit 1 - Reserved, reads as 1. */
182	#define X86_EFL_1 RT_BIT_32(1)
183	/** Bit 2 - PF - Parity flag - Status flag. */
184	#define X86_EFL_PF RT_BIT_32(2)
185	#define X86_EFL_PF_BIT 2
186	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
187	#define X86_EFL_AF RT_BIT_32(4)
188	#define X86_EFL_AF_BIT 4
189	/** Bit 6 - ZF - Zero flag - Status flag. */
190	#define X86_EFL_ZF RT_BIT_32(6)
191	#define X86_EFL_ZF_BIT 6
192	/** Bit 7 - SF - Signed flag - Status flag. */
193	#define X86_EFL_SF RT_BIT_32(7)
194	#define X86_EFL_SF_BIT 7
195	/** Bit 8 - TF - Trap flag - System flag. */
196	#define X86_EFL_TF RT_BIT_32(8)
197	#define X86_EFL_TF_BIT 8
198	/** Bit 9 - IF - Interrupt flag - System flag. */
199	#define X86_EFL_IF RT_BIT_32(9)
200	#define X86_EFL_IF_BIT 9
201	/** Bit 10 - DF - Direction flag - Control flag. */
202	#define X86_EFL_DF RT_BIT_32(10)
203	#define X86_EFL_DF_BIT 10
204	/** Bit 11 - OF - Overflow flag - Status flag. */
205	#define X86_EFL_OF RT_BIT_32(11)
206	#define X86_EFL_OF_BIT 11
207	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
208	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
209	/** Bit 14 - NT - Nested task flag - System flag. */
210	#define X86_EFL_NT RT_BIT_32(14)
211	#define X86_EFL_NT_BIT 14
212	/** Bit 16 - RF - Resume flag - System flag. */
213	#define X86_EFL_RF RT_BIT_32(16)
214	#define X86_EFL_RF_BIT 16
215	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
216	#define X86_EFL_VM RT_BIT_32(17)
217	#define X86_EFL_VM_BIT 17
218	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
219	#define X86_EFL_AC RT_BIT_32(18)
220	#define X86_EFL_AC_BIT 18
221	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
222	#define X86_EFL_VIF RT_BIT_32(19)
223	#define X86_EFL_VIF_BIT 19
224	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
225	#define X86_EFL_VIP RT_BIT_32(20)
226	#define X86_EFL_VIP_BIT 20
227	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
228	#define X86_EFL_ID RT_BIT_32(21)
229	#define X86_EFL_ID_BIT 21
230	/** All live bits. */
231	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
232	/** Read as 1 bits. */
233	#define X86_EFL_RA1_MASK RT_BIT_32(1)
234	/** Read as 0 bits, excluding bits 31:22.
235	* Bits 3, 5, 15, and 22 thru 31. */
236	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
237	/** Read as 0 bits, excluding bits 31:22.
238	* Bits 3, 5 and 15. */
239	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
240	/** IOPL shift. */
241	#define X86_EFL_IOPL_SHIFT 12
242	/** The IOPL level from the flags. */
243	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
244	/** Bits restored by popf */
245	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
246	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
247	/** Bits restored by popf */
248	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
249	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
250	/** The status bits commonly updated by arithmetic instructions. */
251	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
252	/** @} */
253
254
255	/** CPUID Feature information - ECX.
256	* CPUID query with EAX=1.
257	*/
258	#ifndef VBOX_FOR_DTRACE_LIB
259	typedef struct X86CPUIDFEATECX
260	{
261	/** Bit 0 - SSE3 - Supports SSE3 or not. */
262	unsigned u1SSE3 : 1;
263	/** Bit 1 - PCLMULQDQ. */
264	unsigned u1PCLMULQDQ : 1;
265	/** Bit 2 - DS Area 64-bit layout. */
266	unsigned u1DTE64 : 1;
267	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
268	unsigned u1Monitor : 1;
269	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
270	unsigned u1CPLDS : 1;
271	/** Bit 5 - VMX - Virtual Machine Technology. */
272	unsigned u1VMX : 1;
273	/** Bit 6 - SMX: Safer Mode Extensions. */
274	unsigned u1SMX : 1;
275	/** Bit 7 - EST - Enh. SpeedStep Tech. */
276	unsigned u1EST : 1;
277	/** Bit 8 - TM2 - Terminal Monitor 2. */
278	unsigned u1TM2 : 1;
279	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
280	unsigned u1SSSE3 : 1;
281	/** Bit 10 - CNTX-ID - L1 Context ID. */
282	unsigned u1CNTXID : 1;
283	/** Bit 11 - Reserved. */
284	unsigned u1Reserved1 : 1;
285	/** Bit 12 - FMA. */
286	unsigned u1FMA : 1;
287	/** Bit 13 - CX16 - CMPXCHG16B. */
288	unsigned u1CX16 : 1;
289	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
290	unsigned u1TPRUpdate : 1;
291	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
292	unsigned u1PDCM : 1;
293	/** Bit 16 - Reserved. */
294	unsigned u1Reserved2 : 1;
295	/** Bit 17 - PCID - Process-context identifiers. */
296	unsigned u1PCID : 1;
297	/** Bit 18 - Direct Cache Access. */
298	unsigned u1DCA : 1;
299	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
300	unsigned u1SSE4_1 : 1;
301	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
302	unsigned u1SSE4_2 : 1;
303	/** Bit 21 - x2APIC. */
304	unsigned u1x2APIC : 1;
305	/** Bit 22 - MOVBE - Supports MOVBE. */
306	unsigned u1MOVBE : 1;
307	/** Bit 23 - POPCNT - Supports POPCNT. */
308	unsigned u1POPCNT : 1;
309	/** Bit 24 - TSC-Deadline. */
310	unsigned u1TSCDEADLINE : 1;
311	/** Bit 25 - AES. */
312	unsigned u1AES : 1;
313	/** Bit 26 - XSAVE - Supports XSAVE. */
314	unsigned u1XSAVE : 1;
315	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
316	unsigned u1OSXSAVE : 1;
317	/** Bit 28 - AVX - Supports AVX instruction extensions. */
318	unsigned u1AVX : 1;
319	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
320	unsigned u1F16C : 1;
321	/** Bit 30 - RDRAND - Supports RDRAND. */
322	unsigned u1RDRAND : 1;
323	/** Bit 31 - Hypervisor present (we're a guest). */
324	unsigned u1HVP : 1;
325	} X86CPUIDFEATECX;
326	#else /* VBOX_FOR_DTRACE_LIB */
327	typedef uint32_t X86CPUIDFEATECX;
328	#endif /* VBOX_FOR_DTRACE_LIB */
329	/** Pointer to CPUID Feature Information - ECX. */
330	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
331	/** Pointer to const CPUID Feature Information - ECX. */
332	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
333
334
335	/** CPUID Feature Information - EDX.
336	* CPUID query with EAX=1.
337	*/
338	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
339	typedef struct X86CPUIDFEATEDX
340	{
341	/** Bit 0 - FPU - x87 FPU on Chip. */
342	unsigned u1FPU : 1;
343	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
344	unsigned u1VME : 1;
345	/** Bit 2 - DE - Debugging extensions. */
346	unsigned u1DE : 1;
347	/** Bit 3 - PSE - Page Size Extension. */
348	unsigned u1PSE : 1;
349	/** Bit 4 - TSC - Time Stamp Counter. */
350	unsigned u1TSC : 1;
351	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
352	unsigned u1MSR : 1;
353	/** Bit 6 - PAE - Physical Address Extension. */
354	unsigned u1PAE : 1;
355	/** Bit 7 - MCE - Machine Check Exception. */
356	unsigned u1MCE : 1;
357	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
358	unsigned u1CX8 : 1;
359	/** Bit 9 - APIC - APIC On-Chip. */
360	unsigned u1APIC : 1;
361	/** Bit 10 - Reserved. */
362	unsigned u1Reserved1 : 1;
363	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
364	unsigned u1SEP : 1;
365	/** Bit 12 - MTRR - Memory Type Range Registers. */
366	unsigned u1MTRR : 1;
367	/** Bit 13 - PGE - PTE Global Bit. */
368	unsigned u1PGE : 1;
369	/** Bit 14 - MCA - Machine Check Architecture. */
370	unsigned u1MCA : 1;
371	/** Bit 15 - CMOV - Conditional Move Instructions. */
372	unsigned u1CMOV : 1;
373	/** Bit 16 - PAT - Page Attribute Table. */
374	unsigned u1PAT : 1;
375	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
376	unsigned u1PSE36 : 1;
377	/** Bit 18 - PSN - Processor Serial Number. */
378	unsigned u1PSN : 1;
379	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
380	unsigned u1CLFSH : 1;
381	/** Bit 20 - Reserved. */
382	unsigned u1Reserved2 : 1;
383	/** Bit 21 - DS - Debug Store. */
384	unsigned u1DS : 1;
385	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
386	unsigned u1ACPI : 1;
387	/** Bit 23 - MMX - Intel MMX 'Technology'. */
388	unsigned u1MMX : 1;
389	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
390	unsigned u1FXSR : 1;
391	/** Bit 25 - SSE - SSE Support. */
392	unsigned u1SSE : 1;
393	/** Bit 26 - SSE2 - SSE2 Support. */
394	unsigned u1SSE2 : 1;
395	/** Bit 27 - SS - Self Snoop. */
396	unsigned u1SS : 1;
397	/** Bit 28 - HTT - Hyper-Threading Technology. */
398	unsigned u1HTT : 1;
399	/** Bit 29 - TM - Thermal Monitor. */
400	unsigned u1TM : 1;
401	/** Bit 30 - Reserved - . */
402	unsigned u1Reserved3 : 1;
403	/** Bit 31 - PBE - Pending Break Enabled. */
404	unsigned u1PBE : 1;
405	} X86CPUIDFEATEDX;
406	#else /* VBOX_FOR_DTRACE_LIB */
407	typedef uint32_t X86CPUIDFEATEDX;
408	#endif /* VBOX_FOR_DTRACE_LIB */
409	/** Pointer to CPUID Feature Information - EDX. */
410	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
411	/** Pointer to const CPUID Feature Information - EDX. */
412	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
413
414	/** @name CPUID Vendor information.
415	* CPUID query with EAX=0.
416	* @{
417	*/
418	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
419	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
420	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
421
422	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
423	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
424	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
425
426	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
427	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
428	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
429
430	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
431	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
432	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
433
434	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
435	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
436	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
437	/** @} */
438
439
440	/** @name CPUID Feature information.
441	* CPUID query with EAX=1.
442	* @{
443	*/
444	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
445	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
446	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
447	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
448	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
449	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
450	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
451	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
452	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
453	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
454	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
455	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
456	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
457	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
458	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
459	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
460	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
461	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
462	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
463	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
464	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
465	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
466	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
467	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
468	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
469	/** ECX Bit 12 - FMA. */
470	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
471	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
472	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
473	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
474	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
475	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
476	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
477	/** ECX Bit 17 - PCID - Process-context identifiers. */
478	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
479	/** ECX Bit 18 - DCA - Direct Cache Access. */
480	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
481	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
482	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
483	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
484	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
485	/** ECX Bit 21 - x2APIC support. */
486	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
487	/** ECX Bit 22 - MOVBE instruction. */
488	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
489	/** ECX Bit 23 - POPCNT instruction. */
490	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
491	/** ECX Bir 24 - TSC-Deadline. */
492	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
493	/** ECX Bit 25 - AES instructions. */
494	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
495	/** ECX Bit 26 - XSAVE instruction. */
496	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
497	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
498	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
499	/** ECX Bit 28 - AVX. */
500	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
501	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
502	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
503	/** ECX Bit 30 - RDRAND instruction. */
504	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
505	/** ECX Bit 31 - Hypervisor Present (software only). */
506	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
507
508
509	/** Bit 0 - FPU - x87 FPU on Chip. */
510	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
511	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
512	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
513	/** Bit 2 - DE - Debugging extensions. */
514	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
515	/** Bit 3 - PSE - Page Size Extension. */
516	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
517	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
518	/** Bit 4 - TSC - Time Stamp Counter. */
519	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
520	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
521	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
522	/** Bit 6 - PAE - Physical Address Extension. */
523	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
524	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
525	/** Bit 7 - MCE - Machine Check Exception. */
526	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
527	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
528	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
529	/** Bit 9 - APIC - APIC On-Chip. */
530	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
531	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
532	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
533	/** Bit 12 - MTRR - Memory Type Range Registers. */
534	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
535	/** Bit 13 - PGE - PTE Global Bit. */
536	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
537	/** Bit 14 - MCA - Machine Check Architecture. */
538	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
539	/** Bit 15 - CMOV - Conditional Move Instructions. */
540	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
541	/** Bit 16 - PAT - Page Attribute Table. */
542	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
543	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
544	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
545	/** Bit 18 - PSN - Processor Serial Number. */
546	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
547	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
548	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
549	/** Bit 21 - DS - Debug Store. */
550	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
551	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
552	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
553	/** Bit 23 - MMX - Intel MMX Technology. */
554	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
555	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
556	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
557	/** Bit 25 - SSE - SSE Support. */
558	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
559	/** Bit 26 - SSE2 - SSE2 Support. */
560	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
561	/** Bit 27 - SS - Self Snoop. */
562	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
563	/** Bit 28 - HTT - Hyper-Threading Technology. */
564	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
565	/** Bit 29 - TM - Therm. Monitor. */
566	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
567	/** Bit 31 - PBE - Pending Break Enabled. */
568	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
569	/** @} */
570
571	/** @name CPUID mwait/monitor information.
572	* CPUID query with EAX=5.
573	* @{
574	*/
575	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
576	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
577	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
578	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
579	/** @} */
580
581
582	/** @name CPUID Structured Extended Feature information.
583	* CPUID query with EAX=7.
584	* @{
585	*/
586	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
588	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
589	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
590	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
591	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
592	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
593	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
594	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
595	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
596	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
597	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
598	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
599	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
600	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
601	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
602	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
603	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
604	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
605	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
606	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
607	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
608	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
609	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
610	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
611	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
612	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
613	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
614	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
615	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
616	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
617	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
618	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
619	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
620	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
621	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
622	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
623	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
624	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
625	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
626	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
627	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
628	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
629	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
630	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
631	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
632	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
633	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
634	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
635	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
636	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
637	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
638
639	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
640	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
641	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
642	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
643	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
644	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
645	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
646	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
647	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
648	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
649	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
650	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
651	/** ECX Bit 22 - RDPID - Support pread process ID. */
652	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
653	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
654	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
655
656	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
657	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
658	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
659	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
660	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
661	* IBPB command in IA32_PRED_CMD. */
662	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
663	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
664	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
665	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
666	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
667	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
668	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
669	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
670	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
671
672	/** @} */
673
674
675	/** @name CPUID Extended Feature information.
676	* CPUID query with EAX=0x80000001.
677	* @{
678	*/
679	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
680	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
681
682	/** EDX Bit 11 - SYSCALL/SYSRET. */
683	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
684	/** EDX Bit 20 - No-Execute/Execute-Disable. */
685	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
686	/** EDX Bit 26 - 1 GB large page. */
687	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
688	/** EDX Bit 27 - RDTSCP. */
689	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
690	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
691	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
692	/** @}*/
693
694	/** @name CPUID AMD Feature information.
695	* CPUID query with EAX=0x80000001.
696	* @{
697	*/
698	/** Bit 0 - FPU - x87 FPU on Chip. */
699	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
700	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
701	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
702	/** Bit 2 - DE - Debugging extensions. */
703	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
704	/** Bit 3 - PSE - Page Size Extension. */
705	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
706	/** Bit 4 - TSC - Time Stamp Counter. */
707	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
708	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
709	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
710	/** Bit 6 - PAE - Physical Address Extension. */
711	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
712	/** Bit 7 - MCE - Machine Check Exception. */
713	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
714	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
715	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
716	/** Bit 9 - APIC - APIC On-Chip. */
717	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
718	/** Bit 12 - MTRR - Memory Type Range Registers. */
719	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
720	/** Bit 13 - PGE - PTE Global Bit. */
721	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
722	/** Bit 14 - MCA - Machine Check Architecture. */
723	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
724	/** Bit 15 - CMOV - Conditional Move Instructions. */
725	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
726	/** Bit 16 - PAT - Page Attribute Table. */
727	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
728	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
729	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
730	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
731	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
732	/** Bit 23 - MMX - Intel MMX Technology. */
733	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
734	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
735	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
736	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
737	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
738	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
739	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
740	/** Bit 31 - 3DNOW - AMD 3DNow. */
741	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
742
743	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
744	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
745	/** Bit 2 - SVM - AMD VM extensions. */
746	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
747	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
748	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
749	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
750	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
751	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
752	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
753	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
754	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
755	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
756	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
757	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
758	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
759	/** Bit 9 - OSVW - AMD OS visible workaround. */
760	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
761	/** Bit 10 - IBS - Instruct based sampling. */
762	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
763	/** Bit 11 - XOP - Extended operation support (see APM6). */
764	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
765	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
766	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
767	/** Bit 13 - WDT - AMD Watchdog timer support. */
768	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
769	/** Bit 15 - LWP - Lightweight profiling support. */
770	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
771	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
772	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
773	/** Bit 19 - NodeId - Indicates support for
774	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
775	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
776	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
777	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
778	/** Bit 22 - TopologyExtensions - . */
779	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
780	/** @} */
781
782
783	/** @name CPUID AMD Feature information.
784	* CPUID query with EAX=0x80000007.
785	* @{
786	*/
787	/** Bit 0 - TS - Temperature Sensor. */
788	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
789	/** Bit 1 - FID - Frequency ID Control. */
790	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
791	/** Bit 2 - VID - Voltage ID Control. */
792	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
793	/** Bit 3 - TTP - THERMTRIP. */
794	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
795	/** Bit 4 - TM - Hardware Thermal Control. */
796	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
797	/** Bit 5 - STC - Software Thermal Control. */
798	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
799	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
800	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
801	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
802	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
803	/** Bit 8 - TSCINVAR - TSC Invariant. */
804	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
805	/** Bit 9 - CPB - TSC Invariant. */
806	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
807	/** Bit 10 - EffFreqRO - MPERF/APERF. */
808	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
809	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
810	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
811	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
812	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
813	/** @} */
814
815
816	/** @name CPUID AMD extended feature extensions ID (EBX).
817	* CPUID query with EAX=0x80000008.
818	* @{
819	*/
820	/** Bit 0 - CLZERO - Clear zero instruction. */
821	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
822	/** Bit 1 - IRPerf - Instructions retired count support. */
823	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
824	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
825	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
826	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
827	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
828	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
829	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
830	/* AMD pipeline length: 9 feature bits ;-) */
831	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
832	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
833	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
834	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
835	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
836	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
837	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
838	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
839	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
840	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
841	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
842	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
843	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
844	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
845	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
846	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
847	/** Bit 26 - Speculative Store Bypass Disable not required. */
848	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
849	/** @} */
850
851
852	/** @name CPUID AMD SVM Feature information.
853	* CPUID query with EAX=0x8000000a.
854	* @{
855	*/
856	/** Bit 0 - NP - Nested Paging supported. */
857	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
858	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
859	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
860	/** Bit 2 - SVML - SVM locking bit supported. */
861	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
862	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
863	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
864	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
865	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
866	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
867	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
868	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
869	* VMCB.TLB_Control is supported. */
870	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
871	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
872	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
873	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
874	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
875	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
876	* intercept filter cycle count threshold. */
877	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
878	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
879	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
880	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
881	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
882	/** Bit 16 - VGIF - Supports virtualized GIF. */
883	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
884	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
885	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
886	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
887	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
888	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
889	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
890	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
891	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
892	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
893	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
894	/** @} */
895
896
897	/** @name CR0
898	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
899	* reserved flags.
900	* @{ */
901	/** Bit 0 - PE - Protection Enabled */
902	#define X86_CR0_PE RT_BIT_32(0)
903	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
904	/** Bit 1 - MP - Monitor Coprocessor */
905	#define X86_CR0_MP RT_BIT_32(1)
906	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
907	/** Bit 2 - EM - Emulation. */
908	#define X86_CR0_EM RT_BIT_32(2)
909	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
910	/** Bit 3 - TS - Task Switch. */
911	#define X86_CR0_TS RT_BIT_32(3)
912	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
913	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
914	#define X86_CR0_ET RT_BIT_32(4)
915	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
916	/** Bit 5 - NE - Numeric error (486+). */
917	#define X86_CR0_NE RT_BIT_32(5)
918	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
919	/** Bit 16 - WP - Write Protect (486+). */
920	#define X86_CR0_WP RT_BIT_32(16)
921	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
922	/** Bit 18 - AM - Alignment Mask (486+). */
923	#define X86_CR0_AM RT_BIT_32(18)
924	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
925	/** Bit 29 - NW - Not Write-though (486+). */
926	#define X86_CR0_NW RT_BIT_32(29)
927	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
928	/** Bit 30 - WP - Cache Disable (486+). */
929	#define X86_CR0_CD RT_BIT_32(30)
930	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
931	/** Bit 31 - PG - Paging. */
932	#define X86_CR0_PG RT_BIT_32(31)
933	#define X86_CR0_PAGING RT_BIT_32(31)
934	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
935	/** @} */
936
937
938	/** @name CR3
939	* @{ */
940	/** Bit 3 - PWT - Page-level Writes Transparent. */
941	#define X86_CR3_PWT RT_BIT_32(3)
942	/** Bit 4 - PCD - Page-level Cache Disable. */
943	#define X86_CR3_PCD RT_BIT_32(4)
944	/** Bits 12-31 - - Page directory page number. */
945	#define X86_CR3_PAGE_MASK (0xfffff000)
946	/** Bits 5-31 - - PAE Page directory page number. */
947	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
948	/** Bits 12-51 - - AMD64 PML4 page number.
949	* @note This is a maxed out mask, the actual acceptable CR3 value can
950	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
951	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
952	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
953	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
954	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
955	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
956	/** @} */
957
958
959	/** @name CR4
960	* @{ */
961	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
962	#define X86_CR4_VME RT_BIT_32(0)
963	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
964	#define X86_CR4_PVI RT_BIT_32(1)
965	/** Bit 2 - TSD - Time Stamp Disable. */
966	#define X86_CR4_TSD RT_BIT_32(2)
967	/** Bit 3 - DE - Debugging Extensions. */
968	#define X86_CR4_DE RT_BIT_32(3)
969	/** Bit 4 - PSE - Page Size Extension. */
970	#define X86_CR4_PSE RT_BIT_32(4)
971	/** Bit 5 - PAE - Physical Address Extension. */
972	#define X86_CR4_PAE RT_BIT_32(5)
973	/** Bit 6 - MCE - Machine-Check Enable. */
974	#define X86_CR4_MCE RT_BIT_32(6)
975	/** Bit 7 - PGE - Page Global Enable. */
976	#define X86_CR4_PGE RT_BIT_32(7)
977	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
978	#define X86_CR4_PCE RT_BIT_32(8)
979	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
980	#define X86_CR4_OSFXSR RT_BIT_32(9)
981	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
982	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
983	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
984	#define X86_CR4_UMIP RT_BIT_32(11)
985	/** Bit 13 - VMXE - VMX mode is enabled. */
986	#define X86_CR4_VMXE RT_BIT_32(13)
987	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
988	#define X86_CR4_SMXE RT_BIT_32(14)
989	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
990	#define X86_CR4_FSGSBASE RT_BIT_32(16)
991	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
992	#define X86_CR4_PCIDE RT_BIT_32(17)
993	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
994	* extended states. */
995	#define X86_CR4_OSXSAVE RT_BIT_32(18)
996	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
997	#define X86_CR4_SMEP RT_BIT_32(20)
998	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
999	#define X86_CR4_SMAP RT_BIT_32(21)
1000	/** Bit 22 - PKE - Protection Key Enable. */
1001	#define X86_CR4_PKE RT_BIT_32(22)
1002	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1003	#define X86_CR4_CET RT_BIT_32(23)
1004	/** @} */
1005
1006
1007	/** @name DR6
1008	* @{ */
1009	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1010	#define X86_DR6_B0 RT_BIT_32(0)
1011	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1012	#define X86_DR6_B1 RT_BIT_32(1)
1013	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1014	#define X86_DR6_B2 RT_BIT_32(2)
1015	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1016	#define X86_DR6_B3 RT_BIT_32(3)
1017	/** Mask of all the Bx bits. */
1018	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1019	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1020	#define X86_DR6_BD RT_BIT_32(13)
1021	/** Bit 14 - BS - Single step */
1022	#define X86_DR6_BS RT_BIT_32(14)
1023	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1024	#define X86_DR6_BT RT_BIT_32(15)
1025	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1026	#define X86_DR6_RTM RT_BIT_32(16)
1027	/** Value of DR6 after powerup/reset. */
1028	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1029	/** Bits which must be 1s in DR6. */
1030	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1031	/** Bits which must be 1s in DR6, when RTM is supported. */
1032	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1033	/** Bits which must be 0s in DR6. */
1034	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1035	/** Bits which must be 0s on writes to DR6. */
1036	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1037	/** @} */
1038
1039	/** Get the DR6.Bx bit for a the given breakpoint. */
1040	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1041
1042
1043	/** @name DR7
1044	* @{ */
1045	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1046	#define X86_DR7_L0 RT_BIT_32(0)
1047	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1048	#define X86_DR7_G0 RT_BIT_32(1)
1049	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1050	#define X86_DR7_L1 RT_BIT_32(2)
1051	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1052	#define X86_DR7_G1 RT_BIT_32(3)
1053	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1054	#define X86_DR7_L2 RT_BIT_32(4)
1055	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1056	#define X86_DR7_G2 RT_BIT_32(5)
1057	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1058	#define X86_DR7_L3 RT_BIT_32(6)
1059	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1060	#define X86_DR7_G3 RT_BIT_32(7)
1061	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1062	#define X86_DR7_LE RT_BIT_32(8)
1063	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1064	#define X86_DR7_GE RT_BIT_32(9)
1065
1066	/** L0, L1, L2, and L3. */
1067	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1068	/** L0, L1, L2, and L3. */
1069	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1070
1071	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1072	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1073	#define X86_DR7_RTM RT_BIT_32(11)
1074	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1075	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1076	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1077	* instruction is executed.
1078	* @see http://www.rcollins.org/secrets/DR7.html */
1079	#define X86_DR7_ICE_IR RT_BIT_32(12)
1080	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1081	* any DR register is accessed. */
1082	#define X86_DR7_GD RT_BIT_32(13)
1083	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1084	* Pentium. */
1085	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1086	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1087	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1088	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1089	#define X86_DR7_RW0_MASK (3 << 16)
1090	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1091	#define X86_DR7_LEN0_MASK (3 << 18)
1092	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1093	#define X86_DR7_RW1_MASK (3 << 20)
1094	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1095	#define X86_DR7_LEN1_MASK (3 << 22)
1096	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1097	#define X86_DR7_RW2_MASK (3 << 24)
1098	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1099	#define X86_DR7_LEN2_MASK (3 << 26)
1100	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1101	#define X86_DR7_RW3_MASK (3 << 28)
1102	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1103	#define X86_DR7_LEN3_MASK (3 << 30)
1104
1105	/** Bits which reads as 1s. */
1106	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1107	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1108	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1109	/** Bits which must be 0s when writing to DR7. */
1110	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1111
1112	/** Calcs the L bit of Nth breakpoint.
1113	* @param iBp The breakpoint number [0..3].
1114	*/
1115	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1116
1117	/** Calcs the G bit of Nth breakpoint.
1118	* @param iBp The breakpoint number [0..3].
1119	*/
1120	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1121
1122	/** Calcs the L and G bits of Nth breakpoint.
1123	* @param iBp The breakpoint number [0..3].
1124	*/
1125	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1126
1127	/** @name Read/Write values.
1128	* @{ */
1129	/** Break on instruction fetch only. */
1130	#define X86_DR7_RW_EO UINT32_C(0)
1131	/** Break on write only. */
1132	#define X86_DR7_RW_WO UINT32_C(1)
1133	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1134	#define X86_DR7_RW_IO UINT32_C(2)
1135	/** Break on read or write (but not instruction fetches). */
1136	#define X86_DR7_RW_RW UINT32_C(3)
1137	/** @} */
1138
1139	/** Shifts a X86_DR7_RW_* value to its right place.
1140	* @param iBp The breakpoint number [0..3].
1141	* @param fRw One of the X86_DR7_RW_* value.
1142	*/
1143	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1144
1145	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1146	* one of the X86_DR7_RW_XXX constants).
1147	*
1148	* @returns X86_DR7_RW_XXX
1149	* @param uDR7 DR7 value
1150	* @param iBp The breakpoint number [0..3].
1151	*/
1152	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1153
1154	/** R/W0, R/W1, R/W2, and R/W3. */
1155	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1156
1157	#ifndef VBOX_FOR_DTRACE_LIB
1158	/** Checks the RW and LEN fields are set up for an instruction breakpoint.
1159	* @note This does not check if it's enabled. */
1160	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1161	/** Checks if an instruction breakpoint is enabled and configured correctly.
1162	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1163	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1164	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1165	/** Checks if there are any instruction fetch breakpoint types configured in the
1166	* RW and LEN registers.
1167	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1168	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1169	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1170	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1171	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1172	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1173
1174	/** Checks if there are any I/O breakpoint types configured in the RW
1175	* registers. Does NOT check if these are enabled, sorry. */
1176	# define X86_DR7_ANY_RW_IO(uDR7) \
1177	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1178	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1179	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1180	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1181	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1182	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1183	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1184	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1185	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1186	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1187	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1188
1189	#endif /* !VBOX_FOR_DTRACE_LIB */
1190
1191	/** @name Length values.
1192	* @{ */
1193	#define X86_DR7_LEN_BYTE UINT32_C(0)
1194	#define X86_DR7_LEN_WORD UINT32_C(1)
1195	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1196	#define X86_DR7_LEN_DWORD UINT32_C(3)
1197	/** @} */
1198
1199	/** Shifts a X86_DR7_LEN_* value to its right place.
1200	* @param iBp The breakpoint number [0..3].
1201	* @param cb One of the X86_DR7_LEN_* values.
1202	*/
1203	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1204
1205	/** Fetch the breakpoint length bits from the DR7 value.
1206	* @param uDR7 DR7 value
1207	* @param iBp The breakpoint number [0..3].
1208	*/
1209	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1210
1211	/** Mask used to check if any breakpoints are enabled. */
1212	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1213
1214	/** LEN0, LEN1, LEN2, and LEN3. */
1215	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1216	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1217	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1218
1219	/** Value of DR7 after powerup/reset. */
1220	#define X86_DR7_INIT_VAL 0x400
1221	/** @} */
1222
1223
1224	/** @name Machine Specific Registers
1225	* @{
1226	*/
1227	/** Machine check address register (P5). */
1228	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1229	/** Machine check type register (P5). */
1230	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1231	/** Time Stamp Counter. */
1232	#define MSR_IA32_TSC 0x10
1233	#define MSR_IA32_CESR UINT32_C(0x00000011)
1234	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1235	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1236
1237	#define MSR_IA32_PLATFORM_ID 0x17
1238
1239	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1240	# define MSR_IA32_APICBASE 0x1b
1241	/** Local APIC enabled. */
1242	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1243	/** X2APIC enabled (requires the EN bit to be set). */
1244	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1245	/** The processor is the boot strap processor (BSP). */
1246	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1247	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1248	* width. */
1249	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1250	/** The default physical base address of the APIC. */
1251	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1252	/** Gets the physical base address from the MSR. */
1253	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1254	#endif
1255
1256	/** Undocumented intel MSR for reporting thread and core counts.
1257	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1258	* first 16 bits is the thread count. The next 16 bits the core count, except
1259	* on Westmere where it seems it's only the next 4 bits for some reason. */
1260	#define MSR_CORE_THREAD_COUNT 0x35
1261
1262	/** CPU Feature control. */
1263	#define MSR_IA32_FEATURE_CONTROL 0x3A
1264	/** Feature control - Lock MSR from writes (R/W0). */
1265	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1266	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1267	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1268	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1269	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1270	/** Feature control - SENTER local functions enable (R/WL). */
1271	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1272	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1273	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1274	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1275	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1276	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1277	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1278	/** Feature control - SENTER global enable (R/WL). */
1279	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1280	/** Feature control - SGX launch control enable (R/WL). */
1281	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1282	/** Feature control - SGX global enable (R/WL). */
1283	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1284	/** Feature control - LMCE on (R/WL). */
1285	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1286
1287	/** Per-processor TSC adjust MSR. */
1288	#define MSR_IA32_TSC_ADJUST 0x3B
1289
1290	/** Spectre control register.
1291	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1292	#define MSR_IA32_SPEC_CTRL 0x48
1293	/** IBRS - Indirect branch restricted speculation. */
1294	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1295	/** STIBP - Single thread indirect branch predictors. */
1296	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1297	/** SSBD - Speculative Store Bypass Disable. */
1298	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1299
1300	/** Prediction command register.
1301	* Write only, logical processor scope, no state since write only. */
1302	#define MSR_IA32_PRED_CMD 0x49
1303	/** IBPB - Indirect branch prediction barrie when written as 1. */
1304	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1305
1306	/** BIOS update trigger (microcode update). */
1307	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1308
1309	/** BIOS update signature (microcode). */
1310	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1311
1312	/** SMM monitor control. */
1313	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1314	/** SMM control - Valid. */
1315	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1316	/** SMM control - VMXOFF unblocks SMI. */
1317	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1318	/** SMM control - MSEG base physical address. */
1319	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1320
1321	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1322	#define MSR_IA32_SMBASE 0x9E
1323
1324	/** General performance counter no. 0. */
1325	#define MSR_IA32_PMC0 0xC1
1326	/** General performance counter no. 1. */
1327	#define MSR_IA32_PMC1 0xC2
1328	/** General performance counter no. 2. */
1329	#define MSR_IA32_PMC2 0xC3
1330	/** General performance counter no. 3. */
1331	#define MSR_IA32_PMC3 0xC4
1332	/** General performance counter no. 4. */
1333	#define MSR_IA32_PMC4 0xC5
1334	/** General performance counter no. 5. */
1335	#define MSR_IA32_PMC5 0xC6
1336	/** General performance counter no. 6. */
1337	#define MSR_IA32_PMC6 0xC7
1338	/** General performance counter no. 7. */
1339	#define MSR_IA32_PMC7 0xC8
1340
1341	/** Nehalem power control. */
1342	#define MSR_IA32_PLATFORM_INFO 0xCE
1343
1344	/** Get FSB clock status (Intel-specific). */
1345	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1346
1347	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1348	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1349
1350	/** C0 Maximum Frequency Clock Count */
1351	#define MSR_IA32_MPERF 0xE7
1352	/** C0 Actual Frequency Clock Count */
1353	#define MSR_IA32_APERF 0xE8
1354
1355	/** MTRR Capabilities. */
1356	#define MSR_IA32_MTRR_CAP 0xFE
1357	/** Bits 0-7 - VCNT - Variable range registers count. */
1358	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1359	/** Bit 8 - FIX - Fixed range registers supported. */
1360	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1361	/** Bit 10 - WC - Write-Combining memory type supported. */
1362	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1363	/** Bit 11 - SMRR - System Management Range Register supported. */
1364	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1365	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1366	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1367
1368	/**
1369	* Variable-range MTRR MSR pair.
1370	*/
1371	typedef struct X86MTRRVAR
1372	{
1373	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1374	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1375	} X86MTRRVAR;
1376	#ifndef VBOX_FOR_DTRACE_LIB
1377	AssertCompileSize(X86MTRRVAR, 16);
1378	#endif
1379	/** Pointer to a variable-range MTRR MSR pair. */
1380	typedef X86MTRRVAR *PX86MTRRVAR;
1381	/** Pointer to a const variable-range MTRR MSR pair. */
1382	typedef const X86MTRRVAR *PCX86MTRRVAR;
1383
1384	/** Memory types that can be encoded in MTRRs.
1385	* @{ */
1386	/** Uncacheable. */
1387	#define X86_MTRR_MT_UC 0
1388	/** Write Combining. */
1389	#define X86_MTRR_MT_WC 1
1390	/** Write-through. */
1391	#define X86_MTRR_MT_WT 4
1392	/** Write-protected. */
1393	#define X86_MTRR_MT_WP 5
1394	/** Writeback. */
1395	#define X86_MTRR_MT_WB 6
1396	/** @}*/
1397
1398	/** Architecture capabilities (bugfixes). */
1399	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1400	/** CPU is no subject to meltdown problems. */
1401	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1402	/** CPU has better IBRS and you can leave it on all the time. */
1403	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1404	/** CPU has return stack buffer (RSB) override. */
1405	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1406	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1407	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1408	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1409	/** CPU does not suffer from MDS issues. */
1410	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1411
1412	/** Flush command register. */
1413	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1414	/** Flush the level 1 data cache when this bit is written. */
1415	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1416
1417	/** Cache control/info. */
1418	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1419
1420	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1421	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1422	* R0 SS == CS + 8
1423	* R3 CS == CS + 16
1424	* R3 SS == CS + 24
1425	*/
1426	#define MSR_IA32_SYSENTER_CS 0x174
1427	/** SYSENTER_ESP - the R0 ESP. */
1428	#define MSR_IA32_SYSENTER_ESP 0x175
1429	/** SYSENTER_EIP - the R0 EIP. */
1430	#define MSR_IA32_SYSENTER_EIP 0x176
1431	#endif
1432
1433	/** Machine Check Global Capabilities Register. */
1434	#define MSR_IA32_MCG_CAP 0x179
1435	/** Machine Check Global Status Register. */
1436	#define MSR_IA32_MCG_STATUS 0x17A
1437	/** Machine Check Global Control Register. */
1438	#define MSR_IA32_MCG_CTRL 0x17B
1439
1440	/** Page Attribute Table. */
1441	#define MSR_IA32_CR_PAT 0x277
1442	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1443	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1444	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1445
1446	/** Performance event select MSRs. (Intel only) */
1447	#define MSR_IA32_PERFEVTSEL0 0x186
1448	#define MSR_IA32_PERFEVTSEL1 0x187
1449	#define MSR_IA32_PERFEVTSEL2 0x188
1450	#define MSR_IA32_PERFEVTSEL3 0x189
1451
1452	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1453	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1454	* holds a ratio that Apple takes for TSC granularity.
1455	*
1456	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1457	#define MSR_FLEX_RATIO 0x194
1458	/** Performance state value and starting with Intel core more.
1459	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1460	#define MSR_IA32_PERF_STATUS 0x198
1461	#define MSR_IA32_PERF_CTL 0x199
1462	#define MSR_IA32_THERM_STATUS 0x19c
1463
1464	/** Offcore response event select registers. */
1465	#define MSR_OFFCORE_RSP_0 0x1a6
1466	#define MSR_OFFCORE_RSP_1 0x1a7
1467
1468	/** Enable misc. processor features (R/W). */
1469	#define MSR_IA32_MISC_ENABLE 0x1A0
1470	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1471	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1472	/** Automatic Thermal Control Circuit Enable (R/W). */
1473	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1474	/** Performance Monitoring Available (R). */
1475	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1476	/** Branch Trace Storage Unavailable (R/O). */
1477	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1478	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1479	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1480	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1481	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1482	/** If MONITOR/MWAIT is supported (R/W). */
1483	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1484	/** Limit CPUID Maxval to 3 leafs (R/W). */
1485	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1486	/** When set to 1, xTPR messages are disabled (R/W). */
1487	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1488	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1489	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1490
1491	/** Trace/Profile Resource Control (R/W) */
1492	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1493	/** Last branch record. */
1494	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1495	/** Branch trace flag (single step on branches). */
1496	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1497	/** Performance monitoring pin control (AMD only). */
1498	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1499	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1500	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1501	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1502	/** Trace message enable (Intel only). */
1503	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1504	/** Branch trace store (Intel only). */
1505	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1506	/** Branch trace interrupt (Intel only). */
1507	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1508	/** Branch trace off in privileged code (Intel only). */
1509	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1510	/** Branch trace off in user code (Intel only). */
1511	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1512	/** Freeze LBR on PMI flag (Intel only). */
1513	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1514	/** Freeze PERFMON on PMI flag (Intel only). */
1515	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1516	/** Freeze while SMM enabled (Intel only). */
1517	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1518	/** Advanced debugging of RTM regions (Intel only). */
1519	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1520	/** Debug control MSR valid bits (Intel only). */
1521	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1522	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1523	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1524	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1525	\| MSR_IA32_DEBUGCTL_RTM)
1526
1527	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1528	* @{ */
1529	#define MSR_P4_LASTBRANCH_0 0x1db
1530	#define MSR_P4_LASTBRANCH_1 0x1dc
1531	#define MSR_P4_LASTBRANCH_2 0x1dd
1532	#define MSR_P4_LASTBRANCH_3 0x1de
1533
1534	/** LBR Top-of-stack MSR (index to most recent record). */
1535	#define MSR_P4_LASTBRANCH_TOS 0x1da
1536	/** @} */
1537
1538	/** @name Last branch registers for Core 2 and related Xeons.
1539	* @{ */
1540	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1541	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1542	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1543	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1544
1545	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1546	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1547	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1548	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1549
1550	/** LBR Top-of-stack MSR (index to most recent record). */
1551	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1552	/** @} */
1553
1554	/** @name Last branch registers.
1555	* @{ */
1556	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1557	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1558	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1559	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1560	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1561	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1562	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1563	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1564	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1565	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1566	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1567	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1568	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1569	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1570	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1571	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1572	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1573	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1574	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1575	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1576	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1577	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1578	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1579	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1580	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1581	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1582	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1583	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1584	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1585	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1586	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1587	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1588
1589	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1590	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1591	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1592	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1593	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1594	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1595	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1596	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1597	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1598	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1599	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1600	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1601	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1602	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1603	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1604	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1605	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1606	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1607	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1608	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1609	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1610	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1611	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1612	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1613	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1614	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1615	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1616	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1617	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1618	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1619	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1620	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1621
1622	#define MSR_LASTBRANCH_0_INFO 0xdc0
1623	#define MSR_LASTBRANCH_1_INFO 0xdc1
1624	#define MSR_LASTBRANCH_2_INFO 0xdc2
1625	#define MSR_LASTBRANCH_3_INFO 0xdc3
1626	#define MSR_LASTBRANCH_4_INFO 0xdc4
1627	#define MSR_LASTBRANCH_5_INFO 0xdc5
1628	#define MSR_LASTBRANCH_6_INFO 0xdc6
1629	#define MSR_LASTBRANCH_7_INFO 0xdc7
1630	#define MSR_LASTBRANCH_8_INFO 0xdc8
1631	#define MSR_LASTBRANCH_9_INFO 0xdc9
1632	#define MSR_LASTBRANCH_10_INFO 0xdca
1633	#define MSR_LASTBRANCH_11_INFO 0xdcb
1634	#define MSR_LASTBRANCH_12_INFO 0xdcc
1635	#define MSR_LASTBRANCH_13_INFO 0xdcd
1636	#define MSR_LASTBRANCH_14_INFO 0xdce
1637	#define MSR_LASTBRANCH_15_INFO 0xdcf
1638	#define MSR_LASTBRANCH_16_INFO 0xdd0
1639	#define MSR_LASTBRANCH_17_INFO 0xdd1
1640	#define MSR_LASTBRANCH_18_INFO 0xdd2
1641	#define MSR_LASTBRANCH_19_INFO 0xdd3
1642	#define MSR_LASTBRANCH_20_INFO 0xdd4
1643	#define MSR_LASTBRANCH_21_INFO 0xdd5
1644	#define MSR_LASTBRANCH_22_INFO 0xdd6
1645	#define MSR_LASTBRANCH_23_INFO 0xdd7
1646	#define MSR_LASTBRANCH_24_INFO 0xdd8
1647	#define MSR_LASTBRANCH_25_INFO 0xdd9
1648	#define MSR_LASTBRANCH_26_INFO 0xdda
1649	#define MSR_LASTBRANCH_27_INFO 0xddb
1650	#define MSR_LASTBRANCH_28_INFO 0xddc
1651	#define MSR_LASTBRANCH_29_INFO 0xddd
1652	#define MSR_LASTBRANCH_30_INFO 0xdde
1653	#define MSR_LASTBRANCH_31_INFO 0xddf
1654
1655	/** LBR branch tracking selection MSR. */
1656	#define MSR_LASTBRANCH_SELECT 0x1c8
1657	/** LBR Top-of-stack MSR (index to most recent record). */
1658	#define MSR_LASTBRANCH_TOS 0x1c9
1659	/** @} */
1660
1661	/** @name Last event record registers.
1662	* @{ */
1663	/** Last event record source IP register. */
1664	#define MSR_LER_FROM_IP 0x1dd
1665	/** Last event record destination IP register. */
1666	#define MSR_LER_TO_IP 0x1de
1667	/** @} */
1668
1669	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1670	#define MSR_IA32_TSX_CTRL 0x122
1671
1672	/** Variable range MTRRs.
1673	* @{ */
1674	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1675	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1676	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1677	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1678	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1679	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1680	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1681	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1682	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1683	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1684	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1685	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1686	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1687	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1688	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1689	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1690	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1691	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1692	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1693	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1694	/** @} */
1695
1696	/** Fixed range MTRRs.
1697	* @{ */
1698	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1699	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1700	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1701	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1702	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1703	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1704	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1705	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1706	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1707	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1708	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1709	/** @} */
1710
1711	/** MTRR Default Type.
1712	* @{ */
1713	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1714	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1715	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1716	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1717	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1718	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1719	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1720	/** @} */
1721
1722	/** Variable-range MTRR physical mask valid. */
1723	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1724
1725	/** Global performance counter control facilities (Intel only). */
1726	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1727	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1728	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1729
1730	/** Precise Event Based sampling (Intel only). */
1731	#define MSR_IA32_PEBS_ENABLE 0x3F1
1732
1733	#define MSR_IA32_MC0_CTL 0x400
1734	#define MSR_IA32_MC0_STATUS 0x401
1735
1736	/** Basic VMX information. */
1737	#define MSR_IA32_VMX_BASIC 0x480
1738	/** Allowed settings for pin-based VM execution controls. */
1739	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1740	/** Allowed settings for proc-based VM execution controls. */
1741	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1742	/** Allowed settings for the VM-exit controls. */
1743	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1744	/** Allowed settings for the VM-entry controls. */
1745	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1746	/** Misc VMX info. */
1747	#define MSR_IA32_VMX_MISC 0x485
1748	/** Fixed cleared bits in CR0. */
1749	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1750	/** Fixed set bits in CR0. */
1751	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1752	/** Fixed cleared bits in CR4. */
1753	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1754	/** Fixed set bits in CR4. */
1755	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1756	/** Information for enumerating fields in the VMCS. */
1757	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1758	/** Allowed settings for secondary processor-based VM-execution controls. */
1759	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1760	/** EPT capabilities. */
1761	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1762	/** Allowed settings of all pin-based VM execution controls. */
1763	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1764	/** Allowed settings of all proc-based VM execution controls. */
1765	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1766	/** Allowed settings of all VMX exit controls. */
1767	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1768	/** Allowed settings of all VMX entry controls. */
1769	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1770	/** Allowed settings for the VM-function controls. */
1771	#define MSR_IA32_VMX_VMFUNC 0x491
1772	/** Tertiary processor-based VM execution controls. */
1773	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1774	/** Secondary VM-exit controls. */
1775	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
1776
1777	/** Intel PT - Enable and control for trace packet generation. */
1778	#define MSR_IA32_RTIT_CTL 0x570
1779
1780	/** DS Save Area (R/W). */
1781	#define MSR_IA32_DS_AREA 0x600
1782	/** Running Average Power Limit (RAPL) power units. */
1783	#define MSR_RAPL_POWER_UNIT 0x606
1784	/** Package C3 Interrupt Response Limit. */
1785	#define MSR_PKGC3_IRTL 0x60a
1786	/** Package C6/C7S Interrupt Response Limit 1. */
1787	#define MSR_PKGC_IRTL1 0x60b
1788	/** Package C6/C7S Interrupt Response Limit 2. */
1789	#define MSR_PKGC_IRTL2 0x60c
1790	/** Package C2 Residency Counter. */
1791	#define MSR_PKG_C2_RESIDENCY 0x60d
1792	/** PKG RAPL Power Limit Control. */
1793	#define MSR_PKG_POWER_LIMIT 0x610
1794	/** PKG Energy Status. */
1795	#define MSR_PKG_ENERGY_STATUS 0x611
1796	/** PKG Perf Status. */
1797	#define MSR_PKG_PERF_STATUS 0x613
1798	/** PKG RAPL Parameters. */
1799	#define MSR_PKG_POWER_INFO 0x614
1800	/** DRAM RAPL Power Limit Control. */
1801	#define MSR_DRAM_POWER_LIMIT 0x618
1802	/** DRAM Energy Status. */
1803	#define MSR_DRAM_ENERGY_STATUS 0x619
1804	/** DRAM Performance Throttling Status. */
1805	#define MSR_DRAM_PERF_STATUS 0x61b
1806	/** DRAM RAPL Parameters. */
1807	#define MSR_DRAM_POWER_INFO 0x61c
1808	/** Package C10 Residency Counter. */
1809	#define MSR_PKG_C10_RESIDENCY 0x632
1810	/** PP0 Energy Status. */
1811	#define MSR_PP0_ENERGY_STATUS 0x639
1812	/** PP1 Energy Status. */
1813	#define MSR_PP1_ENERGY_STATUS 0x641
1814	/** Turbo Activation Ratio. */
1815	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1816	/** Core Performance Limit Reasons. */
1817	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1818
1819	/** Userspace Control flow Enforcement Technology setting. */
1820	#define MSR_IA32_U_CET 0x6a0
1821	/** Supervisor space Control flow Enforcement Technology setting. */
1822	#define MSR_IA32_S_CET 0x6a2
1823	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
1824	* @{ */
1825	/** Enables the Shadow stack. */
1826	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
1827	/** Enables WRSS{D,Q}W instructions. */
1828	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
1829	/** Enables indirect branch tracking. */
1830	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
1831	/** Enable legacy compatibility treatment for indirect branch tracking. */
1832	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
1833	/** Enables the use of no-track prefix for indirect branch tracking. */
1834	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
1835	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
1836	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
1837	/** Suppresses indirect branch tracking. */
1838	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
1839	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
1840	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
1841	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
1842	* on a ENDBRANCH instruction. */
1843	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
1844	/** @} */
1845
1846	/** X2APIC MSR range start. */
1847	#define MSR_IA32_X2APIC_START 0x800
1848	/** X2APIC MSR - APIC ID Register. */
1849	#define MSR_IA32_X2APIC_ID 0x802
1850	/** X2APIC MSR - APIC Version Register. */
1851	#define MSR_IA32_X2APIC_VERSION 0x803
1852	/** X2APIC MSR - Task Priority Register. */
1853	#define MSR_IA32_X2APIC_TPR 0x808
1854	/** X2APIC MSR - Processor Priority register. */
1855	#define MSR_IA32_X2APIC_PPR 0x80A
1856	/** X2APIC MSR - End Of Interrupt register. */
1857	#define MSR_IA32_X2APIC_EOI 0x80B
1858	/** X2APIC MSR - Logical Destination Register. */
1859	#define MSR_IA32_X2APIC_LDR 0x80D
1860	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1861	#define MSR_IA32_X2APIC_SVR 0x80F
1862	/** X2APIC MSR - In-service Register (bits 31:0). */
1863	#define MSR_IA32_X2APIC_ISR0 0x810
1864	/** X2APIC MSR - In-service Register (bits 63:32). */
1865	#define MSR_IA32_X2APIC_ISR1 0x811
1866	/** X2APIC MSR - In-service Register (bits 95:64). */
1867	#define MSR_IA32_X2APIC_ISR2 0x812
1868	/** X2APIC MSR - In-service Register (bits 127:96). */
1869	#define MSR_IA32_X2APIC_ISR3 0x813
1870	/** X2APIC MSR - In-service Register (bits 159:128). */
1871	#define MSR_IA32_X2APIC_ISR4 0x814
1872	/** X2APIC MSR - In-service Register (bits 191:160). */
1873	#define MSR_IA32_X2APIC_ISR5 0x815
1874	/** X2APIC MSR - In-service Register (bits 223:192). */
1875	#define MSR_IA32_X2APIC_ISR6 0x816
1876	/** X2APIC MSR - In-service Register (bits 255:224). */
1877	#define MSR_IA32_X2APIC_ISR7 0x817
1878	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1879	#define MSR_IA32_X2APIC_TMR0 0x818
1880	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1881	#define MSR_IA32_X2APIC_TMR1 0x819
1882	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1883	#define MSR_IA32_X2APIC_TMR2 0x81A
1884	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1885	#define MSR_IA32_X2APIC_TMR3 0x81B
1886	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1887	#define MSR_IA32_X2APIC_TMR4 0x81C
1888	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1889	#define MSR_IA32_X2APIC_TMR5 0x81D
1890	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1891	#define MSR_IA32_X2APIC_TMR6 0x81E
1892	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1893	#define MSR_IA32_X2APIC_TMR7 0x81F
1894	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1895	#define MSR_IA32_X2APIC_IRR0 0x820
1896	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1897	#define MSR_IA32_X2APIC_IRR1 0x821
1898	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1899	#define MSR_IA32_X2APIC_IRR2 0x822
1900	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1901	#define MSR_IA32_X2APIC_IRR3 0x823
1902	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1903	#define MSR_IA32_X2APIC_IRR4 0x824
1904	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1905	#define MSR_IA32_X2APIC_IRR5 0x825
1906	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1907	#define MSR_IA32_X2APIC_IRR6 0x826
1908	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1909	#define MSR_IA32_X2APIC_IRR7 0x827
1910	/** X2APIC MSR - Error Status Register. */
1911	#define MSR_IA32_X2APIC_ESR 0x828
1912	/** X2APIC MSR - LVT CMCI Register. */
1913	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1914	/** X2APIC MSR - Interrupt Command Register. */
1915	#define MSR_IA32_X2APIC_ICR 0x830
1916	/** X2APIC MSR - LVT Timer Register. */
1917	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1918	/** X2APIC MSR - LVT Thermal Sensor Register. */
1919	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1920	/** X2APIC MSR - LVT Performance Counter Register. */
1921	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1922	/** X2APIC MSR - LVT LINT0 Register. */
1923	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1924	/** X2APIC MSR - LVT LINT1 Register. */
1925	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1926	/** X2APIC MSR - LVT Error Register . */
1927	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1928	/** X2APIC MSR - Timer Initial Count Register. */
1929	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1930	/** X2APIC MSR - Timer Current Count Register. */
1931	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1932	/** X2APIC MSR - Timer Divide Configuration Register. */
1933	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1934	/** X2APIC MSR - Self IPI. */
1935	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1936	/** X2APIC MSR range end. */
1937	#define MSR_IA32_X2APIC_END 0x8FF
1938	/** X2APIC MSR - LVT start range. */
1939	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1940	/** X2APIC MSR - LVT end range (inclusive). */
1941	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1942
1943	/** K6 EFER - Extended Feature Enable Register. */
1944	#define MSR_K6_EFER UINT32_C(0xc0000080)
1945	/** @todo document EFER */
1946	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1947	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1948	/** Bit 8 - LME - Long mode enabled. (R/W) */
1949	#define MSR_K6_EFER_LME RT_BIT_32(8)
1950	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1951	/** Bit 10 - LMA - Long mode active. (R) */
1952	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1953	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1954	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1955	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1956	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1957	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1958	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1959	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1960	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1961	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1962	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1963	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1964	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1965	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1966	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1967
1968	/** K6 STAR - SYSCALL/RET targets. */
1969	#define MSR_K6_STAR UINT32_C(0xc0000081)
1970	/** Shift value for getting the SYSRET CS and SS value. */
1971	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1972	/** Shift value for getting the SYSCALL CS and SS value. */
1973	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1974	/** Selector mask for use after shifting. */
1975	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1976	/** The mask which give the SYSCALL EIP. */
1977	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1978	/** K6 WHCR - Write Handling Control Register. */
1979	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1980	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1981	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1982	/** K6 PSOR - Processor State Observability Register. */
1983	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1984	/** K6 PFIR - Page Flush/Invalidate Register. */
1985	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1986
1987	/** Performance counter MSRs. (AMD only) */
1988	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1989	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1990	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1991	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1992	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1993	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1994	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1995	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1996
1997	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1998	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1999	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2000	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2001	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2002	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2003	/** K8 FS.base - The 64-bit base FS register. */
2004	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2005	/** K8 GS.base - The 64-bit base GS register. */
2006	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2007	/** K8 KernelGSbase - Used with SWAPGS. */
2008	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2009	/** K8 TSC_AUX - Used with RDTSCP. */
2010	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2011	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2012	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2013	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2014	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2015	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2016	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2017	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2018	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2019
2020	/** SMM MSRs. */
2021	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2022	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2023	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2024
2025	/** North bridge config? See BIOS & Kernel dev guides for
2026	* details. */
2027	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2028
2029	/** Hypertransport interrupt pending register.
2030	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2031	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2032
2033	/** SVM Control. */
2034	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2035	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2036	* features. */
2037	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2038	/** If set, non-intercepted INIT signals are converted to \#SX
2039	* exceptions. */
2040	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2041	/** Disables A20 masking. */
2042	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2043	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2044	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2045	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2046	* clear, EFER.SVME can be written normally. */
2047	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2048
2049	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2050	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2051	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2052	* host state during world switch. */
2053	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2054
2055	/** Virtualized speculation control for AMD processors.
2056	*
2057	* Unified interface among different CPU generations.
2058	* The VMM will set any architectural MSRs based on the CPU.
2059	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2060	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2061	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2062	/** Speculative Store Bypass Disable. */
2063	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2064
2065	/** @} */
2066
2067
2068	/** @name Page Table / Directory / Directory Pointers / L4.
2069	* @{
2070	*/
2071
2072	/** Page table/directory entry as an unsigned integer. */
2073	typedef uint32_t X86PGUINT;
2074	/** Pointer to a page table/directory table entry as an unsigned integer. */
2075	typedef X86PGUINT *PX86PGUINT;
2076	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2077	typedef X86PGUINT const *PCX86PGUINT;
2078
2079	/** Number of entries in a 32-bit PT/PD. */
2080	#define X86_PG_ENTRIES 1024
2081
2082
2083	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2084	typedef uint64_t X86PGPAEUINT;
2085	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2086	typedef X86PGPAEUINT *PX86PGPAEUINT;
2087	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2088	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2089
2090	/** Number of entries in a PAE PT/PD. */
2091	#define X86_PG_PAE_ENTRIES 512
2092	/** Number of entries in a PAE PDPT. */
2093	#define X86_PG_PAE_PDPE_ENTRIES 4
2094
2095	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2096	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2097	/** Number of entries in an AMD64 PDPT.
2098	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2099	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2100
2101	/** The size of a default page. */
2102	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2103	/** The page shift of a default page. */
2104	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2105	/** The default page offset mask. */
2106	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2107	/** The default page base mask for virtual addresses. */
2108	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2109	/** The default page base mask for virtual addresses - 32bit version. */
2110	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2111
2112	/** The size of a 4KB page. */
2113	#define X86_PAGE_4K_SIZE _4K
2114	/** The page shift of a 4KB page. */
2115	#define X86_PAGE_4K_SHIFT 12
2116	/** The 4KB page offset mask. */
2117	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2118	/** The 4KB page base mask for virtual addresses. */
2119	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2120	/** The 4KB page base mask for virtual addresses - 32bit version. */
2121	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2122
2123	/** The size of a 2MB page. */
2124	#define X86_PAGE_2M_SIZE _2M
2125	/** The page shift of a 2MB page. */
2126	#define X86_PAGE_2M_SHIFT 21
2127	/** The 2MB page offset mask. */
2128	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2129	/** The 2MB page base mask for virtual addresses. */
2130	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2131	/** The 2MB page base mask for virtual addresses - 32bit version. */
2132	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2133
2134	/** The size of a 4MB page. */
2135	#define X86_PAGE_4M_SIZE _4M
2136	/** The page shift of a 4MB page. */
2137	#define X86_PAGE_4M_SHIFT 22
2138	/** The 4MB page offset mask. */
2139	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2140	/** The 4MB page base mask for virtual addresses. */
2141	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2142	/** The 4MB page base mask for virtual addresses - 32bit version. */
2143	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2144
2145	/** The size of a 1GB page. */
2146	#define X86_PAGE_1G_SIZE _1G
2147	/** The page shift of a 1GB page. */
2148	#define X86_PAGE_1G_SHIFT 30
2149	/** The 1GB page offset mask. */
2150	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2151	/** The 1GB page base mask for virtual addresses. */
2152	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2153
2154	/**
2155	* Check if the given address is canonical.
2156	*/
2157	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2158
2159	/**
2160	* Gets the page base mask given the page shift.
2161	*/
2162	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2163
2164	/**
2165	* Gets the page offset mask given the page shift.
2166	*/
2167	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2168
2169
2170	/** @name Page Table Entry
2171	* @{
2172	*/
2173	/** Bit 0 - P - Present bit. */
2174	#define X86_PTE_BIT_P 0
2175	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2176	#define X86_PTE_BIT_RW 1
2177	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2178	#define X86_PTE_BIT_US 2
2179	/** Bit 3 - PWT - Page level write thru bit. */
2180	#define X86_PTE_BIT_PWT 3
2181	/** Bit 4 - PCD - Page level cache disable bit. */
2182	#define X86_PTE_BIT_PCD 4
2183	/** Bit 5 - A - Access bit. */
2184	#define X86_PTE_BIT_A 5
2185	/** Bit 6 - D - Dirty bit. */
2186	#define X86_PTE_BIT_D 6
2187	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2188	#define X86_PTE_BIT_PAT 7
2189	/** Bit 8 - G - Global flag. */
2190	#define X86_PTE_BIT_G 8
2191	/** Bits 63 - NX - PAE/LM - No execution flag. */
2192	#define X86_PTE_PAE_BIT_NX 63
2193
2194	/** Bit 0 - P - Present bit mask. */
2195	#define X86_PTE_P RT_BIT_32(0)
2196	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2197	#define X86_PTE_RW RT_BIT_32(1)
2198	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2199	#define X86_PTE_US RT_BIT_32(2)
2200	/** Bit 3 - PWT - Page level write thru bit mask. */
2201	#define X86_PTE_PWT RT_BIT_32(3)
2202	/** Bit 4 - PCD - Page level cache disable bit mask. */
2203	#define X86_PTE_PCD RT_BIT_32(4)
2204	/** Bit 5 - A - Access bit mask. */
2205	#define X86_PTE_A RT_BIT_32(5)
2206	/** Bit 6 - D - Dirty bit mask. */
2207	#define X86_PTE_D RT_BIT_32(6)
2208	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2209	#define X86_PTE_PAT RT_BIT_32(7)
2210	/** Bit 8 - G - Global bit mask. */
2211	#define X86_PTE_G RT_BIT_32(8)
2212
2213	/** Bits 9-11 - - Available for use to system software. */
2214	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2215	/** Bits 12-31 - - Physical Page number of the next level. */
2216	#define X86_PTE_PG_MASK ( 0xfffff000 )
2217
2218	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2219	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2220	/** Bits 63 - NX - PAE/LM - No execution flag. */
2221	#define X86_PTE_PAE_NX RT_BIT_64(63)
2222	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2223	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2224	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2225	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2226	/** No bits - - LM - MBZ bits when NX is active. */
2227	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2228	/** Bits 63 - - LM - MBZ bits when no NX. */
2229	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2230
2231	/**
2232	* Page table entry.
2233	*/
2234	typedef struct X86PTEBITS
2235	{
2236	/** Flags whether(=1) or not the page is present. */
2237	uint32_t u1Present : 1;
2238	/** Read(=0) / Write(=1) flag. */
2239	uint32_t u1Write : 1;
2240	/** User(=1) / Supervisor (=0) flag. */
2241	uint32_t u1User : 1;
2242	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2243	uint32_t u1WriteThru : 1;
2244	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2245	uint32_t u1CacheDisable : 1;
2246	/** Accessed flag.
2247	* Indicates that the page have been read or written to. */
2248	uint32_t u1Accessed : 1;
2249	/** Dirty flag.
2250	* Indicates that the page has been written to. */
2251	uint32_t u1Dirty : 1;
2252	/** Reserved / If PAT enabled, bit 2 of the index. */
2253	uint32_t u1PAT : 1;
2254	/** Global flag. (Ignored in all but final level.) */
2255	uint32_t u1Global : 1;
2256	/** Available for use to system software. */
2257	uint32_t u3Available : 3;
2258	/** Physical Page number of the next level. */
2259	uint32_t u20PageNo : 20;
2260	} X86PTEBITS;
2261	#ifndef VBOX_FOR_DTRACE_LIB
2262	AssertCompileSize(X86PTEBITS, 4);
2263	#endif
2264	/** Pointer to a page table entry. */
2265	typedef X86PTEBITS *PX86PTEBITS;
2266	/** Pointer to a const page table entry. */
2267	typedef const X86PTEBITS *PCX86PTEBITS;
2268
2269	/**
2270	* Page table entry.
2271	*/
2272	typedef union X86PTE
2273	{
2274	/** Unsigned integer view */
2275	X86PGUINT u;
2276	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2277	/** Bit field view. */
2278	X86PTEBITS n;
2279	#endif
2280	/** 32-bit view. */
2281	uint32_t au32[1];
2282	/** 16-bit view. */
2283	uint16_t au16[2];
2284	/** 8-bit view. */
2285	uint8_t au8[4];
2286	} X86PTE;
2287	#ifndef VBOX_FOR_DTRACE_LIB
2288	AssertCompileSize(X86PTE, 4);
2289	#endif
2290	/** Pointer to a page table entry. */
2291	typedef X86PTE *PX86PTE;
2292	/** Pointer to a const page table entry. */
2293	typedef const X86PTE *PCX86PTE;
2294
2295
2296	/**
2297	* PAE page table entry.
2298	*/
2299	typedef struct X86PTEPAEBITS
2300	{
2301	/** Flags whether(=1) or not the page is present. */
2302	uint32_t u1Present : 1;
2303	/** Read(=0) / Write(=1) flag. */
2304	uint32_t u1Write : 1;
2305	/** User(=1) / Supervisor(=0) flag. */
2306	uint32_t u1User : 1;
2307	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2308	uint32_t u1WriteThru : 1;
2309	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2310	uint32_t u1CacheDisable : 1;
2311	/** Accessed flag.
2312	* Indicates that the page have been read or written to. */
2313	uint32_t u1Accessed : 1;
2314	/** Dirty flag.
2315	* Indicates that the page has been written to. */
2316	uint32_t u1Dirty : 1;
2317	/** Reserved / If PAT enabled, bit 2 of the index. */
2318	uint32_t u1PAT : 1;
2319	/** Global flag. (Ignored in all but final level.) */
2320	uint32_t u1Global : 1;
2321	/** Available for use to system software. */
2322	uint32_t u3Available : 3;
2323	/** Physical Page number of the next level - Low Part. Don't use this. */
2324	uint32_t u20PageNoLow : 20;
2325	/** Physical Page number of the next level - High Part. Don't use this. */
2326	uint32_t u20PageNoHigh : 20;
2327	/** MBZ bits */
2328	uint32_t u11Reserved : 11;
2329	/** No Execute flag. */
2330	uint32_t u1NoExecute : 1;
2331	} X86PTEPAEBITS;
2332	#ifndef VBOX_FOR_DTRACE_LIB
2333	AssertCompileSize(X86PTEPAEBITS, 8);
2334	#endif
2335	/** Pointer to a page table entry. */
2336	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2337	/** Pointer to a page table entry. */
2338	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2339
2340	/**
2341	* PAE Page table entry.
2342	*/
2343	typedef union X86PTEPAE
2344	{
2345	/** Unsigned integer view */
2346	X86PGPAEUINT u;
2347	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2348	/** Bit field view. */
2349	X86PTEPAEBITS n;
2350	#endif
2351	/** 32-bit view. */
2352	uint32_t au32[2];
2353	/** 16-bit view. */
2354	uint16_t au16[4];
2355	/** 8-bit view. */
2356	uint8_t au8[8];
2357	} X86PTEPAE;
2358	#ifndef VBOX_FOR_DTRACE_LIB
2359	AssertCompileSize(X86PTEPAE, 8);
2360	#endif
2361	/** Pointer to a PAE page table entry. */
2362	typedef X86PTEPAE *PX86PTEPAE;
2363	/** Pointer to a const PAE page table entry. */
2364	typedef const X86PTEPAE *PCX86PTEPAE;
2365	/** @} */
2366
2367	/**
2368	* Page table.
2369	*/
2370	typedef struct X86PT
2371	{
2372	/** PTE Array. */
2373	X86PTE a[X86_PG_ENTRIES];
2374	} X86PT;
2375	#ifndef VBOX_FOR_DTRACE_LIB
2376	AssertCompileSize(X86PT, 4096);
2377	#endif
2378	/** Pointer to a page table. */
2379	typedef X86PT *PX86PT;
2380	/** Pointer to a const page table. */
2381	typedef const X86PT *PCX86PT;
2382
2383	/** The page shift to get the PT index. */
2384	#define X86_PT_SHIFT 12
2385	/** The PT index mask (apply to a shifted page address). */
2386	#define X86_PT_MASK 0x3ff
2387
2388
2389	/**
2390	* Page directory.
2391	*/
2392	typedef struct X86PTPAE
2393	{
2394	/** PTE Array. */
2395	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2396	} X86PTPAE;
2397	#ifndef VBOX_FOR_DTRACE_LIB
2398	AssertCompileSize(X86PTPAE, 4096);
2399	#endif
2400	/** Pointer to a page table. */
2401	typedef X86PTPAE *PX86PTPAE;
2402	/** Pointer to a const page table. */
2403	typedef const X86PTPAE *PCX86PTPAE;
2404
2405	/** The page shift to get the PA PTE index. */
2406	#define X86_PT_PAE_SHIFT 12
2407	/** The PAE PT index mask (apply to a shifted page address). */
2408	#define X86_PT_PAE_MASK 0x1ff
2409
2410
2411	/** @name 4KB Page Directory Entry
2412	* @{
2413	*/
2414	/** Bit 0 - P - Present bit. */
2415	#define X86_PDE_P RT_BIT_32(0)
2416	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2417	#define X86_PDE_RW RT_BIT_32(1)
2418	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2419	#define X86_PDE_US RT_BIT_32(2)
2420	/** Bit 3 - PWT - Page level write thru bit. */
2421	#define X86_PDE_PWT RT_BIT_32(3)
2422	/** Bit 4 - PCD - Page level cache disable bit. */
2423	#define X86_PDE_PCD RT_BIT_32(4)
2424	/** Bit 5 - A - Access bit. */
2425	#define X86_PDE_A RT_BIT_32(5)
2426	/** Bit 7 - PS - Page size attribute.
2427	* Clear mean 4KB pages, set means large pages (2/4MB). */
2428	#define X86_PDE_PS RT_BIT_32(7)
2429	/** Bits 9-11 - - Available for use to system software. */
2430	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2431	/** Bits 12-31 - - Physical Page number of the next level. */
2432	#define X86_PDE_PG_MASK ( 0xfffff000 )
2433
2434	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2435	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2436	/** Bits 63 - NX - PAE/LM - No execution flag. */
2437	#define X86_PDE_PAE_NX RT_BIT_64(63)
2438	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2439	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2440	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2441	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2442	/** Bit 7 - - LM - MBZ bits when NX is active. */
2443	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2444	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2445	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2446
2447	/**
2448	* Page directory entry.
2449	*/
2450	typedef struct X86PDEBITS
2451	{
2452	/** Flags whether(=1) or not the page is present. */
2453	uint32_t u1Present : 1;
2454	/** Read(=0) / Write(=1) flag. */
2455	uint32_t u1Write : 1;
2456	/** User(=1) / Supervisor (=0) flag. */
2457	uint32_t u1User : 1;
2458	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2459	uint32_t u1WriteThru : 1;
2460	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2461	uint32_t u1CacheDisable : 1;
2462	/** Accessed flag.
2463	* Indicates that the page has been read or written to. */
2464	uint32_t u1Accessed : 1;
2465	/** Reserved / Ignored (dirty bit). */
2466	uint32_t u1Reserved0 : 1;
2467	/** Size bit if PSE is enabled - in any event it's 0. */
2468	uint32_t u1Size : 1;
2469	/** Reserved / Ignored (global bit). */
2470	uint32_t u1Reserved1 : 1;
2471	/** Available for use to system software. */
2472	uint32_t u3Available : 3;
2473	/** Physical Page number of the next level. */
2474	uint32_t u20PageNo : 20;
2475	} X86PDEBITS;
2476	#ifndef VBOX_FOR_DTRACE_LIB
2477	AssertCompileSize(X86PDEBITS, 4);
2478	#endif
2479	/** Pointer to a page directory entry. */
2480	typedef X86PDEBITS *PX86PDEBITS;
2481	/** Pointer to a const page directory entry. */
2482	typedef const X86PDEBITS *PCX86PDEBITS;
2483
2484
2485	/**
2486	* PAE page directory entry.
2487	*/
2488	typedef struct X86PDEPAEBITS
2489	{
2490	/** Flags whether(=1) or not the page is present. */
2491	uint32_t u1Present : 1;
2492	/** Read(=0) / Write(=1) flag. */
2493	uint32_t u1Write : 1;
2494	/** User(=1) / Supervisor (=0) flag. */
2495	uint32_t u1User : 1;
2496	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2497	uint32_t u1WriteThru : 1;
2498	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2499	uint32_t u1CacheDisable : 1;
2500	/** Accessed flag.
2501	* Indicates that the page has been read or written to. */
2502	uint32_t u1Accessed : 1;
2503	/** Reserved / Ignored (dirty bit). */
2504	uint32_t u1Reserved0 : 1;
2505	/** Size bit if PSE is enabled - in any event it's 0. */
2506	uint32_t u1Size : 1;
2507	/** Reserved / Ignored (global bit). / */
2508	uint32_t u1Reserved1 : 1;
2509	/** Available for use to system software. */
2510	uint32_t u3Available : 3;
2511	/** Physical Page number of the next level - Low Part. Don't use! */
2512	uint32_t u20PageNoLow : 20;
2513	/** Physical Page number of the next level - High Part. Don't use! */
2514	uint32_t u20PageNoHigh : 20;
2515	/** MBZ bits */
2516	uint32_t u11Reserved : 11;
2517	/** No Execute flag. */
2518	uint32_t u1NoExecute : 1;
2519	} X86PDEPAEBITS;
2520	#ifndef VBOX_FOR_DTRACE_LIB
2521	AssertCompileSize(X86PDEPAEBITS, 8);
2522	#endif
2523	/** Pointer to a page directory entry. */
2524	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2525	/** Pointer to a const page directory entry. */
2526	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2527
2528	/** @} */
2529
2530
2531	/** @name 2/4MB Page Directory Entry
2532	* @{
2533	*/
2534	/** Bit 0 - P - Present bit. */
2535	#define X86_PDE4M_P RT_BIT_32(0)
2536	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2537	#define X86_PDE4M_RW RT_BIT_32(1)
2538	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2539	#define X86_PDE4M_US RT_BIT_32(2)
2540	/** Bit 3 - PWT - Page level write thru bit. */
2541	#define X86_PDE4M_PWT RT_BIT_32(3)
2542	/** Bit 4 - PCD - Page level cache disable bit. */
2543	#define X86_PDE4M_PCD RT_BIT_32(4)
2544	/** Bit 5 - A - Access bit. */
2545	#define X86_PDE4M_A RT_BIT_32(5)
2546	/** Bit 6 - D - Dirty bit. */
2547	#define X86_PDE4M_D RT_BIT_32(6)
2548	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2549	#define X86_PDE4M_PS RT_BIT_32(7)
2550	/** Bit 8 - G - Global flag. */
2551	#define X86_PDE4M_G RT_BIT_32(8)
2552	/** Bits 9-11 - AVL - Available for use to system software. */
2553	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2554	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2555	#define X86_PDE4M_PAT RT_BIT_32(12)
2556	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2557	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2558	/** Bits 22-31 - - Physical Page number. */
2559	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2560	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2561	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2562	/** The number of bits to the high part of the page number. */
2563	#define X86_PDE4M_PG_HIGH_SHIFT 19
2564	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2565	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2566
2567	/** Bits 21-51 - - PAE/LM - Physical Page number.
2568	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2569	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2570	/** Bits 63 - NX - PAE/LM - No execution flag. */
2571	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2572	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2573	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2574	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2575	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2576	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2577	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2578	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2579	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2580
2581	/**
2582	* 4MB page directory entry.
2583	*/
2584	typedef struct X86PDE4MBITS
2585	{
2586	/** Flags whether(=1) or not the page is present. */
2587	uint32_t u1Present : 1;
2588	/** Read(=0) / Write(=1) flag. */
2589	uint32_t u1Write : 1;
2590	/** User(=1) / Supervisor (=0) flag. */
2591	uint32_t u1User : 1;
2592	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2593	uint32_t u1WriteThru : 1;
2594	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2595	uint32_t u1CacheDisable : 1;
2596	/** Accessed flag.
2597	* Indicates that the page have been read or written to. */
2598	uint32_t u1Accessed : 1;
2599	/** Dirty flag.
2600	* Indicates that the page has been written to. */
2601	uint32_t u1Dirty : 1;
2602	/** Page size flag - always 1 for 4MB entries. */
2603	uint32_t u1Size : 1;
2604	/** Global flag. */
2605	uint32_t u1Global : 1;
2606	/** Available for use to system software. */
2607	uint32_t u3Available : 3;
2608	/** Reserved / If PAT enabled, bit 2 of the index. */
2609	uint32_t u1PAT : 1;
2610	/** Bits 32-39 of the page number on AMD64.
2611	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2612	uint32_t u8PageNoHigh : 8;
2613	/** Reserved. */
2614	uint32_t u1Reserved : 1;
2615	/** Physical Page number of the page. */
2616	uint32_t u10PageNo : 10;
2617	} X86PDE4MBITS;
2618	#ifndef VBOX_FOR_DTRACE_LIB
2619	AssertCompileSize(X86PDE4MBITS, 4);
2620	#endif
2621	/** Pointer to a page table entry. */
2622	typedef X86PDE4MBITS *PX86PDE4MBITS;
2623	/** Pointer to a const page table entry. */
2624	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2625
2626
2627	/**
2628	* 2MB PAE page directory entry.
2629	*/
2630	typedef struct X86PDE2MPAEBITS
2631	{
2632	/** Flags whether(=1) or not the page is present. */
2633	uint32_t u1Present : 1;
2634	/** Read(=0) / Write(=1) flag. */
2635	uint32_t u1Write : 1;
2636	/** User(=1) / Supervisor(=0) flag. */
2637	uint32_t u1User : 1;
2638	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2639	uint32_t u1WriteThru : 1;
2640	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2641	uint32_t u1CacheDisable : 1;
2642	/** Accessed flag.
2643	* Indicates that the page have been read or written to. */
2644	uint32_t u1Accessed : 1;
2645	/** Dirty flag.
2646	* Indicates that the page has been written to. */
2647	uint32_t u1Dirty : 1;
2648	/** Page size flag - always 1 for 2MB entries. */
2649	uint32_t u1Size : 1;
2650	/** Global flag. */
2651	uint32_t u1Global : 1;
2652	/** Available for use to system software. */
2653	uint32_t u3Available : 3;
2654	/** Reserved / If PAT enabled, bit 2 of the index. */
2655	uint32_t u1PAT : 1;
2656	/** Reserved. */
2657	uint32_t u9Reserved : 9;
2658	/** Physical Page number of the next level - Low part. Don't use! */
2659	uint32_t u10PageNoLow : 10;
2660	/** Physical Page number of the next level - High part. Don't use! */
2661	uint32_t u20PageNoHigh : 20;
2662	/** MBZ bits */
2663	uint32_t u11Reserved : 11;
2664	/** No Execute flag. */
2665	uint32_t u1NoExecute : 1;
2666	} X86PDE2MPAEBITS;
2667	#ifndef VBOX_FOR_DTRACE_LIB
2668	AssertCompileSize(X86PDE2MPAEBITS, 8);
2669	#endif
2670	/** Pointer to a 2MB PAE page table entry. */
2671	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2672	/** Pointer to a 2MB PAE page table entry. */
2673	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2674
2675	/** @} */
2676
2677	/**
2678	* Page directory entry.
2679	*/
2680	typedef union X86PDE
2681	{
2682	/** Unsigned integer view. */
2683	X86PGUINT u;
2684	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2685	/** Normal view. */
2686	X86PDEBITS n;
2687	/** 4MB view (big). */
2688	X86PDE4MBITS b;
2689	#endif
2690	/** 8 bit unsigned integer view. */
2691	uint8_t au8[4];
2692	/** 16 bit unsigned integer view. */
2693	uint16_t au16[2];
2694	/** 32 bit unsigned integer view. */
2695	uint32_t au32[1];
2696	} X86PDE;
2697	#ifndef VBOX_FOR_DTRACE_LIB
2698	AssertCompileSize(X86PDE, 4);
2699	#endif
2700	/** Pointer to a page directory entry. */
2701	typedef X86PDE *PX86PDE;
2702	/** Pointer to a const page directory entry. */
2703	typedef const X86PDE *PCX86PDE;
2704
2705	/**
2706	* PAE page directory entry.
2707	*/
2708	typedef union X86PDEPAE
2709	{
2710	/** Unsigned integer view. */
2711	X86PGPAEUINT u;
2712	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2713	/** Normal view. */
2714	X86PDEPAEBITS n;
2715	/** 2MB page view (big). */
2716	X86PDE2MPAEBITS b;
2717	#endif
2718	/** 8 bit unsigned integer view. */
2719	uint8_t au8[8];
2720	/** 16 bit unsigned integer view. */
2721	uint16_t au16[4];
2722	/** 32 bit unsigned integer view. */
2723	uint32_t au32[2];
2724	} X86PDEPAE;
2725	#ifndef VBOX_FOR_DTRACE_LIB
2726	AssertCompileSize(X86PDEPAE, 8);
2727	#endif
2728	/** Pointer to a page directory entry. */
2729	typedef X86PDEPAE *PX86PDEPAE;
2730	/** Pointer to a const page directory entry. */
2731	typedef const X86PDEPAE *PCX86PDEPAE;
2732
2733	/**
2734	* Page directory.
2735	*/
2736	typedef struct X86PD
2737	{
2738	/** PDE Array. */
2739	X86PDE a[X86_PG_ENTRIES];
2740	} X86PD;
2741	#ifndef VBOX_FOR_DTRACE_LIB
2742	AssertCompileSize(X86PD, 4096);
2743	#endif
2744	/** Pointer to a page directory. */
2745	typedef X86PD *PX86PD;
2746	/** Pointer to a const page directory. */
2747	typedef const X86PD *PCX86PD;
2748
2749	/** The page shift to get the PD index. */
2750	#define X86_PD_SHIFT 22
2751	/** The PD index mask (apply to a shifted page address). */
2752	#define X86_PD_MASK 0x3ff
2753
2754
2755	/**
2756	* PAE page directory.
2757	*/
2758	typedef struct X86PDPAE
2759	{
2760	/** PDE Array. */
2761	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2762	} X86PDPAE;
2763	#ifndef VBOX_FOR_DTRACE_LIB
2764	AssertCompileSize(X86PDPAE, 4096);
2765	#endif
2766	/** Pointer to a PAE page directory. */
2767	typedef X86PDPAE *PX86PDPAE;
2768	/** Pointer to a const PAE page directory. */
2769	typedef const X86PDPAE *PCX86PDPAE;
2770
2771	/** The page shift to get the PAE PD index. */
2772	#define X86_PD_PAE_SHIFT 21
2773	/** The PAE PD index mask (apply to a shifted page address). */
2774	#define X86_PD_PAE_MASK 0x1ff
2775
2776
2777	/** @name Page Directory Pointer Table Entry (PAE)
2778	* @{
2779	*/
2780	/** Bit 0 - P - Present bit. */
2781	#define X86_PDPE_P RT_BIT_32(0)
2782	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2783	#define X86_PDPE_RW RT_BIT_32(1)
2784	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2785	#define X86_PDPE_US RT_BIT_32(2)
2786	/** Bit 3 - PWT - Page level write thru bit. */
2787	#define X86_PDPE_PWT RT_BIT_32(3)
2788	/** Bit 4 - PCD - Page level cache disable bit. */
2789	#define X86_PDPE_PCD RT_BIT_32(4)
2790	/** Bit 5 - A - Access bit. Long Mode only. */
2791	#define X86_PDPE_A RT_BIT_32(5)
2792	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2793	#define X86_PDPE_LM_PS RT_BIT_32(7)
2794	/** Bits 9-11 - - Available for use to system software. */
2795	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2796	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2797	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2798	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2799	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2800	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2801	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2802	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2803	#define X86_PDPE_LM_NX RT_BIT_64(63)
2804	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2805	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2806	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2807	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2808	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2809	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2810	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2811	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2812
2813
2814	/**
2815	* Page directory pointer table entry.
2816	*/
2817	typedef struct X86PDPEBITS
2818	{
2819	/** Flags whether(=1) or not the page is present. */
2820	uint32_t u1Present : 1;
2821	/** Chunk of reserved bits. */
2822	uint32_t u2Reserved : 2;
2823	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2824	uint32_t u1WriteThru : 1;
2825	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2826	uint32_t u1CacheDisable : 1;
2827	/** Chunk of reserved bits. */
2828	uint32_t u4Reserved : 4;
2829	/** Available for use to system software. */
2830	uint32_t u3Available : 3;
2831	/** Physical Page number of the next level - Low Part. Don't use! */
2832	uint32_t u20PageNoLow : 20;
2833	/** Physical Page number of the next level - High Part. Don't use! */
2834	uint32_t u20PageNoHigh : 20;
2835	/** MBZ bits */
2836	uint32_t u12Reserved : 12;
2837	} X86PDPEBITS;
2838	#ifndef VBOX_FOR_DTRACE_LIB
2839	AssertCompileSize(X86PDPEBITS, 8);
2840	#endif
2841	/** Pointer to a page directory pointer table entry. */
2842	typedef X86PDPEBITS *PX86PTPEBITS;
2843	/** Pointer to a const page directory pointer table entry. */
2844	typedef const X86PDPEBITS *PCX86PTPEBITS;
2845
2846	/**
2847	* Page directory pointer table entry. AMD64 version
2848	*/
2849	typedef struct X86PDPEAMD64BITS
2850	{
2851	/** Flags whether(=1) or not the page is present. */
2852	uint32_t u1Present : 1;
2853	/** Read(=0) / Write(=1) flag. */
2854	uint32_t u1Write : 1;
2855	/** User(=1) / Supervisor (=0) flag. */
2856	uint32_t u1User : 1;
2857	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2858	uint32_t u1WriteThru : 1;
2859	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2860	uint32_t u1CacheDisable : 1;
2861	/** Accessed flag.
2862	* Indicates that the page have been read or written to. */
2863	uint32_t u1Accessed : 1;
2864	/** Chunk of reserved bits. */
2865	uint32_t u3Reserved : 3;
2866	/** Available for use to system software. */
2867	uint32_t u3Available : 3;
2868	/** Physical Page number of the next level - Low Part. Don't use! */
2869	uint32_t u20PageNoLow : 20;
2870	/** Physical Page number of the next level - High Part. Don't use! */
2871	uint32_t u20PageNoHigh : 20;
2872	/** MBZ bits */
2873	uint32_t u11Reserved : 11;
2874	/** No Execute flag. */
2875	uint32_t u1NoExecute : 1;
2876	} X86PDPEAMD64BITS;
2877	#ifndef VBOX_FOR_DTRACE_LIB
2878	AssertCompileSize(X86PDPEAMD64BITS, 8);
2879	#endif
2880	/** Pointer to a page directory pointer table entry. */
2881	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2882	/** Pointer to a const page directory pointer table entry. */
2883	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2884
2885	/**
2886	* Page directory pointer table entry for 1GB page. (AMD64 only)
2887	*/
2888	typedef struct X86PDPE1GB
2889	{
2890	/** 0: Flags whether(=1) or not the page is present. */
2891	uint32_t u1Present : 1;
2892	/** 1: Read(=0) / Write(=1) flag. */
2893	uint32_t u1Write : 1;
2894	/** 2: User(=1) / Supervisor (=0) flag. */
2895	uint32_t u1User : 1;
2896	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2897	uint32_t u1WriteThru : 1;
2898	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2899	uint32_t u1CacheDisable : 1;
2900	/** 5: Accessed flag.
2901	* Indicates that the page have been read or written to. */
2902	uint32_t u1Accessed : 1;
2903	/** 6: Dirty flag for 1GB pages. */
2904	uint32_t u1Dirty : 1;
2905	/** 7: Indicates 1GB page if set. */
2906	uint32_t u1Size : 1;
2907	/** 8: Global 1GB page. */
2908	uint32_t u1Global: 1;
2909	/** 9-11: Available for use to system software. */
2910	uint32_t u3Available : 3;
2911	/** 12: PAT bit for 1GB page. */
2912	uint32_t u1PAT : 1;
2913	/** 13-29: MBZ bits. */
2914	uint32_t u17Reserved : 17;
2915	/** 30-31: Physical page number - Low Part. Don't use! */
2916	uint32_t u2PageNoLow : 2;
2917	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2918	uint32_t u20PageNoHigh : 20;
2919	/** 52-62: MBZ bits */
2920	uint32_t u11Reserved : 11;
2921	/** 63: No Execute flag. */
2922	uint32_t u1NoExecute : 1;
2923	} X86PDPE1GB;
2924	#ifndef VBOX_FOR_DTRACE_LIB
2925	AssertCompileSize(X86PDPE1GB, 8);
2926	#endif
2927	/** Pointer to a page directory pointer table entry for a 1GB page. */
2928	typedef X86PDPE1GB *PX86PDPE1GB;
2929	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2930	typedef const X86PDPE1GB *PCX86PDPE1GB;
2931
2932	/**
2933	* Page directory pointer table entry.
2934	*/
2935	typedef union X86PDPE
2936	{
2937	/** Unsigned integer view. */
2938	X86PGPAEUINT u;
2939	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2940	/** Normal view. */
2941	X86PDPEBITS n;
2942	/** AMD64 view. */
2943	X86PDPEAMD64BITS lm;
2944	/** AMD64 big view. */
2945	X86PDPE1GB b;
2946	#endif
2947	/** 8 bit unsigned integer view. */
2948	uint8_t au8[8];
2949	/** 16 bit unsigned integer view. */
2950	uint16_t au16[4];
2951	/** 32 bit unsigned integer view. */
2952	uint32_t au32[2];
2953	} X86PDPE;
2954	#ifndef VBOX_FOR_DTRACE_LIB
2955	AssertCompileSize(X86PDPE, 8);
2956	#endif
2957	/** Pointer to a page directory pointer table entry. */
2958	typedef X86PDPE *PX86PDPE;
2959	/** Pointer to a const page directory pointer table entry. */
2960	typedef const X86PDPE *PCX86PDPE;
2961
2962
2963	/**
2964	* Page directory pointer table.
2965	*/
2966	typedef struct X86PDPT
2967	{
2968	/** PDE Array. */
2969	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2970	} X86PDPT;
2971	#ifndef VBOX_FOR_DTRACE_LIB
2972	AssertCompileSize(X86PDPT, 4096);
2973	#endif
2974	/** Pointer to a page directory pointer table. */
2975	typedef X86PDPT *PX86PDPT;
2976	/** Pointer to a const page directory pointer table. */
2977	typedef const X86PDPT *PCX86PDPT;
2978
2979	/** The page shift to get the PDPT index. */
2980	#define X86_PDPT_SHIFT 30
2981	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2982	#define X86_PDPT_MASK_PAE 0x3
2983	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2984	#define X86_PDPT_MASK_AMD64 0x1ff
2985
2986	/** @} */
2987
2988
2989	/** @name Page Map Level-4 Entry (Long Mode PAE)
2990	* @{
2991	*/
2992	/** Bit 0 - P - Present bit. */
2993	#define X86_PML4E_P RT_BIT_32(0)
2994	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2995	#define X86_PML4E_RW RT_BIT_32(1)
2996	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2997	#define X86_PML4E_US RT_BIT_32(2)
2998	/** Bit 3 - PWT - Page level write thru bit. */
2999	#define X86_PML4E_PWT RT_BIT_32(3)
3000	/** Bit 4 - PCD - Page level cache disable bit. */
3001	#define X86_PML4E_PCD RT_BIT_32(4)
3002	/** Bit 5 - A - Access bit. */
3003	#define X86_PML4E_A RT_BIT_32(5)
3004	/** Bits 9-11 - - Available for use to system software. */
3005	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3006	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3007	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3008	/** Bits 8, 7 - - MBZ bits when NX is active. */
3009	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3010	/** Bits 63, 7 - - MBZ bits when no NX. */
3011	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3012	/** Bits 63 - NX - PAE - No execution flag. */
3013	#define X86_PML4E_NX RT_BIT_64(63)
3014
3015	/**
3016	* Page Map Level-4 Entry
3017	*/
3018	typedef struct X86PML4EBITS
3019	{
3020	/** Flags whether(=1) or not the page is present. */
3021	uint32_t u1Present : 1;
3022	/** Read(=0) / Write(=1) flag. */
3023	uint32_t u1Write : 1;
3024	/** User(=1) / Supervisor (=0) flag. */
3025	uint32_t u1User : 1;
3026	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3027	uint32_t u1WriteThru : 1;
3028	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3029	uint32_t u1CacheDisable : 1;
3030	/** Accessed flag.
3031	* Indicates that the page have been read or written to. */
3032	uint32_t u1Accessed : 1;
3033	/** Chunk of reserved bits. */
3034	uint32_t u3Reserved : 3;
3035	/** Available for use to system software. */
3036	uint32_t u3Available : 3;
3037	/** Physical Page number of the next level - Low Part. Don't use! */
3038	uint32_t u20PageNoLow : 20;
3039	/** Physical Page number of the next level - High Part. Don't use! */
3040	uint32_t u20PageNoHigh : 20;
3041	/** MBZ bits */
3042	uint32_t u11Reserved : 11;
3043	/** No Execute flag. */
3044	uint32_t u1NoExecute : 1;
3045	} X86PML4EBITS;
3046	#ifndef VBOX_FOR_DTRACE_LIB
3047	AssertCompileSize(X86PML4EBITS, 8);
3048	#endif
3049	/** Pointer to a page map level-4 entry. */
3050	typedef X86PML4EBITS *PX86PML4EBITS;
3051	/** Pointer to a const page map level-4 entry. */
3052	typedef const X86PML4EBITS *PCX86PML4EBITS;
3053
3054	/**
3055	* Page Map Level-4 Entry.
3056	*/
3057	typedef union X86PML4E
3058	{
3059	/** Unsigned integer view. */
3060	X86PGPAEUINT u;
3061	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3062	/** Normal view. */
3063	X86PML4EBITS n;
3064	#endif
3065	/** 8 bit unsigned integer view. */
3066	uint8_t au8[8];
3067	/** 16 bit unsigned integer view. */
3068	uint16_t au16[4];
3069	/** 32 bit unsigned integer view. */
3070	uint32_t au32[2];
3071	} X86PML4E;
3072	#ifndef VBOX_FOR_DTRACE_LIB
3073	AssertCompileSize(X86PML4E, 8);
3074	#endif
3075	/** Pointer to a page map level-4 entry. */
3076	typedef X86PML4E *PX86PML4E;
3077	/** Pointer to a const page map level-4 entry. */
3078	typedef const X86PML4E *PCX86PML4E;
3079
3080
3081	/**
3082	* Page Map Level-4.
3083	*/
3084	typedef struct X86PML4
3085	{
3086	/** PDE Array. */
3087	X86PML4E a[X86_PG_PAE_ENTRIES];
3088	} X86PML4;
3089	#ifndef VBOX_FOR_DTRACE_LIB
3090	AssertCompileSize(X86PML4, 4096);
3091	#endif
3092	/** Pointer to a page map level-4. */
3093	typedef X86PML4 *PX86PML4;
3094	/** Pointer to a const page map level-4. */
3095	typedef const X86PML4 *PCX86PML4;
3096
3097	/** The page shift to get the PML4 index. */
3098	#define X86_PML4_SHIFT 39
3099	/** The PML4 index mask (apply to a shifted page address). */
3100	#define X86_PML4_MASK 0x1ff
3101
3102	/** @} */
3103
3104	/** @} */
3105
3106	/**
3107	* Intel PCID invalidation types.
3108	*/
3109	/** Individual address invalidation. */
3110	#define X86_INVPCID_TYPE_INDV_ADDR 0
3111	/** Single-context invalidation. */
3112	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3113	/** All-context including globals invalidation. */
3114	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3115	/** All-context excluding globals invalidation. */
3116	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3117	/** The maximum valid invalidation type value. */
3118	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3119
3120
3121	/** @name Special FPU integer values.
3122	* @{ */
3123	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3124	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3125	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3126	/** @} */
3127
3128	/**
3129	* 32-bit protected mode FSTENV image.
3130	*/
3131	typedef struct X86FSTENV32P
3132	{
3133	uint16_t FCW; /*< 0x00 /
3134	uint16_t padding1; /*< 0x02 /
3135	uint16_t FSW; /*< 0x04 /
3136	uint16_t padding2; /*< 0x06 /
3137	uint16_t FTW; /*< 0x08 /
3138	uint16_t padding3; /*< 0x0a /
3139	uint32_t FPUIP; /*< 0x0c /
3140	uint16_t FPUCS; /*< 0x10 /
3141	uint16_t FOP; /*< 0x12 /
3142	uint32_t FPUDP; /*< 0x14 /
3143	uint16_t FPUDS; /*< 0x18 /
3144	uint16_t padding4; /*< 0x1a /
3145	} X86FSTENV32P;
3146	#ifndef VBOX_FOR_DTRACE_LIB
3147	AssertCompileSize(X86FSTENV32P, 0x1c);
3148	#endif
3149	/** Pointer to a 32-bit protected mode FSTENV image. */
3150	typedef X86FSTENV32P *PX86FSTENV32P;
3151	/** Pointer to a const 32-bit protected mode FSTENV image. */
3152	typedef X86FSTENV32P const *PCX86FSTENV32P;
3153
3154
3155	/**
3156	* 80-bit MMX/FPU register type.
3157	*/
3158	typedef struct X86FPUMMX
3159	{
3160	uint8_t reg[10];
3161	} X86FPUMMX;
3162	#ifndef VBOX_FOR_DTRACE_LIB
3163	AssertCompileSize(X86FPUMMX, 10);
3164	#endif
3165	/** Pointer to a 80-bit MMX/FPU register type. */
3166	typedef X86FPUMMX *PX86FPUMMX;
3167	/** Pointer to a const 80-bit MMX/FPU register type. */
3168	typedef const X86FPUMMX *PCX86FPUMMX;
3169
3170	/** FPU (x87) register. */
3171	typedef union X86FPUREG
3172	{
3173	/** MMX view. */
3174	uint64_t mmx;
3175	/** FPU view - todo. */
3176	X86FPUMMX fpu;
3177	/** Extended precision floating point view. */
3178	RTFLOAT80U r80;
3179	/** Extended precision floating point view v2 */
3180	RTFLOAT80U2 r80Ex;
3181	/** 8-bit view. */
3182	uint8_t au8[16];
3183	/** 16-bit view. */
3184	uint16_t au16[8];
3185	/** 32-bit view. */
3186	uint32_t au32[4];
3187	/** 64-bit view. */
3188	uint64_t au64[2];
3189	/** 128-bit view. (yeah, very helpful) */
3190	uint128_t au128[1];
3191	} X86FPUREG;
3192	#ifndef VBOX_FOR_DTRACE_LIB
3193	AssertCompileSize(X86FPUREG, 16);
3194	#endif
3195	/** Pointer to a FPU register. */
3196	typedef X86FPUREG *PX86FPUREG;
3197	/** Pointer to a const FPU register. */
3198	typedef X86FPUREG const *PCX86FPUREG;
3199
3200	/** FPU (x87) register - v2 with correct size. */
3201	#pragma pack(1)
3202	typedef union X86FPUREG2
3203	{
3204	/** MMX view. */
3205	uint64_t mmx;
3206	/** FPU view - todo. */
3207	X86FPUMMX fpu;
3208	/** Extended precision floating point view. */
3209	RTFLOAT80U r80;
3210	/** 8-bit view. */
3211	uint8_t au8[10];
3212	/** 16-bit view. */
3213	uint16_t au16[5];
3214	/** 32-bit view. */
3215	uint32_t au32[2];
3216	/** 64-bit view. */
3217	uint64_t au64[1];
3218	} X86FPUREG2;
3219	#pragma pack()
3220	#ifndef VBOX_FOR_DTRACE_LIB
3221	AssertCompileSize(X86FPUREG2, 10);
3222	#endif
3223	/** Pointer to a FPU register - v2. */
3224	typedef X86FPUREG2 *PX86FPUREG2;
3225	/** Pointer to a const FPU register - v2. */
3226	typedef X86FPUREG2 const *PCX86FPUREG2;
3227
3228	/**
3229	* XMM register union.
3230	*/
3231	typedef union X86XMMREG
3232	{
3233	/** XMM Register view. */
3234	uint128_t xmm;
3235	/** 8-bit view. */
3236	uint8_t au8[16];
3237	/** 16-bit view. */
3238	uint16_t au16[8];
3239	/** 32-bit view. */
3240	uint32_t au32[4];
3241	/** 64-bit view. */
3242	uint64_t au64[2];
3243	/** Signed 8-bit view. */
3244	int8_t ai8[16];
3245	/** Signed 16-bit view. */
3246	int16_t ai16[8];
3247	/** Signed 32-bit view. */
3248	int32_t ai32[4];
3249	/** Signed 64-bit view. */
3250	int64_t ai64[2];
3251	/** 128-bit view. (yeah, very helpful) */
3252	uint128_t au128[1];
3253	/** Single precision floating point view. */
3254	RTFLOAT32U ar32[4];
3255	/** Double precision floating point view. */
3256	RTFLOAT64U ar64[2];
3257	#ifndef VBOX_FOR_DTRACE_LIB
3258	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3259	RTUINT128U uXmm;
3260	#endif
3261	} X86XMMREG;
3262	#ifndef VBOX_FOR_DTRACE_LIB
3263	AssertCompileSize(X86XMMREG, 16);
3264	#endif
3265	/** Pointer to an XMM register state. */
3266	typedef X86XMMREG *PX86XMMREG;
3267	/** Pointer to a const XMM register state. */
3268	typedef X86XMMREG const *PCX86XMMREG;
3269
3270	/**
3271	* YMM register union.
3272	*/
3273	typedef union X86YMMREG
3274	{
3275	/** YMM register view. */
3276	RTUINT256U ymm;
3277	/** 8-bit view. */
3278	uint8_t au8[32];
3279	/** 16-bit view. */
3280	uint16_t au16[16];
3281	/** 32-bit view. */
3282	uint32_t au32[8];
3283	/** 64-bit view. */
3284	uint64_t au64[4];
3285	/** 128-bit view. (yeah, very helpful) */
3286	uint128_t au128[2];
3287	/** Single precision floating point view. */
3288	RTFLOAT32U ar32[8];
3289	/** Double precision floating point view. */
3290	RTFLOAT64U ar64[4];
3291	/** XMM sub register view. */
3292	X86XMMREG aXmm[2];
3293	} X86YMMREG;
3294	#ifndef VBOX_FOR_DTRACE_LIB
3295	AssertCompileSize(X86YMMREG, 32);
3296	#endif
3297	/** Pointer to an YMM register state. */
3298	typedef X86YMMREG *PX86YMMREG;
3299	/** Pointer to a const YMM register state. */
3300	typedef X86YMMREG const *PCX86YMMREG;
3301
3302	/**
3303	* ZMM register union.
3304	*/
3305	typedef union X86ZMMREG
3306	{
3307	/** 8-bit view. */
3308	uint8_t au8[64];
3309	/** 16-bit view. */
3310	uint16_t au16[32];
3311	/** 32-bit view. */
3312	uint32_t au32[16];
3313	/** 64-bit view. */
3314	uint64_t au64[8];
3315	/** 128-bit view. (yeah, very helpful) */
3316	uint128_t au128[4];
3317	/** Single precision floating point view. */
3318	RTFLOAT32U ar32[16];
3319	/** Double precision floating point view. */
3320	RTFLOAT64U ar64[8];
3321	/** XMM sub register view. */
3322	X86XMMREG aXmm[4];
3323	/** YMM sub register view. */
3324	X86YMMREG aYmm[2];
3325	} X86ZMMREG;
3326	#ifndef VBOX_FOR_DTRACE_LIB
3327	AssertCompileSize(X86ZMMREG, 64);
3328	#endif
3329	/** Pointer to an ZMM register state. */
3330	typedef X86ZMMREG *PX86ZMMREG;
3331	/** Pointer to a const ZMM register state. */
3332	typedef X86ZMMREG const *PCX86ZMMREG;
3333
3334
3335	/**
3336	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3337	*/
3338	#pragma pack(1)
3339	typedef struct X86FPUSTATE
3340	{
3341	/** 0x00 - Control word. */
3342	uint16_t FCW;
3343	/** 0x02 - Alignment word */
3344	uint16_t Dummy1;
3345	/** 0x04 - Status word. */
3346	uint16_t FSW;
3347	/** 0x06 - Alignment word */
3348	uint16_t Dummy2;
3349	/** 0x08 - Tag word */
3350	uint16_t FTW;
3351	/** 0x0a - Alignment word */
3352	uint16_t Dummy3;
3353
3354	/** 0x0c - Instruction pointer. */
3355	uint32_t FPUIP;
3356	/** 0x10 - Code selector. */
3357	uint16_t CS;
3358	/** 0x12 - Opcode. */
3359	uint16_t FOP;
3360	/** 0x14 - Data pointer. */
3361	uint32_t FPUOO;
3362	/** 0x18 - FOS. */
3363	uint16_t FPUOS;
3364	/** 0x0a - Alignment word */
3365	uint16_t Dummy4;
3366	/** 0x1c - FPU register. */
3367	X86FPUREG2 regs[8];
3368	} X86FPUSTATE;
3369	#pragma pack()
3370	AssertCompileSize(X86FPUSTATE, 108);
3371	/** Pointer to a FPU state. */
3372	typedef X86FPUSTATE *PX86FPUSTATE;
3373	/** Pointer to a const FPU state. */
3374	typedef const X86FPUSTATE *PCX86FPUSTATE;
3375
3376	/**
3377	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3378	*/
3379	#pragma pack(1)
3380	typedef struct X86FXSTATE
3381	{
3382	/** 0x00 - Control word. */
3383	uint16_t FCW;
3384	/** 0x02 - Status word. */
3385	uint16_t FSW;
3386	/** 0x04 - Tag word. (The upper byte is always zero.) */
3387	uint16_t FTW;
3388	/** 0x06 - Opcode. */
3389	uint16_t FOP;
3390	/** 0x08 - Instruction pointer. */
3391	uint32_t FPUIP;
3392	/** 0x0c - Code selector. */
3393	uint16_t CS;
3394	uint16_t Rsrvd1;
3395	/** 0x10 - Data pointer. */
3396	uint32_t FPUDP;
3397	/** 0x14 - Data segment */
3398	uint16_t DS;
3399	/** 0x16 */
3400	uint16_t Rsrvd2;
3401	/** 0x18 */
3402	uint32_t MXCSR;
3403	/** 0x1c */
3404	uint32_t MXCSR_MASK;
3405	/** 0x20 - FPU registers. */
3406	X86FPUREG aRegs[8];
3407	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3408	X86XMMREG aXMM[16];
3409	/* - offset 416 - */
3410	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3411	/* - offset 464 - Software usable reserved bits. */
3412	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3413	} X86FXSTATE;
3414	#pragma pack()
3415	/** Pointer to a FPU Extended state. */
3416	typedef X86FXSTATE *PX86FXSTATE;
3417	/** Pointer to a const FPU Extended state. */
3418	typedef const X86FXSTATE *PCX86FXSTATE;
3419
3420	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3421	* magic. Don't forget to update x86.mac if you change this! */
3422	#define X86_OFF_FXSTATE_RSVD 0x1d0
3423	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3424	* forget to update x86.mac if you change this!
3425	* @todo r=bird: This has nothing what-so-ever to do here.... */
3426	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3427	#ifndef VBOX_FOR_DTRACE_LIB
3428	AssertCompileSize(X86FXSTATE, 512);
3429	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3430	#endif
3431
3432	/** @name FPU status word flags.
3433	* @{ */
3434	/** Exception Flag: Invalid operation. */
3435	#define X86_FSW_IE RT_BIT_32(0)
3436	#define X86_FSW_IE_BIT 0
3437	/** Exception Flag: Denormalized operand. */
3438	#define X86_FSW_DE RT_BIT_32(1)
3439	#define X86_FSW_DE_BIT 1
3440	/** Exception Flag: Zero divide. */
3441	#define X86_FSW_ZE RT_BIT_32(2)
3442	#define X86_FSW_ZE_BIT 2
3443	/** Exception Flag: Overflow. */
3444	#define X86_FSW_OE RT_BIT_32(3)
3445	#define X86_FSW_OE_BIT 3
3446	/** Exception Flag: Underflow. */
3447	#define X86_FSW_UE RT_BIT_32(4)
3448	#define X86_FSW_UE_BIT 4
3449	/** Exception Flag: Precision. */
3450	#define X86_FSW_PE RT_BIT_32(5)
3451	#define X86_FSW_PE_BIT 5
3452	/** Stack fault. */
3453	#define X86_FSW_SF RT_BIT_32(6)
3454	#define X86_FSW_SF_BIT 6
3455	/** Error summary status. */
3456	#define X86_FSW_ES RT_BIT_32(7)
3457	#define X86_FSW_ES_BIT 7
3458	/** Mask of exceptions flags, excluding the summary bit. */
3459	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3460	/** Mask of exceptions flags, including the summary bit. */
3461	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3462	/** Condition code 0. */
3463	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3464	#define X86_FSW_C0_BIT 8
3465	/** Condition code 1. */
3466	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3467	#define X86_FSW_C1_BIT 9
3468	/** Condition code 2. */
3469	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3470	#define X86_FSW_C2_BIT 10
3471	/** Top of the stack mask. */
3472	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3473	/** TOP shift value. */
3474	#define X86_FSW_TOP_SHIFT 11
3475	/** Mask for getting TOP value after shifting it right. */
3476	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3477	/** Get the TOP value. */
3478	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3479	/** Get the TOP value offsetted by a_iSt (0-7). */
3480	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3481	/** Condition code 3. */
3482	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3483	#define X86_FSW_C3_BIT 14
3484	/** Mask of exceptions flags, including the summary bit. */
3485	#define X86_FSW_C_MASK UINT16_C(0x4700)
3486	/** FPU busy. */
3487	#define X86_FSW_B RT_BIT_32(15)
3488	/** For use with FPREM and FPREM1. */
3489	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3490	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3491	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3492	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3493	/** For use with FPREM and FPREM1. */
3494	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3495	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3496	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3497	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3498	/** @} */
3499
3500
3501	/** @name FPU control word flags.
3502	* @{ */
3503	/** Exception Mask: Invalid operation. */
3504	#define X86_FCW_IM RT_BIT_32(0)
3505	#define X86_FCW_IM_BIT 0
3506	/** Exception Mask: Denormalized operand. */
3507	#define X86_FCW_DM RT_BIT_32(1)
3508	#define X86_FCW_DM_BIT 1
3509	/** Exception Mask: Zero divide. */
3510	#define X86_FCW_ZM RT_BIT_32(2)
3511	#define X86_FCW_ZM_BIT 2
3512	/** Exception Mask: Overflow. */
3513	#define X86_FCW_OM RT_BIT_32(3)
3514	#define X86_FCW_OM_BIT 3
3515	/** Exception Mask: Underflow. */
3516	#define X86_FCW_UM RT_BIT_32(4)
3517	#define X86_FCW_UM_BIT 4
3518	/** Exception Mask: Precision. */
3519	#define X86_FCW_PM RT_BIT_32(5)
3520	#define X86_FCW_PM_BIT 5
3521	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3522	* @remarks This includes reserved bit 6. */
3523	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3524	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3525	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3526	/** Precision control mask. */
3527	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3528	/** Precision control shift. */
3529	#define X86_FCW_PC_SHIFT 8
3530	/** Precision control: 24-bit. */
3531	#define X86_FCW_PC_24 UINT16_C(0x0000)
3532	/** Precision control: Reserved. */
3533	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3534	/** Precision control: 53-bit. */
3535	#define X86_FCW_PC_53 UINT16_C(0x0200)
3536	/** Precision control: 64-bit. */
3537	#define X86_FCW_PC_64 UINT16_C(0x0300)
3538	/** Rounding control mask. */
3539	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3540	/** Rounding control shift. */
3541	#define X86_FCW_RC_SHIFT 10
3542	/** Rounding control: To nearest. */
3543	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3544	/** Rounding control: Down. */
3545	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3546	/** Rounding control: Up. */
3547	#define X86_FCW_RC_UP UINT16_C(0x0800)
3548	/** Rounding control: Towards zero. */
3549	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3550	/** Infinity control mask - obsolete, 8087 & 287 only. */
3551	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3552	/** Infinity control: Affine - positive infinity is distictly different from
3553	* negative infinity.
3554	* @note 8087, 287 only */
3555	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3556	/** Infinity control: Projective - positive and negative infinity are the
3557	* same (sign ignored).
3558	* @note 8087, 287 only */
3559	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3560	/** Bits which should be zero, apparently. */
3561	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3562	/** @} */
3563
3564	/** @name SSE MXCSR
3565	* @{ */
3566	/** Exception Flag: Invalid operation. */
3567	#define X86_MXCSR_IE RT_BIT_32(0)
3568	/** Exception Flag: Denormalized operand. */
3569	#define X86_MXCSR_DE RT_BIT_32(1)
3570	/** Exception Flag: Zero divide. */
3571	#define X86_MXCSR_ZE RT_BIT_32(2)
3572	/** Exception Flag: Overflow. */
3573	#define X86_MXCSR_OE RT_BIT_32(3)
3574	/** Exception Flag: Underflow. */
3575	#define X86_MXCSR_UE RT_BIT_32(4)
3576	/** Exception Flag: Precision. */
3577	#define X86_MXCSR_PE RT_BIT_32(5)
3578	/** Exception Flags: mask */
3579	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3580
3581	/** Denormals are zero. */
3582	#define X86_MXCSR_DAZ RT_BIT_32(6)
3583
3584	/** Exception Mask: Invalid operation. */
3585	#define X86_MXCSR_IM RT_BIT_32(7)
3586	/** Exception Mask: Denormalized operand. */
3587	#define X86_MXCSR_DM RT_BIT_32(8)
3588	/** Exception Mask: Zero divide. */
3589	#define X86_MXCSR_ZM RT_BIT_32(9)
3590	/** Exception Mask: Overflow. */
3591	#define X86_MXCSR_OM RT_BIT_32(10)
3592	/** Exception Mask: Underflow. */
3593	#define X86_MXCSR_UM RT_BIT_32(11)
3594	/** Exception Mask: Precision. */
3595	#define X86_MXCSR_PM RT_BIT_32(12)
3596	/** Exception Mask: mask. */
3597	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3598	/** Exception Mask: shift. */
3599	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3600
3601	/** Rounding control mask. */
3602	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3603	/** Rounding control shift. */
3604	#define X86_MXCSR_RC_SHIFT 13
3605	/** Rounding control: To nearest. */
3606	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3607	/** Rounding control: Down. */
3608	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3609	/** Rounding control: Up. */
3610	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3611	/** Rounding control: Towards zero. */
3612	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3613
3614	/** Flush-to-zero for masked underflow. */
3615	#define X86_MXCSR_FZ RT_BIT_32(15)
3616
3617	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3618	#define X86_MXCSR_MM RT_BIT_32(17)
3619	/** Bits which should be zero, apparently. */
3620	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3621	/** @} */
3622
3623	/**
3624	* XSAVE header.
3625	*/
3626	typedef struct X86XSAVEHDR
3627	{
3628	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3629	uint64_t bmXState;
3630	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3631	uint64_t bmXComp;
3632	/** Reserved for furture extensions, probably MBZ. */
3633	uint64_t au64Reserved[6];
3634	} X86XSAVEHDR;
3635	#ifndef VBOX_FOR_DTRACE_LIB
3636	AssertCompileSize(X86XSAVEHDR, 64);
3637	#endif
3638	/** Pointer to an XSAVE header. */
3639	typedef X86XSAVEHDR *PX86XSAVEHDR;
3640	/** Pointer to a const XSAVE header. */
3641	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3642
3643
3644	/**
3645	* The high 128-bit YMM register state (XSAVE_C_YMM).
3646	* (The lower 128-bits being in X86FXSTATE.)
3647	*/
3648	typedef struct X86XSAVEYMMHI
3649	{
3650	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3651	X86XMMREG aYmmHi[16];
3652	} X86XSAVEYMMHI;
3653	#ifndef VBOX_FOR_DTRACE_LIB
3654	AssertCompileSize(X86XSAVEYMMHI, 256);
3655	#endif
3656	/** Pointer to a high 128-bit YMM register state. */
3657	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3658	/** Pointer to a const high 128-bit YMM register state. */
3659	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3660
3661	/**
3662	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3663	*/
3664	typedef struct X86XSAVEBNDREGS
3665	{
3666	/** Array of registers (BND0...BND3). */
3667	struct
3668	{
3669	/** Lower bound. */
3670	uint64_t uLowerBound;
3671	/** Upper bound. */
3672	uint64_t uUpperBound;
3673	} aRegs[4];
3674	} X86XSAVEBNDREGS;
3675	#ifndef VBOX_FOR_DTRACE_LIB
3676	AssertCompileSize(X86XSAVEBNDREGS, 64);
3677	#endif
3678	/** Pointer to a MPX bound register state. */
3679	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3680	/** Pointer to a const MPX bound register state. */
3681	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3682
3683	/**
3684	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3685	*/
3686	typedef struct X86XSAVEBNDCFG
3687	{
3688	uint64_t fConfig;
3689	uint64_t fStatus;
3690	} X86XSAVEBNDCFG;
3691	#ifndef VBOX_FOR_DTRACE_LIB
3692	AssertCompileSize(X86XSAVEBNDCFG, 16);
3693	#endif
3694	/** Pointer to a MPX bound config and status register state. */
3695	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3696	/** Pointer to a const MPX bound config and status register state. */
3697	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3698
3699	/**
3700	* AVX-512 opmask state (XSAVE_C_OPMASK).
3701	*/
3702	typedef struct X86XSAVEOPMASK
3703	{
3704	/** The K0..K7 values. */
3705	uint64_t aKRegs[8];
3706	} X86XSAVEOPMASK;
3707	#ifndef VBOX_FOR_DTRACE_LIB
3708	AssertCompileSize(X86XSAVEOPMASK, 64);
3709	#endif
3710	/** Pointer to a AVX-512 opmask state. */
3711	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3712	/** Pointer to a const AVX-512 opmask state. */
3713	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3714
3715	/**
3716	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3717	*/
3718	typedef struct X86XSAVEZMMHI256
3719	{
3720	/** Upper 256-bits of ZMM0-15. */
3721	X86YMMREG aHi256Regs[16];
3722	} X86XSAVEZMMHI256;
3723	#ifndef VBOX_FOR_DTRACE_LIB
3724	AssertCompileSize(X86XSAVEZMMHI256, 512);
3725	#endif
3726	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3727	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3728	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3729	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3730
3731	/**
3732	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3733	*/
3734	typedef struct X86XSAVEZMM16HI
3735	{
3736	/** ZMM16 thru ZMM31. */
3737	X86ZMMREG aRegs[16];
3738	} X86XSAVEZMM16HI;
3739	#ifndef VBOX_FOR_DTRACE_LIB
3740	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3741	#endif
3742	/** Pointer to a state comprising ZMM16-32. */
3743	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3744	/** Pointer to a const state comprising ZMM16-32. */
3745	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3746
3747	/**
3748	* AMD Light weight profiling state (XSAVE_C_LWP).
3749	*
3750	* We probably won't play with this as AMD seems to be dropping from their "zen"
3751	* processor micro architecture.
3752	*/
3753	typedef struct X86XSAVELWP
3754	{
3755	/** Details when needed. */
3756	uint64_t auLater[128/8];
3757	} X86XSAVELWP;
3758	#ifndef VBOX_FOR_DTRACE_LIB
3759	AssertCompileSize(X86XSAVELWP, 128);
3760	#endif
3761
3762
3763	/**
3764	* x86 FPU/SSE/AVX/XXXX state.
3765	*
3766	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3767	* changes to this structure.
3768	*/
3769	typedef struct X86XSAVEAREA
3770	{
3771	/** The x87 and SSE region (or legacy region if you like). */
3772	X86FXSTATE x87;
3773	/** The XSAVE header. */
3774	X86XSAVEHDR Hdr;
3775	/** Beyond the header, there isn't really a fixed layout, but we can
3776	generally assume the YMM (AVX) register extensions are present and
3777	follows immediately. */
3778	union
3779	{
3780	/** The high 128-bit AVX registers for easy access by IEM.
3781	* @note This ASSUMES they will always be here... */
3782	X86XSAVEYMMHI YmmHi;
3783
3784	/** This is a typical layout on intel CPUs (good for debuggers). */
3785	struct
3786	{
3787	X86XSAVEYMMHI YmmHi;
3788	X86XSAVEBNDREGS BndRegs;
3789	X86XSAVEBNDCFG BndCfg;
3790	uint8_t abFudgeToMatchDocs[0xB0];
3791	X86XSAVEOPMASK Opmask;
3792	X86XSAVEZMMHI256 ZmmHi256;
3793	X86XSAVEZMM16HI Zmm16Hi;
3794	} Intel;
3795
3796	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3797	struct
3798	{
3799	X86XSAVEYMMHI YmmHi;
3800	X86XSAVELWP Lwp;
3801	} AmdBd;
3802
3803	/** To enbling static deployments that have a reasonable chance of working for
3804	* the next 3-6 CPU generations without running short on space, we allocate a
3805	* lot of extra space here, making the structure a round 8KB in size. This
3806	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3807	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3808	uint8_t ab[8192 - 512 - 64];
3809	} u;
3810	} X86XSAVEAREA;
3811	#ifndef VBOX_FOR_DTRACE_LIB
3812	AssertCompileSize(X86XSAVEAREA, 8192);
3813	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3814	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3815	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3816	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3817	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3818	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3819	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3820	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3821	#endif
3822	/** Pointer to a XSAVE area. */
3823	typedef X86XSAVEAREA *PX86XSAVEAREA;
3824	/** Pointer to a const XSAVE area. */
3825	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3826
3827
3828	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3829	* @{ */
3830	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3831	#define XSAVE_C_X87_BIT 0
3832	/** Bit 0 - x87 - Legacy FPU state. */
3833	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3834	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3835	#define XSAVE_C_SSE_BIT 1
3836	/** Bit 1 - SSE - 128-bit SSE state. */
3837	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3838	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3839	#define XSAVE_C_YMM_BIT 2
3840	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3841	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3842	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3843	#define XSAVE_C_BNDREGS_BIT 3
3844	/** Bit 3 - BNDREGS - MPX bound register state. */
3845	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3846	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3847	#define XSAVE_C_BNDCSR_BIT 4
3848	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3849	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3850	/** Bit 5 - Opmask - opmask state (bit number). */
3851	#define XSAVE_C_OPMASK_BIT 5
3852	/** Bit 5 - Opmask - opmask state. */
3853	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3854	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3855	#define XSAVE_C_ZMM_HI256_BIT 6
3856	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3857	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3858	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3859	#define XSAVE_C_ZMM_16HI_BIT 7
3860	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3861	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3862	/** Bit 9 - PKRU - Protection-key state (bit number). */
3863	#define XSAVE_C_PKRU_BIT 9
3864	/** Bit 9 - PKRU - Protection-key state. */
3865	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3866	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3867	#define XSAVE_C_LWP_BIT 62
3868	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3869	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3870	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3871	#define XSAVE_C_X_BIT 63
3872	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3873	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3874	/** @} */
3875
3876
3877
3878	/** @name Selector Descriptor
3879	* @{
3880	*/
3881
3882	#ifndef VBOX_FOR_DTRACE_LIB
3883	/**
3884	* Descriptor attributes (as seen by VT-x).
3885	*/
3886	typedef struct X86DESCATTRBITS
3887	{
3888	/** 00 - Segment Type. */
3889	unsigned u4Type : 4;
3890	/** 04 - Descriptor Type. System(=0) or code/data selector */
3891	unsigned u1DescType : 1;
3892	/** 05 - Descriptor Privilege level. */
3893	unsigned u2Dpl : 2;
3894	/** 07 - Flags selector present(=1) or not. */
3895	unsigned u1Present : 1;
3896	/** 08 - Segment limit 16-19. */
3897	unsigned u4LimitHigh : 4;
3898	/** 0c - Available for system software. */
3899	unsigned u1Available : 1;
3900	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3901	unsigned u1Long : 1;
3902	/** 0e - This flags meaning depends on the segment type. Try make sense out
3903	* of the intel manual yourself. */
3904	unsigned u1DefBig : 1;
3905	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3906	* clear byte. */
3907	unsigned u1Granularity : 1;
3908	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3909	unsigned u1Unusable : 1;
3910	} X86DESCATTRBITS;
3911	#endif /* !VBOX_FOR_DTRACE_LIB */
3912
3913	/** @name X86DESCATTR masks
3914	* @{ */
3915	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3916	#define X86DESCATTR_DT UINT32_C(0x00000010)
3917	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3918	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3919	#define X86DESCATTR_P UINT32_C(0x00000080)
3920	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3921	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3922	#define X86DESCATTR_L UINT32_C(0x00002000)
3923	#define X86DESCATTR_D UINT32_C(0x00004000)
3924	#define X86DESCATTR_G UINT32_C(0x00008000)
3925	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3926	/** @} */
3927
3928	#pragma pack(1)
3929	typedef union X86DESCATTR
3930	{
3931	/** Unsigned integer view. */
3932	uint32_t u;
3933	#ifndef VBOX_FOR_DTRACE_LIB
3934	/** Normal view. */
3935	X86DESCATTRBITS n;
3936	#endif
3937	} X86DESCATTR;
3938	#pragma pack()
3939	/** Pointer to descriptor attributes. */
3940	typedef X86DESCATTR *PX86DESCATTR;
3941	/** Pointer to const descriptor attributes. */
3942	typedef const X86DESCATTR *PCX86DESCATTR;
3943
3944	#ifndef VBOX_FOR_DTRACE_LIB
3945
3946	/**
3947	* Generic descriptor table entry
3948	*/
3949	#pragma pack(1)
3950	typedef struct X86DESCGENERIC
3951	{
3952	/** 00 - Limit - Low word. */
3953	unsigned u16LimitLow : 16;
3954	/** 10 - Base address - low word.
3955	* Don't try set this to 24 because MSC is doing stupid things then. */
3956	unsigned u16BaseLow : 16;
3957	/** 20 - Base address - first 8 bits of high word. */
3958	unsigned u8BaseHigh1 : 8;
3959	/** 28 - Segment Type. */
3960	unsigned u4Type : 4;
3961	/** 2c - Descriptor Type. System(=0) or code/data selector */
3962	unsigned u1DescType : 1;
3963	/** 2d - Descriptor Privilege level. */
3964	unsigned u2Dpl : 2;
3965	/** 2f - Flags selector present(=1) or not. */
3966	unsigned u1Present : 1;
3967	/** 30 - Segment limit 16-19. */
3968	unsigned u4LimitHigh : 4;
3969	/** 34 - Available for system software. */
3970	unsigned u1Available : 1;
3971	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3972	unsigned u1Long : 1;
3973	/** 36 - This flags meaning depends on the segment type. Try make sense out
3974	* of the intel manual yourself. */
3975	unsigned u1DefBig : 1;
3976	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3977	* clear byte. */
3978	unsigned u1Granularity : 1;
3979	/** 38 - Base address - highest 8 bits. */
3980	unsigned u8BaseHigh2 : 8;
3981	} X86DESCGENERIC;
3982	#pragma pack()
3983	/** Pointer to a generic descriptor entry. */
3984	typedef X86DESCGENERIC *PX86DESCGENERIC;
3985	/** Pointer to a const generic descriptor entry. */
3986	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3987
3988	/** @name Bit offsets of X86DESCGENERIC members.
3989	* @{*/
3990	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3991	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3992	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3993	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3994	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3995	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3996	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3997	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3998	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3999	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4000	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4001	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4002	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4003	/** @} */
4004
4005
4006	/** @name LAR mask
4007	* @{ */
4008	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
4009	#define X86LAR_F_DT UINT16_C( 0x1000)
4010	#define X86LAR_F_DPL UINT16_C( 0x6000)
4011	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4012	#define X86LAR_F_P UINT16_C( 0x8000)
4013	#define X86LAR_F_AVL UINT32_C(0x00100000)
4014	#define X86LAR_F_L UINT32_C(0x00200000)
4015	#define X86LAR_F_D UINT32_C(0x00400000)
4016	#define X86LAR_F_G UINT32_C(0x00800000)
4017	/** @} */
4018
4019
4020	/**
4021	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4022	*/
4023	typedef struct X86DESCGATE
4024	{
4025	/** 00 - Target code segment offset - Low word.
4026	* Ignored if task-gate. */
4027	unsigned u16OffsetLow : 16;
4028	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4029	* TSS selector if task-gate. */
4030	unsigned u16Sel : 16;
4031	/** 20 - Number of parameters for a call-gate.
4032	* Ignored if interrupt-, trap- or task-gate. */
4033	unsigned u5ParmCount : 5;
4034	/** 25 - Reserved / ignored. */
4035	unsigned u3Reserved : 3;
4036	/** 28 - Segment Type. */
4037	unsigned u4Type : 4;
4038	/** 2c - Descriptor Type (0 = system). */
4039	unsigned u1DescType : 1;
4040	/** 2d - Descriptor Privilege level. */
4041	unsigned u2Dpl : 2;
4042	/** 2f - Flags selector present(=1) or not. */
4043	unsigned u1Present : 1;
4044	/** 30 - Target code segment offset - High word.
4045	* Ignored if task-gate. */
4046	unsigned u16OffsetHigh : 16;
4047	} X86DESCGATE;
4048	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4049	typedef X86DESCGATE *PX86DESCGATE;
4050	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4051	typedef const X86DESCGATE *PCX86DESCGATE;
4052
4053	#endif /* VBOX_FOR_DTRACE_LIB */
4054
4055	/**
4056	* Descriptor table entry.
4057	*/
4058	#pragma pack(1)
4059	typedef union X86DESC
4060	{
4061	#ifndef VBOX_FOR_DTRACE_LIB
4062	/** Generic descriptor view. */
4063	X86DESCGENERIC Gen;
4064	/** Gate descriptor view. */
4065	X86DESCGATE Gate;
4066	#endif
4067
4068	/** 8 bit unsigned integer view. */
4069	uint8_t au8[8];
4070	/** 16 bit unsigned integer view. */
4071	uint16_t au16[4];
4072	/** 32 bit unsigned integer view. */
4073	uint32_t au32[2];
4074	/** 64 bit unsigned integer view. */
4075	uint64_t au64[1];
4076	/** Unsigned integer view. */
4077	uint64_t u;
4078	} X86DESC;
4079	#ifndef VBOX_FOR_DTRACE_LIB
4080	AssertCompileSize(X86DESC, 8);
4081	#endif
4082	#pragma pack()
4083	/** Pointer to descriptor table entry. */
4084	typedef X86DESC *PX86DESC;
4085	/** Pointer to const descriptor table entry. */
4086	typedef const X86DESC *PCX86DESC;
4087
4088	/** @def X86DESC_BASE
4089	* Return the base address of a descriptor.
4090	*/
4091	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4092	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4093	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4094	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4095
4096	/** @def X86DESC_LIMIT
4097	* Return the limit of a descriptor.
4098	*/
4099	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4100	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4101	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4102
4103	/** @def X86DESC_LIMIT_G
4104	* Return the limit of a descriptor with the granularity bit taken into account.
4105	* @returns Selector limit (uint32_t).
4106	* @param a_pDesc Pointer to the descriptor.
4107	*/
4108	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4109	( (a_pDesc)->Gen.u1Granularity \
4110	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4111	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4112	)
4113
4114	/** @def X86DESC_GET_HID_ATTR
4115	* Get the descriptor attributes for the hidden register.
4116	*/
4117	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4118	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4119
4120	#ifndef VBOX_FOR_DTRACE_LIB
4121
4122	/**
4123	* 64 bits generic descriptor table entry
4124	* Note: most of these bits have no meaning in long mode.
4125	*/
4126	#pragma pack(1)
4127	typedef struct X86DESC64GENERIC
4128	{
4129	/** Limit - Low word - IGNORED. */
4130	uint32_t u16LimitLow : 16;
4131	/** Base address - low word. - IGNORED
4132	* Don't try set this to 24 because MSC is doing stupid things then. */
4133	uint32_t u16BaseLow : 16;
4134	/** Base address - first 8 bits of high word. - IGNORED */
4135	uint32_t u8BaseHigh1 : 8;
4136	/** Segment Type. */
4137	uint32_t u4Type : 4;
4138	/** Descriptor Type. System(=0) or code/data selector */
4139	uint32_t u1DescType : 1;
4140	/** Descriptor Privilege level. */
4141	uint32_t u2Dpl : 2;
4142	/** Flags selector present(=1) or not. */
4143	uint32_t u1Present : 1;
4144	/** Segment limit 16-19. - IGNORED */
4145	uint32_t u4LimitHigh : 4;
4146	/** Available for system software. - IGNORED */
4147	uint32_t u1Available : 1;
4148	/** Long mode flag. */
4149	uint32_t u1Long : 1;
4150	/** This flags meaning depends on the segment type. Try make sense out
4151	* of the intel manual yourself. */
4152	uint32_t u1DefBig : 1;
4153	/** Granularity of the limit. If set 4KB granularity is used, if
4154	* clear byte. - IGNORED */
4155	uint32_t u1Granularity : 1;
4156	/** Base address - highest 8 bits. - IGNORED */
4157	uint32_t u8BaseHigh2 : 8;
4158	/** Base address - bits 63-32. */
4159	uint32_t u32BaseHigh3 : 32;
4160	uint32_t u8Reserved : 8;
4161	uint32_t u5Zeros : 5;
4162	uint32_t u19Reserved : 19;
4163	} X86DESC64GENERIC;
4164	#pragma pack()
4165	/** Pointer to a generic descriptor entry. */
4166	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4167	/** Pointer to a const generic descriptor entry. */
4168	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4169
4170	/**
4171	* System descriptor table entry (64 bits)
4172	*
4173	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4174	*/
4175	#pragma pack(1)
4176	typedef struct X86DESC64SYSTEM
4177	{
4178	/** Limit - Low word. */
4179	uint32_t u16LimitLow : 16;
4180	/** Base address - low word.
4181	* Don't try set this to 24 because MSC is doing stupid things then. */
4182	uint32_t u16BaseLow : 16;
4183	/** Base address - first 8 bits of high word. */
4184	uint32_t u8BaseHigh1 : 8;
4185	/** Segment Type. */
4186	uint32_t u4Type : 4;
4187	/** Descriptor Type. System(=0) or code/data selector */
4188	uint32_t u1DescType : 1;
4189	/** Descriptor Privilege level. */
4190	uint32_t u2Dpl : 2;
4191	/** Flags selector present(=1) or not. */
4192	uint32_t u1Present : 1;
4193	/** Segment limit 16-19. */
4194	uint32_t u4LimitHigh : 4;
4195	/** Available for system software. */
4196	uint32_t u1Available : 1;
4197	/** Reserved - 0. */
4198	uint32_t u1Reserved : 1;
4199	/** This flags meaning depends on the segment type. Try make sense out
4200	* of the intel manual yourself. */
4201	uint32_t u1DefBig : 1;
4202	/** Granularity of the limit. If set 4KB granularity is used, if
4203	* clear byte. */
4204	uint32_t u1Granularity : 1;
4205	/** Base address - bits 31-24. */
4206	uint32_t u8BaseHigh2 : 8;
4207	/** Base address - bits 63-32. */
4208	uint32_t u32BaseHigh3 : 32;
4209	uint32_t u8Reserved : 8;
4210	uint32_t u5Zeros : 5;
4211	uint32_t u19Reserved : 19;
4212	} X86DESC64SYSTEM;
4213	#pragma pack()
4214	/** Pointer to a system descriptor entry. */
4215	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4216	/** Pointer to a const system descriptor entry. */
4217	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4218
4219	/**
4220	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4221	*/
4222	typedef struct X86DESC64GATE
4223	{
4224	/** Target code segment offset - Low word. */
4225	uint32_t u16OffsetLow : 16;
4226	/** Target code segment selector. */
4227	uint32_t u16Sel : 16;
4228	/** Interrupt stack table for interrupt- and trap-gates.
4229	* Ignored by call-gates. */
4230	uint32_t u3IST : 3;
4231	/** Reserved / ignored. */
4232	uint32_t u5Reserved : 5;
4233	/** Segment Type. */
4234	uint32_t u4Type : 4;
4235	/** Descriptor Type (0 = system). */
4236	uint32_t u1DescType : 1;
4237	/** Descriptor Privilege level. */
4238	uint32_t u2Dpl : 2;
4239	/** Flags selector present(=1) or not. */
4240	uint32_t u1Present : 1;
4241	/** Target code segment offset - High word.
4242	* Ignored if task-gate. */
4243	uint32_t u16OffsetHigh : 16;
4244	/** Target code segment offset - Top dword.
4245	* Ignored if task-gate. */
4246	uint32_t u32OffsetTop : 32;
4247	/** Reserved / ignored / must be zero.
4248	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4249	uint32_t u32Reserved : 32;
4250	} X86DESC64GATE;
4251	AssertCompileSize(X86DESC64GATE, 16);
4252	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4253	typedef X86DESC64GATE *PX86DESC64GATE;
4254	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4255	typedef const X86DESC64GATE *PCX86DESC64GATE;
4256
4257	#endif /* VBOX_FOR_DTRACE_LIB */
4258
4259	/**
4260	* Descriptor table entry.
4261	*/
4262	#pragma pack(1)
4263	typedef union X86DESC64
4264	{
4265	#ifndef VBOX_FOR_DTRACE_LIB
4266	/** Generic descriptor view. */
4267	X86DESC64GENERIC Gen;
4268	/** System descriptor view. */
4269	X86DESC64SYSTEM System;
4270	/** Gate descriptor view. */
4271	X86DESC64GATE Gate;
4272	#endif
4273
4274	/** 8 bit unsigned integer view. */
4275	uint8_t au8[16];
4276	/** 16 bit unsigned integer view. */
4277	uint16_t au16[8];
4278	/** 32 bit unsigned integer view. */
4279	uint32_t au32[4];
4280	/** 64 bit unsigned integer view. */
4281	uint64_t au64[2];
4282	} X86DESC64;
4283	#ifndef VBOX_FOR_DTRACE_LIB
4284	AssertCompileSize(X86DESC64, 16);
4285	#endif
4286	#pragma pack()
4287	/** Pointer to descriptor table entry. */
4288	typedef X86DESC64 *PX86DESC64;
4289	/** Pointer to const descriptor table entry. */
4290	typedef const X86DESC64 *PCX86DESC64;
4291
4292	/** @def X86DESC64_BASE
4293	* Return the base of a 64-bit descriptor.
4294	*/
4295	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4296	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4297	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4298	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4299	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4300
4301
4302
4303	/** @name Host system descriptor table entry - Use with care!
4304	* @{ */
4305	/** Host system descriptor table entry. */
4306	#if HC_ARCH_BITS == 64
4307	typedef X86DESC64 X86DESCHC;
4308	#else
4309	typedef X86DESC X86DESCHC;
4310	#endif
4311	/** Pointer to a host system descriptor table entry. */
4312	#if HC_ARCH_BITS == 64
4313	typedef PX86DESC64 PX86DESCHC;
4314	#else
4315	typedef PX86DESC PX86DESCHC;
4316	#endif
4317	/** Pointer to a const host system descriptor table entry. */
4318	#if HC_ARCH_BITS == 64
4319	typedef PCX86DESC64 PCX86DESCHC;
4320	#else
4321	typedef PCX86DESC PCX86DESCHC;
4322	#endif
4323	/** @} */
4324
4325
4326	/** @name Selector Descriptor Types.
4327	* @{
4328	*/
4329
4330	/** @name Non-System Selector Types.
4331	* @{ */
4332	/** Code(=set)/Data(=clear) bit. */
4333	#define X86_SEL_TYPE_CODE 8
4334	/** Memory(=set)/System(=clear) bit. */
4335	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4336	/** Accessed bit. */
4337	#define X86_SEL_TYPE_ACCESSED 1
4338	/** Expand down bit (for data selectors only). */
4339	#define X86_SEL_TYPE_DOWN 4
4340	/** Conforming bit (for code selectors only). */
4341	#define X86_SEL_TYPE_CONF 4
4342	/** Write bit (for data selectors only). */
4343	#define X86_SEL_TYPE_WRITE 2
4344	/** Read bit (for code selectors only). */
4345	#define X86_SEL_TYPE_READ 2
4346	/** The bit number of the code segment read bit (relative to u4Type). */
4347	#define X86_SEL_TYPE_READ_BIT 1
4348
4349	/** Read only selector type. */
4350	#define X86_SEL_TYPE_RO 0
4351	/** Accessed read only selector type. */
4352	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4353	/** Read write selector type. */
4354	#define X86_SEL_TYPE_RW 2
4355	/** Accessed read write selector type. */
4356	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4357	/** Expand down read only selector type. */
4358	#define X86_SEL_TYPE_RO_DOWN 4
4359	/** Accessed expand down read only selector type. */
4360	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4361	/** Expand down read write selector type. */
4362	#define X86_SEL_TYPE_RW_DOWN 6
4363	/** Accessed expand down read write selector type. */
4364	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4365	/** Execute only selector type. */
4366	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4367	/** Accessed execute only selector type. */
4368	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4369	/** Execute and read selector type. */
4370	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4371	/** Accessed execute and read selector type. */
4372	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4373	/** Conforming execute only selector type. */
4374	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4375	/** Accessed Conforming execute only selector type. */
4376	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4377	/** Conforming execute and write selector type. */
4378	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4379	/** Accessed Conforming execute and write selector type. */
4380	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4381	/** @} */
4382
4383
4384	/** @name System Selector Types.
4385	* @{ */
4386	/** The TSS busy bit mask. */
4387	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4388
4389	/** Undefined system selector type. */
4390	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4391	/** 286 TSS selector. */
4392	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4393	/** LDT selector. */
4394	#define X86_SEL_TYPE_SYS_LDT 2
4395	/** 286 TSS selector - Busy. */
4396	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4397	/** 286 Callgate selector. */
4398	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4399	/** Taskgate selector. */
4400	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4401	/** 286 Interrupt gate selector. */
4402	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4403	/** 286 Trapgate selector. */
4404	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4405	/** Undefined system selector. */
4406	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4407	/** 386 TSS selector. */
4408	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4409	/** Undefined system selector. */
4410	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4411	/** 386 TSS selector - Busy. */
4412	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4413	/** 386 Callgate selector. */
4414	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4415	/** Undefined system selector. */
4416	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4417	/** 386 Interruptgate selector. */
4418	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4419	/** 386 Trapgate selector. */
4420	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4421	/** @} */
4422
4423	/** @name AMD64 System Selector Types.
4424	* @{ */
4425	/** LDT selector. */
4426	#define AMD64_SEL_TYPE_SYS_LDT 2
4427	/** TSS selector - Busy. */
4428	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4429	/** TSS selector - Busy. */
4430	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4431	/** Callgate selector. */
4432	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4433	/** Interruptgate selector. */
4434	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4435	/** Trapgate selector. */
4436	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4437	/** @} */
4438
4439	/** @} */
4440
4441
4442	/** @name Descriptor Table Entry Flag Masks.
4443	* These are for the 2nd 32-bit word of a descriptor.
4444	* @{ */
4445	/** Bits 8-11 - TYPE - Descriptor type mask. */
4446	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4447	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4448	#define X86_DESC_S RT_BIT_32(12)
4449	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4450	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4451	/** Bit 15 - P - Present. */
4452	#define X86_DESC_P RT_BIT_32(15)
4453	/** Bit 20 - AVL - Available for system software. */
4454	#define X86_DESC_AVL RT_BIT_32(20)
4455	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4456	#define X86_DESC_DB RT_BIT_32(22)
4457	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4458	* used, if clear byte. */
4459	#define X86_DESC_G RT_BIT_32(23)
4460	/** @} */
4461
4462	/** @} */
4463
4464
4465	/** @name Task Segments.
4466	* @{
4467	*/
4468
4469	/**
4470	* The minimum TSS descriptor limit for 286 tasks.
4471	*/
4472	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4473
4474	/**
4475	* The minimum TSS descriptor segment limit for 386 tasks.
4476	*/
4477	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4478
4479	/**
4480	* 16-bit Task Segment (TSS).
4481	*/
4482	#pragma pack(1)
4483	typedef struct X86TSS16
4484	{
4485	/** Back link to previous task. (static) */
4486	RTSEL selPrev;
4487	/** Ring-0 stack pointer. (static) */
4488	uint16_t sp0;
4489	/** Ring-0 stack segment. (static) */
4490	RTSEL ss0;
4491	/** Ring-1 stack pointer. (static) */
4492	uint16_t sp1;
4493	/** Ring-1 stack segment. (static) */
4494	RTSEL ss1;
4495	/** Ring-2 stack pointer. (static) */
4496	uint16_t sp2;
4497	/** Ring-2 stack segment. (static) */
4498	RTSEL ss2;
4499	/** IP before task switch. */
4500	uint16_t ip;
4501	/** FLAGS before task switch. */
4502	uint16_t flags;
4503	/** AX before task switch. */
4504	uint16_t ax;
4505	/** CX before task switch. */
4506	uint16_t cx;
4507	/** DX before task switch. */
4508	uint16_t dx;
4509	/** BX before task switch. */
4510	uint16_t bx;
4511	/** SP before task switch. */
4512	uint16_t sp;
4513	/** BP before task switch. */
4514	uint16_t bp;
4515	/** SI before task switch. */
4516	uint16_t si;
4517	/** DI before task switch. */
4518	uint16_t di;
4519	/** ES before task switch. */
4520	RTSEL es;
4521	/** CS before task switch. */
4522	RTSEL cs;
4523	/** SS before task switch. */
4524	RTSEL ss;
4525	/** DS before task switch. */
4526	RTSEL ds;
4527	/** LDTR before task switch. */
4528	RTSEL selLdt;
4529	} X86TSS16;
4530	#ifndef VBOX_FOR_DTRACE_LIB
4531	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4532	#endif
4533	#pragma pack()
4534	/** Pointer to a 16-bit task segment. */
4535	typedef X86TSS16 *PX86TSS16;
4536	/** Pointer to a const 16-bit task segment. */
4537	typedef const X86TSS16 *PCX86TSS16;
4538
4539
4540	/**
4541	* 32-bit Task Segment (TSS).
4542	*/
4543	#pragma pack(1)
4544	typedef struct X86TSS32
4545	{
4546	/** Back link to previous task. (static) */
4547	RTSEL selPrev;
4548	uint16_t padding1;
4549	/** Ring-0 stack pointer. (static) */
4550	uint32_t esp0;
4551	/** Ring-0 stack segment. (static) */
4552	RTSEL ss0;
4553	uint16_t padding_ss0;
4554	/** Ring-1 stack pointer. (static) */
4555	uint32_t esp1;
4556	/** Ring-1 stack segment. (static) */
4557	RTSEL ss1;
4558	uint16_t padding_ss1;
4559	/** Ring-2 stack pointer. (static) */
4560	uint32_t esp2;
4561	/** Ring-2 stack segment. (static) */
4562	RTSEL ss2;
4563	uint16_t padding_ss2;
4564	/** Page directory for the task. (static) */
4565	uint32_t cr3;
4566	/** EIP before task switch. */
4567	uint32_t eip;
4568	/** EFLAGS before task switch. */
4569	uint32_t eflags;
4570	/** EAX before task switch. */
4571	uint32_t eax;
4572	/** ECX before task switch. */
4573	uint32_t ecx;
4574	/** EDX before task switch. */
4575	uint32_t edx;
4576	/** EBX before task switch. */
4577	uint32_t ebx;
4578	/** ESP before task switch. */
4579	uint32_t esp;
4580	/** EBP before task switch. */
4581	uint32_t ebp;
4582	/** ESI before task switch. */
4583	uint32_t esi;
4584	/** EDI before task switch. */
4585	uint32_t edi;
4586	/** ES before task switch. */
4587	RTSEL es;
4588	uint16_t padding_es;
4589	/** CS before task switch. */
4590	RTSEL cs;
4591	uint16_t padding_cs;
4592	/** SS before task switch. */
4593	RTSEL ss;
4594	uint16_t padding_ss;
4595	/** DS before task switch. */
4596	RTSEL ds;
4597	uint16_t padding_ds;
4598	/** FS before task switch. */
4599	RTSEL fs;
4600	uint16_t padding_fs;
4601	/** GS before task switch. */
4602	RTSEL gs;
4603	uint16_t padding_gs;
4604	/** LDTR before task switch. */
4605	RTSEL selLdt;
4606	uint16_t padding_ldt;
4607	/** Debug trap flag */
4608	uint16_t fDebugTrap;
4609	/** Offset relative to the TSS of the start of the I/O Bitmap
4610	* and the end of the interrupt redirection bitmap. */
4611	uint16_t offIoBitmap;
4612	} X86TSS32;
4613	#pragma pack()
4614	/** Pointer to task segment. */
4615	typedef X86TSS32 *PX86TSS32;
4616	/** Pointer to const task segment. */
4617	typedef const X86TSS32 *PCX86TSS32;
4618	#ifndef VBOX_FOR_DTRACE_LIB
4619	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4620	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4621	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4622	#endif
4623
4624	/**
4625	* 64-bit Task segment.
4626	*/
4627	#pragma pack(1)
4628	typedef struct X86TSS64
4629	{
4630	/** Reserved. */
4631	uint32_t u32Reserved;
4632	/** Ring-0 stack pointer. (static) */
4633	uint64_t rsp0;
4634	/** Ring-1 stack pointer. (static) */
4635	uint64_t rsp1;
4636	/** Ring-2 stack pointer. (static) */
4637	uint64_t rsp2;
4638	/** Reserved. */
4639	uint32_t u32Reserved2[2];
4640	/* IST */
4641	uint64_t ist1;
4642	uint64_t ist2;
4643	uint64_t ist3;
4644	uint64_t ist4;
4645	uint64_t ist5;
4646	uint64_t ist6;
4647	uint64_t ist7;
4648	/* Reserved. */
4649	uint16_t u16Reserved[5];
4650	/** Offset relative to the TSS of the start of the I/O Bitmap
4651	* and the end of the interrupt redirection bitmap. */
4652	uint16_t offIoBitmap;
4653	} X86TSS64;
4654	#pragma pack()
4655	/** Pointer to a 64-bit task segment. */
4656	typedef X86TSS64 *PX86TSS64;
4657	/** Pointer to a const 64-bit task segment. */
4658	typedef const X86TSS64 *PCX86TSS64;
4659	#ifndef VBOX_FOR_DTRACE_LIB
4660	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4661	#endif
4662
4663	/** @} */
4664
4665
4666	/** @name Selectors.
4667	* @{
4668	*/
4669
4670	/**
4671	* The shift used to convert a selector from and to index an index (C).
4672	*/
4673	#define X86_SEL_SHIFT 3
4674
4675	/**
4676	* The mask used to mask off the table indicator and RPL of an selector.
4677	*/
4678	#define X86_SEL_MASK 0xfff8U
4679
4680	/**
4681	* The mask used to mask off the RPL of an selector.
4682	* This is suitable for checking for NULL selectors.
4683	*/
4684	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4685
4686	/**
4687	* The bit indicating that a selector is in the LDT and not in the GDT.
4688	*/
4689	#define X86_SEL_LDT 0x0004U
4690
4691	/**
4692	* The bit mask for getting the RPL of a selector.
4693	*/
4694	#define X86_SEL_RPL 0x0003U
4695
4696	/**
4697	* The mask covering both RPL and LDT.
4698	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4699	* checks.
4700	*/
4701	#define X86_SEL_RPL_LDT 0x0007U
4702
4703	/** @} */
4704
4705
4706	/**
4707	* x86 Exceptions/Faults/Traps.
4708	*/
4709	typedef enum X86XCPT
4710	{
4711	/** \#DE - Divide error. */
4712	X86_XCPT_DE = 0x00,
4713	/** \#DB - Debug event (single step, DRx, ..) */
4714	X86_XCPT_DB = 0x01,
4715	/** NMI - Non-Maskable Interrupt */
4716	X86_XCPT_NMI = 0x02,
4717	/** \#BP - Breakpoint (INT3). */
4718	X86_XCPT_BP = 0x03,
4719	/** \#OF - Overflow (INTO). */
4720	X86_XCPT_OF = 0x04,
4721	/** \#BR - Bound range exceeded (BOUND). */
4722	X86_XCPT_BR = 0x05,
4723	/** \#UD - Undefined opcode. */
4724	X86_XCPT_UD = 0x06,
4725	/** \#NM - Device not available (math coprocessor device). */
4726	X86_XCPT_NM = 0x07,
4727	/** \#DF - Double fault. */
4728	X86_XCPT_DF = 0x08,
4729	/** ??? - Coprocessor segment overrun (obsolete). */
4730	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4731	/** \#TS - Taskswitch (TSS). */
4732	X86_XCPT_TS = 0x0a,
4733	/** \#NP - Segment no present. */
4734	X86_XCPT_NP = 0x0b,
4735	/** \#SS - Stack segment fault. */
4736	X86_XCPT_SS = 0x0c,
4737	/** \#GP - General protection fault. */
4738	X86_XCPT_GP = 0x0d,
4739	/** \#PF - Page fault. */
4740	X86_XCPT_PF = 0x0e,
4741	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4742	/** \#MF - Math fault (FPU). */
4743	X86_XCPT_MF = 0x10,
4744	/** \#AC - Alignment check. */
4745	X86_XCPT_AC = 0x11,
4746	/** \#MC - Machine check. */
4747	X86_XCPT_MC = 0x12,
4748	/** \#XF - SIMD Floating-Point Exception. */
4749	X86_XCPT_XF = 0x13,
4750	/** \#VE - Virtualization Exception (Intel only). */
4751	X86_XCPT_VE = 0x14,
4752	/** \#CP - Control Protection Exception (Intel only). */
4753	X86_XCPT_CP = 0x15,
4754	/** \#VC - VMM Communication Exception (AMD only). */
4755	X86_XCPT_VC = 0x1d,
4756	/** \#SX - Security Exception (AMD only). */
4757	X86_XCPT_SX = 0x1e
4758	} X86XCPT;
4759	/** Pointer to a x86 exception code. */
4760	typedef X86XCPT *PX86XCPT;
4761	/** Pointer to a const x86 exception code. */
4762	typedef const X86XCPT *PCX86XCPT;
4763	/** The last valid (currently reserved) exception value. */
4764	#define X86_XCPT_LAST 0x1f
4765
4766
4767	/** @name Trap Error Codes
4768	* @{
4769	*/
4770	/** External indicator. */
4771	#define X86_TRAP_ERR_EXTERNAL 1
4772	/** IDT indicator. */
4773	#define X86_TRAP_ERR_IDT 2
4774	/** Descriptor table indicator - If set LDT, if clear GDT. */
4775	#define X86_TRAP_ERR_TI 4
4776	/** Mask for getting the selector. */
4777	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4778	/** Shift for getting the selector table index (C type index). */
4779	#define X86_TRAP_ERR_SEL_SHIFT 3
4780	/** @} */
4781
4782
4783	/** @name \#PF Trap Error Codes
4784	* @{
4785	*/
4786	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4787	#define X86_TRAP_PF_P RT_BIT_32(0)
4788	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4789	#define X86_TRAP_PF_RW RT_BIT_32(1)
4790	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4791	#define X86_TRAP_PF_US RT_BIT_32(2)
4792	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4793	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4794	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4795	#define X86_TRAP_PF_ID RT_BIT_32(4)
4796	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4797	#define X86_TRAP_PF_PK RT_BIT_32(5)
4798	/** @} */
4799
4800	#pragma pack(1)
4801	/**
4802	* 16-bit IDTR.
4803	*/
4804	typedef struct X86IDTR16
4805	{
4806	/** Offset. */
4807	uint16_t offSel;
4808	/** Selector. */
4809	uint16_t uSel;
4810	} X86IDTR16, *PX86IDTR16;
4811	#pragma pack()
4812
4813	#pragma pack(1)
4814	/**
4815	* 32-bit IDTR/GDTR.
4816	*/
4817	typedef struct X86XDTR32
4818	{
4819	/** Size of the descriptor table. */
4820	uint16_t cb;
4821	/** Address of the descriptor table. */
4822	#ifndef VBOX_FOR_DTRACE_LIB
4823	uint32_t uAddr;
4824	#else
4825	uint16_t au16Addr[2];
4826	#endif
4827	} X86XDTR32, *PX86XDTR32;
4828	#pragma pack()
4829
4830	#pragma pack(1)
4831	/**
4832	* 64-bit IDTR/GDTR.
4833	*/
4834	typedef struct X86XDTR64
4835	{
4836	/** Size of the descriptor table. */
4837	uint16_t cb;
4838	/** Address of the descriptor table. */
4839	#ifndef VBOX_FOR_DTRACE_LIB
4840	uint64_t uAddr;
4841	#else
4842	uint16_t au16Addr[4];
4843	#endif
4844	} X86XDTR64, *PX86XDTR64;
4845	#pragma pack()
4846
4847
4848	/** @name ModR/M
4849	* @{ */
4850	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4851	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4852	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4853	#define X86_MODRM_REG_SHIFT 3
4854	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4855	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4856	#define X86_MODRM_MOD_SHIFT 6
4857	#ifndef VBOX_FOR_DTRACE_LIB
4858	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4859	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4860	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4861	/** @def X86_MODRM_MAKE
4862	* @param a_Mod The mod value (0..3).
4863	* @param a_Reg The register value (0..7).
4864	* @param a_RegMem The register or memory value (0..7). */
4865	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4866	#endif
4867	/** @} */
4868
4869	/** @name SIB
4870	* @{ */
4871	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4872	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4873	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4874	#define X86_SIB_INDEX_SHIFT 3
4875	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4876	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4877	#define X86_SIB_SCALE_SHIFT 6
4878	#ifndef VBOX_FOR_DTRACE_LIB
4879	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4880	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4881	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4882	#endif
4883	/** @} */
4884
4885	/** @name General register indexes.
4886	* @{ */
4887	#define X86_GREG_xAX 0
4888	#define X86_GREG_xCX 1
4889	#define X86_GREG_xDX 2
4890	#define X86_GREG_xBX 3
4891	#define X86_GREG_xSP 4
4892	#define X86_GREG_xBP 5
4893	#define X86_GREG_xSI 6
4894	#define X86_GREG_xDI 7
4895	#define X86_GREG_x8 8
4896	#define X86_GREG_x9 9
4897	#define X86_GREG_x10 10
4898	#define X86_GREG_x11 11
4899	#define X86_GREG_x12 12
4900	#define X86_GREG_x13 13
4901	#define X86_GREG_x14 14
4902	#define X86_GREG_x15 15
4903	/** @} */
4904	/** General register count. */
4905	#define X86_GREG_COUNT 16
4906
4907	/** @name X86_SREG_XXX - Segment register indexes.
4908	* @{ */
4909	#define X86_SREG_ES 0
4910	#define X86_SREG_CS 1
4911	#define X86_SREG_SS 2
4912	#define X86_SREG_DS 3
4913	#define X86_SREG_FS 4
4914	#define X86_SREG_GS 5
4915	/** @} */
4916	/** Segment register count. */
4917	#define X86_SREG_COUNT 6
4918
4919
4920	/** @name X86_OP_XXX - Prefixes
4921	* @{ */
4922	#define X86_OP_PRF_CS UINT8_C(0x2e)
4923	#define X86_OP_PRF_SS UINT8_C(0x36)
4924	#define X86_OP_PRF_DS UINT8_C(0x3e)
4925	#define X86_OP_PRF_ES UINT8_C(0x26)
4926	#define X86_OP_PRF_FS UINT8_C(0x64)
4927	#define X86_OP_PRF_GS UINT8_C(0x65)
4928	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4929	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4930	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4931	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4932	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4933	#define X86_OP_REX_B UINT8_C(0x41)
4934	#define X86_OP_REX_X UINT8_C(0x42)
4935	#define X86_OP_REX_R UINT8_C(0x44)
4936	#define X86_OP_REX_W UINT8_C(0x48)
4937	/** @} */
4938
4939
4940	/** @} */
4941
4942	#endif /* !IPRT_INCLUDED_x86_h */
4943

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source: vbox/trunk/include/iprt/x86.h@ 100997

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