x86.h@ 101430

Last change on this file since 101430 was 101430, checked in by vboxsync, 14 months ago
iprt/x86.h: CP exception is no longer Intel only, updated comment.
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# include <iprt/types.h>
46	# include <iprt/assert.h>
47	#else
48	# pragma D depends_on library vbox-types.d
49	#endif
50
51	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
52	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
53	#ifdef RT_OS_SOLARIS
54	# undef CS
55	# undef DS
56	# undef MSR_IA32_FLUSH_CMD
57	# undef MSR_AMD_VIRT_SPEC_CTL
58	#endif
59
60	/** @defgroup grp_rt_x86 x86 Types and Definitions
61	* @ingroup grp_rt
62	* @{
63	*/
64
65	#ifndef VBOX_FOR_DTRACE_LIB
66	/**
67	* EFLAGS Bits.
68	*/
69	typedef struct X86EFLAGSBITS
70	{
71	/** Bit 0 - CF - Carry flag - Status flag. */
72	unsigned u1CF : 1;
73	/** Bit 1 - 1 - Reserved flag. */
74	unsigned u1Reserved0 : 1;
75	/** Bit 2 - PF - Parity flag - Status flag. */
76	unsigned u1PF : 1;
77	/** Bit 3 - 0 - Reserved flag. */
78	unsigned u1Reserved1 : 1;
79	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
80	unsigned u1AF : 1;
81	/** Bit 5 - 0 - Reserved flag. */
82	unsigned u1Reserved2 : 1;
83	/** Bit 6 - ZF - Zero flag - Status flag. */
84	unsigned u1ZF : 1;
85	/** Bit 7 - SF - Signed flag - Status flag. */
86	unsigned u1SF : 1;
87	/** Bit 8 - TF - Trap flag - System flag. */
88	unsigned u1TF : 1;
89	/** Bit 9 - IF - Interrupt flag - System flag. */
90	unsigned u1IF : 1;
91	/** Bit 10 - DF - Direction flag - Control flag. */
92	unsigned u1DF : 1;
93	/** Bit 11 - OF - Overflow flag - Status flag. */
94	unsigned u1OF : 1;
95	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
96	unsigned u2IOPL : 2;
97	/** Bit 14 - NT - Nested task flag - System flag. */
98	unsigned u1NT : 1;
99	/** Bit 15 - 0 - Reserved flag. */
100	unsigned u1Reserved3 : 1;
101	/** Bit 16 - RF - Resume flag - System flag. */
102	unsigned u1RF : 1;
103	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
104	unsigned u1VM : 1;
105	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
106	unsigned u1AC : 1;
107	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
108	unsigned u1VIF : 1;
109	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
110	unsigned u1VIP : 1;
111	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
112	unsigned u1ID : 1;
113	/** Bit 22-31 - 0 - Reserved flag. */
114	unsigned u10Reserved4 : 10;
115	} X86EFLAGSBITS;
116	/** Pointer to EFLAGS bits. */
117	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
118	/** Pointer to const EFLAGS bits. */
119	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
120	#endif /* !VBOX_FOR_DTRACE_LIB */
121
122	/**
123	* EFLAGS.
124	*/
125	typedef union X86EFLAGS
126	{
127	/** The plain unsigned view. */
128	uint32_t u;
129	#ifndef VBOX_FOR_DTRACE_LIB
130	/** The bitfield view. */
131	X86EFLAGSBITS Bits;
132	#endif
133	/** The 8-bit view. */
134	uint8_t au8[4];
135	/** The 16-bit view. */
136	uint16_t au16[2];
137	/** The 32-bit view. */
138	uint32_t au32[1];
139	/** The 32-bit view. */
140	uint32_t u32;
141	} X86EFLAGS;
142	/** Pointer to EFLAGS. */
143	typedef X86EFLAGS *PX86EFLAGS;
144	/** Pointer to const EFLAGS. */
145	typedef const X86EFLAGS *PCX86EFLAGS;
146
147	/**
148	* RFLAGS (32 upper bits are reserved).
149	*/
150	typedef union X86RFLAGS
151	{
152	/** The plain unsigned view. */
153	uint64_t u;
154	#ifndef VBOX_FOR_DTRACE_LIB
155	/** The bitfield view. */
156	X86EFLAGSBITS Bits;
157	#endif
158	/** The 8-bit view. */
159	uint8_t au8[8];
160	/** The 16-bit view. */
161	uint16_t au16[4];
162	/** The 32-bit view. */
163	uint32_t au32[2];
164	/** The 64-bit view. */
165	uint64_t au64[1];
166	/** The 64-bit view. */
167	uint64_t u64;
168	} X86RFLAGS;
169	/** Pointer to RFLAGS. */
170	typedef X86RFLAGS *PX86RFLAGS;
171	/** Pointer to const RFLAGS. */
172	typedef const X86RFLAGS *PCX86RFLAGS;
173
174
175	/** @name EFLAGS
176	* @{
177	*/
178	/** Bit 0 - CF - Carry flag - Status flag. */
179	#define X86_EFL_CF RT_BIT_32(0)
180	#define X86_EFL_CF_BIT 0
181	/** Bit 1 - Reserved, reads as 1. */
182	#define X86_EFL_1 RT_BIT_32(1)
183	/** Bit 2 - PF - Parity flag - Status flag. */
184	#define X86_EFL_PF RT_BIT_32(2)
185	#define X86_EFL_PF_BIT 2
186	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
187	#define X86_EFL_AF RT_BIT_32(4)
188	#define X86_EFL_AF_BIT 4
189	/** Bit 6 - ZF - Zero flag - Status flag. */
190	#define X86_EFL_ZF RT_BIT_32(6)
191	#define X86_EFL_ZF_BIT 6
192	/** Bit 7 - SF - Signed flag - Status flag. */
193	#define X86_EFL_SF RT_BIT_32(7)
194	#define X86_EFL_SF_BIT 7
195	/** Bit 8 - TF - Trap flag - System flag. */
196	#define X86_EFL_TF RT_BIT_32(8)
197	#define X86_EFL_TF_BIT 8
198	/** Bit 9 - IF - Interrupt flag - System flag. */
199	#define X86_EFL_IF RT_BIT_32(9)
200	#define X86_EFL_IF_BIT 9
201	/** Bit 10 - DF - Direction flag - Control flag. */
202	#define X86_EFL_DF RT_BIT_32(10)
203	#define X86_EFL_DF_BIT 10
204	/** Bit 11 - OF - Overflow flag - Status flag. */
205	#define X86_EFL_OF RT_BIT_32(11)
206	#define X86_EFL_OF_BIT 11
207	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
208	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
209	/** Bit 14 - NT - Nested task flag - System flag. */
210	#define X86_EFL_NT RT_BIT_32(14)
211	#define X86_EFL_NT_BIT 14
212	/** Bit 16 - RF - Resume flag - System flag. */
213	#define X86_EFL_RF RT_BIT_32(16)
214	#define X86_EFL_RF_BIT 16
215	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
216	#define X86_EFL_VM RT_BIT_32(17)
217	#define X86_EFL_VM_BIT 17
218	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
219	#define X86_EFL_AC RT_BIT_32(18)
220	#define X86_EFL_AC_BIT 18
221	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
222	#define X86_EFL_VIF RT_BIT_32(19)
223	#define X86_EFL_VIF_BIT 19
224	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
225	#define X86_EFL_VIP RT_BIT_32(20)
226	#define X86_EFL_VIP_BIT 20
227	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
228	#define X86_EFL_ID RT_BIT_32(21)
229	#define X86_EFL_ID_BIT 21
230	/** All live bits. */
231	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
232	/** Read as 1 bits. */
233	#define X86_EFL_RA1_MASK RT_BIT_32(1)
234	/** Read as 0 bits, excluding bits 31:22.
235	* Bits 3, 5, 15, and 22 thru 31. */
236	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
237	/** Read as 0 bits, excluding bits 31:22.
238	* Bits 3, 5 and 15. */
239	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
240	/** IOPL shift. */
241	#define X86_EFL_IOPL_SHIFT 12
242	/** The IOPL level from the flags. */
243	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
244	/** Bits restored by popf */
245	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
246	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
247	/** Bits restored by popf */
248	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
249	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
250	/** The status bits commonly updated by arithmetic instructions. */
251	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
252	/** @} */
253
254
255	/** CPUID Feature information - ECX.
256	* CPUID query with EAX=1.
257	*/
258	#ifndef VBOX_FOR_DTRACE_LIB
259	typedef struct X86CPUIDFEATECX
260	{
261	/** Bit 0 - SSE3 - Supports SSE3 or not. */
262	unsigned u1SSE3 : 1;
263	/** Bit 1 - PCLMULQDQ. */
264	unsigned u1PCLMULQDQ : 1;
265	/** Bit 2 - DS Area 64-bit layout. */
266	unsigned u1DTE64 : 1;
267	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
268	unsigned u1Monitor : 1;
269	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
270	unsigned u1CPLDS : 1;
271	/** Bit 5 - VMX - Virtual Machine Technology. */
272	unsigned u1VMX : 1;
273	/** Bit 6 - SMX: Safer Mode Extensions. */
274	unsigned u1SMX : 1;
275	/** Bit 7 - EST - Enh. SpeedStep Tech. */
276	unsigned u1EST : 1;
277	/** Bit 8 - TM2 - Terminal Monitor 2. */
278	unsigned u1TM2 : 1;
279	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
280	unsigned u1SSSE3 : 1;
281	/** Bit 10 - CNTX-ID - L1 Context ID. */
282	unsigned u1CNTXID : 1;
283	/** Bit 11 - Reserved. */
284	unsigned u1Reserved1 : 1;
285	/** Bit 12 - FMA. */
286	unsigned u1FMA : 1;
287	/** Bit 13 - CX16 - CMPXCHG16B. */
288	unsigned u1CX16 : 1;
289	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
290	unsigned u1TPRUpdate : 1;
291	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
292	unsigned u1PDCM : 1;
293	/** Bit 16 - Reserved. */
294	unsigned u1Reserved2 : 1;
295	/** Bit 17 - PCID - Process-context identifiers. */
296	unsigned u1PCID : 1;
297	/** Bit 18 - Direct Cache Access. */
298	unsigned u1DCA : 1;
299	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
300	unsigned u1SSE4_1 : 1;
301	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
302	unsigned u1SSE4_2 : 1;
303	/** Bit 21 - x2APIC. */
304	unsigned u1x2APIC : 1;
305	/** Bit 22 - MOVBE - Supports MOVBE. */
306	unsigned u1MOVBE : 1;
307	/** Bit 23 - POPCNT - Supports POPCNT. */
308	unsigned u1POPCNT : 1;
309	/** Bit 24 - TSC-Deadline. */
310	unsigned u1TSCDEADLINE : 1;
311	/** Bit 25 - AES. */
312	unsigned u1AES : 1;
313	/** Bit 26 - XSAVE - Supports XSAVE. */
314	unsigned u1XSAVE : 1;
315	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
316	unsigned u1OSXSAVE : 1;
317	/** Bit 28 - AVX - Supports AVX instruction extensions. */
318	unsigned u1AVX : 1;
319	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
320	unsigned u1F16C : 1;
321	/** Bit 30 - RDRAND - Supports RDRAND. */
322	unsigned u1RDRAND : 1;
323	/** Bit 31 - Hypervisor present (we're a guest). */
324	unsigned u1HVP : 1;
325	} X86CPUIDFEATECX;
326	#else /* VBOX_FOR_DTRACE_LIB */
327	typedef uint32_t X86CPUIDFEATECX;
328	#endif /* VBOX_FOR_DTRACE_LIB */
329	/** Pointer to CPUID Feature Information - ECX. */
330	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
331	/** Pointer to const CPUID Feature Information - ECX. */
332	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
333
334
335	/** CPUID Feature Information - EDX.
336	* CPUID query with EAX=1.
337	*/
338	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
339	typedef struct X86CPUIDFEATEDX
340	{
341	/** Bit 0 - FPU - x87 FPU on Chip. */
342	unsigned u1FPU : 1;
343	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
344	unsigned u1VME : 1;
345	/** Bit 2 - DE - Debugging extensions. */
346	unsigned u1DE : 1;
347	/** Bit 3 - PSE - Page Size Extension. */
348	unsigned u1PSE : 1;
349	/** Bit 4 - TSC - Time Stamp Counter. */
350	unsigned u1TSC : 1;
351	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
352	unsigned u1MSR : 1;
353	/** Bit 6 - PAE - Physical Address Extension. */
354	unsigned u1PAE : 1;
355	/** Bit 7 - MCE - Machine Check Exception. */
356	unsigned u1MCE : 1;
357	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
358	unsigned u1CX8 : 1;
359	/** Bit 9 - APIC - APIC On-Chip. */
360	unsigned u1APIC : 1;
361	/** Bit 10 - Reserved. */
362	unsigned u1Reserved1 : 1;
363	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
364	unsigned u1SEP : 1;
365	/** Bit 12 - MTRR - Memory Type Range Registers. */
366	unsigned u1MTRR : 1;
367	/** Bit 13 - PGE - PTE Global Bit. */
368	unsigned u1PGE : 1;
369	/** Bit 14 - MCA - Machine Check Architecture. */
370	unsigned u1MCA : 1;
371	/** Bit 15 - CMOV - Conditional Move Instructions. */
372	unsigned u1CMOV : 1;
373	/** Bit 16 - PAT - Page Attribute Table. */
374	unsigned u1PAT : 1;
375	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
376	unsigned u1PSE36 : 1;
377	/** Bit 18 - PSN - Processor Serial Number. */
378	unsigned u1PSN : 1;
379	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
380	unsigned u1CLFSH : 1;
381	/** Bit 20 - Reserved. */
382	unsigned u1Reserved2 : 1;
383	/** Bit 21 - DS - Debug Store. */
384	unsigned u1DS : 1;
385	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
386	unsigned u1ACPI : 1;
387	/** Bit 23 - MMX - Intel MMX 'Technology'. */
388	unsigned u1MMX : 1;
389	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
390	unsigned u1FXSR : 1;
391	/** Bit 25 - SSE - SSE Support. */
392	unsigned u1SSE : 1;
393	/** Bit 26 - SSE2 - SSE2 Support. */
394	unsigned u1SSE2 : 1;
395	/** Bit 27 - SS - Self Snoop. */
396	unsigned u1SS : 1;
397	/** Bit 28 - HTT - Hyper-Threading Technology. */
398	unsigned u1HTT : 1;
399	/** Bit 29 - TM - Thermal Monitor. */
400	unsigned u1TM : 1;
401	/** Bit 30 - Reserved - . */
402	unsigned u1Reserved3 : 1;
403	/** Bit 31 - PBE - Pending Break Enabled. */
404	unsigned u1PBE : 1;
405	} X86CPUIDFEATEDX;
406	#else /* VBOX_FOR_DTRACE_LIB */
407	typedef uint32_t X86CPUIDFEATEDX;
408	#endif /* VBOX_FOR_DTRACE_LIB */
409	/** Pointer to CPUID Feature Information - EDX. */
410	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
411	/** Pointer to const CPUID Feature Information - EDX. */
412	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
413
414	/** @name CPUID Vendor information.
415	* CPUID query with EAX=0.
416	* @{
417	*/
418	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
419	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
420	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
421
422	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
423	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
424	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
425
426	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
427	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
428	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
429
430	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
431	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
432	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
433
434	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
435	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
436	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
437	/** @} */
438
439
440	/** @name CPUID Feature information.
441	* CPUID query with EAX=1.
442	* @{
443	*/
444	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
445	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
446	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
447	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
448	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
449	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
450	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
451	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
452	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
453	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
454	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
455	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
456	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
457	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
458	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
459	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
460	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
461	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
462	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
463	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
464	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
465	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
466	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
467	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
468	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
469	/** ECX Bit 12 - FMA. */
470	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
471	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
472	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
473	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
474	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
475	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
476	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
477	/** ECX Bit 17 - PCID - Process-context identifiers. */
478	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
479	/** ECX Bit 18 - DCA - Direct Cache Access. */
480	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
481	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
482	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
483	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
484	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
485	/** ECX Bit 21 - x2APIC support. */
486	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
487	/** ECX Bit 22 - MOVBE instruction. */
488	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
489	/** ECX Bit 23 - POPCNT instruction. */
490	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
491	/** ECX Bir 24 - TSC-Deadline. */
492	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
493	/** ECX Bit 25 - AES instructions. */
494	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
495	/** ECX Bit 26 - XSAVE instruction. */
496	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
497	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
498	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
499	/** ECX Bit 28 - AVX. */
500	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
501	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
502	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
503	/** ECX Bit 30 - RDRAND instruction. */
504	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
505	/** ECX Bit 31 - Hypervisor Present (software only). */
506	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
507
508
509	/** Bit 0 - FPU - x87 FPU on Chip. */
510	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
511	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
512	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
513	/** Bit 2 - DE - Debugging extensions. */
514	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
515	/** Bit 3 - PSE - Page Size Extension. */
516	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
517	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
518	/** Bit 4 - TSC - Time Stamp Counter. */
519	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
520	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
521	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
522	/** Bit 6 - PAE - Physical Address Extension. */
523	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
524	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
525	/** Bit 7 - MCE - Machine Check Exception. */
526	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
527	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
528	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
529	/** Bit 9 - APIC - APIC On-Chip. */
530	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
531	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
532	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
533	/** Bit 12 - MTRR - Memory Type Range Registers. */
534	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
535	/** Bit 13 - PGE - PTE Global Bit. */
536	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
537	/** Bit 14 - MCA - Machine Check Architecture. */
538	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
539	/** Bit 15 - CMOV - Conditional Move Instructions. */
540	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
541	/** Bit 16 - PAT - Page Attribute Table. */
542	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
543	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
544	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
545	/** Bit 18 - PSN - Processor Serial Number. */
546	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
547	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
548	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
549	/** Bit 21 - DS - Debug Store. */
550	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
551	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
552	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
553	/** Bit 23 - MMX - Intel MMX Technology. */
554	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
555	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
556	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
557	/** Bit 25 - SSE - SSE Support. */
558	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
559	/** Bit 26 - SSE2 - SSE2 Support. */
560	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
561	/** Bit 27 - SS - Self Snoop. */
562	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
563	/** Bit 28 - HTT - Hyper-Threading Technology. */
564	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
565	/** Bit 29 - TM - Therm. Monitor. */
566	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
567	/** Bit 31 - PBE - Pending Break Enabled. */
568	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
569	/** @} */
570
571	/** @name CPUID mwait/monitor information.
572	* CPUID query with EAX=5.
573	* @{
574	*/
575	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
576	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
577	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
578	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
579	/** @} */
580
581
582	/** @name CPUID Structured Extended Feature information.
583	* CPUID query with EAX=7.
584	* @{
585	*/
586	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
588	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
589	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
590	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
591	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
592	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
593	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
594	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
595	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
596	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
597	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
598	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
599	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
600	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
601	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
602	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
603	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
604	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
605	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
606	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
607	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
608	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
609	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
610	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
611	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
612	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
613	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
614	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
615	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
616	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
617	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
618	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
619	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
620	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
621	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
622	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
623	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
624	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
625	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
626	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
627	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
628	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
629	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
630	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
631	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
632	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
633	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
634	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
635	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
636	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
637	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
638
639	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
640	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
641	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
642	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
643	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
644	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
645	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
646	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
647	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
648	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
649	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
650	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
651	/** ECX Bit 22 - RDPID - Support pread process ID. */
652	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
653	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
654	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
655
656	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
657	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
658	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
659	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
660	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
661	* IBPB command in IA32_PRED_CMD. */
662	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
663	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
664	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
665	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
666	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
667	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
668	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
669	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
670	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
671
672	/** @} */
673
674
675	/** @name CPUID Extended Feature information.
676	* CPUID query with EAX=0x80000001.
677	* @{
678	*/
679	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
680	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
681
682	/** EDX Bit 11 - SYSCALL/SYSRET. */
683	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
684	/** EDX Bit 20 - No-Execute/Execute-Disable. */
685	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
686	/** EDX Bit 26 - 1 GB large page. */
687	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
688	/** EDX Bit 27 - RDTSCP. */
689	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
690	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
691	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
692	/** @}*/
693
694	/** @name CPUID AMD Feature information.
695	* CPUID query with EAX=0x80000001.
696	* @{
697	*/
698	/** Bit 0 - FPU - x87 FPU on Chip. */
699	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
700	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
701	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
702	/** Bit 2 - DE - Debugging extensions. */
703	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
704	/** Bit 3 - PSE - Page Size Extension. */
705	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
706	/** Bit 4 - TSC - Time Stamp Counter. */
707	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
708	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
709	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
710	/** Bit 6 - PAE - Physical Address Extension. */
711	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
712	/** Bit 7 - MCE - Machine Check Exception. */
713	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
714	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
715	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
716	/** Bit 9 - APIC - APIC On-Chip. */
717	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
718	/** Bit 12 - MTRR - Memory Type Range Registers. */
719	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
720	/** Bit 13 - PGE - PTE Global Bit. */
721	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
722	/** Bit 14 - MCA - Machine Check Architecture. */
723	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
724	/** Bit 15 - CMOV - Conditional Move Instructions. */
725	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
726	/** Bit 16 - PAT - Page Attribute Table. */
727	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
728	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
729	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
730	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
731	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
732	/** Bit 23 - MMX - Intel MMX Technology. */
733	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
734	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
735	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
736	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
737	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
738	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
739	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
740	/** Bit 31 - 3DNOW - AMD 3DNow. */
741	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
742
743	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
744	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
745	/** Bit 2 - SVM - AMD VM extensions. */
746	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
747	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
748	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
749	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
750	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
751	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
752	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
753	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
754	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
755	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
756	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
757	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
758	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
759	/** Bit 9 - OSVW - AMD OS visible workaround. */
760	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
761	/** Bit 10 - IBS - Instruct based sampling. */
762	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
763	/** Bit 11 - XOP - Extended operation support (see APM6). */
764	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
765	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
766	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
767	/** Bit 13 - WDT - AMD Watchdog timer support. */
768	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
769	/** Bit 15 - LWP - Lightweight profiling support. */
770	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
771	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
772	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
773	/** Bit 19 - NodeId - Indicates support for
774	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
775	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
776	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
777	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
778	/** Bit 22 - TopologyExtensions - . */
779	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
780	/** @} */
781
782
783	/** @name CPUID AMD Feature information.
784	* CPUID query with EAX=0x80000007.
785	* @{
786	*/
787	/** Bit 0 - TS - Temperature Sensor. */
788	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
789	/** Bit 1 - FID - Frequency ID Control. */
790	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
791	/** Bit 2 - VID - Voltage ID Control. */
792	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
793	/** Bit 3 - TTP - THERMTRIP. */
794	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
795	/** Bit 4 - TM - Hardware Thermal Control. */
796	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
797	/** Bit 5 - STC - Software Thermal Control. */
798	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
799	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
800	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
801	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
802	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
803	/** Bit 8 - TSCINVAR - TSC Invariant. */
804	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
805	/** Bit 9 - CPB - TSC Invariant. */
806	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
807	/** Bit 10 - EffFreqRO - MPERF/APERF. */
808	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
809	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
810	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
811	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
812	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
813	/** @} */
814
815
816	/** @name CPUID AMD extended feature extensions ID (EBX).
817	* CPUID query with EAX=0x80000008.
818	* @{
819	*/
820	/** Bit 0 - CLZERO - Clear zero instruction. */
821	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
822	/** Bit 1 - IRPerf - Instructions retired count support. */
823	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
824	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
825	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
826	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
827	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
828	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
829	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
830	/* AMD pipeline length: 9 feature bits ;-) */
831	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
832	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
833	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
834	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
835	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
836	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
837	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
838	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
839	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
840	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
841	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
842	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
843	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
844	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
845	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
846	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
847	/** Bit 26 - Speculative Store Bypass Disable not required. */
848	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
849	/** @} */
850
851
852	/** @name CPUID AMD SVM Feature information.
853	* CPUID query with EAX=0x8000000a.
854	* @{
855	*/
856	/** Bit 0 - NP - Nested Paging supported. */
857	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
858	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
859	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
860	/** Bit 2 - SVML - SVM locking bit supported. */
861	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
862	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
863	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
864	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
865	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
866	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
867	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
868	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
869	* VMCB.TLB_Control is supported. */
870	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
871	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
872	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
873	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
874	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
875	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
876	* intercept filter cycle count threshold. */
877	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
878	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
879	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
880	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
881	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
882	/** Bit 16 - VGIF - Supports virtualized GIF. */
883	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
884	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
885	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
886	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
887	* mode. */
888	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
889	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
890	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
891	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
892	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
893	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
894	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
895	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
896	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
897	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
898	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
899	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
900	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
901	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
902	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
903	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
904	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
905	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
906	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
907	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
908	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
909
910	/** @} */
911
912
913	/** @name CR0
914	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
915	* reserved flags.
916	* @{ */
917	/** Bit 0 - PE - Protection Enabled */
918	#define X86_CR0_PE RT_BIT_32(0)
919	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
920	/** Bit 1 - MP - Monitor Coprocessor */
921	#define X86_CR0_MP RT_BIT_32(1)
922	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
923	/** Bit 2 - EM - Emulation. */
924	#define X86_CR0_EM RT_BIT_32(2)
925	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
926	/** Bit 3 - TS - Task Switch. */
927	#define X86_CR0_TS RT_BIT_32(3)
928	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
929	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
930	#define X86_CR0_ET RT_BIT_32(4)
931	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
932	/** Bit 5 - NE - Numeric error (486+). */
933	#define X86_CR0_NE RT_BIT_32(5)
934	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
935	/** Bit 16 - WP - Write Protect (486+). */
936	#define X86_CR0_WP RT_BIT_32(16)
937	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
938	/** Bit 18 - AM - Alignment Mask (486+). */
939	#define X86_CR0_AM RT_BIT_32(18)
940	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
941	/** Bit 29 - NW - Not Write-though (486+). */
942	#define X86_CR0_NW RT_BIT_32(29)
943	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
944	/** Bit 30 - WP - Cache Disable (486+). */
945	#define X86_CR0_CD RT_BIT_32(30)
946	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
947	/** Bit 31 - PG - Paging. */
948	#define X86_CR0_PG RT_BIT_32(31)
949	#define X86_CR0_PAGING RT_BIT_32(31)
950	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
951	/** @} */
952
953
954	/** @name CR3
955	* @{ */
956	/** Bit 3 - PWT - Page-level Writes Transparent. */
957	#define X86_CR3_PWT RT_BIT_32(3)
958	/** Bit 4 - PCD - Page-level Cache Disable. */
959	#define X86_CR3_PCD RT_BIT_32(4)
960	/** Bits 12-31 - - Page directory page number. */
961	#define X86_CR3_PAGE_MASK (0xfffff000)
962	/** Bits 5-31 - - PAE Page directory page number. */
963	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
964	/** Bits 12-51 - - AMD64 PML4 page number.
965	* @note This is a maxed out mask, the actual acceptable CR3 value can
966	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
967	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
968	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
969	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
970	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
971	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
972	/** @} */
973
974
975	/** @name CR4
976	* @{ */
977	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
978	#define X86_CR4_VME RT_BIT_32(0)
979	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
980	#define X86_CR4_PVI RT_BIT_32(1)
981	/** Bit 2 - TSD - Time Stamp Disable. */
982	#define X86_CR4_TSD RT_BIT_32(2)
983	/** Bit 3 - DE - Debugging Extensions. */
984	#define X86_CR4_DE RT_BIT_32(3)
985	/** Bit 4 - PSE - Page Size Extension. */
986	#define X86_CR4_PSE RT_BIT_32(4)
987	/** Bit 5 - PAE - Physical Address Extension. */
988	#define X86_CR4_PAE RT_BIT_32(5)
989	/** Bit 6 - MCE - Machine-Check Enable. */
990	#define X86_CR4_MCE RT_BIT_32(6)
991	/** Bit 7 - PGE - Page Global Enable. */
992	#define X86_CR4_PGE RT_BIT_32(7)
993	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
994	#define X86_CR4_PCE RT_BIT_32(8)
995	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
996	#define X86_CR4_OSFXSR RT_BIT_32(9)
997	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
998	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
999	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1000	#define X86_CR4_UMIP RT_BIT_32(11)
1001	/** Bit 13 - VMXE - VMX mode is enabled. */
1002	#define X86_CR4_VMXE RT_BIT_32(13)
1003	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1004	#define X86_CR4_SMXE RT_BIT_32(14)
1005	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1006	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1007	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1008	#define X86_CR4_PCIDE RT_BIT_32(17)
1009	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1010	* extended states. */
1011	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1012	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1013	#define X86_CR4_SMEP RT_BIT_32(20)
1014	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1015	#define X86_CR4_SMAP RT_BIT_32(21)
1016	/** Bit 22 - PKE - Protection Key Enable. */
1017	#define X86_CR4_PKE RT_BIT_32(22)
1018	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1019	#define X86_CR4_CET RT_BIT_32(23)
1020	/** @} */
1021
1022
1023	/** @name DR6
1024	* @{ */
1025	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1026	#define X86_DR6_B0 RT_BIT_32(0)
1027	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1028	#define X86_DR6_B1 RT_BIT_32(1)
1029	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1030	#define X86_DR6_B2 RT_BIT_32(2)
1031	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1032	#define X86_DR6_B3 RT_BIT_32(3)
1033	/** Mask of all the Bx bits. */
1034	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1035	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1036	#define X86_DR6_BD RT_BIT_32(13)
1037	/** Bit 14 - BS - Single step */
1038	#define X86_DR6_BS RT_BIT_32(14)
1039	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1040	#define X86_DR6_BT RT_BIT_32(15)
1041	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1042	#define X86_DR6_RTM RT_BIT_32(16)
1043	/** Value of DR6 after powerup/reset. */
1044	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1045	/** Bits which must be 1s in DR6. */
1046	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1047	/** Bits which must be 1s in DR6, when RTM is supported. */
1048	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1049	/** Bits which must be 0s in DR6. */
1050	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1051	/** Bits which must be 0s on writes to DR6. */
1052	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1053	/** @} */
1054
1055	/** Get the DR6.Bx bit for a the given breakpoint. */
1056	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1057
1058
1059	/** @name DR7
1060	* @{ */
1061	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1062	#define X86_DR7_L0 RT_BIT_32(0)
1063	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1064	#define X86_DR7_G0 RT_BIT_32(1)
1065	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1066	#define X86_DR7_L1 RT_BIT_32(2)
1067	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1068	#define X86_DR7_G1 RT_BIT_32(3)
1069	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1070	#define X86_DR7_L2 RT_BIT_32(4)
1071	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1072	#define X86_DR7_G2 RT_BIT_32(5)
1073	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1074	#define X86_DR7_L3 RT_BIT_32(6)
1075	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1076	#define X86_DR7_G3 RT_BIT_32(7)
1077	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1078	#define X86_DR7_LE RT_BIT_32(8)
1079	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1080	#define X86_DR7_GE RT_BIT_32(9)
1081
1082	/** L0, L1, L2, and L3. */
1083	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1084	/** L0, L1, L2, and L3. */
1085	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1086
1087	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1088	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1089	#define X86_DR7_RTM RT_BIT_32(11)
1090	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1091	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1092	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1093	* instruction is executed.
1094	* @see http://www.rcollins.org/secrets/DR7.html */
1095	#define X86_DR7_ICE_IR RT_BIT_32(12)
1096	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1097	* any DR register is accessed. */
1098	#define X86_DR7_GD RT_BIT_32(13)
1099	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1100	* Pentium. */
1101	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1102	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1103	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1104	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1105	#define X86_DR7_RW0_MASK (3 << 16)
1106	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1107	#define X86_DR7_LEN0_MASK (3 << 18)
1108	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1109	#define X86_DR7_RW1_MASK (3 << 20)
1110	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1111	#define X86_DR7_LEN1_MASK (3 << 22)
1112	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1113	#define X86_DR7_RW2_MASK (3 << 24)
1114	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1115	#define X86_DR7_LEN2_MASK (3 << 26)
1116	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1117	#define X86_DR7_RW3_MASK (3 << 28)
1118	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1119	#define X86_DR7_LEN3_MASK (3 << 30)
1120
1121	/** Bits which reads as 1s. */
1122	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1123	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1124	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1125	/** Bits which must be 0s when writing to DR7. */
1126	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1127
1128	/** Calcs the L bit of Nth breakpoint.
1129	* @param iBp The breakpoint number [0..3].
1130	*/
1131	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1132
1133	/** Calcs the G bit of Nth breakpoint.
1134	* @param iBp The breakpoint number [0..3].
1135	*/
1136	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1137
1138	/** Calcs the L and G bits of Nth breakpoint.
1139	* @param iBp The breakpoint number [0..3].
1140	*/
1141	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1142
1143	/** @name Read/Write values.
1144	* @{ */
1145	/** Break on instruction fetch only. */
1146	#define X86_DR7_RW_EO UINT32_C(0)
1147	/** Break on write only. */
1148	#define X86_DR7_RW_WO UINT32_C(1)
1149	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1150	#define X86_DR7_RW_IO UINT32_C(2)
1151	/** Break on read or write (but not instruction fetches). */
1152	#define X86_DR7_RW_RW UINT32_C(3)
1153	/** @} */
1154
1155	/** Shifts a X86_DR7_RW_* value to its right place.
1156	* @param iBp The breakpoint number [0..3].
1157	* @param fRw One of the X86_DR7_RW_* value.
1158	*/
1159	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1160
1161	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1162	* one of the X86_DR7_RW_XXX constants).
1163	*
1164	* @returns X86_DR7_RW_XXX
1165	* @param uDR7 DR7 value
1166	* @param iBp The breakpoint number [0..3].
1167	*/
1168	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1169
1170	/** R/W0, R/W1, R/W2, and R/W3. */
1171	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1172
1173	#ifndef VBOX_FOR_DTRACE_LIB
1174	/** Checks the RW and LEN fields are set up for an instruction breakpoint.
1175	* @note This does not check if it's enabled. */
1176	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1177	/** Checks if an instruction breakpoint is enabled and configured correctly.
1178	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1179	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1180	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1181	/** Checks if there are any instruction fetch breakpoint types configured in the
1182	* RW and LEN registers.
1183	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1184	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1185	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1186	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1187	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1188	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1189
1190	/** Checks if there are any I/O breakpoint types configured in the RW
1191	* registers. Does NOT check if these are enabled, sorry. */
1192	# define X86_DR7_ANY_RW_IO(uDR7) \
1193	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1194	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1195	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1196	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1197	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1198	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1199	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1200	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1201	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1202	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1203	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1204
1205	#endif /* !VBOX_FOR_DTRACE_LIB */
1206
1207	/** @name Length values.
1208	* @{ */
1209	#define X86_DR7_LEN_BYTE UINT32_C(0)
1210	#define X86_DR7_LEN_WORD UINT32_C(1)
1211	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1212	#define X86_DR7_LEN_DWORD UINT32_C(3)
1213	/** @} */
1214
1215	/** Shifts a X86_DR7_LEN_* value to its right place.
1216	* @param iBp The breakpoint number [0..3].
1217	* @param cb One of the X86_DR7_LEN_* values.
1218	*/
1219	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1220
1221	/** Fetch the breakpoint length bits from the DR7 value.
1222	* @param uDR7 DR7 value
1223	* @param iBp The breakpoint number [0..3].
1224	*/
1225	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1226
1227	/** Mask used to check if any breakpoints are enabled. */
1228	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1229
1230	/** LEN0, LEN1, LEN2, and LEN3. */
1231	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1232	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1233	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1234
1235	/** Value of DR7 after powerup/reset. */
1236	#define X86_DR7_INIT_VAL 0x400
1237	/** @} */
1238
1239
1240	/** @name Machine Specific Registers
1241	* @{
1242	*/
1243	/** Machine check address register (P5). */
1244	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1245	/** Machine check type register (P5). */
1246	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1247	/** Time Stamp Counter. */
1248	#define MSR_IA32_TSC 0x10
1249	#define MSR_IA32_CESR UINT32_C(0x00000011)
1250	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1251	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1252
1253	#define MSR_IA32_PLATFORM_ID 0x17
1254
1255	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1256	# define MSR_IA32_APICBASE 0x1b
1257	/** Local APIC enabled. */
1258	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1259	/** X2APIC enabled (requires the EN bit to be set). */
1260	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1261	/** The processor is the boot strap processor (BSP). */
1262	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1263	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1264	* width. */
1265	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1266	/** The default physical base address of the APIC. */
1267	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1268	/** Gets the physical base address from the MSR. */
1269	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1270	#endif
1271
1272	/** Undocumented intel MSR for reporting thread and core counts.
1273	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1274	* first 16 bits is the thread count. The next 16 bits the core count, except
1275	* on Westmere where it seems it's only the next 4 bits for some reason. */
1276	#define MSR_CORE_THREAD_COUNT 0x35
1277
1278	/** CPU Feature control. */
1279	#define MSR_IA32_FEATURE_CONTROL 0x3A
1280	/** Feature control - Lock MSR from writes (R/W0). */
1281	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1282	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1283	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1284	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1285	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1286	/** Feature control - SENTER local functions enable (R/WL). */
1287	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1288	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1289	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1290	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1291	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1292	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1293	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1294	/** Feature control - SENTER global enable (R/WL). */
1295	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1296	/** Feature control - SGX launch control enable (R/WL). */
1297	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1298	/** Feature control - SGX global enable (R/WL). */
1299	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1300	/** Feature control - LMCE on (R/WL). */
1301	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1302
1303	/** Per-processor TSC adjust MSR. */
1304	#define MSR_IA32_TSC_ADJUST 0x3B
1305
1306	/** Spectre control register.
1307	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1308	#define MSR_IA32_SPEC_CTRL 0x48
1309	/** IBRS - Indirect branch restricted speculation. */
1310	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1311	/** STIBP - Single thread indirect branch predictors. */
1312	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1313	/** SSBD - Speculative Store Bypass Disable. */
1314	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1315
1316	/** Prediction command register.
1317	* Write only, logical processor scope, no state since write only. */
1318	#define MSR_IA32_PRED_CMD 0x49
1319	/** IBPB - Indirect branch prediction barrie when written as 1. */
1320	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1321
1322	/** BIOS update trigger (microcode update). */
1323	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1324
1325	/** BIOS update signature (microcode). */
1326	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1327
1328	/** SMM monitor control. */
1329	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1330	/** SMM control - Valid. */
1331	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1332	/** SMM control - VMXOFF unblocks SMI. */
1333	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1334	/** SMM control - MSEG base physical address. */
1335	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1336
1337	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1338	#define MSR_IA32_SMBASE 0x9E
1339
1340	/** General performance counter no. 0. */
1341	#define MSR_IA32_PMC0 0xC1
1342	/** General performance counter no. 1. */
1343	#define MSR_IA32_PMC1 0xC2
1344	/** General performance counter no. 2. */
1345	#define MSR_IA32_PMC2 0xC3
1346	/** General performance counter no. 3. */
1347	#define MSR_IA32_PMC3 0xC4
1348	/** General performance counter no. 4. */
1349	#define MSR_IA32_PMC4 0xC5
1350	/** General performance counter no. 5. */
1351	#define MSR_IA32_PMC5 0xC6
1352	/** General performance counter no. 6. */
1353	#define MSR_IA32_PMC6 0xC7
1354	/** General performance counter no. 7. */
1355	#define MSR_IA32_PMC7 0xC8
1356
1357	/** Nehalem power control. */
1358	#define MSR_IA32_PLATFORM_INFO 0xCE
1359
1360	/** Get FSB clock status (Intel-specific). */
1361	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1362
1363	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1364	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1365
1366	/** C0 Maximum Frequency Clock Count */
1367	#define MSR_IA32_MPERF 0xE7
1368	/** C0 Actual Frequency Clock Count */
1369	#define MSR_IA32_APERF 0xE8
1370
1371	/** MTRR Capabilities. */
1372	#define MSR_IA32_MTRR_CAP 0xFE
1373	/** Bits 0-7 - VCNT - Variable range registers count. */
1374	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1375	/** Bit 8 - FIX - Fixed range registers supported. */
1376	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1377	/** Bit 10 - WC - Write-Combining memory type supported. */
1378	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1379	/** Bit 11 - SMRR - System Management Range Register supported. */
1380	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1381	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1382	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1383
1384	/**
1385	* Variable-range MTRR MSR pair.
1386	*/
1387	typedef struct X86MTRRVAR
1388	{
1389	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1390	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1391	} X86MTRRVAR;
1392	#ifndef VBOX_FOR_DTRACE_LIB
1393	AssertCompileSize(X86MTRRVAR, 16);
1394	#endif
1395	/** Pointer to a variable-range MTRR MSR pair. */
1396	typedef X86MTRRVAR *PX86MTRRVAR;
1397	/** Pointer to a const variable-range MTRR MSR pair. */
1398	typedef const X86MTRRVAR *PCX86MTRRVAR;
1399
1400	/** Memory types that can be encoded in MTRRs.
1401	* @{ */
1402	/** Uncacheable. */
1403	#define X86_MTRR_MT_UC 0
1404	/** Write Combining. */
1405	#define X86_MTRR_MT_WC 1
1406	/** Write-through. */
1407	#define X86_MTRR_MT_WT 4
1408	/** Write-protected. */
1409	#define X86_MTRR_MT_WP 5
1410	/** Writeback. */
1411	#define X86_MTRR_MT_WB 6
1412	/** @}*/
1413
1414	/** Architecture capabilities (bugfixes). */
1415	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1416	/** CPU is no subject to meltdown problems. */
1417	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1418	/** CPU has better IBRS and you can leave it on all the time. */
1419	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1420	/** CPU has return stack buffer (RSB) override. */
1421	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1422	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1423	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1424	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1425	/** CPU does not suffer from MDS issues. */
1426	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1427
1428	/** Flush command register. */
1429	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1430	/** Flush the level 1 data cache when this bit is written. */
1431	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1432
1433	/** Cache control/info. */
1434	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1435
1436	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1437	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1438	* R0 SS == CS + 8
1439	* R3 CS == CS + 16
1440	* R3 SS == CS + 24
1441	*/
1442	#define MSR_IA32_SYSENTER_CS 0x174
1443	/** SYSENTER_ESP - the R0 ESP. */
1444	#define MSR_IA32_SYSENTER_ESP 0x175
1445	/** SYSENTER_EIP - the R0 EIP. */
1446	#define MSR_IA32_SYSENTER_EIP 0x176
1447	#endif
1448
1449	/** Machine Check Global Capabilities Register. */
1450	#define MSR_IA32_MCG_CAP 0x179
1451	/** Machine Check Global Status Register. */
1452	#define MSR_IA32_MCG_STATUS 0x17A
1453	/** Machine Check Global Control Register. */
1454	#define MSR_IA32_MCG_CTRL 0x17B
1455
1456	/** Page Attribute Table. */
1457	#define MSR_IA32_CR_PAT 0x277
1458	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1459	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1460	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1461
1462	/** Memory types that can be encoded in the IA32_PAT MSR.
1463	* @{ */
1464	/** Uncacheable. */
1465	#define MSR_IA32_PAT_MT_UC 0
1466	/** Write Combining. */
1467	#define MSR_IA32_PAT_MT_WC 1
1468	/** Reserved value 2. */
1469	#define MSR_IA32_PAT_MT_RSVD_2 2
1470	/** Reserved value 3. */
1471	#define MSR_IA32_PAT_MT_RSVD_3 3
1472	/** Write-through. */
1473	#define MSR_IA32_PAT_MT_WT 4
1474	/** Write-protected. */
1475	#define MSR_IA32_PAT_MT_WP 5
1476	/** Writeback. */
1477	#define MSR_IA32_PAT_MT_WB 6
1478	/** Uncached (UC-). */
1479	#define MSR_IA32_PAT_MT_UCD 7
1480	/** @}*/
1481
1482
1483	/** Performance event select MSRs. (Intel only) */
1484	#define MSR_IA32_PERFEVTSEL0 0x186
1485	#define MSR_IA32_PERFEVTSEL1 0x187
1486	#define MSR_IA32_PERFEVTSEL2 0x188
1487	#define MSR_IA32_PERFEVTSEL3 0x189
1488
1489	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1490	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1491	* holds a ratio that Apple takes for TSC granularity.
1492	*
1493	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1494	#define MSR_FLEX_RATIO 0x194
1495	/** Performance state value and starting with Intel core more.
1496	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1497	#define MSR_IA32_PERF_STATUS 0x198
1498	#define MSR_IA32_PERF_CTL 0x199
1499	#define MSR_IA32_THERM_STATUS 0x19c
1500
1501	/** Offcore response event select registers. */
1502	#define MSR_OFFCORE_RSP_0 0x1a6
1503	#define MSR_OFFCORE_RSP_1 0x1a7
1504
1505	/** Enable misc. processor features (R/W). */
1506	#define MSR_IA32_MISC_ENABLE 0x1A0
1507	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1508	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1509	/** Automatic Thermal Control Circuit Enable (R/W). */
1510	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1511	/** Performance Monitoring Available (R). */
1512	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1513	/** Branch Trace Storage Unavailable (R/O). */
1514	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1515	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1516	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1517	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1518	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1519	/** If MONITOR/MWAIT is supported (R/W). */
1520	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1521	/** Limit CPUID Maxval to 3 leafs (R/W). */
1522	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1523	/** When set to 1, xTPR messages are disabled (R/W). */
1524	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1525	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1526	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1527
1528	/** Trace/Profile Resource Control (R/W) */
1529	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1530	/** Last branch record. */
1531	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1532	/** Branch trace flag (single step on branches). */
1533	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1534	/** Performance monitoring pin control (AMD only). */
1535	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1536	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1537	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1538	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1539	/** Trace message enable (Intel only). */
1540	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1541	/** Branch trace store (Intel only). */
1542	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1543	/** Branch trace interrupt (Intel only). */
1544	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1545	/** Branch trace off in privileged code (Intel only). */
1546	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1547	/** Branch trace off in user code (Intel only). */
1548	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1549	/** Freeze LBR on PMI flag (Intel only). */
1550	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1551	/** Freeze PERFMON on PMI flag (Intel only). */
1552	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1553	/** Freeze while SMM enabled (Intel only). */
1554	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1555	/** Advanced debugging of RTM regions (Intel only). */
1556	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1557	/** Debug control MSR valid bits (Intel only). */
1558	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1559	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1560	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1561	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1562	\| MSR_IA32_DEBUGCTL_RTM)
1563
1564	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1565	* @{ */
1566	#define MSR_P4_LASTBRANCH_0 0x1db
1567	#define MSR_P4_LASTBRANCH_1 0x1dc
1568	#define MSR_P4_LASTBRANCH_2 0x1dd
1569	#define MSR_P4_LASTBRANCH_3 0x1de
1570
1571	/** LBR Top-of-stack MSR (index to most recent record). */
1572	#define MSR_P4_LASTBRANCH_TOS 0x1da
1573	/** @} */
1574
1575	/** @name Last branch registers for Core 2 and related Xeons.
1576	* @{ */
1577	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1578	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1579	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1580	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1581
1582	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1583	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1584	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1585	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1586
1587	/** LBR Top-of-stack MSR (index to most recent record). */
1588	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1589	/** @} */
1590
1591	/** @name Last branch registers.
1592	* @{ */
1593	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1594	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1595	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1596	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1597	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1598	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1599	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1600	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1601	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1602	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1603	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1604	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1605	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1606	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1607	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1608	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1609	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1610	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1611	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1612	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1613	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1614	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1615	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1616	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1617	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1618	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1619	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1620	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1621	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1622	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1623	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1624	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1625
1626	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1627	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1628	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1629	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1630	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1631	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1632	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1633	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1634	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1635	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1636	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1637	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1638	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1639	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1640	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1641	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1642	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1643	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1644	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1645	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1646	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1647	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1648	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1649	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1650	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1651	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1652	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1653	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1654	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1655	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1656	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1657	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1658
1659	#define MSR_LASTBRANCH_0_INFO 0xdc0
1660	#define MSR_LASTBRANCH_1_INFO 0xdc1
1661	#define MSR_LASTBRANCH_2_INFO 0xdc2
1662	#define MSR_LASTBRANCH_3_INFO 0xdc3
1663	#define MSR_LASTBRANCH_4_INFO 0xdc4
1664	#define MSR_LASTBRANCH_5_INFO 0xdc5
1665	#define MSR_LASTBRANCH_6_INFO 0xdc6
1666	#define MSR_LASTBRANCH_7_INFO 0xdc7
1667	#define MSR_LASTBRANCH_8_INFO 0xdc8
1668	#define MSR_LASTBRANCH_9_INFO 0xdc9
1669	#define MSR_LASTBRANCH_10_INFO 0xdca
1670	#define MSR_LASTBRANCH_11_INFO 0xdcb
1671	#define MSR_LASTBRANCH_12_INFO 0xdcc
1672	#define MSR_LASTBRANCH_13_INFO 0xdcd
1673	#define MSR_LASTBRANCH_14_INFO 0xdce
1674	#define MSR_LASTBRANCH_15_INFO 0xdcf
1675	#define MSR_LASTBRANCH_16_INFO 0xdd0
1676	#define MSR_LASTBRANCH_17_INFO 0xdd1
1677	#define MSR_LASTBRANCH_18_INFO 0xdd2
1678	#define MSR_LASTBRANCH_19_INFO 0xdd3
1679	#define MSR_LASTBRANCH_20_INFO 0xdd4
1680	#define MSR_LASTBRANCH_21_INFO 0xdd5
1681	#define MSR_LASTBRANCH_22_INFO 0xdd6
1682	#define MSR_LASTBRANCH_23_INFO 0xdd7
1683	#define MSR_LASTBRANCH_24_INFO 0xdd8
1684	#define MSR_LASTBRANCH_25_INFO 0xdd9
1685	#define MSR_LASTBRANCH_26_INFO 0xdda
1686	#define MSR_LASTBRANCH_27_INFO 0xddb
1687	#define MSR_LASTBRANCH_28_INFO 0xddc
1688	#define MSR_LASTBRANCH_29_INFO 0xddd
1689	#define MSR_LASTBRANCH_30_INFO 0xdde
1690	#define MSR_LASTBRANCH_31_INFO 0xddf
1691
1692	/** LBR branch tracking selection MSR. */
1693	#define MSR_LASTBRANCH_SELECT 0x1c8
1694	/** LBR Top-of-stack MSR (index to most recent record). */
1695	#define MSR_LASTBRANCH_TOS 0x1c9
1696	/** @} */
1697
1698	/** @name Last event record registers.
1699	* @{ */
1700	/** Last event record source IP register. */
1701	#define MSR_LER_FROM_IP 0x1dd
1702	/** Last event record destination IP register. */
1703	#define MSR_LER_TO_IP 0x1de
1704	/** @} */
1705
1706	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1707	#define MSR_IA32_TSX_CTRL 0x122
1708
1709	/** Variable range MTRRs.
1710	* @{ */
1711	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1712	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1713	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1714	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1715	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1716	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1717	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1718	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1719	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1720	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1721	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1722	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1723	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1724	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1725	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1726	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1727	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1728	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1729	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1730	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1731	/** @} */
1732
1733	/** Fixed range MTRRs.
1734	* @{ */
1735	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1736	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1737	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1738	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1739	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1740	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1741	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1742	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1743	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1744	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1745	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1746	/** @} */
1747
1748	/** MTRR Default Type.
1749	* @{ */
1750	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1751	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1752	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1753	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1754	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1755	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1756	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1757	/** @} */
1758
1759	/** Variable-range MTRR physical mask valid. */
1760	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1761
1762	/** Global performance counter control facilities (Intel only). */
1763	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1764	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1765	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1766
1767	/** Precise Event Based sampling (Intel only). */
1768	#define MSR_IA32_PEBS_ENABLE 0x3F1
1769
1770	#define MSR_IA32_MC0_CTL 0x400
1771	#define MSR_IA32_MC0_STATUS 0x401
1772
1773	/** Basic VMX information. */
1774	#define MSR_IA32_VMX_BASIC 0x480
1775	/** Allowed settings for pin-based VM execution controls. */
1776	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1777	/** Allowed settings for proc-based VM execution controls. */
1778	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1779	/** Allowed settings for the VM-exit controls. */
1780	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1781	/** Allowed settings for the VM-entry controls. */
1782	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1783	/** Misc VMX info. */
1784	#define MSR_IA32_VMX_MISC 0x485
1785	/** Fixed cleared bits in CR0. */
1786	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1787	/** Fixed set bits in CR0. */
1788	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1789	/** Fixed cleared bits in CR4. */
1790	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1791	/** Fixed set bits in CR4. */
1792	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1793	/** Information for enumerating fields in the VMCS. */
1794	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1795	/** Allowed settings for secondary processor-based VM-execution controls. */
1796	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1797	/** EPT capabilities. */
1798	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1799	/** Allowed settings of all pin-based VM execution controls. */
1800	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1801	/** Allowed settings of all proc-based VM execution controls. */
1802	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1803	/** Allowed settings of all VMX exit controls. */
1804	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1805	/** Allowed settings of all VMX entry controls. */
1806	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1807	/** Allowed settings for the VM-function controls. */
1808	#define MSR_IA32_VMX_VMFUNC 0x491
1809	/** Tertiary processor-based VM execution controls. */
1810	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1811	/** Secondary VM-exit controls. */
1812	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
1813
1814	/** Intel PT - Enable and control for trace packet generation. */
1815	#define MSR_IA32_RTIT_CTL 0x570
1816
1817	/** DS Save Area (R/W). */
1818	#define MSR_IA32_DS_AREA 0x600
1819	/** Running Average Power Limit (RAPL) power units. */
1820	#define MSR_RAPL_POWER_UNIT 0x606
1821	/** Package C3 Interrupt Response Limit. */
1822	#define MSR_PKGC3_IRTL 0x60a
1823	/** Package C6/C7S Interrupt Response Limit 1. */
1824	#define MSR_PKGC_IRTL1 0x60b
1825	/** Package C6/C7S Interrupt Response Limit 2. */
1826	#define MSR_PKGC_IRTL2 0x60c
1827	/** Package C2 Residency Counter. */
1828	#define MSR_PKG_C2_RESIDENCY 0x60d
1829	/** PKG RAPL Power Limit Control. */
1830	#define MSR_PKG_POWER_LIMIT 0x610
1831	/** PKG Energy Status. */
1832	#define MSR_PKG_ENERGY_STATUS 0x611
1833	/** PKG Perf Status. */
1834	#define MSR_PKG_PERF_STATUS 0x613
1835	/** PKG RAPL Parameters. */
1836	#define MSR_PKG_POWER_INFO 0x614
1837	/** DRAM RAPL Power Limit Control. */
1838	#define MSR_DRAM_POWER_LIMIT 0x618
1839	/** DRAM Energy Status. */
1840	#define MSR_DRAM_ENERGY_STATUS 0x619
1841	/** DRAM Performance Throttling Status. */
1842	#define MSR_DRAM_PERF_STATUS 0x61b
1843	/** DRAM RAPL Parameters. */
1844	#define MSR_DRAM_POWER_INFO 0x61c
1845	/** Package C10 Residency Counter. */
1846	#define MSR_PKG_C10_RESIDENCY 0x632
1847	/** PP0 Energy Status. */
1848	#define MSR_PP0_ENERGY_STATUS 0x639
1849	/** PP1 Energy Status. */
1850	#define MSR_PP1_ENERGY_STATUS 0x641
1851	/** Turbo Activation Ratio. */
1852	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1853	/** Core Performance Limit Reasons. */
1854	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1855
1856	/** Userspace Control flow Enforcement Technology setting. */
1857	#define MSR_IA32_U_CET 0x6a0
1858	/** Supervisor space Control flow Enforcement Technology setting. */
1859	#define MSR_IA32_S_CET 0x6a2
1860	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
1861	* @{ */
1862	/** Enables the Shadow stack. */
1863	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
1864	/** Enables WRSS{D,Q}W instructions. */
1865	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
1866	/** Enables indirect branch tracking. */
1867	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
1868	/** Enable legacy compatibility treatment for indirect branch tracking. */
1869	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
1870	/** Enables the use of no-track prefix for indirect branch tracking. */
1871	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
1872	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
1873	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
1874	/** Suppresses indirect branch tracking. */
1875	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
1876	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
1877	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
1878	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
1879	* on a ENDBRANCH instruction. */
1880	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
1881	/** @} */
1882
1883	/** X2APIC MSR range start. */
1884	#define MSR_IA32_X2APIC_START 0x800
1885	/** X2APIC MSR - APIC ID Register. */
1886	#define MSR_IA32_X2APIC_ID 0x802
1887	/** X2APIC MSR - APIC Version Register. */
1888	#define MSR_IA32_X2APIC_VERSION 0x803
1889	/** X2APIC MSR - Task Priority Register. */
1890	#define MSR_IA32_X2APIC_TPR 0x808
1891	/** X2APIC MSR - Processor Priority register. */
1892	#define MSR_IA32_X2APIC_PPR 0x80A
1893	/** X2APIC MSR - End Of Interrupt register. */
1894	#define MSR_IA32_X2APIC_EOI 0x80B
1895	/** X2APIC MSR - Logical Destination Register. */
1896	#define MSR_IA32_X2APIC_LDR 0x80D
1897	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1898	#define MSR_IA32_X2APIC_SVR 0x80F
1899	/** X2APIC MSR - In-service Register (bits 31:0). */
1900	#define MSR_IA32_X2APIC_ISR0 0x810
1901	/** X2APIC MSR - In-service Register (bits 63:32). */
1902	#define MSR_IA32_X2APIC_ISR1 0x811
1903	/** X2APIC MSR - In-service Register (bits 95:64). */
1904	#define MSR_IA32_X2APIC_ISR2 0x812
1905	/** X2APIC MSR - In-service Register (bits 127:96). */
1906	#define MSR_IA32_X2APIC_ISR3 0x813
1907	/** X2APIC MSR - In-service Register (bits 159:128). */
1908	#define MSR_IA32_X2APIC_ISR4 0x814
1909	/** X2APIC MSR - In-service Register (bits 191:160). */
1910	#define MSR_IA32_X2APIC_ISR5 0x815
1911	/** X2APIC MSR - In-service Register (bits 223:192). */
1912	#define MSR_IA32_X2APIC_ISR6 0x816
1913	/** X2APIC MSR - In-service Register (bits 255:224). */
1914	#define MSR_IA32_X2APIC_ISR7 0x817
1915	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1916	#define MSR_IA32_X2APIC_TMR0 0x818
1917	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1918	#define MSR_IA32_X2APIC_TMR1 0x819
1919	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1920	#define MSR_IA32_X2APIC_TMR2 0x81A
1921	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1922	#define MSR_IA32_X2APIC_TMR3 0x81B
1923	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1924	#define MSR_IA32_X2APIC_TMR4 0x81C
1925	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1926	#define MSR_IA32_X2APIC_TMR5 0x81D
1927	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1928	#define MSR_IA32_X2APIC_TMR6 0x81E
1929	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1930	#define MSR_IA32_X2APIC_TMR7 0x81F
1931	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1932	#define MSR_IA32_X2APIC_IRR0 0x820
1933	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1934	#define MSR_IA32_X2APIC_IRR1 0x821
1935	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1936	#define MSR_IA32_X2APIC_IRR2 0x822
1937	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1938	#define MSR_IA32_X2APIC_IRR3 0x823
1939	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1940	#define MSR_IA32_X2APIC_IRR4 0x824
1941	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1942	#define MSR_IA32_X2APIC_IRR5 0x825
1943	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1944	#define MSR_IA32_X2APIC_IRR6 0x826
1945	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1946	#define MSR_IA32_X2APIC_IRR7 0x827
1947	/** X2APIC MSR - Error Status Register. */
1948	#define MSR_IA32_X2APIC_ESR 0x828
1949	/** X2APIC MSR - LVT CMCI Register. */
1950	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1951	/** X2APIC MSR - Interrupt Command Register. */
1952	#define MSR_IA32_X2APIC_ICR 0x830
1953	/** X2APIC MSR - LVT Timer Register. */
1954	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1955	/** X2APIC MSR - LVT Thermal Sensor Register. */
1956	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1957	/** X2APIC MSR - LVT Performance Counter Register. */
1958	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1959	/** X2APIC MSR - LVT LINT0 Register. */
1960	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1961	/** X2APIC MSR - LVT LINT1 Register. */
1962	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1963	/** X2APIC MSR - LVT Error Register . */
1964	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1965	/** X2APIC MSR - Timer Initial Count Register. */
1966	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1967	/** X2APIC MSR - Timer Current Count Register. */
1968	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1969	/** X2APIC MSR - Timer Divide Configuration Register. */
1970	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1971	/** X2APIC MSR - Self IPI. */
1972	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1973	/** X2APIC MSR range end. */
1974	#define MSR_IA32_X2APIC_END 0x8FF
1975	/** X2APIC MSR - LVT start range. */
1976	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1977	/** X2APIC MSR - LVT end range (inclusive). */
1978	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1979
1980	/** K6 EFER - Extended Feature Enable Register. */
1981	#define MSR_K6_EFER UINT32_C(0xc0000080)
1982	/** @todo document EFER */
1983	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1984	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1985	/** Bit 8 - LME - Long mode enabled. (R/W) */
1986	#define MSR_K6_EFER_LME RT_BIT_32(8)
1987	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1988	/** Bit 10 - LMA - Long mode active. (R) */
1989	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1990	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1991	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1992	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1993	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1994	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1995	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1996	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1997	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1998	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1999	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2000	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2001	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2002	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2003	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2004
2005	/** K6 STAR - SYSCALL/RET targets. */
2006	#define MSR_K6_STAR UINT32_C(0xc0000081)
2007	/** Shift value for getting the SYSRET CS and SS value. */
2008	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2009	/** Shift value for getting the SYSCALL CS and SS value. */
2010	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2011	/** Selector mask for use after shifting. */
2012	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2013	/** The mask which give the SYSCALL EIP. */
2014	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2015	/** K6 WHCR - Write Handling Control Register. */
2016	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2017	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2018	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2019	/** K6 PSOR - Processor State Observability Register. */
2020	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2021	/** K6 PFIR - Page Flush/Invalidate Register. */
2022	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2023
2024	/** Performance counter MSRs. (AMD only) */
2025	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2026	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2027	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2028	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2029	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2030	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2031	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2032	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2033
2034	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2035	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2036	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2037	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2038	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2039	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2040	/** K8 FS.base - The 64-bit base FS register. */
2041	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2042	/** K8 GS.base - The 64-bit base GS register. */
2043	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2044	/** K8 KernelGSbase - Used with SWAPGS. */
2045	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2046	/** K8 TSC_AUX - Used with RDTSCP. */
2047	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2048	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2049	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2050	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2051	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2052	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2053	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2054	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2055	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2056
2057	/** SMM MSRs. */
2058	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2059	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2060	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2061
2062	/** North bridge config? See BIOS & Kernel dev guides for
2063	* details. */
2064	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2065
2066	/** Hypertransport interrupt pending register.
2067	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2068	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2069
2070	/** SVM Control. */
2071	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2072	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2073	* features. */
2074	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2075	/** If set, non-intercepted INIT signals are converted to \#SX
2076	* exceptions. */
2077	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2078	/** Disables A20 masking. */
2079	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2080	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2081	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2082	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2083	* clear, EFER.SVME can be written normally. */
2084	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2085
2086	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2087	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2088	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2089	* host state during world switch. */
2090	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2091
2092	/** Virtualized speculation control for AMD processors.
2093	*
2094	* Unified interface among different CPU generations.
2095	* The VMM will set any architectural MSRs based on the CPU.
2096	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2097	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2098	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2099	/** Speculative Store Bypass Disable. */
2100	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2101
2102	/** @} */
2103
2104
2105	/** @name Page Table / Directory / Directory Pointers / L4.
2106	* @{
2107	*/
2108
2109	/** Page table/directory entry as an unsigned integer. */
2110	typedef uint32_t X86PGUINT;
2111	/** Pointer to a page table/directory table entry as an unsigned integer. */
2112	typedef X86PGUINT *PX86PGUINT;
2113	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2114	typedef X86PGUINT const *PCX86PGUINT;
2115
2116	/** Number of entries in a 32-bit PT/PD. */
2117	#define X86_PG_ENTRIES 1024
2118
2119
2120	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2121	typedef uint64_t X86PGPAEUINT;
2122	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2123	typedef X86PGPAEUINT *PX86PGPAEUINT;
2124	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2125	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2126
2127	/** Number of entries in a PAE PT/PD. */
2128	#define X86_PG_PAE_ENTRIES 512
2129	/** Number of entries in a PAE PDPT. */
2130	#define X86_PG_PAE_PDPE_ENTRIES 4
2131
2132	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2133	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2134	/** Number of entries in an AMD64 PDPT.
2135	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2136	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2137
2138	/** The size of a default page. */
2139	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2140	/** The page shift of a default page. */
2141	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2142	/** The default page offset mask. */
2143	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2144	/** The default page base mask for virtual addresses. */
2145	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2146	/** The default page base mask for virtual addresses - 32bit version. */
2147	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2148
2149	/** The size of a 4KB page. */
2150	#define X86_PAGE_4K_SIZE _4K
2151	/** The page shift of a 4KB page. */
2152	#define X86_PAGE_4K_SHIFT 12
2153	/** The 4KB page offset mask. */
2154	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2155	/** The 4KB page base mask for virtual addresses. */
2156	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2157	/** The 4KB page base mask for virtual addresses - 32bit version. */
2158	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2159
2160	/** The size of a 2MB page. */
2161	#define X86_PAGE_2M_SIZE _2M
2162	/** The page shift of a 2MB page. */
2163	#define X86_PAGE_2M_SHIFT 21
2164	/** The 2MB page offset mask. */
2165	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2166	/** The 2MB page base mask for virtual addresses. */
2167	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2168	/** The 2MB page base mask for virtual addresses - 32bit version. */
2169	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2170
2171	/** The size of a 4MB page. */
2172	#define X86_PAGE_4M_SIZE _4M
2173	/** The page shift of a 4MB page. */
2174	#define X86_PAGE_4M_SHIFT 22
2175	/** The 4MB page offset mask. */
2176	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2177	/** The 4MB page base mask for virtual addresses. */
2178	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2179	/** The 4MB page base mask for virtual addresses - 32bit version. */
2180	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2181
2182	/** The size of a 1GB page. */
2183	#define X86_PAGE_1G_SIZE _1G
2184	/** The page shift of a 1GB page. */
2185	#define X86_PAGE_1G_SHIFT 30
2186	/** The 1GB page offset mask. */
2187	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2188	/** The 1GB page base mask for virtual addresses. */
2189	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2190
2191	/**
2192	* Check if the given address is canonical.
2193	*/
2194	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2195
2196	/**
2197	* Gets the page base mask given the page shift.
2198	*/
2199	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2200
2201	/**
2202	* Gets the page offset mask given the page shift.
2203	*/
2204	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2205
2206
2207	/** @name Page Table Entry
2208	* @{
2209	*/
2210	/** Bit 0 - P - Present bit. */
2211	#define X86_PTE_BIT_P 0
2212	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2213	#define X86_PTE_BIT_RW 1
2214	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2215	#define X86_PTE_BIT_US 2
2216	/** Bit 3 - PWT - Page level write thru bit. */
2217	#define X86_PTE_BIT_PWT 3
2218	/** Bit 4 - PCD - Page level cache disable bit. */
2219	#define X86_PTE_BIT_PCD 4
2220	/** Bit 5 - A - Access bit. */
2221	#define X86_PTE_BIT_A 5
2222	/** Bit 6 - D - Dirty bit. */
2223	#define X86_PTE_BIT_D 6
2224	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2225	#define X86_PTE_BIT_PAT 7
2226	/** Bit 8 - G - Global flag. */
2227	#define X86_PTE_BIT_G 8
2228	/** Bits 63 - NX - PAE/LM - No execution flag. */
2229	#define X86_PTE_PAE_BIT_NX 63
2230
2231	/** Bit 0 - P - Present bit mask. */
2232	#define X86_PTE_P RT_BIT_32(0)
2233	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2234	#define X86_PTE_RW RT_BIT_32(1)
2235	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2236	#define X86_PTE_US RT_BIT_32(2)
2237	/** Bit 3 - PWT - Page level write thru bit mask. */
2238	#define X86_PTE_PWT RT_BIT_32(3)
2239	/** Bit 4 - PCD - Page level cache disable bit mask. */
2240	#define X86_PTE_PCD RT_BIT_32(4)
2241	/** Bit 5 - A - Access bit mask. */
2242	#define X86_PTE_A RT_BIT_32(5)
2243	/** Bit 6 - D - Dirty bit mask. */
2244	#define X86_PTE_D RT_BIT_32(6)
2245	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2246	#define X86_PTE_PAT RT_BIT_32(7)
2247	/** Bit 8 - G - Global bit mask. */
2248	#define X86_PTE_G RT_BIT_32(8)
2249
2250	/** Bits 9-11 - - Available for use to system software. */
2251	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2252	/** Bits 12-31 - - Physical Page number of the next level. */
2253	#define X86_PTE_PG_MASK ( 0xfffff000 )
2254
2255	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2256	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2257	/** Bits 63 - NX - PAE/LM - No execution flag. */
2258	#define X86_PTE_PAE_NX RT_BIT_64(63)
2259	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2260	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2261	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2262	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2263	/** No bits - - LM - MBZ bits when NX is active. */
2264	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2265	/** Bits 63 - - LM - MBZ bits when no NX. */
2266	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2267
2268	/**
2269	* Page table entry.
2270	*/
2271	typedef struct X86PTEBITS
2272	{
2273	/** Flags whether(=1) or not the page is present. */
2274	uint32_t u1Present : 1;
2275	/** Read(=0) / Write(=1) flag. */
2276	uint32_t u1Write : 1;
2277	/** User(=1) / Supervisor (=0) flag. */
2278	uint32_t u1User : 1;
2279	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2280	uint32_t u1WriteThru : 1;
2281	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2282	uint32_t u1CacheDisable : 1;
2283	/** Accessed flag.
2284	* Indicates that the page have been read or written to. */
2285	uint32_t u1Accessed : 1;
2286	/** Dirty flag.
2287	* Indicates that the page has been written to. */
2288	uint32_t u1Dirty : 1;
2289	/** Reserved / If PAT enabled, bit 2 of the index. */
2290	uint32_t u1PAT : 1;
2291	/** Global flag. (Ignored in all but final level.) */
2292	uint32_t u1Global : 1;
2293	/** Available for use to system software. */
2294	uint32_t u3Available : 3;
2295	/** Physical Page number of the next level. */
2296	uint32_t u20PageNo : 20;
2297	} X86PTEBITS;
2298	#ifndef VBOX_FOR_DTRACE_LIB
2299	AssertCompileSize(X86PTEBITS, 4);
2300	#endif
2301	/** Pointer to a page table entry. */
2302	typedef X86PTEBITS *PX86PTEBITS;
2303	/** Pointer to a const page table entry. */
2304	typedef const X86PTEBITS *PCX86PTEBITS;
2305
2306	/**
2307	* Page table entry.
2308	*/
2309	typedef union X86PTE
2310	{
2311	/** Unsigned integer view */
2312	X86PGUINT u;
2313	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2314	/** Bit field view. */
2315	X86PTEBITS n;
2316	#endif
2317	/** 32-bit view. */
2318	uint32_t au32[1];
2319	/** 16-bit view. */
2320	uint16_t au16[2];
2321	/** 8-bit view. */
2322	uint8_t au8[4];
2323	} X86PTE;
2324	#ifndef VBOX_FOR_DTRACE_LIB
2325	AssertCompileSize(X86PTE, 4);
2326	#endif
2327	/** Pointer to a page table entry. */
2328	typedef X86PTE *PX86PTE;
2329	/** Pointer to a const page table entry. */
2330	typedef const X86PTE *PCX86PTE;
2331
2332
2333	/**
2334	* PAE page table entry.
2335	*/
2336	typedef struct X86PTEPAEBITS
2337	{
2338	/** Flags whether(=1) or not the page is present. */
2339	uint32_t u1Present : 1;
2340	/** Read(=0) / Write(=1) flag. */
2341	uint32_t u1Write : 1;
2342	/** User(=1) / Supervisor(=0) flag. */
2343	uint32_t u1User : 1;
2344	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2345	uint32_t u1WriteThru : 1;
2346	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2347	uint32_t u1CacheDisable : 1;
2348	/** Accessed flag.
2349	* Indicates that the page have been read or written to. */
2350	uint32_t u1Accessed : 1;
2351	/** Dirty flag.
2352	* Indicates that the page has been written to. */
2353	uint32_t u1Dirty : 1;
2354	/** Reserved / If PAT enabled, bit 2 of the index. */
2355	uint32_t u1PAT : 1;
2356	/** Global flag. (Ignored in all but final level.) */
2357	uint32_t u1Global : 1;
2358	/** Available for use to system software. */
2359	uint32_t u3Available : 3;
2360	/** Physical Page number of the next level - Low Part. Don't use this. */
2361	uint32_t u20PageNoLow : 20;
2362	/** Physical Page number of the next level - High Part. Don't use this. */
2363	uint32_t u20PageNoHigh : 20;
2364	/** MBZ bits */
2365	uint32_t u11Reserved : 11;
2366	/** No Execute flag. */
2367	uint32_t u1NoExecute : 1;
2368	} X86PTEPAEBITS;
2369	#ifndef VBOX_FOR_DTRACE_LIB
2370	AssertCompileSize(X86PTEPAEBITS, 8);
2371	#endif
2372	/** Pointer to a page table entry. */
2373	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2374	/** Pointer to a page table entry. */
2375	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2376
2377	/**
2378	* PAE Page table entry.
2379	*/
2380	typedef union X86PTEPAE
2381	{
2382	/** Unsigned integer view */
2383	X86PGPAEUINT u;
2384	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2385	/** Bit field view. */
2386	X86PTEPAEBITS n;
2387	#endif
2388	/** 32-bit view. */
2389	uint32_t au32[2];
2390	/** 16-bit view. */
2391	uint16_t au16[4];
2392	/** 8-bit view. */
2393	uint8_t au8[8];
2394	} X86PTEPAE;
2395	#ifndef VBOX_FOR_DTRACE_LIB
2396	AssertCompileSize(X86PTEPAE, 8);
2397	#endif
2398	/** Pointer to a PAE page table entry. */
2399	typedef X86PTEPAE *PX86PTEPAE;
2400	/** Pointer to a const PAE page table entry. */
2401	typedef const X86PTEPAE *PCX86PTEPAE;
2402	/** @} */
2403
2404	/**
2405	* Page table.
2406	*/
2407	typedef struct X86PT
2408	{
2409	/** PTE Array. */
2410	X86PTE a[X86_PG_ENTRIES];
2411	} X86PT;
2412	#ifndef VBOX_FOR_DTRACE_LIB
2413	AssertCompileSize(X86PT, 4096);
2414	#endif
2415	/** Pointer to a page table. */
2416	typedef X86PT *PX86PT;
2417	/** Pointer to a const page table. */
2418	typedef const X86PT *PCX86PT;
2419
2420	/** The page shift to get the PT index. */
2421	#define X86_PT_SHIFT 12
2422	/** The PT index mask (apply to a shifted page address). */
2423	#define X86_PT_MASK 0x3ff
2424
2425
2426	/**
2427	* Page directory.
2428	*/
2429	typedef struct X86PTPAE
2430	{
2431	/** PTE Array. */
2432	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2433	} X86PTPAE;
2434	#ifndef VBOX_FOR_DTRACE_LIB
2435	AssertCompileSize(X86PTPAE, 4096);
2436	#endif
2437	/** Pointer to a page table. */
2438	typedef X86PTPAE *PX86PTPAE;
2439	/** Pointer to a const page table. */
2440	typedef const X86PTPAE *PCX86PTPAE;
2441
2442	/** The page shift to get the PA PTE index. */
2443	#define X86_PT_PAE_SHIFT 12
2444	/** The PAE PT index mask (apply to a shifted page address). */
2445	#define X86_PT_PAE_MASK 0x1ff
2446
2447
2448	/** @name 4KB Page Directory Entry
2449	* @{
2450	*/
2451	/** Bit 0 - P - Present bit. */
2452	#define X86_PDE_P RT_BIT_32(0)
2453	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2454	#define X86_PDE_RW RT_BIT_32(1)
2455	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2456	#define X86_PDE_US RT_BIT_32(2)
2457	/** Bit 3 - PWT - Page level write thru bit. */
2458	#define X86_PDE_PWT RT_BIT_32(3)
2459	/** Bit 4 - PCD - Page level cache disable bit. */
2460	#define X86_PDE_PCD RT_BIT_32(4)
2461	/** Bit 5 - A - Access bit. */
2462	#define X86_PDE_A RT_BIT_32(5)
2463	/** Bit 7 - PS - Page size attribute.
2464	* Clear mean 4KB pages, set means large pages (2/4MB). */
2465	#define X86_PDE_PS RT_BIT_32(7)
2466	/** Bits 9-11 - - Available for use to system software. */
2467	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2468	/** Bits 12-31 - - Physical Page number of the next level. */
2469	#define X86_PDE_PG_MASK ( 0xfffff000 )
2470
2471	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2472	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2473	/** Bits 63 - NX - PAE/LM - No execution flag. */
2474	#define X86_PDE_PAE_NX RT_BIT_64(63)
2475	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2476	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2477	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2478	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2479	/** Bit 7 - - LM - MBZ bits when NX is active. */
2480	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2481	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2482	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2483
2484	/**
2485	* Page directory entry.
2486	*/
2487	typedef struct X86PDEBITS
2488	{
2489	/** Flags whether(=1) or not the page is present. */
2490	uint32_t u1Present : 1;
2491	/** Read(=0) / Write(=1) flag. */
2492	uint32_t u1Write : 1;
2493	/** User(=1) / Supervisor (=0) flag. */
2494	uint32_t u1User : 1;
2495	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2496	uint32_t u1WriteThru : 1;
2497	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2498	uint32_t u1CacheDisable : 1;
2499	/** Accessed flag.
2500	* Indicates that the page has been read or written to. */
2501	uint32_t u1Accessed : 1;
2502	/** Reserved / Ignored (dirty bit). */
2503	uint32_t u1Reserved0 : 1;
2504	/** Size bit if PSE is enabled - in any event it's 0. */
2505	uint32_t u1Size : 1;
2506	/** Reserved / Ignored (global bit). */
2507	uint32_t u1Reserved1 : 1;
2508	/** Available for use to system software. */
2509	uint32_t u3Available : 3;
2510	/** Physical Page number of the next level. */
2511	uint32_t u20PageNo : 20;
2512	} X86PDEBITS;
2513	#ifndef VBOX_FOR_DTRACE_LIB
2514	AssertCompileSize(X86PDEBITS, 4);
2515	#endif
2516	/** Pointer to a page directory entry. */
2517	typedef X86PDEBITS *PX86PDEBITS;
2518	/** Pointer to a const page directory entry. */
2519	typedef const X86PDEBITS *PCX86PDEBITS;
2520
2521
2522	/**
2523	* PAE page directory entry.
2524	*/
2525	typedef struct X86PDEPAEBITS
2526	{
2527	/** Flags whether(=1) or not the page is present. */
2528	uint32_t u1Present : 1;
2529	/** Read(=0) / Write(=1) flag. */
2530	uint32_t u1Write : 1;
2531	/** User(=1) / Supervisor (=0) flag. */
2532	uint32_t u1User : 1;
2533	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2534	uint32_t u1WriteThru : 1;
2535	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2536	uint32_t u1CacheDisable : 1;
2537	/** Accessed flag.
2538	* Indicates that the page has been read or written to. */
2539	uint32_t u1Accessed : 1;
2540	/** Reserved / Ignored (dirty bit). */
2541	uint32_t u1Reserved0 : 1;
2542	/** Size bit if PSE is enabled - in any event it's 0. */
2543	uint32_t u1Size : 1;
2544	/** Reserved / Ignored (global bit). / */
2545	uint32_t u1Reserved1 : 1;
2546	/** Available for use to system software. */
2547	uint32_t u3Available : 3;
2548	/** Physical Page number of the next level - Low Part. Don't use! */
2549	uint32_t u20PageNoLow : 20;
2550	/** Physical Page number of the next level - High Part. Don't use! */
2551	uint32_t u20PageNoHigh : 20;
2552	/** MBZ bits */
2553	uint32_t u11Reserved : 11;
2554	/** No Execute flag. */
2555	uint32_t u1NoExecute : 1;
2556	} X86PDEPAEBITS;
2557	#ifndef VBOX_FOR_DTRACE_LIB
2558	AssertCompileSize(X86PDEPAEBITS, 8);
2559	#endif
2560	/** Pointer to a page directory entry. */
2561	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2562	/** Pointer to a const page directory entry. */
2563	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2564
2565	/** @} */
2566
2567
2568	/** @name 2/4MB Page Directory Entry
2569	* @{
2570	*/
2571	/** Bit 0 - P - Present bit. */
2572	#define X86_PDE4M_P RT_BIT_32(0)
2573	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2574	#define X86_PDE4M_RW RT_BIT_32(1)
2575	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2576	#define X86_PDE4M_US RT_BIT_32(2)
2577	/** Bit 3 - PWT - Page level write thru bit. */
2578	#define X86_PDE4M_PWT RT_BIT_32(3)
2579	/** Bit 4 - PCD - Page level cache disable bit. */
2580	#define X86_PDE4M_PCD RT_BIT_32(4)
2581	/** Bit 5 - A - Access bit. */
2582	#define X86_PDE4M_A RT_BIT_32(5)
2583	/** Bit 6 - D - Dirty bit. */
2584	#define X86_PDE4M_D RT_BIT_32(6)
2585	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2586	#define X86_PDE4M_PS RT_BIT_32(7)
2587	/** Bit 8 - G - Global flag. */
2588	#define X86_PDE4M_G RT_BIT_32(8)
2589	/** Bits 9-11 - AVL - Available for use to system software. */
2590	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2591	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2592	#define X86_PDE4M_PAT RT_BIT_32(12)
2593	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2594	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2595	/** Bits 22-31 - - Physical Page number. */
2596	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2597	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2598	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2599	/** The number of bits to the high part of the page number. */
2600	#define X86_PDE4M_PG_HIGH_SHIFT 19
2601	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2602	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2603
2604	/** Bits 21-51 - - PAE/LM - Physical Page number.
2605	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2606	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2607	/** Bits 63 - NX - PAE/LM - No execution flag. */
2608	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2609	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2610	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2611	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2612	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2613	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2614	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2615	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2616	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2617
2618	/**
2619	* 4MB page directory entry.
2620	*/
2621	typedef struct X86PDE4MBITS
2622	{
2623	/** Flags whether(=1) or not the page is present. */
2624	uint32_t u1Present : 1;
2625	/** Read(=0) / Write(=1) flag. */
2626	uint32_t u1Write : 1;
2627	/** User(=1) / Supervisor (=0) flag. */
2628	uint32_t u1User : 1;
2629	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2630	uint32_t u1WriteThru : 1;
2631	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2632	uint32_t u1CacheDisable : 1;
2633	/** Accessed flag.
2634	* Indicates that the page have been read or written to. */
2635	uint32_t u1Accessed : 1;
2636	/** Dirty flag.
2637	* Indicates that the page has been written to. */
2638	uint32_t u1Dirty : 1;
2639	/** Page size flag - always 1 for 4MB entries. */
2640	uint32_t u1Size : 1;
2641	/** Global flag. */
2642	uint32_t u1Global : 1;
2643	/** Available for use to system software. */
2644	uint32_t u3Available : 3;
2645	/** Reserved / If PAT enabled, bit 2 of the index. */
2646	uint32_t u1PAT : 1;
2647	/** Bits 32-39 of the page number on AMD64.
2648	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2649	uint32_t u8PageNoHigh : 8;
2650	/** Reserved. */
2651	uint32_t u1Reserved : 1;
2652	/** Physical Page number of the page. */
2653	uint32_t u10PageNo : 10;
2654	} X86PDE4MBITS;
2655	#ifndef VBOX_FOR_DTRACE_LIB
2656	AssertCompileSize(X86PDE4MBITS, 4);
2657	#endif
2658	/** Pointer to a page table entry. */
2659	typedef X86PDE4MBITS *PX86PDE4MBITS;
2660	/** Pointer to a const page table entry. */
2661	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2662
2663
2664	/**
2665	* 2MB PAE page directory entry.
2666	*/
2667	typedef struct X86PDE2MPAEBITS
2668	{
2669	/** Flags whether(=1) or not the page is present. */
2670	uint32_t u1Present : 1;
2671	/** Read(=0) / Write(=1) flag. */
2672	uint32_t u1Write : 1;
2673	/** User(=1) / Supervisor(=0) flag. */
2674	uint32_t u1User : 1;
2675	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2676	uint32_t u1WriteThru : 1;
2677	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2678	uint32_t u1CacheDisable : 1;
2679	/** Accessed flag.
2680	* Indicates that the page have been read or written to. */
2681	uint32_t u1Accessed : 1;
2682	/** Dirty flag.
2683	* Indicates that the page has been written to. */
2684	uint32_t u1Dirty : 1;
2685	/** Page size flag - always 1 for 2MB entries. */
2686	uint32_t u1Size : 1;
2687	/** Global flag. */
2688	uint32_t u1Global : 1;
2689	/** Available for use to system software. */
2690	uint32_t u3Available : 3;
2691	/** Reserved / If PAT enabled, bit 2 of the index. */
2692	uint32_t u1PAT : 1;
2693	/** Reserved. */
2694	uint32_t u9Reserved : 9;
2695	/** Physical Page number of the next level - Low part. Don't use! */
2696	uint32_t u10PageNoLow : 10;
2697	/** Physical Page number of the next level - High part. Don't use! */
2698	uint32_t u20PageNoHigh : 20;
2699	/** MBZ bits */
2700	uint32_t u11Reserved : 11;
2701	/** No Execute flag. */
2702	uint32_t u1NoExecute : 1;
2703	} X86PDE2MPAEBITS;
2704	#ifndef VBOX_FOR_DTRACE_LIB
2705	AssertCompileSize(X86PDE2MPAEBITS, 8);
2706	#endif
2707	/** Pointer to a 2MB PAE page table entry. */
2708	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2709	/** Pointer to a 2MB PAE page table entry. */
2710	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2711
2712	/** @} */
2713
2714	/**
2715	* Page directory entry.
2716	*/
2717	typedef union X86PDE
2718	{
2719	/** Unsigned integer view. */
2720	X86PGUINT u;
2721	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2722	/** Normal view. */
2723	X86PDEBITS n;
2724	/** 4MB view (big). */
2725	X86PDE4MBITS b;
2726	#endif
2727	/** 8 bit unsigned integer view. */
2728	uint8_t au8[4];
2729	/** 16 bit unsigned integer view. */
2730	uint16_t au16[2];
2731	/** 32 bit unsigned integer view. */
2732	uint32_t au32[1];
2733	} X86PDE;
2734	#ifndef VBOX_FOR_DTRACE_LIB
2735	AssertCompileSize(X86PDE, 4);
2736	#endif
2737	/** Pointer to a page directory entry. */
2738	typedef X86PDE *PX86PDE;
2739	/** Pointer to a const page directory entry. */
2740	typedef const X86PDE *PCX86PDE;
2741
2742	/**
2743	* PAE page directory entry.
2744	*/
2745	typedef union X86PDEPAE
2746	{
2747	/** Unsigned integer view. */
2748	X86PGPAEUINT u;
2749	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2750	/** Normal view. */
2751	X86PDEPAEBITS n;
2752	/** 2MB page view (big). */
2753	X86PDE2MPAEBITS b;
2754	#endif
2755	/** 8 bit unsigned integer view. */
2756	uint8_t au8[8];
2757	/** 16 bit unsigned integer view. */
2758	uint16_t au16[4];
2759	/** 32 bit unsigned integer view. */
2760	uint32_t au32[2];
2761	} X86PDEPAE;
2762	#ifndef VBOX_FOR_DTRACE_LIB
2763	AssertCompileSize(X86PDEPAE, 8);
2764	#endif
2765	/** Pointer to a page directory entry. */
2766	typedef X86PDEPAE *PX86PDEPAE;
2767	/** Pointer to a const page directory entry. */
2768	typedef const X86PDEPAE *PCX86PDEPAE;
2769
2770	/**
2771	* Page directory.
2772	*/
2773	typedef struct X86PD
2774	{
2775	/** PDE Array. */
2776	X86PDE a[X86_PG_ENTRIES];
2777	} X86PD;
2778	#ifndef VBOX_FOR_DTRACE_LIB
2779	AssertCompileSize(X86PD, 4096);
2780	#endif
2781	/** Pointer to a page directory. */
2782	typedef X86PD *PX86PD;
2783	/** Pointer to a const page directory. */
2784	typedef const X86PD *PCX86PD;
2785
2786	/** The page shift to get the PD index. */
2787	#define X86_PD_SHIFT 22
2788	/** The PD index mask (apply to a shifted page address). */
2789	#define X86_PD_MASK 0x3ff
2790
2791
2792	/**
2793	* PAE page directory.
2794	*/
2795	typedef struct X86PDPAE
2796	{
2797	/** PDE Array. */
2798	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2799	} X86PDPAE;
2800	#ifndef VBOX_FOR_DTRACE_LIB
2801	AssertCompileSize(X86PDPAE, 4096);
2802	#endif
2803	/** Pointer to a PAE page directory. */
2804	typedef X86PDPAE *PX86PDPAE;
2805	/** Pointer to a const PAE page directory. */
2806	typedef const X86PDPAE *PCX86PDPAE;
2807
2808	/** The page shift to get the PAE PD index. */
2809	#define X86_PD_PAE_SHIFT 21
2810	/** The PAE PD index mask (apply to a shifted page address). */
2811	#define X86_PD_PAE_MASK 0x1ff
2812
2813
2814	/** @name Page Directory Pointer Table Entry (PAE)
2815	* @{
2816	*/
2817	/** Bit 0 - P - Present bit. */
2818	#define X86_PDPE_P RT_BIT_32(0)
2819	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2820	#define X86_PDPE_RW RT_BIT_32(1)
2821	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2822	#define X86_PDPE_US RT_BIT_32(2)
2823	/** Bit 3 - PWT - Page level write thru bit. */
2824	#define X86_PDPE_PWT RT_BIT_32(3)
2825	/** Bit 4 - PCD - Page level cache disable bit. */
2826	#define X86_PDPE_PCD RT_BIT_32(4)
2827	/** Bit 5 - A - Access bit. Long Mode only. */
2828	#define X86_PDPE_A RT_BIT_32(5)
2829	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2830	#define X86_PDPE_LM_PS RT_BIT_32(7)
2831	/** Bits 9-11 - - Available for use to system software. */
2832	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2833	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2834	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2835	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2836	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2837	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2838	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2839	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2840	#define X86_PDPE_LM_NX RT_BIT_64(63)
2841	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2842	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2843	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2844	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2845	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2846	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2847	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2848	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2849
2850
2851	/**
2852	* Page directory pointer table entry.
2853	*/
2854	typedef struct X86PDPEBITS
2855	{
2856	/** Flags whether(=1) or not the page is present. */
2857	uint32_t u1Present : 1;
2858	/** Chunk of reserved bits. */
2859	uint32_t u2Reserved : 2;
2860	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2861	uint32_t u1WriteThru : 1;
2862	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2863	uint32_t u1CacheDisable : 1;
2864	/** Chunk of reserved bits. */
2865	uint32_t u4Reserved : 4;
2866	/** Available for use to system software. */
2867	uint32_t u3Available : 3;
2868	/** Physical Page number of the next level - Low Part. Don't use! */
2869	uint32_t u20PageNoLow : 20;
2870	/** Physical Page number of the next level - High Part. Don't use! */
2871	uint32_t u20PageNoHigh : 20;
2872	/** MBZ bits */
2873	uint32_t u12Reserved : 12;
2874	} X86PDPEBITS;
2875	#ifndef VBOX_FOR_DTRACE_LIB
2876	AssertCompileSize(X86PDPEBITS, 8);
2877	#endif
2878	/** Pointer to a page directory pointer table entry. */
2879	typedef X86PDPEBITS *PX86PTPEBITS;
2880	/** Pointer to a const page directory pointer table entry. */
2881	typedef const X86PDPEBITS *PCX86PTPEBITS;
2882
2883	/**
2884	* Page directory pointer table entry. AMD64 version
2885	*/
2886	typedef struct X86PDPEAMD64BITS
2887	{
2888	/** Flags whether(=1) or not the page is present. */
2889	uint32_t u1Present : 1;
2890	/** Read(=0) / Write(=1) flag. */
2891	uint32_t u1Write : 1;
2892	/** User(=1) / Supervisor (=0) flag. */
2893	uint32_t u1User : 1;
2894	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2895	uint32_t u1WriteThru : 1;
2896	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2897	uint32_t u1CacheDisable : 1;
2898	/** Accessed flag.
2899	* Indicates that the page have been read or written to. */
2900	uint32_t u1Accessed : 1;
2901	/** Chunk of reserved bits. */
2902	uint32_t u3Reserved : 3;
2903	/** Available for use to system software. */
2904	uint32_t u3Available : 3;
2905	/** Physical Page number of the next level - Low Part. Don't use! */
2906	uint32_t u20PageNoLow : 20;
2907	/** Physical Page number of the next level - High Part. Don't use! */
2908	uint32_t u20PageNoHigh : 20;
2909	/** MBZ bits */
2910	uint32_t u11Reserved : 11;
2911	/** No Execute flag. */
2912	uint32_t u1NoExecute : 1;
2913	} X86PDPEAMD64BITS;
2914	#ifndef VBOX_FOR_DTRACE_LIB
2915	AssertCompileSize(X86PDPEAMD64BITS, 8);
2916	#endif
2917	/** Pointer to a page directory pointer table entry. */
2918	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2919	/** Pointer to a const page directory pointer table entry. */
2920	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2921
2922	/**
2923	* Page directory pointer table entry for 1GB page. (AMD64 only)
2924	*/
2925	typedef struct X86PDPE1GB
2926	{
2927	/** 0: Flags whether(=1) or not the page is present. */
2928	uint32_t u1Present : 1;
2929	/** 1: Read(=0) / Write(=1) flag. */
2930	uint32_t u1Write : 1;
2931	/** 2: User(=1) / Supervisor (=0) flag. */
2932	uint32_t u1User : 1;
2933	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2934	uint32_t u1WriteThru : 1;
2935	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2936	uint32_t u1CacheDisable : 1;
2937	/** 5: Accessed flag.
2938	* Indicates that the page have been read or written to. */
2939	uint32_t u1Accessed : 1;
2940	/** 6: Dirty flag for 1GB pages. */
2941	uint32_t u1Dirty : 1;
2942	/** 7: Indicates 1GB page if set. */
2943	uint32_t u1Size : 1;
2944	/** 8: Global 1GB page. */
2945	uint32_t u1Global: 1;
2946	/** 9-11: Available for use to system software. */
2947	uint32_t u3Available : 3;
2948	/** 12: PAT bit for 1GB page. */
2949	uint32_t u1PAT : 1;
2950	/** 13-29: MBZ bits. */
2951	uint32_t u17Reserved : 17;
2952	/** 30-31: Physical page number - Low Part. Don't use! */
2953	uint32_t u2PageNoLow : 2;
2954	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2955	uint32_t u20PageNoHigh : 20;
2956	/** 52-62: MBZ bits */
2957	uint32_t u11Reserved : 11;
2958	/** 63: No Execute flag. */
2959	uint32_t u1NoExecute : 1;
2960	} X86PDPE1GB;
2961	#ifndef VBOX_FOR_DTRACE_LIB
2962	AssertCompileSize(X86PDPE1GB, 8);
2963	#endif
2964	/** Pointer to a page directory pointer table entry for a 1GB page. */
2965	typedef X86PDPE1GB *PX86PDPE1GB;
2966	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2967	typedef const X86PDPE1GB *PCX86PDPE1GB;
2968
2969	/**
2970	* Page directory pointer table entry.
2971	*/
2972	typedef union X86PDPE
2973	{
2974	/** Unsigned integer view. */
2975	X86PGPAEUINT u;
2976	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2977	/** Normal view. */
2978	X86PDPEBITS n;
2979	/** AMD64 view. */
2980	X86PDPEAMD64BITS lm;
2981	/** AMD64 big view. */
2982	X86PDPE1GB b;
2983	#endif
2984	/** 8 bit unsigned integer view. */
2985	uint8_t au8[8];
2986	/** 16 bit unsigned integer view. */
2987	uint16_t au16[4];
2988	/** 32 bit unsigned integer view. */
2989	uint32_t au32[2];
2990	} X86PDPE;
2991	#ifndef VBOX_FOR_DTRACE_LIB
2992	AssertCompileSize(X86PDPE, 8);
2993	#endif
2994	/** Pointer to a page directory pointer table entry. */
2995	typedef X86PDPE *PX86PDPE;
2996	/** Pointer to a const page directory pointer table entry. */
2997	typedef const X86PDPE *PCX86PDPE;
2998
2999
3000	/**
3001	* Page directory pointer table.
3002	*/
3003	typedef struct X86PDPT
3004	{
3005	/** PDE Array. */
3006	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3007	} X86PDPT;
3008	#ifndef VBOX_FOR_DTRACE_LIB
3009	AssertCompileSize(X86PDPT, 4096);
3010	#endif
3011	/** Pointer to a page directory pointer table. */
3012	typedef X86PDPT *PX86PDPT;
3013	/** Pointer to a const page directory pointer table. */
3014	typedef const X86PDPT *PCX86PDPT;
3015
3016	/** The page shift to get the PDPT index. */
3017	#define X86_PDPT_SHIFT 30
3018	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3019	#define X86_PDPT_MASK_PAE 0x3
3020	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3021	#define X86_PDPT_MASK_AMD64 0x1ff
3022
3023	/** @} */
3024
3025
3026	/** @name Page Map Level-4 Entry (Long Mode PAE)
3027	* @{
3028	*/
3029	/** Bit 0 - P - Present bit. */
3030	#define X86_PML4E_P RT_BIT_32(0)
3031	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3032	#define X86_PML4E_RW RT_BIT_32(1)
3033	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3034	#define X86_PML4E_US RT_BIT_32(2)
3035	/** Bit 3 - PWT - Page level write thru bit. */
3036	#define X86_PML4E_PWT RT_BIT_32(3)
3037	/** Bit 4 - PCD - Page level cache disable bit. */
3038	#define X86_PML4E_PCD RT_BIT_32(4)
3039	/** Bit 5 - A - Access bit. */
3040	#define X86_PML4E_A RT_BIT_32(5)
3041	/** Bits 9-11 - - Available for use to system software. */
3042	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3043	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3044	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3045	/** Bits 8, 7 - - MBZ bits when NX is active. */
3046	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3047	/** Bits 63, 7 - - MBZ bits when no NX. */
3048	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3049	/** Bits 63 - NX - PAE - No execution flag. */
3050	#define X86_PML4E_NX RT_BIT_64(63)
3051
3052	/**
3053	* Page Map Level-4 Entry
3054	*/
3055	typedef struct X86PML4EBITS
3056	{
3057	/** Flags whether(=1) or not the page is present. */
3058	uint32_t u1Present : 1;
3059	/** Read(=0) / Write(=1) flag. */
3060	uint32_t u1Write : 1;
3061	/** User(=1) / Supervisor (=0) flag. */
3062	uint32_t u1User : 1;
3063	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3064	uint32_t u1WriteThru : 1;
3065	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3066	uint32_t u1CacheDisable : 1;
3067	/** Accessed flag.
3068	* Indicates that the page have been read or written to. */
3069	uint32_t u1Accessed : 1;
3070	/** Chunk of reserved bits. */
3071	uint32_t u3Reserved : 3;
3072	/** Available for use to system software. */
3073	uint32_t u3Available : 3;
3074	/** Physical Page number of the next level - Low Part. Don't use! */
3075	uint32_t u20PageNoLow : 20;
3076	/** Physical Page number of the next level - High Part. Don't use! */
3077	uint32_t u20PageNoHigh : 20;
3078	/** MBZ bits */
3079	uint32_t u11Reserved : 11;
3080	/** No Execute flag. */
3081	uint32_t u1NoExecute : 1;
3082	} X86PML4EBITS;
3083	#ifndef VBOX_FOR_DTRACE_LIB
3084	AssertCompileSize(X86PML4EBITS, 8);
3085	#endif
3086	/** Pointer to a page map level-4 entry. */
3087	typedef X86PML4EBITS *PX86PML4EBITS;
3088	/** Pointer to a const page map level-4 entry. */
3089	typedef const X86PML4EBITS *PCX86PML4EBITS;
3090
3091	/**
3092	* Page Map Level-4 Entry.
3093	*/
3094	typedef union X86PML4E
3095	{
3096	/** Unsigned integer view. */
3097	X86PGPAEUINT u;
3098	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3099	/** Normal view. */
3100	X86PML4EBITS n;
3101	#endif
3102	/** 8 bit unsigned integer view. */
3103	uint8_t au8[8];
3104	/** 16 bit unsigned integer view. */
3105	uint16_t au16[4];
3106	/** 32 bit unsigned integer view. */
3107	uint32_t au32[2];
3108	} X86PML4E;
3109	#ifndef VBOX_FOR_DTRACE_LIB
3110	AssertCompileSize(X86PML4E, 8);
3111	#endif
3112	/** Pointer to a page map level-4 entry. */
3113	typedef X86PML4E *PX86PML4E;
3114	/** Pointer to a const page map level-4 entry. */
3115	typedef const X86PML4E *PCX86PML4E;
3116
3117
3118	/**
3119	* Page Map Level-4.
3120	*/
3121	typedef struct X86PML4
3122	{
3123	/** PDE Array. */
3124	X86PML4E a[X86_PG_PAE_ENTRIES];
3125	} X86PML4;
3126	#ifndef VBOX_FOR_DTRACE_LIB
3127	AssertCompileSize(X86PML4, 4096);
3128	#endif
3129	/** Pointer to a page map level-4. */
3130	typedef X86PML4 *PX86PML4;
3131	/** Pointer to a const page map level-4. */
3132	typedef const X86PML4 *PCX86PML4;
3133
3134	/** The page shift to get the PML4 index. */
3135	#define X86_PML4_SHIFT 39
3136	/** The PML4 index mask (apply to a shifted page address). */
3137	#define X86_PML4_MASK 0x1ff
3138
3139	/** @} */
3140
3141	/** @} */
3142
3143	/**
3144	* Intel PCID invalidation types.
3145	*/
3146	/** Individual address invalidation. */
3147	#define X86_INVPCID_TYPE_INDV_ADDR 0
3148	/** Single-context invalidation. */
3149	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3150	/** All-context including globals invalidation. */
3151	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3152	/** All-context excluding globals invalidation. */
3153	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3154	/** The maximum valid invalidation type value. */
3155	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3156
3157
3158	/** @name Special FPU integer values.
3159	* @{ */
3160	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3161	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3162	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3163	/** @} */
3164
3165	/**
3166	* 32-bit protected mode FSTENV image.
3167	*/
3168	typedef struct X86FSTENV32P
3169	{
3170	uint16_t FCW; /*< 0x00 /
3171	uint16_t padding1; /*< 0x02 /
3172	uint16_t FSW; /*< 0x04 /
3173	uint16_t padding2; /*< 0x06 /
3174	uint16_t FTW; /*< 0x08 /
3175	uint16_t padding3; /*< 0x0a /
3176	uint32_t FPUIP; /*< 0x0c /
3177	uint16_t FPUCS; /*< 0x10 /
3178	uint16_t FOP; /*< 0x12 /
3179	uint32_t FPUDP; /*< 0x14 /
3180	uint16_t FPUDS; /*< 0x18 /
3181	uint16_t padding4; /*< 0x1a /
3182	} X86FSTENV32P;
3183	#ifndef VBOX_FOR_DTRACE_LIB
3184	AssertCompileSize(X86FSTENV32P, 0x1c);
3185	#endif
3186	/** Pointer to a 32-bit protected mode FSTENV image. */
3187	typedef X86FSTENV32P *PX86FSTENV32P;
3188	/** Pointer to a const 32-bit protected mode FSTENV image. */
3189	typedef X86FSTENV32P const *PCX86FSTENV32P;
3190
3191
3192	/**
3193	* 80-bit MMX/FPU register type.
3194	*/
3195	typedef struct X86FPUMMX
3196	{
3197	uint8_t reg[10];
3198	} X86FPUMMX;
3199	#ifndef VBOX_FOR_DTRACE_LIB
3200	AssertCompileSize(X86FPUMMX, 10);
3201	#endif
3202	/** Pointer to a 80-bit MMX/FPU register type. */
3203	typedef X86FPUMMX *PX86FPUMMX;
3204	/** Pointer to a const 80-bit MMX/FPU register type. */
3205	typedef const X86FPUMMX *PCX86FPUMMX;
3206
3207	/** FPU (x87) register. */
3208	typedef union X86FPUREG
3209	{
3210	/** MMX view. */
3211	uint64_t mmx;
3212	/** FPU view - todo. */
3213	X86FPUMMX fpu;
3214	/** Extended precision floating point view. */
3215	RTFLOAT80U r80;
3216	/** Extended precision floating point view v2 */
3217	RTFLOAT80U2 r80Ex;
3218	/** 8-bit view. */
3219	uint8_t au8[16];
3220	/** 16-bit view. */
3221	uint16_t au16[8];
3222	/** 32-bit view. */
3223	uint32_t au32[4];
3224	/** 64-bit view. */
3225	uint64_t au64[2];
3226	/** 128-bit view. (yeah, very helpful) */
3227	uint128_t au128[1];
3228	} X86FPUREG;
3229	#ifndef VBOX_FOR_DTRACE_LIB
3230	AssertCompileSize(X86FPUREG, 16);
3231	#endif
3232	/** Pointer to a FPU register. */
3233	typedef X86FPUREG *PX86FPUREG;
3234	/** Pointer to a const FPU register. */
3235	typedef X86FPUREG const *PCX86FPUREG;
3236
3237	/** FPU (x87) register - v2 with correct size. */
3238	#pragma pack(1)
3239	typedef union X86FPUREG2
3240	{
3241	/** MMX view. */
3242	uint64_t mmx;
3243	/** FPU view - todo. */
3244	X86FPUMMX fpu;
3245	/** Extended precision floating point view. */
3246	RTFLOAT80U r80;
3247	/** 8-bit view. */
3248	uint8_t au8[10];
3249	/** 16-bit view. */
3250	uint16_t au16[5];
3251	/** 32-bit view. */
3252	uint32_t au32[2];
3253	/** 64-bit view. */
3254	uint64_t au64[1];
3255	} X86FPUREG2;
3256	#pragma pack()
3257	#ifndef VBOX_FOR_DTRACE_LIB
3258	AssertCompileSize(X86FPUREG2, 10);
3259	#endif
3260	/** Pointer to a FPU register - v2. */
3261	typedef X86FPUREG2 *PX86FPUREG2;
3262	/** Pointer to a const FPU register - v2. */
3263	typedef X86FPUREG2 const *PCX86FPUREG2;
3264
3265	/**
3266	* XMM register union.
3267	*/
3268	typedef union X86XMMREG
3269	{
3270	/** XMM Register view. */
3271	uint128_t xmm;
3272	/** 8-bit view. */
3273	uint8_t au8[16];
3274	/** 16-bit view. */
3275	uint16_t au16[8];
3276	/** 32-bit view. */
3277	uint32_t au32[4];
3278	/** 64-bit view. */
3279	uint64_t au64[2];
3280	/** Signed 8-bit view. */
3281	int8_t ai8[16];
3282	/** Signed 16-bit view. */
3283	int16_t ai16[8];
3284	/** Signed 32-bit view. */
3285	int32_t ai32[4];
3286	/** Signed 64-bit view. */
3287	int64_t ai64[2];
3288	/** 128-bit view. (yeah, very helpful) */
3289	uint128_t au128[1];
3290	/** Single precision floating point view. */
3291	RTFLOAT32U ar32[4];
3292	/** Double precision floating point view. */
3293	RTFLOAT64U ar64[2];
3294	#ifndef VBOX_FOR_DTRACE_LIB
3295	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3296	RTUINT128U uXmm;
3297	#endif
3298	} X86XMMREG;
3299	#ifndef VBOX_FOR_DTRACE_LIB
3300	AssertCompileSize(X86XMMREG, 16);
3301	#endif
3302	/** Pointer to an XMM register state. */
3303	typedef X86XMMREG *PX86XMMREG;
3304	/** Pointer to a const XMM register state. */
3305	typedef X86XMMREG const *PCX86XMMREG;
3306
3307	/**
3308	* YMM register union.
3309	*/
3310	typedef union X86YMMREG
3311	{
3312	/** YMM register view. */
3313	RTUINT256U ymm;
3314	/** 8-bit view. */
3315	uint8_t au8[32];
3316	/** 16-bit view. */
3317	uint16_t au16[16];
3318	/** 32-bit view. */
3319	uint32_t au32[8];
3320	/** 64-bit view. */
3321	uint64_t au64[4];
3322	/** 128-bit view. (yeah, very helpful) */
3323	uint128_t au128[2];
3324	/** Single precision floating point view. */
3325	RTFLOAT32U ar32[8];
3326	/** Double precision floating point view. */
3327	RTFLOAT64U ar64[4];
3328	/** XMM sub register view. */
3329	X86XMMREG aXmm[2];
3330	} X86YMMREG;
3331	#ifndef VBOX_FOR_DTRACE_LIB
3332	AssertCompileSize(X86YMMREG, 32);
3333	#endif
3334	/** Pointer to an YMM register state. */
3335	typedef X86YMMREG *PX86YMMREG;
3336	/** Pointer to a const YMM register state. */
3337	typedef X86YMMREG const *PCX86YMMREG;
3338
3339	/**
3340	* ZMM register union.
3341	*/
3342	typedef union X86ZMMREG
3343	{
3344	/** 8-bit view. */
3345	uint8_t au8[64];
3346	/** 16-bit view. */
3347	uint16_t au16[32];
3348	/** 32-bit view. */
3349	uint32_t au32[16];
3350	/** 64-bit view. */
3351	uint64_t au64[8];
3352	/** 128-bit view. (yeah, very helpful) */
3353	uint128_t au128[4];
3354	/** Single precision floating point view. */
3355	RTFLOAT32U ar32[16];
3356	/** Double precision floating point view. */
3357	RTFLOAT64U ar64[8];
3358	/** XMM sub register view. */
3359	X86XMMREG aXmm[4];
3360	/** YMM sub register view. */
3361	X86YMMREG aYmm[2];
3362	} X86ZMMREG;
3363	#ifndef VBOX_FOR_DTRACE_LIB
3364	AssertCompileSize(X86ZMMREG, 64);
3365	#endif
3366	/** Pointer to an ZMM register state. */
3367	typedef X86ZMMREG *PX86ZMMREG;
3368	/** Pointer to a const ZMM register state. */
3369	typedef X86ZMMREG const *PCX86ZMMREG;
3370
3371
3372	/**
3373	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3374	*/
3375	#pragma pack(1)
3376	typedef struct X86FPUSTATE
3377	{
3378	/** 0x00 - Control word. */
3379	uint16_t FCW;
3380	/** 0x02 - Alignment word */
3381	uint16_t Dummy1;
3382	/** 0x04 - Status word. */
3383	uint16_t FSW;
3384	/** 0x06 - Alignment word */
3385	uint16_t Dummy2;
3386	/** 0x08 - Tag word */
3387	uint16_t FTW;
3388	/** 0x0a - Alignment word */
3389	uint16_t Dummy3;
3390
3391	/** 0x0c - Instruction pointer. */
3392	uint32_t FPUIP;
3393	/** 0x10 - Code selector. */
3394	uint16_t CS;
3395	/** 0x12 - Opcode. */
3396	uint16_t FOP;
3397	/** 0x14 - Data pointer. */
3398	uint32_t FPUOO;
3399	/** 0x18 - FOS. */
3400	uint16_t FPUOS;
3401	/** 0x0a - Alignment word */
3402	uint16_t Dummy4;
3403	/** 0x1c - FPU register. */
3404	X86FPUREG2 regs[8];
3405	} X86FPUSTATE;
3406	#pragma pack()
3407	AssertCompileSize(X86FPUSTATE, 108);
3408	/** Pointer to a FPU state. */
3409	typedef X86FPUSTATE *PX86FPUSTATE;
3410	/** Pointer to a const FPU state. */
3411	typedef const X86FPUSTATE *PCX86FPUSTATE;
3412
3413	/**
3414	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3415	*/
3416	#pragma pack(1)
3417	typedef struct X86FXSTATE
3418	{
3419	/** 0x00 - Control word. */
3420	uint16_t FCW;
3421	/** 0x02 - Status word. */
3422	uint16_t FSW;
3423	/** 0x04 - Tag word. (The upper byte is always zero.) */
3424	uint16_t FTW;
3425	/** 0x06 - Opcode. */
3426	uint16_t FOP;
3427	/** 0x08 - Instruction pointer. */
3428	uint32_t FPUIP;
3429	/** 0x0c - Code selector. */
3430	uint16_t CS;
3431	uint16_t Rsrvd1;
3432	/** 0x10 - Data pointer. */
3433	uint32_t FPUDP;
3434	/** 0x14 - Data segment */
3435	uint16_t DS;
3436	/** 0x16 */
3437	uint16_t Rsrvd2;
3438	/** 0x18 */
3439	uint32_t MXCSR;
3440	/** 0x1c */
3441	uint32_t MXCSR_MASK;
3442	/** 0x20 - FPU registers. */
3443	X86FPUREG aRegs[8];
3444	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3445	X86XMMREG aXMM[16];
3446	/* - offset 416 - */
3447	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3448	/* - offset 464 - Software usable reserved bits. */
3449	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3450	} X86FXSTATE;
3451	#pragma pack()
3452	/** Pointer to a FPU Extended state. */
3453	typedef X86FXSTATE *PX86FXSTATE;
3454	/** Pointer to a const FPU Extended state. */
3455	typedef const X86FXSTATE *PCX86FXSTATE;
3456
3457	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3458	* magic. Don't forget to update x86.mac if you change this! */
3459	#define X86_OFF_FXSTATE_RSVD 0x1d0
3460	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3461	* forget to update x86.mac if you change this!
3462	* @todo r=bird: This has nothing what-so-ever to do here.... */
3463	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3464	#ifndef VBOX_FOR_DTRACE_LIB
3465	AssertCompileSize(X86FXSTATE, 512);
3466	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3467	#endif
3468
3469	/** @name FPU status word flags.
3470	* @{ */
3471	/** Exception Flag: Invalid operation. */
3472	#define X86_FSW_IE RT_BIT_32(0)
3473	#define X86_FSW_IE_BIT 0
3474	/** Exception Flag: Denormalized operand. */
3475	#define X86_FSW_DE RT_BIT_32(1)
3476	#define X86_FSW_DE_BIT 1
3477	/** Exception Flag: Zero divide. */
3478	#define X86_FSW_ZE RT_BIT_32(2)
3479	#define X86_FSW_ZE_BIT 2
3480	/** Exception Flag: Overflow. */
3481	#define X86_FSW_OE RT_BIT_32(3)
3482	#define X86_FSW_OE_BIT 3
3483	/** Exception Flag: Underflow. */
3484	#define X86_FSW_UE RT_BIT_32(4)
3485	#define X86_FSW_UE_BIT 4
3486	/** Exception Flag: Precision. */
3487	#define X86_FSW_PE RT_BIT_32(5)
3488	#define X86_FSW_PE_BIT 5
3489	/** Stack fault. */
3490	#define X86_FSW_SF RT_BIT_32(6)
3491	#define X86_FSW_SF_BIT 6
3492	/** Error summary status. */
3493	#define X86_FSW_ES RT_BIT_32(7)
3494	#define X86_FSW_ES_BIT 7
3495	/** Mask of exceptions flags, excluding the summary bit. */
3496	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3497	/** Mask of exceptions flags, including the summary bit. */
3498	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3499	/** Condition code 0. */
3500	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3501	#define X86_FSW_C0_BIT 8
3502	/** Condition code 1. */
3503	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3504	#define X86_FSW_C1_BIT 9
3505	/** Condition code 2. */
3506	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3507	#define X86_FSW_C2_BIT 10
3508	/** Top of the stack mask. */
3509	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3510	/** TOP shift value. */
3511	#define X86_FSW_TOP_SHIFT 11
3512	/** Mask for getting TOP value after shifting it right. */
3513	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3514	/** Get the TOP value. */
3515	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3516	/** Get the TOP value offsetted by a_iSt (0-7). */
3517	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3518	/** Condition code 3. */
3519	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3520	#define X86_FSW_C3_BIT 14
3521	/** Mask of exceptions flags, including the summary bit. */
3522	#define X86_FSW_C_MASK UINT16_C(0x4700)
3523	/** FPU busy. */
3524	#define X86_FSW_B RT_BIT_32(15)
3525	/** For use with FPREM and FPREM1. */
3526	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3527	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3528	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3529	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3530	/** For use with FPREM and FPREM1. */
3531	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3532	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3533	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3534	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3535	/** @} */
3536
3537
3538	/** @name FPU control word flags.
3539	* @{ */
3540	/** Exception Mask: Invalid operation. */
3541	#define X86_FCW_IM RT_BIT_32(0)
3542	#define X86_FCW_IM_BIT 0
3543	/** Exception Mask: Denormalized operand. */
3544	#define X86_FCW_DM RT_BIT_32(1)
3545	#define X86_FCW_DM_BIT 1
3546	/** Exception Mask: Zero divide. */
3547	#define X86_FCW_ZM RT_BIT_32(2)
3548	#define X86_FCW_ZM_BIT 2
3549	/** Exception Mask: Overflow. */
3550	#define X86_FCW_OM RT_BIT_32(3)
3551	#define X86_FCW_OM_BIT 3
3552	/** Exception Mask: Underflow. */
3553	#define X86_FCW_UM RT_BIT_32(4)
3554	#define X86_FCW_UM_BIT 4
3555	/** Exception Mask: Precision. */
3556	#define X86_FCW_PM RT_BIT_32(5)
3557	#define X86_FCW_PM_BIT 5
3558	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3559	* @remarks This includes reserved bit 6. */
3560	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3561	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3562	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3563	/** Precision control mask. */
3564	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3565	/** Precision control shift. */
3566	#define X86_FCW_PC_SHIFT 8
3567	/** Precision control: 24-bit. */
3568	#define X86_FCW_PC_24 UINT16_C(0x0000)
3569	/** Precision control: Reserved. */
3570	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3571	/** Precision control: 53-bit. */
3572	#define X86_FCW_PC_53 UINT16_C(0x0200)
3573	/** Precision control: 64-bit. */
3574	#define X86_FCW_PC_64 UINT16_C(0x0300)
3575	/** Rounding control mask. */
3576	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3577	/** Rounding control shift. */
3578	#define X86_FCW_RC_SHIFT 10
3579	/** Rounding control: To nearest. */
3580	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3581	/** Rounding control: Down. */
3582	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3583	/** Rounding control: Up. */
3584	#define X86_FCW_RC_UP UINT16_C(0x0800)
3585	/** Rounding control: Towards zero. */
3586	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3587	/** Infinity control mask - obsolete, 8087 & 287 only. */
3588	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3589	/** Infinity control: Affine - positive infinity is distictly different from
3590	* negative infinity.
3591	* @note 8087, 287 only */
3592	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3593	/** Infinity control: Projective - positive and negative infinity are the
3594	* same (sign ignored).
3595	* @note 8087, 287 only */
3596	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3597	/** Bits which should be zero, apparently. */
3598	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3599	/** @} */
3600
3601	/** @name SSE MXCSR
3602	* @{ */
3603	/** Exception Flag: Invalid operation. */
3604	#define X86_MXCSR_IE RT_BIT_32(0)
3605	/** Exception Flag: Denormalized operand. */
3606	#define X86_MXCSR_DE RT_BIT_32(1)
3607	/** Exception Flag: Zero divide. */
3608	#define X86_MXCSR_ZE RT_BIT_32(2)
3609	/** Exception Flag: Overflow. */
3610	#define X86_MXCSR_OE RT_BIT_32(3)
3611	/** Exception Flag: Underflow. */
3612	#define X86_MXCSR_UE RT_BIT_32(4)
3613	/** Exception Flag: Precision. */
3614	#define X86_MXCSR_PE RT_BIT_32(5)
3615	/** Exception Flags: mask */
3616	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3617
3618	/** Denormals are zero. */
3619	#define X86_MXCSR_DAZ RT_BIT_32(6)
3620
3621	/** Exception Mask: Invalid operation. */
3622	#define X86_MXCSR_IM RT_BIT_32(7)
3623	/** Exception Mask: Denormalized operand. */
3624	#define X86_MXCSR_DM RT_BIT_32(8)
3625	/** Exception Mask: Zero divide. */
3626	#define X86_MXCSR_ZM RT_BIT_32(9)
3627	/** Exception Mask: Overflow. */
3628	#define X86_MXCSR_OM RT_BIT_32(10)
3629	/** Exception Mask: Underflow. */
3630	#define X86_MXCSR_UM RT_BIT_32(11)
3631	/** Exception Mask: Precision. */
3632	#define X86_MXCSR_PM RT_BIT_32(12)
3633	/** Exception Mask: mask. */
3634	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3635	/** Exception Mask: shift. */
3636	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3637
3638	/** Rounding control mask. */
3639	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3640	/** Rounding control shift. */
3641	#define X86_MXCSR_RC_SHIFT 13
3642	/** Rounding control: To nearest. */
3643	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3644	/** Rounding control: Down. */
3645	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3646	/** Rounding control: Up. */
3647	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3648	/** Rounding control: Towards zero. */
3649	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3650
3651	/** Flush-to-zero for masked underflow. */
3652	#define X86_MXCSR_FZ RT_BIT_32(15)
3653
3654	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3655	#define X86_MXCSR_MM RT_BIT_32(17)
3656	/** Bits which should be zero, apparently. */
3657	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3658	/** @} */
3659
3660	/**
3661	* XSAVE header.
3662	*/
3663	typedef struct X86XSAVEHDR
3664	{
3665	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3666	uint64_t bmXState;
3667	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3668	uint64_t bmXComp;
3669	/** Reserved for furture extensions, probably MBZ. */
3670	uint64_t au64Reserved[6];
3671	} X86XSAVEHDR;
3672	#ifndef VBOX_FOR_DTRACE_LIB
3673	AssertCompileSize(X86XSAVEHDR, 64);
3674	#endif
3675	/** Pointer to an XSAVE header. */
3676	typedef X86XSAVEHDR *PX86XSAVEHDR;
3677	/** Pointer to a const XSAVE header. */
3678	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3679
3680
3681	/**
3682	* The high 128-bit YMM register state (XSAVE_C_YMM).
3683	* (The lower 128-bits being in X86FXSTATE.)
3684	*/
3685	typedef struct X86XSAVEYMMHI
3686	{
3687	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3688	X86XMMREG aYmmHi[16];
3689	} X86XSAVEYMMHI;
3690	#ifndef VBOX_FOR_DTRACE_LIB
3691	AssertCompileSize(X86XSAVEYMMHI, 256);
3692	#endif
3693	/** Pointer to a high 128-bit YMM register state. */
3694	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3695	/** Pointer to a const high 128-bit YMM register state. */
3696	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3697
3698	/**
3699	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3700	*/
3701	typedef struct X86XSAVEBNDREGS
3702	{
3703	/** Array of registers (BND0...BND3). */
3704	struct
3705	{
3706	/** Lower bound. */
3707	uint64_t uLowerBound;
3708	/** Upper bound. */
3709	uint64_t uUpperBound;
3710	} aRegs[4];
3711	} X86XSAVEBNDREGS;
3712	#ifndef VBOX_FOR_DTRACE_LIB
3713	AssertCompileSize(X86XSAVEBNDREGS, 64);
3714	#endif
3715	/** Pointer to a MPX bound register state. */
3716	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3717	/** Pointer to a const MPX bound register state. */
3718	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3719
3720	/**
3721	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3722	*/
3723	typedef struct X86XSAVEBNDCFG
3724	{
3725	uint64_t fConfig;
3726	uint64_t fStatus;
3727	} X86XSAVEBNDCFG;
3728	#ifndef VBOX_FOR_DTRACE_LIB
3729	AssertCompileSize(X86XSAVEBNDCFG, 16);
3730	#endif
3731	/** Pointer to a MPX bound config and status register state. */
3732	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3733	/** Pointer to a const MPX bound config and status register state. */
3734	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3735
3736	/**
3737	* AVX-512 opmask state (XSAVE_C_OPMASK).
3738	*/
3739	typedef struct X86XSAVEOPMASK
3740	{
3741	/** The K0..K7 values. */
3742	uint64_t aKRegs[8];
3743	} X86XSAVEOPMASK;
3744	#ifndef VBOX_FOR_DTRACE_LIB
3745	AssertCompileSize(X86XSAVEOPMASK, 64);
3746	#endif
3747	/** Pointer to a AVX-512 opmask state. */
3748	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3749	/** Pointer to a const AVX-512 opmask state. */
3750	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3751
3752	/**
3753	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3754	*/
3755	typedef struct X86XSAVEZMMHI256
3756	{
3757	/** Upper 256-bits of ZMM0-15. */
3758	X86YMMREG aHi256Regs[16];
3759	} X86XSAVEZMMHI256;
3760	#ifndef VBOX_FOR_DTRACE_LIB
3761	AssertCompileSize(X86XSAVEZMMHI256, 512);
3762	#endif
3763	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3764	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3765	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3766	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3767
3768	/**
3769	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3770	*/
3771	typedef struct X86XSAVEZMM16HI
3772	{
3773	/** ZMM16 thru ZMM31. */
3774	X86ZMMREG aRegs[16];
3775	} X86XSAVEZMM16HI;
3776	#ifndef VBOX_FOR_DTRACE_LIB
3777	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3778	#endif
3779	/** Pointer to a state comprising ZMM16-32. */
3780	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3781	/** Pointer to a const state comprising ZMM16-32. */
3782	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3783
3784	/**
3785	* AMD Light weight profiling state (XSAVE_C_LWP).
3786	*
3787	* We probably won't play with this as AMD seems to be dropping from their "zen"
3788	* processor micro architecture.
3789	*/
3790	typedef struct X86XSAVELWP
3791	{
3792	/** Details when needed. */
3793	uint64_t auLater[128/8];
3794	} X86XSAVELWP;
3795	#ifndef VBOX_FOR_DTRACE_LIB
3796	AssertCompileSize(X86XSAVELWP, 128);
3797	#endif
3798
3799
3800	/**
3801	* x86 FPU/SSE/AVX/XXXX state.
3802	*
3803	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3804	* changes to this structure.
3805	*/
3806	typedef struct X86XSAVEAREA
3807	{
3808	/** The x87 and SSE region (or legacy region if you like). */
3809	X86FXSTATE x87;
3810	/** The XSAVE header. */
3811	X86XSAVEHDR Hdr;
3812	/** Beyond the header, there isn't really a fixed layout, but we can
3813	generally assume the YMM (AVX) register extensions are present and
3814	follows immediately. */
3815	union
3816	{
3817	/** The high 128-bit AVX registers for easy access by IEM.
3818	* @note This ASSUMES they will always be here... */
3819	X86XSAVEYMMHI YmmHi;
3820
3821	/** This is a typical layout on intel CPUs (good for debuggers). */
3822	struct
3823	{
3824	X86XSAVEYMMHI YmmHi;
3825	X86XSAVEBNDREGS BndRegs;
3826	X86XSAVEBNDCFG BndCfg;
3827	uint8_t abFudgeToMatchDocs[0xB0];
3828	X86XSAVEOPMASK Opmask;
3829	X86XSAVEZMMHI256 ZmmHi256;
3830	X86XSAVEZMM16HI Zmm16Hi;
3831	} Intel;
3832
3833	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3834	struct
3835	{
3836	X86XSAVEYMMHI YmmHi;
3837	X86XSAVELWP Lwp;
3838	} AmdBd;
3839
3840	/** To enbling static deployments that have a reasonable chance of working for
3841	* the next 3-6 CPU generations without running short on space, we allocate a
3842	* lot of extra space here, making the structure a round 8KB in size. This
3843	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3844	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3845	uint8_t ab[8192 - 512 - 64];
3846	} u;
3847	} X86XSAVEAREA;
3848	#ifndef VBOX_FOR_DTRACE_LIB
3849	AssertCompileSize(X86XSAVEAREA, 8192);
3850	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3851	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3852	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3853	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3854	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3855	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3856	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3857	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3858	#endif
3859	/** Pointer to a XSAVE area. */
3860	typedef X86XSAVEAREA *PX86XSAVEAREA;
3861	/** Pointer to a const XSAVE area. */
3862	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3863
3864
3865	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3866	* @{ */
3867	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3868	#define XSAVE_C_X87_BIT 0
3869	/** Bit 0 - x87 - Legacy FPU state. */
3870	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3871	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3872	#define XSAVE_C_SSE_BIT 1
3873	/** Bit 1 - SSE - 128-bit SSE state. */
3874	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3875	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3876	#define XSAVE_C_YMM_BIT 2
3877	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3878	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3879	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3880	#define XSAVE_C_BNDREGS_BIT 3
3881	/** Bit 3 - BNDREGS - MPX bound register state. */
3882	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3883	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3884	#define XSAVE_C_BNDCSR_BIT 4
3885	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3886	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3887	/** Bit 5 - Opmask - opmask state (bit number). */
3888	#define XSAVE_C_OPMASK_BIT 5
3889	/** Bit 5 - Opmask - opmask state. */
3890	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3891	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3892	#define XSAVE_C_ZMM_HI256_BIT 6
3893	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3894	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3895	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3896	#define XSAVE_C_ZMM_16HI_BIT 7
3897	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3898	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3899	/** Bit 9 - PKRU - Protection-key state (bit number). */
3900	#define XSAVE_C_PKRU_BIT 9
3901	/** Bit 9 - PKRU - Protection-key state. */
3902	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3903	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3904	#define XSAVE_C_LWP_BIT 62
3905	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3906	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3907	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3908	#define XSAVE_C_X_BIT 63
3909	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3910	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3911	/** @} */
3912
3913
3914
3915	/** @name Selector Descriptor
3916	* @{
3917	*/
3918
3919	#ifndef VBOX_FOR_DTRACE_LIB
3920	/**
3921	* Descriptor attributes (as seen by VT-x).
3922	*/
3923	typedef struct X86DESCATTRBITS
3924	{
3925	/** 00 - Segment Type. */
3926	unsigned u4Type : 4;
3927	/** 04 - Descriptor Type. System(=0) or code/data selector */
3928	unsigned u1DescType : 1;
3929	/** 05 - Descriptor Privilege level. */
3930	unsigned u2Dpl : 2;
3931	/** 07 - Flags selector present(=1) or not. */
3932	unsigned u1Present : 1;
3933	/** 08 - Segment limit 16-19. */
3934	unsigned u4LimitHigh : 4;
3935	/** 0c - Available for system software. */
3936	unsigned u1Available : 1;
3937	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3938	unsigned u1Long : 1;
3939	/** 0e - This flags meaning depends on the segment type. Try make sense out
3940	* of the intel manual yourself. */
3941	unsigned u1DefBig : 1;
3942	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3943	* clear byte. */
3944	unsigned u1Granularity : 1;
3945	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3946	unsigned u1Unusable : 1;
3947	} X86DESCATTRBITS;
3948	#endif /* !VBOX_FOR_DTRACE_LIB */
3949
3950	/** @name X86DESCATTR masks
3951	* @{ */
3952	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3953	#define X86DESCATTR_DT UINT32_C(0x00000010)
3954	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3955	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3956	#define X86DESCATTR_P UINT32_C(0x00000080)
3957	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3958	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3959	#define X86DESCATTR_L UINT32_C(0x00002000)
3960	#define X86DESCATTR_D UINT32_C(0x00004000)
3961	#define X86DESCATTR_G UINT32_C(0x00008000)
3962	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3963	/** @} */
3964
3965	#pragma pack(1)
3966	typedef union X86DESCATTR
3967	{
3968	/** Unsigned integer view. */
3969	uint32_t u;
3970	#ifndef VBOX_FOR_DTRACE_LIB
3971	/** Normal view. */
3972	X86DESCATTRBITS n;
3973	#endif
3974	} X86DESCATTR;
3975	#pragma pack()
3976	/** Pointer to descriptor attributes. */
3977	typedef X86DESCATTR *PX86DESCATTR;
3978	/** Pointer to const descriptor attributes. */
3979	typedef const X86DESCATTR *PCX86DESCATTR;
3980
3981	#ifndef VBOX_FOR_DTRACE_LIB
3982
3983	/**
3984	* Generic descriptor table entry
3985	*/
3986	#pragma pack(1)
3987	typedef struct X86DESCGENERIC
3988	{
3989	/** 00 - Limit - Low word. */
3990	unsigned u16LimitLow : 16;
3991	/** 10 - Base address - low word.
3992	* Don't try set this to 24 because MSC is doing stupid things then. */
3993	unsigned u16BaseLow : 16;
3994	/** 20 - Base address - first 8 bits of high word. */
3995	unsigned u8BaseHigh1 : 8;
3996	/** 28 - Segment Type. */
3997	unsigned u4Type : 4;
3998	/** 2c - Descriptor Type. System(=0) or code/data selector */
3999	unsigned u1DescType : 1;
4000	/** 2d - Descriptor Privilege level. */
4001	unsigned u2Dpl : 2;
4002	/** 2f - Flags selector present(=1) or not. */
4003	unsigned u1Present : 1;
4004	/** 30 - Segment limit 16-19. */
4005	unsigned u4LimitHigh : 4;
4006	/** 34 - Available for system software. */
4007	unsigned u1Available : 1;
4008	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4009	unsigned u1Long : 1;
4010	/** 36 - This flags meaning depends on the segment type. Try make sense out
4011	* of the intel manual yourself. */
4012	unsigned u1DefBig : 1;
4013	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4014	* clear byte. */
4015	unsigned u1Granularity : 1;
4016	/** 38 - Base address - highest 8 bits. */
4017	unsigned u8BaseHigh2 : 8;
4018	} X86DESCGENERIC;
4019	#pragma pack()
4020	/** Pointer to a generic descriptor entry. */
4021	typedef X86DESCGENERIC *PX86DESCGENERIC;
4022	/** Pointer to a const generic descriptor entry. */
4023	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4024
4025	/** @name Bit offsets of X86DESCGENERIC members.
4026	* @{*/
4027	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4028	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4029	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4030	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4031	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4032	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4033	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4034	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4035	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4036	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4037	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4038	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4039	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4040	/** @} */
4041
4042
4043	/** @name LAR mask
4044	* @{ */
4045	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
4046	#define X86LAR_F_DT UINT16_C( 0x1000)
4047	#define X86LAR_F_DPL UINT16_C( 0x6000)
4048	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4049	#define X86LAR_F_P UINT16_C( 0x8000)
4050	#define X86LAR_F_AVL UINT32_C(0x00100000)
4051	#define X86LAR_F_L UINT32_C(0x00200000)
4052	#define X86LAR_F_D UINT32_C(0x00400000)
4053	#define X86LAR_F_G UINT32_C(0x00800000)
4054	/** @} */
4055
4056
4057	/**
4058	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4059	*/
4060	typedef struct X86DESCGATE
4061	{
4062	/** 00 - Target code segment offset - Low word.
4063	* Ignored if task-gate. */
4064	unsigned u16OffsetLow : 16;
4065	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4066	* TSS selector if task-gate. */
4067	unsigned u16Sel : 16;
4068	/** 20 - Number of parameters for a call-gate.
4069	* Ignored if interrupt-, trap- or task-gate. */
4070	unsigned u5ParmCount : 5;
4071	/** 25 - Reserved / ignored. */
4072	unsigned u3Reserved : 3;
4073	/** 28 - Segment Type. */
4074	unsigned u4Type : 4;
4075	/** 2c - Descriptor Type (0 = system). */
4076	unsigned u1DescType : 1;
4077	/** 2d - Descriptor Privilege level. */
4078	unsigned u2Dpl : 2;
4079	/** 2f - Flags selector present(=1) or not. */
4080	unsigned u1Present : 1;
4081	/** 30 - Target code segment offset - High word.
4082	* Ignored if task-gate. */
4083	unsigned u16OffsetHigh : 16;
4084	} X86DESCGATE;
4085	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4086	typedef X86DESCGATE *PX86DESCGATE;
4087	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4088	typedef const X86DESCGATE *PCX86DESCGATE;
4089
4090	#endif /* VBOX_FOR_DTRACE_LIB */
4091
4092	/**
4093	* Descriptor table entry.
4094	*/
4095	#pragma pack(1)
4096	typedef union X86DESC
4097	{
4098	#ifndef VBOX_FOR_DTRACE_LIB
4099	/** Generic descriptor view. */
4100	X86DESCGENERIC Gen;
4101	/** Gate descriptor view. */
4102	X86DESCGATE Gate;
4103	#endif
4104
4105	/** 8 bit unsigned integer view. */
4106	uint8_t au8[8];
4107	/** 16 bit unsigned integer view. */
4108	uint16_t au16[4];
4109	/** 32 bit unsigned integer view. */
4110	uint32_t au32[2];
4111	/** 64 bit unsigned integer view. */
4112	uint64_t au64[1];
4113	/** Unsigned integer view. */
4114	uint64_t u;
4115	} X86DESC;
4116	#ifndef VBOX_FOR_DTRACE_LIB
4117	AssertCompileSize(X86DESC, 8);
4118	#endif
4119	#pragma pack()
4120	/** Pointer to descriptor table entry. */
4121	typedef X86DESC *PX86DESC;
4122	/** Pointer to const descriptor table entry. */
4123	typedef const X86DESC *PCX86DESC;
4124
4125	/** @def X86DESC_BASE
4126	* Return the base address of a descriptor.
4127	*/
4128	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4129	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4130	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4131	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4132
4133	/** @def X86DESC_LIMIT
4134	* Return the limit of a descriptor.
4135	*/
4136	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4137	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4138	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4139
4140	/** @def X86DESC_LIMIT_G
4141	* Return the limit of a descriptor with the granularity bit taken into account.
4142	* @returns Selector limit (uint32_t).
4143	* @param a_pDesc Pointer to the descriptor.
4144	*/
4145	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4146	( (a_pDesc)->Gen.u1Granularity \
4147	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4148	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4149	)
4150
4151	/** @def X86DESC_GET_HID_ATTR
4152	* Get the descriptor attributes for the hidden register.
4153	*/
4154	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4155	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4156
4157	#ifndef VBOX_FOR_DTRACE_LIB
4158
4159	/**
4160	* 64 bits generic descriptor table entry
4161	* Note: most of these bits have no meaning in long mode.
4162	*/
4163	#pragma pack(1)
4164	typedef struct X86DESC64GENERIC
4165	{
4166	/** Limit - Low word - IGNORED. */
4167	uint32_t u16LimitLow : 16;
4168	/** Base address - low word. - IGNORED
4169	* Don't try set this to 24 because MSC is doing stupid things then. */
4170	uint32_t u16BaseLow : 16;
4171	/** Base address - first 8 bits of high word. - IGNORED */
4172	uint32_t u8BaseHigh1 : 8;
4173	/** Segment Type. */
4174	uint32_t u4Type : 4;
4175	/** Descriptor Type. System(=0) or code/data selector */
4176	uint32_t u1DescType : 1;
4177	/** Descriptor Privilege level. */
4178	uint32_t u2Dpl : 2;
4179	/** Flags selector present(=1) or not. */
4180	uint32_t u1Present : 1;
4181	/** Segment limit 16-19. - IGNORED */
4182	uint32_t u4LimitHigh : 4;
4183	/** Available for system software. - IGNORED */
4184	uint32_t u1Available : 1;
4185	/** Long mode flag. */
4186	uint32_t u1Long : 1;
4187	/** This flags meaning depends on the segment type. Try make sense out
4188	* of the intel manual yourself. */
4189	uint32_t u1DefBig : 1;
4190	/** Granularity of the limit. If set 4KB granularity is used, if
4191	* clear byte. - IGNORED */
4192	uint32_t u1Granularity : 1;
4193	/** Base address - highest 8 bits. - IGNORED */
4194	uint32_t u8BaseHigh2 : 8;
4195	/** Base address - bits 63-32. */
4196	uint32_t u32BaseHigh3 : 32;
4197	uint32_t u8Reserved : 8;
4198	uint32_t u5Zeros : 5;
4199	uint32_t u19Reserved : 19;
4200	} X86DESC64GENERIC;
4201	#pragma pack()
4202	/** Pointer to a generic descriptor entry. */
4203	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4204	/** Pointer to a const generic descriptor entry. */
4205	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4206
4207	/**
4208	* System descriptor table entry (64 bits)
4209	*
4210	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4211	*/
4212	#pragma pack(1)
4213	typedef struct X86DESC64SYSTEM
4214	{
4215	/** Limit - Low word. */
4216	uint32_t u16LimitLow : 16;
4217	/** Base address - low word.
4218	* Don't try set this to 24 because MSC is doing stupid things then. */
4219	uint32_t u16BaseLow : 16;
4220	/** Base address - first 8 bits of high word. */
4221	uint32_t u8BaseHigh1 : 8;
4222	/** Segment Type. */
4223	uint32_t u4Type : 4;
4224	/** Descriptor Type. System(=0) or code/data selector */
4225	uint32_t u1DescType : 1;
4226	/** Descriptor Privilege level. */
4227	uint32_t u2Dpl : 2;
4228	/** Flags selector present(=1) or not. */
4229	uint32_t u1Present : 1;
4230	/** Segment limit 16-19. */
4231	uint32_t u4LimitHigh : 4;
4232	/** Available for system software. */
4233	uint32_t u1Available : 1;
4234	/** Reserved - 0. */
4235	uint32_t u1Reserved : 1;
4236	/** This flags meaning depends on the segment type. Try make sense out
4237	* of the intel manual yourself. */
4238	uint32_t u1DefBig : 1;
4239	/** Granularity of the limit. If set 4KB granularity is used, if
4240	* clear byte. */
4241	uint32_t u1Granularity : 1;
4242	/** Base address - bits 31-24. */
4243	uint32_t u8BaseHigh2 : 8;
4244	/** Base address - bits 63-32. */
4245	uint32_t u32BaseHigh3 : 32;
4246	uint32_t u8Reserved : 8;
4247	uint32_t u5Zeros : 5;
4248	uint32_t u19Reserved : 19;
4249	} X86DESC64SYSTEM;
4250	#pragma pack()
4251	/** Pointer to a system descriptor entry. */
4252	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4253	/** Pointer to a const system descriptor entry. */
4254	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4255
4256	/**
4257	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4258	*/
4259	typedef struct X86DESC64GATE
4260	{
4261	/** Target code segment offset - Low word. */
4262	uint32_t u16OffsetLow : 16;
4263	/** Target code segment selector. */
4264	uint32_t u16Sel : 16;
4265	/** Interrupt stack table for interrupt- and trap-gates.
4266	* Ignored by call-gates. */
4267	uint32_t u3IST : 3;
4268	/** Reserved / ignored. */
4269	uint32_t u5Reserved : 5;
4270	/** Segment Type. */
4271	uint32_t u4Type : 4;
4272	/** Descriptor Type (0 = system). */
4273	uint32_t u1DescType : 1;
4274	/** Descriptor Privilege level. */
4275	uint32_t u2Dpl : 2;
4276	/** Flags selector present(=1) or not. */
4277	uint32_t u1Present : 1;
4278	/** Target code segment offset - High word.
4279	* Ignored if task-gate. */
4280	uint32_t u16OffsetHigh : 16;
4281	/** Target code segment offset - Top dword.
4282	* Ignored if task-gate. */
4283	uint32_t u32OffsetTop : 32;
4284	/** Reserved / ignored / must be zero.
4285	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4286	uint32_t u32Reserved : 32;
4287	} X86DESC64GATE;
4288	AssertCompileSize(X86DESC64GATE, 16);
4289	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4290	typedef X86DESC64GATE *PX86DESC64GATE;
4291	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4292	typedef const X86DESC64GATE *PCX86DESC64GATE;
4293
4294	#endif /* VBOX_FOR_DTRACE_LIB */
4295
4296	/**
4297	* Descriptor table entry.
4298	*/
4299	#pragma pack(1)
4300	typedef union X86DESC64
4301	{
4302	#ifndef VBOX_FOR_DTRACE_LIB
4303	/** Generic descriptor view. */
4304	X86DESC64GENERIC Gen;
4305	/** System descriptor view. */
4306	X86DESC64SYSTEM System;
4307	/** Gate descriptor view. */
4308	X86DESC64GATE Gate;
4309	#endif
4310
4311	/** 8 bit unsigned integer view. */
4312	uint8_t au8[16];
4313	/** 16 bit unsigned integer view. */
4314	uint16_t au16[8];
4315	/** 32 bit unsigned integer view. */
4316	uint32_t au32[4];
4317	/** 64 bit unsigned integer view. */
4318	uint64_t au64[2];
4319	} X86DESC64;
4320	#ifndef VBOX_FOR_DTRACE_LIB
4321	AssertCompileSize(X86DESC64, 16);
4322	#endif
4323	#pragma pack()
4324	/** Pointer to descriptor table entry. */
4325	typedef X86DESC64 *PX86DESC64;
4326	/** Pointer to const descriptor table entry. */
4327	typedef const X86DESC64 *PCX86DESC64;
4328
4329	/** @def X86DESC64_BASE
4330	* Return the base of a 64-bit descriptor.
4331	*/
4332	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4333	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4334	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4335	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4336	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4337
4338
4339
4340	/** @name Host system descriptor table entry - Use with care!
4341	* @{ */
4342	/** Host system descriptor table entry. */
4343	#if HC_ARCH_BITS == 64
4344	typedef X86DESC64 X86DESCHC;
4345	#else
4346	typedef X86DESC X86DESCHC;
4347	#endif
4348	/** Pointer to a host system descriptor table entry. */
4349	#if HC_ARCH_BITS == 64
4350	typedef PX86DESC64 PX86DESCHC;
4351	#else
4352	typedef PX86DESC PX86DESCHC;
4353	#endif
4354	/** Pointer to a const host system descriptor table entry. */
4355	#if HC_ARCH_BITS == 64
4356	typedef PCX86DESC64 PCX86DESCHC;
4357	#else
4358	typedef PCX86DESC PCX86DESCHC;
4359	#endif
4360	/** @} */
4361
4362
4363	/** @name Selector Descriptor Types.
4364	* @{
4365	*/
4366
4367	/** @name Non-System Selector Types.
4368	* @{ */
4369	/** Code(=set)/Data(=clear) bit. */
4370	#define X86_SEL_TYPE_CODE 8
4371	/** Memory(=set)/System(=clear) bit. */
4372	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4373	/** Accessed bit. */
4374	#define X86_SEL_TYPE_ACCESSED 1
4375	/** Expand down bit (for data selectors only). */
4376	#define X86_SEL_TYPE_DOWN 4
4377	/** Conforming bit (for code selectors only). */
4378	#define X86_SEL_TYPE_CONF 4
4379	/** Write bit (for data selectors only). */
4380	#define X86_SEL_TYPE_WRITE 2
4381	/** Read bit (for code selectors only). */
4382	#define X86_SEL_TYPE_READ 2
4383	/** The bit number of the code segment read bit (relative to u4Type). */
4384	#define X86_SEL_TYPE_READ_BIT 1
4385
4386	/** Read only selector type. */
4387	#define X86_SEL_TYPE_RO 0
4388	/** Accessed read only selector type. */
4389	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4390	/** Read write selector type. */
4391	#define X86_SEL_TYPE_RW 2
4392	/** Accessed read write selector type. */
4393	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4394	/** Expand down read only selector type. */
4395	#define X86_SEL_TYPE_RO_DOWN 4
4396	/** Accessed expand down read only selector type. */
4397	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4398	/** Expand down read write selector type. */
4399	#define X86_SEL_TYPE_RW_DOWN 6
4400	/** Accessed expand down read write selector type. */
4401	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4402	/** Execute only selector type. */
4403	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4404	/** Accessed execute only selector type. */
4405	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4406	/** Execute and read selector type. */
4407	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4408	/** Accessed execute and read selector type. */
4409	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4410	/** Conforming execute only selector type. */
4411	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4412	/** Accessed Conforming execute only selector type. */
4413	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4414	/** Conforming execute and write selector type. */
4415	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4416	/** Accessed Conforming execute and write selector type. */
4417	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4418	/** @} */
4419
4420
4421	/** @name System Selector Types.
4422	* @{ */
4423	/** The TSS busy bit mask. */
4424	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4425
4426	/** Undefined system selector type. */
4427	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4428	/** 286 TSS selector. */
4429	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4430	/** LDT selector. */
4431	#define X86_SEL_TYPE_SYS_LDT 2
4432	/** 286 TSS selector - Busy. */
4433	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4434	/** 286 Callgate selector. */
4435	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4436	/** Taskgate selector. */
4437	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4438	/** 286 Interrupt gate selector. */
4439	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4440	/** 286 Trapgate selector. */
4441	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4442	/** Undefined system selector. */
4443	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4444	/** 386 TSS selector. */
4445	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4446	/** Undefined system selector. */
4447	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4448	/** 386 TSS selector - Busy. */
4449	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4450	/** 386 Callgate selector. */
4451	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4452	/** Undefined system selector. */
4453	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4454	/** 386 Interruptgate selector. */
4455	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4456	/** 386 Trapgate selector. */
4457	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4458	/** @} */
4459
4460	/** @name AMD64 System Selector Types.
4461	* @{ */
4462	/** LDT selector. */
4463	#define AMD64_SEL_TYPE_SYS_LDT 2
4464	/** TSS selector - Busy. */
4465	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4466	/** TSS selector - Busy. */
4467	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4468	/** Callgate selector. */
4469	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4470	/** Interruptgate selector. */
4471	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4472	/** Trapgate selector. */
4473	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4474	/** @} */
4475
4476	/** @} */
4477
4478
4479	/** @name Descriptor Table Entry Flag Masks.
4480	* These are for the 2nd 32-bit word of a descriptor.
4481	* @{ */
4482	/** Bits 8-11 - TYPE - Descriptor type mask. */
4483	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4484	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4485	#define X86_DESC_S RT_BIT_32(12)
4486	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4487	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4488	/** Bit 15 - P - Present. */
4489	#define X86_DESC_P RT_BIT_32(15)
4490	/** Bit 20 - AVL - Available for system software. */
4491	#define X86_DESC_AVL RT_BIT_32(20)
4492	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4493	#define X86_DESC_DB RT_BIT_32(22)
4494	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4495	* used, if clear byte. */
4496	#define X86_DESC_G RT_BIT_32(23)
4497	/** @} */
4498
4499	/** @} */
4500
4501
4502	/** @name Task Segments.
4503	* @{
4504	*/
4505
4506	/**
4507	* The minimum TSS descriptor limit for 286 tasks.
4508	*/
4509	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4510
4511	/**
4512	* The minimum TSS descriptor segment limit for 386 tasks.
4513	*/
4514	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4515
4516	/**
4517	* 16-bit Task Segment (TSS).
4518	*/
4519	#pragma pack(1)
4520	typedef struct X86TSS16
4521	{
4522	/** Back link to previous task. (static) */
4523	RTSEL selPrev;
4524	/** Ring-0 stack pointer. (static) */
4525	uint16_t sp0;
4526	/** Ring-0 stack segment. (static) */
4527	RTSEL ss0;
4528	/** Ring-1 stack pointer. (static) */
4529	uint16_t sp1;
4530	/** Ring-1 stack segment. (static) */
4531	RTSEL ss1;
4532	/** Ring-2 stack pointer. (static) */
4533	uint16_t sp2;
4534	/** Ring-2 stack segment. (static) */
4535	RTSEL ss2;
4536	/** IP before task switch. */
4537	uint16_t ip;
4538	/** FLAGS before task switch. */
4539	uint16_t flags;
4540	/** AX before task switch. */
4541	uint16_t ax;
4542	/** CX before task switch. */
4543	uint16_t cx;
4544	/** DX before task switch. */
4545	uint16_t dx;
4546	/** BX before task switch. */
4547	uint16_t bx;
4548	/** SP before task switch. */
4549	uint16_t sp;
4550	/** BP before task switch. */
4551	uint16_t bp;
4552	/** SI before task switch. */
4553	uint16_t si;
4554	/** DI before task switch. */
4555	uint16_t di;
4556	/** ES before task switch. */
4557	RTSEL es;
4558	/** CS before task switch. */
4559	RTSEL cs;
4560	/** SS before task switch. */
4561	RTSEL ss;
4562	/** DS before task switch. */
4563	RTSEL ds;
4564	/** LDTR before task switch. */
4565	RTSEL selLdt;
4566	} X86TSS16;
4567	#ifndef VBOX_FOR_DTRACE_LIB
4568	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4569	#endif
4570	#pragma pack()
4571	/** Pointer to a 16-bit task segment. */
4572	typedef X86TSS16 *PX86TSS16;
4573	/** Pointer to a const 16-bit task segment. */
4574	typedef const X86TSS16 *PCX86TSS16;
4575
4576
4577	/**
4578	* 32-bit Task Segment (TSS).
4579	*/
4580	#pragma pack(1)
4581	typedef struct X86TSS32
4582	{
4583	/** Back link to previous task. (static) */
4584	RTSEL selPrev;
4585	uint16_t padding1;
4586	/** Ring-0 stack pointer. (static) */
4587	uint32_t esp0;
4588	/** Ring-0 stack segment. (static) */
4589	RTSEL ss0;
4590	uint16_t padding_ss0;
4591	/** Ring-1 stack pointer. (static) */
4592	uint32_t esp1;
4593	/** Ring-1 stack segment. (static) */
4594	RTSEL ss1;
4595	uint16_t padding_ss1;
4596	/** Ring-2 stack pointer. (static) */
4597	uint32_t esp2;
4598	/** Ring-2 stack segment. (static) */
4599	RTSEL ss2;
4600	uint16_t padding_ss2;
4601	/** Page directory for the task. (static) */
4602	uint32_t cr3;
4603	/** EIP before task switch. */
4604	uint32_t eip;
4605	/** EFLAGS before task switch. */
4606	uint32_t eflags;
4607	/** EAX before task switch. */
4608	uint32_t eax;
4609	/** ECX before task switch. */
4610	uint32_t ecx;
4611	/** EDX before task switch. */
4612	uint32_t edx;
4613	/** EBX before task switch. */
4614	uint32_t ebx;
4615	/** ESP before task switch. */
4616	uint32_t esp;
4617	/** EBP before task switch. */
4618	uint32_t ebp;
4619	/** ESI before task switch. */
4620	uint32_t esi;
4621	/** EDI before task switch. */
4622	uint32_t edi;
4623	/** ES before task switch. */
4624	RTSEL es;
4625	uint16_t padding_es;
4626	/** CS before task switch. */
4627	RTSEL cs;
4628	uint16_t padding_cs;
4629	/** SS before task switch. */
4630	RTSEL ss;
4631	uint16_t padding_ss;
4632	/** DS before task switch. */
4633	RTSEL ds;
4634	uint16_t padding_ds;
4635	/** FS before task switch. */
4636	RTSEL fs;
4637	uint16_t padding_fs;
4638	/** GS before task switch. */
4639	RTSEL gs;
4640	uint16_t padding_gs;
4641	/** LDTR before task switch. */
4642	RTSEL selLdt;
4643	uint16_t padding_ldt;
4644	/** Debug trap flag */
4645	uint16_t fDebugTrap;
4646	/** Offset relative to the TSS of the start of the I/O Bitmap
4647	* and the end of the interrupt redirection bitmap. */
4648	uint16_t offIoBitmap;
4649	} X86TSS32;
4650	#pragma pack()
4651	/** Pointer to task segment. */
4652	typedef X86TSS32 *PX86TSS32;
4653	/** Pointer to const task segment. */
4654	typedef const X86TSS32 *PCX86TSS32;
4655	#ifndef VBOX_FOR_DTRACE_LIB
4656	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4657	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4658	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4659	#endif
4660
4661	/**
4662	* 64-bit Task segment.
4663	*/
4664	#pragma pack(1)
4665	typedef struct X86TSS64
4666	{
4667	/** Reserved. */
4668	uint32_t u32Reserved;
4669	/** Ring-0 stack pointer. (static) */
4670	uint64_t rsp0;
4671	/** Ring-1 stack pointer. (static) */
4672	uint64_t rsp1;
4673	/** Ring-2 stack pointer. (static) */
4674	uint64_t rsp2;
4675	/** Reserved. */
4676	uint32_t u32Reserved2[2];
4677	/* IST */
4678	uint64_t ist1;
4679	uint64_t ist2;
4680	uint64_t ist3;
4681	uint64_t ist4;
4682	uint64_t ist5;
4683	uint64_t ist6;
4684	uint64_t ist7;
4685	/* Reserved. */
4686	uint16_t u16Reserved[5];
4687	/** Offset relative to the TSS of the start of the I/O Bitmap
4688	* and the end of the interrupt redirection bitmap. */
4689	uint16_t offIoBitmap;
4690	} X86TSS64;
4691	#pragma pack()
4692	/** Pointer to a 64-bit task segment. */
4693	typedef X86TSS64 *PX86TSS64;
4694	/** Pointer to a const 64-bit task segment. */
4695	typedef const X86TSS64 *PCX86TSS64;
4696	#ifndef VBOX_FOR_DTRACE_LIB
4697	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4698	#endif
4699
4700	/** @} */
4701
4702
4703	/** @name Selectors.
4704	* @{
4705	*/
4706
4707	/**
4708	* The shift used to convert a selector from and to index an index (C).
4709	*/
4710	#define X86_SEL_SHIFT 3
4711
4712	/**
4713	* The mask used to mask off the table indicator and RPL of an selector.
4714	*/
4715	#define X86_SEL_MASK 0xfff8U
4716
4717	/**
4718	* The mask used to mask off the RPL of an selector.
4719	* This is suitable for checking for NULL selectors.
4720	*/
4721	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4722
4723	/**
4724	* The bit indicating that a selector is in the LDT and not in the GDT.
4725	*/
4726	#define X86_SEL_LDT 0x0004U
4727
4728	/**
4729	* The bit mask for getting the RPL of a selector.
4730	*/
4731	#define X86_SEL_RPL 0x0003U
4732
4733	/**
4734	* The mask covering both RPL and LDT.
4735	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4736	* checks.
4737	*/
4738	#define X86_SEL_RPL_LDT 0x0007U
4739
4740	/** @} */
4741
4742
4743	/**
4744	* x86 Exceptions/Faults/Traps.
4745	*/
4746	typedef enum X86XCPT
4747	{
4748	/** \#DE - Divide error. */
4749	X86_XCPT_DE = 0x00,
4750	/** \#DB - Debug event (single step, DRx, ..) */
4751	X86_XCPT_DB = 0x01,
4752	/** NMI - Non-Maskable Interrupt */
4753	X86_XCPT_NMI = 0x02,
4754	/** \#BP - Breakpoint (INT3). */
4755	X86_XCPT_BP = 0x03,
4756	/** \#OF - Overflow (INTO). */
4757	X86_XCPT_OF = 0x04,
4758	/** \#BR - Bound range exceeded (BOUND). */
4759	X86_XCPT_BR = 0x05,
4760	/** \#UD - Undefined opcode. */
4761	X86_XCPT_UD = 0x06,
4762	/** \#NM - Device not available (math coprocessor device). */
4763	X86_XCPT_NM = 0x07,
4764	/** \#DF - Double fault. */
4765	X86_XCPT_DF = 0x08,
4766	/** ??? - Coprocessor segment overrun (obsolete). */
4767	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4768	/** \#TS - Taskswitch (TSS). */
4769	X86_XCPT_TS = 0x0a,
4770	/** \#NP - Segment no present. */
4771	X86_XCPT_NP = 0x0b,
4772	/** \#SS - Stack segment fault. */
4773	X86_XCPT_SS = 0x0c,
4774	/** \#GP - General protection fault. */
4775	X86_XCPT_GP = 0x0d,
4776	/** \#PF - Page fault. */
4777	X86_XCPT_PF = 0x0e,
4778	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4779	/** \#MF - Math fault (FPU). */
4780	X86_XCPT_MF = 0x10,
4781	/** \#AC - Alignment check. */
4782	X86_XCPT_AC = 0x11,
4783	/** \#MC - Machine check. */
4784	X86_XCPT_MC = 0x12,
4785	/** \#XF - SIMD Floating-Point Exception. */
4786	X86_XCPT_XF = 0x13,
4787	/** \#VE - Virtualization Exception (Intel only). */
4788	X86_XCPT_VE = 0x14,
4789	/** \#CP - Control Protection Exception. */
4790	X86_XCPT_CP = 0x15,
4791	/** \#VC - VMM Communication Exception (AMD only). */
4792	X86_XCPT_VC = 0x1d,
4793	/** \#SX - Security Exception (AMD only). */
4794	X86_XCPT_SX = 0x1e
4795	} X86XCPT;
4796	/** Pointer to a x86 exception code. */
4797	typedef X86XCPT *PX86XCPT;
4798	/** Pointer to a const x86 exception code. */
4799	typedef const X86XCPT *PCX86XCPT;
4800	/** The last valid (currently reserved) exception value. */
4801	#define X86_XCPT_LAST 0x1f
4802
4803
4804	/** @name Trap Error Codes
4805	* @{
4806	*/
4807	/** External indicator. */
4808	#define X86_TRAP_ERR_EXTERNAL 1
4809	/** IDT indicator. */
4810	#define X86_TRAP_ERR_IDT 2
4811	/** Descriptor table indicator - If set LDT, if clear GDT. */
4812	#define X86_TRAP_ERR_TI 4
4813	/** Mask for getting the selector. */
4814	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4815	/** Shift for getting the selector table index (C type index). */
4816	#define X86_TRAP_ERR_SEL_SHIFT 3
4817	/** @} */
4818
4819
4820	/** @name \#PF Trap Error Codes
4821	* @{
4822	*/
4823	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4824	#define X86_TRAP_PF_P RT_BIT_32(0)
4825	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4826	#define X86_TRAP_PF_RW RT_BIT_32(1)
4827	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4828	#define X86_TRAP_PF_US RT_BIT_32(2)
4829	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4830	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4831	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4832	#define X86_TRAP_PF_ID RT_BIT_32(4)
4833	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4834	#define X86_TRAP_PF_PK RT_BIT_32(5)
4835	/** @} */
4836
4837	#pragma pack(1)
4838	/**
4839	* 16-bit IDTR.
4840	*/
4841	typedef struct X86IDTR16
4842	{
4843	/** Offset. */
4844	uint16_t offSel;
4845	/** Selector. */
4846	uint16_t uSel;
4847	} X86IDTR16, *PX86IDTR16;
4848	#pragma pack()
4849
4850	#pragma pack(1)
4851	/**
4852	* 32-bit IDTR/GDTR.
4853	*/
4854	typedef struct X86XDTR32
4855	{
4856	/** Size of the descriptor table. */
4857	uint16_t cb;
4858	/** Address of the descriptor table. */
4859	#ifndef VBOX_FOR_DTRACE_LIB
4860	uint32_t uAddr;
4861	#else
4862	uint16_t au16Addr[2];
4863	#endif
4864	} X86XDTR32, *PX86XDTR32;
4865	#pragma pack()
4866
4867	#pragma pack(1)
4868	/**
4869	* 64-bit IDTR/GDTR.
4870	*/
4871	typedef struct X86XDTR64
4872	{
4873	/** Size of the descriptor table. */
4874	uint16_t cb;
4875	/** Address of the descriptor table. */
4876	#ifndef VBOX_FOR_DTRACE_LIB
4877	uint64_t uAddr;
4878	#else
4879	uint16_t au16Addr[4];
4880	#endif
4881	} X86XDTR64, *PX86XDTR64;
4882	#pragma pack()
4883
4884
4885	/** @name ModR/M
4886	* @{ */
4887	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4888	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4889	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4890	#define X86_MODRM_REG_SHIFT 3
4891	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4892	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4893	#define X86_MODRM_MOD_SHIFT 6
4894
4895	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
4896	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
4897	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
4898	#define X86_MOD_REG 3 /*< Registers. /
4899
4900	#ifndef VBOX_FOR_DTRACE_LIB
4901	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4902	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4903	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4904	/** @def X86_MODRM_MAKE
4905	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
4906	* @param a_Reg The register value (0..7).
4907	* @param a_RegMem The register or memory value (0..7). */
4908	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4909	#endif
4910
4911	/** @} */
4912
4913	/** @name SIB
4914	* @{ */
4915	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4916	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4917	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4918	#define X86_SIB_INDEX_SHIFT 3
4919	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4920	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4921	#define X86_SIB_SCALE_SHIFT 6
4922	#ifndef VBOX_FOR_DTRACE_LIB
4923	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4924	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4925	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4926	#endif
4927	/** @} */
4928
4929	/** @name General register indexes.
4930	* @{ */
4931	#define X86_GREG_xAX 0
4932	#define X86_GREG_xCX 1
4933	#define X86_GREG_xDX 2
4934	#define X86_GREG_xBX 3
4935	#define X86_GREG_xSP 4
4936	#define X86_GREG_xBP 5
4937	#define X86_GREG_xSI 6
4938	#define X86_GREG_xDI 7
4939	#define X86_GREG_x8 8
4940	#define X86_GREG_x9 9
4941	#define X86_GREG_x10 10
4942	#define X86_GREG_x11 11
4943	#define X86_GREG_x12 12
4944	#define X86_GREG_x13 13
4945	#define X86_GREG_x14 14
4946	#define X86_GREG_x15 15
4947	/** @} */
4948	/** General register count. */
4949	#define X86_GREG_COUNT 16
4950
4951	/** @name X86_SREG_XXX - Segment register indexes.
4952	* @{ */
4953	#define X86_SREG_ES 0
4954	#define X86_SREG_CS 1
4955	#define X86_SREG_SS 2
4956	#define X86_SREG_DS 3
4957	#define X86_SREG_FS 4
4958	#define X86_SREG_GS 5
4959	/** @} */
4960	/** Segment register count. */
4961	#define X86_SREG_COUNT 6
4962
4963
4964	/** @name X86_OP_XXX - Prefixes
4965	* @{ */
4966	#define X86_OP_PRF_CS UINT8_C(0x2e)
4967	#define X86_OP_PRF_SS UINT8_C(0x36)
4968	#define X86_OP_PRF_DS UINT8_C(0x3e)
4969	#define X86_OP_PRF_ES UINT8_C(0x26)
4970	#define X86_OP_PRF_FS UINT8_C(0x64)
4971	#define X86_OP_PRF_GS UINT8_C(0x65)
4972	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4973	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4974	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4975	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4976	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4977	#define X86_OP_REX_B UINT8_C(0x41)
4978	#define X86_OP_REX_X UINT8_C(0x42)
4979	#define X86_OP_REX_R UINT8_C(0x44)
4980	#define X86_OP_REX_W UINT8_C(0x48)
4981	/** @} */
4982
4983
4984	/** @} */
4985
4986	#endif /* !IPRT_INCLUDED_x86_h */
4987

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source: vbox/trunk/include/iprt/x86.h@ 101430

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