x86.h@ 102629

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# include <iprt/types.h>
46	# include <iprt/assert.h>
47	#else
48	# pragma D depends_on library vbox-types.d
49	#endif
50
51	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
52	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
53	#ifdef RT_OS_SOLARIS
54	# undef CS
55	# undef DS
56	# undef MSR_IA32_FLUSH_CMD
57	# undef MSR_AMD_VIRT_SPEC_CTL
58	#endif
59
60	/** @defgroup grp_rt_x86 x86 Types and Definitions
61	* @ingroup grp_rt
62	* @{
63	*/
64
65	#ifndef VBOX_FOR_DTRACE_LIB
66	/**
67	* EFLAGS Bits.
68	*/
69	typedef struct X86EFLAGSBITS
70	{
71	/** Bit 0 - CF - Carry flag - Status flag. */
72	unsigned u1CF : 1;
73	/** Bit 1 - 1 - Reserved flag. */
74	unsigned u1Reserved0 : 1;
75	/** Bit 2 - PF - Parity flag - Status flag. */
76	unsigned u1PF : 1;
77	/** Bit 3 - 0 - Reserved flag. */
78	unsigned u1Reserved1 : 1;
79	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
80	unsigned u1AF : 1;
81	/** Bit 5 - 0 - Reserved flag. */
82	unsigned u1Reserved2 : 1;
83	/** Bit 6 - ZF - Zero flag - Status flag. */
84	unsigned u1ZF : 1;
85	/** Bit 7 - SF - Signed flag - Status flag. */
86	unsigned u1SF : 1;
87	/** Bit 8 - TF - Trap flag - System flag. */
88	unsigned u1TF : 1;
89	/** Bit 9 - IF - Interrupt flag - System flag. */
90	unsigned u1IF : 1;
91	/** Bit 10 - DF - Direction flag - Control flag. */
92	unsigned u1DF : 1;
93	/** Bit 11 - OF - Overflow flag - Status flag. */
94	unsigned u1OF : 1;
95	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
96	unsigned u2IOPL : 2;
97	/** Bit 14 - NT - Nested task flag - System flag. */
98	unsigned u1NT : 1;
99	/** Bit 15 - 0 - Reserved flag. */
100	unsigned u1Reserved3 : 1;
101	/** Bit 16 - RF - Resume flag - System flag. */
102	unsigned u1RF : 1;
103	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
104	unsigned u1VM : 1;
105	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
106	unsigned u1AC : 1;
107	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
108	unsigned u1VIF : 1;
109	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
110	unsigned u1VIP : 1;
111	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
112	unsigned u1ID : 1;
113	/** Bit 22-31 - 0 - Reserved flag. */
114	unsigned u10Reserved4 : 10;
115	} X86EFLAGSBITS;
116	/** Pointer to EFLAGS bits. */
117	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
118	/** Pointer to const EFLAGS bits. */
119	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
120	#endif /* !VBOX_FOR_DTRACE_LIB */
121
122	/**
123	* EFLAGS.
124	*/
125	typedef union X86EFLAGS
126	{
127	/** The plain unsigned view. */
128	uint32_t u;
129	#ifndef VBOX_FOR_DTRACE_LIB
130	/** The bitfield view. */
131	X86EFLAGSBITS Bits;
132	#endif
133	/** The 8-bit view. */
134	uint8_t au8[4];
135	/** The 16-bit view. */
136	uint16_t au16[2];
137	/** The 32-bit view. */
138	uint32_t au32[1];
139	/** The 32-bit view. */
140	uint32_t u32;
141	} X86EFLAGS;
142	/** Pointer to EFLAGS. */
143	typedef X86EFLAGS *PX86EFLAGS;
144	/** Pointer to const EFLAGS. */
145	typedef const X86EFLAGS *PCX86EFLAGS;
146
147	/**
148	* RFLAGS (32 upper bits are reserved).
149	*/
150	typedef union X86RFLAGS
151	{
152	/** The plain unsigned view. */
153	uint64_t u;
154	#ifndef VBOX_FOR_DTRACE_LIB
155	/** The bitfield view. */
156	X86EFLAGSBITS Bits;
157	#endif
158	/** The 8-bit view. */
159	uint8_t au8[8];
160	/** The 16-bit view. */
161	uint16_t au16[4];
162	/** The 32-bit view. */
163	uint32_t au32[2];
164	/** The 64-bit view. */
165	uint64_t au64[1];
166	/** The 64-bit view. */
167	uint64_t u64;
168	} X86RFLAGS;
169	/** Pointer to RFLAGS. */
170	typedef X86RFLAGS *PX86RFLAGS;
171	/** Pointer to const RFLAGS. */
172	typedef const X86RFLAGS *PCX86RFLAGS;
173
174
175	/** @name EFLAGS
176	* @{
177	*/
178	/** Bit 0 - CF - Carry flag - Status flag. */
179	#define X86_EFL_CF RT_BIT_32(0)
180	#define X86_EFL_CF_BIT 0
181	/** Bit 1 - Reserved, reads as 1. */
182	#define X86_EFL_1 RT_BIT_32(1)
183	/** Bit 2 - PF - Parity flag - Status flag. */
184	#define X86_EFL_PF RT_BIT_32(2)
185	#define X86_EFL_PF_BIT 2
186	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
187	#define X86_EFL_AF RT_BIT_32(4)
188	#define X86_EFL_AF_BIT 4
189	/** Bit 6 - ZF - Zero flag - Status flag. */
190	#define X86_EFL_ZF RT_BIT_32(6)
191	#define X86_EFL_ZF_BIT 6
192	/** Bit 7 - SF - Signed flag - Status flag. */
193	#define X86_EFL_SF RT_BIT_32(7)
194	#define X86_EFL_SF_BIT 7
195	/** Bit 8 - TF - Trap flag - System flag. */
196	#define X86_EFL_TF RT_BIT_32(8)
197	#define X86_EFL_TF_BIT 8
198	/** Bit 9 - IF - Interrupt flag - System flag. */
199	#define X86_EFL_IF RT_BIT_32(9)
200	#define X86_EFL_IF_BIT 9
201	/** Bit 10 - DF - Direction flag - Control flag. */
202	#define X86_EFL_DF RT_BIT_32(10)
203	#define X86_EFL_DF_BIT 10
204	/** Bit 11 - OF - Overflow flag - Status flag. */
205	#define X86_EFL_OF RT_BIT_32(11)
206	#define X86_EFL_OF_BIT 11
207	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
208	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
209	/** Bit 14 - NT - Nested task flag - System flag. */
210	#define X86_EFL_NT RT_BIT_32(14)
211	#define X86_EFL_NT_BIT 14
212	/** Bit 16 - RF - Resume flag - System flag. */
213	#define X86_EFL_RF RT_BIT_32(16)
214	#define X86_EFL_RF_BIT 16
215	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
216	#define X86_EFL_VM RT_BIT_32(17)
217	#define X86_EFL_VM_BIT 17
218	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
219	#define X86_EFL_AC RT_BIT_32(18)
220	#define X86_EFL_AC_BIT 18
221	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
222	#define X86_EFL_VIF RT_BIT_32(19)
223	#define X86_EFL_VIF_BIT 19
224	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
225	#define X86_EFL_VIP RT_BIT_32(20)
226	#define X86_EFL_VIP_BIT 20
227	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
228	#define X86_EFL_ID RT_BIT_32(21)
229	#define X86_EFL_ID_BIT 21
230	/** All live bits. */
231	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
232	/** Read as 1 bits. */
233	#define X86_EFL_RA1_MASK RT_BIT_32(1)
234	/** Read as 0 bits, excluding bits 31:22.
235	* Bits 3, 5, 15, and 22 thru 31. */
236	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
237	/** Read as 0 bits, excluding bits 31:22.
238	* Bits 3, 5 and 15. */
239	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
240	/** IOPL shift. */
241	#define X86_EFL_IOPL_SHIFT 12
242	/** The IOPL level from the flags. */
243	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
244	/** Bits restored by popf */
245	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
246	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
247	/** Bits restored by popf */
248	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
249	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
250	/** The status bits commonly updated by arithmetic instructions. */
251	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
252	/** @} */
253
254
255	/** CPUID Feature information - ECX.
256	* CPUID query with EAX=1.
257	*/
258	#ifndef VBOX_FOR_DTRACE_LIB
259	typedef struct X86CPUIDFEATECX
260	{
261	/** Bit 0 - SSE3 - Supports SSE3 or not. */
262	unsigned u1SSE3 : 1;
263	/** Bit 1 - PCLMULQDQ. */
264	unsigned u1PCLMULQDQ : 1;
265	/** Bit 2 - DS Area 64-bit layout. */
266	unsigned u1DTE64 : 1;
267	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
268	unsigned u1Monitor : 1;
269	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
270	unsigned u1CPLDS : 1;
271	/** Bit 5 - VMX - Virtual Machine Technology. */
272	unsigned u1VMX : 1;
273	/** Bit 6 - SMX: Safer Mode Extensions. */
274	unsigned u1SMX : 1;
275	/** Bit 7 - EST - Enh. SpeedStep Tech. */
276	unsigned u1EST : 1;
277	/** Bit 8 - TM2 - Terminal Monitor 2. */
278	unsigned u1TM2 : 1;
279	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
280	unsigned u1SSSE3 : 1;
281	/** Bit 10 - CNTX-ID - L1 Context ID. */
282	unsigned u1CNTXID : 1;
283	/** Bit 11 - Reserved. */
284	unsigned u1Reserved1 : 1;
285	/** Bit 12 - FMA. */
286	unsigned u1FMA : 1;
287	/** Bit 13 - CX16 - CMPXCHG16B. */
288	unsigned u1CX16 : 1;
289	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
290	unsigned u1TPRUpdate : 1;
291	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
292	unsigned u1PDCM : 1;
293	/** Bit 16 - Reserved. */
294	unsigned u1Reserved2 : 1;
295	/** Bit 17 - PCID - Process-context identifiers. */
296	unsigned u1PCID : 1;
297	/** Bit 18 - Direct Cache Access. */
298	unsigned u1DCA : 1;
299	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
300	unsigned u1SSE4_1 : 1;
301	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
302	unsigned u1SSE4_2 : 1;
303	/** Bit 21 - x2APIC. */
304	unsigned u1x2APIC : 1;
305	/** Bit 22 - MOVBE - Supports MOVBE. */
306	unsigned u1MOVBE : 1;
307	/** Bit 23 - POPCNT - Supports POPCNT. */
308	unsigned u1POPCNT : 1;
309	/** Bit 24 - TSC-Deadline. */
310	unsigned u1TSCDEADLINE : 1;
311	/** Bit 25 - AES. */
312	unsigned u1AES : 1;
313	/** Bit 26 - XSAVE - Supports XSAVE. */
314	unsigned u1XSAVE : 1;
315	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
316	unsigned u1OSXSAVE : 1;
317	/** Bit 28 - AVX - Supports AVX instruction extensions. */
318	unsigned u1AVX : 1;
319	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
320	unsigned u1F16C : 1;
321	/** Bit 30 - RDRAND - Supports RDRAND. */
322	unsigned u1RDRAND : 1;
323	/** Bit 31 - Hypervisor present (we're a guest). */
324	unsigned u1HVP : 1;
325	} X86CPUIDFEATECX;
326	#else /* VBOX_FOR_DTRACE_LIB */
327	typedef uint32_t X86CPUIDFEATECX;
328	#endif /* VBOX_FOR_DTRACE_LIB */
329	/** Pointer to CPUID Feature Information - ECX. */
330	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
331	/** Pointer to const CPUID Feature Information - ECX. */
332	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
333
334
335	/** CPUID Feature Information - EDX.
336	* CPUID query with EAX=1.
337	*/
338	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
339	typedef struct X86CPUIDFEATEDX
340	{
341	/** Bit 0 - FPU - x87 FPU on Chip. */
342	unsigned u1FPU : 1;
343	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
344	unsigned u1VME : 1;
345	/** Bit 2 - DE - Debugging extensions. */
346	unsigned u1DE : 1;
347	/** Bit 3 - PSE - Page Size Extension. */
348	unsigned u1PSE : 1;
349	/** Bit 4 - TSC - Time Stamp Counter. */
350	unsigned u1TSC : 1;
351	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
352	unsigned u1MSR : 1;
353	/** Bit 6 - PAE - Physical Address Extension. */
354	unsigned u1PAE : 1;
355	/** Bit 7 - MCE - Machine Check Exception. */
356	unsigned u1MCE : 1;
357	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
358	unsigned u1CX8 : 1;
359	/** Bit 9 - APIC - APIC On-Chip. */
360	unsigned u1APIC : 1;
361	/** Bit 10 - Reserved. */
362	unsigned u1Reserved1 : 1;
363	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
364	unsigned u1SEP : 1;
365	/** Bit 12 - MTRR - Memory Type Range Registers. */
366	unsigned u1MTRR : 1;
367	/** Bit 13 - PGE - PTE Global Bit. */
368	unsigned u1PGE : 1;
369	/** Bit 14 - MCA - Machine Check Architecture. */
370	unsigned u1MCA : 1;
371	/** Bit 15 - CMOV - Conditional Move Instructions. */
372	unsigned u1CMOV : 1;
373	/** Bit 16 - PAT - Page Attribute Table. */
374	unsigned u1PAT : 1;
375	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
376	unsigned u1PSE36 : 1;
377	/** Bit 18 - PSN - Processor Serial Number. */
378	unsigned u1PSN : 1;
379	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
380	unsigned u1CLFSH : 1;
381	/** Bit 20 - Reserved. */
382	unsigned u1Reserved2 : 1;
383	/** Bit 21 - DS - Debug Store. */
384	unsigned u1DS : 1;
385	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
386	unsigned u1ACPI : 1;
387	/** Bit 23 - MMX - Intel MMX 'Technology'. */
388	unsigned u1MMX : 1;
389	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
390	unsigned u1FXSR : 1;
391	/** Bit 25 - SSE - SSE Support. */
392	unsigned u1SSE : 1;
393	/** Bit 26 - SSE2 - SSE2 Support. */
394	unsigned u1SSE2 : 1;
395	/** Bit 27 - SS - Self Snoop. */
396	unsigned u1SS : 1;
397	/** Bit 28 - HTT - Hyper-Threading Technology. */
398	unsigned u1HTT : 1;
399	/** Bit 29 - TM - Thermal Monitor. */
400	unsigned u1TM : 1;
401	/** Bit 30 - Reserved - . */
402	unsigned u1Reserved3 : 1;
403	/** Bit 31 - PBE - Pending Break Enabled. */
404	unsigned u1PBE : 1;
405	} X86CPUIDFEATEDX;
406	#else /* VBOX_FOR_DTRACE_LIB */
407	typedef uint32_t X86CPUIDFEATEDX;
408	#endif /* VBOX_FOR_DTRACE_LIB */
409	/** Pointer to CPUID Feature Information - EDX. */
410	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
411	/** Pointer to const CPUID Feature Information - EDX. */
412	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
413
414	/** @name CPUID Vendor information.
415	* CPUID query with EAX=0.
416	* @{
417	*/
418	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
419	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
420	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
421
422	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
423	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
424	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
425
426	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
427	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
428	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
429
430	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
431	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
432	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
433
434	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
435	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
436	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
437	/** @} */
438
439
440	/** @name CPUID Feature information.
441	* CPUID query with EAX=1.
442	* @{
443	*/
444	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
445	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
446	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
447	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
448	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
449	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
450	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
451	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
452	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
453	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
454	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
455	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
456	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
457	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
458	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
459	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
460	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
461	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
462	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
463	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
464	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
465	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
466	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
467	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
468	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
469	/** ECX Bit 12 - FMA. */
470	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
471	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
472	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
473	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
474	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
475	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
476	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
477	/** ECX Bit 17 - PCID - Process-context identifiers. */
478	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
479	/** ECX Bit 18 - DCA - Direct Cache Access. */
480	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
481	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
482	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
483	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
484	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
485	/** ECX Bit 21 - x2APIC support. */
486	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
487	/** ECX Bit 22 - MOVBE instruction. */
488	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
489	/** ECX Bit 23 - POPCNT instruction. */
490	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
491	/** ECX Bir 24 - TSC-Deadline. */
492	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
493	/** ECX Bit 25 - AES instructions. */
494	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
495	/** ECX Bit 26 - XSAVE instruction. */
496	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
497	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
498	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
499	/** ECX Bit 28 - AVX. */
500	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
501	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
502	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
503	/** ECX Bit 30 - RDRAND instruction. */
504	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
505	/** ECX Bit 31 - Hypervisor Present (software only). */
506	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
507
508
509	/** Bit 0 - FPU - x87 FPU on Chip. */
510	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
511	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
512	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
513	/** Bit 2 - DE - Debugging extensions. */
514	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
515	/** Bit 3 - PSE - Page Size Extension. */
516	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
517	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
518	/** Bit 4 - TSC - Time Stamp Counter. */
519	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
520	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
521	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
522	/** Bit 6 - PAE - Physical Address Extension. */
523	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
524	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
525	/** Bit 7 - MCE - Machine Check Exception. */
526	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
527	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
528	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
529	/** Bit 9 - APIC - APIC On-Chip. */
530	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
531	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
532	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
533	/** Bit 12 - MTRR - Memory Type Range Registers. */
534	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
535	/** Bit 13 - PGE - PTE Global Bit. */
536	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
537	/** Bit 14 - MCA - Machine Check Architecture. */
538	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
539	/** Bit 15 - CMOV - Conditional Move Instructions. */
540	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
541	/** Bit 16 - PAT - Page Attribute Table. */
542	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
543	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
544	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
545	/** Bit 18 - PSN - Processor Serial Number. */
546	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
547	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
548	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
549	/** Bit 21 - DS - Debug Store. */
550	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
551	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
552	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
553	/** Bit 23 - MMX - Intel MMX Technology. */
554	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
555	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
556	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
557	/** Bit 25 - SSE - SSE Support. */
558	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
559	/** Bit 26 - SSE2 - SSE2 Support. */
560	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
561	/** Bit 27 - SS - Self Snoop. */
562	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
563	/** Bit 28 - HTT - Hyper-Threading Technology. */
564	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
565	/** Bit 29 - TM - Therm. Monitor. */
566	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
567	/** Bit 31 - PBE - Pending Break Enabled. */
568	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
569	/** @} */
570
571	/** @name CPUID mwait/monitor information.
572	* CPUID query with EAX=5.
573	* @{
574	*/
575	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
576	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
577	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
578	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
579	/** @} */
580
581
582	/** @name CPUID Thermal and Power Management information.
583	* Generally Intel only unless noted otherwise.
584	* CPUID query with EAX=5. @{
585	*/
586	/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
587	#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
588	/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
589	#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
590	/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
591	#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
592	/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
593	#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
594	/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
595	#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
596	/** EAX Bit 6 - PTM - Package Thermal Management supported. */
597	#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
598	/** EAX Bit 7 - HWP - HWP base MSRs supported. */
599	#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
600	/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
601	#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
602	/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
603	#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
604	/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
605	#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
606	/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
607	#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
608	/** EAX Bit 13 - HDC - HDC base MSRs supported. */
609	#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
610	/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
611	#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
612	/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
613	#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
614	/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
615	#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
616	/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
617	#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
618
619	/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
620	#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
621	/** @} */
622
623
624	/** @name CPUID Structured Extended Feature information.
625	* CPUID query with EAX=7.
626	* @{
627	*/
628	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
629	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
630	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
631	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
632	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
633	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
634	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
635	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
636	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
637	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
638	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
639	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
640	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
641	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
642	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
643	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
644	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
645	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
646	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
647	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
648	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
649	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
650	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
651	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
652	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
653	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
654	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
655	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
656	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
657	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
658	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
659	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
660	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
661	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
662	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
663	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
664	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
665	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
666	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
667	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
668	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
669	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
670	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
671	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
672	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
673	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
674	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
675	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
676	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
677	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
678	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
679	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
680
681	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
682	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
683	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
684	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
685	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
686	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
687	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
688	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
689	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
690	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
691	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
692	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
693	/** ECX Bit 22 - RDPID - Support pread process ID. */
694	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
695	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
696	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
697
698	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
699	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
700	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
701	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
702	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
703	* IBPB command in IA32_PRED_CMD. */
704	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
705	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
706	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
707	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
708	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
709	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
710	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
711	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
712	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
713
714	/** @} */
715
716
717	/** @name CPUID Extended Feature information.
718	* CPUID query with EAX=0x80000001.
719	* @{
720	*/
721	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
722	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
723
724	/** EDX Bit 11 - SYSCALL/SYSRET. */
725	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
726	/** EDX Bit 20 - No-Execute/Execute-Disable. */
727	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
728	/** EDX Bit 26 - 1 GB large page. */
729	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
730	/** EDX Bit 27 - RDTSCP. */
731	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
732	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
733	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
734	/** @}*/
735
736	/** @name CPUID AMD Feature information.
737	* CPUID query with EAX=0x80000001.
738	* @{
739	*/
740	/** Bit 0 - FPU - x87 FPU on Chip. */
741	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
742	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
743	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
744	/** Bit 2 - DE - Debugging extensions. */
745	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
746	/** Bit 3 - PSE - Page Size Extension. */
747	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
748	/** Bit 4 - TSC - Time Stamp Counter. */
749	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
750	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
751	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
752	/** Bit 6 - PAE - Physical Address Extension. */
753	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
754	/** Bit 7 - MCE - Machine Check Exception. */
755	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
756	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
757	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
758	/** Bit 9 - APIC - APIC On-Chip. */
759	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
760	/** Bit 12 - MTRR - Memory Type Range Registers. */
761	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
762	/** Bit 13 - PGE - PTE Global Bit. */
763	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
764	/** Bit 14 - MCA - Machine Check Architecture. */
765	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
766	/** Bit 15 - CMOV - Conditional Move Instructions. */
767	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
768	/** Bit 16 - PAT - Page Attribute Table. */
769	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
770	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
771	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
772	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
773	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
774	/** Bit 23 - MMX - Intel MMX Technology. */
775	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
776	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
777	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
778	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
779	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
780	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
781	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
782	/** Bit 31 - 3DNOW - AMD 3DNow. */
783	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
784
785	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
786	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
787	/** Bit 2 - SVM - AMD VM extensions. */
788	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
789	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
790	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
791	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
792	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
793	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
794	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
795	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
796	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
797	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
798	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
799	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
800	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
801	/** Bit 9 - OSVW - AMD OS visible workaround. */
802	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
803	/** Bit 10 - IBS - Instruct based sampling. */
804	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
805	/** Bit 11 - XOP - Extended operation support (see APM6). */
806	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
807	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
808	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
809	/** Bit 13 - WDT - AMD Watchdog timer support. */
810	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
811	/** Bit 15 - LWP - Lightweight profiling support. */
812	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
813	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
814	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
815	/** Bit 19 - NodeId - Indicates support for
816	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
817	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
818	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
819	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
820	/** Bit 22 - TopologyExtensions - . */
821	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
822	/** @} */
823
824
825	/** @name CPUID AMD Feature information.
826	* CPUID query with EAX=0x80000007.
827	* @{
828	*/
829	/** Bit 0 - TS - Temperature Sensor. */
830	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
831	/** Bit 1 - FID - Frequency ID Control. */
832	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
833	/** Bit 2 - VID - Voltage ID Control. */
834	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
835	/** Bit 3 - TTP - THERMTRIP. */
836	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
837	/** Bit 4 - TM - Hardware Thermal Control. */
838	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
839	/** Bit 5 - STC - Software Thermal Control. */
840	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
841	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
842	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
843	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
844	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
845	/** Bit 8 - TSCINVAR - TSC Invariant. */
846	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
847	/** Bit 9 - CPB - TSC Invariant. */
848	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
849	/** Bit 10 - EffFreqRO - MPERF/APERF. */
850	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
851	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
852	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
853	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
854	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
855	/** @} */
856
857
858	/** @name CPUID AMD extended feature extensions ID (EBX).
859	* CPUID query with EAX=0x80000008.
860	* @{
861	*/
862	/** Bit 0 - CLZERO - Clear zero instruction. */
863	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
864	/** Bit 1 - IRPerf - Instructions retired count support. */
865	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
866	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
867	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
868	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
869	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
870	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
871	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
872	/* AMD pipeline length: 9 feature bits ;-) */
873	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
874	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
875	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
876	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
877	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
878	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
879	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
880	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
881	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
882	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
883	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
884	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
885	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
886	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
887	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
888	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
889	/** Bit 26 - Speculative Store Bypass Disable not required. */
890	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
891	/** @} */
892
893
894	/** @name CPUID AMD SVM Feature information.
895	* CPUID query with EAX=0x8000000a.
896	* @{
897	*/
898	/** Bit 0 - NP - Nested Paging supported. */
899	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
900	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
901	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
902	/** Bit 2 - SVML - SVM locking bit supported. */
903	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
904	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
905	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
906	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
907	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
908	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
909	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
910	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
911	* VMCB.TLB_Control is supported. */
912	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
913	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
914	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
915	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
916	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
917	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
918	* intercept filter cycle count threshold. */
919	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
920	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
921	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
922	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
923	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
924	/** Bit 16 - VGIF - Supports virtualized GIF. */
925	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
926	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
927	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
928	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
929	* mode. */
930	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
931	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
932	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
933	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
934	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
935	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
936	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
937	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
938	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
939	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
940	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
941	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
942	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
943	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
944	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
945	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
946	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
947	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
948	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
949	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
950	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
951
952	/** @} */
953
954
955	/** @name CR0
956	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
957	* reserved flags.
958	* @{ */
959	/** Bit 0 - PE - Protection Enabled */
960	#define X86_CR0_PE RT_BIT_32(0)
961	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
962	/** Bit 1 - MP - Monitor Coprocessor */
963	#define X86_CR0_MP RT_BIT_32(1)
964	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
965	/** Bit 2 - EM - Emulation. */
966	#define X86_CR0_EM RT_BIT_32(2)
967	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
968	/** Bit 3 - TS - Task Switch. */
969	#define X86_CR0_TS RT_BIT_32(3)
970	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
971	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
972	#define X86_CR0_ET RT_BIT_32(4)
973	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
974	/** Bit 5 - NE - Numeric error (486+). */
975	#define X86_CR0_NE RT_BIT_32(5)
976	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
977	/** Bit 16 - WP - Write Protect (486+). */
978	#define X86_CR0_WP RT_BIT_32(16)
979	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
980	/** Bit 18 - AM - Alignment Mask (486+). */
981	#define X86_CR0_AM RT_BIT_32(18)
982	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
983	/** Bit 29 - NW - Not Write-though (486+). */
984	#define X86_CR0_NW RT_BIT_32(29)
985	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
986	/** Bit 30 - WP - Cache Disable (486+). */
987	#define X86_CR0_CD RT_BIT_32(30)
988	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
989	/** Bit 31 - PG - Paging. */
990	#define X86_CR0_PG RT_BIT_32(31)
991	#define X86_CR0_PAGING RT_BIT_32(31)
992	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
993	/** @} */
994
995
996	/** @name CR3
997	* @{ */
998	/** Bit 3 - PWT - Page-level Writes Transparent. */
999	#define X86_CR3_PWT RT_BIT_32(3)
1000	/** Bit 4 - PCD - Page-level Cache Disable. */
1001	#define X86_CR3_PCD RT_BIT_32(4)
1002	/** Bits 12-31 - - Page directory page number. */
1003	#define X86_CR3_PAGE_MASK (0xfffff000)
1004	/** Bits 5-31 - - PAE Page directory page number. */
1005	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1006	/** Bits 12-51 - - AMD64 PML4 page number.
1007	* @note This is a maxed out mask, the actual acceptable CR3 value can
1008	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1009	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1010	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1011	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1012	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1013	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1014	/** @} */
1015
1016
1017	/** @name CR4
1018	* @{ */
1019	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1020	#define X86_CR4_VME RT_BIT_32(0)
1021	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1022	#define X86_CR4_PVI RT_BIT_32(1)
1023	/** Bit 2 - TSD - Time Stamp Disable. */
1024	#define X86_CR4_TSD RT_BIT_32(2)
1025	/** Bit 3 - DE - Debugging Extensions. */
1026	#define X86_CR4_DE RT_BIT_32(3)
1027	/** Bit 4 - PSE - Page Size Extension. */
1028	#define X86_CR4_PSE RT_BIT_32(4)
1029	/** Bit 5 - PAE - Physical Address Extension. */
1030	#define X86_CR4_PAE RT_BIT_32(5)
1031	/** Bit 6 - MCE - Machine-Check Enable. */
1032	#define X86_CR4_MCE RT_BIT_32(6)
1033	/** Bit 7 - PGE - Page Global Enable. */
1034	#define X86_CR4_PGE RT_BIT_32(7)
1035	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1036	#define X86_CR4_PCE RT_BIT_32(8)
1037	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1038	#define X86_CR4_OSFXSR RT_BIT_32(9)
1039	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1040	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1041	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1042	#define X86_CR4_UMIP RT_BIT_32(11)
1043	/** Bit 13 - VMXE - VMX mode is enabled. */
1044	#define X86_CR4_VMXE RT_BIT_32(13)
1045	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1046	#define X86_CR4_SMXE RT_BIT_32(14)
1047	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1048	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1049	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1050	#define X86_CR4_PCIDE RT_BIT_32(17)
1051	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1052	* extended states. */
1053	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1054	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1055	#define X86_CR4_SMEP RT_BIT_32(20)
1056	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1057	#define X86_CR4_SMAP RT_BIT_32(21)
1058	/** Bit 22 - PKE - Protection Key Enable. */
1059	#define X86_CR4_PKE RT_BIT_32(22)
1060	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1061	#define X86_CR4_CET RT_BIT_32(23)
1062	/** @} */
1063
1064
1065	/** @name DR6
1066	* @{ */
1067	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1068	#define X86_DR6_B0 RT_BIT_32(0)
1069	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1070	#define X86_DR6_B1 RT_BIT_32(1)
1071	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1072	#define X86_DR6_B2 RT_BIT_32(2)
1073	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1074	#define X86_DR6_B3 RT_BIT_32(3)
1075	/** Mask of all the Bx bits. */
1076	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1077	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1078	#define X86_DR6_BD RT_BIT_32(13)
1079	/** Bit 14 - BS - Single step */
1080	#define X86_DR6_BS RT_BIT_32(14)
1081	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1082	#define X86_DR6_BT RT_BIT_32(15)
1083	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1084	#define X86_DR6_RTM RT_BIT_32(16)
1085	/** Value of DR6 after powerup/reset. */
1086	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1087	/** Bits which must be 1s in DR6. */
1088	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1089	/** Bits which must be 1s in DR6, when RTM is supported. */
1090	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1091	/** Bits which must be 0s in DR6. */
1092	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1093	/** Bits which must be 0s on writes to DR6. */
1094	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1095	/** @} */
1096
1097	/** Get the DR6.Bx bit for a the given breakpoint. */
1098	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1099
1100
1101	/** @name DR7
1102	* @{ */
1103	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1104	#define X86_DR7_L0 RT_BIT_32(0)
1105	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1106	#define X86_DR7_G0 RT_BIT_32(1)
1107	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1108	#define X86_DR7_L1 RT_BIT_32(2)
1109	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1110	#define X86_DR7_G1 RT_BIT_32(3)
1111	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1112	#define X86_DR7_L2 RT_BIT_32(4)
1113	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1114	#define X86_DR7_G2 RT_BIT_32(5)
1115	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1116	#define X86_DR7_L3 RT_BIT_32(6)
1117	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1118	#define X86_DR7_G3 RT_BIT_32(7)
1119	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1120	#define X86_DR7_LE RT_BIT_32(8)
1121	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1122	#define X86_DR7_GE RT_BIT_32(9)
1123
1124	/** L0, L1, L2, and L3. */
1125	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1126	/** L0, L1, L2, and L3. */
1127	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1128
1129	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1130	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1131	#define X86_DR7_RTM RT_BIT_32(11)
1132	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1133	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1134	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1135	* instruction is executed.
1136	* @see http://www.rcollins.org/secrets/DR7.html */
1137	#define X86_DR7_ICE_IR RT_BIT_32(12)
1138	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1139	* any DR register is accessed. */
1140	#define X86_DR7_GD RT_BIT_32(13)
1141	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1142	* Pentium. */
1143	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1144	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1145	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1146	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1147	#define X86_DR7_RW0_MASK (3 << 16)
1148	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1149	#define X86_DR7_LEN0_MASK (3 << 18)
1150	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1151	#define X86_DR7_RW1_MASK (3 << 20)
1152	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1153	#define X86_DR7_LEN1_MASK (3 << 22)
1154	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1155	#define X86_DR7_RW2_MASK (3 << 24)
1156	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1157	#define X86_DR7_LEN2_MASK (3 << 26)
1158	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1159	#define X86_DR7_RW3_MASK (3 << 28)
1160	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1161	#define X86_DR7_LEN3_MASK (3 << 30)
1162
1163	/** Bits which reads as 1s. */
1164	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1165	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1166	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1167	/** Bits which must be 0s when writing to DR7. */
1168	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1169
1170	/** Calcs the L bit of Nth breakpoint.
1171	* @param iBp The breakpoint number [0..3].
1172	*/
1173	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1174
1175	/** Calcs the G bit of Nth breakpoint.
1176	* @param iBp The breakpoint number [0..3].
1177	*/
1178	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1179
1180	/** Calcs the L and G bits of Nth breakpoint.
1181	* @param iBp The breakpoint number [0..3].
1182	*/
1183	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1184
1185	/** @name Read/Write values.
1186	* @{ */
1187	/** Break on instruction fetch only. */
1188	#define X86_DR7_RW_EO UINT32_C(0)
1189	/** Break on write only. */
1190	#define X86_DR7_RW_WO UINT32_C(1)
1191	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1192	#define X86_DR7_RW_IO UINT32_C(2)
1193	/** Break on read or write (but not instruction fetches). */
1194	#define X86_DR7_RW_RW UINT32_C(3)
1195	/** @} */
1196
1197	/** Shifts a X86_DR7_RW_* value to its right place.
1198	* @param iBp The breakpoint number [0..3].
1199	* @param fRw One of the X86_DR7_RW_* value.
1200	*/
1201	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1202
1203	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1204	* one of the X86_DR7_RW_XXX constants).
1205	*
1206	* @returns X86_DR7_RW_XXX
1207	* @param uDR7 DR7 value
1208	* @param iBp The breakpoint number [0..3].
1209	*/
1210	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1211
1212	/** R/W0, R/W1, R/W2, and R/W3. */
1213	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1214
1215	#ifndef VBOX_FOR_DTRACE_LIB
1216	/** Checks the RW and LEN fields are set up for an instruction breakpoint.
1217	* @note This does not check if it's enabled. */
1218	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1219	/** Checks if an instruction breakpoint is enabled and configured correctly.
1220	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1221	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1222	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1223	/** Checks if there are any instruction fetch breakpoint types configured in the
1224	* RW and LEN registers.
1225	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1226	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1227	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1228	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1229	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1230	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1231
1232	/** Checks if there are any I/O breakpoint types configured in the RW
1233	* registers. Does NOT check if these are enabled, sorry. */
1234	# define X86_DR7_ANY_RW_IO(uDR7) \
1235	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1236	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1237	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1238	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1239	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1240	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1241	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1242	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1243	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1244	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1245	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1246
1247	#endif /* !VBOX_FOR_DTRACE_LIB */
1248
1249	/** @name Length values.
1250	* @{ */
1251	#define X86_DR7_LEN_BYTE UINT32_C(0)
1252	#define X86_DR7_LEN_WORD UINT32_C(1)
1253	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1254	#define X86_DR7_LEN_DWORD UINT32_C(3)
1255	/** @} */
1256
1257	/** Shifts a X86_DR7_LEN_* value to its right place.
1258	* @param iBp The breakpoint number [0..3].
1259	* @param cb One of the X86_DR7_LEN_* values.
1260	*/
1261	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1262
1263	/** Fetch the breakpoint length bits from the DR7 value.
1264	* @param uDR7 DR7 value
1265	* @param iBp The breakpoint number [0..3].
1266	*/
1267	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1268
1269	/** Mask used to check if any breakpoints are enabled. */
1270	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1271
1272	/** LEN0, LEN1, LEN2, and LEN3. */
1273	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1274	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1275	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1276
1277	/** Value of DR7 after powerup/reset. */
1278	#define X86_DR7_INIT_VAL 0x400
1279	/** @} */
1280
1281
1282	/** @name Machine Specific Registers
1283	* @{
1284	*/
1285	/** Machine check address register (P5). */
1286	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1287	/** Machine check type register (P5). */
1288	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1289	/** Time Stamp Counter. */
1290	#define MSR_IA32_TSC 0x10
1291	#define MSR_IA32_CESR UINT32_C(0x00000011)
1292	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1293	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1294
1295	#define MSR_IA32_PLATFORM_ID 0x17
1296
1297	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1298	# define MSR_IA32_APICBASE 0x1b
1299	/** Local APIC enabled. */
1300	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1301	/** X2APIC enabled (requires the EN bit to be set). */
1302	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1303	/** The processor is the boot strap processor (BSP). */
1304	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1305	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1306	* width. */
1307	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1308	/** The default physical base address of the APIC. */
1309	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1310	/** Gets the physical base address from the MSR. */
1311	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1312	#endif
1313
1314	/** Undocumented intel MSR for reporting thread and core counts.
1315	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1316	* first 16 bits is the thread count. The next 16 bits the core count, except
1317	* on Westmere where it seems it's only the next 4 bits for some reason. */
1318	#define MSR_CORE_THREAD_COUNT 0x35
1319
1320	/** CPU Feature control. */
1321	#define MSR_IA32_FEATURE_CONTROL 0x3A
1322	/** Feature control - Lock MSR from writes (R/W0). */
1323	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1324	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1325	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1326	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1327	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1328	/** Feature control - SENTER local functions enable (R/WL). */
1329	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1330	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1331	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1332	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1333	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1334	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1335	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1336	/** Feature control - SENTER global enable (R/WL). */
1337	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1338	/** Feature control - SGX launch control enable (R/WL). */
1339	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1340	/** Feature control - SGX global enable (R/WL). */
1341	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1342	/** Feature control - LMCE on (R/WL). */
1343	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1344
1345	/** Per-processor TSC adjust MSR. */
1346	#define MSR_IA32_TSC_ADJUST 0x3B
1347
1348	/** Spectre control register.
1349	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1350	#define MSR_IA32_SPEC_CTRL 0x48
1351	/** IBRS - Indirect branch restricted speculation. */
1352	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1353	/** STIBP - Single thread indirect branch predictors. */
1354	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1355	/** SSBD - Speculative Store Bypass Disable. */
1356	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1357
1358	/** Prediction command register.
1359	* Write only, logical processor scope, no state since write only. */
1360	#define MSR_IA32_PRED_CMD 0x49
1361	/** IBPB - Indirect branch prediction barrie when written as 1. */
1362	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1363
1364	/** BIOS update trigger (microcode update). */
1365	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1366
1367	/** BIOS update signature (microcode). */
1368	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1369
1370	/** SMM monitor control. */
1371	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1372	/** SMM control - Valid. */
1373	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1374	/** SMM control - VMXOFF unblocks SMI. */
1375	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1376	/** SMM control - MSEG base physical address. */
1377	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1378
1379	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1380	#define MSR_IA32_SMBASE 0x9E
1381
1382	/** General performance counter no. 0. */
1383	#define MSR_IA32_PMC0 0xC1
1384	/** General performance counter no. 1. */
1385	#define MSR_IA32_PMC1 0xC2
1386	/** General performance counter no. 2. */
1387	#define MSR_IA32_PMC2 0xC3
1388	/** General performance counter no. 3. */
1389	#define MSR_IA32_PMC3 0xC4
1390	/** General performance counter no. 4. */
1391	#define MSR_IA32_PMC4 0xC5
1392	/** General performance counter no. 5. */
1393	#define MSR_IA32_PMC5 0xC6
1394	/** General performance counter no. 6. */
1395	#define MSR_IA32_PMC6 0xC7
1396	/** General performance counter no. 7. */
1397	#define MSR_IA32_PMC7 0xC8
1398
1399	/** Nehalem power control. */
1400	#define MSR_IA32_PLATFORM_INFO 0xCE
1401
1402	/** Get FSB clock status (Intel-specific). */
1403	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1404
1405	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1406	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1407
1408	/** C0 Maximum Frequency Clock Count */
1409	#define MSR_IA32_MPERF 0xE7
1410	/** C0 Actual Frequency Clock Count */
1411	#define MSR_IA32_APERF 0xE8
1412
1413	/** MTRR Capabilities. */
1414	#define MSR_IA32_MTRR_CAP 0xFE
1415	/** Bits 0-7 - VCNT - Variable range registers count. */
1416	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1417	/** Bit 8 - FIX - Fixed range registers supported. */
1418	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1419	/** Bit 10 - WC - Write-Combining memory type supported. */
1420	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1421	/** Bit 11 - SMRR - System Management Range Register supported. */
1422	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1423	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1424	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1425
1426	/**
1427	* Variable-range MTRR MSR pair.
1428	*/
1429	typedef struct X86MTRRVAR
1430	{
1431	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1432	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1433	} X86MTRRVAR;
1434	#ifndef VBOX_FOR_DTRACE_LIB
1435	AssertCompileSize(X86MTRRVAR, 16);
1436	#endif
1437	/** Pointer to a variable-range MTRR MSR pair. */
1438	typedef X86MTRRVAR *PX86MTRRVAR;
1439	/** Pointer to a const variable-range MTRR MSR pair. */
1440	typedef const X86MTRRVAR *PCX86MTRRVAR;
1441
1442	/** Memory types that can be encoded in MTRRs.
1443	* @{ */
1444	/** Uncacheable. */
1445	#define X86_MTRR_MT_UC 0
1446	/** Write Combining. */
1447	#define X86_MTRR_MT_WC 1
1448	/** Write-through. */
1449	#define X86_MTRR_MT_WT 4
1450	/** Write-protected. */
1451	#define X86_MTRR_MT_WP 5
1452	/** Writeback. */
1453	#define X86_MTRR_MT_WB 6
1454	/** @}*/
1455
1456	/** Architecture capabilities (bugfixes). */
1457	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1458	/** CPU is no subject to meltdown problems. */
1459	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1460	/** CPU has better IBRS and you can leave it on all the time. */
1461	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1462	/** CPU has return stack buffer (RSB) override. */
1463	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1464	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1465	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1466	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1467	/** CPU does not suffer from MDS issues. */
1468	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1469
1470	/** Flush command register. */
1471	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1472	/** Flush the level 1 data cache when this bit is written. */
1473	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1474
1475	/** Cache control/info. */
1476	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1477
1478	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1479	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1480	* R0 SS == CS + 8
1481	* R3 CS == CS + 16
1482	* R3 SS == CS + 24
1483	*/
1484	#define MSR_IA32_SYSENTER_CS 0x174
1485	/** SYSENTER_ESP - the R0 ESP. */
1486	#define MSR_IA32_SYSENTER_ESP 0x175
1487	/** SYSENTER_EIP - the R0 EIP. */
1488	#define MSR_IA32_SYSENTER_EIP 0x176
1489	#endif
1490
1491	/** Machine Check Global Capabilities Register. */
1492	#define MSR_IA32_MCG_CAP 0x179
1493	/** Machine Check Global Status Register. */
1494	#define MSR_IA32_MCG_STATUS 0x17A
1495	/** Machine Check Global Control Register. */
1496	#define MSR_IA32_MCG_CTRL 0x17B
1497
1498	/** Page Attribute Table. */
1499	#define MSR_IA32_CR_PAT 0x277
1500	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1501	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1502	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1503
1504	/** Memory types that can be encoded in the IA32_PAT MSR.
1505	* @{ */
1506	/** Uncacheable. */
1507	#define MSR_IA32_PAT_MT_UC 0
1508	/** Write Combining. */
1509	#define MSR_IA32_PAT_MT_WC 1
1510	/** Reserved value 2. */
1511	#define MSR_IA32_PAT_MT_RSVD_2 2
1512	/** Reserved value 3. */
1513	#define MSR_IA32_PAT_MT_RSVD_3 3
1514	/** Write-through. */
1515	#define MSR_IA32_PAT_MT_WT 4
1516	/** Write-protected. */
1517	#define MSR_IA32_PAT_MT_WP 5
1518	/** Writeback. */
1519	#define MSR_IA32_PAT_MT_WB 6
1520	/** Uncached (UC-). */
1521	#define MSR_IA32_PAT_MT_UCD 7
1522	/** @}*/
1523
1524
1525	/** Performance event select MSRs. (Intel only) */
1526	#define MSR_IA32_PERFEVTSEL0 0x186
1527	#define MSR_IA32_PERFEVTSEL1 0x187
1528	#define MSR_IA32_PERFEVTSEL2 0x188
1529	#define MSR_IA32_PERFEVTSEL3 0x189
1530
1531	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1532	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1533	* holds a ratio that Apple takes for TSC granularity.
1534	*
1535	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1536	#define MSR_FLEX_RATIO 0x194
1537	/** Performance state value and starting with Intel core more.
1538	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1539	#define MSR_IA32_PERF_STATUS 0x198
1540	#define MSR_IA32_PERF_CTL 0x199
1541	#define MSR_IA32_THERM_STATUS 0x19c
1542
1543	/** Offcore response event select registers. */
1544	#define MSR_OFFCORE_RSP_0 0x1a6
1545	#define MSR_OFFCORE_RSP_1 0x1a7
1546
1547	/** Enable misc. processor features (R/W). */
1548	#define MSR_IA32_MISC_ENABLE 0x1A0
1549	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1550	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1551	/** Automatic Thermal Control Circuit Enable (R/W). */
1552	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1553	/** Performance Monitoring Available (R). */
1554	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1555	/** Branch Trace Storage Unavailable (R/O). */
1556	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1557	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1558	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1559	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1560	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1561	/** If MONITOR/MWAIT is supported (R/W). */
1562	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1563	/** Limit CPUID Maxval to 3 leafs (R/W). */
1564	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1565	/** When set to 1, xTPR messages are disabled (R/W). */
1566	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1567	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1568	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1569
1570	/** Trace/Profile Resource Control (R/W) */
1571	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1572	/** Last branch record. */
1573	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1574	/** Branch trace flag (single step on branches). */
1575	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1576	/** Performance monitoring pin control (AMD only). */
1577	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1578	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1579	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1580	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1581	/** Trace message enable (Intel only). */
1582	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1583	/** Branch trace store (Intel only). */
1584	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1585	/** Branch trace interrupt (Intel only). */
1586	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1587	/** Branch trace off in privileged code (Intel only). */
1588	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1589	/** Branch trace off in user code (Intel only). */
1590	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1591	/** Freeze LBR on PMI flag (Intel only). */
1592	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1593	/** Freeze PERFMON on PMI flag (Intel only). */
1594	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1595	/** Freeze while SMM enabled (Intel only). */
1596	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1597	/** Advanced debugging of RTM regions (Intel only). */
1598	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1599	/** Debug control MSR valid bits (Intel only). */
1600	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1601	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1602	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1603	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1604	\| MSR_IA32_DEBUGCTL_RTM)
1605
1606	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1607	* @{ */
1608	#define MSR_P4_LASTBRANCH_0 0x1db
1609	#define MSR_P4_LASTBRANCH_1 0x1dc
1610	#define MSR_P4_LASTBRANCH_2 0x1dd
1611	#define MSR_P4_LASTBRANCH_3 0x1de
1612
1613	/** LBR Top-of-stack MSR (index to most recent record). */
1614	#define MSR_P4_LASTBRANCH_TOS 0x1da
1615	/** @} */
1616
1617	/** @name Last branch registers for Core 2 and related Xeons.
1618	* @{ */
1619	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1620	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1621	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1622	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1623
1624	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1625	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1626	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1627	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1628
1629	/** LBR Top-of-stack MSR (index to most recent record). */
1630	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1631	/** @} */
1632
1633	/** @name Last branch registers.
1634	* @{ */
1635	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1636	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1637	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1638	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1639	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1640	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1641	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1642	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1643	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1644	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1645	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1646	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1647	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1648	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1649	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1650	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1651	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1652	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1653	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1654	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1655	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1656	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1657	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1658	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1659	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1660	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1661	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1662	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1663	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1664	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1665	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1666	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1667
1668	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1669	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1670	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1671	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1672	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1673	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1674	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1675	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1676	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1677	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1678	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1679	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1680	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1681	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1682	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1683	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1684	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1685	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1686	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1687	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1688	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1689	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1690	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1691	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1692	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1693	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1694	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1695	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1696	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1697	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1698	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1699	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1700
1701	#define MSR_LASTBRANCH_0_INFO 0xdc0
1702	#define MSR_LASTBRANCH_1_INFO 0xdc1
1703	#define MSR_LASTBRANCH_2_INFO 0xdc2
1704	#define MSR_LASTBRANCH_3_INFO 0xdc3
1705	#define MSR_LASTBRANCH_4_INFO 0xdc4
1706	#define MSR_LASTBRANCH_5_INFO 0xdc5
1707	#define MSR_LASTBRANCH_6_INFO 0xdc6
1708	#define MSR_LASTBRANCH_7_INFO 0xdc7
1709	#define MSR_LASTBRANCH_8_INFO 0xdc8
1710	#define MSR_LASTBRANCH_9_INFO 0xdc9
1711	#define MSR_LASTBRANCH_10_INFO 0xdca
1712	#define MSR_LASTBRANCH_11_INFO 0xdcb
1713	#define MSR_LASTBRANCH_12_INFO 0xdcc
1714	#define MSR_LASTBRANCH_13_INFO 0xdcd
1715	#define MSR_LASTBRANCH_14_INFO 0xdce
1716	#define MSR_LASTBRANCH_15_INFO 0xdcf
1717	#define MSR_LASTBRANCH_16_INFO 0xdd0
1718	#define MSR_LASTBRANCH_17_INFO 0xdd1
1719	#define MSR_LASTBRANCH_18_INFO 0xdd2
1720	#define MSR_LASTBRANCH_19_INFO 0xdd3
1721	#define MSR_LASTBRANCH_20_INFO 0xdd4
1722	#define MSR_LASTBRANCH_21_INFO 0xdd5
1723	#define MSR_LASTBRANCH_22_INFO 0xdd6
1724	#define MSR_LASTBRANCH_23_INFO 0xdd7
1725	#define MSR_LASTBRANCH_24_INFO 0xdd8
1726	#define MSR_LASTBRANCH_25_INFO 0xdd9
1727	#define MSR_LASTBRANCH_26_INFO 0xdda
1728	#define MSR_LASTBRANCH_27_INFO 0xddb
1729	#define MSR_LASTBRANCH_28_INFO 0xddc
1730	#define MSR_LASTBRANCH_29_INFO 0xddd
1731	#define MSR_LASTBRANCH_30_INFO 0xdde
1732	#define MSR_LASTBRANCH_31_INFO 0xddf
1733
1734	/** LBR branch tracking selection MSR. */
1735	#define MSR_LASTBRANCH_SELECT 0x1c8
1736	/** LBR Top-of-stack MSR (index to most recent record). */
1737	#define MSR_LASTBRANCH_TOS 0x1c9
1738	/** @} */
1739
1740	/** @name Last event record registers.
1741	* @{ */
1742	/** Last event record source IP register. */
1743	#define MSR_LER_FROM_IP 0x1dd
1744	/** Last event record destination IP register. */
1745	#define MSR_LER_TO_IP 0x1de
1746	/** @} */
1747
1748	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1749	#define MSR_IA32_TSX_CTRL 0x122
1750
1751	/** Variable range MTRRs.
1752	* @{ */
1753	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1754	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1755	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1756	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1757	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1758	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1759	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1760	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1761	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1762	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1763	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1764	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1765	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1766	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1767	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1768	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1769	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1770	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1771	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1772	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1773	/** @} */
1774
1775	/** Fixed range MTRRs.
1776	* @{ */
1777	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1778	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1779	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1780	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1781	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1782	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1783	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1784	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1785	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1786	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1787	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1788	/** @} */
1789
1790	/** MTRR Default Type.
1791	* @{ */
1792	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1793	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1794	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1795	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1796	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1797	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1798	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1799	/** @} */
1800
1801	/** Variable-range MTRR physical mask valid. */
1802	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1803
1804	/** Global performance counter control facilities (Intel only). */
1805	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1806	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1807	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1808
1809	/** Precise Event Based sampling (Intel only). */
1810	#define MSR_IA32_PEBS_ENABLE 0x3F1
1811
1812	#define MSR_IA32_MC0_CTL 0x400
1813	#define MSR_IA32_MC0_STATUS 0x401
1814
1815	/** Basic VMX information. */
1816	#define MSR_IA32_VMX_BASIC 0x480
1817	/** Allowed settings for pin-based VM execution controls. */
1818	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1819	/** Allowed settings for proc-based VM execution controls. */
1820	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1821	/** Allowed settings for the VM-exit controls. */
1822	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1823	/** Allowed settings for the VM-entry controls. */
1824	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1825	/** Misc VMX info. */
1826	#define MSR_IA32_VMX_MISC 0x485
1827	/** Fixed cleared bits in CR0. */
1828	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1829	/** Fixed set bits in CR0. */
1830	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1831	/** Fixed cleared bits in CR4. */
1832	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1833	/** Fixed set bits in CR4. */
1834	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1835	/** Information for enumerating fields in the VMCS. */
1836	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1837	/** Allowed settings for secondary processor-based VM-execution controls. */
1838	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1839	/** EPT capabilities. */
1840	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1841	/** Allowed settings of all pin-based VM execution controls. */
1842	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1843	/** Allowed settings of all proc-based VM execution controls. */
1844	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1845	/** Allowed settings of all VMX exit controls. */
1846	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1847	/** Allowed settings of all VMX entry controls. */
1848	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1849	/** Allowed settings for the VM-function controls. */
1850	#define MSR_IA32_VMX_VMFUNC 0x491
1851	/** Tertiary processor-based VM execution controls. */
1852	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1853	/** Secondary VM-exit controls. */
1854	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
1855
1856	/** Intel PT - Enable and control for trace packet generation. */
1857	#define MSR_IA32_RTIT_CTL 0x570
1858
1859	/** DS Save Area (R/W). */
1860	#define MSR_IA32_DS_AREA 0x600
1861	/** Running Average Power Limit (RAPL) power units. */
1862	#define MSR_RAPL_POWER_UNIT 0x606
1863	/** Package C3 Interrupt Response Limit. */
1864	#define MSR_PKGC3_IRTL 0x60a
1865	/** Package C6/C7S Interrupt Response Limit 1. */
1866	#define MSR_PKGC_IRTL1 0x60b
1867	/** Package C6/C7S Interrupt Response Limit 2. */
1868	#define MSR_PKGC_IRTL2 0x60c
1869	/** Package C2 Residency Counter. */
1870	#define MSR_PKG_C2_RESIDENCY 0x60d
1871	/** PKG RAPL Power Limit Control. */
1872	#define MSR_PKG_POWER_LIMIT 0x610
1873	/** PKG Energy Status. */
1874	#define MSR_PKG_ENERGY_STATUS 0x611
1875	/** PKG Perf Status. */
1876	#define MSR_PKG_PERF_STATUS 0x613
1877	/** PKG RAPL Parameters. */
1878	#define MSR_PKG_POWER_INFO 0x614
1879	/** DRAM RAPL Power Limit Control. */
1880	#define MSR_DRAM_POWER_LIMIT 0x618
1881	/** DRAM Energy Status. */
1882	#define MSR_DRAM_ENERGY_STATUS 0x619
1883	/** DRAM Performance Throttling Status. */
1884	#define MSR_DRAM_PERF_STATUS 0x61b
1885	/** DRAM RAPL Parameters. */
1886	#define MSR_DRAM_POWER_INFO 0x61c
1887	/** Package C10 Residency Counter. */
1888	#define MSR_PKG_C10_RESIDENCY 0x632
1889	/** PP0 Energy Status. */
1890	#define MSR_PP0_ENERGY_STATUS 0x639
1891	/** PP1 Energy Status. */
1892	#define MSR_PP1_ENERGY_STATUS 0x641
1893	/** Turbo Activation Ratio. */
1894	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1895	/** Core Performance Limit Reasons. */
1896	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1897
1898	/** Userspace Control flow Enforcement Technology setting. */
1899	#define MSR_IA32_U_CET 0x6a0
1900	/** Supervisor space Control flow Enforcement Technology setting. */
1901	#define MSR_IA32_S_CET 0x6a2
1902	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
1903	* @{ */
1904	/** Enables the Shadow stack. */
1905	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
1906	/** Enables WRSS{D,Q}W instructions. */
1907	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
1908	/** Enables indirect branch tracking. */
1909	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
1910	/** Enable legacy compatibility treatment for indirect branch tracking. */
1911	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
1912	/** Enables the use of no-track prefix for indirect branch tracking. */
1913	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
1914	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
1915	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
1916	/** Suppresses indirect branch tracking. */
1917	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
1918	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
1919	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
1920	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
1921	* on a ENDBRANCH instruction. */
1922	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
1923	/** @} */
1924
1925	/** X2APIC MSR range start. */
1926	#define MSR_IA32_X2APIC_START 0x800
1927	/** X2APIC MSR - APIC ID Register. */
1928	#define MSR_IA32_X2APIC_ID 0x802
1929	/** X2APIC MSR - APIC Version Register. */
1930	#define MSR_IA32_X2APIC_VERSION 0x803
1931	/** X2APIC MSR - Task Priority Register. */
1932	#define MSR_IA32_X2APIC_TPR 0x808
1933	/** X2APIC MSR - Processor Priority register. */
1934	#define MSR_IA32_X2APIC_PPR 0x80A
1935	/** X2APIC MSR - End Of Interrupt register. */
1936	#define MSR_IA32_X2APIC_EOI 0x80B
1937	/** X2APIC MSR - Logical Destination Register. */
1938	#define MSR_IA32_X2APIC_LDR 0x80D
1939	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1940	#define MSR_IA32_X2APIC_SVR 0x80F
1941	/** X2APIC MSR - In-service Register (bits 31:0). */
1942	#define MSR_IA32_X2APIC_ISR0 0x810
1943	/** X2APIC MSR - In-service Register (bits 63:32). */
1944	#define MSR_IA32_X2APIC_ISR1 0x811
1945	/** X2APIC MSR - In-service Register (bits 95:64). */
1946	#define MSR_IA32_X2APIC_ISR2 0x812
1947	/** X2APIC MSR - In-service Register (bits 127:96). */
1948	#define MSR_IA32_X2APIC_ISR3 0x813
1949	/** X2APIC MSR - In-service Register (bits 159:128). */
1950	#define MSR_IA32_X2APIC_ISR4 0x814
1951	/** X2APIC MSR - In-service Register (bits 191:160). */
1952	#define MSR_IA32_X2APIC_ISR5 0x815
1953	/** X2APIC MSR - In-service Register (bits 223:192). */
1954	#define MSR_IA32_X2APIC_ISR6 0x816
1955	/** X2APIC MSR - In-service Register (bits 255:224). */
1956	#define MSR_IA32_X2APIC_ISR7 0x817
1957	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1958	#define MSR_IA32_X2APIC_TMR0 0x818
1959	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1960	#define MSR_IA32_X2APIC_TMR1 0x819
1961	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1962	#define MSR_IA32_X2APIC_TMR2 0x81A
1963	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1964	#define MSR_IA32_X2APIC_TMR3 0x81B
1965	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1966	#define MSR_IA32_X2APIC_TMR4 0x81C
1967	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1968	#define MSR_IA32_X2APIC_TMR5 0x81D
1969	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1970	#define MSR_IA32_X2APIC_TMR6 0x81E
1971	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1972	#define MSR_IA32_X2APIC_TMR7 0x81F
1973	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1974	#define MSR_IA32_X2APIC_IRR0 0x820
1975	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1976	#define MSR_IA32_X2APIC_IRR1 0x821
1977	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1978	#define MSR_IA32_X2APIC_IRR2 0x822
1979	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1980	#define MSR_IA32_X2APIC_IRR3 0x823
1981	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1982	#define MSR_IA32_X2APIC_IRR4 0x824
1983	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1984	#define MSR_IA32_X2APIC_IRR5 0x825
1985	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1986	#define MSR_IA32_X2APIC_IRR6 0x826
1987	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1988	#define MSR_IA32_X2APIC_IRR7 0x827
1989	/** X2APIC MSR - Error Status Register. */
1990	#define MSR_IA32_X2APIC_ESR 0x828
1991	/** X2APIC MSR - LVT CMCI Register. */
1992	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1993	/** X2APIC MSR - Interrupt Command Register. */
1994	#define MSR_IA32_X2APIC_ICR 0x830
1995	/** X2APIC MSR - LVT Timer Register. */
1996	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1997	/** X2APIC MSR - LVT Thermal Sensor Register. */
1998	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1999	/** X2APIC MSR - LVT Performance Counter Register. */
2000	#define MSR_IA32_X2APIC_LVT_PERF 0x834
2001	/** X2APIC MSR - LVT LINT0 Register. */
2002	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2003	/** X2APIC MSR - LVT LINT1 Register. */
2004	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2005	/** X2APIC MSR - LVT Error Register . */
2006	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2007	/** X2APIC MSR - Timer Initial Count Register. */
2008	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2009	/** X2APIC MSR - Timer Current Count Register. */
2010	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2011	/** X2APIC MSR - Timer Divide Configuration Register. */
2012	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2013	/** X2APIC MSR - Self IPI. */
2014	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2015	/** X2APIC MSR range end. */
2016	#define MSR_IA32_X2APIC_END 0x8FF
2017	/** X2APIC MSR - LVT start range. */
2018	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2019	/** X2APIC MSR - LVT end range (inclusive). */
2020	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2021
2022	/** K6 EFER - Extended Feature Enable Register. */
2023	#define MSR_K6_EFER UINT32_C(0xc0000080)
2024	/** @todo document EFER */
2025	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2026	#define MSR_K6_EFER_SCE RT_BIT_32(0)
2027	/** Bit 8 - LME - Long mode enabled. (R/W) */
2028	#define MSR_K6_EFER_LME RT_BIT_32(8)
2029	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
2030	/** Bit 10 - LMA - Long mode active. (R) */
2031	#define MSR_K6_EFER_LMA RT_BIT_32(10)
2032	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
2033	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2034	#define MSR_K6_EFER_NXE RT_BIT_32(11)
2035	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
2036	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2037	#define MSR_K6_EFER_SVME RT_BIT_32(12)
2038	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2039	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2040	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
2041	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2042	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2043	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2044	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2045	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2046
2047	/** K6 STAR - SYSCALL/RET targets. */
2048	#define MSR_K6_STAR UINT32_C(0xc0000081)
2049	/** Shift value for getting the SYSRET CS and SS value. */
2050	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2051	/** Shift value for getting the SYSCALL CS and SS value. */
2052	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2053	/** Selector mask for use after shifting. */
2054	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2055	/** The mask which give the SYSCALL EIP. */
2056	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2057	/** K6 WHCR - Write Handling Control Register. */
2058	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2059	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2060	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2061	/** K6 PSOR - Processor State Observability Register. */
2062	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2063	/** K6 PFIR - Page Flush/Invalidate Register. */
2064	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2065
2066	/** Performance counter MSRs. (AMD only) */
2067	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2068	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2069	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2070	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2071	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2072	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2073	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2074	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2075
2076	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2077	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2078	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2079	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2080	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2081	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2082	/** K8 FS.base - The 64-bit base FS register. */
2083	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2084	/** K8 GS.base - The 64-bit base GS register. */
2085	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2086	/** K8 KernelGSbase - Used with SWAPGS. */
2087	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2088	/** K8 TSC_AUX - Used with RDTSCP. */
2089	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2090	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2091	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2092	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2093	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2094	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2095	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2096	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2097	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2098
2099	/** SMM MSRs. */
2100	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2101	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2102	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2103
2104	/** North bridge config? See BIOS & Kernel dev guides for
2105	* details. */
2106	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2107
2108	/** Hypertransport interrupt pending register.
2109	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2110	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2111
2112	/** SVM Control. */
2113	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2114	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2115	* features. */
2116	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2117	/** If set, non-intercepted INIT signals are converted to \#SX
2118	* exceptions. */
2119	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2120	/** Disables A20 masking. */
2121	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2122	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2123	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2124	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2125	* clear, EFER.SVME can be written normally. */
2126	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2127
2128	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2129	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2130	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2131	* host state during world switch. */
2132	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2133
2134	/** Virtualized speculation control for AMD processors.
2135	*
2136	* Unified interface among different CPU generations.
2137	* The VMM will set any architectural MSRs based on the CPU.
2138	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2139	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2140	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2141	/** Speculative Store Bypass Disable. */
2142	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2143
2144	/** @} */
2145
2146
2147	/** @name Page Table / Directory / Directory Pointers / L4.
2148	* @{
2149	*/
2150
2151	/** Page table/directory entry as an unsigned integer. */
2152	typedef uint32_t X86PGUINT;
2153	/** Pointer to a page table/directory table entry as an unsigned integer. */
2154	typedef X86PGUINT *PX86PGUINT;
2155	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2156	typedef X86PGUINT const *PCX86PGUINT;
2157
2158	/** Number of entries in a 32-bit PT/PD. */
2159	#define X86_PG_ENTRIES 1024
2160
2161
2162	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2163	typedef uint64_t X86PGPAEUINT;
2164	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2165	typedef X86PGPAEUINT *PX86PGPAEUINT;
2166	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2167	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2168
2169	/** Number of entries in a PAE PT/PD. */
2170	#define X86_PG_PAE_ENTRIES 512
2171	/** Number of entries in a PAE PDPT. */
2172	#define X86_PG_PAE_PDPE_ENTRIES 4
2173
2174	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2175	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2176	/** Number of entries in an AMD64 PDPT.
2177	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2178	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2179
2180	/** The size of a default page. */
2181	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2182	/** The page shift of a default page. */
2183	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2184	/** The default page offset mask. */
2185	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2186	/** The default page base mask for virtual addresses. */
2187	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2188	/** The default page base mask for virtual addresses - 32bit version. */
2189	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2190
2191	/** The size of a 4KB page. */
2192	#define X86_PAGE_4K_SIZE _4K
2193	/** The page shift of a 4KB page. */
2194	#define X86_PAGE_4K_SHIFT 12
2195	/** The 4KB page offset mask. */
2196	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2197	/** The 4KB page base mask for virtual addresses. */
2198	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2199	/** The 4KB page base mask for virtual addresses - 32bit version. */
2200	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2201
2202	/** The size of a 2MB page. */
2203	#define X86_PAGE_2M_SIZE _2M
2204	/** The page shift of a 2MB page. */
2205	#define X86_PAGE_2M_SHIFT 21
2206	/** The 2MB page offset mask. */
2207	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2208	/** The 2MB page base mask for virtual addresses. */
2209	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2210	/** The 2MB page base mask for virtual addresses - 32bit version. */
2211	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2212
2213	/** The size of a 4MB page. */
2214	#define X86_PAGE_4M_SIZE _4M
2215	/** The page shift of a 4MB page. */
2216	#define X86_PAGE_4M_SHIFT 22
2217	/** The 4MB page offset mask. */
2218	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2219	/** The 4MB page base mask for virtual addresses. */
2220	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2221	/** The 4MB page base mask for virtual addresses - 32bit version. */
2222	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2223
2224	/** The size of a 1GB page. */
2225	#define X86_PAGE_1G_SIZE _1G
2226	/** The page shift of a 1GB page. */
2227	#define X86_PAGE_1G_SHIFT 30
2228	/** The 1GB page offset mask. */
2229	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2230	/** The 1GB page base mask for virtual addresses. */
2231	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2232
2233	/**
2234	* Check if the given address is canonical.
2235	*/
2236	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2237
2238	/**
2239	* Gets the page base mask given the page shift.
2240	*/
2241	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2242
2243	/**
2244	* Gets the page offset mask given the page shift.
2245	*/
2246	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2247
2248
2249	/** @name Page Table Entry
2250	* @{
2251	*/
2252	/** Bit 0 - P - Present bit. */
2253	#define X86_PTE_BIT_P 0
2254	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2255	#define X86_PTE_BIT_RW 1
2256	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2257	#define X86_PTE_BIT_US 2
2258	/** Bit 3 - PWT - Page level write thru bit. */
2259	#define X86_PTE_BIT_PWT 3
2260	/** Bit 4 - PCD - Page level cache disable bit. */
2261	#define X86_PTE_BIT_PCD 4
2262	/** Bit 5 - A - Access bit. */
2263	#define X86_PTE_BIT_A 5
2264	/** Bit 6 - D - Dirty bit. */
2265	#define X86_PTE_BIT_D 6
2266	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2267	#define X86_PTE_BIT_PAT 7
2268	/** Bit 8 - G - Global flag. */
2269	#define X86_PTE_BIT_G 8
2270	/** Bits 63 - NX - PAE/LM - No execution flag. */
2271	#define X86_PTE_PAE_BIT_NX 63
2272
2273	/** Bit 0 - P - Present bit mask. */
2274	#define X86_PTE_P RT_BIT_32(0)
2275	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2276	#define X86_PTE_RW RT_BIT_32(1)
2277	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2278	#define X86_PTE_US RT_BIT_32(2)
2279	/** Bit 3 - PWT - Page level write thru bit mask. */
2280	#define X86_PTE_PWT RT_BIT_32(3)
2281	/** Bit 4 - PCD - Page level cache disable bit mask. */
2282	#define X86_PTE_PCD RT_BIT_32(4)
2283	/** Bit 5 - A - Access bit mask. */
2284	#define X86_PTE_A RT_BIT_32(5)
2285	/** Bit 6 - D - Dirty bit mask. */
2286	#define X86_PTE_D RT_BIT_32(6)
2287	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2288	#define X86_PTE_PAT RT_BIT_32(7)
2289	/** Bit 8 - G - Global bit mask. */
2290	#define X86_PTE_G RT_BIT_32(8)
2291
2292	/** Bits 9-11 - - Available for use to system software. */
2293	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2294	/** Bits 12-31 - - Physical Page number of the next level. */
2295	#define X86_PTE_PG_MASK ( 0xfffff000 )
2296
2297	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2298	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2299	/** Bits 63 - NX - PAE/LM - No execution flag. */
2300	#define X86_PTE_PAE_NX RT_BIT_64(63)
2301	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2302	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2303	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2304	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2305	/** No bits - - LM - MBZ bits when NX is active. */
2306	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2307	/** Bits 63 - - LM - MBZ bits when no NX. */
2308	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2309
2310	/**
2311	* Page table entry.
2312	*/
2313	typedef struct X86PTEBITS
2314	{
2315	/** Flags whether(=1) or not the page is present. */
2316	uint32_t u1Present : 1;
2317	/** Read(=0) / Write(=1) flag. */
2318	uint32_t u1Write : 1;
2319	/** User(=1) / Supervisor (=0) flag. */
2320	uint32_t u1User : 1;
2321	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2322	uint32_t u1WriteThru : 1;
2323	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2324	uint32_t u1CacheDisable : 1;
2325	/** Accessed flag.
2326	* Indicates that the page have been read or written to. */
2327	uint32_t u1Accessed : 1;
2328	/** Dirty flag.
2329	* Indicates that the page has been written to. */
2330	uint32_t u1Dirty : 1;
2331	/** Reserved / If PAT enabled, bit 2 of the index. */
2332	uint32_t u1PAT : 1;
2333	/** Global flag. (Ignored in all but final level.) */
2334	uint32_t u1Global : 1;
2335	/** Available for use to system software. */
2336	uint32_t u3Available : 3;
2337	/** Physical Page number of the next level. */
2338	uint32_t u20PageNo : 20;
2339	} X86PTEBITS;
2340	#ifndef VBOX_FOR_DTRACE_LIB
2341	AssertCompileSize(X86PTEBITS, 4);
2342	#endif
2343	/** Pointer to a page table entry. */
2344	typedef X86PTEBITS *PX86PTEBITS;
2345	/** Pointer to a const page table entry. */
2346	typedef const X86PTEBITS *PCX86PTEBITS;
2347
2348	/**
2349	* Page table entry.
2350	*/
2351	typedef union X86PTE
2352	{
2353	/** Unsigned integer view */
2354	X86PGUINT u;
2355	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2356	/** Bit field view. */
2357	X86PTEBITS n;
2358	#endif
2359	/** 32-bit view. */
2360	uint32_t au32[1];
2361	/** 16-bit view. */
2362	uint16_t au16[2];
2363	/** 8-bit view. */
2364	uint8_t au8[4];
2365	} X86PTE;
2366	#ifndef VBOX_FOR_DTRACE_LIB
2367	AssertCompileSize(X86PTE, 4);
2368	#endif
2369	/** Pointer to a page table entry. */
2370	typedef X86PTE *PX86PTE;
2371	/** Pointer to a const page table entry. */
2372	typedef const X86PTE *PCX86PTE;
2373
2374
2375	/**
2376	* PAE page table entry.
2377	*/
2378	typedef struct X86PTEPAEBITS
2379	{
2380	/** Flags whether(=1) or not the page is present. */
2381	uint32_t u1Present : 1;
2382	/** Read(=0) / Write(=1) flag. */
2383	uint32_t u1Write : 1;
2384	/** User(=1) / Supervisor(=0) flag. */
2385	uint32_t u1User : 1;
2386	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2387	uint32_t u1WriteThru : 1;
2388	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2389	uint32_t u1CacheDisable : 1;
2390	/** Accessed flag.
2391	* Indicates that the page have been read or written to. */
2392	uint32_t u1Accessed : 1;
2393	/** Dirty flag.
2394	* Indicates that the page has been written to. */
2395	uint32_t u1Dirty : 1;
2396	/** Reserved / If PAT enabled, bit 2 of the index. */
2397	uint32_t u1PAT : 1;
2398	/** Global flag. (Ignored in all but final level.) */
2399	uint32_t u1Global : 1;
2400	/** Available for use to system software. */
2401	uint32_t u3Available : 3;
2402	/** Physical Page number of the next level - Low Part. Don't use this. */
2403	uint32_t u20PageNoLow : 20;
2404	/** Physical Page number of the next level - High Part. Don't use this. */
2405	uint32_t u20PageNoHigh : 20;
2406	/** MBZ bits */
2407	uint32_t u11Reserved : 11;
2408	/** No Execute flag. */
2409	uint32_t u1NoExecute : 1;
2410	} X86PTEPAEBITS;
2411	#ifndef VBOX_FOR_DTRACE_LIB
2412	AssertCompileSize(X86PTEPAEBITS, 8);
2413	#endif
2414	/** Pointer to a page table entry. */
2415	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2416	/** Pointer to a page table entry. */
2417	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2418
2419	/**
2420	* PAE Page table entry.
2421	*/
2422	typedef union X86PTEPAE
2423	{
2424	/** Unsigned integer view */
2425	X86PGPAEUINT u;
2426	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2427	/** Bit field view. */
2428	X86PTEPAEBITS n;
2429	#endif
2430	/** 32-bit view. */
2431	uint32_t au32[2];
2432	/** 16-bit view. */
2433	uint16_t au16[4];
2434	/** 8-bit view. */
2435	uint8_t au8[8];
2436	} X86PTEPAE;
2437	#ifndef VBOX_FOR_DTRACE_LIB
2438	AssertCompileSize(X86PTEPAE, 8);
2439	#endif
2440	/** Pointer to a PAE page table entry. */
2441	typedef X86PTEPAE *PX86PTEPAE;
2442	/** Pointer to a const PAE page table entry. */
2443	typedef const X86PTEPAE *PCX86PTEPAE;
2444	/** @} */
2445
2446	/**
2447	* Page table.
2448	*/
2449	typedef struct X86PT
2450	{
2451	/** PTE Array. */
2452	X86PTE a[X86_PG_ENTRIES];
2453	} X86PT;
2454	#ifndef VBOX_FOR_DTRACE_LIB
2455	AssertCompileSize(X86PT, 4096);
2456	#endif
2457	/** Pointer to a page table. */
2458	typedef X86PT *PX86PT;
2459	/** Pointer to a const page table. */
2460	typedef const X86PT *PCX86PT;
2461
2462	/** The page shift to get the PT index. */
2463	#define X86_PT_SHIFT 12
2464	/** The PT index mask (apply to a shifted page address). */
2465	#define X86_PT_MASK 0x3ff
2466
2467
2468	/**
2469	* Page directory.
2470	*/
2471	typedef struct X86PTPAE
2472	{
2473	/** PTE Array. */
2474	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2475	} X86PTPAE;
2476	#ifndef VBOX_FOR_DTRACE_LIB
2477	AssertCompileSize(X86PTPAE, 4096);
2478	#endif
2479	/** Pointer to a page table. */
2480	typedef X86PTPAE *PX86PTPAE;
2481	/** Pointer to a const page table. */
2482	typedef const X86PTPAE *PCX86PTPAE;
2483
2484	/** The page shift to get the PA PTE index. */
2485	#define X86_PT_PAE_SHIFT 12
2486	/** The PAE PT index mask (apply to a shifted page address). */
2487	#define X86_PT_PAE_MASK 0x1ff
2488
2489
2490	/** @name 4KB Page Directory Entry
2491	* @{
2492	*/
2493	/** Bit 0 - P - Present bit. */
2494	#define X86_PDE_P RT_BIT_32(0)
2495	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2496	#define X86_PDE_RW RT_BIT_32(1)
2497	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2498	#define X86_PDE_US RT_BIT_32(2)
2499	/** Bit 3 - PWT - Page level write thru bit. */
2500	#define X86_PDE_PWT RT_BIT_32(3)
2501	/** Bit 4 - PCD - Page level cache disable bit. */
2502	#define X86_PDE_PCD RT_BIT_32(4)
2503	/** Bit 5 - A - Access bit. */
2504	#define X86_PDE_A RT_BIT_32(5)
2505	/** Bit 7 - PS - Page size attribute.
2506	* Clear mean 4KB pages, set means large pages (2/4MB). */
2507	#define X86_PDE_PS RT_BIT_32(7)
2508	/** Bits 9-11 - - Available for use to system software. */
2509	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2510	/** Bits 12-31 - - Physical Page number of the next level. */
2511	#define X86_PDE_PG_MASK ( 0xfffff000 )
2512
2513	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2514	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2515	/** Bits 63 - NX - PAE/LM - No execution flag. */
2516	#define X86_PDE_PAE_NX RT_BIT_64(63)
2517	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2518	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2519	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2520	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2521	/** Bit 7 - - LM - MBZ bits when NX is active. */
2522	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2523	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2524	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2525
2526	/**
2527	* Page directory entry.
2528	*/
2529	typedef struct X86PDEBITS
2530	{
2531	/** Flags whether(=1) or not the page is present. */
2532	uint32_t u1Present : 1;
2533	/** Read(=0) / Write(=1) flag. */
2534	uint32_t u1Write : 1;
2535	/** User(=1) / Supervisor (=0) flag. */
2536	uint32_t u1User : 1;
2537	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2538	uint32_t u1WriteThru : 1;
2539	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2540	uint32_t u1CacheDisable : 1;
2541	/** Accessed flag.
2542	* Indicates that the page has been read or written to. */
2543	uint32_t u1Accessed : 1;
2544	/** Reserved / Ignored (dirty bit). */
2545	uint32_t u1Reserved0 : 1;
2546	/** Size bit if PSE is enabled - in any event it's 0. */
2547	uint32_t u1Size : 1;
2548	/** Reserved / Ignored (global bit). */
2549	uint32_t u1Reserved1 : 1;
2550	/** Available for use to system software. */
2551	uint32_t u3Available : 3;
2552	/** Physical Page number of the next level. */
2553	uint32_t u20PageNo : 20;
2554	} X86PDEBITS;
2555	#ifndef VBOX_FOR_DTRACE_LIB
2556	AssertCompileSize(X86PDEBITS, 4);
2557	#endif
2558	/** Pointer to a page directory entry. */
2559	typedef X86PDEBITS *PX86PDEBITS;
2560	/** Pointer to a const page directory entry. */
2561	typedef const X86PDEBITS *PCX86PDEBITS;
2562
2563
2564	/**
2565	* PAE page directory entry.
2566	*/
2567	typedef struct X86PDEPAEBITS
2568	{
2569	/** Flags whether(=1) or not the page is present. */
2570	uint32_t u1Present : 1;
2571	/** Read(=0) / Write(=1) flag. */
2572	uint32_t u1Write : 1;
2573	/** User(=1) / Supervisor (=0) flag. */
2574	uint32_t u1User : 1;
2575	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2576	uint32_t u1WriteThru : 1;
2577	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2578	uint32_t u1CacheDisable : 1;
2579	/** Accessed flag.
2580	* Indicates that the page has been read or written to. */
2581	uint32_t u1Accessed : 1;
2582	/** Reserved / Ignored (dirty bit). */
2583	uint32_t u1Reserved0 : 1;
2584	/** Size bit if PSE is enabled - in any event it's 0. */
2585	uint32_t u1Size : 1;
2586	/** Reserved / Ignored (global bit). / */
2587	uint32_t u1Reserved1 : 1;
2588	/** Available for use to system software. */
2589	uint32_t u3Available : 3;
2590	/** Physical Page number of the next level - Low Part. Don't use! */
2591	uint32_t u20PageNoLow : 20;
2592	/** Physical Page number of the next level - High Part. Don't use! */
2593	uint32_t u20PageNoHigh : 20;
2594	/** MBZ bits */
2595	uint32_t u11Reserved : 11;
2596	/** No Execute flag. */
2597	uint32_t u1NoExecute : 1;
2598	} X86PDEPAEBITS;
2599	#ifndef VBOX_FOR_DTRACE_LIB
2600	AssertCompileSize(X86PDEPAEBITS, 8);
2601	#endif
2602	/** Pointer to a page directory entry. */
2603	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2604	/** Pointer to a const page directory entry. */
2605	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2606
2607	/** @} */
2608
2609
2610	/** @name 2/4MB Page Directory Entry
2611	* @{
2612	*/
2613	/** Bit 0 - P - Present bit. */
2614	#define X86_PDE4M_P RT_BIT_32(0)
2615	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2616	#define X86_PDE4M_RW RT_BIT_32(1)
2617	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2618	#define X86_PDE4M_US RT_BIT_32(2)
2619	/** Bit 3 - PWT - Page level write thru bit. */
2620	#define X86_PDE4M_PWT RT_BIT_32(3)
2621	/** Bit 4 - PCD - Page level cache disable bit. */
2622	#define X86_PDE4M_PCD RT_BIT_32(4)
2623	/** Bit 5 - A - Access bit. */
2624	#define X86_PDE4M_A RT_BIT_32(5)
2625	/** Bit 6 - D - Dirty bit. */
2626	#define X86_PDE4M_D RT_BIT_32(6)
2627	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2628	#define X86_PDE4M_PS RT_BIT_32(7)
2629	/** Bit 8 - G - Global flag. */
2630	#define X86_PDE4M_G RT_BIT_32(8)
2631	/** Bits 9-11 - AVL - Available for use to system software. */
2632	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2633	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2634	#define X86_PDE4M_PAT RT_BIT_32(12)
2635	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2636	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2637	/** Bits 22-31 - - Physical Page number. */
2638	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2639	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2640	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2641	/** The number of bits to the high part of the page number. */
2642	#define X86_PDE4M_PG_HIGH_SHIFT 19
2643	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2644	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2645
2646	/** Bits 21-51 - - PAE/LM - Physical Page number.
2647	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2648	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2649	/** Bits 63 - NX - PAE/LM - No execution flag. */
2650	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2651	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2652	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2653	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2654	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2655	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2656	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2657	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2658	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2659
2660	/**
2661	* 4MB page directory entry.
2662	*/
2663	typedef struct X86PDE4MBITS
2664	{
2665	/** Flags whether(=1) or not the page is present. */
2666	uint32_t u1Present : 1;
2667	/** Read(=0) / Write(=1) flag. */
2668	uint32_t u1Write : 1;
2669	/** User(=1) / Supervisor (=0) flag. */
2670	uint32_t u1User : 1;
2671	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2672	uint32_t u1WriteThru : 1;
2673	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2674	uint32_t u1CacheDisable : 1;
2675	/** Accessed flag.
2676	* Indicates that the page have been read or written to. */
2677	uint32_t u1Accessed : 1;
2678	/** Dirty flag.
2679	* Indicates that the page has been written to. */
2680	uint32_t u1Dirty : 1;
2681	/** Page size flag - always 1 for 4MB entries. */
2682	uint32_t u1Size : 1;
2683	/** Global flag. */
2684	uint32_t u1Global : 1;
2685	/** Available for use to system software. */
2686	uint32_t u3Available : 3;
2687	/** Reserved / If PAT enabled, bit 2 of the index. */
2688	uint32_t u1PAT : 1;
2689	/** Bits 32-39 of the page number on AMD64.
2690	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2691	uint32_t u8PageNoHigh : 8;
2692	/** Reserved. */
2693	uint32_t u1Reserved : 1;
2694	/** Physical Page number of the page. */
2695	uint32_t u10PageNo : 10;
2696	} X86PDE4MBITS;
2697	#ifndef VBOX_FOR_DTRACE_LIB
2698	AssertCompileSize(X86PDE4MBITS, 4);
2699	#endif
2700	/** Pointer to a page table entry. */
2701	typedef X86PDE4MBITS *PX86PDE4MBITS;
2702	/** Pointer to a const page table entry. */
2703	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2704
2705
2706	/**
2707	* 2MB PAE page directory entry.
2708	*/
2709	typedef struct X86PDE2MPAEBITS
2710	{
2711	/** Flags whether(=1) or not the page is present. */
2712	uint32_t u1Present : 1;
2713	/** Read(=0) / Write(=1) flag. */
2714	uint32_t u1Write : 1;
2715	/** User(=1) / Supervisor(=0) flag. */
2716	uint32_t u1User : 1;
2717	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2718	uint32_t u1WriteThru : 1;
2719	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2720	uint32_t u1CacheDisable : 1;
2721	/** Accessed flag.
2722	* Indicates that the page have been read or written to. */
2723	uint32_t u1Accessed : 1;
2724	/** Dirty flag.
2725	* Indicates that the page has been written to. */
2726	uint32_t u1Dirty : 1;
2727	/** Page size flag - always 1 for 2MB entries. */
2728	uint32_t u1Size : 1;
2729	/** Global flag. */
2730	uint32_t u1Global : 1;
2731	/** Available for use to system software. */
2732	uint32_t u3Available : 3;
2733	/** Reserved / If PAT enabled, bit 2 of the index. */
2734	uint32_t u1PAT : 1;
2735	/** Reserved. */
2736	uint32_t u9Reserved : 9;
2737	/** Physical Page number of the next level - Low part. Don't use! */
2738	uint32_t u10PageNoLow : 10;
2739	/** Physical Page number of the next level - High part. Don't use! */
2740	uint32_t u20PageNoHigh : 20;
2741	/** MBZ bits */
2742	uint32_t u11Reserved : 11;
2743	/** No Execute flag. */
2744	uint32_t u1NoExecute : 1;
2745	} X86PDE2MPAEBITS;
2746	#ifndef VBOX_FOR_DTRACE_LIB
2747	AssertCompileSize(X86PDE2MPAEBITS, 8);
2748	#endif
2749	/** Pointer to a 2MB PAE page table entry. */
2750	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2751	/** Pointer to a 2MB PAE page table entry. */
2752	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2753
2754	/** @} */
2755
2756	/**
2757	* Page directory entry.
2758	*/
2759	typedef union X86PDE
2760	{
2761	/** Unsigned integer view. */
2762	X86PGUINT u;
2763	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2764	/** Normal view. */
2765	X86PDEBITS n;
2766	/** 4MB view (big). */
2767	X86PDE4MBITS b;
2768	#endif
2769	/** 8 bit unsigned integer view. */
2770	uint8_t au8[4];
2771	/** 16 bit unsigned integer view. */
2772	uint16_t au16[2];
2773	/** 32 bit unsigned integer view. */
2774	uint32_t au32[1];
2775	} X86PDE;
2776	#ifndef VBOX_FOR_DTRACE_LIB
2777	AssertCompileSize(X86PDE, 4);
2778	#endif
2779	/** Pointer to a page directory entry. */
2780	typedef X86PDE *PX86PDE;
2781	/** Pointer to a const page directory entry. */
2782	typedef const X86PDE *PCX86PDE;
2783
2784	/**
2785	* PAE page directory entry.
2786	*/
2787	typedef union X86PDEPAE
2788	{
2789	/** Unsigned integer view. */
2790	X86PGPAEUINT u;
2791	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2792	/** Normal view. */
2793	X86PDEPAEBITS n;
2794	/** 2MB page view (big). */
2795	X86PDE2MPAEBITS b;
2796	#endif
2797	/** 8 bit unsigned integer view. */
2798	uint8_t au8[8];
2799	/** 16 bit unsigned integer view. */
2800	uint16_t au16[4];
2801	/** 32 bit unsigned integer view. */
2802	uint32_t au32[2];
2803	} X86PDEPAE;
2804	#ifndef VBOX_FOR_DTRACE_LIB
2805	AssertCompileSize(X86PDEPAE, 8);
2806	#endif
2807	/** Pointer to a page directory entry. */
2808	typedef X86PDEPAE *PX86PDEPAE;
2809	/** Pointer to a const page directory entry. */
2810	typedef const X86PDEPAE *PCX86PDEPAE;
2811
2812	/**
2813	* Page directory.
2814	*/
2815	typedef struct X86PD
2816	{
2817	/** PDE Array. */
2818	X86PDE a[X86_PG_ENTRIES];
2819	} X86PD;
2820	#ifndef VBOX_FOR_DTRACE_LIB
2821	AssertCompileSize(X86PD, 4096);
2822	#endif
2823	/** Pointer to a page directory. */
2824	typedef X86PD *PX86PD;
2825	/** Pointer to a const page directory. */
2826	typedef const X86PD *PCX86PD;
2827
2828	/** The page shift to get the PD index. */
2829	#define X86_PD_SHIFT 22
2830	/** The PD index mask (apply to a shifted page address). */
2831	#define X86_PD_MASK 0x3ff
2832
2833
2834	/**
2835	* PAE page directory.
2836	*/
2837	typedef struct X86PDPAE
2838	{
2839	/** PDE Array. */
2840	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2841	} X86PDPAE;
2842	#ifndef VBOX_FOR_DTRACE_LIB
2843	AssertCompileSize(X86PDPAE, 4096);
2844	#endif
2845	/** Pointer to a PAE page directory. */
2846	typedef X86PDPAE *PX86PDPAE;
2847	/** Pointer to a const PAE page directory. */
2848	typedef const X86PDPAE *PCX86PDPAE;
2849
2850	/** The page shift to get the PAE PD index. */
2851	#define X86_PD_PAE_SHIFT 21
2852	/** The PAE PD index mask (apply to a shifted page address). */
2853	#define X86_PD_PAE_MASK 0x1ff
2854
2855
2856	/** @name Page Directory Pointer Table Entry (PAE)
2857	* @{
2858	*/
2859	/** Bit 0 - P - Present bit. */
2860	#define X86_PDPE_P RT_BIT_32(0)
2861	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2862	#define X86_PDPE_RW RT_BIT_32(1)
2863	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2864	#define X86_PDPE_US RT_BIT_32(2)
2865	/** Bit 3 - PWT - Page level write thru bit. */
2866	#define X86_PDPE_PWT RT_BIT_32(3)
2867	/** Bit 4 - PCD - Page level cache disable bit. */
2868	#define X86_PDPE_PCD RT_BIT_32(4)
2869	/** Bit 5 - A - Access bit. Long Mode only. */
2870	#define X86_PDPE_A RT_BIT_32(5)
2871	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2872	#define X86_PDPE_LM_PS RT_BIT_32(7)
2873	/** Bits 9-11 - - Available for use to system software. */
2874	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2875	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2876	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2877	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2878	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2879	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2880	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2881	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2882	#define X86_PDPE_LM_NX RT_BIT_64(63)
2883	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2884	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2885	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2886	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2887	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2888	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2889	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2890	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2891
2892
2893	/**
2894	* Page directory pointer table entry.
2895	*/
2896	typedef struct X86PDPEBITS
2897	{
2898	/** Flags whether(=1) or not the page is present. */
2899	uint32_t u1Present : 1;
2900	/** Chunk of reserved bits. */
2901	uint32_t u2Reserved : 2;
2902	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2903	uint32_t u1WriteThru : 1;
2904	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2905	uint32_t u1CacheDisable : 1;
2906	/** Chunk of reserved bits. */
2907	uint32_t u4Reserved : 4;
2908	/** Available for use to system software. */
2909	uint32_t u3Available : 3;
2910	/** Physical Page number of the next level - Low Part. Don't use! */
2911	uint32_t u20PageNoLow : 20;
2912	/** Physical Page number of the next level - High Part. Don't use! */
2913	uint32_t u20PageNoHigh : 20;
2914	/** MBZ bits */
2915	uint32_t u12Reserved : 12;
2916	} X86PDPEBITS;
2917	#ifndef VBOX_FOR_DTRACE_LIB
2918	AssertCompileSize(X86PDPEBITS, 8);
2919	#endif
2920	/** Pointer to a page directory pointer table entry. */
2921	typedef X86PDPEBITS *PX86PTPEBITS;
2922	/** Pointer to a const page directory pointer table entry. */
2923	typedef const X86PDPEBITS *PCX86PTPEBITS;
2924
2925	/**
2926	* Page directory pointer table entry. AMD64 version
2927	*/
2928	typedef struct X86PDPEAMD64BITS
2929	{
2930	/** Flags whether(=1) or not the page is present. */
2931	uint32_t u1Present : 1;
2932	/** Read(=0) / Write(=1) flag. */
2933	uint32_t u1Write : 1;
2934	/** User(=1) / Supervisor (=0) flag. */
2935	uint32_t u1User : 1;
2936	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2937	uint32_t u1WriteThru : 1;
2938	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2939	uint32_t u1CacheDisable : 1;
2940	/** Accessed flag.
2941	* Indicates that the page have been read or written to. */
2942	uint32_t u1Accessed : 1;
2943	/** Chunk of reserved bits. */
2944	uint32_t u3Reserved : 3;
2945	/** Available for use to system software. */
2946	uint32_t u3Available : 3;
2947	/** Physical Page number of the next level - Low Part. Don't use! */
2948	uint32_t u20PageNoLow : 20;
2949	/** Physical Page number of the next level - High Part. Don't use! */
2950	uint32_t u20PageNoHigh : 20;
2951	/** MBZ bits */
2952	uint32_t u11Reserved : 11;
2953	/** No Execute flag. */
2954	uint32_t u1NoExecute : 1;
2955	} X86PDPEAMD64BITS;
2956	#ifndef VBOX_FOR_DTRACE_LIB
2957	AssertCompileSize(X86PDPEAMD64BITS, 8);
2958	#endif
2959	/** Pointer to a page directory pointer table entry. */
2960	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2961	/** Pointer to a const page directory pointer table entry. */
2962	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2963
2964	/**
2965	* Page directory pointer table entry for 1GB page. (AMD64 only)
2966	*/
2967	typedef struct X86PDPE1GB
2968	{
2969	/** 0: Flags whether(=1) or not the page is present. */
2970	uint32_t u1Present : 1;
2971	/** 1: Read(=0) / Write(=1) flag. */
2972	uint32_t u1Write : 1;
2973	/** 2: User(=1) / Supervisor (=0) flag. */
2974	uint32_t u1User : 1;
2975	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2976	uint32_t u1WriteThru : 1;
2977	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2978	uint32_t u1CacheDisable : 1;
2979	/** 5: Accessed flag.
2980	* Indicates that the page have been read or written to. */
2981	uint32_t u1Accessed : 1;
2982	/** 6: Dirty flag for 1GB pages. */
2983	uint32_t u1Dirty : 1;
2984	/** 7: Indicates 1GB page if set. */
2985	uint32_t u1Size : 1;
2986	/** 8: Global 1GB page. */
2987	uint32_t u1Global: 1;
2988	/** 9-11: Available for use to system software. */
2989	uint32_t u3Available : 3;
2990	/** 12: PAT bit for 1GB page. */
2991	uint32_t u1PAT : 1;
2992	/** 13-29: MBZ bits. */
2993	uint32_t u17Reserved : 17;
2994	/** 30-31: Physical page number - Low Part. Don't use! */
2995	uint32_t u2PageNoLow : 2;
2996	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2997	uint32_t u20PageNoHigh : 20;
2998	/** 52-62: MBZ bits */
2999	uint32_t u11Reserved : 11;
3000	/** 63: No Execute flag. */
3001	uint32_t u1NoExecute : 1;
3002	} X86PDPE1GB;
3003	#ifndef VBOX_FOR_DTRACE_LIB
3004	AssertCompileSize(X86PDPE1GB, 8);
3005	#endif
3006	/** Pointer to a page directory pointer table entry for a 1GB page. */
3007	typedef X86PDPE1GB *PX86PDPE1GB;
3008	/** Pointer to a const page directory pointer table entry for a 1GB page. */
3009	typedef const X86PDPE1GB *PCX86PDPE1GB;
3010
3011	/**
3012	* Page directory pointer table entry.
3013	*/
3014	typedef union X86PDPE
3015	{
3016	/** Unsigned integer view. */
3017	X86PGPAEUINT u;
3018	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3019	/** Normal view. */
3020	X86PDPEBITS n;
3021	/** AMD64 view. */
3022	X86PDPEAMD64BITS lm;
3023	/** AMD64 big view. */
3024	X86PDPE1GB b;
3025	#endif
3026	/** 8 bit unsigned integer view. */
3027	uint8_t au8[8];
3028	/** 16 bit unsigned integer view. */
3029	uint16_t au16[4];
3030	/** 32 bit unsigned integer view. */
3031	uint32_t au32[2];
3032	} X86PDPE;
3033	#ifndef VBOX_FOR_DTRACE_LIB
3034	AssertCompileSize(X86PDPE, 8);
3035	#endif
3036	/** Pointer to a page directory pointer table entry. */
3037	typedef X86PDPE *PX86PDPE;
3038	/** Pointer to a const page directory pointer table entry. */
3039	typedef const X86PDPE *PCX86PDPE;
3040
3041
3042	/**
3043	* Page directory pointer table.
3044	*/
3045	typedef struct X86PDPT
3046	{
3047	/** PDE Array. */
3048	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3049	} X86PDPT;
3050	#ifndef VBOX_FOR_DTRACE_LIB
3051	AssertCompileSize(X86PDPT, 4096);
3052	#endif
3053	/** Pointer to a page directory pointer table. */
3054	typedef X86PDPT *PX86PDPT;
3055	/** Pointer to a const page directory pointer table. */
3056	typedef const X86PDPT *PCX86PDPT;
3057
3058	/** The page shift to get the PDPT index. */
3059	#define X86_PDPT_SHIFT 30
3060	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3061	#define X86_PDPT_MASK_PAE 0x3
3062	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3063	#define X86_PDPT_MASK_AMD64 0x1ff
3064
3065	/** @} */
3066
3067
3068	/** @name Page Map Level-4 Entry (Long Mode PAE)
3069	* @{
3070	*/
3071	/** Bit 0 - P - Present bit. */
3072	#define X86_PML4E_P RT_BIT_32(0)
3073	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3074	#define X86_PML4E_RW RT_BIT_32(1)
3075	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3076	#define X86_PML4E_US RT_BIT_32(2)
3077	/** Bit 3 - PWT - Page level write thru bit. */
3078	#define X86_PML4E_PWT RT_BIT_32(3)
3079	/** Bit 4 - PCD - Page level cache disable bit. */
3080	#define X86_PML4E_PCD RT_BIT_32(4)
3081	/** Bit 5 - A - Access bit. */
3082	#define X86_PML4E_A RT_BIT_32(5)
3083	/** Bits 9-11 - - Available for use to system software. */
3084	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3085	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3086	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3087	/** Bits 8, 7 - - MBZ bits when NX is active. */
3088	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3089	/** Bits 63, 7 - - MBZ bits when no NX. */
3090	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3091	/** Bits 63 - NX - PAE - No execution flag. */
3092	#define X86_PML4E_NX RT_BIT_64(63)
3093
3094	/**
3095	* Page Map Level-4 Entry
3096	*/
3097	typedef struct X86PML4EBITS
3098	{
3099	/** Flags whether(=1) or not the page is present. */
3100	uint32_t u1Present : 1;
3101	/** Read(=0) / Write(=1) flag. */
3102	uint32_t u1Write : 1;
3103	/** User(=1) / Supervisor (=0) flag. */
3104	uint32_t u1User : 1;
3105	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3106	uint32_t u1WriteThru : 1;
3107	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3108	uint32_t u1CacheDisable : 1;
3109	/** Accessed flag.
3110	* Indicates that the page have been read or written to. */
3111	uint32_t u1Accessed : 1;
3112	/** Chunk of reserved bits. */
3113	uint32_t u3Reserved : 3;
3114	/** Available for use to system software. */
3115	uint32_t u3Available : 3;
3116	/** Physical Page number of the next level - Low Part. Don't use! */
3117	uint32_t u20PageNoLow : 20;
3118	/** Physical Page number of the next level - High Part. Don't use! */
3119	uint32_t u20PageNoHigh : 20;
3120	/** MBZ bits */
3121	uint32_t u11Reserved : 11;
3122	/** No Execute flag. */
3123	uint32_t u1NoExecute : 1;
3124	} X86PML4EBITS;
3125	#ifndef VBOX_FOR_DTRACE_LIB
3126	AssertCompileSize(X86PML4EBITS, 8);
3127	#endif
3128	/** Pointer to a page map level-4 entry. */
3129	typedef X86PML4EBITS *PX86PML4EBITS;
3130	/** Pointer to a const page map level-4 entry. */
3131	typedef const X86PML4EBITS *PCX86PML4EBITS;
3132
3133	/**
3134	* Page Map Level-4 Entry.
3135	*/
3136	typedef union X86PML4E
3137	{
3138	/** Unsigned integer view. */
3139	X86PGPAEUINT u;
3140	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3141	/** Normal view. */
3142	X86PML4EBITS n;
3143	#endif
3144	/** 8 bit unsigned integer view. */
3145	uint8_t au8[8];
3146	/** 16 bit unsigned integer view. */
3147	uint16_t au16[4];
3148	/** 32 bit unsigned integer view. */
3149	uint32_t au32[2];
3150	} X86PML4E;
3151	#ifndef VBOX_FOR_DTRACE_LIB
3152	AssertCompileSize(X86PML4E, 8);
3153	#endif
3154	/** Pointer to a page map level-4 entry. */
3155	typedef X86PML4E *PX86PML4E;
3156	/** Pointer to a const page map level-4 entry. */
3157	typedef const X86PML4E *PCX86PML4E;
3158
3159
3160	/**
3161	* Page Map Level-4.
3162	*/
3163	typedef struct X86PML4
3164	{
3165	/** PDE Array. */
3166	X86PML4E a[X86_PG_PAE_ENTRIES];
3167	} X86PML4;
3168	#ifndef VBOX_FOR_DTRACE_LIB
3169	AssertCompileSize(X86PML4, 4096);
3170	#endif
3171	/** Pointer to a page map level-4. */
3172	typedef X86PML4 *PX86PML4;
3173	/** Pointer to a const page map level-4. */
3174	typedef const X86PML4 *PCX86PML4;
3175
3176	/** The page shift to get the PML4 index. */
3177	#define X86_PML4_SHIFT 39
3178	/** The PML4 index mask (apply to a shifted page address). */
3179	#define X86_PML4_MASK 0x1ff
3180
3181	/** @} */
3182
3183	/** @} */
3184
3185	/**
3186	* Intel PCID invalidation types.
3187	*/
3188	/** Individual address invalidation. */
3189	#define X86_INVPCID_TYPE_INDV_ADDR 0
3190	/** Single-context invalidation. */
3191	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3192	/** All-context including globals invalidation. */
3193	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3194	/** All-context excluding globals invalidation. */
3195	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3196	/** The maximum valid invalidation type value. */
3197	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3198
3199
3200	/** @name Special FPU integer values.
3201	* @{ */
3202	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3203	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3204	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3205	/** @} */
3206
3207	/**
3208	* 32-bit protected mode FSTENV image.
3209	*/
3210	typedef struct X86FSTENV32P
3211	{
3212	uint16_t FCW; /*< 0x00 /
3213	uint16_t padding1; /*< 0x02 /
3214	uint16_t FSW; /*< 0x04 /
3215	uint16_t padding2; /*< 0x06 /
3216	uint16_t FTW; /*< 0x08 /
3217	uint16_t padding3; /*< 0x0a /
3218	uint32_t FPUIP; /*< 0x0c /
3219	uint16_t FPUCS; /*< 0x10 /
3220	uint16_t FOP; /*< 0x12 /
3221	uint32_t FPUDP; /*< 0x14 /
3222	uint16_t FPUDS; /*< 0x18 /
3223	uint16_t padding4; /*< 0x1a /
3224	} X86FSTENV32P;
3225	#ifndef VBOX_FOR_DTRACE_LIB
3226	AssertCompileSize(X86FSTENV32P, 0x1c);
3227	#endif
3228	/** Pointer to a 32-bit protected mode FSTENV image. */
3229	typedef X86FSTENV32P *PX86FSTENV32P;
3230	/** Pointer to a const 32-bit protected mode FSTENV image. */
3231	typedef X86FSTENV32P const *PCX86FSTENV32P;
3232
3233
3234	/**
3235	* 80-bit MMX/FPU register type.
3236	*/
3237	typedef struct X86FPUMMX
3238	{
3239	uint8_t reg[10];
3240	} X86FPUMMX;
3241	#ifndef VBOX_FOR_DTRACE_LIB
3242	AssertCompileSize(X86FPUMMX, 10);
3243	#endif
3244	/** Pointer to a 80-bit MMX/FPU register type. */
3245	typedef X86FPUMMX *PX86FPUMMX;
3246	/** Pointer to a const 80-bit MMX/FPU register type. */
3247	typedef const X86FPUMMX *PCX86FPUMMX;
3248
3249	/** FPU (x87) register. */
3250	typedef union X86FPUREG
3251	{
3252	/** MMX view. */
3253	uint64_t mmx;
3254	/** FPU view - todo. */
3255	X86FPUMMX fpu;
3256	/** Extended precision floating point view. */
3257	RTFLOAT80U r80;
3258	/** Extended precision floating point view v2 */
3259	RTFLOAT80U2 r80Ex;
3260	/** 8-bit view. */
3261	uint8_t au8[16];
3262	/** 16-bit view. */
3263	uint16_t au16[8];
3264	/** 32-bit view. */
3265	uint32_t au32[4];
3266	/** 64-bit view. */
3267	uint64_t au64[2];
3268	/** 128-bit view. (yeah, very helpful) */
3269	uint128_t au128[1];
3270	} X86FPUREG;
3271	#ifndef VBOX_FOR_DTRACE_LIB
3272	AssertCompileSize(X86FPUREG, 16);
3273	#endif
3274	/** Pointer to a FPU register. */
3275	typedef X86FPUREG *PX86FPUREG;
3276	/** Pointer to a const FPU register. */
3277	typedef X86FPUREG const *PCX86FPUREG;
3278
3279	/** FPU (x87) register - v2 with correct size. */
3280	#pragma pack(1)
3281	typedef union X86FPUREG2
3282	{
3283	/** MMX view. */
3284	uint64_t mmx;
3285	/** FPU view - todo. */
3286	X86FPUMMX fpu;
3287	/** Extended precision floating point view. */
3288	RTFLOAT80U r80;
3289	/** 8-bit view. */
3290	uint8_t au8[10];
3291	/** 16-bit view. */
3292	uint16_t au16[5];
3293	/** 32-bit view. */
3294	uint32_t au32[2];
3295	/** 64-bit view. */
3296	uint64_t au64[1];
3297	} X86FPUREG2;
3298	#pragma pack()
3299	#ifndef VBOX_FOR_DTRACE_LIB
3300	AssertCompileSize(X86FPUREG2, 10);
3301	#endif
3302	/** Pointer to a FPU register - v2. */
3303	typedef X86FPUREG2 *PX86FPUREG2;
3304	/** Pointer to a const FPU register - v2. */
3305	typedef X86FPUREG2 const *PCX86FPUREG2;
3306
3307	/**
3308	* XMM register union.
3309	*/
3310	typedef union X86XMMREG
3311	{
3312	/** XMM Register view. */
3313	uint128_t xmm;
3314	/** 8-bit view. */
3315	uint8_t au8[16];
3316	/** 16-bit view. */
3317	uint16_t au16[8];
3318	/** 32-bit view. */
3319	uint32_t au32[4];
3320	/** 64-bit view. */
3321	uint64_t au64[2];
3322	/** Signed 8-bit view. */
3323	int8_t ai8[16];
3324	/** Signed 16-bit view. */
3325	int16_t ai16[8];
3326	/** Signed 32-bit view. */
3327	int32_t ai32[4];
3328	/** Signed 64-bit view. */
3329	int64_t ai64[2];
3330	/** 128-bit view. (yeah, very helpful) */
3331	uint128_t au128[1];
3332	/** Single precision floating point view. */
3333	RTFLOAT32U ar32[4];
3334	/** Double precision floating point view. */
3335	RTFLOAT64U ar64[2];
3336	#ifndef VBOX_FOR_DTRACE_LIB
3337	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3338	RTUINT128U uXmm;
3339	#endif
3340	} X86XMMREG;
3341	#ifndef VBOX_FOR_DTRACE_LIB
3342	AssertCompileSize(X86XMMREG, 16);
3343	#endif
3344	/** Pointer to an XMM register state. */
3345	typedef X86XMMREG *PX86XMMREG;
3346	/** Pointer to a const XMM register state. */
3347	typedef X86XMMREG const *PCX86XMMREG;
3348
3349	/**
3350	* YMM register union.
3351	*/
3352	typedef union X86YMMREG
3353	{
3354	/** YMM register view. */
3355	RTUINT256U ymm;
3356	/** 8-bit view. */
3357	uint8_t au8[32];
3358	/** 16-bit view. */
3359	uint16_t au16[16];
3360	/** 32-bit view. */
3361	uint32_t au32[8];
3362	/** 64-bit view. */
3363	uint64_t au64[4];
3364	/** 128-bit view. (yeah, very helpful) */
3365	uint128_t au128[2];
3366	/** Single precision floating point view. */
3367	RTFLOAT32U ar32[8];
3368	/** Double precision floating point view. */
3369	RTFLOAT64U ar64[4];
3370	/** XMM sub register view. */
3371	X86XMMREG aXmm[2];
3372	} X86YMMREG;
3373	#ifndef VBOX_FOR_DTRACE_LIB
3374	AssertCompileSize(X86YMMREG, 32);
3375	#endif
3376	/** Pointer to an YMM register state. */
3377	typedef X86YMMREG *PX86YMMREG;
3378	/** Pointer to a const YMM register state. */
3379	typedef X86YMMREG const *PCX86YMMREG;
3380
3381	/**
3382	* ZMM register union.
3383	*/
3384	typedef union X86ZMMREG
3385	{
3386	/** 8-bit view. */
3387	uint8_t au8[64];
3388	/** 16-bit view. */
3389	uint16_t au16[32];
3390	/** 32-bit view. */
3391	uint32_t au32[16];
3392	/** 64-bit view. */
3393	uint64_t au64[8];
3394	/** 128-bit view. (yeah, very helpful) */
3395	uint128_t au128[4];
3396	/** Single precision floating point view. */
3397	RTFLOAT32U ar32[16];
3398	/** Double precision floating point view. */
3399	RTFLOAT64U ar64[8];
3400	/** XMM sub register view. */
3401	X86XMMREG aXmm[4];
3402	/** YMM sub register view. */
3403	X86YMMREG aYmm[2];
3404	} X86ZMMREG;
3405	#ifndef VBOX_FOR_DTRACE_LIB
3406	AssertCompileSize(X86ZMMREG, 64);
3407	#endif
3408	/** Pointer to an ZMM register state. */
3409	typedef X86ZMMREG *PX86ZMMREG;
3410	/** Pointer to a const ZMM register state. */
3411	typedef X86ZMMREG const *PCX86ZMMREG;
3412
3413
3414	/**
3415	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3416	*/
3417	#pragma pack(1)
3418	typedef struct X86FPUSTATE
3419	{
3420	/** 0x00 - Control word. */
3421	uint16_t FCW;
3422	/** 0x02 - Alignment word */
3423	uint16_t Dummy1;
3424	/** 0x04 - Status word. */
3425	uint16_t FSW;
3426	/** 0x06 - Alignment word */
3427	uint16_t Dummy2;
3428	/** 0x08 - Tag word */
3429	uint16_t FTW;
3430	/** 0x0a - Alignment word */
3431	uint16_t Dummy3;
3432
3433	/** 0x0c - Instruction pointer. */
3434	uint32_t FPUIP;
3435	/** 0x10 - Code selector. */
3436	uint16_t CS;
3437	/** 0x12 - Opcode. */
3438	uint16_t FOP;
3439	/** 0x14 - Data pointer. */
3440	uint32_t FPUOO;
3441	/** 0x18 - FOS. */
3442	uint16_t FPUOS;
3443	/** 0x0a - Alignment word */
3444	uint16_t Dummy4;
3445	/** 0x1c - FPU register. */
3446	X86FPUREG2 regs[8];
3447	} X86FPUSTATE;
3448	#pragma pack()
3449	AssertCompileSize(X86FPUSTATE, 108);
3450	/** Pointer to a FPU state. */
3451	typedef X86FPUSTATE *PX86FPUSTATE;
3452	/** Pointer to a const FPU state. */
3453	typedef const X86FPUSTATE *PCX86FPUSTATE;
3454
3455	/**
3456	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3457	*/
3458	#pragma pack(1)
3459	typedef struct X86FXSTATE
3460	{
3461	/** 0x00 - Control word. */
3462	uint16_t FCW;
3463	/** 0x02 - Status word. */
3464	uint16_t FSW;
3465	/** 0x04 - Tag word. (The upper byte is always zero.) */
3466	uint16_t FTW;
3467	/** 0x06 - Opcode. */
3468	uint16_t FOP;
3469	/** 0x08 - Instruction pointer. */
3470	uint32_t FPUIP;
3471	/** 0x0c - Code selector. */
3472	uint16_t CS;
3473	uint16_t Rsrvd1;
3474	/** 0x10 - Data pointer. */
3475	uint32_t FPUDP;
3476	/** 0x14 - Data segment */
3477	uint16_t DS;
3478	/** 0x16 */
3479	uint16_t Rsrvd2;
3480	/** 0x18 */
3481	uint32_t MXCSR;
3482	/** 0x1c */
3483	uint32_t MXCSR_MASK;
3484	/** 0x20 - FPU registers. */
3485	X86FPUREG aRegs[8];
3486	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3487	X86XMMREG aXMM[16];
3488	/* - offset 416 - */
3489	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3490	/* - offset 464 - Software usable reserved bits. */
3491	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3492	} X86FXSTATE;
3493	#pragma pack()
3494	/** Pointer to a FPU Extended state. */
3495	typedef X86FXSTATE *PX86FXSTATE;
3496	/** Pointer to a const FPU Extended state. */
3497	typedef const X86FXSTATE *PCX86FXSTATE;
3498
3499	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3500	* magic. Don't forget to update x86.mac if you change this! */
3501	#define X86_OFF_FXSTATE_RSVD 0x1d0
3502	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3503	* forget to update x86.mac if you change this!
3504	* @todo r=bird: This has nothing what-so-ever to do here.... */
3505	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3506	#ifndef VBOX_FOR_DTRACE_LIB
3507	AssertCompileSize(X86FXSTATE, 512);
3508	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3509	#endif
3510
3511	/** @name FPU status word flags.
3512	* @{ */
3513	/** Exception Flag: Invalid operation. */
3514	#define X86_FSW_IE RT_BIT_32(0)
3515	#define X86_FSW_IE_BIT 0
3516	/** Exception Flag: Denormalized operand. */
3517	#define X86_FSW_DE RT_BIT_32(1)
3518	#define X86_FSW_DE_BIT 1
3519	/** Exception Flag: Zero divide. */
3520	#define X86_FSW_ZE RT_BIT_32(2)
3521	#define X86_FSW_ZE_BIT 2
3522	/** Exception Flag: Overflow. */
3523	#define X86_FSW_OE RT_BIT_32(3)
3524	#define X86_FSW_OE_BIT 3
3525	/** Exception Flag: Underflow. */
3526	#define X86_FSW_UE RT_BIT_32(4)
3527	#define X86_FSW_UE_BIT 4
3528	/** Exception Flag: Precision. */
3529	#define X86_FSW_PE RT_BIT_32(5)
3530	#define X86_FSW_PE_BIT 5
3531	/** Stack fault. */
3532	#define X86_FSW_SF RT_BIT_32(6)
3533	#define X86_FSW_SF_BIT 6
3534	/** Error summary status. */
3535	#define X86_FSW_ES RT_BIT_32(7)
3536	#define X86_FSW_ES_BIT 7
3537	/** Mask of exceptions flags, excluding the summary bit. */
3538	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3539	/** Mask of exceptions flags, including the summary bit. */
3540	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3541	/** Condition code 0. */
3542	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3543	#define X86_FSW_C0_BIT 8
3544	/** Condition code 1. */
3545	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3546	#define X86_FSW_C1_BIT 9
3547	/** Condition code 2. */
3548	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3549	#define X86_FSW_C2_BIT 10
3550	/** Top of the stack mask. */
3551	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3552	/** TOP shift value. */
3553	#define X86_FSW_TOP_SHIFT 11
3554	/** Mask for getting TOP value after shifting it right. */
3555	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3556	/** Get the TOP value. */
3557	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3558	/** Get the TOP value offsetted by a_iSt (0-7). */
3559	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3560	/** Condition code 3. */
3561	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3562	#define X86_FSW_C3_BIT 14
3563	/** Mask of exceptions flags, including the summary bit. */
3564	#define X86_FSW_C_MASK UINT16_C(0x4700)
3565	/** FPU busy. */
3566	#define X86_FSW_B RT_BIT_32(15)
3567	/** For use with FPREM and FPREM1. */
3568	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3569	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3570	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3571	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3572	/** For use with FPREM and FPREM1. */
3573	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3574	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3575	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3576	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3577	/** @} */
3578
3579
3580	/** @name FPU control word flags.
3581	* @{ */
3582	/** Exception Mask: Invalid operation. */
3583	#define X86_FCW_IM RT_BIT_32(0)
3584	#define X86_FCW_IM_BIT 0
3585	/** Exception Mask: Denormalized operand. */
3586	#define X86_FCW_DM RT_BIT_32(1)
3587	#define X86_FCW_DM_BIT 1
3588	/** Exception Mask: Zero divide. */
3589	#define X86_FCW_ZM RT_BIT_32(2)
3590	#define X86_FCW_ZM_BIT 2
3591	/** Exception Mask: Overflow. */
3592	#define X86_FCW_OM RT_BIT_32(3)
3593	#define X86_FCW_OM_BIT 3
3594	/** Exception Mask: Underflow. */
3595	#define X86_FCW_UM RT_BIT_32(4)
3596	#define X86_FCW_UM_BIT 4
3597	/** Exception Mask: Precision. */
3598	#define X86_FCW_PM RT_BIT_32(5)
3599	#define X86_FCW_PM_BIT 5
3600	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3601	* @remarks This includes reserved bit 6. */
3602	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3603	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3604	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3605	/** Precision control mask. */
3606	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3607	/** Precision control shift. */
3608	#define X86_FCW_PC_SHIFT 8
3609	/** Precision control: 24-bit. */
3610	#define X86_FCW_PC_24 UINT16_C(0x0000)
3611	/** Precision control: Reserved. */
3612	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3613	/** Precision control: 53-bit. */
3614	#define X86_FCW_PC_53 UINT16_C(0x0200)
3615	/** Precision control: 64-bit. */
3616	#define X86_FCW_PC_64 UINT16_C(0x0300)
3617	/** Rounding control mask. */
3618	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3619	/** Rounding control shift. */
3620	#define X86_FCW_RC_SHIFT 10
3621	/** Rounding control: To nearest. */
3622	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3623	/** Rounding control: Down. */
3624	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3625	/** Rounding control: Up. */
3626	#define X86_FCW_RC_UP UINT16_C(0x0800)
3627	/** Rounding control: Towards zero. */
3628	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3629	/** Infinity control mask - obsolete, 8087 & 287 only. */
3630	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3631	/** Infinity control: Affine - positive infinity is distictly different from
3632	* negative infinity.
3633	* @note 8087, 287 only */
3634	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3635	/** Infinity control: Projective - positive and negative infinity are the
3636	* same (sign ignored).
3637	* @note 8087, 287 only */
3638	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3639	/** Bits which should be zero, apparently. */
3640	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3641	/** @} */
3642
3643	/** @name SSE MXCSR
3644	* @{ */
3645	/** Exception Flag: Invalid operation. */
3646	#define X86_MXCSR_IE RT_BIT_32(0)
3647	/** Exception Flag: Denormalized operand. */
3648	#define X86_MXCSR_DE RT_BIT_32(1)
3649	/** Exception Flag: Zero divide. */
3650	#define X86_MXCSR_ZE RT_BIT_32(2)
3651	/** Exception Flag: Overflow. */
3652	#define X86_MXCSR_OE RT_BIT_32(3)
3653	/** Exception Flag: Underflow. */
3654	#define X86_MXCSR_UE RT_BIT_32(4)
3655	/** Exception Flag: Precision. */
3656	#define X86_MXCSR_PE RT_BIT_32(5)
3657	/** Exception Flags: mask */
3658	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3659
3660	/** Denormals are zero. */
3661	#define X86_MXCSR_DAZ RT_BIT_32(6)
3662
3663	/** Exception Mask: Invalid operation. */
3664	#define X86_MXCSR_IM RT_BIT_32(7)
3665	/** Exception Mask: Denormalized operand. */
3666	#define X86_MXCSR_DM RT_BIT_32(8)
3667	/** Exception Mask: Zero divide. */
3668	#define X86_MXCSR_ZM RT_BIT_32(9)
3669	/** Exception Mask: Overflow. */
3670	#define X86_MXCSR_OM RT_BIT_32(10)
3671	/** Exception Mask: Underflow. */
3672	#define X86_MXCSR_UM RT_BIT_32(11)
3673	/** Exception Mask: Precision. */
3674	#define X86_MXCSR_PM RT_BIT_32(12)
3675	/** Exception Mask: mask. */
3676	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3677	/** Exception Mask: shift. */
3678	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3679
3680	/** Rounding control mask. */
3681	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3682	/** Rounding control shift. */
3683	#define X86_MXCSR_RC_SHIFT 13
3684	/** Rounding control: To nearest. */
3685	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3686	/** Rounding control: Down. */
3687	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3688	/** Rounding control: Up. */
3689	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3690	/** Rounding control: Towards zero. */
3691	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3692
3693	/** Flush-to-zero for masked underflow. */
3694	#define X86_MXCSR_FZ RT_BIT_32(15)
3695
3696	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3697	#define X86_MXCSR_MM RT_BIT_32(17)
3698	/** Bits which should be zero, apparently. */
3699	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3700	/** @} */
3701
3702	/**
3703	* XSAVE header.
3704	*/
3705	typedef struct X86XSAVEHDR
3706	{
3707	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3708	uint64_t bmXState;
3709	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3710	uint64_t bmXComp;
3711	/** Reserved for furture extensions, probably MBZ. */
3712	uint64_t au64Reserved[6];
3713	} X86XSAVEHDR;
3714	#ifndef VBOX_FOR_DTRACE_LIB
3715	AssertCompileSize(X86XSAVEHDR, 64);
3716	#endif
3717	/** Pointer to an XSAVE header. */
3718	typedef X86XSAVEHDR *PX86XSAVEHDR;
3719	/** Pointer to a const XSAVE header. */
3720	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3721
3722
3723	/**
3724	* The high 128-bit YMM register state (XSAVE_C_YMM).
3725	* (The lower 128-bits being in X86FXSTATE.)
3726	*/
3727	typedef struct X86XSAVEYMMHI
3728	{
3729	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3730	X86XMMREG aYmmHi[16];
3731	} X86XSAVEYMMHI;
3732	#ifndef VBOX_FOR_DTRACE_LIB
3733	AssertCompileSize(X86XSAVEYMMHI, 256);
3734	#endif
3735	/** Pointer to a high 128-bit YMM register state. */
3736	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3737	/** Pointer to a const high 128-bit YMM register state. */
3738	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3739
3740	/**
3741	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3742	*/
3743	typedef struct X86XSAVEBNDREGS
3744	{
3745	/** Array of registers (BND0...BND3). */
3746	struct
3747	{
3748	/** Lower bound. */
3749	uint64_t uLowerBound;
3750	/** Upper bound. */
3751	uint64_t uUpperBound;
3752	} aRegs[4];
3753	} X86XSAVEBNDREGS;
3754	#ifndef VBOX_FOR_DTRACE_LIB
3755	AssertCompileSize(X86XSAVEBNDREGS, 64);
3756	#endif
3757	/** Pointer to a MPX bound register state. */
3758	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3759	/** Pointer to a const MPX bound register state. */
3760	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3761
3762	/**
3763	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3764	*/
3765	typedef struct X86XSAVEBNDCFG
3766	{
3767	uint64_t fConfig;
3768	uint64_t fStatus;
3769	} X86XSAVEBNDCFG;
3770	#ifndef VBOX_FOR_DTRACE_LIB
3771	AssertCompileSize(X86XSAVEBNDCFG, 16);
3772	#endif
3773	/** Pointer to a MPX bound config and status register state. */
3774	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3775	/** Pointer to a const MPX bound config and status register state. */
3776	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3777
3778	/**
3779	* AVX-512 opmask state (XSAVE_C_OPMASK).
3780	*/
3781	typedef struct X86XSAVEOPMASK
3782	{
3783	/** The K0..K7 values. */
3784	uint64_t aKRegs[8];
3785	} X86XSAVEOPMASK;
3786	#ifndef VBOX_FOR_DTRACE_LIB
3787	AssertCompileSize(X86XSAVEOPMASK, 64);
3788	#endif
3789	/** Pointer to a AVX-512 opmask state. */
3790	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3791	/** Pointer to a const AVX-512 opmask state. */
3792	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3793
3794	/**
3795	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3796	*/
3797	typedef struct X86XSAVEZMMHI256
3798	{
3799	/** Upper 256-bits of ZMM0-15. */
3800	X86YMMREG aHi256Regs[16];
3801	} X86XSAVEZMMHI256;
3802	#ifndef VBOX_FOR_DTRACE_LIB
3803	AssertCompileSize(X86XSAVEZMMHI256, 512);
3804	#endif
3805	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3806	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3807	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3808	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3809
3810	/**
3811	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3812	*/
3813	typedef struct X86XSAVEZMM16HI
3814	{
3815	/** ZMM16 thru ZMM31. */
3816	X86ZMMREG aRegs[16];
3817	} X86XSAVEZMM16HI;
3818	#ifndef VBOX_FOR_DTRACE_LIB
3819	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3820	#endif
3821	/** Pointer to a state comprising ZMM16-32. */
3822	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3823	/** Pointer to a const state comprising ZMM16-32. */
3824	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3825
3826	/**
3827	* AMD Light weight profiling state (XSAVE_C_LWP).
3828	*
3829	* We probably won't play with this as AMD seems to be dropping from their "zen"
3830	* processor micro architecture.
3831	*/
3832	typedef struct X86XSAVELWP
3833	{
3834	/** Details when needed. */
3835	uint64_t auLater[128/8];
3836	} X86XSAVELWP;
3837	#ifndef VBOX_FOR_DTRACE_LIB
3838	AssertCompileSize(X86XSAVELWP, 128);
3839	#endif
3840
3841
3842	/**
3843	* x86 FPU/SSE/AVX/XXXX state.
3844	*
3845	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3846	* changes to this structure.
3847	*/
3848	typedef struct X86XSAVEAREA
3849	{
3850	/** The x87 and SSE region (or legacy region if you like). */
3851	X86FXSTATE x87;
3852	/** The XSAVE header. */
3853	X86XSAVEHDR Hdr;
3854	/** Beyond the header, there isn't really a fixed layout, but we can
3855	generally assume the YMM (AVX) register extensions are present and
3856	follows immediately. */
3857	union
3858	{
3859	/** The high 128-bit AVX registers for easy access by IEM.
3860	* @note This ASSUMES they will always be here... */
3861	X86XSAVEYMMHI YmmHi;
3862
3863	/** This is a typical layout on intel CPUs (good for debuggers). */
3864	struct
3865	{
3866	X86XSAVEYMMHI YmmHi;
3867	X86XSAVEBNDREGS BndRegs;
3868	X86XSAVEBNDCFG BndCfg;
3869	uint8_t abFudgeToMatchDocs[0xB0];
3870	X86XSAVEOPMASK Opmask;
3871	X86XSAVEZMMHI256 ZmmHi256;
3872	X86XSAVEZMM16HI Zmm16Hi;
3873	} Intel;
3874
3875	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3876	struct
3877	{
3878	X86XSAVEYMMHI YmmHi;
3879	X86XSAVELWP Lwp;
3880	} AmdBd;
3881
3882	/** To enbling static deployments that have a reasonable chance of working for
3883	* the next 3-6 CPU generations without running short on space, we allocate a
3884	* lot of extra space here, making the structure a round 8KB in size. This
3885	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3886	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3887	uint8_t ab[8192 - 512 - 64];
3888	} u;
3889	} X86XSAVEAREA;
3890	#ifndef VBOX_FOR_DTRACE_LIB
3891	AssertCompileSize(X86XSAVEAREA, 8192);
3892	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3893	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3894	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3895	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3896	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3897	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3898	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3899	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3900	#endif
3901	/** Pointer to a XSAVE area. */
3902	typedef X86XSAVEAREA *PX86XSAVEAREA;
3903	/** Pointer to a const XSAVE area. */
3904	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3905
3906
3907	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3908	* @{ */
3909	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3910	#define XSAVE_C_X87_BIT 0
3911	/** Bit 0 - x87 - Legacy FPU state. */
3912	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3913	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3914	#define XSAVE_C_SSE_BIT 1
3915	/** Bit 1 - SSE - 128-bit SSE state. */
3916	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3917	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3918	#define XSAVE_C_YMM_BIT 2
3919	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3920	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3921	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3922	#define XSAVE_C_BNDREGS_BIT 3
3923	/** Bit 3 - BNDREGS - MPX bound register state. */
3924	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3925	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3926	#define XSAVE_C_BNDCSR_BIT 4
3927	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3928	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3929	/** Bit 5 - Opmask - opmask state (bit number). */
3930	#define XSAVE_C_OPMASK_BIT 5
3931	/** Bit 5 - Opmask - opmask state. */
3932	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3933	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3934	#define XSAVE_C_ZMM_HI256_BIT 6
3935	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3936	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3937	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3938	#define XSAVE_C_ZMM_16HI_BIT 7
3939	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3940	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3941	/** Bit 9 - PKRU - Protection-key state (bit number). */
3942	#define XSAVE_C_PKRU_BIT 9
3943	/** Bit 9 - PKRU - Protection-key state. */
3944	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3945	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3946	#define XSAVE_C_LWP_BIT 62
3947	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3948	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3949	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3950	#define XSAVE_C_X_BIT 63
3951	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3952	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3953	/** @} */
3954
3955
3956
3957	/** @name Selector Descriptor
3958	* @{
3959	*/
3960
3961	#ifndef VBOX_FOR_DTRACE_LIB
3962	/**
3963	* Descriptor attributes (as seen by VT-x).
3964	*/
3965	typedef struct X86DESCATTRBITS
3966	{
3967	/** 00 - Segment Type. */
3968	unsigned u4Type : 4;
3969	/** 04 - Descriptor Type. System(=0) or code/data selector */
3970	unsigned u1DescType : 1;
3971	/** 05 - Descriptor Privilege level. */
3972	unsigned u2Dpl : 2;
3973	/** 07 - Flags selector present(=1) or not. */
3974	unsigned u1Present : 1;
3975	/** 08 - Segment limit 16-19. */
3976	unsigned u4LimitHigh : 4;
3977	/** 0c - Available for system software. */
3978	unsigned u1Available : 1;
3979	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3980	unsigned u1Long : 1;
3981	/** 0e - This flags meaning depends on the segment type. Try make sense out
3982	* of the intel manual yourself. */
3983	unsigned u1DefBig : 1;
3984	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3985	* clear byte. */
3986	unsigned u1Granularity : 1;
3987	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3988	unsigned u1Unusable : 1;
3989	} X86DESCATTRBITS;
3990	#endif /* !VBOX_FOR_DTRACE_LIB */
3991
3992	/** @name X86DESCATTR masks
3993	* @{ */
3994	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3995	#define X86DESCATTR_DT UINT32_C(0x00000010)
3996	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3997	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3998	#define X86DESCATTR_P UINT32_C(0x00000080)
3999	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4000	#define X86DESCATTR_AVL UINT32_C(0x00001000)
4001	#define X86DESCATTR_L UINT32_C(0x00002000)
4002	#define X86DESCATTR_D UINT32_C(0x00004000)
4003	#define X86DESCATTR_G UINT32_C(0x00008000)
4004	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4005	/** @} */
4006
4007	#pragma pack(1)
4008	typedef union X86DESCATTR
4009	{
4010	/** Unsigned integer view. */
4011	uint32_t u;
4012	#ifndef VBOX_FOR_DTRACE_LIB
4013	/** Normal view. */
4014	X86DESCATTRBITS n;
4015	#endif
4016	} X86DESCATTR;
4017	#pragma pack()
4018	/** Pointer to descriptor attributes. */
4019	typedef X86DESCATTR *PX86DESCATTR;
4020	/** Pointer to const descriptor attributes. */
4021	typedef const X86DESCATTR *PCX86DESCATTR;
4022
4023	#ifndef VBOX_FOR_DTRACE_LIB
4024
4025	/**
4026	* Generic descriptor table entry
4027	*/
4028	#pragma pack(1)
4029	typedef struct X86DESCGENERIC
4030	{
4031	/** 00 - Limit - Low word. */
4032	unsigned u16LimitLow : 16;
4033	/** 10 - Base address - low word.
4034	* Don't try set this to 24 because MSC is doing stupid things then. */
4035	unsigned u16BaseLow : 16;
4036	/** 20 - Base address - first 8 bits of high word. */
4037	unsigned u8BaseHigh1 : 8;
4038	/** 28 - Segment Type. */
4039	unsigned u4Type : 4;
4040	/** 2c - Descriptor Type. System(=0) or code/data selector */
4041	unsigned u1DescType : 1;
4042	/** 2d - Descriptor Privilege level. */
4043	unsigned u2Dpl : 2;
4044	/** 2f - Flags selector present(=1) or not. */
4045	unsigned u1Present : 1;
4046	/** 30 - Segment limit 16-19. */
4047	unsigned u4LimitHigh : 4;
4048	/** 34 - Available for system software. */
4049	unsigned u1Available : 1;
4050	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4051	unsigned u1Long : 1;
4052	/** 36 - This flags meaning depends on the segment type. Try make sense out
4053	* of the intel manual yourself. */
4054	unsigned u1DefBig : 1;
4055	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4056	* clear byte. */
4057	unsigned u1Granularity : 1;
4058	/** 38 - Base address - highest 8 bits. */
4059	unsigned u8BaseHigh2 : 8;
4060	} X86DESCGENERIC;
4061	#pragma pack()
4062	/** Pointer to a generic descriptor entry. */
4063	typedef X86DESCGENERIC *PX86DESCGENERIC;
4064	/** Pointer to a const generic descriptor entry. */
4065	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4066
4067	/** @name Bit offsets of X86DESCGENERIC members.
4068	* @{*/
4069	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4070	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4071	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4072	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4073	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4074	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4075	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4076	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4077	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4078	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4079	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4080	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4081	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4082	/** @} */
4083
4084
4085	/** @name LAR mask
4086	* @{ */
4087	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
4088	#define X86LAR_F_DT UINT16_C( 0x1000)
4089	#define X86LAR_F_DPL UINT16_C( 0x6000)
4090	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4091	#define X86LAR_F_P UINT16_C( 0x8000)
4092	#define X86LAR_F_AVL UINT32_C(0x00100000)
4093	#define X86LAR_F_L UINT32_C(0x00200000)
4094	#define X86LAR_F_D UINT32_C(0x00400000)
4095	#define X86LAR_F_G UINT32_C(0x00800000)
4096	/** @} */
4097
4098
4099	/**
4100	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4101	*/
4102	typedef struct X86DESCGATE
4103	{
4104	/** 00 - Target code segment offset - Low word.
4105	* Ignored if task-gate. */
4106	unsigned u16OffsetLow : 16;
4107	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4108	* TSS selector if task-gate. */
4109	unsigned u16Sel : 16;
4110	/** 20 - Number of parameters for a call-gate.
4111	* Ignored if interrupt-, trap- or task-gate. */
4112	unsigned u5ParmCount : 5;
4113	/** 25 - Reserved / ignored. */
4114	unsigned u3Reserved : 3;
4115	/** 28 - Segment Type. */
4116	unsigned u4Type : 4;
4117	/** 2c - Descriptor Type (0 = system). */
4118	unsigned u1DescType : 1;
4119	/** 2d - Descriptor Privilege level. */
4120	unsigned u2Dpl : 2;
4121	/** 2f - Flags selector present(=1) or not. */
4122	unsigned u1Present : 1;
4123	/** 30 - Target code segment offset - High word.
4124	* Ignored if task-gate. */
4125	unsigned u16OffsetHigh : 16;
4126	} X86DESCGATE;
4127	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4128	typedef X86DESCGATE *PX86DESCGATE;
4129	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4130	typedef const X86DESCGATE *PCX86DESCGATE;
4131
4132	#endif /* VBOX_FOR_DTRACE_LIB */
4133
4134	/**
4135	* Descriptor table entry.
4136	*/
4137	#pragma pack(1)
4138	typedef union X86DESC
4139	{
4140	#ifndef VBOX_FOR_DTRACE_LIB
4141	/** Generic descriptor view. */
4142	X86DESCGENERIC Gen;
4143	/** Gate descriptor view. */
4144	X86DESCGATE Gate;
4145	#endif
4146
4147	/** 8 bit unsigned integer view. */
4148	uint8_t au8[8];
4149	/** 16 bit unsigned integer view. */
4150	uint16_t au16[4];
4151	/** 32 bit unsigned integer view. */
4152	uint32_t au32[2];
4153	/** 64 bit unsigned integer view. */
4154	uint64_t au64[1];
4155	/** Unsigned integer view. */
4156	uint64_t u;
4157	} X86DESC;
4158	#ifndef VBOX_FOR_DTRACE_LIB
4159	AssertCompileSize(X86DESC, 8);
4160	#endif
4161	#pragma pack()
4162	/** Pointer to descriptor table entry. */
4163	typedef X86DESC *PX86DESC;
4164	/** Pointer to const descriptor table entry. */
4165	typedef const X86DESC *PCX86DESC;
4166
4167	/** @def X86DESC_BASE
4168	* Return the base address of a descriptor.
4169	*/
4170	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4171	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4172	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4173	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4174
4175	/** @def X86DESC_LIMIT
4176	* Return the limit of a descriptor.
4177	*/
4178	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4179	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4180	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4181
4182	/** @def X86DESC_LIMIT_G
4183	* Return the limit of a descriptor with the granularity bit taken into account.
4184	* @returns Selector limit (uint32_t).
4185	* @param a_pDesc Pointer to the descriptor.
4186	*/
4187	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4188	( (a_pDesc)->Gen.u1Granularity \
4189	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4190	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4191	)
4192
4193	/** @def X86DESC_GET_HID_ATTR
4194	* Get the descriptor attributes for the hidden register.
4195	*/
4196	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4197	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4198
4199	#ifndef VBOX_FOR_DTRACE_LIB
4200
4201	/**
4202	* 64 bits generic descriptor table entry
4203	* Note: most of these bits have no meaning in long mode.
4204	*/
4205	#pragma pack(1)
4206	typedef struct X86DESC64GENERIC
4207	{
4208	/** Limit - Low word - IGNORED. */
4209	uint32_t u16LimitLow : 16;
4210	/** Base address - low word. - IGNORED
4211	* Don't try set this to 24 because MSC is doing stupid things then. */
4212	uint32_t u16BaseLow : 16;
4213	/** Base address - first 8 bits of high word. - IGNORED */
4214	uint32_t u8BaseHigh1 : 8;
4215	/** Segment Type. */
4216	uint32_t u4Type : 4;
4217	/** Descriptor Type. System(=0) or code/data selector */
4218	uint32_t u1DescType : 1;
4219	/** Descriptor Privilege level. */
4220	uint32_t u2Dpl : 2;
4221	/** Flags selector present(=1) or not. */
4222	uint32_t u1Present : 1;
4223	/** Segment limit 16-19. - IGNORED */
4224	uint32_t u4LimitHigh : 4;
4225	/** Available for system software. - IGNORED */
4226	uint32_t u1Available : 1;
4227	/** Long mode flag. */
4228	uint32_t u1Long : 1;
4229	/** This flags meaning depends on the segment type. Try make sense out
4230	* of the intel manual yourself. */
4231	uint32_t u1DefBig : 1;
4232	/** Granularity of the limit. If set 4KB granularity is used, if
4233	* clear byte. - IGNORED */
4234	uint32_t u1Granularity : 1;
4235	/** Base address - highest 8 bits. - IGNORED */
4236	uint32_t u8BaseHigh2 : 8;
4237	/** Base address - bits 63-32. */
4238	uint32_t u32BaseHigh3 : 32;
4239	uint32_t u8Reserved : 8;
4240	uint32_t u5Zeros : 5;
4241	uint32_t u19Reserved : 19;
4242	} X86DESC64GENERIC;
4243	#pragma pack()
4244	/** Pointer to a generic descriptor entry. */
4245	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4246	/** Pointer to a const generic descriptor entry. */
4247	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4248
4249	/**
4250	* System descriptor table entry (64 bits)
4251	*
4252	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4253	*/
4254	#pragma pack(1)
4255	typedef struct X86DESC64SYSTEM
4256	{
4257	/** Limit - Low word. */
4258	uint32_t u16LimitLow : 16;
4259	/** Base address - low word.
4260	* Don't try set this to 24 because MSC is doing stupid things then. */
4261	uint32_t u16BaseLow : 16;
4262	/** Base address - first 8 bits of high word. */
4263	uint32_t u8BaseHigh1 : 8;
4264	/** Segment Type. */
4265	uint32_t u4Type : 4;
4266	/** Descriptor Type. System(=0) or code/data selector */
4267	uint32_t u1DescType : 1;
4268	/** Descriptor Privilege level. */
4269	uint32_t u2Dpl : 2;
4270	/** Flags selector present(=1) or not. */
4271	uint32_t u1Present : 1;
4272	/** Segment limit 16-19. */
4273	uint32_t u4LimitHigh : 4;
4274	/** Available for system software. */
4275	uint32_t u1Available : 1;
4276	/** Reserved - 0. */
4277	uint32_t u1Reserved : 1;
4278	/** This flags meaning depends on the segment type. Try make sense out
4279	* of the intel manual yourself. */
4280	uint32_t u1DefBig : 1;
4281	/** Granularity of the limit. If set 4KB granularity is used, if
4282	* clear byte. */
4283	uint32_t u1Granularity : 1;
4284	/** Base address - bits 31-24. */
4285	uint32_t u8BaseHigh2 : 8;
4286	/** Base address - bits 63-32. */
4287	uint32_t u32BaseHigh3 : 32;
4288	uint32_t u8Reserved : 8;
4289	uint32_t u5Zeros : 5;
4290	uint32_t u19Reserved : 19;
4291	} X86DESC64SYSTEM;
4292	#pragma pack()
4293	/** Pointer to a system descriptor entry. */
4294	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4295	/** Pointer to a const system descriptor entry. */
4296	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4297
4298	/**
4299	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4300	*/
4301	typedef struct X86DESC64GATE
4302	{
4303	/** Target code segment offset - Low word. */
4304	uint32_t u16OffsetLow : 16;
4305	/** Target code segment selector. */
4306	uint32_t u16Sel : 16;
4307	/** Interrupt stack table for interrupt- and trap-gates.
4308	* Ignored by call-gates. */
4309	uint32_t u3IST : 3;
4310	/** Reserved / ignored. */
4311	uint32_t u5Reserved : 5;
4312	/** Segment Type. */
4313	uint32_t u4Type : 4;
4314	/** Descriptor Type (0 = system). */
4315	uint32_t u1DescType : 1;
4316	/** Descriptor Privilege level. */
4317	uint32_t u2Dpl : 2;
4318	/** Flags selector present(=1) or not. */
4319	uint32_t u1Present : 1;
4320	/** Target code segment offset - High word.
4321	* Ignored if task-gate. */
4322	uint32_t u16OffsetHigh : 16;
4323	/** Target code segment offset - Top dword.
4324	* Ignored if task-gate. */
4325	uint32_t u32OffsetTop : 32;
4326	/** Reserved / ignored / must be zero.
4327	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4328	uint32_t u32Reserved : 32;
4329	} X86DESC64GATE;
4330	AssertCompileSize(X86DESC64GATE, 16);
4331	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4332	typedef X86DESC64GATE *PX86DESC64GATE;
4333	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4334	typedef const X86DESC64GATE *PCX86DESC64GATE;
4335
4336	#endif /* VBOX_FOR_DTRACE_LIB */
4337
4338	/**
4339	* Descriptor table entry.
4340	*/
4341	#pragma pack(1)
4342	typedef union X86DESC64
4343	{
4344	#ifndef VBOX_FOR_DTRACE_LIB
4345	/** Generic descriptor view. */
4346	X86DESC64GENERIC Gen;
4347	/** System descriptor view. */
4348	X86DESC64SYSTEM System;
4349	/** Gate descriptor view. */
4350	X86DESC64GATE Gate;
4351	#endif
4352
4353	/** 8 bit unsigned integer view. */
4354	uint8_t au8[16];
4355	/** 16 bit unsigned integer view. */
4356	uint16_t au16[8];
4357	/** 32 bit unsigned integer view. */
4358	uint32_t au32[4];
4359	/** 64 bit unsigned integer view. */
4360	uint64_t au64[2];
4361	} X86DESC64;
4362	#ifndef VBOX_FOR_DTRACE_LIB
4363	AssertCompileSize(X86DESC64, 16);
4364	#endif
4365	#pragma pack()
4366	/** Pointer to descriptor table entry. */
4367	typedef X86DESC64 *PX86DESC64;
4368	/** Pointer to const descriptor table entry. */
4369	typedef const X86DESC64 *PCX86DESC64;
4370
4371	/** @def X86DESC64_BASE
4372	* Return the base of a 64-bit descriptor.
4373	*/
4374	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4375	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4376	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4377	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4378	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4379
4380
4381
4382	/** @name Host system descriptor table entry - Use with care!
4383	* @{ */
4384	/** Host system descriptor table entry. */
4385	#if HC_ARCH_BITS == 64
4386	typedef X86DESC64 X86DESCHC;
4387	#else
4388	typedef X86DESC X86DESCHC;
4389	#endif
4390	/** Pointer to a host system descriptor table entry. */
4391	#if HC_ARCH_BITS == 64
4392	typedef PX86DESC64 PX86DESCHC;
4393	#else
4394	typedef PX86DESC PX86DESCHC;
4395	#endif
4396	/** Pointer to a const host system descriptor table entry. */
4397	#if HC_ARCH_BITS == 64
4398	typedef PCX86DESC64 PCX86DESCHC;
4399	#else
4400	typedef PCX86DESC PCX86DESCHC;
4401	#endif
4402	/** @} */
4403
4404
4405	/** @name Selector Descriptor Types.
4406	* @{
4407	*/
4408
4409	/** @name Non-System Selector Types.
4410	* @{ */
4411	/** Code(=set)/Data(=clear) bit. */
4412	#define X86_SEL_TYPE_CODE 8
4413	/** Memory(=set)/System(=clear) bit. */
4414	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4415	/** Accessed bit. */
4416	#define X86_SEL_TYPE_ACCESSED 1
4417	/** Expand down bit (for data selectors only). */
4418	#define X86_SEL_TYPE_DOWN 4
4419	/** Conforming bit (for code selectors only). */
4420	#define X86_SEL_TYPE_CONF 4
4421	/** Write bit (for data selectors only). */
4422	#define X86_SEL_TYPE_WRITE 2
4423	/** Read bit (for code selectors only). */
4424	#define X86_SEL_TYPE_READ 2
4425	/** The bit number of the code segment read bit (relative to u4Type). */
4426	#define X86_SEL_TYPE_READ_BIT 1
4427
4428	/** Read only selector type. */
4429	#define X86_SEL_TYPE_RO 0
4430	/** Accessed read only selector type. */
4431	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4432	/** Read write selector type. */
4433	#define X86_SEL_TYPE_RW 2
4434	/** Accessed read write selector type. */
4435	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4436	/** Expand down read only selector type. */
4437	#define X86_SEL_TYPE_RO_DOWN 4
4438	/** Accessed expand down read only selector type. */
4439	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4440	/** Expand down read write selector type. */
4441	#define X86_SEL_TYPE_RW_DOWN 6
4442	/** Accessed expand down read write selector type. */
4443	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4444	/** Execute only selector type. */
4445	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4446	/** Accessed execute only selector type. */
4447	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4448	/** Execute and read selector type. */
4449	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4450	/** Accessed execute and read selector type. */
4451	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4452	/** Conforming execute only selector type. */
4453	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4454	/** Accessed Conforming execute only selector type. */
4455	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4456	/** Conforming execute and write selector type. */
4457	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4458	/** Accessed Conforming execute and write selector type. */
4459	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4460	/** @} */
4461
4462
4463	/** @name System Selector Types.
4464	* @{ */
4465	/** The TSS busy bit mask. */
4466	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4467
4468	/** Undefined system selector type. */
4469	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4470	/** 286 TSS selector. */
4471	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4472	/** LDT selector. */
4473	#define X86_SEL_TYPE_SYS_LDT 2
4474	/** 286 TSS selector - Busy. */
4475	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4476	/** 286 Callgate selector. */
4477	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4478	/** Taskgate selector. */
4479	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4480	/** 286 Interrupt gate selector. */
4481	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4482	/** 286 Trapgate selector. */
4483	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4484	/** Undefined system selector. */
4485	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4486	/** 386 TSS selector. */
4487	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4488	/** Undefined system selector. */
4489	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4490	/** 386 TSS selector - Busy. */
4491	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4492	/** 386 Callgate selector. */
4493	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4494	/** Undefined system selector. */
4495	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4496	/** 386 Interruptgate selector. */
4497	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4498	/** 386 Trapgate selector. */
4499	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4500	/** @} */
4501
4502	/** @name AMD64 System Selector Types.
4503	* @{ */
4504	/** LDT selector. */
4505	#define AMD64_SEL_TYPE_SYS_LDT 2
4506	/** TSS selector - Busy. */
4507	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4508	/** TSS selector - Busy. */
4509	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4510	/** Callgate selector. */
4511	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4512	/** Interruptgate selector. */
4513	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4514	/** Trapgate selector. */
4515	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4516	/** @} */
4517
4518	/** @} */
4519
4520
4521	/** @name Descriptor Table Entry Flag Masks.
4522	* These are for the 2nd 32-bit word of a descriptor.
4523	* @{ */
4524	/** Bits 8-11 - TYPE - Descriptor type mask. */
4525	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4526	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4527	#define X86_DESC_S RT_BIT_32(12)
4528	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4529	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4530	/** Bit 15 - P - Present. */
4531	#define X86_DESC_P RT_BIT_32(15)
4532	/** Bit 20 - AVL - Available for system software. */
4533	#define X86_DESC_AVL RT_BIT_32(20)
4534	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4535	#define X86_DESC_DB RT_BIT_32(22)
4536	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4537	* used, if clear byte. */
4538	#define X86_DESC_G RT_BIT_32(23)
4539	/** @} */
4540
4541	/** @} */
4542
4543
4544	/** @name Task Segments.
4545	* @{
4546	*/
4547
4548	/**
4549	* The minimum TSS descriptor limit for 286 tasks.
4550	*/
4551	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4552
4553	/**
4554	* The minimum TSS descriptor segment limit for 386 tasks.
4555	*/
4556	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4557
4558	/**
4559	* 16-bit Task Segment (TSS).
4560	*/
4561	#pragma pack(1)
4562	typedef struct X86TSS16
4563	{
4564	/** Back link to previous task. (static) */
4565	RTSEL selPrev;
4566	/** Ring-0 stack pointer. (static) */
4567	uint16_t sp0;
4568	/** Ring-0 stack segment. (static) */
4569	RTSEL ss0;
4570	/** Ring-1 stack pointer. (static) */
4571	uint16_t sp1;
4572	/** Ring-1 stack segment. (static) */
4573	RTSEL ss1;
4574	/** Ring-2 stack pointer. (static) */
4575	uint16_t sp2;
4576	/** Ring-2 stack segment. (static) */
4577	RTSEL ss2;
4578	/** IP before task switch. */
4579	uint16_t ip;
4580	/** FLAGS before task switch. */
4581	uint16_t flags;
4582	/** AX before task switch. */
4583	uint16_t ax;
4584	/** CX before task switch. */
4585	uint16_t cx;
4586	/** DX before task switch. */
4587	uint16_t dx;
4588	/** BX before task switch. */
4589	uint16_t bx;
4590	/** SP before task switch. */
4591	uint16_t sp;
4592	/** BP before task switch. */
4593	uint16_t bp;
4594	/** SI before task switch. */
4595	uint16_t si;
4596	/** DI before task switch. */
4597	uint16_t di;
4598	/** ES before task switch. */
4599	RTSEL es;
4600	/** CS before task switch. */
4601	RTSEL cs;
4602	/** SS before task switch. */
4603	RTSEL ss;
4604	/** DS before task switch. */
4605	RTSEL ds;
4606	/** LDTR before task switch. */
4607	RTSEL selLdt;
4608	} X86TSS16;
4609	#ifndef VBOX_FOR_DTRACE_LIB
4610	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4611	#endif
4612	#pragma pack()
4613	/** Pointer to a 16-bit task segment. */
4614	typedef X86TSS16 *PX86TSS16;
4615	/** Pointer to a const 16-bit task segment. */
4616	typedef const X86TSS16 *PCX86TSS16;
4617
4618
4619	/**
4620	* 32-bit Task Segment (TSS).
4621	*/
4622	#pragma pack(1)
4623	typedef struct X86TSS32
4624	{
4625	/** Back link to previous task. (static) */
4626	RTSEL selPrev;
4627	uint16_t padding1;
4628	/** Ring-0 stack pointer. (static) */
4629	uint32_t esp0;
4630	/** Ring-0 stack segment. (static) */
4631	RTSEL ss0;
4632	uint16_t padding_ss0;
4633	/** Ring-1 stack pointer. (static) */
4634	uint32_t esp1;
4635	/** Ring-1 stack segment. (static) */
4636	RTSEL ss1;
4637	uint16_t padding_ss1;
4638	/** Ring-2 stack pointer. (static) */
4639	uint32_t esp2;
4640	/** Ring-2 stack segment. (static) */
4641	RTSEL ss2;
4642	uint16_t padding_ss2;
4643	/** Page directory for the task. (static) */
4644	uint32_t cr3;
4645	/** EIP before task switch. */
4646	uint32_t eip;
4647	/** EFLAGS before task switch. */
4648	uint32_t eflags;
4649	/** EAX before task switch. */
4650	uint32_t eax;
4651	/** ECX before task switch. */
4652	uint32_t ecx;
4653	/** EDX before task switch. */
4654	uint32_t edx;
4655	/** EBX before task switch. */
4656	uint32_t ebx;
4657	/** ESP before task switch. */
4658	uint32_t esp;
4659	/** EBP before task switch. */
4660	uint32_t ebp;
4661	/** ESI before task switch. */
4662	uint32_t esi;
4663	/** EDI before task switch. */
4664	uint32_t edi;
4665	/** ES before task switch. */
4666	RTSEL es;
4667	uint16_t padding_es;
4668	/** CS before task switch. */
4669	RTSEL cs;
4670	uint16_t padding_cs;
4671	/** SS before task switch. */
4672	RTSEL ss;
4673	uint16_t padding_ss;
4674	/** DS before task switch. */
4675	RTSEL ds;
4676	uint16_t padding_ds;
4677	/** FS before task switch. */
4678	RTSEL fs;
4679	uint16_t padding_fs;
4680	/** GS before task switch. */
4681	RTSEL gs;
4682	uint16_t padding_gs;
4683	/** LDTR before task switch. */
4684	RTSEL selLdt;
4685	uint16_t padding_ldt;
4686	/** Debug trap flag */
4687	uint16_t fDebugTrap;
4688	/** Offset relative to the TSS of the start of the I/O Bitmap
4689	* and the end of the interrupt redirection bitmap. */
4690	uint16_t offIoBitmap;
4691	} X86TSS32;
4692	#pragma pack()
4693	/** Pointer to task segment. */
4694	typedef X86TSS32 *PX86TSS32;
4695	/** Pointer to const task segment. */
4696	typedef const X86TSS32 *PCX86TSS32;
4697	#ifndef VBOX_FOR_DTRACE_LIB
4698	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4699	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4700	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4701	#endif
4702
4703	/**
4704	* 64-bit Task segment.
4705	*/
4706	#pragma pack(1)
4707	typedef struct X86TSS64
4708	{
4709	/** Reserved. */
4710	uint32_t u32Reserved;
4711	/** Ring-0 stack pointer. (static) */
4712	uint64_t rsp0;
4713	/** Ring-1 stack pointer. (static) */
4714	uint64_t rsp1;
4715	/** Ring-2 stack pointer. (static) */
4716	uint64_t rsp2;
4717	/** Reserved. */
4718	uint32_t u32Reserved2[2];
4719	/* IST */
4720	uint64_t ist1;
4721	uint64_t ist2;
4722	uint64_t ist3;
4723	uint64_t ist4;
4724	uint64_t ist5;
4725	uint64_t ist6;
4726	uint64_t ist7;
4727	/* Reserved. */
4728	uint16_t u16Reserved[5];
4729	/** Offset relative to the TSS of the start of the I/O Bitmap
4730	* and the end of the interrupt redirection bitmap. */
4731	uint16_t offIoBitmap;
4732	} X86TSS64;
4733	#pragma pack()
4734	/** Pointer to a 64-bit task segment. */
4735	typedef X86TSS64 *PX86TSS64;
4736	/** Pointer to a const 64-bit task segment. */
4737	typedef const X86TSS64 *PCX86TSS64;
4738	#ifndef VBOX_FOR_DTRACE_LIB
4739	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4740	#endif
4741
4742	/** @} */
4743
4744
4745	/** @name Selectors.
4746	* @{
4747	*/
4748
4749	/**
4750	* The shift used to convert a selector from and to index an index (C).
4751	*/
4752	#define X86_SEL_SHIFT 3
4753
4754	/**
4755	* The mask used to mask off the table indicator and RPL of an selector.
4756	*/
4757	#define X86_SEL_MASK 0xfff8U
4758
4759	/**
4760	* The mask used to mask off the RPL of an selector.
4761	* This is suitable for checking for NULL selectors.
4762	*/
4763	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4764
4765	/**
4766	* The bit indicating that a selector is in the LDT and not in the GDT.
4767	*/
4768	#define X86_SEL_LDT 0x0004U
4769
4770	/**
4771	* The bit mask for getting the RPL of a selector.
4772	*/
4773	#define X86_SEL_RPL 0x0003U
4774
4775	/**
4776	* The mask covering both RPL and LDT.
4777	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4778	* checks.
4779	*/
4780	#define X86_SEL_RPL_LDT 0x0007U
4781
4782	/** @} */
4783
4784
4785	/**
4786	* x86 Exceptions/Faults/Traps.
4787	*/
4788	typedef enum X86XCPT
4789	{
4790	/** \#DE - Divide error. */
4791	X86_XCPT_DE = 0x00,
4792	/** \#DB - Debug event (single step, DRx, ..) */
4793	X86_XCPT_DB = 0x01,
4794	/** NMI - Non-Maskable Interrupt */
4795	X86_XCPT_NMI = 0x02,
4796	/** \#BP - Breakpoint (INT3). */
4797	X86_XCPT_BP = 0x03,
4798	/** \#OF - Overflow (INTO). */
4799	X86_XCPT_OF = 0x04,
4800	/** \#BR - Bound range exceeded (BOUND). */
4801	X86_XCPT_BR = 0x05,
4802	/** \#UD - Undefined opcode. */
4803	X86_XCPT_UD = 0x06,
4804	/** \#NM - Device not available (math coprocessor device). */
4805	X86_XCPT_NM = 0x07,
4806	/** \#DF - Double fault. */
4807	X86_XCPT_DF = 0x08,
4808	/** ??? - Coprocessor segment overrun (obsolete). */
4809	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4810	/** \#TS - Taskswitch (TSS). */
4811	X86_XCPT_TS = 0x0a,
4812	/** \#NP - Segment no present. */
4813	X86_XCPT_NP = 0x0b,
4814	/** \#SS - Stack segment fault. */
4815	X86_XCPT_SS = 0x0c,
4816	/** \#GP - General protection fault. */
4817	X86_XCPT_GP = 0x0d,
4818	/** \#PF - Page fault. */
4819	X86_XCPT_PF = 0x0e,
4820	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4821	/** \#MF - Math fault (FPU). */
4822	X86_XCPT_MF = 0x10,
4823	/** \#AC - Alignment check. */
4824	X86_XCPT_AC = 0x11,
4825	/** \#MC - Machine check. */
4826	X86_XCPT_MC = 0x12,
4827	/** \#XF - SIMD Floating-Point Exception. */
4828	X86_XCPT_XF = 0x13,
4829	/** \#VE - Virtualization Exception (Intel only). */
4830	X86_XCPT_VE = 0x14,
4831	/** \#CP - Control Protection Exception. */
4832	X86_XCPT_CP = 0x15,
4833	/** \#VC - VMM Communication Exception (AMD only). */
4834	X86_XCPT_VC = 0x1d,
4835	/** \#SX - Security Exception (AMD only). */
4836	X86_XCPT_SX = 0x1e
4837	} X86XCPT;
4838	/** Pointer to a x86 exception code. */
4839	typedef X86XCPT *PX86XCPT;
4840	/** Pointer to a const x86 exception code. */
4841	typedef const X86XCPT *PCX86XCPT;
4842	/** The last valid (currently reserved) exception value. */
4843	#define X86_XCPT_LAST 0x1f
4844
4845
4846	/** @name Trap Error Codes
4847	* @{
4848	*/
4849	/** External indicator. */
4850	#define X86_TRAP_ERR_EXTERNAL 1
4851	/** IDT indicator. */
4852	#define X86_TRAP_ERR_IDT 2
4853	/** Descriptor table indicator - If set LDT, if clear GDT. */
4854	#define X86_TRAP_ERR_TI 4
4855	/** Mask for getting the selector. */
4856	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4857	/** Shift for getting the selector table index (C type index). */
4858	#define X86_TRAP_ERR_SEL_SHIFT 3
4859	/** @} */
4860
4861
4862	/** @name \#PF Trap Error Codes
4863	* @{
4864	*/
4865	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4866	#define X86_TRAP_PF_P RT_BIT_32(0)
4867	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4868	#define X86_TRAP_PF_RW RT_BIT_32(1)
4869	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4870	#define X86_TRAP_PF_US RT_BIT_32(2)
4871	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4872	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4873	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4874	#define X86_TRAP_PF_ID RT_BIT_32(4)
4875	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4876	#define X86_TRAP_PF_PK RT_BIT_32(5)
4877	/** @} */
4878
4879	#pragma pack(1)
4880	/**
4881	* 16-bit IDTR.
4882	*/
4883	typedef struct X86IDTR16
4884	{
4885	/** Offset. */
4886	uint16_t offSel;
4887	/** Selector. */
4888	uint16_t uSel;
4889	} X86IDTR16, *PX86IDTR16;
4890	#pragma pack()
4891
4892	#pragma pack(1)
4893	/**
4894	* 32-bit IDTR/GDTR.
4895	*/
4896	typedef struct X86XDTR32
4897	{
4898	/** Size of the descriptor table. */
4899	uint16_t cb;
4900	/** Address of the descriptor table. */
4901	#ifndef VBOX_FOR_DTRACE_LIB
4902	uint32_t uAddr;
4903	#else
4904	uint16_t au16Addr[2];
4905	#endif
4906	} X86XDTR32, *PX86XDTR32;
4907	#pragma pack()
4908
4909	#pragma pack(1)
4910	/**
4911	* 64-bit IDTR/GDTR.
4912	*/
4913	typedef struct X86XDTR64
4914	{
4915	/** Size of the descriptor table. */
4916	uint16_t cb;
4917	/** Address of the descriptor table. */
4918	#ifndef VBOX_FOR_DTRACE_LIB
4919	uint64_t uAddr;
4920	#else
4921	uint16_t au16Addr[4];
4922	#endif
4923	} X86XDTR64, *PX86XDTR64;
4924	#pragma pack()
4925
4926
4927	/** @name ModR/M
4928	* @{ */
4929	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4930	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4931	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4932	#define X86_MODRM_REG_SHIFT 3
4933	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4934	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4935	#define X86_MODRM_MOD_SHIFT 6
4936
4937	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
4938	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
4939	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
4940	#define X86_MOD_REG 3 /*< Registers. /
4941
4942	#ifndef VBOX_FOR_DTRACE_LIB
4943	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4944	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4945	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4946	/** @def X86_MODRM_MAKE
4947	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
4948	* @param a_Reg The register value (0..7).
4949	* @param a_RegMem The register or memory value (0..7). */
4950	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4951	#endif
4952
4953	/** @} */
4954
4955	/** @name SIB
4956	* @{ */
4957	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4958	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4959	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4960	#define X86_SIB_INDEX_SHIFT 3
4961	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4962	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4963	#define X86_SIB_SCALE_SHIFT 6
4964	#ifndef VBOX_FOR_DTRACE_LIB
4965	/** @def X86_SIB_MAKE
4966	* @param a_BaseReg The base register value (0..7).
4967	* @param a_IndexReg The index register value (0..7).
4968	* @param a_Scale The left shift (0..3) to be applied to the index
4969	* register (0 = none, 1 = x2, 2 = x4, 3 = x8).
4970	* */
4971	# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
4972	(((a_Scale) << X86_SIB_SCALE_SHIFT) \| ((a_IndexReg) << X86_SIB_INDEX_SHIFT) \| (a_BaseReg))
4973
4974	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4975	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4976	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4977	#endif
4978	/** @} */
4979
4980	/** @name General register indexes.
4981	* @{ */
4982	#define X86_GREG_xAX 0
4983	#define X86_GREG_xCX 1
4984	#define X86_GREG_xDX 2
4985	#define X86_GREG_xBX 3
4986	#define X86_GREG_xSP 4
4987	#define X86_GREG_xBP 5
4988	#define X86_GREG_xSI 6
4989	#define X86_GREG_xDI 7
4990	#define X86_GREG_x8 8
4991	#define X86_GREG_x9 9
4992	#define X86_GREG_x10 10
4993	#define X86_GREG_x11 11
4994	#define X86_GREG_x12 12
4995	#define X86_GREG_x13 13
4996	#define X86_GREG_x14 14
4997	#define X86_GREG_x15 15
4998	/** @} */
4999	/** General register count. */
5000	#define X86_GREG_COUNT 16
5001
5002	/** @name X86_SREG_XXX - Segment register indexes.
5003	* @{ */
5004	#define X86_SREG_ES 0
5005	#define X86_SREG_CS 1
5006	#define X86_SREG_SS 2
5007	#define X86_SREG_DS 3
5008	#define X86_SREG_FS 4
5009	#define X86_SREG_GS 5
5010	/** @} */
5011	/** Segment register count. */
5012	#define X86_SREG_COUNT 6
5013
5014
5015	/** @name X86_OP_XXX - Prefixes
5016	* @{ */
5017	#define X86_OP_PRF_CS UINT8_C(0x2e)
5018	#define X86_OP_PRF_SS UINT8_C(0x36)
5019	#define X86_OP_PRF_DS UINT8_C(0x3e)
5020	#define X86_OP_PRF_ES UINT8_C(0x26)
5021	#define X86_OP_PRF_FS UINT8_C(0x64)
5022	#define X86_OP_PRF_GS UINT8_C(0x65)
5023	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5024	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5025	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5026	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5027	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5028	#define X86_OP_REX UINT8_C(0x40)
5029	#define X86_OP_REX_B UINT8_C(0x41)
5030	#define X86_OP_REX_X UINT8_C(0x42)
5031	#define X86_OP_REX_R UINT8_C(0x44)
5032	#define X86_OP_REX_W UINT8_C(0x48)
5033	/** @} */
5034
5035
5036	/** @} */
5037
5038	#endif /* !IPRT_INCLUDED_x86_h */
5039

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