x86.h@ 106472

Last change on this file since 106472 was 106472, checked in by vboxsync, 6 weeks ago
Fix ancient macro typo (fortunately, not used by any code); bugref:9898 I suppose
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 205.3 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# ifndef __ASSEMBLER__
46	# include <iprt/types.h>
47	# include <iprt/assert.h>
48	# else
49	# include <iprt/stdint.h>
50	# include <iprt/assertcompile.h>
51	# endif
52	#else
53	# pragma D depends_on library vbox-types.d
54	#endif
55
56	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
57	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
58	#ifdef RT_OS_SOLARIS
59	# undef CS
60	# undef DS
61	# undef MSR_IA32_FLUSH_CMD
62	# undef MSR_AMD_VIRT_SPEC_CTL
63	#endif
64
65	/** @defgroup grp_rt_x86 x86 Types and Definitions
66	* @ingroup grp_rt
67	* @{
68	*/
69
70	#ifndef __ASSEMBLER__
71
72	# ifndef VBOX_FOR_DTRACE_LIB
73	/**
74	* EFLAGS Bits.
75	*/
76	typedef struct X86EFLAGSBITS
77	{
78	/** Bit 0 - CF - Carry flag - Status flag. */
79	unsigned u1CF : 1;
80	/** Bit 1 - 1 - Reserved flag. */
81	unsigned u1Reserved0 : 1;
82	/** Bit 2 - PF - Parity flag - Status flag. */
83	unsigned u1PF : 1;
84	/** Bit 3 - 0 - Reserved flag. */
85	unsigned u1Reserved1 : 1;
86	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
87	unsigned u1AF : 1;
88	/** Bit 5 - 0 - Reserved flag. */
89	unsigned u1Reserved2 : 1;
90	/** Bit 6 - ZF - Zero flag - Status flag. */
91	unsigned u1ZF : 1;
92	/** Bit 7 - SF - Signed flag - Status flag. */
93	unsigned u1SF : 1;
94	/** Bit 8 - TF - Trap flag - System flag. */
95	unsigned u1TF : 1;
96	/** Bit 9 - IF - Interrupt flag - System flag. */
97	unsigned u1IF : 1;
98	/** Bit 10 - DF - Direction flag - Control flag. */
99	unsigned u1DF : 1;
100	/** Bit 11 - OF - Overflow flag - Status flag. */
101	unsigned u1OF : 1;
102	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
103	unsigned u2IOPL : 2;
104	/** Bit 14 - NT - Nested task flag - System flag. */
105	unsigned u1NT : 1;
106	/** Bit 15 - 0 - Reserved flag. */
107	unsigned u1Reserved3 : 1;
108	/** Bit 16 - RF - Resume flag - System flag. */
109	unsigned u1RF : 1;
110	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
111	unsigned u1VM : 1;
112	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
113	unsigned u1AC : 1;
114	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
115	unsigned u1VIF : 1;
116	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
117	unsigned u1VIP : 1;
118	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
119	unsigned u1ID : 1;
120	/** Bit 22-31 - 0 - Reserved flag. */
121	unsigned u10Reserved4 : 10;
122	} X86EFLAGSBITS;
123	/** Pointer to EFLAGS bits. */
124	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
125	/** Pointer to const EFLAGS bits. */
126	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
127	# endif /* !VBOX_FOR_DTRACE_LIB */
128
129	/**
130	* EFLAGS.
131	*/
132	typedef union X86EFLAGS
133	{
134	/** The plain unsigned view. */
135	uint32_t u;
136	# ifndef VBOX_FOR_DTRACE_LIB
137	/** The bitfield view. */
138	X86EFLAGSBITS Bits;
139	# endif
140	/** The 8-bit view. */
141	uint8_t au8[4];
142	/** The 16-bit view. */
143	uint16_t au16[2];
144	/** The 32-bit view. */
145	uint32_t au32[1];
146	/** The 32-bit view. */
147	uint32_t u32;
148	} X86EFLAGS;
149	/** Pointer to EFLAGS. */
150	typedef X86EFLAGS *PX86EFLAGS;
151	/** Pointer to const EFLAGS. */
152	typedef const X86EFLAGS *PCX86EFLAGS;
153
154	/**
155	* RFLAGS (32 upper bits are reserved).
156	*/
157	typedef union X86RFLAGS
158	{
159	/** The plain unsigned view. */
160	uint64_t u;
161	# ifndef VBOX_FOR_DTRACE_LIB
162	/** The bitfield view. */
163	X86EFLAGSBITS Bits;
164	# endif
165	/** The 8-bit view. */
166	uint8_t au8[8];
167	/** The 16-bit view. */
168	uint16_t au16[4];
169	/** The 32-bit view. */
170	uint32_t au32[2];
171	/** The 64-bit view. */
172	uint64_t au64[1];
173	/** The 64-bit view. */
174	uint64_t u64;
175	} X86RFLAGS;
176	/** Pointer to RFLAGS. */
177	typedef X86RFLAGS *PX86RFLAGS;
178	/** Pointer to const RFLAGS. */
179	typedef const X86RFLAGS *PCX86RFLAGS;
180
181	#endif /* !__ASSEMBLER__ */
182
183
184	/** @name EFLAGS
185	* @{
186	*/
187	/** Bit 0 - CF - Carry flag - Status flag. */
188	#define X86_EFL_CF RT_BIT_32(0)
189	#define X86_EFL_CF_BIT 0
190	/** Bit 1 - Reserved, reads as 1. */
191	#define X86_EFL_1 RT_BIT_32(1)
192	#define X86_EFL_1_BIT 1
193	/** Bit 2 - PF - Parity flag - Status flag. */
194	#define X86_EFL_PF RT_BIT_32(2)
195	#define X86_EFL_PF_BIT 2
196	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
197	#define X86_EFL_AF RT_BIT_32(4)
198	#define X86_EFL_AF_BIT 4
199	/** Bit 6 - ZF - Zero flag - Status flag. */
200	#define X86_EFL_ZF RT_BIT_32(6)
201	#define X86_EFL_ZF_BIT 6
202	/** Bit 7 - SF - Signed flag - Status flag. */
203	#define X86_EFL_SF RT_BIT_32(7)
204	#define X86_EFL_SF_BIT 7
205	/** Bit 8 - TF - Trap flag - System flag. */
206	#define X86_EFL_TF RT_BIT_32(8)
207	#define X86_EFL_TF_BIT 8
208	/** Bit 9 - IF - Interrupt flag - System flag. */
209	#define X86_EFL_IF RT_BIT_32(9)
210	#define X86_EFL_IF_BIT 9
211	/** Bit 10 - DF - Direction flag - Control flag. */
212	#define X86_EFL_DF RT_BIT_32(10)
213	#define X86_EFL_DF_BIT 10
214	/** Bit 11 - OF - Overflow flag - Status flag. */
215	#define X86_EFL_OF RT_BIT_32(11)
216	#define X86_EFL_OF_BIT 11
217	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
218	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
219	/** Bit 14 - NT - Nested task flag - System flag. */
220	#define X86_EFL_NT RT_BIT_32(14)
221	#define X86_EFL_NT_BIT 14
222	/** Bit 16 - RF - Resume flag - System flag. */
223	#define X86_EFL_RF RT_BIT_32(16)
224	#define X86_EFL_RF_BIT 16
225	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
226	#define X86_EFL_VM RT_BIT_32(17)
227	#define X86_EFL_VM_BIT 17
228	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
229	#define X86_EFL_AC RT_BIT_32(18)
230	#define X86_EFL_AC_BIT 18
231	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
232	#define X86_EFL_VIF RT_BIT_32(19)
233	#define X86_EFL_VIF_BIT 19
234	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
235	#define X86_EFL_VIP RT_BIT_32(20)
236	#define X86_EFL_VIP_BIT 20
237	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
238	#define X86_EFL_ID RT_BIT_32(21)
239	#define X86_EFL_ID_BIT 21
240	/** All live bits. */
241	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
242	/** Read as 1 bits. */
243	#define X86_EFL_RA1_MASK RT_BIT_32(1)
244	/** Read as 0 bits, excluding bits 31:22.
245	* Bits 3, 5, 15, and 22 thru 31. */
246	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
247	/** Read as 0 bits, excluding bits 31:22.
248	* Bits 3, 5 and 15. */
249	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
250	/** IOPL shift. */
251	#define X86_EFL_IOPL_SHIFT 12
252	/** The IOPL level from the flags. */
253	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
254	/** Bits restored by popf */
255	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
256	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
257	/** Bits restored by popf */
258	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
259	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
260	/** The status bits commonly updated by arithmetic instructions. */
261	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
262	/** @} */
263
264
265	#ifndef __ASSEMBLER__
266
267	/** CPUID Feature information - ECX.
268	* CPUID query with EAX=1.
269	*/
270	# ifndef VBOX_FOR_DTRACE_LIB
271	typedef struct X86CPUIDFEATECX
272	{
273	/** Bit 0 - SSE3 - Supports SSE3 or not. */
274	unsigned u1SSE3 : 1;
275	/** Bit 1 - PCLMULQDQ. */
276	unsigned u1PCLMULQDQ : 1;
277	/** Bit 2 - DS Area 64-bit layout. */
278	unsigned u1DTE64 : 1;
279	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
280	unsigned u1Monitor : 1;
281	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
282	unsigned u1CPLDS : 1;
283	/** Bit 5 - VMX - Virtual Machine Technology. */
284	unsigned u1VMX : 1;
285	/** Bit 6 - SMX: Safer Mode Extensions. */
286	unsigned u1SMX : 1;
287	/** Bit 7 - EST - Enh. SpeedStep Tech. */
288	unsigned u1EST : 1;
289	/** Bit 8 - TM2 - Terminal Monitor 2. */
290	unsigned u1TM2 : 1;
291	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
292	unsigned u1SSSE3 : 1;
293	/** Bit 10 - CNTX-ID - L1 Context ID. */
294	unsigned u1CNTXID : 1;
295	/** Bit 11 - Reserved. */
296	unsigned u1Reserved1 : 1;
297	/** Bit 12 - FMA. */
298	unsigned u1FMA : 1;
299	/** Bit 13 - CX16 - CMPXCHG16B. */
300	unsigned u1CX16 : 1;
301	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
302	unsigned u1TPRUpdate : 1;
303	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
304	unsigned u1PDCM : 1;
305	/** Bit 16 - Reserved. */
306	unsigned u1Reserved2 : 1;
307	/** Bit 17 - PCID - Process-context identifiers. */
308	unsigned u1PCID : 1;
309	/** Bit 18 - Direct Cache Access. */
310	unsigned u1DCA : 1;
311	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
312	unsigned u1SSE4_1 : 1;
313	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
314	unsigned u1SSE4_2 : 1;
315	/** Bit 21 - x2APIC. */
316	unsigned u1x2APIC : 1;
317	/** Bit 22 - MOVBE - Supports MOVBE. */
318	unsigned u1MOVBE : 1;
319	/** Bit 23 - POPCNT - Supports POPCNT. */
320	unsigned u1POPCNT : 1;
321	/** Bit 24 - TSC-Deadline. */
322	unsigned u1TSCDEADLINE : 1;
323	/** Bit 25 - AES. */
324	unsigned u1AES : 1;
325	/** Bit 26 - XSAVE - Supports XSAVE. */
326	unsigned u1XSAVE : 1;
327	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
328	unsigned u1OSXSAVE : 1;
329	/** Bit 28 - AVX - Supports AVX instruction extensions. */
330	unsigned u1AVX : 1;
331	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
332	unsigned u1F16C : 1;
333	/** Bit 30 - RDRAND - Supports RDRAND. */
334	unsigned u1RDRAND : 1;
335	/** Bit 31 - Hypervisor present (we're a guest). */
336	unsigned u1HVP : 1;
337	} X86CPUIDFEATECX;
338	# else /* VBOX_FOR_DTRACE_LIB */
339	typedef uint32_t X86CPUIDFEATECX;
340	# endif /* VBOX_FOR_DTRACE_LIB */
341	/** Pointer to CPUID Feature Information - ECX. */
342	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
343	/** Pointer to const CPUID Feature Information - ECX. */
344	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
345
346
347	/** CPUID Feature Information - EDX.
348	* CPUID query with EAX=1.
349	*/
350	# ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
351	typedef struct X86CPUIDFEATEDX
352	{
353	/** Bit 0 - FPU - x87 FPU on Chip. */
354	unsigned u1FPU : 1;
355	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
356	unsigned u1VME : 1;
357	/** Bit 2 - DE - Debugging extensions. */
358	unsigned u1DE : 1;
359	/** Bit 3 - PSE - Page Size Extension. */
360	unsigned u1PSE : 1;
361	/** Bit 4 - TSC - Time Stamp Counter. */
362	unsigned u1TSC : 1;
363	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
364	unsigned u1MSR : 1;
365	/** Bit 6 - PAE - Physical Address Extension. */
366	unsigned u1PAE : 1;
367	/** Bit 7 - MCE - Machine Check Exception. */
368	unsigned u1MCE : 1;
369	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
370	unsigned u1CX8 : 1;
371	/** Bit 9 - APIC - APIC On-Chip. */
372	unsigned u1APIC : 1;
373	/** Bit 10 - Reserved. */
374	unsigned u1Reserved1 : 1;
375	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
376	unsigned u1SEP : 1;
377	/** Bit 12 - MTRR - Memory Type Range Registers. */
378	unsigned u1MTRR : 1;
379	/** Bit 13 - PGE - PTE Global Bit. */
380	unsigned u1PGE : 1;
381	/** Bit 14 - MCA - Machine Check Architecture. */
382	unsigned u1MCA : 1;
383	/** Bit 15 - CMOV - Conditional Move Instructions. */
384	unsigned u1CMOV : 1;
385	/** Bit 16 - PAT - Page Attribute Table. */
386	unsigned u1PAT : 1;
387	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
388	unsigned u1PSE36 : 1;
389	/** Bit 18 - PSN - Processor Serial Number. */
390	unsigned u1PSN : 1;
391	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
392	unsigned u1CLFSH : 1;
393	/** Bit 20 - Reserved. */
394	unsigned u1Reserved2 : 1;
395	/** Bit 21 - DS - Debug Store. */
396	unsigned u1DS : 1;
397	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
398	unsigned u1ACPI : 1;
399	/** Bit 23 - MMX - Intel MMX 'Technology'. */
400	unsigned u1MMX : 1;
401	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
402	unsigned u1FXSR : 1;
403	/** Bit 25 - SSE - SSE Support. */
404	unsigned u1SSE : 1;
405	/** Bit 26 - SSE2 - SSE2 Support. */
406	unsigned u1SSE2 : 1;
407	/** Bit 27 - SS - Self Snoop. */
408	unsigned u1SS : 1;
409	/** Bit 28 - HTT - Hyper-Threading Technology. */
410	unsigned u1HTT : 1;
411	/** Bit 29 - TM - Thermal Monitor. */
412	unsigned u1TM : 1;
413	/** Bit 30 - Reserved - . */
414	unsigned u1Reserved3 : 1;
415	/** Bit 31 - PBE - Pending Break Enabled. */
416	unsigned u1PBE : 1;
417	} X86CPUIDFEATEDX;
418	# else /* VBOX_FOR_DTRACE_LIB */
419	typedef uint32_t X86CPUIDFEATEDX;
420	# endif /* VBOX_FOR_DTRACE_LIB */
421	/** Pointer to CPUID Feature Information - EDX. */
422	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
423	/** Pointer to const CPUID Feature Information - EDX. */
424	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
425
426	#endif /* !__ASSEMBLER__ */
427
428
429	/** @name CPUID Vendor information.
430	* CPUID query with EAX=0.
431	* @{
432	*/
433	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
434	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
435	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
436
437	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
438	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
439	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
440
441	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
442	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
443	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
444
445	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
446	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
447	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
448
449	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
450	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
451	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
452	/** @} */
453
454
455	/** @name CPUID Feature information.
456	* CPUID query with EAX=1.
457	* @{
458	*/
459	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
460	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
461	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
462	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
463	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
464	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
465	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
466	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
467	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
468	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
469	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
470	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
471	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
472	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
473	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
474	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
475	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
476	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
477	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
478	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
479	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
480	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
481	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
482	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
483	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
484	/** ECX Bit 12 - FMA. */
485	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
486	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
487	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
488	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
489	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
490	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
491	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
492	/** ECX Bit 17 - PCID - Process-context identifiers. */
493	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
494	/** ECX Bit 18 - DCA - Direct Cache Access. */
495	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
496	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
497	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
498	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
499	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
500	/** ECX Bit 21 - x2APIC support. */
501	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
502	/** ECX Bit 22 - MOVBE instruction. */
503	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
504	/** ECX Bit 23 - POPCNT instruction. */
505	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
506	/** ECX Bir 24 - TSC-Deadline. */
507	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
508	/** ECX Bit 25 - AES instructions. */
509	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
510	/** ECX Bit 26 - XSAVE instruction. */
511	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
512	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
513	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
514	/** ECX Bit 28 - AVX. */
515	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
516	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
517	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
518	/** ECX Bit 30 - RDRAND instruction. */
519	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
520	/** ECX Bit 31 - Hypervisor Present (software only). */
521	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
522
523
524	/** Bit 0 - FPU - x87 FPU on Chip. */
525	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
526	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
527	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
528	/** Bit 2 - DE - Debugging extensions. */
529	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
530	/** Bit 3 - PSE - Page Size Extension. */
531	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
532	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
533	/** Bit 4 - TSC - Time Stamp Counter. */
534	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
535	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
536	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
537	/** Bit 6 - PAE - Physical Address Extension. */
538	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
539	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
540	/** Bit 7 - MCE - Machine Check Exception. */
541	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
542	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
543	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
544	/** Bit 9 - APIC - APIC On-Chip. */
545	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
546	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
547	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
548	/** Bit 12 - MTRR - Memory Type Range Registers. */
549	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
550	/** Bit 13 - PGE - PTE Global Bit. */
551	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
552	/** Bit 14 - MCA - Machine Check Architecture. */
553	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
554	/** Bit 15 - CMOV - Conditional Move Instructions. */
555	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
556	/** Bit 16 - PAT - Page Attribute Table. */
557	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
558	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
559	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
560	/** Bit 18 - PSN - Processor Serial Number. */
561	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
562	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
563	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
564	/** Bit 21 - DS - Debug Store. */
565	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
566	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
567	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
568	/** Bit 23 - MMX - Intel MMX Technology. */
569	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
570	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
571	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
572	/** Bit 25 - SSE - SSE Support. */
573	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
574	/** Bit 26 - SSE2 - SSE2 Support. */
575	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
576	/** Bit 27 - SS - Self Snoop. */
577	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
578	/** Bit 28 - HTT - Hyper-Threading Technology. */
579	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
580	/** Bit 29 - TM - Therm. Monitor. */
581	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
582	/** Bit 31 - PBE - Pending Break Enabled. */
583	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
584	/** @} */
585
586	/** @name CPUID mwait/monitor information.
587	* CPUID query with EAX=5.
588	* @{
589	*/
590	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
591	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
592	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
593	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
594	/** @} */
595
596
597	/** @name CPUID Thermal and Power Management information.
598	* Generally Intel only unless noted otherwise.
599	* CPUID query with EAX=5. @{
600	*/
601	/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
602	#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
603	/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
604	#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
605	/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
606	#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
607	/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
608	#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
609	/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
610	#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
611	/** EAX Bit 6 - PTM - Package Thermal Management supported. */
612	#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
613	/** EAX Bit 7 - HWP - HWP base MSRs supported. */
614	#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
615	/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
616	#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
617	/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
618	#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
619	/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
620	#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
621	/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
622	#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
623	/** EAX Bit 13 - HDC - HDC base MSRs supported. */
624	#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
625	/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
626	#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
627	/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
628	#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
629	/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
630	#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
631	/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
632	#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
633
634	/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
635	#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
636	/** @} */
637
638
639	/** @name CPUID Structured Extended Feature information.
640	* CPUID query with EAX=7.
641	* @{
642	*/
643	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
644	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
645	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
646	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
647	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
648	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
649	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
650	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
651	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
652	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
653	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
654	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
655	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
656	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
657	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
658	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
659	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
660	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
661	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
662	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
663	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
664	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
665	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
666	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
667	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
668	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
669	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
670	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
671	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
672	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
673	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
674	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
675	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
676	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
677	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
678	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
679	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
680	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
681	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
682	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
683	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
684	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
685	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
686	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
687	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
688	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
689	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
690	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
691	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
692	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
693	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
694	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
695
696	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
697	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
698	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
699	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
700	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
701	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
702	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
703	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
704	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
705	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
706	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
707	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
708	/** ECX Bit 22 - RDPID - Support pread process ID. */
709	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
710	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
711	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
712
713	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
714	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
715	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
716	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
717	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
718	* IBPB command in IA32_PRED_CMD. */
719	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
720	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
721	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
722	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
723	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
724	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
725	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
726	/** EDX Bit 30 - CORECAP - Supports the IA32_CORE_CAPABILITIES MSR. */
727	#define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
728	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
729	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
730
731	/** @} */
732
733
734	/** @name CPUID Extended Feature information.
735	* CPUID query with EAX=0x80000001.
736	* @{
737	*/
738	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
739	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
740
741	/** EDX Bit 11 - SYSCALL/SYSRET. */
742	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
743	/** EDX Bit 20 - No-Execute/Execute-Disable. */
744	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
745	/** EDX Bit 26 - 1 GB large page. */
746	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
747	/** EDX Bit 27 - RDTSCP. */
748	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
749	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
750	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
751	/** @}*/
752
753	/** @name CPUID AMD Feature information.
754	* CPUID query with EAX=0x80000001.
755	* @{
756	*/
757	/** Bit 0 - FPU - x87 FPU on Chip. */
758	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
759	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
760	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
761	/** Bit 2 - DE - Debugging extensions. */
762	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
763	/** Bit 3 - PSE - Page Size Extension. */
764	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
765	/** Bit 4 - TSC - Time Stamp Counter. */
766	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
767	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
768	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
769	/** Bit 6 - PAE - Physical Address Extension. */
770	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
771	/** Bit 7 - MCE - Machine Check Exception. */
772	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
773	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
774	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
775	/** Bit 9 - APIC - APIC On-Chip. */
776	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
777	/** Bit 12 - MTRR - Memory Type Range Registers. */
778	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
779	/** Bit 13 - PGE - PTE Global Bit. */
780	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
781	/** Bit 14 - MCA - Machine Check Architecture. */
782	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
783	/** Bit 15 - CMOV - Conditional Move Instructions. */
784	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
785	/** Bit 16 - PAT - Page Attribute Table. */
786	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
787	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
788	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
789	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
790	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
791	/** Bit 23 - MMX - Intel MMX Technology. */
792	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
793	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
794	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
795	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
796	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
797	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
798	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
799	/** Bit 31 - 3DNOW - AMD 3DNow. */
800	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
801
802	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
803	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
804	/** Bit 2 - SVM - AMD VM extensions. */
805	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
806	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
807	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
808	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
809	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
810	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
811	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
812	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
813	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
814	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
815	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
816	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
817	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
818	/** Bit 9 - OSVW - AMD OS visible workaround. */
819	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
820	/** Bit 10 - IBS - Instruct based sampling. */
821	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
822	/** Bit 11 - XOP - Extended operation support (see APM6). */
823	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
824	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
825	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
826	/** Bit 13 - WDT - AMD Watchdog timer support. */
827	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
828	/** Bit 15 - LWP - Lightweight profiling support. */
829	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
830	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
831	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
832	/** Bit 19 - NodeId - Indicates support for
833	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
834	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
835	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
836	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
837	/** Bit 22 - TopologyExtensions - . */
838	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
839	/** @} */
840
841
842	/** @name CPUID AMD Feature information.
843	* CPUID query with EAX=0x80000007.
844	* @{
845	*/
846	/** Bit 0 - TS - Temperature Sensor. */
847	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
848	/** Bit 1 - FID - Frequency ID Control. */
849	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
850	/** Bit 2 - VID - Voltage ID Control. */
851	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
852	/** Bit 3 - TTP - THERMTRIP. */
853	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
854	/** Bit 4 - TM - Hardware Thermal Control. */
855	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
856	/** Bit 5 - STC - Software Thermal Control. */
857	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
858	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
859	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
860	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
861	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
862	/** Bit 8 - TSCINVAR - TSC Invariant. */
863	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
864	/** Bit 9 - CPB - TSC Invariant. */
865	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
866	/** Bit 10 - EffFreqRO - MPERF/APERF. */
867	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
868	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
869	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
870	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
871	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
872	/** @} */
873
874
875	/** @name CPUID AMD extended feature extensions ID (EBX).
876	* CPUID query with EAX=0x80000008.
877	* @{
878	*/
879	/** Bit 0 - CLZERO - Clear zero instruction. */
880	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
881	/** Bit 1 - IRPerf - Instructions retired count support. */
882	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
883	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
884	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
885	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
886	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
887	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
888	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
889	/* AMD pipeline length: 9 feature bits ;-) */
890	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
891	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
892	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
893	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
894	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
895	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
896	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
897	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
898	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
899	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
900	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
901	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
902	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
903	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
904	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
905	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
906	/** Bit 26 - Speculative Store Bypass Disable not required. */
907	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
908	/** @} */
909
910
911	/** @name CPUID AMD SVM Feature information.
912	* CPUID query with EAX=0x8000000a.
913	* @{
914	*/
915	/** Bit 0 - NP - Nested Paging supported. */
916	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
917	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
918	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
919	/** Bit 2 - SVML - SVM locking bit supported. */
920	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
921	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
922	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
923	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
924	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
925	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
926	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
927	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
928	* VMCB.TLB_Control is supported. */
929	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
930	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
931	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
932	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
933	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
934	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
935	* intercept filter cycle count threshold. */
936	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
937	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
938	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
939	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
940	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
941	/** Bit 16 - VGIF - Supports virtualized GIF. */
942	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
943	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
944	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
945	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
946	* mode. */
947	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
948	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
949	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
950	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
951	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
952	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
953	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
954	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
955	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
956	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
957	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
958	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
959	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
960	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
961	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
962	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
963	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
964	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
965	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
966	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
967	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
968
969	/** @} */
970
971
972	/** @name CR0
973	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
974	* reserved flags.
975	* @{ */
976	/** Bit 0 - PE - Protection Enabled */
977	#define X86_CR0_PE RT_BIT_32(0)
978	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
979	#define X86_CR0_PE_BIT 0
980	/** Bit 1 - MP - Monitor Coprocessor */
981	#define X86_CR0_MP RT_BIT_32(1)
982	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
983	#define X86_CR0_MP_BIT 1
984	/** Bit 2 - EM - Emulation. */
985	#define X86_CR0_EM RT_BIT_32(2)
986	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
987	#define X86_CR0_EM_BIT 2
988	/** Bit 3 - TS - Task Switch. */
989	#define X86_CR0_TS RT_BIT_32(3)
990	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
991	#define X86_CR0_TS_BIT 3
992	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
993	#define X86_CR0_ET RT_BIT_32(4)
994	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
995	#define X86_CR0_ET_BIT 4
996	/** Bit 5 - NE - Numeric error (486+). */
997	#define X86_CR0_NE RT_BIT_32(5)
998	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
999	#define X86_CR0_NE_BIT 5
1000	/** Bit 16 - WP - Write Protect (486+). */
1001	#define X86_CR0_WP RT_BIT_32(16)
1002	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
1003	#define X86_CR0_WP_BIT 16
1004	/** Bit 18 - AM - Alignment Mask (486+). */
1005	#define X86_CR0_AM RT_BIT_32(18)
1006	#define X86_CR0_ALIGNMENT_MASK RT_BIT_32(18)
1007	#define X86_CR0_AM_BIT 18
1008	/** Bit 29 - NW - Not Write-though (486+). */
1009	#define X86_CR0_NW RT_BIT_32(29)
1010	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
1011	#define X86_CR0_NW_BIT 29
1012	/** Bit 30 - WP - Cache Disable (486+). */
1013	#define X86_CR0_CD RT_BIT_32(30)
1014	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
1015	#define X86_CR0_CD_BIT 30
1016	/** Bit 31 - PG - Paging. */
1017	#define X86_CR0_PG RT_BIT_32(31)
1018	#define X86_CR0_PAGING RT_BIT_32(31)
1019	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
1020	/** @} */
1021
1022
1023	/** @name CR3
1024	* @{ */
1025	/** Bit 3 - PWT - Page-level Writes Transparent. */
1026	#define X86_CR3_PWT RT_BIT_32(3)
1027	#define X86_CR3_PWT_BIT 3
1028	/** Bit 4 - PCD - Page-level Cache Disable. */
1029	#define X86_CR3_PCD RT_BIT_32(4)
1030	#define X86_CR3_PCD_BIT 4
1031	/** Bits 12-31 - - Page directory page number. */
1032	#define X86_CR3_PAGE_MASK (0xfffff000)
1033	/** Bits 5-31 - - PAE Page directory page number. */
1034	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1035	/** Bits 12-51 - - AMD64 PML4 page number.
1036	* @note This is a maxed out mask, the actual acceptable CR3 value can
1037	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1038	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1039	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1040	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1041	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1042	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1043	/** @} */
1044
1045
1046	/** @name CR4
1047	* @{ */
1048	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1049	#define X86_CR4_VME RT_BIT_32(0)
1050	#define X86_CR4_VME_BIT 0
1051	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1052	#define X86_CR4_PVI RT_BIT_32(1)
1053	#define X86_CR4_PVI_BIT 1
1054	/** Bit 2 - TSD - Time Stamp Disable. */
1055	#define X86_CR4_TSD RT_BIT_32(2)
1056	#define X86_CR4_TSD_BIT 2
1057	/** Bit 3 - DE - Debugging Extensions. */
1058	#define X86_CR4_DE RT_BIT_32(3)
1059	#define X86_CR4_DE_BIT 3
1060	/** Bit 4 - PSE - Page Size Extension. */
1061	#define X86_CR4_PSE RT_BIT_32(4)
1062	#define X86_CR4_PSE_BIT 4
1063	/** Bit 5 - PAE - Physical Address Extension. */
1064	#define X86_CR4_PAE RT_BIT_32(5)
1065	#define X86_CR4_PAE_BIT 5
1066	/** Bit 6 - MCE - Machine-Check Enable. */
1067	#define X86_CR4_MCE RT_BIT_32(6)
1068	#define X86_CR4_MCE_BIT 6
1069	/** Bit 7 - PGE - Page Global Enable. */
1070	#define X86_CR4_PGE RT_BIT_32(7)
1071	#define X86_CR4_PGE_BIT 7
1072	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1073	#define X86_CR4_PCE RT_BIT_32(8)
1074	#define X86_CR4_PCE_BIT 8
1075	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1076	#define X86_CR4_OSFXSR RT_BIT_32(9)
1077	#define X86_CR4_OSFXSR_BIT 9
1078	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1079	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1080	#define X86_CR4_OSXMMEEXCPT_BIT 10
1081	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1082	#define X86_CR4_UMIP RT_BIT_32(11)
1083	#define X86_CR4_UMIP_BIT 11
1084	/** Bit 13 - VMXE - VMX mode is enabled. */
1085	#define X86_CR4_VMXE RT_BIT_32(13)
1086	#define X86_CR4_VMXE_BIT 13
1087	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1088	#define X86_CR4_SMXE RT_BIT_32(14)
1089	#define X86_CR4_SMXE_BIT 14
1090	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1091	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1092	#define X86_CR4_FSGSBASE_BIT 16
1093	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1094	#define X86_CR4_PCIDE RT_BIT_32(17)
1095	#define X86_CR4_PCIDE_BIT 17
1096	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1097	* extended states. */
1098	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1099	#define X86_CR4_OSXSAVE_BIT 18
1100	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1101	#define X86_CR4_SMEP RT_BIT_32(20)
1102	#define X86_CR4_SMEP_BIt 20
1103	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1104	#define X86_CR4_SMAP RT_BIT_32(21)
1105	#define X86_CR4_SMAP_BIT 21
1106	/** Bit 22 - PKE - Protection Key Enable. */
1107	#define X86_CR4_PKE RT_BIT_32(22)
1108	#define X86_CR4_PKE_BIT 22
1109	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1110	#define X86_CR4_CET RT_BIT_32(23)
1111	#define X86_CR4_CET_BIT 23
1112	/** @} */
1113
1114
1115	/** @name DR6
1116	* @{ */
1117	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1118	#define X86_DR6_B0 RT_BIT_32(0)
1119	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1120	#define X86_DR6_B1 RT_BIT_32(1)
1121	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1122	#define X86_DR6_B2 RT_BIT_32(2)
1123	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1124	#define X86_DR6_B3 RT_BIT_32(3)
1125	/** Mask of all the Bx bits. */
1126	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1127	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1128	#define X86_DR6_BD RT_BIT_32(13)
1129	/** Bit 14 - BS - Single step */
1130	#define X86_DR6_BS RT_BIT_32(14)
1131	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1132	#define X86_DR6_BT RT_BIT_32(15)
1133	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1134	#define X86_DR6_RTM RT_BIT_32(16)
1135	/** Value of DR6 after powerup/reset. */
1136	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1137	/** Bits which must be 1s in DR6. */
1138	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1139	/** Bits which must be 1s in DR6, when RTM is supported. */
1140	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1141	/** Bits which must be 0s in DR6. */
1142	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1143	/** Bits which must be 0s on writes to DR6. */
1144	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1145	/** @} */
1146
1147	/** Get the DR6.Bx bit for a the given breakpoint. */
1148	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1149
1150
1151	/** @name DR7
1152	* @{ */
1153	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1154	#define X86_DR7_L0 RT_BIT_32(0)
1155	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1156	#define X86_DR7_G0 RT_BIT_32(1)
1157	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1158	#define X86_DR7_L1 RT_BIT_32(2)
1159	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1160	#define X86_DR7_G1 RT_BIT_32(3)
1161	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1162	#define X86_DR7_L2 RT_BIT_32(4)
1163	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1164	#define X86_DR7_G2 RT_BIT_32(5)
1165	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1166	#define X86_DR7_L3 RT_BIT_32(6)
1167	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1168	#define X86_DR7_G3 RT_BIT_32(7)
1169	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1170	#define X86_DR7_LE RT_BIT_32(8)
1171	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1172	#define X86_DR7_GE RT_BIT_32(9)
1173
1174	/** L0, L1, L2, and L3. */
1175	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1176	/** L0, L1, L2, and L3. */
1177	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1178
1179	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1180	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1181	#define X86_DR7_RTM RT_BIT_32(11)
1182	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1183	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1184	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1185	* instruction is executed.
1186	* @see http://www.rcollins.org/secrets/DR7.html */
1187	#define X86_DR7_ICE_IR RT_BIT_32(12)
1188	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1189	* any DR register is accessed. */
1190	#define X86_DR7_GD RT_BIT_32(13)
1191	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1192	* Pentium. */
1193	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1194	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1195	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1196	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1197	#define X86_DR7_RW0_MASK (3 << 16)
1198	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1199	#define X86_DR7_LEN0_MASK (3 << 18)
1200	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1201	#define X86_DR7_RW1_MASK (3 << 20)
1202	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1203	#define X86_DR7_LEN1_MASK (3 << 22)
1204	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1205	#define X86_DR7_RW2_MASK (3 << 24)
1206	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1207	#define X86_DR7_LEN2_MASK (3 << 26)
1208	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1209	#define X86_DR7_RW3_MASK (3 << 28)
1210	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1211	#define X86_DR7_LEN3_MASK (3 << 30)
1212
1213	/** Bits which reads as 1s. */
1214	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1215	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1216	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1217	/** Bits which must be 0s when writing to DR7. */
1218	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1219
1220	/** Calcs the L bit of Nth breakpoint.
1221	* @param iBp The breakpoint number [0..3].
1222	*/
1223	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1224
1225	/** Calcs the G bit of Nth breakpoint.
1226	* @param iBp The breakpoint number [0..3].
1227	*/
1228	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1229
1230	/** Calcs the L and G bits of Nth breakpoint.
1231	* @param iBp The breakpoint number [0..3].
1232	*/
1233	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1234
1235	/** @name Read/Write values.
1236	* @{ */
1237	/** Break on instruction fetch only. */
1238	#define X86_DR7_RW_EO UINT32_C(0)
1239	/** Break on write only. */
1240	#define X86_DR7_RW_WO UINT32_C(1)
1241	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1242	#define X86_DR7_RW_IO UINT32_C(2)
1243	/** Break on read or write (but not instruction fetches). */
1244	#define X86_DR7_RW_RW UINT32_C(3)
1245	/** @} */
1246
1247	/** Shifts a X86_DR7_RW_* value to its right place.
1248	* @param iBp The breakpoint number [0..3].
1249	* @param fRw One of the X86_DR7_RW_* value.
1250	*/
1251	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1252
1253	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1254	* one of the X86_DR7_RW_XXX constants).
1255	*
1256	* @returns X86_DR7_RW_XXX
1257	* @param uDR7 DR7 value
1258	* @param iBp The breakpoint number [0..3].
1259	*/
1260	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1261
1262	/** R/W0, R/W1, R/W2, and R/W3. */
1263	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1264
1265	#ifndef VBOX_FOR_DTRACE_LIB
1266	/** Checks if the RW and LEN fields are set up for an instruction breakpoint.
1267	* @note This does not check if it's enabled. */
1268	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1269	/** Checks if an instruction breakpoint is enabled and configured correctly.
1270	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1271	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1272	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1273	/** Checks if there are any instruction fetch breakpoint types configured in
1274	* the RW and LEN registers and enabled in the Lx/Gx bits.
1275	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1276	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1277	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1278	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1279	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1280	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1281
1282	/** Checks if the RW field is set up for a read-write data breakpoint.
1283	* @note This does not check if it's enabled. */
1284	# define X86_DR7_IS_RW_CFG(a_uDR7, a_iBp) ( ~((a_uDR7) & (UINT32_C(0x00030000) << ((a_iBp) * 4))) == 0)
1285
1286	/** Checks if there are any read-write data breakpoint types configured in the
1287	* RW registers and enabled in the Lx/Gx bits.
1288	*
1289	* @note We don't consider the LEN registers here, even if qword isn't
1290	* techincally valid for older processors - see
1291	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1292	*/
1293	# define X86_DR7_ANY_RW_ENABLED(a_uDR7) \
1294	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00030000)) == UINT32_C(0x00030000)) \
1295	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00300000)) == UINT32_C(0x00300000)) \
1296	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x03000000)) == UINT32_C(0x03000000)) \
1297	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x30000000)) == UINT32_C(0x30000000)) )
1298
1299	/** Checks if the RW field is set up for a write-only or read-write data
1300	* breakpoint.
1301	* @note This does not check if it's enabled. */
1302	# define X86_DR7_IS_W_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x00010000) << ((a_iBp) * 4))) != 0)
1303
1304	/** Checks if there are any read-write or write-only data breakpoint types
1305	* configured in the the RW registers and enabled in the Lx/Gx bits.
1306	*
1307	* @note We don't consider the LEN registers here, even if qword isn't
1308	* techincally valid for older processors - see
1309	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1310	*/
1311	# define X86_DR7_ANY_W_ENABLED(a_uDR7) \
1312	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00010000)) != 0) \
1313	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00100000)) != 0) \
1314	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x01000000)) != 0) \
1315	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x10000000)) != 0) )
1316
1317	/** Checks if there are any I/O breakpoint types configured in the RW
1318	* registers. Does NOT check if these are enabled, sorry. */
1319	# define X86_DR7_ANY_RW_IO(uDR7) \
1320	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1321	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1322	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1323	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1324	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1325	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1326	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1327	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1328	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1329	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1330	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1331
1332	#endif /* !VBOX_FOR_DTRACE_LIB */
1333
1334	/** @name Length values.
1335	* @{ */
1336	#define X86_DR7_LEN_BYTE UINT32_C(0)
1337	#define X86_DR7_LEN_WORD UINT32_C(1)
1338	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1339	#define X86_DR7_LEN_DWORD UINT32_C(3)
1340	/** @} */
1341
1342	/** Shifts a X86_DR7_LEN_* value to its right place.
1343	* @param iBp The breakpoint number [0..3].
1344	* @param cb One of the X86_DR7_LEN_* values.
1345	*/
1346	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1347
1348	/** Fetch the breakpoint length bits from the DR7 value.
1349	* @param uDR7 DR7 value
1350	* @param iBp The breakpoint number [0..3].
1351	*/
1352	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1353
1354	/** Mask used to check if any breakpoints are enabled. */
1355	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1356
1357	/** LEN0, LEN1, LEN2, and LEN3. */
1358	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1359	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1360	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1361
1362	/** Value of DR7 after powerup/reset. */
1363	#define X86_DR7_INIT_VAL 0x400
1364	/** @} */
1365
1366
1367	/** @name Machine Specific Registers
1368	* @{
1369	*/
1370	/** Machine check address register (P5). */
1371	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1372	/** Machine check type register (P5). */
1373	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1374	/** Time Stamp Counter. */
1375	#define MSR_IA32_TSC 0x10
1376	#define MSR_IA32_CESR UINT32_C(0x00000011)
1377	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1378	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1379
1380	#define MSR_IA32_PLATFORM_ID 0x17
1381
1382	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1383	# define MSR_IA32_APICBASE 0x1b
1384	/** Local APIC enabled. */
1385	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1386	/** X2APIC enabled (requires the EN bit to be set). */
1387	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1388	/** The processor is the boot strap processor (BSP). */
1389	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1390	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1391	* width. */
1392	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1393	/** The default physical base address of the APIC. */
1394	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1395	/** Gets the physical base address from the MSR. */
1396	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1397	#endif
1398
1399	/** Memory Control (Intel-specific). */
1400	#define MSR_MEMORY_CTRL 0x33
1401	/** Memory Control - UC-store throttle. */
1402	#define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
1403	/** Memory Control - UC-lock disable. */
1404	#define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
1405	/** Memory Control - Split-lock disable. */
1406	#define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
1407
1408	/** Undocumented intel MSR for reporting thread and core counts.
1409	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1410	* first 16 bits is the thread count. The next 16 bits the core count, except
1411	* on Westmere where it seems it's only the next 4 bits for some reason. */
1412	#define MSR_CORE_THREAD_COUNT 0x35
1413
1414	/** CPU Feature control. */
1415	#define MSR_IA32_FEATURE_CONTROL 0x3A
1416	/** Feature control - Lock MSR from writes (R/W0). */
1417	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1418	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1419	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1420	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1421	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1422	/** Feature control - SENTER local functions enable (R/WL). */
1423	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1424	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1425	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1426	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1427	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1428	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1429	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1430	/** Feature control - SENTER global enable (R/WL). */
1431	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1432	/** Feature control - SGX launch control enable (R/WL). */
1433	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1434	/** Feature control - SGX global enable (R/WL). */
1435	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1436	/** Feature control - LMCE on (R/WL). */
1437	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1438
1439	/** Per-processor TSC adjust MSR. */
1440	#define MSR_IA32_TSC_ADJUST 0x3B
1441
1442	/** Spectre control register.
1443	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1444	#define MSR_IA32_SPEC_CTRL 0x48
1445	/** IBRS - Indirect branch restricted speculation. */
1446	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1447	/** STIBP - Single thread indirect branch predictors. */
1448	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1449	/** SSBD - Speculative Store Bypass Disable. */
1450	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1451
1452	/** Prediction command register.
1453	* Write only, logical processor scope, no state since write only. */
1454	#define MSR_IA32_PRED_CMD 0x49
1455	/** IBPB - Indirect branch prediction barrie when written as 1. */
1456	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1457
1458	/** BIOS update trigger (microcode update). */
1459	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1460
1461	/** BIOS update signature (microcode). */
1462	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1463
1464	/** SMM monitor control. */
1465	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1466	/** SMM control - Valid. */
1467	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1468	/** SMM control - VMXOFF unblocks SMI. */
1469	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1470	/** SMM control - MSEG base physical address. */
1471	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1472
1473	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1474	#define MSR_IA32_SMBASE 0x9E
1475
1476	/** General performance counter no. 0. */
1477	#define MSR_IA32_PMC0 0xC1
1478	/** General performance counter no. 1. */
1479	#define MSR_IA32_PMC1 0xC2
1480	/** General performance counter no. 2. */
1481	#define MSR_IA32_PMC2 0xC3
1482	/** General performance counter no. 3. */
1483	#define MSR_IA32_PMC3 0xC4
1484	/** General performance counter no. 4. */
1485	#define MSR_IA32_PMC4 0xC5
1486	/** General performance counter no. 5. */
1487	#define MSR_IA32_PMC5 0xC6
1488	/** General performance counter no. 6. */
1489	#define MSR_IA32_PMC6 0xC7
1490	/** General performance counter no. 7. */
1491	#define MSR_IA32_PMC7 0xC8
1492
1493	/** Nehalem power control. */
1494	#define MSR_IA32_PLATFORM_INFO 0xCE
1495
1496	/** Core Capabilities (Intel-specific). */
1497	#define MSR_IA32_CORE_CAPABILITIES 0xCF
1498	/** STLB QoS feature supported. */
1499	#define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
1500	/** FUSA feature supported. */
1501	#define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
1502	/** RSM instruction only allowed in CPL 0. */
1503	#define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
1504	/** UC lock disable supported. */
1505	#define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
1506	/** Split-lock disable supported. */
1507	#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
1508	/** Snoop filter QoS Mask MSRs supported. */
1509	#define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
1510	/** UC store throttling supported. */
1511	#define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
1512
1513	/** Get FSB clock status (Intel-specific). */
1514	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1515
1516	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1517	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1518
1519	/** C0 Maximum Frequency Clock Count */
1520	#define MSR_IA32_MPERF 0xE7
1521	/** C0 Actual Frequency Clock Count */
1522	#define MSR_IA32_APERF 0xE8
1523
1524	/** MTRR Capabilities. */
1525	#define MSR_IA32_MTRR_CAP 0xFE
1526	/** Bits 0-7 - VCNT - Variable range registers count. */
1527	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1528	/** Bit 8 - FIX - Fixed range registers supported. */
1529	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1530	/** Bit 10 - WC - Write-Combining memory type supported. */
1531	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1532	/** Bit 11 - SMRR - System Management Range Register supported. */
1533	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1534	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1535	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1536
1537
1538	#ifndef __ASSEMBLER__
1539	/**
1540	* Variable-range MTRR MSR pair.
1541	*/
1542	typedef struct X86MTRRVAR
1543	{
1544	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1545	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1546	} X86MTRRVAR;
1547	# ifndef VBOX_FOR_DTRACE_LIB
1548	AssertCompileSize(X86MTRRVAR, 16);
1549	# endif
1550	/** Pointer to a variable-range MTRR MSR pair. */
1551	typedef X86MTRRVAR *PX86MTRRVAR;
1552	/** Pointer to a const variable-range MTRR MSR pair. */
1553	typedef const X86MTRRVAR *PCX86MTRRVAR;
1554	#endif /* __ASSEMBLER__ */
1555
1556
1557	/** Memory types that can be encoded in MTRRs.
1558	* @{ */
1559	/** Uncacheable. */
1560	#define X86_MTRR_MT_UC 0
1561	/** Write Combining. */
1562	#define X86_MTRR_MT_WC 1
1563	/** Write-through. */
1564	#define X86_MTRR_MT_WT 4
1565	/** Write-protected. */
1566	#define X86_MTRR_MT_WP 5
1567	/** Writeback. */
1568	#define X86_MTRR_MT_WB 6
1569	/** @}*/
1570
1571	/** Architecture capabilities (bugfixes). */
1572	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1573	/** CPU is no subject to meltdown problems. */
1574	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1575	/** CPU has better IBRS and you can leave it on all the time. */
1576	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1577	/** CPU has return stack buffer (RSB) override. */
1578	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1579	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1580	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1581	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1582	/** CPU does not suffer from speculative store bypass (SSB) issues. */
1583	#define MSR_IA32_ARCH_CAP_F_SSB_NO RT_BIT_32(4)
1584	/** CPU does not suffer from microarchitectural data sampling (MDS) issues. */
1585	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(5)
1586	/** CPU does not suffer MCE after change code page size w/o invlpg issues. */
1587	#define MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO RT_BIT_32(6)
1588	/** CPU has RTM_DISABLE and TXS_CPUID_CLEAR support. */
1589	#define MSR_IA32_ARCH_CAP_F_TSX_CTRL RT_BIT_32(7)
1590	/** CPU does not suffer from transaction synchronization extensions (TSX)
1591	* asyncrhonous abort (TAA) issues. */
1592	#define MSR_IA32_ARCH_CAP_F_TAA_NO RT_BIT_32(8)
1593	/* 9 is 'reserved' */
1594	#define MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS RT_BIT_32(10)
1595	#define MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL RT_BIT_32(11)
1596	#define MSR_IA32_ARCH_CAP_F_DOITM RT_BIT_32(12)
1597	#define MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO RT_BIT_32(13)
1598	#define MSR_IA32_ARCH_CAP_F_FBSDP_NO RT_BIT_32(14)
1599	#define MSR_IA32_ARCH_CAP_F_PSDP_NO RT_BIT_32(15)
1600	/* 16 is 'reserved' */
1601	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR RT_BIT_32(17)
1602	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL RT_BIT_32(18)
1603	#define MSR_IA32_ARCH_CAP_F_RRSBA RT_BIT_32(19)
1604	#define MSR_IA32_ARCH_CAP_F_BHI_NO RT_BIT_32(20)
1605	#define MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS RT_BIT_32(21)
1606	/* 22 is 'reserved' */
1607	#define MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS RT_BIT_32(22)
1608	#define MSR_IA32_ARCH_CAP_F_PBRSB_NO RT_BIT_32(23)
1609	#define MSR_IA32_ARCH_CAP_F_GDS_CTRL RT_BIT_32(24)
1610	#define MSR_IA32_ARCH_CAP_F_GDS_NO RT_BIT_32(25)
1611	#define MSR_IA32_ARCH_CAP_F_RFDS_NO RT_BIT_32(26)
1612	#define MSR_IA32_ARCH_CAP_F_RFDS_CLEAR RT_BIT_32(27)
1613
1614	/** Flush command register. */
1615	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1616	/** Flush the level 1 data cache when this bit is written. */
1617	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1618
1619	/** Cache control/info. */
1620	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1621
1622	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1623	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1624	* R0 SS == CS + 8
1625	* R3 CS == CS + 16
1626	* R3 SS == CS + 24
1627	*/
1628	#define MSR_IA32_SYSENTER_CS 0x174
1629	/** SYSENTER_ESP - the R0 ESP. */
1630	#define MSR_IA32_SYSENTER_ESP 0x175
1631	/** SYSENTER_EIP - the R0 EIP. */
1632	#define MSR_IA32_SYSENTER_EIP 0x176
1633	#endif
1634
1635	/** Machine Check Global Capabilities Register. */
1636	#define MSR_IA32_MCG_CAP 0x179
1637	/** Machine Check Global Status Register. */
1638	#define MSR_IA32_MCG_STATUS 0x17A
1639	/** Machine Check Global Control Register. */
1640	#define MSR_IA32_MCG_CTRL 0x17B
1641
1642	/** Page Attribute Table. */
1643	#define MSR_IA32_CR_PAT 0x277
1644	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1645	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1646	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1647
1648	/** Memory types that can be encoded in the IA32_PAT MSR.
1649	* @{ */
1650	/** Uncacheable. */
1651	#define MSR_IA32_PAT_MT_UC 0
1652	/** Write Combining. */
1653	#define MSR_IA32_PAT_MT_WC 1
1654	/** Reserved value 2. */
1655	#define MSR_IA32_PAT_MT_RSVD_2 2
1656	/** Reserved value 3. */
1657	#define MSR_IA32_PAT_MT_RSVD_3 3
1658	/** Write-through. */
1659	#define MSR_IA32_PAT_MT_WT 4
1660	/** Write-protected. */
1661	#define MSR_IA32_PAT_MT_WP 5
1662	/** Writeback. */
1663	#define MSR_IA32_PAT_MT_WB 6
1664	/** Uncached (UC-). */
1665	#define MSR_IA32_PAT_MT_UCD 7
1666	/** @}*/
1667
1668
1669	/** Performance event select MSRs. (Intel only) */
1670	#define MSR_IA32_PERFEVTSEL0 0x186
1671	#define MSR_IA32_PERFEVTSEL1 0x187
1672	#define MSR_IA32_PERFEVTSEL2 0x188
1673	#define MSR_IA32_PERFEVTSEL3 0x189
1674
1675	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1676	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1677	* holds a ratio that Apple takes for TSC granularity.
1678	*
1679	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1680	#define MSR_FLEX_RATIO 0x194
1681	/** Performance state value and starting with Intel core more.
1682	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1683	#define MSR_IA32_PERF_STATUS 0x198
1684	#define MSR_IA32_PERF_CTL 0x199
1685	#define MSR_IA32_THERM_STATUS 0x19c
1686
1687	/** Offcore response event select registers. */
1688	#define MSR_OFFCORE_RSP_0 0x1a6
1689	#define MSR_OFFCORE_RSP_1 0x1a7
1690
1691	/** Enable misc. processor features (R/W). */
1692	#define MSR_IA32_MISC_ENABLE 0x1A0
1693	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1694	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1695	/** Automatic Thermal Control Circuit Enable (R/W). */
1696	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1697	/** Performance Monitoring Available (R). */
1698	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1699	/** Branch Trace Storage Unavailable (R/O). */
1700	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1701	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1702	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1703	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1704	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1705	/** If MONITOR/MWAIT is supported (R/W). */
1706	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1707	/** Limit CPUID Maxval to 3 leafs (R/W). */
1708	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1709	/** When set to 1, xTPR messages are disabled (R/W). */
1710	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1711	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1712	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1713
1714	/** Trace/Profile Resource Control (R/W) */
1715	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1716	/** Last branch record. */
1717	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1718	/** Branch trace flag (single step on branches). */
1719	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1720	/** Performance monitoring pin control (AMD only). */
1721	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1722	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1723	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1724	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1725	/** Trace message enable (Intel only). */
1726	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1727	/** Branch trace store (Intel only). */
1728	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1729	/** Branch trace interrupt (Intel only). */
1730	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1731	/** Branch trace off in privileged code (Intel only). */
1732	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1733	/** Branch trace off in user code (Intel only). */
1734	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1735	/** Freeze LBR on PMI flag (Intel only). */
1736	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1737	/** Freeze PERFMON on PMI flag (Intel only). */
1738	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1739	/** Freeze while SMM enabled (Intel only). */
1740	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1741	/** Advanced debugging of RTM regions (Intel only). */
1742	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1743	/** Debug control MSR valid bits (Intel only). */
1744	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1745	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1746	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1747	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1748	\| MSR_IA32_DEBUGCTL_RTM)
1749
1750	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1751	* @{ */
1752	#define MSR_P4_LASTBRANCH_0 0x1db
1753	#define MSR_P4_LASTBRANCH_1 0x1dc
1754	#define MSR_P4_LASTBRANCH_2 0x1dd
1755	#define MSR_P4_LASTBRANCH_3 0x1de
1756
1757	/** LBR Top-of-stack MSR (index to most recent record). */
1758	#define MSR_P4_LASTBRANCH_TOS 0x1da
1759	/** @} */
1760
1761	/** @name Last branch registers for Core 2 and related Xeons.
1762	* @{ */
1763	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1764	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1765	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1766	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1767
1768	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1769	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1770	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1771	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1772
1773	/** LBR Top-of-stack MSR (index to most recent record). */
1774	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1775	/** @} */
1776
1777	/** @name Last branch registers.
1778	* @{ */
1779	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1780	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1781	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1782	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1783	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1784	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1785	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1786	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1787	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1788	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1789	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1790	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1791	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1792	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1793	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1794	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1795	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1796	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1797	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1798	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1799	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1800	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1801	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1802	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1803	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1804	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1805	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1806	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1807	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1808	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1809	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1810	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1811
1812	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1813	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1814	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1815	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1816	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1817	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1818	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1819	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1820	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1821	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1822	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1823	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1824	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1825	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1826	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1827	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1828	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1829	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1830	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1831	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1832	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1833	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1834	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1835	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1836	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1837	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1838	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1839	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1840	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1841	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1842	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1843	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1844
1845	#define MSR_LASTBRANCH_0_INFO 0xdc0
1846	#define MSR_LASTBRANCH_1_INFO 0xdc1
1847	#define MSR_LASTBRANCH_2_INFO 0xdc2
1848	#define MSR_LASTBRANCH_3_INFO 0xdc3
1849	#define MSR_LASTBRANCH_4_INFO 0xdc4
1850	#define MSR_LASTBRANCH_5_INFO 0xdc5
1851	#define MSR_LASTBRANCH_6_INFO 0xdc6
1852	#define MSR_LASTBRANCH_7_INFO 0xdc7
1853	#define MSR_LASTBRANCH_8_INFO 0xdc8
1854	#define MSR_LASTBRANCH_9_INFO 0xdc9
1855	#define MSR_LASTBRANCH_10_INFO 0xdca
1856	#define MSR_LASTBRANCH_11_INFO 0xdcb
1857	#define MSR_LASTBRANCH_12_INFO 0xdcc
1858	#define MSR_LASTBRANCH_13_INFO 0xdcd
1859	#define MSR_LASTBRANCH_14_INFO 0xdce
1860	#define MSR_LASTBRANCH_15_INFO 0xdcf
1861	#define MSR_LASTBRANCH_16_INFO 0xdd0
1862	#define MSR_LASTBRANCH_17_INFO 0xdd1
1863	#define MSR_LASTBRANCH_18_INFO 0xdd2
1864	#define MSR_LASTBRANCH_19_INFO 0xdd3
1865	#define MSR_LASTBRANCH_20_INFO 0xdd4
1866	#define MSR_LASTBRANCH_21_INFO 0xdd5
1867	#define MSR_LASTBRANCH_22_INFO 0xdd6
1868	#define MSR_LASTBRANCH_23_INFO 0xdd7
1869	#define MSR_LASTBRANCH_24_INFO 0xdd8
1870	#define MSR_LASTBRANCH_25_INFO 0xdd9
1871	#define MSR_LASTBRANCH_26_INFO 0xdda
1872	#define MSR_LASTBRANCH_27_INFO 0xddb
1873	#define MSR_LASTBRANCH_28_INFO 0xddc
1874	#define MSR_LASTBRANCH_29_INFO 0xddd
1875	#define MSR_LASTBRANCH_30_INFO 0xdde
1876	#define MSR_LASTBRANCH_31_INFO 0xddf
1877
1878	/** LBR branch tracking selection MSR. */
1879	#define MSR_LASTBRANCH_SELECT 0x1c8
1880	/** LBR Top-of-stack MSR (index to most recent record). */
1881	#define MSR_LASTBRANCH_TOS 0x1c9
1882	/** @} */
1883
1884	/** @name Last event record registers.
1885	* @{ */
1886	/** Last event record source IP register. */
1887	#define MSR_LER_FROM_IP 0x1dd
1888	/** Last event record destination IP register. */
1889	#define MSR_LER_TO_IP 0x1de
1890	/** @} */
1891
1892	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1893	#define MSR_IA32_TSX_CTRL 0x122
1894
1895	/** Variable range MTRRs.
1896	* @{ */
1897	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1898	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1899	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1900	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1901	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1902	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1903	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1904	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1905	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1906	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1907	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1908	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1909	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1910	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1911	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1912	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1913	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1914	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1915	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1916	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1917	/** @} */
1918
1919	/** Fixed range MTRRs.
1920	* @{ */
1921	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1922	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1923	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1924	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1925	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1926	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1927	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1928	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1929	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1930	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1931	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1932	/** @} */
1933
1934	/** MTRR Default Type.
1935	* @{ */
1936	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1937	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1938	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1939	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1940	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1941	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1942	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1943	/** @} */
1944
1945	/** Variable-range MTRR physical mask valid. */
1946	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1947
1948	/** Variable-range MTRR memory type mask. */
1949	#define MSR_IA32_MTRR_PHYSBASE_MT_MASK UINT64_C(0xff)
1950
1951	/** Global performance counter control facilities (Intel only). */
1952	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1953	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1954	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1955
1956	/** Precise Event Based sampling (Intel only). */
1957	#define MSR_IA32_PEBS_ENABLE 0x3F1
1958
1959	#define MSR_IA32_MC0_CTL 0x400
1960	#define MSR_IA32_MC0_STATUS 0x401
1961
1962	/** Basic VMX information. */
1963	#define MSR_IA32_VMX_BASIC 0x480
1964	/** Allowed settings for pin-based VM execution controls. */
1965	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1966	/** Allowed settings for proc-based VM execution controls. */
1967	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1968	/** Allowed settings for the VM-exit controls. */
1969	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1970	/** Allowed settings for the VM-entry controls. */
1971	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1972	/** Misc VMX info. */
1973	#define MSR_IA32_VMX_MISC 0x485
1974	/** Fixed cleared bits in CR0. */
1975	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1976	/** Fixed set bits in CR0. */
1977	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1978	/** Fixed cleared bits in CR4. */
1979	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1980	/** Fixed set bits in CR4. */
1981	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1982	/** Information for enumerating fields in the VMCS. */
1983	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1984	/** Allowed settings for secondary processor-based VM-execution controls. */
1985	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1986	/** EPT capabilities. */
1987	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1988	/** Allowed settings of all pin-based VM execution controls. */
1989	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1990	/** Allowed settings of all proc-based VM execution controls. */
1991	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1992	/** Allowed settings of all VMX exit controls. */
1993	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1994	/** Allowed settings of all VMX entry controls. */
1995	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1996	/** Allowed settings for the VM-function controls. */
1997	#define MSR_IA32_VMX_VMFUNC 0x491
1998	/** Tertiary processor-based VM execution controls. */
1999	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
2000	/** Secondary VM-exit controls. */
2001	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
2002
2003	/** Intel PT - Enable and control for trace packet generation. */
2004	#define MSR_IA32_RTIT_CTL 0x570
2005
2006	/** DS Save Area (R/W). */
2007	#define MSR_IA32_DS_AREA 0x600
2008	/** Running Average Power Limit (RAPL) power units. */
2009	#define MSR_RAPL_POWER_UNIT 0x606
2010	/** Package C3 Interrupt Response Limit. */
2011	#define MSR_PKGC3_IRTL 0x60a
2012	/** Package C6/C7S Interrupt Response Limit 1. */
2013	#define MSR_PKGC_IRTL1 0x60b
2014	/** Package C6/C7S Interrupt Response Limit 2. */
2015	#define MSR_PKGC_IRTL2 0x60c
2016	/** Package C2 Residency Counter. */
2017	#define MSR_PKG_C2_RESIDENCY 0x60d
2018	/** PKG RAPL Power Limit Control. */
2019	#define MSR_PKG_POWER_LIMIT 0x610
2020	/** PKG Energy Status. */
2021	#define MSR_PKG_ENERGY_STATUS 0x611
2022	/** PKG Perf Status. */
2023	#define MSR_PKG_PERF_STATUS 0x613
2024	/** PKG RAPL Parameters. */
2025	#define MSR_PKG_POWER_INFO 0x614
2026	/** DRAM RAPL Power Limit Control. */
2027	#define MSR_DRAM_POWER_LIMIT 0x618
2028	/** DRAM Energy Status. */
2029	#define MSR_DRAM_ENERGY_STATUS 0x619
2030	/** DRAM Performance Throttling Status. */
2031	#define MSR_DRAM_PERF_STATUS 0x61b
2032	/** DRAM RAPL Parameters. */
2033	#define MSR_DRAM_POWER_INFO 0x61c
2034	/** Package C10 Residency Counter. */
2035	#define MSR_PKG_C10_RESIDENCY 0x632
2036	/** PP0 Energy Status. */
2037	#define MSR_PP0_ENERGY_STATUS 0x639
2038	/** PP1 Energy Status. */
2039	#define MSR_PP1_ENERGY_STATUS 0x641
2040	/** Turbo Activation Ratio. */
2041	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
2042	/** Core Performance Limit Reasons. */
2043	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
2044
2045	/** Userspace Control flow Enforcement Technology setting. */
2046	#define MSR_IA32_U_CET 0x6a0
2047	/** Supervisor space Control flow Enforcement Technology setting. */
2048	#define MSR_IA32_S_CET 0x6a2
2049	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
2050	* @{ */
2051	/** Enables the Shadow stack. */
2052	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
2053	/** Enables WRSS{D,Q}W instructions. */
2054	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
2055	/** Enables indirect branch tracking. */
2056	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
2057	/** Enable legacy compatibility treatment for indirect branch tracking. */
2058	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
2059	/** Enables the use of no-track prefix for indirect branch tracking. */
2060	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
2061	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
2062	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
2063	/** Suppresses indirect branch tracking. */
2064	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
2065	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
2066	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
2067	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
2068	* on a ENDBRANCH instruction. */
2069	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
2070	/** @} */
2071
2072	/** X2APIC MSR range start. */
2073	#define MSR_IA32_X2APIC_START 0x800
2074	/** X2APIC MSR - APIC ID Register. */
2075	#define MSR_IA32_X2APIC_ID 0x802
2076	/** X2APIC MSR - APIC Version Register. */
2077	#define MSR_IA32_X2APIC_VERSION 0x803
2078	/** X2APIC MSR - Task Priority Register. */
2079	#define MSR_IA32_X2APIC_TPR 0x808
2080	/** X2APIC MSR - Processor Priority register. */
2081	#define MSR_IA32_X2APIC_PPR 0x80A
2082	/** X2APIC MSR - End Of Interrupt register. */
2083	#define MSR_IA32_X2APIC_EOI 0x80B
2084	/** X2APIC MSR - Logical Destination Register. */
2085	#define MSR_IA32_X2APIC_LDR 0x80D
2086	/** X2APIC MSR - Spurious Interrupt Vector Register. */
2087	#define MSR_IA32_X2APIC_SVR 0x80F
2088	/** X2APIC MSR - In-service Register (bits 31:0). */
2089	#define MSR_IA32_X2APIC_ISR0 0x810
2090	/** X2APIC MSR - In-service Register (bits 63:32). */
2091	#define MSR_IA32_X2APIC_ISR1 0x811
2092	/** X2APIC MSR - In-service Register (bits 95:64). */
2093	#define MSR_IA32_X2APIC_ISR2 0x812
2094	/** X2APIC MSR - In-service Register (bits 127:96). */
2095	#define MSR_IA32_X2APIC_ISR3 0x813
2096	/** X2APIC MSR - In-service Register (bits 159:128). */
2097	#define MSR_IA32_X2APIC_ISR4 0x814
2098	/** X2APIC MSR - In-service Register (bits 191:160). */
2099	#define MSR_IA32_X2APIC_ISR5 0x815
2100	/** X2APIC MSR - In-service Register (bits 223:192). */
2101	#define MSR_IA32_X2APIC_ISR6 0x816
2102	/** X2APIC MSR - In-service Register (bits 255:224). */
2103	#define MSR_IA32_X2APIC_ISR7 0x817
2104	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
2105	#define MSR_IA32_X2APIC_TMR0 0x818
2106	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
2107	#define MSR_IA32_X2APIC_TMR1 0x819
2108	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
2109	#define MSR_IA32_X2APIC_TMR2 0x81A
2110	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
2111	#define MSR_IA32_X2APIC_TMR3 0x81B
2112	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
2113	#define MSR_IA32_X2APIC_TMR4 0x81C
2114	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
2115	#define MSR_IA32_X2APIC_TMR5 0x81D
2116	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
2117	#define MSR_IA32_X2APIC_TMR6 0x81E
2118	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
2119	#define MSR_IA32_X2APIC_TMR7 0x81F
2120	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
2121	#define MSR_IA32_X2APIC_IRR0 0x820
2122	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
2123	#define MSR_IA32_X2APIC_IRR1 0x821
2124	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
2125	#define MSR_IA32_X2APIC_IRR2 0x822
2126	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
2127	#define MSR_IA32_X2APIC_IRR3 0x823
2128	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
2129	#define MSR_IA32_X2APIC_IRR4 0x824
2130	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
2131	#define MSR_IA32_X2APIC_IRR5 0x825
2132	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
2133	#define MSR_IA32_X2APIC_IRR6 0x826
2134	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
2135	#define MSR_IA32_X2APIC_IRR7 0x827
2136	/** X2APIC MSR - Error Status Register. */
2137	#define MSR_IA32_X2APIC_ESR 0x828
2138	/** X2APIC MSR - LVT CMCI Register. */
2139	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
2140	/** X2APIC MSR - Interrupt Command Register. */
2141	#define MSR_IA32_X2APIC_ICR 0x830
2142	/** X2APIC MSR - LVT Timer Register. */
2143	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
2144	/** X2APIC MSR - LVT Thermal Sensor Register. */
2145	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
2146	/** X2APIC MSR - LVT Performance Counter Register. */
2147	#define MSR_IA32_X2APIC_LVT_PERF 0x834
2148	/** X2APIC MSR - LVT LINT0 Register. */
2149	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2150	/** X2APIC MSR - LVT LINT1 Register. */
2151	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2152	/** X2APIC MSR - LVT Error Register . */
2153	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2154	/** X2APIC MSR - Timer Initial Count Register. */
2155	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2156	/** X2APIC MSR - Timer Current Count Register. */
2157	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2158	/** X2APIC MSR - Timer Divide Configuration Register. */
2159	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2160	/** X2APIC MSR - Self IPI. */
2161	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2162	/** X2APIC MSR range end. */
2163	#define MSR_IA32_X2APIC_END 0x8FF
2164	/** X2APIC MSR - LVT start range. */
2165	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2166	/** X2APIC MSR - LVT end range (inclusive). */
2167	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2168
2169	/** K6 EFER - Extended Feature Enable Register. */
2170	#define MSR_K6_EFER UINT32_C(0xc0000080)
2171	/** @todo document EFER */
2172	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2173	#define MSR_K6_EFER_SCE RT_BIT_32(0)
2174	/** Bit 8 - LME - Long mode enabled. (R/W) */
2175	#define MSR_K6_EFER_LME RT_BIT_32(8)
2176	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
2177	/** Bit 10 - LMA - Long mode active. (R) */
2178	#define MSR_K6_EFER_LMA RT_BIT_32(10)
2179	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
2180	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2181	#define MSR_K6_EFER_NXE RT_BIT_32(11)
2182	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
2183	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2184	#define MSR_K6_EFER_SVME RT_BIT_32(12)
2185	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2186	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2187	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
2188	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2189	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2190	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2191	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2192	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2193
2194	/** K6 STAR - SYSCALL/RET targets. */
2195	#define MSR_K6_STAR UINT32_C(0xc0000081)
2196	/** Shift value for getting the SYSRET CS and SS value. */
2197	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2198	/** Shift value for getting the SYSCALL CS and SS value. */
2199	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2200	/** Selector mask for use after shifting. */
2201	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2202	/** The mask which give the SYSCALL EIP. */
2203	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2204	/** K6 WHCR - Write Handling Control Register. */
2205	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2206	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2207	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2208	/** K6 PSOR - Processor State Observability Register. */
2209	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2210	/** K6 PFIR - Page Flush/Invalidate Register. */
2211	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2212
2213	/** Performance counter MSRs. (AMD only) */
2214	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2215	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2216	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2217	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2218	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2219	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2220	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2221	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2222
2223	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2224	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2225	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2226	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2227	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2228	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2229	/** K8 FS.base - The 64-bit base FS register. */
2230	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2231	/** K8 GS.base - The 64-bit base GS register. */
2232	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2233	/** K8 KernelGSbase - Used with SWAPGS. */
2234	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2235	/** K8 TSC_AUX - Used with RDTSCP. */
2236	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2237	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2238	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2239	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2240	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2241	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2242	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2243	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2244	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2245
2246	/** SMM MSRs. */
2247	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2248	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2249	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2250
2251	/** North bridge config? See BIOS & Kernel dev guides for
2252	* details. */
2253	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2254
2255	/** Hypertransport interrupt pending register.
2256	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2257	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2258
2259	/** SVM Control. */
2260	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2261	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2262	* features. */
2263	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2264	/** If set, non-intercepted INIT signals are converted to \#SX
2265	* exceptions. */
2266	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2267	/** Disables A20 masking. */
2268	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2269	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2270	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2271	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2272	* clear, EFER.SVME can be written normally. */
2273	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2274
2275	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2276	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2277	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2278	* host state during world switch. */
2279	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2280
2281	/** Virtualized speculation control for AMD processors.
2282	*
2283	* Unified interface among different CPU generations.
2284	* The VMM will set any architectural MSRs based on the CPU.
2285	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2286	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2287	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2288	/** Speculative Store Bypass Disable. */
2289	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2290
2291	/** @} */
2292
2293
2294	/** @name Page Table / Directory / Directory Pointers / L4.
2295	* @{
2296	*/
2297
2298	#ifndef __ASSEMBLER__
2299	/** Page table/directory entry as an unsigned integer. */
2300	typedef uint32_t X86PGUINT;
2301	/** Pointer to a page table/directory table entry as an unsigned integer. */
2302	typedef X86PGUINT *PX86PGUINT;
2303	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2304	typedef X86PGUINT const *PCX86PGUINT;
2305	#endif
2306
2307	/** Number of entries in a 32-bit PT/PD. */
2308	#define X86_PG_ENTRIES 1024
2309
2310
2311	#ifndef __ASSEMBLER__
2312	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2313	typedef uint64_t X86PGPAEUINT;
2314	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2315	typedef X86PGPAEUINT *PX86PGPAEUINT;
2316	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2317	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2318	#endif
2319
2320	/** Number of entries in a PAE PT/PD. */
2321	#define X86_PG_PAE_ENTRIES 512
2322	/** Number of entries in a PAE PDPT. */
2323	#define X86_PG_PAE_PDPE_ENTRIES 4
2324
2325	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2326	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2327	/** Number of entries in an AMD64 PDPT.
2328	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2329	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2330
2331	/** The size of a default page. */
2332	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2333	/** The page shift of a default page. */
2334	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2335	/** The default page offset mask. */
2336	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2337	/** The default page base mask for virtual addresses. */
2338	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2339	/** The default page base mask for virtual addresses - 32bit version. */
2340	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2341
2342	/** The size of a 4KB page. */
2343	#define X86_PAGE_4K_SIZE _4K
2344	/** The page shift of a 4KB page. */
2345	#define X86_PAGE_4K_SHIFT 12
2346	/** The 4KB page offset mask. */
2347	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2348	/** The 4KB page base mask for virtual addresses. */
2349	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2350	/** The 4KB page base mask for virtual addresses - 32bit version. */
2351	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2352
2353	/** The size of a 2MB page. */
2354	#define X86_PAGE_2M_SIZE _2M
2355	/** The page shift of a 2MB page. */
2356	#define X86_PAGE_2M_SHIFT 21
2357	/** The 2MB page offset mask. */
2358	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2359	/** The 2MB page base mask for virtual addresses. */
2360	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2361	/** The 2MB page base mask for virtual addresses - 32bit version. */
2362	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2363
2364	/** The size of a 4MB page. */
2365	#define X86_PAGE_4M_SIZE _4M
2366	/** The page shift of a 4MB page. */
2367	#define X86_PAGE_4M_SHIFT 22
2368	/** The 4MB page offset mask. */
2369	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2370	/** The 4MB page base mask for virtual addresses. */
2371	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2372	/** The 4MB page base mask for virtual addresses - 32bit version. */
2373	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2374
2375	/** The size of a 1GB page. */
2376	#define X86_PAGE_1G_SIZE _1G
2377	/** The page shift of a 1GB page. */
2378	#define X86_PAGE_1G_SHIFT 30
2379	/** The 1GB page offset mask. */
2380	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2381	/** The 1GB page base mask for virtual addresses. */
2382	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2383
2384	/**
2385	* Check if the given address is canonical.
2386	*/
2387	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2388
2389	/**
2390	* Gets the page base mask given the page shift.
2391	*/
2392	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2393
2394	/**
2395	* Gets the page offset mask given the page shift.
2396	*/
2397	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2398
2399
2400	/** @name Page Table Entry
2401	* @{
2402	*/
2403	/** Bit 0 - P - Present bit. */
2404	#define X86_PTE_BIT_P 0
2405	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2406	#define X86_PTE_BIT_RW 1
2407	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2408	#define X86_PTE_BIT_US 2
2409	/** Bit 3 - PWT - Page level write thru bit. */
2410	#define X86_PTE_BIT_PWT 3
2411	/** Bit 4 - PCD - Page level cache disable bit. */
2412	#define X86_PTE_BIT_PCD 4
2413	/** Bit 5 - A - Access bit. */
2414	#define X86_PTE_BIT_A 5
2415	/** Bit 6 - D - Dirty bit. */
2416	#define X86_PTE_BIT_D 6
2417	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2418	#define X86_PTE_BIT_PAT 7
2419	/** Bit 8 - G - Global flag. */
2420	#define X86_PTE_BIT_G 8
2421	/** Bits 63 - NX - PAE/LM - No execution flag. */
2422	#define X86_PTE_PAE_BIT_NX 63
2423
2424	/** Bit 0 - P - Present bit mask. */
2425	#define X86_PTE_P RT_BIT_32(0)
2426	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2427	#define X86_PTE_RW RT_BIT_32(1)
2428	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2429	#define X86_PTE_US RT_BIT_32(2)
2430	/** Bit 3 - PWT - Page level write thru bit mask. */
2431	#define X86_PTE_PWT RT_BIT_32(3)
2432	/** Bit 4 - PCD - Page level cache disable bit mask. */
2433	#define X86_PTE_PCD RT_BIT_32(4)
2434	/** Bit 5 - A - Access bit mask. */
2435	#define X86_PTE_A RT_BIT_32(5)
2436	/** Bit 6 - D - Dirty bit mask. */
2437	#define X86_PTE_D RT_BIT_32(6)
2438	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2439	#define X86_PTE_PAT RT_BIT_32(7)
2440	/** Bit 8 - G - Global bit mask. */
2441	#define X86_PTE_G RT_BIT_32(8)
2442
2443	/** Bits 9-11 - - Available for use to system software. */
2444	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2445	/** Bits 12-31 - - Physical Page number of the next level. */
2446	#define X86_PTE_PG_MASK ( 0xfffff000 )
2447
2448	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2449	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2450	/** Bits 63 - NX - PAE/LM - No execution flag. */
2451	#define X86_PTE_PAE_NX RT_BIT_64(63)
2452	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2453	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2454	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2455	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2456	/** No bits - - LM - MBZ bits when NX is active. */
2457	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2458	/** Bits 63 - - LM - MBZ bits when no NX. */
2459	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2460
2461	#ifndef __ASSEMBLER__
2462
2463	/**
2464	* Page table entry.
2465	*/
2466	typedef struct X86PTEBITS
2467	{
2468	/** Flags whether(=1) or not the page is present. */
2469	uint32_t u1Present : 1;
2470	/** Read(=0) / Write(=1) flag. */
2471	uint32_t u1Write : 1;
2472	/** User(=1) / Supervisor (=0) flag. */
2473	uint32_t u1User : 1;
2474	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2475	uint32_t u1WriteThru : 1;
2476	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2477	uint32_t u1CacheDisable : 1;
2478	/** Accessed flag.
2479	* Indicates that the page have been read or written to. */
2480	uint32_t u1Accessed : 1;
2481	/** Dirty flag.
2482	* Indicates that the page has been written to. */
2483	uint32_t u1Dirty : 1;
2484	/** Reserved / If PAT enabled, bit 2 of the index. */
2485	uint32_t u1PAT : 1;
2486	/** Global flag. (Ignored in all but final level.) */
2487	uint32_t u1Global : 1;
2488	/** Available for use to system software. */
2489	uint32_t u3Available : 3;
2490	/** Physical Page number of the next level. */
2491	uint32_t u20PageNo : 20;
2492	} X86PTEBITS;
2493	# ifndef VBOX_FOR_DTRACE_LIB
2494	AssertCompileSize(X86PTEBITS, 4);
2495	# endif
2496	/** Pointer to a page table entry. */
2497	typedef X86PTEBITS *PX86PTEBITS;
2498	/** Pointer to a const page table entry. */
2499	typedef const X86PTEBITS *PCX86PTEBITS;
2500
2501	/**
2502	* Page table entry.
2503	*/
2504	typedef union X86PTE
2505	{
2506	/** Unsigned integer view */
2507	X86PGUINT u;
2508	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2509	/** Bit field view. */
2510	X86PTEBITS n;
2511	# endif
2512	/** 32-bit view. */
2513	uint32_t au32[1];
2514	/** 16-bit view. */
2515	uint16_t au16[2];
2516	/** 8-bit view. */
2517	uint8_t au8[4];
2518	} X86PTE;
2519	# ifndef VBOX_FOR_DTRACE_LIB
2520	AssertCompileSize(X86PTE, 4);
2521	# endif
2522	/** Pointer to a page table entry. */
2523	typedef X86PTE *PX86PTE;
2524	/** Pointer to a const page table entry. */
2525	typedef const X86PTE *PCX86PTE;
2526
2527
2528	/**
2529	* PAE page table entry.
2530	*/
2531	typedef struct X86PTEPAEBITS
2532	{
2533	/** Flags whether(=1) or not the page is present. */
2534	uint32_t u1Present : 1;
2535	/** Read(=0) / Write(=1) flag. */
2536	uint32_t u1Write : 1;
2537	/** User(=1) / Supervisor(=0) flag. */
2538	uint32_t u1User : 1;
2539	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2540	uint32_t u1WriteThru : 1;
2541	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2542	uint32_t u1CacheDisable : 1;
2543	/** Accessed flag.
2544	* Indicates that the page have been read or written to. */
2545	uint32_t u1Accessed : 1;
2546	/** Dirty flag.
2547	* Indicates that the page has been written to. */
2548	uint32_t u1Dirty : 1;
2549	/** Reserved / If PAT enabled, bit 2 of the index. */
2550	uint32_t u1PAT : 1;
2551	/** Global flag. (Ignored in all but final level.) */
2552	uint32_t u1Global : 1;
2553	/** Available for use to system software. */
2554	uint32_t u3Available : 3;
2555	/** Physical Page number of the next level - Low Part. Don't use this. */
2556	uint32_t u20PageNoLow : 20;
2557	/** Physical Page number of the next level - High Part. Don't use this. */
2558	uint32_t u20PageNoHigh : 20;
2559	/** MBZ bits */
2560	uint32_t u11Reserved : 11;
2561	/** No Execute flag. */
2562	uint32_t u1NoExecute : 1;
2563	} X86PTEPAEBITS;
2564	# ifndef VBOX_FOR_DTRACE_LIB
2565	AssertCompileSize(X86PTEPAEBITS, 8);
2566	# endif
2567	/** Pointer to a page table entry. */
2568	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2569	/** Pointer to a page table entry. */
2570	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2571
2572	/**
2573	* PAE Page table entry.
2574	*/
2575	typedef union X86PTEPAE
2576	{
2577	/** Unsigned integer view */
2578	X86PGPAEUINT u;
2579	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2580	/** Bit field view. */
2581	X86PTEPAEBITS n;
2582	# endif
2583	/** 32-bit view. */
2584	uint32_t au32[2];
2585	/** 16-bit view. */
2586	uint16_t au16[4];
2587	/** 8-bit view. */
2588	uint8_t au8[8];
2589	} X86PTEPAE;
2590	# ifndef VBOX_FOR_DTRACE_LIB
2591	AssertCompileSize(X86PTEPAE, 8);
2592	# endif
2593	/** Pointer to a PAE page table entry. */
2594	typedef X86PTEPAE *PX86PTEPAE;
2595	/** Pointer to a const PAE page table entry. */
2596	typedef const X86PTEPAE *PCX86PTEPAE;
2597	/** @} */
2598
2599	/**
2600	* Page table.
2601	*/
2602	typedef struct X86PT
2603	{
2604	/** PTE Array. */
2605	X86PTE a[X86_PG_ENTRIES];
2606	} X86PT;
2607	# ifndef VBOX_FOR_DTRACE_LIB
2608	AssertCompileSize(X86PT, 4096);
2609	# endif
2610	/** Pointer to a page table. */
2611	typedef X86PT *PX86PT;
2612	/** Pointer to a const page table. */
2613	typedef const X86PT *PCX86PT;
2614
2615	#endif /* !__ASSEMBLER__ */
2616
2617	/** The page shift to get the PT index. */
2618	#define X86_PT_SHIFT 12
2619	/** The PT index mask (apply to a shifted page address). */
2620	#define X86_PT_MASK 0x3ff
2621
2622
2623	#ifndef __ASSEMBLER__
2624	/**
2625	* Page directory.
2626	*/
2627	typedef struct X86PTPAE
2628	{
2629	/** PTE Array. */
2630	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2631	} X86PTPAE;
2632	# ifndef VBOX_FOR_DTRACE_LIB
2633	AssertCompileSize(X86PTPAE, 4096);
2634	# endif
2635	/** Pointer to a page table. */
2636	typedef X86PTPAE *PX86PTPAE;
2637	/** Pointer to a const page table. */
2638	typedef const X86PTPAE *PCX86PTPAE;
2639	#endif /* !__ASSEMBLY__ */
2640
2641	/** The page shift to get the PA PTE index. */
2642	#define X86_PT_PAE_SHIFT 12
2643	/** The PAE PT index mask (apply to a shifted page address). */
2644	#define X86_PT_PAE_MASK 0x1ff
2645
2646
2647	/** @name 4KB Page Directory Entry
2648	* @{
2649	*/
2650	/** Bit 0 - P - Present bit. */
2651	#define X86_PDE_P RT_BIT_32(0)
2652	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2653	#define X86_PDE_RW RT_BIT_32(1)
2654	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2655	#define X86_PDE_US RT_BIT_32(2)
2656	/** Bit 3 - PWT - Page level write thru bit. */
2657	#define X86_PDE_PWT RT_BIT_32(3)
2658	/** Bit 4 - PCD - Page level cache disable bit. */
2659	#define X86_PDE_PCD RT_BIT_32(4)
2660	/** Bit 5 - A - Access bit. */
2661	#define X86_PDE_A RT_BIT_32(5)
2662	/** Bit 7 - PS - Page size attribute.
2663	* Clear mean 4KB pages, set means large pages (2/4MB). */
2664	#define X86_PDE_PS RT_BIT_32(7)
2665	/** Bits 9-11 - - Available for use to system software. */
2666	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2667	/** Bits 12-31 - - Physical Page number of the next level. */
2668	#define X86_PDE_PG_MASK ( 0xfffff000 )
2669
2670	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2671	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2672	/** Bits 63 - NX - PAE/LM - No execution flag. */
2673	#define X86_PDE_PAE_NX RT_BIT_64(63)
2674	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2675	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2676	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2677	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2678	/** Bit 7 - - LM - MBZ bits when NX is active. */
2679	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2680	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2681	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2682
2683	#ifndef __ASSEMBLER__
2684
2685	/**
2686	* Page directory entry.
2687	*/
2688	typedef struct X86PDEBITS
2689	{
2690	/** Flags whether(=1) or not the page is present. */
2691	uint32_t u1Present : 1;
2692	/** Read(=0) / Write(=1) flag. */
2693	uint32_t u1Write : 1;
2694	/** User(=1) / Supervisor (=0) flag. */
2695	uint32_t u1User : 1;
2696	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2697	uint32_t u1WriteThru : 1;
2698	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2699	uint32_t u1CacheDisable : 1;
2700	/** Accessed flag.
2701	* Indicates that the page has been read or written to. */
2702	uint32_t u1Accessed : 1;
2703	/** Reserved / Ignored (dirty bit). */
2704	uint32_t u1Reserved0 : 1;
2705	/** Size bit if PSE is enabled - in any event it's 0. */
2706	uint32_t u1Size : 1;
2707	/** Reserved / Ignored (global bit). */
2708	uint32_t u1Reserved1 : 1;
2709	/** Available for use to system software. */
2710	uint32_t u3Available : 3;
2711	/** Physical Page number of the next level. */
2712	uint32_t u20PageNo : 20;
2713	} X86PDEBITS;
2714	# ifndef VBOX_FOR_DTRACE_LIB
2715	AssertCompileSize(X86PDEBITS, 4);
2716	# endif
2717	/** Pointer to a page directory entry. */
2718	typedef X86PDEBITS *PX86PDEBITS;
2719	/** Pointer to a const page directory entry. */
2720	typedef const X86PDEBITS *PCX86PDEBITS;
2721
2722
2723	/**
2724	* PAE page directory entry.
2725	*/
2726	typedef struct X86PDEPAEBITS
2727	{
2728	/** Flags whether(=1) or not the page is present. */
2729	uint32_t u1Present : 1;
2730	/** Read(=0) / Write(=1) flag. */
2731	uint32_t u1Write : 1;
2732	/** User(=1) / Supervisor (=0) flag. */
2733	uint32_t u1User : 1;
2734	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2735	uint32_t u1WriteThru : 1;
2736	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2737	uint32_t u1CacheDisable : 1;
2738	/** Accessed flag.
2739	* Indicates that the page has been read or written to. */
2740	uint32_t u1Accessed : 1;
2741	/** Reserved / Ignored (dirty bit). */
2742	uint32_t u1Reserved0 : 1;
2743	/** Size bit if PSE is enabled - in any event it's 0. */
2744	uint32_t u1Size : 1;
2745	/** Reserved / Ignored (global bit). / */
2746	uint32_t u1Reserved1 : 1;
2747	/** Available for use to system software. */
2748	uint32_t u3Available : 3;
2749	/** Physical Page number of the next level - Low Part. Don't use! */
2750	uint32_t u20PageNoLow : 20;
2751	/** Physical Page number of the next level - High Part. Don't use! */
2752	uint32_t u20PageNoHigh : 20;
2753	/** MBZ bits */
2754	uint32_t u11Reserved : 11;
2755	/** No Execute flag. */
2756	uint32_t u1NoExecute : 1;
2757	} X86PDEPAEBITS;
2758	# ifndef VBOX_FOR_DTRACE_LIB
2759	AssertCompileSize(X86PDEPAEBITS, 8);
2760	# endif
2761	/** Pointer to a page directory entry. */
2762	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2763	/** Pointer to a const page directory entry. */
2764	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2765
2766	#endif /* !__ASSEMBLER__ */
2767
2768	/** @} */
2769
2770
2771	/** @name 2/4MB Page Directory Entry
2772	* @{
2773	*/
2774	/** Bit 0 - P - Present bit. */
2775	#define X86_PDE4M_P RT_BIT_32(0)
2776	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2777	#define X86_PDE4M_RW RT_BIT_32(1)
2778	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2779	#define X86_PDE4M_US RT_BIT_32(2)
2780	/** Bit 3 - PWT - Page level write thru bit. */
2781	#define X86_PDE4M_PWT RT_BIT_32(3)
2782	/** Bit 4 - PCD - Page level cache disable bit. */
2783	#define X86_PDE4M_PCD RT_BIT_32(4)
2784	/** Bit 5 - A - Access bit. */
2785	#define X86_PDE4M_A RT_BIT_32(5)
2786	/** Bit 6 - D - Dirty bit. */
2787	#define X86_PDE4M_D RT_BIT_32(6)
2788	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2789	#define X86_PDE4M_PS RT_BIT_32(7)
2790	/** Bit 8 - G - Global flag. */
2791	#define X86_PDE4M_G RT_BIT_32(8)
2792	/** Bits 9-11 - AVL - Available for use to system software. */
2793	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2794	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2795	#define X86_PDE4M_PAT RT_BIT_32(12)
2796	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2797	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2798	/** Bits 22-31 - - Physical Page number. */
2799	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2800	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2801	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2802	/** The number of bits to the high part of the page number. */
2803	#define X86_PDE4M_PG_HIGH_SHIFT 19
2804	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2805	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2806
2807	/** Bits 21-51 - - PAE/LM - Physical Page number.
2808	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2809	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2810	/** Bits 63 - NX - PAE/LM - No execution flag. */
2811	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2812	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2813	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2814	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2815	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2816	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2817	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2818	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2819	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2820
2821	#ifndef __ASSEMBLER__
2822
2823	/**
2824	* 4MB page directory entry.
2825	*/
2826	typedef struct X86PDE4MBITS
2827	{
2828	/** Flags whether(=1) or not the page is present. */
2829	uint32_t u1Present : 1;
2830	/** Read(=0) / Write(=1) flag. */
2831	uint32_t u1Write : 1;
2832	/** User(=1) / Supervisor (=0) flag. */
2833	uint32_t u1User : 1;
2834	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2835	uint32_t u1WriteThru : 1;
2836	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2837	uint32_t u1CacheDisable : 1;
2838	/** Accessed flag.
2839	* Indicates that the page have been read or written to. */
2840	uint32_t u1Accessed : 1;
2841	/** Dirty flag.
2842	* Indicates that the page has been written to. */
2843	uint32_t u1Dirty : 1;
2844	/** Page size flag - always 1 for 4MB entries. */
2845	uint32_t u1Size : 1;
2846	/** Global flag. */
2847	uint32_t u1Global : 1;
2848	/** Available for use to system software. */
2849	uint32_t u3Available : 3;
2850	/** Reserved / If PAT enabled, bit 2 of the index. */
2851	uint32_t u1PAT : 1;
2852	/** Bits 32-39 of the page number on AMD64.
2853	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2854	uint32_t u8PageNoHigh : 8;
2855	/** Reserved. */
2856	uint32_t u1Reserved : 1;
2857	/** Physical Page number of the page. */
2858	uint32_t u10PageNo : 10;
2859	} X86PDE4MBITS;
2860	# ifndef VBOX_FOR_DTRACE_LIB
2861	AssertCompileSize(X86PDE4MBITS, 4);
2862	# endif
2863	/** Pointer to a page table entry. */
2864	typedef X86PDE4MBITS *PX86PDE4MBITS;
2865	/** Pointer to a const page table entry. */
2866	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2867
2868
2869	/**
2870	* 2MB PAE page directory entry.
2871	*/
2872	typedef struct X86PDE2MPAEBITS
2873	{
2874	/** Flags whether(=1) or not the page is present. */
2875	uint32_t u1Present : 1;
2876	/** Read(=0) / Write(=1) flag. */
2877	uint32_t u1Write : 1;
2878	/** User(=1) / Supervisor(=0) flag. */
2879	uint32_t u1User : 1;
2880	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2881	uint32_t u1WriteThru : 1;
2882	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2883	uint32_t u1CacheDisable : 1;
2884	/** Accessed flag.
2885	* Indicates that the page have been read or written to. */
2886	uint32_t u1Accessed : 1;
2887	/** Dirty flag.
2888	* Indicates that the page has been written to. */
2889	uint32_t u1Dirty : 1;
2890	/** Page size flag - always 1 for 2MB entries. */
2891	uint32_t u1Size : 1;
2892	/** Global flag. */
2893	uint32_t u1Global : 1;
2894	/** Available for use to system software. */
2895	uint32_t u3Available : 3;
2896	/** Reserved / If PAT enabled, bit 2 of the index. */
2897	uint32_t u1PAT : 1;
2898	/** Reserved. */
2899	uint32_t u9Reserved : 9;
2900	/** Physical Page number of the next level - Low part. Don't use! */
2901	uint32_t u10PageNoLow : 10;
2902	/** Physical Page number of the next level - High part. Don't use! */
2903	uint32_t u20PageNoHigh : 20;
2904	/** MBZ bits */
2905	uint32_t u11Reserved : 11;
2906	/** No Execute flag. */
2907	uint32_t u1NoExecute : 1;
2908	} X86PDE2MPAEBITS;
2909	# ifndef VBOX_FOR_DTRACE_LIB
2910	AssertCompileSize(X86PDE2MPAEBITS, 8);
2911	# endif
2912	/** Pointer to a 2MB PAE page table entry. */
2913	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2914	/** Pointer to a 2MB PAE page table entry. */
2915	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2916
2917	#endif /* !__ASSEMBLER__ */
2918
2919	/** @} */
2920
2921	#ifndef __ASSEMBLER__
2922
2923	/**
2924	* Page directory entry.
2925	*/
2926	typedef union X86PDE
2927	{
2928	/** Unsigned integer view. */
2929	X86PGUINT u;
2930	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2931	/** Normal view. */
2932	X86PDEBITS n;
2933	/** 4MB view (big). */
2934	X86PDE4MBITS b;
2935	# endif
2936	/** 8 bit unsigned integer view. */
2937	uint8_t au8[4];
2938	/** 16 bit unsigned integer view. */
2939	uint16_t au16[2];
2940	/** 32 bit unsigned integer view. */
2941	uint32_t au32[1];
2942	} X86PDE;
2943	# ifndef VBOX_FOR_DTRACE_LIB
2944	AssertCompileSize(X86PDE, 4);
2945	# endif
2946	/** Pointer to a page directory entry. */
2947	typedef X86PDE *PX86PDE;
2948	/** Pointer to a const page directory entry. */
2949	typedef const X86PDE *PCX86PDE;
2950
2951	/**
2952	* PAE page directory entry.
2953	*/
2954	typedef union X86PDEPAE
2955	{
2956	/** Unsigned integer view. */
2957	X86PGPAEUINT u;
2958	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2959	/** Normal view. */
2960	X86PDEPAEBITS n;
2961	/** 2MB page view (big). */
2962	X86PDE2MPAEBITS b;
2963	# endif
2964	/** 8 bit unsigned integer view. */
2965	uint8_t au8[8];
2966	/** 16 bit unsigned integer view. */
2967	uint16_t au16[4];
2968	/** 32 bit unsigned integer view. */
2969	uint32_t au32[2];
2970	} X86PDEPAE;
2971	# ifndef VBOX_FOR_DTRACE_LIB
2972	AssertCompileSize(X86PDEPAE, 8);
2973	# endif
2974	/** Pointer to a page directory entry. */
2975	typedef X86PDEPAE *PX86PDEPAE;
2976	/** Pointer to a const page directory entry. */
2977	typedef const X86PDEPAE *PCX86PDEPAE;
2978
2979	/**
2980	* Page directory.
2981	*/
2982	typedef struct X86PD
2983	{
2984	/** PDE Array. */
2985	X86PDE a[X86_PG_ENTRIES];
2986	} X86PD;
2987	# ifndef VBOX_FOR_DTRACE_LIB
2988	AssertCompileSize(X86PD, 4096);
2989	# endif
2990	/** Pointer to a page directory. */
2991	typedef X86PD *PX86PD;
2992	/** Pointer to a const page directory. */
2993	typedef const X86PD *PCX86PD;
2994
2995	#endif /* !__ASSEMBLER__ */
2996
2997	/** The page shift to get the PD index. */
2998	#define X86_PD_SHIFT 22
2999	/** The PD index mask (apply to a shifted page address). */
3000	#define X86_PD_MASK 0x3ff
3001
3002
3003	#ifndef __ASSEMBLER__
3004	/**
3005	* PAE page directory.
3006	*/
3007	typedef struct X86PDPAE
3008	{
3009	/** PDE Array. */
3010	X86PDEPAE a[X86_PG_PAE_ENTRIES];
3011	} X86PDPAE;
3012	# ifndef VBOX_FOR_DTRACE_LIB
3013	AssertCompileSize(X86PDPAE, 4096);
3014	# endif
3015	/** Pointer to a PAE page directory. */
3016	typedef X86PDPAE *PX86PDPAE;
3017	/** Pointer to a const PAE page directory. */
3018	typedef const X86PDPAE *PCX86PDPAE;
3019	#endif /* !__ASSEMBLER__ */
3020
3021	/** The page shift to get the PAE PD index. */
3022	#define X86_PD_PAE_SHIFT 21
3023	/** The PAE PD index mask (apply to a shifted page address). */
3024	#define X86_PD_PAE_MASK 0x1ff
3025
3026
3027	/** @name Page Directory Pointer Table Entry (PAE)
3028	* @{
3029	*/
3030	/** Bit 0 - P - Present bit. */
3031	#define X86_PDPE_P RT_BIT_32(0)
3032	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
3033	#define X86_PDPE_RW RT_BIT_32(1)
3034	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
3035	#define X86_PDPE_US RT_BIT_32(2)
3036	/** Bit 3 - PWT - Page level write thru bit. */
3037	#define X86_PDPE_PWT RT_BIT_32(3)
3038	/** Bit 4 - PCD - Page level cache disable bit. */
3039	#define X86_PDPE_PCD RT_BIT_32(4)
3040	/** Bit 5 - A - Access bit. Long Mode only. */
3041	#define X86_PDPE_A RT_BIT_32(5)
3042	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
3043	#define X86_PDPE_LM_PS RT_BIT_32(7)
3044	/** Bits 9-11 - - Available for use to system software. */
3045	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3046	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3047	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
3048	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
3049	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
3050	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
3051	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
3052	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
3053	#define X86_PDPE_LM_NX RT_BIT_64(63)
3054	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
3055	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
3056	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
3057	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
3058	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
3059	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
3060	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
3061	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
3062
3063	#ifndef __ASSEMBLER__
3064
3065	/**
3066	* Page directory pointer table entry.
3067	*/
3068	typedef struct X86PDPEBITS
3069	{
3070	/** Flags whether(=1) or not the page is present. */
3071	uint32_t u1Present : 1;
3072	/** Chunk of reserved bits. */
3073	uint32_t u2Reserved : 2;
3074	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3075	uint32_t u1WriteThru : 1;
3076	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3077	uint32_t u1CacheDisable : 1;
3078	/** Chunk of reserved bits. */
3079	uint32_t u4Reserved : 4;
3080	/** Available for use to system software. */
3081	uint32_t u3Available : 3;
3082	/** Physical Page number of the next level - Low Part. Don't use! */
3083	uint32_t u20PageNoLow : 20;
3084	/** Physical Page number of the next level - High Part. Don't use! */
3085	uint32_t u20PageNoHigh : 20;
3086	/** MBZ bits */
3087	uint32_t u12Reserved : 12;
3088	} X86PDPEBITS;
3089	# ifndef VBOX_FOR_DTRACE_LIB
3090	AssertCompileSize(X86PDPEBITS, 8);
3091	# endif
3092	/** Pointer to a page directory pointer table entry. */
3093	typedef X86PDPEBITS *PX86PTPEBITS;
3094	/** Pointer to a const page directory pointer table entry. */
3095	typedef const X86PDPEBITS *PCX86PTPEBITS;
3096
3097	/**
3098	* Page directory pointer table entry. AMD64 version
3099	*/
3100	typedef struct X86PDPEAMD64BITS
3101	{
3102	/** Flags whether(=1) or not the page is present. */
3103	uint32_t u1Present : 1;
3104	/** Read(=0) / Write(=1) flag. */
3105	uint32_t u1Write : 1;
3106	/** User(=1) / Supervisor (=0) flag. */
3107	uint32_t u1User : 1;
3108	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3109	uint32_t u1WriteThru : 1;
3110	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3111	uint32_t u1CacheDisable : 1;
3112	/** Accessed flag.
3113	* Indicates that the page have been read or written to. */
3114	uint32_t u1Accessed : 1;
3115	/** Chunk of reserved bits. */
3116	uint32_t u3Reserved : 3;
3117	/** Available for use to system software. */
3118	uint32_t u3Available : 3;
3119	/** Physical Page number of the next level - Low Part. Don't use! */
3120	uint32_t u20PageNoLow : 20;
3121	/** Physical Page number of the next level - High Part. Don't use! */
3122	uint32_t u20PageNoHigh : 20;
3123	/** MBZ bits */
3124	uint32_t u11Reserved : 11;
3125	/** No Execute flag. */
3126	uint32_t u1NoExecute : 1;
3127	} X86PDPEAMD64BITS;
3128	# ifndef VBOX_FOR_DTRACE_LIB
3129	AssertCompileSize(X86PDPEAMD64BITS, 8);
3130	# endif
3131	/** Pointer to a page directory pointer table entry. */
3132	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
3133	/** Pointer to a const page directory pointer table entry. */
3134	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
3135
3136	/**
3137	* Page directory pointer table entry for 1GB page. (AMD64 only)
3138	*/
3139	typedef struct X86PDPE1GB
3140	{
3141	/** 0: Flags whether(=1) or not the page is present. */
3142	uint32_t u1Present : 1;
3143	/** 1: Read(=0) / Write(=1) flag. */
3144	uint32_t u1Write : 1;
3145	/** 2: User(=1) / Supervisor (=0) flag. */
3146	uint32_t u1User : 1;
3147	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
3148	uint32_t u1WriteThru : 1;
3149	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
3150	uint32_t u1CacheDisable : 1;
3151	/** 5: Accessed flag.
3152	* Indicates that the page have been read or written to. */
3153	uint32_t u1Accessed : 1;
3154	/** 6: Dirty flag for 1GB pages. */
3155	uint32_t u1Dirty : 1;
3156	/** 7: Indicates 1GB page if set. */
3157	uint32_t u1Size : 1;
3158	/** 8: Global 1GB page. */
3159	uint32_t u1Global: 1;
3160	/** 9-11: Available for use to system software. */
3161	uint32_t u3Available : 3;
3162	/** 12: PAT bit for 1GB page. */
3163	uint32_t u1PAT : 1;
3164	/** 13-29: MBZ bits. */
3165	uint32_t u17Reserved : 17;
3166	/** 30-31: Physical page number - Low Part. Don't use! */
3167	uint32_t u2PageNoLow : 2;
3168	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
3169	uint32_t u20PageNoHigh : 20;
3170	/** 52-62: MBZ bits */
3171	uint32_t u11Reserved : 11;
3172	/** 63: No Execute flag. */
3173	uint32_t u1NoExecute : 1;
3174	} X86PDPE1GB;
3175	# ifndef VBOX_FOR_DTRACE_LIB
3176	AssertCompileSize(X86PDPE1GB, 8);
3177	# endif
3178	/** Pointer to a page directory pointer table entry for a 1GB page. */
3179	typedef X86PDPE1GB *PX86PDPE1GB;
3180	/** Pointer to a const page directory pointer table entry for a 1GB page. */
3181	typedef const X86PDPE1GB *PCX86PDPE1GB;
3182
3183	/**
3184	* Page directory pointer table entry.
3185	*/
3186	typedef union X86PDPE
3187	{
3188	/** Unsigned integer view. */
3189	X86PGPAEUINT u;
3190	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3191	/** Normal view. */
3192	X86PDPEBITS n;
3193	/** AMD64 view. */
3194	X86PDPEAMD64BITS lm;
3195	/** AMD64 big view. */
3196	X86PDPE1GB b;
3197	# endif
3198	/** 8 bit unsigned integer view. */
3199	uint8_t au8[8];
3200	/** 16 bit unsigned integer view. */
3201	uint16_t au16[4];
3202	/** 32 bit unsigned integer view. */
3203	uint32_t au32[2];
3204	} X86PDPE;
3205	# ifndef VBOX_FOR_DTRACE_LIB
3206	AssertCompileSize(X86PDPE, 8);
3207	# endif
3208	/** Pointer to a page directory pointer table entry. */
3209	typedef X86PDPE *PX86PDPE;
3210	/** Pointer to a const page directory pointer table entry. */
3211	typedef const X86PDPE *PCX86PDPE;
3212
3213
3214	/**
3215	* Page directory pointer table.
3216	*/
3217	typedef struct X86PDPT
3218	{
3219	/** PDE Array. */
3220	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3221	} X86PDPT;
3222	# ifndef VBOX_FOR_DTRACE_LIB
3223	AssertCompileSize(X86PDPT, 4096);
3224	# endif
3225	/** Pointer to a page directory pointer table. */
3226	typedef X86PDPT *PX86PDPT;
3227	/** Pointer to a const page directory pointer table. */
3228	typedef const X86PDPT *PCX86PDPT;
3229
3230	#endif /* !__ASSEMBLER__ */
3231
3232	/** The page shift to get the PDPT index. */
3233	#define X86_PDPT_SHIFT 30
3234	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3235	#define X86_PDPT_MASK_PAE 0x3
3236	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3237	#define X86_PDPT_MASK_AMD64 0x1ff
3238
3239	/** @} */
3240
3241
3242	/** @name Page Map Level-4 Entry (Long Mode PAE)
3243	* @{
3244	*/
3245	/** Bit 0 - P - Present bit. */
3246	#define X86_PML4E_P RT_BIT_32(0)
3247	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3248	#define X86_PML4E_RW RT_BIT_32(1)
3249	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3250	#define X86_PML4E_US RT_BIT_32(2)
3251	/** Bit 3 - PWT - Page level write thru bit. */
3252	#define X86_PML4E_PWT RT_BIT_32(3)
3253	/** Bit 4 - PCD - Page level cache disable bit. */
3254	#define X86_PML4E_PCD RT_BIT_32(4)
3255	/** Bit 5 - A - Access bit. */
3256	#define X86_PML4E_A RT_BIT_32(5)
3257	/** Bits 9-11 - - Available for use to system software. */
3258	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3259	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3260	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3261	/** Bits 8, 7 - - MBZ bits when NX is active. */
3262	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3263	/** Bits 63, 7 - - MBZ bits when no NX. */
3264	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3265	/** Bits 63 - NX - PAE - No execution flag. */
3266	#define X86_PML4E_NX RT_BIT_64(63)
3267
3268	#ifndef __ASSEMBLER__
3269
3270	/**
3271	* Page Map Level-4 Entry
3272	*/
3273	typedef struct X86PML4EBITS
3274	{
3275	/** Flags whether(=1) or not the page is present. */
3276	uint32_t u1Present : 1;
3277	/** Read(=0) / Write(=1) flag. */
3278	uint32_t u1Write : 1;
3279	/** User(=1) / Supervisor (=0) flag. */
3280	uint32_t u1User : 1;
3281	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3282	uint32_t u1WriteThru : 1;
3283	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3284	uint32_t u1CacheDisable : 1;
3285	/** Accessed flag.
3286	* Indicates that the page have been read or written to. */
3287	uint32_t u1Accessed : 1;
3288	/** Chunk of reserved bits. */
3289	uint32_t u3Reserved : 3;
3290	/** Available for use to system software. */
3291	uint32_t u3Available : 3;
3292	/** Physical Page number of the next level - Low Part. Don't use! */
3293	uint32_t u20PageNoLow : 20;
3294	/** Physical Page number of the next level - High Part. Don't use! */
3295	uint32_t u20PageNoHigh : 20;
3296	/** MBZ bits */
3297	uint32_t u11Reserved : 11;
3298	/** No Execute flag. */
3299	uint32_t u1NoExecute : 1;
3300	} X86PML4EBITS;
3301	# ifndef VBOX_FOR_DTRACE_LIB
3302	AssertCompileSize(X86PML4EBITS, 8);
3303	# endif
3304	/** Pointer to a page map level-4 entry. */
3305	typedef X86PML4EBITS *PX86PML4EBITS;
3306	/** Pointer to a const page map level-4 entry. */
3307	typedef const X86PML4EBITS *PCX86PML4EBITS;
3308
3309	/**
3310	* Page Map Level-4 Entry.
3311	*/
3312	typedef union X86PML4E
3313	{
3314	/** Unsigned integer view. */
3315	X86PGPAEUINT u;
3316	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3317	/** Normal view. */
3318	X86PML4EBITS n;
3319	# endif
3320	/** 8 bit unsigned integer view. */
3321	uint8_t au8[8];
3322	/** 16 bit unsigned integer view. */
3323	uint16_t au16[4];
3324	/** 32 bit unsigned integer view. */
3325	uint32_t au32[2];
3326	} X86PML4E;
3327	# ifndef VBOX_FOR_DTRACE_LIB
3328	AssertCompileSize(X86PML4E, 8);
3329	# endif
3330	/** Pointer to a page map level-4 entry. */
3331	typedef X86PML4E *PX86PML4E;
3332	/** Pointer to a const page map level-4 entry. */
3333	typedef const X86PML4E *PCX86PML4E;
3334
3335
3336	/**
3337	* Page Map Level-4.
3338	*/
3339	typedef struct X86PML4
3340	{
3341	/** PDE Array. */
3342	X86PML4E a[X86_PG_PAE_ENTRIES];
3343	} X86PML4;
3344	# ifndef VBOX_FOR_DTRACE_LIB
3345	AssertCompileSize(X86PML4, 4096);
3346	# endif
3347	/** Pointer to a page map level-4. */
3348	typedef X86PML4 *PX86PML4;
3349	/** Pointer to a const page map level-4. */
3350	typedef const X86PML4 *PCX86PML4;
3351
3352	#endif /* !__ASSEMBLER__ */
3353
3354	/** The page shift to get the PML4 index. */
3355	#define X86_PML4_SHIFT 39
3356	/** The PML4 index mask (apply to a shifted page address). */
3357	#define X86_PML4_MASK 0x1ff
3358
3359	/** @} */
3360
3361	/** @} */
3362
3363	/**
3364	* Intel PCID invalidation types.
3365	*/
3366	/** Individual address invalidation. */
3367	#define X86_INVPCID_TYPE_INDV_ADDR 0
3368	/** Single-context invalidation. */
3369	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3370	/** All-context including globals invalidation. */
3371	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3372	/** All-context excluding globals invalidation. */
3373	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3374	/** The maximum valid invalidation type value. */
3375	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3376
3377
3378	/** @name Special FPU integer values.
3379	* @{ */
3380	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3381	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3382	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3383	/** @} */
3384
3385	#ifndef __ASSEMBLER__
3386
3387	/**
3388	* 32-bit protected mode FSTENV image.
3389	*/
3390	typedef struct X86FSTENV32P
3391	{
3392	uint16_t FCW; /*< 0x00 /
3393	uint16_t padding1; /*< 0x02 /
3394	uint16_t FSW; /*< 0x04 /
3395	uint16_t padding2; /*< 0x06 /
3396	uint16_t FTW; /*< 0x08 /
3397	uint16_t padding3; /*< 0x0a /
3398	uint32_t FPUIP; /*< 0x0c /
3399	uint16_t FPUCS; /*< 0x10 /
3400	uint16_t FOP; /*< 0x12 /
3401	uint32_t FPUDP; /*< 0x14 /
3402	uint16_t FPUDS; /*< 0x18 /
3403	uint16_t padding4; /*< 0x1a /
3404	} X86FSTENV32P;
3405	# ifndef VBOX_FOR_DTRACE_LIB
3406	AssertCompileSize(X86FSTENV32P, 0x1c);
3407	# endif
3408	/** Pointer to a 32-bit protected mode FSTENV image. */
3409	typedef X86FSTENV32P *PX86FSTENV32P;
3410	/** Pointer to a const 32-bit protected mode FSTENV image. */
3411	typedef X86FSTENV32P const *PCX86FSTENV32P;
3412
3413
3414	/**
3415	* 80-bit MMX/FPU register type.
3416	*/
3417	typedef struct X86FPUMMX
3418	{
3419	uint8_t reg[10];
3420	} X86FPUMMX;
3421	# ifndef VBOX_FOR_DTRACE_LIB
3422	AssertCompileSize(X86FPUMMX, 10);
3423	# endif
3424	/** Pointer to a 80-bit MMX/FPU register type. */
3425	typedef X86FPUMMX *PX86FPUMMX;
3426	/** Pointer to a const 80-bit MMX/FPU register type. */
3427	typedef const X86FPUMMX *PCX86FPUMMX;
3428
3429	/** FPU (x87) register. */
3430	typedef union X86FPUREG
3431	{
3432	/** MMX view. */
3433	uint64_t mmx;
3434	/** FPU view - todo. */
3435	X86FPUMMX fpu;
3436	/** Extended precision floating point view. */
3437	RTFLOAT80U r80;
3438	/** Extended precision floating point view v2 */
3439	RTFLOAT80U2 r80Ex;
3440	/** 8-bit view. */
3441	uint8_t au8[16];
3442	/** 16-bit view. */
3443	uint16_t au16[8];
3444	/** 32-bit view. */
3445	uint32_t au32[4];
3446	/** 64-bit view. */
3447	uint64_t au64[2];
3448	/** 128-bit view. (yeah, very helpful) */
3449	uint128_t au128[1];
3450	} X86FPUREG;
3451	# ifndef VBOX_FOR_DTRACE_LIB
3452	AssertCompileSize(X86FPUREG, 16);
3453	# endif
3454	/** Pointer to a FPU register. */
3455	typedef X86FPUREG *PX86FPUREG;
3456	/** Pointer to a const FPU register. */
3457	typedef X86FPUREG const *PCX86FPUREG;
3458
3459	/** FPU (x87) register - v2 with correct size. */
3460	# pragma pack(1)
3461	typedef union X86FPUREG2
3462	{
3463	/** MMX view. */
3464	uint64_t mmx;
3465	/** FPU view - todo. */
3466	X86FPUMMX fpu;
3467	/** Extended precision floating point view. */
3468	RTFLOAT80U r80;
3469	/** 8-bit view. */
3470	uint8_t au8[10];
3471	/** 16-bit view. */
3472	uint16_t au16[5];
3473	/** 32-bit view. */
3474	uint32_t au32[2];
3475	/** 64-bit view. */
3476	uint64_t au64[1];
3477	} X86FPUREG2;
3478	# pragma pack()
3479	# ifndef VBOX_FOR_DTRACE_LIB
3480	AssertCompileSize(X86FPUREG2, 10);
3481	# endif
3482	/** Pointer to a FPU register - v2. */
3483	typedef X86FPUREG2 *PX86FPUREG2;
3484	/** Pointer to a const FPU register - v2. */
3485	typedef X86FPUREG2 const *PCX86FPUREG2;
3486
3487	/**
3488	* XMM register union.
3489	*/
3490	typedef union X86XMMREG
3491	{
3492	/** XMM Register view. */
3493	uint128_t xmm;
3494	/** 8-bit view. */
3495	uint8_t au8[16];
3496	/** 16-bit view. */
3497	uint16_t au16[8];
3498	/** 32-bit view. */
3499	uint32_t au32[4];
3500	/** 64-bit view. */
3501	uint64_t au64[2];
3502	/** Signed 8-bit view. */
3503	int8_t ai8[16];
3504	/** Signed 16-bit view. */
3505	int16_t ai16[8];
3506	/** Signed 32-bit view. */
3507	int32_t ai32[4];
3508	/** Signed 64-bit view. */
3509	int64_t ai64[2];
3510	/** 128-bit view. (yeah, very helpful) */
3511	uint128_t au128[1];
3512	/** Single precision floating point view. */
3513	RTFLOAT32U ar32[4];
3514	/** Double precision floating point view. */
3515	RTFLOAT64U ar64[2];
3516	# ifndef VBOX_FOR_DTRACE_LIB
3517	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3518	RTUINT128U uXmm;
3519	# endif
3520	} X86XMMREG;
3521	# ifndef VBOX_FOR_DTRACE_LIB
3522	AssertCompileSize(X86XMMREG, 16);
3523	# endif
3524	/** Pointer to an XMM register state. */
3525	typedef X86XMMREG *PX86XMMREG;
3526	/** Pointer to a const XMM register state. */
3527	typedef X86XMMREG const *PCX86XMMREG;
3528
3529	/**
3530	* YMM register union.
3531	*/
3532	typedef union X86YMMREG
3533	{
3534	/** YMM register view. */
3535	RTUINT256U ymm;
3536	/** 8-bit view. */
3537	uint8_t au8[32];
3538	/** 16-bit view. */
3539	uint16_t au16[16];
3540	/** 32-bit view. */
3541	uint32_t au32[8];
3542	/** 64-bit view. */
3543	uint64_t au64[4];
3544	/** Signed 8-bit view. */
3545	int8_t ai8[32];
3546	/** Signed 16-bit view. */
3547	int16_t ai16[16];
3548	/** Signed 32-bit view. */
3549	int32_t ai32[8];
3550	/** Signed 64-bit view. */
3551	int64_t ai64[4];
3552	/** 128-bit view. (yeah, very helpful) */
3553	uint128_t au128[2];
3554	/** Single precision floating point view. */
3555	RTFLOAT32U ar32[8];
3556	/** Double precision floating point view. */
3557	RTFLOAT64U ar64[4];
3558	/** XMM sub register view. */
3559	X86XMMREG aXmm[2];
3560	} X86YMMREG;
3561	# ifndef VBOX_FOR_DTRACE_LIB
3562	AssertCompileSize(X86YMMREG, 32);
3563	# endif
3564	/** Pointer to an YMM register state. */
3565	typedef X86YMMREG *PX86YMMREG;
3566	/** Pointer to a const YMM register state. */
3567	typedef X86YMMREG const *PCX86YMMREG;
3568
3569	/**
3570	* ZMM register union.
3571	*/
3572	typedef union X86ZMMREG
3573	{
3574	/** 8-bit view. */
3575	uint8_t au8[64];
3576	/** 16-bit view. */
3577	uint16_t au16[32];
3578	/** 32-bit view. */
3579	uint32_t au32[16];
3580	/** 64-bit view. */
3581	uint64_t au64[8];
3582	/** Signed 8-bit view. */
3583	int8_t ai8[64];
3584	/** Signed 16-bit view. */
3585	int16_t ai16[32];
3586	/** Signed 32-bit view. */
3587	int32_t ai32[16];
3588	/** Signed 64-bit view. */
3589	int64_t ai64[8];
3590	/** 128-bit view. (yeah, very helpful) */
3591	uint128_t au128[4];
3592	/** Single precision floating point view. */
3593	RTFLOAT32U ar32[16];
3594	/** Double precision floating point view. */
3595	RTFLOAT64U ar64[8];
3596	/** XMM sub register view. */
3597	X86XMMREG aXmm[4];
3598	/** YMM sub register view. */
3599	X86YMMREG aYmm[2];
3600	} X86ZMMREG;
3601	# ifndef VBOX_FOR_DTRACE_LIB
3602	AssertCompileSize(X86ZMMREG, 64);
3603	# endif
3604	/** Pointer to an ZMM register state. */
3605	typedef X86ZMMREG *PX86ZMMREG;
3606	/** Pointer to a const ZMM register state. */
3607	typedef X86ZMMREG const *PCX86ZMMREG;
3608
3609
3610	/**
3611	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3612	*/
3613	# pragma pack(1)
3614	typedef struct X86FPUSTATE
3615	{
3616	/** 0x00 - Control word. */
3617	uint16_t FCW;
3618	/** 0x02 - Alignment word */
3619	uint16_t Dummy1;
3620	/** 0x04 - Status word. */
3621	uint16_t FSW;
3622	/** 0x06 - Alignment word */
3623	uint16_t Dummy2;
3624	/** 0x08 - Tag word */
3625	uint16_t FTW;
3626	/** 0x0a - Alignment word */
3627	uint16_t Dummy3;
3628
3629	/** 0x0c - Instruction pointer. */
3630	uint32_t FPUIP;
3631	/** 0x10 - Code selector. */
3632	uint16_t CS;
3633	/** 0x12 - Opcode. */
3634	uint16_t FOP;
3635	/** 0x14 - Data pointer. */
3636	uint32_t FPUOO;
3637	/** 0x18 - FOS. */
3638	uint16_t FPUOS;
3639	/** 0x0a - Alignment word */
3640	uint16_t Dummy4;
3641	/** 0x1c - FPU register. */
3642	X86FPUREG2 regs[8];
3643	} X86FPUSTATE;
3644	# pragma pack()
3645	AssertCompileSize(X86FPUSTATE, 108);
3646	/** Pointer to a FPU state. */
3647	typedef X86FPUSTATE *PX86FPUSTATE;
3648	/** Pointer to a const FPU state. */
3649	typedef const X86FPUSTATE *PCX86FPUSTATE;
3650
3651	/**
3652	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3653	*/
3654	# pragma pack(1)
3655	typedef struct X86FXSTATE
3656	{
3657	/** 0x00 - Control word. */
3658	uint16_t FCW;
3659	/** 0x02 - Status word. */
3660	uint16_t FSW;
3661	/** 0x04 - Tag word. (The upper byte is always zero.) */
3662	uint16_t FTW;
3663	/** 0x06 - Opcode. */
3664	uint16_t FOP;
3665	/** 0x08 - Instruction pointer. */
3666	uint32_t FPUIP;
3667	/** 0x0c - Code selector. */
3668	uint16_t CS;
3669	uint16_t Rsrvd1;
3670	/** 0x10 - Data pointer. */
3671	uint32_t FPUDP;
3672	/** 0x14 - Data segment */
3673	uint16_t DS;
3674	/** 0x16 */
3675	uint16_t Rsrvd2;
3676	/** 0x18 */
3677	uint32_t MXCSR;
3678	/** 0x1c */
3679	uint32_t MXCSR_MASK;
3680	/** 0x20 - FPU registers. */
3681	X86FPUREG aRegs[8];
3682	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3683	X86XMMREG aXMM[16];
3684	/* - offset 416 - */
3685	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3686	/* - offset 464 - Software usable reserved bits. */
3687	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3688	} X86FXSTATE;
3689	# pragma pack()
3690	/** Pointer to a FPU Extended state. */
3691	typedef X86FXSTATE *PX86FXSTATE;
3692	/** Pointer to a const FPU Extended state. */
3693	typedef const X86FXSTATE *PCX86FXSTATE;
3694
3695	#endif /* !__ASSEMBLER__ */
3696
3697
3698	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3699	* magic. Don't forget to update x86.mac if you change this! */
3700	#define X86_OFF_FXSTATE_RSVD 0x1d0
3701	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3702	* forget to update x86.mac if you change this!
3703	* @todo r=bird: This has nothing what-so-ever to do here.... */
3704	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3705	#ifndef VBOX_FOR_DTRACE_LIB
3706	AssertCompileSize(X86FXSTATE, 512);
3707	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3708	#endif
3709
3710	/** @name FPU status word flags.
3711	* @{ */
3712	/** Exception Flag: Invalid operation. */
3713	#define X86_FSW_IE RT_BIT_32(0)
3714	#define X86_FSW_IE_BIT 0
3715	/** Exception Flag: Denormalized operand. */
3716	#define X86_FSW_DE RT_BIT_32(1)
3717	#define X86_FSW_DE_BIT 1
3718	/** Exception Flag: Zero divide. */
3719	#define X86_FSW_ZE RT_BIT_32(2)
3720	#define X86_FSW_ZE_BIT 2
3721	/** Exception Flag: Overflow. */
3722	#define X86_FSW_OE RT_BIT_32(3)
3723	#define X86_FSW_OE_BIT 3
3724	/** Exception Flag: Underflow. */
3725	#define X86_FSW_UE RT_BIT_32(4)
3726	#define X86_FSW_UE_BIT 4
3727	/** Exception Flag: Precision. */
3728	#define X86_FSW_PE RT_BIT_32(5)
3729	#define X86_FSW_PE_BIT 5
3730	/** Stack fault. */
3731	#define X86_FSW_SF RT_BIT_32(6)
3732	#define X86_FSW_SF_BIT 6
3733	/** Error summary status. */
3734	#define X86_FSW_ES RT_BIT_32(7)
3735	#define X86_FSW_ES_BIT 7
3736	/** Mask of exceptions flags, excluding the summary bit. */
3737	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3738	/** Mask of exceptions flags, including the summary bit. */
3739	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3740	/** Condition code 0. */
3741	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3742	#define X86_FSW_C0_BIT 8
3743	/** Condition code 1. */
3744	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3745	#define X86_FSW_C1_BIT 9
3746	/** Condition code 2. */
3747	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3748	#define X86_FSW_C2_BIT 10
3749	/** Top of the stack mask. */
3750	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3751	/** TOP shift value. */
3752	#define X86_FSW_TOP_SHIFT 11
3753	/** Mask for getting TOP value after shifting it right. */
3754	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3755	/** Get the TOP value. */
3756	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3757	/** Get the TOP value offsetted by a_iSt (0-7). */
3758	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3759	/** Condition code 3. */
3760	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3761	#define X86_FSW_C3_BIT 14
3762	/** Mask of exceptions flags, including the summary bit. */
3763	#define X86_FSW_C_MASK UINT16_C(0x4700)
3764	/** FPU busy. */
3765	#define X86_FSW_B RT_BIT_32(15)
3766	/** For use with FPREM and FPREM1. */
3767	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3768	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3769	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3770	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3771	/** For use with FPREM and FPREM1. */
3772	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3773	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3774	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3775	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3776	/** @} */
3777
3778
3779	/** @name FPU control word flags.
3780	* @{ */
3781	/** Exception Mask: Invalid operation. */
3782	#define X86_FCW_IM RT_BIT_32(0)
3783	#define X86_FCW_IM_BIT 0
3784	/** Exception Mask: Denormalized operand. */
3785	#define X86_FCW_DM RT_BIT_32(1)
3786	#define X86_FCW_DM_BIT 1
3787	/** Exception Mask: Zero divide. */
3788	#define X86_FCW_ZM RT_BIT_32(2)
3789	#define X86_FCW_ZM_BIT 2
3790	/** Exception Mask: Overflow. */
3791	#define X86_FCW_OM RT_BIT_32(3)
3792	#define X86_FCW_OM_BIT 3
3793	/** Exception Mask: Underflow. */
3794	#define X86_FCW_UM RT_BIT_32(4)
3795	#define X86_FCW_UM_BIT 4
3796	/** Exception Mask: Precision. */
3797	#define X86_FCW_PM RT_BIT_32(5)
3798	#define X86_FCW_PM_BIT 5
3799	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3800	* @remarks This includes reserved bit 6. */
3801	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3802	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3803	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3804	/** Precision control mask. */
3805	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3806	/** Precision control shift. */
3807	#define X86_FCW_PC_SHIFT 8
3808	/** Precision control: 24-bit. */
3809	#define X86_FCW_PC_24 UINT16_C(0x0000)
3810	/** Precision control: Reserved. */
3811	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3812	/** Precision control: 53-bit. */
3813	#define X86_FCW_PC_53 UINT16_C(0x0200)
3814	/** Precision control: 64-bit. */
3815	#define X86_FCW_PC_64 UINT16_C(0x0300)
3816	/** Rounding control mask. */
3817	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3818	/** Rounding control shift. */
3819	#define X86_FCW_RC_SHIFT 10
3820	/** Rounding control: To nearest. */
3821	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3822	/** Rounding control: Down. */
3823	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3824	/** Rounding control: Up. */
3825	#define X86_FCW_RC_UP UINT16_C(0x0800)
3826	/** Rounding control: Towards zero. */
3827	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3828	/** Infinity control mask - obsolete, 8087 & 287 only. */
3829	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3830	/** Infinity control: Affine - positive infinity is distictly different from
3831	* negative infinity.
3832	* @note 8087, 287 only */
3833	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3834	/** Infinity control: Projective - positive and negative infinity are the
3835	* same (sign ignored).
3836	* @note 8087, 287 only */
3837	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3838	/** Bits which should be zero, apparently. */
3839	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3840	/** @} */
3841
3842	/** @name SSE MXCSR
3843	* @{ */
3844	/** Exception Flag: Invalid operation. */
3845	#define X86_MXCSR_IE RT_BIT_32(0)
3846	#define X86_MXCSR_IE_BIT 0
3847	/** Exception Flag: Denormalized operand. */
3848	#define X86_MXCSR_DE RT_BIT_32(1)
3849	#define X86_MXCSR_DE_BIT 1
3850	/** Exception Flag: Zero divide. */
3851	#define X86_MXCSR_ZE RT_BIT_32(2)
3852	#define X86_MXCSR_ZE_BIT 2
3853	/** Exception Flag: Overflow. */
3854	#define X86_MXCSR_OE RT_BIT_32(3)
3855	#define X86_MXCSR_OE_BIT 3
3856	/** Exception Flag: Underflow. */
3857	#define X86_MXCSR_UE RT_BIT_32(4)
3858	#define X86_MXCSR_UE_BIT 4
3859	/** Exception Flag: Precision. */
3860	#define X86_MXCSR_PE RT_BIT_32(5)
3861	#define X86_MXCSR_PE_BIT 5
3862	/** Exception Flags: mask */
3863	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3864
3865	/** Denormals are zero. */
3866	#define X86_MXCSR_DAZ RT_BIT_32(6)
3867	#define X86_MXCSR_DAZ_BIT 6
3868
3869	/** Exception Mask: Invalid operation. */
3870	#define X86_MXCSR_IM RT_BIT_32(7)
3871	#define X86_MXCSR_IM_BIT 7
3872	/** Exception Mask: Denormalized operand. */
3873	#define X86_MXCSR_DM RT_BIT_32(8)
3874	#define X86_MXCSR_DM_BIT 8
3875	/** Exception Mask: Zero divide. */
3876	#define X86_MXCSR_ZM RT_BIT_32(9)
3877	#define X86_MXCSR_ZM_BIT 9
3878	/** Exception Mask: Overflow. */
3879	#define X86_MXCSR_OM RT_BIT_32(10)
3880	#define X86_MXCSR_OM_BIT 10
3881	/** Exception Mask: Underflow. */
3882	#define X86_MXCSR_UM RT_BIT_32(11)
3883	#define X86_MXCSR_UM_BIT 11
3884	/** Exception Mask: Precision. */
3885	#define X86_MXCSR_PM RT_BIT_32(12)
3886	#define X86_MXCSR_PM_BIT 12
3887	/** Exception Mask: mask. */
3888	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3889	/** Exception Mask: shift. */
3890	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3891
3892	/** Rounding control mask. */
3893	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3894	/** Rounding control shift. */
3895	#define X86_MXCSR_RC_SHIFT 13
3896	/** Rounding control: To nearest. */
3897	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3898	/** Rounding control: Down. */
3899	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3900	/** Rounding control: Up. */
3901	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3902	/** Rounding control: Towards zero. */
3903	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3904
3905	/** Flush-to-zero for masked underflow. */
3906	#define X86_MXCSR_FZ RT_BIT_32(15)
3907	#define X86_MXCSR_FZ_BIT 15
3908
3909	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3910	#define X86_MXCSR_MM RT_BIT_32(17)
3911	#define X86_MXCSR_MM_BIT 17
3912	/** Bits which should be zero, apparently. */
3913	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3914	/** @} */
3915
3916	#ifndef __ASSEMBLER__
3917
3918	/**
3919	* XSAVE header.
3920	*/
3921	typedef struct X86XSAVEHDR
3922	{
3923	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3924	uint64_t bmXState;
3925	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3926	uint64_t bmXComp;
3927	/** Reserved for furture extensions, probably MBZ. */
3928	uint64_t au64Reserved[6];
3929	} X86XSAVEHDR;
3930	# ifndef VBOX_FOR_DTRACE_LIB
3931	AssertCompileSize(X86XSAVEHDR, 64);
3932	# endif
3933	/** Pointer to an XSAVE header. */
3934	typedef X86XSAVEHDR *PX86XSAVEHDR;
3935	/** Pointer to a const XSAVE header. */
3936	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3937
3938
3939	/**
3940	* The high 128-bit YMM register state (XSAVE_C_YMM).
3941	* (The lower 128-bits being in X86FXSTATE.)
3942	*/
3943	typedef struct X86XSAVEYMMHI
3944	{
3945	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3946	X86XMMREG aYmmHi[16];
3947	} X86XSAVEYMMHI;
3948	# ifndef VBOX_FOR_DTRACE_LIB
3949	AssertCompileSize(X86XSAVEYMMHI, 256);
3950	# endif
3951	/** Pointer to a high 128-bit YMM register state. */
3952	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3953	/** Pointer to a const high 128-bit YMM register state. */
3954	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3955
3956	/**
3957	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3958	*/
3959	typedef struct X86XSAVEBNDREGS
3960	{
3961	/** Array of registers (BND0...BND3). */
3962	struct
3963	{
3964	/** Lower bound. */
3965	uint64_t uLowerBound;
3966	/** Upper bound. */
3967	uint64_t uUpperBound;
3968	} aRegs[4];
3969	} X86XSAVEBNDREGS;
3970	# ifndef VBOX_FOR_DTRACE_LIB
3971	AssertCompileSize(X86XSAVEBNDREGS, 64);
3972	# endif
3973	/** Pointer to a MPX bound register state. */
3974	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3975	/** Pointer to a const MPX bound register state. */
3976	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3977
3978	/**
3979	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3980	*/
3981	typedef struct X86XSAVEBNDCFG
3982	{
3983	uint64_t fConfig;
3984	uint64_t fStatus;
3985	} X86XSAVEBNDCFG;
3986	# ifndef VBOX_FOR_DTRACE_LIB
3987	AssertCompileSize(X86XSAVEBNDCFG, 16);
3988	# endif
3989	/** Pointer to a MPX bound config and status register state. */
3990	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3991	/** Pointer to a const MPX bound config and status register state. */
3992	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3993
3994	/**
3995	* AVX-512 opmask state (XSAVE_C_OPMASK).
3996	*/
3997	typedef struct X86XSAVEOPMASK
3998	{
3999	/** The K0..K7 values. */
4000	uint64_t aKRegs[8];
4001	} X86XSAVEOPMASK;
4002	# ifndef VBOX_FOR_DTRACE_LIB
4003	AssertCompileSize(X86XSAVEOPMASK, 64);
4004	# endif
4005	/** Pointer to a AVX-512 opmask state. */
4006	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
4007	/** Pointer to a const AVX-512 opmask state. */
4008	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
4009
4010	/**
4011	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
4012	*/
4013	typedef struct X86XSAVEZMMHI256
4014	{
4015	/** Upper 256-bits of ZMM0-15. */
4016	X86YMMREG aHi256Regs[16];
4017	} X86XSAVEZMMHI256;
4018	# ifndef VBOX_FOR_DTRACE_LIB
4019	AssertCompileSize(X86XSAVEZMMHI256, 512);
4020	# endif
4021	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
4022	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
4023	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
4024	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
4025
4026	/**
4027	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
4028	*/
4029	typedef struct X86XSAVEZMM16HI
4030	{
4031	/** ZMM16 thru ZMM31. */
4032	X86ZMMREG aRegs[16];
4033	} X86XSAVEZMM16HI;
4034	# ifndef VBOX_FOR_DTRACE_LIB
4035	AssertCompileSize(X86XSAVEZMM16HI, 1024);
4036	# endif
4037	/** Pointer to a state comprising ZMM16-32. */
4038	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
4039	/** Pointer to a const state comprising ZMM16-32. */
4040	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
4041
4042	/**
4043	* AMD Light weight profiling state (XSAVE_C_LWP).
4044	*
4045	* We probably won't play with this as AMD seems to be dropping from their "zen"
4046	* processor micro architecture.
4047	*/
4048	typedef struct X86XSAVELWP
4049	{
4050	/** Details when needed. */
4051	uint64_t auLater[128/8];
4052	} X86XSAVELWP;
4053	# ifndef VBOX_FOR_DTRACE_LIB
4054	AssertCompileSize(X86XSAVELWP, 128);
4055	# endif
4056
4057
4058	/**
4059	* x86 FPU/SSE/AVX/XXXX state.
4060	*
4061	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
4062	* changes to this structure.
4063	*/
4064	typedef struct X86XSAVEAREA
4065	{
4066	/** The x87 and SSE region (or legacy region if you like). */
4067	X86FXSTATE x87;
4068	/** The XSAVE header. */
4069	X86XSAVEHDR Hdr;
4070	/** Beyond the header, there isn't really a fixed layout, but we can
4071	generally assume the YMM (AVX) register extensions are present and
4072	follows immediately. */
4073	union
4074	{
4075	/** The high 128-bit AVX registers for easy access by IEM.
4076	* @note This ASSUMES they will always be here... */
4077	X86XSAVEYMMHI YmmHi;
4078
4079	/** This is a typical layout on intel CPUs (good for debuggers). */
4080	struct
4081	{
4082	X86XSAVEYMMHI YmmHi;
4083	X86XSAVEBNDREGS BndRegs;
4084	X86XSAVEBNDCFG BndCfg;
4085	uint8_t abFudgeToMatchDocs[0xB0];
4086	X86XSAVEOPMASK Opmask;
4087	X86XSAVEZMMHI256 ZmmHi256;
4088	X86XSAVEZMM16HI Zmm16Hi;
4089	} Intel;
4090
4091	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
4092	struct
4093	{
4094	X86XSAVEYMMHI YmmHi;
4095	X86XSAVELWP Lwp;
4096	} AmdBd;
4097
4098	/** To enbling static deployments that have a reasonable chance of working for
4099	* the next 3-6 CPU generations without running short on space, we allocate a
4100	* lot of extra space here, making the structure a round 8KB in size. This
4101	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
4102	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
4103	uint8_t ab[8192 - 512 - 64];
4104	} u;
4105	} X86XSAVEAREA;
4106	# ifndef VBOX_FOR_DTRACE_LIB
4107	AssertCompileSize(X86XSAVEAREA, 8192);
4108	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
4109	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
4110	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
4111	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
4112	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
4113	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
4114	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
4115	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
4116	# endif
4117	/** Pointer to a XSAVE area. */
4118	typedef X86XSAVEAREA *PX86XSAVEAREA;
4119	/** Pointer to a const XSAVE area. */
4120	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
4121
4122	#endif /* __ASSEMBLER__ */
4123
4124
4125	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
4126	* @{ */
4127	/** Bit 0 - x87 - Legacy FPU state (bit number) */
4128	#define XSAVE_C_X87_BIT 0
4129	/** Bit 0 - x87 - Legacy FPU state. */
4130	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
4131	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
4132	#define XSAVE_C_SSE_BIT 1
4133	/** Bit 1 - SSE - 128-bit SSE state. */
4134	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
4135	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
4136	#define XSAVE_C_YMM_BIT 2
4137	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
4138	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
4139	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
4140	#define XSAVE_C_BNDREGS_BIT 3
4141	/** Bit 3 - BNDREGS - MPX bound register state. */
4142	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
4143	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
4144	#define XSAVE_C_BNDCSR_BIT 4
4145	/** Bit 4 - BNDCSR - MPX bound config and status state. */
4146	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
4147	/** Bit 5 - Opmask - opmask state (bit number). */
4148	#define XSAVE_C_OPMASK_BIT 5
4149	/** Bit 5 - Opmask - opmask state. */
4150	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
4151	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
4152	#define XSAVE_C_ZMM_HI256_BIT 6
4153	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
4154	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
4155	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
4156	#define XSAVE_C_ZMM_16HI_BIT 7
4157	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
4158	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
4159	/** Bit 9 - PKRU - Protection-key state (bit number). */
4160	#define XSAVE_C_PKRU_BIT 9
4161	/** Bit 9 - PKRU - Protection-key state. */
4162	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
4163	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
4164	#define XSAVE_C_LWP_BIT 62
4165	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
4166	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
4167	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
4168	#define XSAVE_C_X_BIT 63
4169	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
4170	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
4171	/** @} */
4172
4173
4174
4175	/** @name Selector Descriptor
4176	* @{
4177	*/
4178
4179	#ifndef __ASSEMBLER__
4180	# ifndef VBOX_FOR_DTRACE_LIB
4181	/**
4182	* Descriptor attributes (as seen by VT-x).
4183	*/
4184	typedef struct X86DESCATTRBITS
4185	{
4186	/** 00 - Segment Type. */
4187	unsigned u4Type : 4;
4188	/** 04 - Descriptor Type. System(=0) or code/data selector */
4189	unsigned u1DescType : 1;
4190	/** 05 - Descriptor Privilege level. */
4191	unsigned u2Dpl : 2;
4192	/** 07 - Flags selector present(=1) or not. */
4193	unsigned u1Present : 1;
4194	/** 08 - Segment limit 16-19. */
4195	unsigned u4LimitHigh : 4;
4196	/** 0c - Available for system software. */
4197	unsigned u1Available : 1;
4198	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4199	unsigned u1Long : 1;
4200	/** 0e - This flags meaning depends on the segment type. Try make sense out
4201	* of the intel manual yourself. */
4202	unsigned u1DefBig : 1;
4203	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
4204	* clear byte. */
4205	unsigned u1Granularity : 1;
4206	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
4207	unsigned u1Unusable : 1;
4208	} X86DESCATTRBITS;
4209	# endif /* !VBOX_FOR_DTRACE_LIB */
4210	#endif /* !__ASSEMBLER__ */
4211
4212	/** @name X86DESCATTR masks
4213	* Fields X86DESCGENERIC::u4Type thru X86DESCGENERIC::u1Granularity (or
4214	* bits[55:40] if you like). The X86DESCATTR_UNUSABLE bit is an Intel addition.
4215	* @{ */
4216	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
4217	#define X86DESCATTR_DT UINT32_C(0x00000010) /*< Descriptor type: 0=system, 1=code/data /
4218	#define X86DESCATTR_DPL UINT32_C(0x00000060)
4219	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL bitfield. /
4220	#define X86DESCATTR_P UINT32_C(0x00000080)
4221	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4222	#define X86DESCATTR_AVL UINT32_C(0x00001000)
4223	#define X86DESCATTR_L UINT32_C(0x00002000)
4224	#define X86DESCATTR_D UINT32_C(0x00004000)
4225	#define X86DESCATTR_G UINT32_C(0x00008000)
4226	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4227	/** @} */
4228
4229
4230	#ifndef __ASSEMBLER__
4231	# pragma pack(1)
4232	typedef union X86DESCATTR
4233	{
4234	/** Unsigned integer view. */
4235	uint32_t u;
4236	# ifndef VBOX_FOR_DTRACE_LIB
4237	/** Normal view. */
4238	X86DESCATTRBITS n;
4239	# endif
4240	} X86DESCATTR;
4241	# pragma pack()
4242	/** Pointer to descriptor attributes. */
4243	typedef X86DESCATTR *PX86DESCATTR;
4244	/** Pointer to const descriptor attributes. */
4245	typedef const X86DESCATTR *PCX86DESCATTR;
4246	#endif /* !__ASSEMBLER__ */
4247
4248	#ifndef VBOX_FOR_DTRACE_LIB
4249
4250	#ifndef __ASSEMBLER__
4251	/**
4252	* Generic descriptor table entry
4253	*/
4254	# pragma pack(1)
4255	typedef struct X86DESCGENERIC
4256	{
4257	/** 00 - Limit - Low word. */
4258	unsigned u16LimitLow : 16;
4259	/** 10 - Base address - low word.
4260	* Don't try set this to 24 because MSC is doing stupid things then. */
4261	unsigned u16BaseLow : 16;
4262	/** 20 - Base address - first 8 bits of high word. */
4263	unsigned u8BaseHigh1 : 8;
4264	/** 28 - Segment Type. */
4265	unsigned u4Type : 4;
4266	/** 2c - Descriptor Type. System(=0) or code/data selector */
4267	unsigned u1DescType : 1;
4268	/** 2d - Descriptor Privilege level. */
4269	unsigned u2Dpl : 2;
4270	/** 2f - Flags selector present(=1) or not. */
4271	unsigned u1Present : 1;
4272	/** 30 - Segment limit 16-19. */
4273	unsigned u4LimitHigh : 4;
4274	/** 34 - Available for system software. */
4275	unsigned u1Available : 1;
4276	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4277	unsigned u1Long : 1;
4278	/** 36 - This flags meaning depends on the segment type. Try make sense out
4279	* of the intel manual yourself. */
4280	unsigned u1DefBig : 1;
4281	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4282	* clear byte. */
4283	unsigned u1Granularity : 1;
4284	/** 38 - Base address - highest 8 bits. */
4285	unsigned u8BaseHigh2 : 8;
4286	} X86DESCGENERIC;
4287	# pragma pack()
4288	/** Pointer to a generic descriptor entry. */
4289	typedef X86DESCGENERIC *PX86DESCGENERIC;
4290	/** Pointer to a const generic descriptor entry. */
4291	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4292	# endif /* !__ASSEMBLER__ */
4293
4294
4295	/** @name Bit offsets of X86DESCGENERIC members.
4296	* @{*/
4297	# define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4298	# define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4299	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4300	# define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4301	# define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4302	# define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4303	# define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4304	# define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4305	# define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4306	# define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4307	# define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4308	# define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4309	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4310	/** @} */
4311
4312
4313	/** @name LAR mask
4314	* @{ */
4315	# define X86LAR_F_TYPE UINT16_C( 0x0f00)
4316	# define X86LAR_F_DT UINT16_C( 0x1000)
4317	# define X86LAR_F_DPL UINT16_C( 0x6000)
4318	# define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4319	# define X86LAR_F_P UINT16_C( 0x8000)
4320	# define X86LAR_F_AVL UINT32_C(0x00100000)
4321	# define X86LAR_F_L UINT32_C(0x00200000)
4322	# define X86LAR_F_D UINT32_C(0x00400000)
4323	# define X86LAR_F_G UINT32_C(0x00800000)
4324	/** @} */
4325
4326
4327	# ifndef __ASSEMBLER__
4328	/**
4329	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4330	*/
4331	typedef struct X86DESCGATE
4332	{
4333	/** 00 - Target code segment offset - Low word.
4334	* Ignored if task-gate. */
4335	unsigned u16OffsetLow : 16;
4336	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4337	* TSS selector if task-gate. */
4338	unsigned u16Sel : 16;
4339	/** 20 - Number of parameters for a call-gate.
4340	* Ignored if interrupt-, trap- or task-gate. */
4341	unsigned u5ParmCount : 5;
4342	/** 25 - Reserved / ignored. */
4343	unsigned u3Reserved : 3;
4344	/** 28 - Segment Type. */
4345	unsigned u4Type : 4;
4346	/** 2c - Descriptor Type (0 = system). */
4347	unsigned u1DescType : 1;
4348	/** 2d - Descriptor Privilege level. */
4349	unsigned u2Dpl : 2;
4350	/** 2f - Flags selector present(=1) or not. */
4351	unsigned u1Present : 1;
4352	/** 30 - Target code segment offset - High word.
4353	* Ignored if task-gate. */
4354	unsigned u16OffsetHigh : 16;
4355	} X86DESCGATE;
4356	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4357	typedef X86DESCGATE *PX86DESCGATE;
4358	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4359	typedef const X86DESCGATE *PCX86DESCGATE;
4360	# endif /* !__ASSEMBLER__ */
4361
4362	#endif /* VBOX_FOR_DTRACE_LIB */
4363
4364	#ifndef __ASSEMBLER__
4365	/**
4366	* Descriptor table entry.
4367	*/
4368	# pragma pack(1)
4369	typedef union X86DESC
4370	{
4371	# ifndef VBOX_FOR_DTRACE_LIB
4372	/** Generic descriptor view. */
4373	X86DESCGENERIC Gen;
4374	/** Gate descriptor view. */
4375	X86DESCGATE Gate;
4376	# endif
4377	/** 8 bit unsigned integer view. */
4378	uint8_t au8[8];
4379	/** 16 bit unsigned integer view. */
4380	uint16_t au16[4];
4381	/** 32 bit unsigned integer view. */
4382	uint32_t au32[2];
4383	/** 64 bit unsigned integer view. */
4384	uint64_t au64[1];
4385	/** Unsigned integer view. */
4386	uint64_t u;
4387	} X86DESC;
4388	# ifndef VBOX_FOR_DTRACE_LIB
4389	AssertCompileSize(X86DESC, 8);
4390	# endif
4391	# pragma pack()
4392	/** Pointer to descriptor table entry. */
4393	typedef X86DESC *PX86DESC;
4394	/** Pointer to const descriptor table entry. */
4395	typedef const X86DESC *PCX86DESC;
4396	#endif /* !__ASSEMBLER__ */
4397
4398	/** @def X86DESC_BASE
4399	* Return the base address of a descriptor.
4400	*/
4401	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4402	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4403	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4404	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4405
4406	/** @def X86DESC_LIMIT
4407	* Return the limit of a descriptor.
4408	*/
4409	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4410	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4411	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4412
4413	/** @def X86DESC_LIMIT_G
4414	* Return the limit of a descriptor with the granularity bit taken into account.
4415	* @returns Selector limit (uint32_t).
4416	* @param a_pDesc Pointer to the descriptor.
4417	*/
4418	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4419	( (a_pDesc)->Gen.u1Granularity \
4420	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4421	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4422	)
4423
4424	/** @def X86DESC_GET_HID_ATTR
4425	* Get the descriptor attributes for the hidden register.
4426	*/
4427	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4428	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4429
4430	#ifndef __ASSEMBLER__
4431	# ifndef VBOX_FOR_DTRACE_LIB
4432
4433	/**
4434	* 64 bits generic descriptor table entry
4435	* Note: most of these bits have no meaning in long mode.
4436	*/
4437	# pragma pack(1)
4438	typedef struct X86DESC64GENERIC
4439	{
4440	/** Limit - Low word - IGNORED. */
4441	uint32_t u16LimitLow : 16;
4442	/** Base address - low word. - IGNORED
4443	* Don't try set this to 24 because MSC is doing stupid things then. */
4444	uint32_t u16BaseLow : 16;
4445	/** Base address - first 8 bits of high word. - IGNORED */
4446	uint32_t u8BaseHigh1 : 8;
4447	/** Segment Type. */
4448	uint32_t u4Type : 4;
4449	/** Descriptor Type. System(=0) or code/data selector */
4450	uint32_t u1DescType : 1;
4451	/** Descriptor Privilege level. */
4452	uint32_t u2Dpl : 2;
4453	/** Flags selector present(=1) or not. */
4454	uint32_t u1Present : 1;
4455	/** Segment limit 16-19. - IGNORED */
4456	uint32_t u4LimitHigh : 4;
4457	/** Available for system software. - IGNORED */
4458	uint32_t u1Available : 1;
4459	/** Long mode flag. */
4460	uint32_t u1Long : 1;
4461	/** This flags meaning depends on the segment type. Try make sense out
4462	* of the intel manual yourself. */
4463	uint32_t u1DefBig : 1;
4464	/** Granularity of the limit. If set 4KB granularity is used, if
4465	* clear byte. - IGNORED */
4466	uint32_t u1Granularity : 1;
4467	/** Base address - highest 8 bits. - IGNORED */
4468	uint32_t u8BaseHigh2 : 8;
4469	/** Base address - bits 63-32. */
4470	uint32_t u32BaseHigh3 : 32;
4471	uint32_t u8Reserved : 8;
4472	uint32_t u5Zeros : 5;
4473	uint32_t u19Reserved : 19;
4474	} X86DESC64GENERIC;
4475	# pragma pack()
4476	/** Pointer to a generic descriptor entry. */
4477	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4478	/** Pointer to a const generic descriptor entry. */
4479	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4480
4481	/**
4482	* System descriptor table entry (64 bits)
4483	*
4484	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4485	*/
4486	# pragma pack(1)
4487	typedef struct X86DESC64SYSTEM
4488	{
4489	/** Limit - Low word. */
4490	uint32_t u16LimitLow : 16;
4491	/** Base address - low word.
4492	* Don't try set this to 24 because MSC is doing stupid things then. */
4493	uint32_t u16BaseLow : 16;
4494	/** Base address - first 8 bits of high word. */
4495	uint32_t u8BaseHigh1 : 8;
4496	/** Segment Type. */
4497	uint32_t u4Type : 4;
4498	/** Descriptor Type. System(=0) or code/data selector */
4499	uint32_t u1DescType : 1;
4500	/** Descriptor Privilege level. */
4501	uint32_t u2Dpl : 2;
4502	/** Flags selector present(=1) or not. */
4503	uint32_t u1Present : 1;
4504	/** Segment limit 16-19. */
4505	uint32_t u4LimitHigh : 4;
4506	/** Available for system software. */
4507	uint32_t u1Available : 1;
4508	/** Reserved - 0. */
4509	uint32_t u1Reserved : 1;
4510	/** This flags meaning depends on the segment type. Try make sense out
4511	* of the intel manual yourself. */
4512	uint32_t u1DefBig : 1;
4513	/** Granularity of the limit. If set 4KB granularity is used, if
4514	* clear byte. */
4515	uint32_t u1Granularity : 1;
4516	/** Base address - bits 31-24. */
4517	uint32_t u8BaseHigh2 : 8;
4518	/** Base address - bits 63-32. */
4519	uint32_t u32BaseHigh3 : 32;
4520	uint32_t u8Reserved : 8;
4521	uint32_t u5Zeros : 5;
4522	uint32_t u19Reserved : 19;
4523	} X86DESC64SYSTEM;
4524	# pragma pack()
4525	/** Pointer to a system descriptor entry. */
4526	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4527	/** Pointer to a const system descriptor entry. */
4528	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4529
4530	/**
4531	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4532	*/
4533	typedef struct X86DESC64GATE
4534	{
4535	/** Target code segment offset - Low word. */
4536	uint32_t u16OffsetLow : 16;
4537	/** Target code segment selector. */
4538	uint32_t u16Sel : 16;
4539	/** Interrupt stack table for interrupt- and trap-gates.
4540	* Ignored by call-gates. */
4541	uint32_t u3IST : 3;
4542	/** Reserved / ignored. */
4543	uint32_t u5Reserved : 5;
4544	/** Segment Type. */
4545	uint32_t u4Type : 4;
4546	/** Descriptor Type (0 = system). */
4547	uint32_t u1DescType : 1;
4548	/** Descriptor Privilege level. */
4549	uint32_t u2Dpl : 2;
4550	/** Flags selector present(=1) or not. */
4551	uint32_t u1Present : 1;
4552	/** Target code segment offset - High word.
4553	* Ignored if task-gate. */
4554	uint32_t u16OffsetHigh : 16;
4555	/** Target code segment offset - Top dword.
4556	* Ignored if task-gate. */
4557	uint32_t u32OffsetTop : 32;
4558	/** Reserved / ignored / must be zero.
4559	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4560	uint32_t u32Reserved : 32;
4561	} X86DESC64GATE;
4562	AssertCompileSize(X86DESC64GATE, 16);
4563	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4564	typedef X86DESC64GATE *PX86DESC64GATE;
4565	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4566	typedef const X86DESC64GATE *PCX86DESC64GATE;
4567
4568	# endif /* VBOX_FOR_DTRACE_LIB */
4569
4570	/**
4571	* Descriptor table entry.
4572	*/
4573	# pragma pack(1)
4574	typedef union X86DESC64
4575	{
4576	# ifndef VBOX_FOR_DTRACE_LIB
4577	/** Generic descriptor view. */
4578	X86DESC64GENERIC Gen;
4579	/** System descriptor view. */
4580	X86DESC64SYSTEM System;
4581	/** Gate descriptor view. */
4582	X86DESC64GATE Gate;
4583	# endif
4584
4585	/** 8 bit unsigned integer view. */
4586	uint8_t au8[16];
4587	/** 16 bit unsigned integer view. */
4588	uint16_t au16[8];
4589	/** 32 bit unsigned integer view. */
4590	uint32_t au32[4];
4591	/** 64 bit unsigned integer view. */
4592	uint64_t au64[2];
4593	} X86DESC64;
4594	# ifndef VBOX_FOR_DTRACE_LIB
4595	AssertCompileSize(X86DESC64, 16);
4596	# endif
4597	# pragma pack()
4598	/** Pointer to descriptor table entry. */
4599	typedef X86DESC64 *PX86DESC64;
4600	/** Pointer to const descriptor table entry. */
4601	typedef const X86DESC64 *PCX86DESC64;
4602
4603	/** @def X86DESC64_BASE
4604	* Return the base of a 64-bit descriptor.
4605	*/
4606	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4607	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4608	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4609	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4610	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4611
4612
4613
4614	/** @name Host system descriptor table entry - Use with care!
4615	* @{ */
4616	/** Host system descriptor table entry. */
4617	#if HC_ARCH_BITS == 64
4618	typedef X86DESC64 X86DESCHC;
4619	#else
4620	typedef X86DESC X86DESCHC;
4621	#endif
4622	/** Pointer to a host system descriptor table entry. */
4623	#if HC_ARCH_BITS == 64
4624	typedef PX86DESC64 PX86DESCHC;
4625	#else
4626	typedef PX86DESC PX86DESCHC;
4627	#endif
4628	/** Pointer to a const host system descriptor table entry. */
4629	#if HC_ARCH_BITS == 64
4630	typedef PCX86DESC64 PCX86DESCHC;
4631	#else
4632	typedef PCX86DESC PCX86DESCHC;
4633	#endif
4634	/** @} */
4635
4636	#endif /* !__ASSEMBLER__ */
4637
4638
4639	/** @name Selector Descriptor Types.
4640	* @{
4641	*/
4642
4643	/** @name Non-System Selector Types.
4644	* @{ */
4645	/** Code(=set)/Data(=clear) bit. */
4646	#define X86_SEL_TYPE_CODE 8
4647	/** Memory(=set)/System(=clear) bit. */
4648	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4649	/** Accessed bit. */
4650	#define X86_SEL_TYPE_ACCESSED 1
4651	/** Expand down bit (for data selectors only). */
4652	#define X86_SEL_TYPE_DOWN 4
4653	/** Conforming bit (for code selectors only). */
4654	#define X86_SEL_TYPE_CONF 4
4655	/** Write bit (for data selectors only). */
4656	#define X86_SEL_TYPE_WRITE 2
4657	/** Read bit (for code selectors only). */
4658	#define X86_SEL_TYPE_READ 2
4659	/** The bit number of the code segment read bit (relative to u4Type). */
4660	#define X86_SEL_TYPE_READ_BIT 1
4661
4662	/** Read only selector type. */
4663	#define X86_SEL_TYPE_RO 0
4664	/** Accessed read only selector type. */
4665	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4666	/** Read write selector type. */
4667	#define X86_SEL_TYPE_RW 2
4668	/** Accessed read write selector type. */
4669	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4670	/** Expand down read only selector type. */
4671	#define X86_SEL_TYPE_RO_DOWN 4
4672	/** Accessed expand down read only selector type. */
4673	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4674	/** Expand down read write selector type. */
4675	#define X86_SEL_TYPE_RW_DOWN 6
4676	/** Accessed expand down read write selector type. */
4677	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4678	/** Execute only selector type. */
4679	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4680	/** Accessed execute only selector type. */
4681	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4682	/** Execute and read selector type. */
4683	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4684	/** Accessed execute and read selector type. */
4685	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4686	/** Conforming execute only selector type. */
4687	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4688	/** Accessed Conforming execute only selector type. */
4689	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4690	/** Conforming execute and write selector type. */
4691	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4692	/** Accessed Conforming execute and write selector type. */
4693	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4694	/** @} */
4695
4696
4697	/** @name System Selector Types.
4698	* @{ */
4699	/** The TSS busy bit mask. */
4700	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4701
4702	/** Undefined system selector type. */
4703	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4704	/** 286 TSS selector. */
4705	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4706	/** LDT selector. */
4707	#define X86_SEL_TYPE_SYS_LDT 2
4708	/** 286 TSS selector - Busy. */
4709	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4710	/** 286 Callgate selector. */
4711	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4712	/** Taskgate selector. */
4713	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4714	/** 286 Interrupt gate selector. */
4715	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4716	/** 286 Trapgate selector. */
4717	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4718	/** Undefined system selector. */
4719	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4720	/** 386 TSS selector. */
4721	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4722	/** Undefined system selector. */
4723	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4724	/** 386 TSS selector - Busy. */
4725	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4726	/** 386 Callgate selector. */
4727	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4728	/** Undefined system selector. */
4729	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4730	/** 386 Interruptgate selector. */
4731	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4732	/** 386 Trapgate selector. */
4733	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4734	/** @} */
4735
4736	/** @name AMD64 System Selector Types.
4737	* @{ */
4738	/** LDT selector. */
4739	#define AMD64_SEL_TYPE_SYS_LDT 2
4740	/** TSS selector - Busy. */
4741	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4742	/** TSS selector - Busy. */
4743	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4744	/** Callgate selector. */
4745	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4746	/** Interruptgate selector. */
4747	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4748	/** Trapgate selector. */
4749	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4750	/** @} */
4751
4752	/** @} */
4753
4754
4755	/** @name Descriptor Table Entry Flag Masks.
4756	* These are for the 2nd 32-bit word of a descriptor.
4757	* @{ */
4758	/** Bits 8-11 - TYPE - Descriptor type mask. */
4759	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4760	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4761	#define X86_DESC_S RT_BIT_32(12)
4762	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4763	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4764	/** Bit 15 - P - Present. */
4765	#define X86_DESC_P RT_BIT_32(15)
4766	/** Bit 20 - AVL - Available for system software. */
4767	#define X86_DESC_AVL RT_BIT_32(20)
4768	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4769	#define X86_DESC_DB RT_BIT_32(22)
4770	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4771	* used, if clear byte. */
4772	#define X86_DESC_G RT_BIT_32(23)
4773	/** @} */
4774
4775	/** @} */
4776
4777
4778	/** @name Task Segments.
4779	* @{
4780	*/
4781
4782	/**
4783	* The minimum TSS descriptor limit for 286 tasks.
4784	*/
4785	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4786
4787	/**
4788	* The minimum TSS descriptor segment limit for 386 tasks.
4789	*/
4790	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4791
4792	#ifndef __ASSEMBLER__
4793
4794	/**
4795	* 16-bit Task Segment (TSS).
4796	*/
4797	# pragma pack(1)
4798	typedef struct X86TSS16
4799	{
4800	/** Back link to previous task. (static) */
4801	RTSEL selPrev;
4802	/** Ring-0 stack pointer. (static) */
4803	uint16_t sp0;
4804	/** Ring-0 stack segment. (static) */
4805	RTSEL ss0;
4806	/** Ring-1 stack pointer. (static) */
4807	uint16_t sp1;
4808	/** Ring-1 stack segment. (static) */
4809	RTSEL ss1;
4810	/** Ring-2 stack pointer. (static) */
4811	uint16_t sp2;
4812	/** Ring-2 stack segment. (static) */
4813	RTSEL ss2;
4814	/** IP before task switch. */
4815	uint16_t ip;
4816	/** FLAGS before task switch. */
4817	uint16_t flags;
4818	/** AX before task switch. */
4819	uint16_t ax;
4820	/** CX before task switch. */
4821	uint16_t cx;
4822	/** DX before task switch. */
4823	uint16_t dx;
4824	/** BX before task switch. */
4825	uint16_t bx;
4826	/** SP before task switch. */
4827	uint16_t sp;
4828	/** BP before task switch. */
4829	uint16_t bp;
4830	/** SI before task switch. */
4831	uint16_t si;
4832	/** DI before task switch. */
4833	uint16_t di;
4834	/** ES before task switch. */
4835	RTSEL es;
4836	/** CS before task switch. */
4837	RTSEL cs;
4838	/** SS before task switch. */
4839	RTSEL ss;
4840	/** DS before task switch. */
4841	RTSEL ds;
4842	/** LDTR before task switch. */
4843	RTSEL selLdt;
4844	} X86TSS16;
4845	# ifndef VBOX_FOR_DTRACE_LIB
4846	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4847	# endif
4848	# pragma pack()
4849	/** Pointer to a 16-bit task segment. */
4850	typedef X86TSS16 *PX86TSS16;
4851	/** Pointer to a const 16-bit task segment. */
4852	typedef const X86TSS16 *PCX86TSS16;
4853
4854
4855	/**
4856	* 32-bit Task Segment (TSS).
4857	*/
4858	# pragma pack(1)
4859	typedef struct X86TSS32
4860	{
4861	/** Back link to previous task. (static) */
4862	RTSEL selPrev;
4863	uint16_t padding1;
4864	/** Ring-0 stack pointer. (static) */
4865	uint32_t esp0;
4866	/** Ring-0 stack segment. (static) */
4867	RTSEL ss0;
4868	uint16_t padding_ss0;
4869	/** Ring-1 stack pointer. (static) */
4870	uint32_t esp1;
4871	/** Ring-1 stack segment. (static) */
4872	RTSEL ss1;
4873	uint16_t padding_ss1;
4874	/** Ring-2 stack pointer. (static) */
4875	uint32_t esp2;
4876	/** Ring-2 stack segment. (static) */
4877	RTSEL ss2;
4878	uint16_t padding_ss2;
4879	/** Page directory for the task. (static) */
4880	uint32_t cr3;
4881	/** EIP before task switch. */
4882	uint32_t eip;
4883	/** EFLAGS before task switch. */
4884	uint32_t eflags;
4885	/** EAX before task switch. */
4886	uint32_t eax;
4887	/** ECX before task switch. */
4888	uint32_t ecx;
4889	/** EDX before task switch. */
4890	uint32_t edx;
4891	/** EBX before task switch. */
4892	uint32_t ebx;
4893	/** ESP before task switch. */
4894	uint32_t esp;
4895	/** EBP before task switch. */
4896	uint32_t ebp;
4897	/** ESI before task switch. */
4898	uint32_t esi;
4899	/** EDI before task switch. */
4900	uint32_t edi;
4901	/** ES before task switch. */
4902	RTSEL es;
4903	uint16_t padding_es;
4904	/** CS before task switch. */
4905	RTSEL cs;
4906	uint16_t padding_cs;
4907	/** SS before task switch. */
4908	RTSEL ss;
4909	uint16_t padding_ss;
4910	/** DS before task switch. */
4911	RTSEL ds;
4912	uint16_t padding_ds;
4913	/** FS before task switch. */
4914	RTSEL fs;
4915	uint16_t padding_fs;
4916	/** GS before task switch. */
4917	RTSEL gs;
4918	uint16_t padding_gs;
4919	/** LDTR before task switch. */
4920	RTSEL selLdt;
4921	uint16_t padding_ldt;
4922	/** Debug trap flag */
4923	uint16_t fDebugTrap;
4924	/** Offset relative to the TSS of the start of the I/O Bitmap
4925	* and the end of the interrupt redirection bitmap. */
4926	uint16_t offIoBitmap;
4927	} X86TSS32;
4928	# pragma pack()
4929	/** Pointer to task segment. */
4930	typedef X86TSS32 *PX86TSS32;
4931	/** Pointer to const task segment. */
4932	typedef const X86TSS32 *PCX86TSS32;
4933	# ifndef VBOX_FOR_DTRACE_LIB
4934	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4935	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4936	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4937	# endif
4938
4939	/**
4940	* 64-bit Task segment.
4941	*/
4942	# pragma pack(1)
4943	typedef struct X86TSS64
4944	{
4945	/** Reserved. */
4946	uint32_t u32Reserved;
4947	/** Ring-0 stack pointer. (static) */
4948	uint64_t rsp0;
4949	/** Ring-1 stack pointer. (static) */
4950	uint64_t rsp1;
4951	/** Ring-2 stack pointer. (static) */
4952	uint64_t rsp2;
4953	/** Reserved. */
4954	uint32_t u32Reserved2[2];
4955	/* IST */
4956	uint64_t ist1;
4957	uint64_t ist2;
4958	uint64_t ist3;
4959	uint64_t ist4;
4960	uint64_t ist5;
4961	uint64_t ist6;
4962	uint64_t ist7;
4963	/* Reserved. */
4964	uint16_t u16Reserved[5];
4965	/** Offset relative to the TSS of the start of the I/O Bitmap
4966	* and the end of the interrupt redirection bitmap. */
4967	uint16_t offIoBitmap;
4968	} X86TSS64;
4969	# pragma pack()
4970	/** Pointer to a 64-bit task segment. */
4971	typedef X86TSS64 *PX86TSS64;
4972	/** Pointer to a const 64-bit task segment. */
4973	typedef const X86TSS64 *PCX86TSS64;
4974	# ifndef VBOX_FOR_DTRACE_LIB
4975	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4976	# endif
4977
4978	#endif /* !__ASSEMBLER__ */
4979
4980	/** @} */
4981
4982
4983	/** @name Selectors.
4984	* @{
4985	*/
4986
4987	/**
4988	* The shift used to convert a selector from and to index an index (C).
4989	*/
4990	#define X86_SEL_SHIFT 3
4991
4992	/**
4993	* The mask used to mask off the table indicator and RPL of an selector.
4994	*/
4995	#define X86_SEL_MASK 0xfff8U
4996
4997	/**
4998	* The mask used to mask off the RPL of an selector.
4999	* This is suitable for checking for NULL selectors.
5000	*/
5001	#define X86_SEL_MASK_OFF_RPL 0xfffcU
5002
5003	/**
5004	* The bit indicating that a selector is in the LDT and not in the GDT.
5005	*/
5006	#define X86_SEL_LDT 0x0004U
5007
5008	/**
5009	* The bit mask for getting the RPL of a selector.
5010	*/
5011	#define X86_SEL_RPL 0x0003U
5012
5013	/**
5014	* The mask covering both RPL and LDT.
5015	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
5016	* checks.
5017	*/
5018	#define X86_SEL_RPL_LDT 0x0007U
5019
5020	/** @} */
5021
5022
5023	#ifndef __ASSEMBLER__
5024	/**
5025	* x86 Exceptions/Faults/Traps.
5026	*/
5027	typedef enum X86XCPT
5028	{
5029	/** \#DE - Divide error. */
5030	X86_XCPT_DE = 0x00,
5031	/** \#DB - Debug event (single step, DRx, ..) */
5032	X86_XCPT_DB = 0x01,
5033	/** NMI - Non-Maskable Interrupt */
5034	X86_XCPT_NMI = 0x02,
5035	/** \#BP - Breakpoint (INT3). */
5036	X86_XCPT_BP = 0x03,
5037	/** \#OF - Overflow (INTO). */
5038	X86_XCPT_OF = 0x04,
5039	/** \#BR - Bound range exceeded (BOUND). */
5040	X86_XCPT_BR = 0x05,
5041	/** \#UD - Undefined opcode. */
5042	X86_XCPT_UD = 0x06,
5043	/** \#NM - Device not available (math coprocessor device). */
5044	X86_XCPT_NM = 0x07,
5045	/** \#DF - Double fault. */
5046	X86_XCPT_DF = 0x08,
5047	/** ??? - Coprocessor segment overrun (obsolete). */
5048	X86_XCPT_CO_SEG_OVERRUN = 0x09,
5049	/** \#TS - Taskswitch (TSS). */
5050	X86_XCPT_TS = 0x0a,
5051	/** \#NP - Segment no present. */
5052	X86_XCPT_NP = 0x0b,
5053	/** \#SS - Stack segment fault. */
5054	X86_XCPT_SS = 0x0c,
5055	/** \#GP - General protection fault. */
5056	X86_XCPT_GP = 0x0d,
5057	/** \#PF - Page fault. */
5058	X86_XCPT_PF = 0x0e,
5059	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
5060	/** \#MF - Math fault (FPU). */
5061	X86_XCPT_MF = 0x10,
5062	/** \#AC - Alignment check. */
5063	X86_XCPT_AC = 0x11,
5064	/** \#MC - Machine check. */
5065	X86_XCPT_MC = 0x12,
5066	/** \#XF - SIMD Floating-Point Exception. */
5067	X86_XCPT_XF = 0x13,
5068	/** \#VE - Virtualization Exception (Intel only). */
5069	X86_XCPT_VE = 0x14,
5070	/** \#CP - Control Protection Exception. */
5071	X86_XCPT_CP = 0x15,
5072	/** \#VC - VMM Communication Exception (AMD only). */
5073	X86_XCPT_VC = 0x1d,
5074	/** \#SX - Security Exception (AMD only). */
5075	X86_XCPT_SX = 0x1e
5076	} X86XCPT;
5077	/** Pointer to a x86 exception code. */
5078	typedef X86XCPT *PX86XCPT;
5079	/** Pointer to a const x86 exception code. */
5080	typedef const X86XCPT *PCX86XCPT;
5081	#endif /* !__ASSEMBLER__ */
5082	/** The last valid (currently reserved) exception value. */
5083	#define X86_XCPT_LAST 0x1f
5084
5085
5086	/** @name Trap Error Codes
5087	* @{
5088	*/
5089	/** External indicator. */
5090	#define X86_TRAP_ERR_EXTERNAL 1
5091	/** IDT indicator. */
5092	#define X86_TRAP_ERR_IDT 2
5093	/** Descriptor table indicator - If set LDT, if clear GDT. */
5094	#define X86_TRAP_ERR_TI 4
5095	/** Mask for getting the selector. */
5096	#define X86_TRAP_ERR_SEL_MASK 0xfff8
5097	/** Shift for getting the selector table index (C type index). */
5098	#define X86_TRAP_ERR_SEL_SHIFT 3
5099	/** @} */
5100
5101
5102	/** @name \#PF Trap Error Codes
5103	* @{
5104	*/
5105	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
5106	#define X86_TRAP_PF_P RT_BIT_32(0)
5107	/** Bit 1 - R/W - Read (clear) or write (set) access. */
5108	#define X86_TRAP_PF_RW RT_BIT_32(1)
5109	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
5110	#define X86_TRAP_PF_US RT_BIT_32(2)
5111	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
5112	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
5113	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
5114	#define X86_TRAP_PF_ID RT_BIT_32(4)
5115	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
5116	#define X86_TRAP_PF_PK RT_BIT_32(5)
5117	/** @} */
5118
5119	#ifndef __ASSEMBLER__
5120
5121	# pragma pack(1)
5122	/**
5123	* 16-bit IDTR.
5124	*/
5125	typedef struct X86IDTR16
5126	{
5127	/** Offset. */
5128	uint16_t offSel;
5129	/** Selector. */
5130	uint16_t uSel;
5131	} X86IDTR16, *PX86IDTR16;
5132	# pragma pack()
5133
5134	# pragma pack(1)
5135	/**
5136	* 32-bit IDTR/GDTR.
5137	*/
5138	typedef struct X86XDTR32
5139	{
5140	/** Size of the descriptor table. */
5141	uint16_t cb;
5142	/** Address of the descriptor table. */
5143	# ifndef VBOX_FOR_DTRACE_LIB
5144	uint32_t uAddr;
5145	# else
5146	uint16_t au16Addr[2];
5147	# endif
5148	} X86XDTR32, *PX86XDTR32;
5149	# pragma pack()
5150
5151	# pragma pack(1)
5152	/**
5153	* 64-bit IDTR/GDTR.
5154	*/
5155	typedef struct X86XDTR64
5156	{
5157	/** Size of the descriptor table. */
5158	uint16_t cb;
5159	/** Address of the descriptor table. */
5160	# ifndef VBOX_FOR_DTRACE_LIB
5161	uint64_t uAddr;
5162	# else
5163	uint16_t au16Addr[4];
5164	# endif
5165	} X86XDTR64, *PX86XDTR64;
5166	# pragma pack()
5167
5168	#endif /* !__ASSEMBLER__ */
5169
5170
5171	/** @name ModR/M
5172	* @{ */
5173	#define X86_MODRM_RM_MASK UINT8_C(0x07)
5174	#define X86_MODRM_REG_MASK UINT8_C(0x38)
5175	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
5176	#define X86_MODRM_REG_SHIFT 3
5177	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
5178	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
5179	#define X86_MODRM_MOD_SHIFT 6
5180
5181	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
5182	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
5183	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
5184	#define X86_MOD_REG 3 /*< Registers. /
5185
5186	#ifndef VBOX_FOR_DTRACE_LIB
5187	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
5188	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
5189	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
5190	/** @def X86_MODRM_MAKE
5191	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
5192	* @param a_Reg The register value (0..7).
5193	* @param a_RegMem The register or memory value (0..7). */
5194	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
5195	#endif
5196
5197	/** @} */
5198
5199	/** @name SIB
5200	* @{ */
5201	#define X86_SIB_BASE_MASK UINT8_C(0x07)
5202	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
5203	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
5204	#define X86_SIB_INDEX_SHIFT 3
5205	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
5206	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
5207	#define X86_SIB_SCALE_SHIFT 6
5208	#ifndef VBOX_FOR_DTRACE_LIB
5209	/** @def X86_SIB_MAKE
5210	* @param a_BaseReg The base register value (0..7).
5211	* @param a_IndexReg The index register value (0..7).
5212	* @param a_Scale The left shift (0..3) to be applied to the index
5213	* register (0 = none, 1 = x2, 2 = x4, 3 = x8).
5214	* */
5215	# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
5216	(((a_Scale) << X86_SIB_SCALE_SHIFT) \| ((a_IndexReg) << X86_SIB_INDEX_SHIFT) \| (a_BaseReg))
5217
5218	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
5219	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
5220	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
5221	#endif
5222	/** @} */
5223
5224	/** @name General register indexes.
5225	* @{ */
5226	#define X86_GREG_xAX 0
5227	#define X86_GREG_xCX 1
5228	#define X86_GREG_xDX 2
5229	#define X86_GREG_xBX 3
5230	#define X86_GREG_xSP 4
5231	#define X86_GREG_xBP 5
5232	#define X86_GREG_xSI 6
5233	#define X86_GREG_xDI 7
5234	#define X86_GREG_x8 8
5235	#define X86_GREG_x9 9
5236	#define X86_GREG_x10 10
5237	#define X86_GREG_x11 11
5238	#define X86_GREG_x12 12
5239	#define X86_GREG_x13 13
5240	#define X86_GREG_x14 14
5241	#define X86_GREG_x15 15
5242	/** @} */
5243	/** General register count. */
5244	#define X86_GREG_COUNT 16
5245
5246	/** @name X86_SREG_XXX - Segment register indexes.
5247	* @{ */
5248	#define X86_SREG_ES 0
5249	#define X86_SREG_CS 1
5250	#define X86_SREG_SS 2
5251	#define X86_SREG_DS 3
5252	#define X86_SREG_FS 4
5253	#define X86_SREG_GS 5
5254	/** @} */
5255	/** Segment register count. */
5256	#define X86_SREG_COUNT 6
5257
5258
5259	/** @name X86_OP_XXX - Prefixes
5260	* @{ */
5261	#define X86_OP_PRF_CS UINT8_C(0x2e)
5262	#define X86_OP_PRF_SS UINT8_C(0x36)
5263	#define X86_OP_PRF_DS UINT8_C(0x3e)
5264	#define X86_OP_PRF_ES UINT8_C(0x26)
5265	#define X86_OP_PRF_FS UINT8_C(0x64)
5266	#define X86_OP_PRF_GS UINT8_C(0x65)
5267	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5268	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5269	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5270	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5271	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5272	#define X86_OP_REX UINT8_C(0x40)
5273	#define X86_OP_REX_B UINT8_C(0x41)
5274	#define X86_OP_REX_X UINT8_C(0x42)
5275	#define X86_OP_REX_R UINT8_C(0x44)
5276	#define X86_OP_REX_W UINT8_C(0x48)
5277	#define X86_OP_VEX3 UINT8_C(0xc4)
5278	#define X86_OP_VEX2 UINT8_C(0xc5)
5279	/** @} */
5280
5281	/** @name X86_OP_VEX2_XXX - 2-byte VEX prefix helpers.
5282	* @{ */
5283	#define X86_OP_VEX2_BYTE1_P_MASK 0x3
5284	# define X86_OP_VEX2_BYTE1_P_NO_PRF 0
5285	# define X86_OP_VEX2_BYTE1_P_066H 1
5286	# define X86_OP_VEX2_BYTE1_P_0F3H 2
5287	# define X86_OP_VEX2_BYTE1_P_0F2H 3
5288	#define X86_OP_VEX2_BYTE1_L RT_BIT(2)
5289	#define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78
5290	#define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3
5291	#define X86_OP_VEX2_BYTE1_VVVV_NONE 15
5292	#define X86_OP_VEX2_BYTE1_R RT_BIT(7)
5293
5294	#define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5295	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5296	\| (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5297	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5298	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5299
5300	#define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \
5301	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5302	\| (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5303	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5304	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5305	/** @} */
5306
5307	/** @name X86_OP_VEX3_XXX - 3-byte VEX prefix helpers.
5308	* @{ */
5309	#define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f
5310	#define X86_OP_VEX3_BYTE1_B RT_BIT(5)
5311	#define X86_OP_VEX3_BYTE1_X RT_BIT(6)
5312	#define X86_OP_VEX3_BYTE1_R RT_BIT(7)
5313	#define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \
5314	( (uint8_t)(a_idxMap) \
5315	\| ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \
5316	\| ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \
5317	\| ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R))
5318
5319	#define X86_OP_VEX3_BYTE2_P_MASK 0x3
5320	# define X86_OP_VEX3_BYTE2_P_NO_PRF 0
5321	# define X86_OP_VEX3_BYTE2_P_066H 1
5322	# define X86_OP_VEX3_BYTE2_P_0F3H 2
5323	# define X86_OP_VEX3_BYTE2_P_0F2H 3
5324	#define X86_OP_VEX3_BYTE2_L RT_BIT(2)
5325	#define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78
5326	#define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3
5327	#define X86_OP_VEX3_BYTE2_VVVV_NONE 15
5328	#define X86_OP_VEX3_BYTE2_W RT_BIT(7)
5329
5330	/** @todo r=bird: Is the '& UINT8_C(0xf)' bit needed? You mask it again after
5331	* shifting. */
5332	#define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5333	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5334	\| ((~((uint8_t)(a_iSrcReg) & UINT8_C(0xf)) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \
5335	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5336	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5337
5338	#define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \
5339	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5340	\| (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
5341	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5342	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5343	/** @} */
5344
5345	/** @} */
5346
5347	#endif /* !IPRT_INCLUDED_x86_h */
5348

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source: vbox/trunk/include/iprt/x86.h@ 106472

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