x86.h@ 106967

Last change on this file since 106967 was 106636, checked in by vboxsync, 5 weeks ago
SUPDrv: Making it build on win.arm64... jiraref:VBP-1253
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# ifndef __ASSEMBLER__
46	# include <iprt/types.h>
47	# include <iprt/assert.h>
48	# else
49	# include <iprt/stdint.h>
50	# include <iprt/assertcompile.h>
51	# endif
52	#else
53	# pragma D depends_on library vbox-types.d
54	#endif
55
56	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
57	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
58	#ifdef RT_OS_SOLARIS
59	# undef CS
60	# undef DS
61	# undef MSR_IA32_FLUSH_CMD
62	# undef MSR_AMD_VIRT_SPEC_CTL
63	#endif
64
65	/** @defgroup grp_rt_x86 x86 Types and Definitions
66	* @ingroup grp_rt
67	* @{
68	*/
69
70	#ifndef __ASSEMBLER__
71
72	# ifndef VBOX_FOR_DTRACE_LIB
73	/**
74	* EFLAGS Bits.
75	*/
76	typedef struct X86EFLAGSBITS
77	{
78	/** Bit 0 - CF - Carry flag - Status flag. */
79	unsigned u1CF : 1;
80	/** Bit 1 - 1 - Reserved flag. */
81	unsigned u1Reserved0 : 1;
82	/** Bit 2 - PF - Parity flag - Status flag. */
83	unsigned u1PF : 1;
84	/** Bit 3 - 0 - Reserved flag. */
85	unsigned u1Reserved1 : 1;
86	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
87	unsigned u1AF : 1;
88	/** Bit 5 - 0 - Reserved flag. */
89	unsigned u1Reserved2 : 1;
90	/** Bit 6 - ZF - Zero flag - Status flag. */
91	unsigned u1ZF : 1;
92	/** Bit 7 - SF - Signed flag - Status flag. */
93	unsigned u1SF : 1;
94	/** Bit 8 - TF - Trap flag - System flag. */
95	unsigned u1TF : 1;
96	/** Bit 9 - IF - Interrupt flag - System flag. */
97	unsigned u1IF : 1;
98	/** Bit 10 - DF - Direction flag - Control flag. */
99	unsigned u1DF : 1;
100	/** Bit 11 - OF - Overflow flag - Status flag. */
101	unsigned u1OF : 1;
102	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
103	unsigned u2IOPL : 2;
104	/** Bit 14 - NT - Nested task flag - System flag. */
105	unsigned u1NT : 1;
106	/** Bit 15 - 0 - Reserved flag. */
107	unsigned u1Reserved3 : 1;
108	/** Bit 16 - RF - Resume flag - System flag. */
109	unsigned u1RF : 1;
110	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
111	unsigned u1VM : 1;
112	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
113	unsigned u1AC : 1;
114	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
115	unsigned u1VIF : 1;
116	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
117	unsigned u1VIP : 1;
118	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
119	unsigned u1ID : 1;
120	/** Bit 22-31 - 0 - Reserved flag. */
121	unsigned u10Reserved4 : 10;
122	} X86EFLAGSBITS;
123	/** Pointer to EFLAGS bits. */
124	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
125	/** Pointer to const EFLAGS bits. */
126	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
127	# endif /* !VBOX_FOR_DTRACE_LIB */
128
129	/**
130	* EFLAGS.
131	*/
132	typedef union X86EFLAGS
133	{
134	/** The plain unsigned view. */
135	uint32_t u;
136	# ifndef VBOX_FOR_DTRACE_LIB
137	/** The bitfield view. */
138	X86EFLAGSBITS Bits;
139	# endif
140	/** The 8-bit view. */
141	uint8_t au8[4];
142	/** The 16-bit view. */
143	uint16_t au16[2];
144	/** The 32-bit view. */
145	uint32_t au32[1];
146	/** The 32-bit view. */
147	uint32_t u32;
148	} X86EFLAGS;
149	/** Pointer to EFLAGS. */
150	typedef X86EFLAGS *PX86EFLAGS;
151	/** Pointer to const EFLAGS. */
152	typedef const X86EFLAGS *PCX86EFLAGS;
153
154	/**
155	* RFLAGS (32 upper bits are reserved).
156	*/
157	typedef union X86RFLAGS
158	{
159	/** The plain unsigned view. */
160	uint64_t u;
161	# ifndef VBOX_FOR_DTRACE_LIB
162	/** The bitfield view. */
163	X86EFLAGSBITS Bits;
164	# endif
165	/** The 8-bit view. */
166	uint8_t au8[8];
167	/** The 16-bit view. */
168	uint16_t au16[4];
169	/** The 32-bit view. */
170	uint32_t au32[2];
171	/** The 64-bit view. */
172	uint64_t au64[1];
173	/** The 64-bit view. */
174	uint64_t u64;
175	} X86RFLAGS;
176	/** Pointer to RFLAGS. */
177	typedef X86RFLAGS *PX86RFLAGS;
178	/** Pointer to const RFLAGS. */
179	typedef const X86RFLAGS *PCX86RFLAGS;
180
181	#endif /* !__ASSEMBLER__ */
182
183
184	/** @name EFLAGS
185	* @{
186	*/
187	/** Bit 0 - CF - Carry flag - Status flag. */
188	#define X86_EFL_CF RT_BIT_32(0)
189	#define X86_EFL_CF_BIT 0
190	/** Bit 1 - Reserved, reads as 1. */
191	#define X86_EFL_1 RT_BIT_32(1)
192	#define X86_EFL_1_BIT 1
193	/** Bit 2 - PF - Parity flag - Status flag. */
194	#define X86_EFL_PF RT_BIT_32(2)
195	#define X86_EFL_PF_BIT 2
196	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
197	#define X86_EFL_AF RT_BIT_32(4)
198	#define X86_EFL_AF_BIT 4
199	/** Bit 6 - ZF - Zero flag - Status flag. */
200	#define X86_EFL_ZF RT_BIT_32(6)
201	#define X86_EFL_ZF_BIT 6
202	/** Bit 7 - SF - Signed flag - Status flag. */
203	#define X86_EFL_SF RT_BIT_32(7)
204	#define X86_EFL_SF_BIT 7
205	/** Bit 8 - TF - Trap flag - System flag. */
206	#define X86_EFL_TF RT_BIT_32(8)
207	#define X86_EFL_TF_BIT 8
208	/** Bit 9 - IF - Interrupt flag - System flag. */
209	#define X86_EFL_IF RT_BIT_32(9)
210	#define X86_EFL_IF_BIT 9
211	/** Bit 10 - DF - Direction flag - Control flag. */
212	#define X86_EFL_DF RT_BIT_32(10)
213	#define X86_EFL_DF_BIT 10
214	/** Bit 11 - OF - Overflow flag - Status flag. */
215	#define X86_EFL_OF RT_BIT_32(11)
216	#define X86_EFL_OF_BIT 11
217	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
218	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
219	/** Bit 14 - NT - Nested task flag - System flag. */
220	#define X86_EFL_NT RT_BIT_32(14)
221	#define X86_EFL_NT_BIT 14
222	/** Bit 16 - RF - Resume flag - System flag. */
223	#define X86_EFL_RF RT_BIT_32(16)
224	#define X86_EFL_RF_BIT 16
225	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
226	#define X86_EFL_VM RT_BIT_32(17)
227	#define X86_EFL_VM_BIT 17
228	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
229	#define X86_EFL_AC RT_BIT_32(18)
230	#define X86_EFL_AC_BIT 18
231	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
232	#define X86_EFL_VIF RT_BIT_32(19)
233	#define X86_EFL_VIF_BIT 19
234	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
235	#define X86_EFL_VIP RT_BIT_32(20)
236	#define X86_EFL_VIP_BIT 20
237	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
238	#define X86_EFL_ID RT_BIT_32(21)
239	#define X86_EFL_ID_BIT 21
240	/** All live bits. */
241	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
242	/** Read as 1 bits. */
243	#define X86_EFL_RA1_MASK RT_BIT_32(1)
244	/** Read as 0 bits, excluding bits 31:22.
245	* Bits 3, 5, 15, and 22 thru 31. */
246	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
247	/** Read as 0 bits, excluding bits 31:22.
248	* Bits 3, 5 and 15. */
249	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
250	/** IOPL shift. */
251	#define X86_EFL_IOPL_SHIFT 12
252	/** The IOPL level from the flags. */
253	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
254	/** Bits restored by popf */
255	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
256	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
257	/** Bits restored by popf */
258	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
259	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
260	/** The status bits commonly updated by arithmetic instructions. */
261	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
262	/** @} */
263
264
265	#ifndef __ASSEMBLER__
266
267	/** CPUID Feature information - ECX.
268	* CPUID query with EAX=1.
269	*/
270	# ifndef VBOX_FOR_DTRACE_LIB
271	typedef struct X86CPUIDFEATECX
272	{
273	/** Bit 0 - SSE3 - Supports SSE3 or not. */
274	unsigned u1SSE3 : 1;
275	/** Bit 1 - PCLMULQDQ. */
276	unsigned u1PCLMULQDQ : 1;
277	/** Bit 2 - DS Area 64-bit layout. */
278	unsigned u1DTE64 : 1;
279	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
280	unsigned u1Monitor : 1;
281	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
282	unsigned u1CPLDS : 1;
283	/** Bit 5 - VMX - Virtual Machine Technology. */
284	unsigned u1VMX : 1;
285	/** Bit 6 - SMX: Safer Mode Extensions. */
286	unsigned u1SMX : 1;
287	/** Bit 7 - EST - Enh. SpeedStep Tech. */
288	unsigned u1EST : 1;
289	/** Bit 8 - TM2 - Terminal Monitor 2. */
290	unsigned u1TM2 : 1;
291	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
292	unsigned u1SSSE3 : 1;
293	/** Bit 10 - CNTX-ID - L1 Context ID. */
294	unsigned u1CNTXID : 1;
295	/** Bit 11 - Reserved. */
296	unsigned u1Reserved1 : 1;
297	/** Bit 12 - FMA. */
298	unsigned u1FMA : 1;
299	/** Bit 13 - CX16 - CMPXCHG16B. */
300	unsigned u1CX16 : 1;
301	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
302	unsigned u1TPRUpdate : 1;
303	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
304	unsigned u1PDCM : 1;
305	/** Bit 16 - Reserved. */
306	unsigned u1Reserved2 : 1;
307	/** Bit 17 - PCID - Process-context identifiers. */
308	unsigned u1PCID : 1;
309	/** Bit 18 - Direct Cache Access. */
310	unsigned u1DCA : 1;
311	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
312	unsigned u1SSE4_1 : 1;
313	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
314	unsigned u1SSE4_2 : 1;
315	/** Bit 21 - x2APIC. */
316	unsigned u1x2APIC : 1;
317	/** Bit 22 - MOVBE - Supports MOVBE. */
318	unsigned u1MOVBE : 1;
319	/** Bit 23 - POPCNT - Supports POPCNT. */
320	unsigned u1POPCNT : 1;
321	/** Bit 24 - TSC-Deadline. */
322	unsigned u1TSCDEADLINE : 1;
323	/** Bit 25 - AES. */
324	unsigned u1AES : 1;
325	/** Bit 26 - XSAVE - Supports XSAVE. */
326	unsigned u1XSAVE : 1;
327	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
328	unsigned u1OSXSAVE : 1;
329	/** Bit 28 - AVX - Supports AVX instruction extensions. */
330	unsigned u1AVX : 1;
331	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
332	unsigned u1F16C : 1;
333	/** Bit 30 - RDRAND - Supports RDRAND. */
334	unsigned u1RDRAND : 1;
335	/** Bit 31 - Hypervisor present (we're a guest). */
336	unsigned u1HVP : 1;
337	} X86CPUIDFEATECX;
338	# else /* VBOX_FOR_DTRACE_LIB */
339	typedef uint32_t X86CPUIDFEATECX;
340	# endif /* VBOX_FOR_DTRACE_LIB */
341	/** Pointer to CPUID Feature Information - ECX. */
342	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
343	/** Pointer to const CPUID Feature Information - ECX. */
344	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
345
346
347	/** CPUID Feature Information - EDX.
348	* CPUID query with EAX=1.
349	*/
350	# ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
351	typedef struct X86CPUIDFEATEDX
352	{
353	/** Bit 0 - FPU - x87 FPU on Chip. */
354	unsigned u1FPU : 1;
355	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
356	unsigned u1VME : 1;
357	/** Bit 2 - DE - Debugging extensions. */
358	unsigned u1DE : 1;
359	/** Bit 3 - PSE - Page Size Extension. */
360	unsigned u1PSE : 1;
361	/** Bit 4 - TSC - Time Stamp Counter. */
362	unsigned u1TSC : 1;
363	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
364	unsigned u1MSR : 1;
365	/** Bit 6 - PAE - Physical Address Extension. */
366	unsigned u1PAE : 1;
367	/** Bit 7 - MCE - Machine Check Exception. */
368	unsigned u1MCE : 1;
369	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
370	unsigned u1CX8 : 1;
371	/** Bit 9 - APIC - APIC On-Chip. */
372	unsigned u1APIC : 1;
373	/** Bit 10 - Reserved. */
374	unsigned u1Reserved1 : 1;
375	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
376	unsigned u1SEP : 1;
377	/** Bit 12 - MTRR - Memory Type Range Registers. */
378	unsigned u1MTRR : 1;
379	/** Bit 13 - PGE - PTE Global Bit. */
380	unsigned u1PGE : 1;
381	/** Bit 14 - MCA - Machine Check Architecture. */
382	unsigned u1MCA : 1;
383	/** Bit 15 - CMOV - Conditional Move Instructions. */
384	unsigned u1CMOV : 1;
385	/** Bit 16 - PAT - Page Attribute Table. */
386	unsigned u1PAT : 1;
387	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
388	unsigned u1PSE36 : 1;
389	/** Bit 18 - PSN - Processor Serial Number. */
390	unsigned u1PSN : 1;
391	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
392	unsigned u1CLFSH : 1;
393	/** Bit 20 - Reserved. */
394	unsigned u1Reserved2 : 1;
395	/** Bit 21 - DS - Debug Store. */
396	unsigned u1DS : 1;
397	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
398	unsigned u1ACPI : 1;
399	/** Bit 23 - MMX - Intel MMX 'Technology'. */
400	unsigned u1MMX : 1;
401	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
402	unsigned u1FXSR : 1;
403	/** Bit 25 - SSE - SSE Support. */
404	unsigned u1SSE : 1;
405	/** Bit 26 - SSE2 - SSE2 Support. */
406	unsigned u1SSE2 : 1;
407	/** Bit 27 - SS - Self Snoop. */
408	unsigned u1SS : 1;
409	/** Bit 28 - HTT - Hyper-Threading Technology. */
410	unsigned u1HTT : 1;
411	/** Bit 29 - TM - Thermal Monitor. */
412	unsigned u1TM : 1;
413	/** Bit 30 - Reserved - . */
414	unsigned u1Reserved3 : 1;
415	/** Bit 31 - PBE - Pending Break Enabled. */
416	unsigned u1PBE : 1;
417	} X86CPUIDFEATEDX;
418	# else /* VBOX_FOR_DTRACE_LIB */
419	typedef uint32_t X86CPUIDFEATEDX;
420	# endif /* VBOX_FOR_DTRACE_LIB */
421	/** Pointer to CPUID Feature Information - EDX. */
422	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
423	/** Pointer to const CPUID Feature Information - EDX. */
424	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
425
426	#endif /* !__ASSEMBLER__ */
427
428
429	/** @name CPUID Vendor information.
430	* CPUID query with EAX=0.
431	* @{
432	*/
433	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
434	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
435	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
436
437	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
438	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
439	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
440
441	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
442	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
443	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
444
445	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
446	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
447	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
448
449	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
450	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
451	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
452	/** @} */
453
454
455	/** @name CPUID Feature information.
456	* CPUID query with EAX=1.
457	* @{
458	*/
459	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
460	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
461	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
462	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
463	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
464	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
465	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
466	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
467	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
468	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
469	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
470	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
471	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
472	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
473	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
474	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
475	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
476	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
477	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
478	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
479	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
480	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
481	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
482	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
483	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
484	/** ECX Bit 12 - FMA. */
485	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
486	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
487	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
488	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
489	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
490	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
491	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
492	/** ECX Bit 17 - PCID - Process-context identifiers. */
493	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
494	/** ECX Bit 18 - DCA - Direct Cache Access. */
495	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
496	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
497	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
498	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
499	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
500	/** ECX Bit 21 - x2APIC support. */
501	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
502	/** ECX Bit 22 - MOVBE instruction. */
503	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
504	/** ECX Bit 23 - POPCNT instruction. */
505	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
506	/** ECX Bir 24 - TSC-Deadline. */
507	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
508	/** ECX Bit 25 - AES instructions. */
509	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
510	/** ECX Bit 26 - XSAVE instruction. */
511	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
512	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
513	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
514	/** ECX Bit 28 - AVX. */
515	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
516	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
517	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
518	/** ECX Bit 30 - RDRAND instruction. */
519	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
520	/** ECX Bit 31 - Hypervisor Present (software only). */
521	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
522
523
524	/** Bit 0 - FPU - x87 FPU on Chip. */
525	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
526	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
527	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
528	/** Bit 2 - DE - Debugging extensions. */
529	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
530	/** Bit 3 - PSE - Page Size Extension. */
531	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
532	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
533	/** Bit 4 - TSC - Time Stamp Counter. */
534	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
535	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
536	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
537	/** Bit 6 - PAE - Physical Address Extension. */
538	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
539	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
540	/** Bit 7 - MCE - Machine Check Exception. */
541	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
542	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
543	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
544	/** Bit 9 - APIC - APIC On-Chip. */
545	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
546	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
547	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
548	/** Bit 12 - MTRR - Memory Type Range Registers. */
549	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
550	/** Bit 13 - PGE - PTE Global Bit. */
551	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
552	/** Bit 14 - MCA - Machine Check Architecture. */
553	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
554	/** Bit 15 - CMOV - Conditional Move Instructions. */
555	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
556	/** Bit 16 - PAT - Page Attribute Table. */
557	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
558	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
559	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
560	/** Bit 18 - PSN - Processor Serial Number. */
561	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
562	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
563	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
564	/** Bit 21 - DS - Debug Store. */
565	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
566	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
567	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
568	/** Bit 23 - MMX - Intel MMX Technology. */
569	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
570	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
571	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
572	/** Bit 25 - SSE - SSE Support. */
573	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
574	/** Bit 26 - SSE2 - SSE2 Support. */
575	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
576	/** Bit 27 - SS - Self Snoop. */
577	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
578	/** Bit 28 - HTT - Hyper-Threading Technology. */
579	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
580	/** Bit 29 - TM - Therm. Monitor. */
581	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
582	/** Bit 31 - PBE - Pending Break Enabled. */
583	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
584	/** @} */
585
586	/** @name CPUID mwait/monitor information.
587	* CPUID query with EAX=5.
588	* @{
589	*/
590	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
591	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
592	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
593	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
594	/** @} */
595
596
597	/** @name CPUID Thermal and Power Management information.
598	* Generally Intel only unless noted otherwise.
599	* CPUID query with EAX=5. @{
600	*/
601	/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
602	#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
603	/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
604	#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
605	/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
606	#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
607	/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
608	#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
609	/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
610	#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
611	/** EAX Bit 6 - PTM - Package Thermal Management supported. */
612	#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
613	/** EAX Bit 7 - HWP - HWP base MSRs supported. */
614	#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
615	/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
616	#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
617	/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
618	#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
619	/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
620	#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
621	/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
622	#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
623	/** EAX Bit 13 - HDC - HDC base MSRs supported. */
624	#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
625	/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
626	#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
627	/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
628	#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
629	/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
630	#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
631	/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
632	#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
633
634	/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
635	#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
636	/** @} */
637
638
639	/** @name CPUID Structured Extended Feature information.
640	* CPUID query with EAX=7.
641	* @{
642	*/
643	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
644	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
645	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
646	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
647	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
648	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
649	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
650	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
651	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
652	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
653	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
654	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
655	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
656	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
657	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
658	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
659	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
660	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
661	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
662	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
663	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
664	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
665	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
666	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
667	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
668	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
669	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
670	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
671	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
672	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
673	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
674	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
675	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
676	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
677	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
678	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
679	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
680	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
681	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
682	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
683	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
684	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
685	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
686	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
687	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
688	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
689	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
690	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
691	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
692	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
693	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
694	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
695
696	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
697	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
698	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
699	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
700	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
701	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
702	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
703	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
704	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
705	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
706	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
707	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
708	/** ECX Bit 22 - RDPID - Support pread process ID. */
709	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
710	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
711	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
712
713	/** EDX bit 9 - SRBDS_CTRL - (Special Register Buffer Data Sample Control)
714	* Supports IA32_MCU_OPT_CTRL and IA32_MCU_OPT_CTRL.RNGDS_MITG_DIS. */
715	#define X86_CPUID_STEXT_FEATURE_EDX_SRBDS_CTRL RT_BIT_32(9)
716	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
717	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
718	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
719	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
720	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
721	* IBPB command in IA32_PRED_CMD. */
722	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
723	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
724	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
725	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
726	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
727	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
728	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
729	/** EDX Bit 30 - CORECAP - Supports the IA32_CORE_CAPABILITIES MSR. */
730	#define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
731	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
732	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
733
734	/** @} */
735
736
737	/** @name CPUID Extended Feature information.
738	* CPUID query with EAX=0x80000001.
739	* @{
740	*/
741	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
742	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
743
744	/** EDX Bit 11 - SYSCALL/SYSRET. */
745	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
746	/** EDX Bit 20 - No-Execute/Execute-Disable. */
747	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
748	/** EDX Bit 26 - 1 GB large page. */
749	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
750	/** EDX Bit 27 - RDTSCP. */
751	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
752	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
753	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
754	/** @}*/
755
756	/** @name CPUID AMD Feature information.
757	* CPUID query with EAX=0x80000001.
758	* @{
759	*/
760	/** Bit 0 - FPU - x87 FPU on Chip. */
761	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
762	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
763	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
764	/** Bit 2 - DE - Debugging extensions. */
765	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
766	/** Bit 3 - PSE - Page Size Extension. */
767	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
768	/** Bit 4 - TSC - Time Stamp Counter. */
769	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
770	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
771	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
772	/** Bit 6 - PAE - Physical Address Extension. */
773	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
774	/** Bit 7 - MCE - Machine Check Exception. */
775	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
776	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
777	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
778	/** Bit 9 - APIC - APIC On-Chip. */
779	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
780	/** Bit 12 - MTRR - Memory Type Range Registers. */
781	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
782	/** Bit 13 - PGE - PTE Global Bit. */
783	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
784	/** Bit 14 - MCA - Machine Check Architecture. */
785	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
786	/** Bit 15 - CMOV - Conditional Move Instructions. */
787	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
788	/** Bit 16 - PAT - Page Attribute Table. */
789	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
790	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
791	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
792	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
793	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
794	/** Bit 23 - MMX - Intel MMX Technology. */
795	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
796	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
797	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
798	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
799	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
800	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
801	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
802	/** Bit 31 - 3DNOW - AMD 3DNow. */
803	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
804
805	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
806	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
807	/** Bit 2 - SVM - AMD VM extensions. */
808	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
809	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
810	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
811	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
812	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
813	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
814	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
815	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
816	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
817	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
818	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
819	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
820	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
821	/** Bit 9 - OSVW - AMD OS visible workaround. */
822	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
823	/** Bit 10 - IBS - Instruct based sampling. */
824	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
825	/** Bit 11 - XOP - Extended operation support (see APM6). */
826	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
827	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
828	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
829	/** Bit 13 - WDT - AMD Watchdog timer support. */
830	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
831	/** Bit 15 - LWP - Lightweight profiling support. */
832	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
833	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
834	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
835	/** Bit 19 - NodeId - Indicates support for
836	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
837	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
838	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
839	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
840	/** Bit 22 - TopologyExtensions - . */
841	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
842	/** @} */
843
844
845	/** @name CPUID AMD Feature information.
846	* CPUID query with EAX=0x80000007.
847	* @{
848	*/
849	/** Bit 0 - TS - Temperature Sensor. */
850	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
851	/** Bit 1 - FID - Frequency ID Control. */
852	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
853	/** Bit 2 - VID - Voltage ID Control. */
854	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
855	/** Bit 3 - TTP - THERMTRIP. */
856	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
857	/** Bit 4 - TM - Hardware Thermal Control. */
858	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
859	/** Bit 5 - STC - Software Thermal Control. */
860	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
861	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
862	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
863	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
864	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
865	/** Bit 8 - TSCINVAR - TSC Invariant. */
866	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
867	/** Bit 9 - CPB - TSC Invariant. */
868	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
869	/** Bit 10 - EffFreqRO - MPERF/APERF. */
870	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
871	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
872	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
873	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
874	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
875	/** @} */
876
877
878	/** @name CPUID AMD extended feature extensions ID (EBX).
879	* CPUID query with EAX=0x80000008.
880	* @{
881	*/
882	/** Bit 0 - CLZERO - Clear zero instruction. */
883	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
884	/** Bit 1 - IRPerf - Instructions retired count support. */
885	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
886	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
887	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
888	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
889	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
890	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
891	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
892	/* AMD pipeline length: 9 feature bits ;-) */
893	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
894	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
895	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
896	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
897	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
898	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
899	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
900	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
901	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
902	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
903	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
904	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
905	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
906	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
907	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
908	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
909	/** Bit 26 - Speculative Store Bypass Disable not required. */
910	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
911	/** @} */
912
913
914	/** @name CPUID AMD SVM Feature information.
915	* CPUID query with EAX=0x8000000a.
916	* @{
917	*/
918	/** Bit 0 - NP - Nested Paging supported. */
919	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
920	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
921	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
922	/** Bit 2 - SVML - SVM locking bit supported. */
923	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
924	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
925	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
926	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
927	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
928	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
929	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
930	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
931	* VMCB.TLB_Control is supported. */
932	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
933	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
934	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
935	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
936	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
937	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
938	* intercept filter cycle count threshold. */
939	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
940	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
941	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
942	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
943	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
944	/** Bit 16 - VGIF - Supports virtualized GIF. */
945	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
946	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
947	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
948	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
949	* mode. */
950	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
951	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
952	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
953	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
954	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
955	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
956	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
957	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
958	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
959	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
960	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
961	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
962	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
963	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
964	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
965	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
966	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
967	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
968	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
969	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
970	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
971
972	/** @} */
973
974
975	/** @name CR0
976	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
977	* reserved flags.
978	* @{ */
979	/** Bit 0 - PE - Protection Enabled */
980	#define X86_CR0_PE RT_BIT_32(0)
981	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
982	#define X86_CR0_PE_BIT 0
983	/** Bit 1 - MP - Monitor Coprocessor */
984	#define X86_CR0_MP RT_BIT_32(1)
985	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
986	#define X86_CR0_MP_BIT 1
987	/** Bit 2 - EM - Emulation. */
988	#define X86_CR0_EM RT_BIT_32(2)
989	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
990	#define X86_CR0_EM_BIT 2
991	/** Bit 3 - TS - Task Switch. */
992	#define X86_CR0_TS RT_BIT_32(3)
993	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
994	#define X86_CR0_TS_BIT 3
995	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
996	#define X86_CR0_ET RT_BIT_32(4)
997	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
998	#define X86_CR0_ET_BIT 4
999	/** Bit 5 - NE - Numeric error (486+). */
1000	#define X86_CR0_NE RT_BIT_32(5)
1001	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
1002	#define X86_CR0_NE_BIT 5
1003	/** Bit 16 - WP - Write Protect (486+). */
1004	#define X86_CR0_WP RT_BIT_32(16)
1005	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
1006	#define X86_CR0_WP_BIT 16
1007	/** Bit 18 - AM - Alignment Mask (486+). */
1008	#define X86_CR0_AM RT_BIT_32(18)
1009	#define X86_CR0_ALIGNMENT_MASK RT_BIT_32(18)
1010	#define X86_CR0_AM_BIT 18
1011	/** Bit 29 - NW - Not Write-though (486+). */
1012	#define X86_CR0_NW RT_BIT_32(29)
1013	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
1014	#define X86_CR0_NW_BIT 29
1015	/** Bit 30 - WP - Cache Disable (486+). */
1016	#define X86_CR0_CD RT_BIT_32(30)
1017	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
1018	#define X86_CR0_CD_BIT 30
1019	/** Bit 31 - PG - Paging. */
1020	#define X86_CR0_PG RT_BIT_32(31)
1021	#define X86_CR0_PAGING RT_BIT_32(31)
1022	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
1023	/** @} */
1024
1025
1026	/** @name CR3
1027	* @{ */
1028	/** Bit 3 - PWT - Page-level Writes Transparent. */
1029	#define X86_CR3_PWT RT_BIT_32(3)
1030	#define X86_CR3_PWT_BIT 3
1031	/** Bit 4 - PCD - Page-level Cache Disable. */
1032	#define X86_CR3_PCD RT_BIT_32(4)
1033	#define X86_CR3_PCD_BIT 4
1034	/** Bits 12-31 - - Page directory page number. */
1035	#define X86_CR3_PAGE_MASK (0xfffff000)
1036	/** Bits 5-31 - - PAE Page directory page number. */
1037	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1038	/** Bits 12-51 - - AMD64 PML4 page number.
1039	* @note This is a maxed out mask, the actual acceptable CR3 value can
1040	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1041	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1042	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1043	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1044	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1045	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1046	/** @} */
1047
1048
1049	/** @name CR4
1050	* @{ */
1051	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1052	#define X86_CR4_VME RT_BIT_32(0)
1053	#define X86_CR4_VME_BIT 0
1054	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1055	#define X86_CR4_PVI RT_BIT_32(1)
1056	#define X86_CR4_PVI_BIT 1
1057	/** Bit 2 - TSD - Time Stamp Disable. */
1058	#define X86_CR4_TSD RT_BIT_32(2)
1059	#define X86_CR4_TSD_BIT 2
1060	/** Bit 3 - DE - Debugging Extensions. */
1061	#define X86_CR4_DE RT_BIT_32(3)
1062	#define X86_CR4_DE_BIT 3
1063	/** Bit 4 - PSE - Page Size Extension. */
1064	#define X86_CR4_PSE RT_BIT_32(4)
1065	#define X86_CR4_PSE_BIT 4
1066	/** Bit 5 - PAE - Physical Address Extension. */
1067	#define X86_CR4_PAE RT_BIT_32(5)
1068	#define X86_CR4_PAE_BIT 5
1069	/** Bit 6 - MCE - Machine-Check Enable. */
1070	#define X86_CR4_MCE RT_BIT_32(6)
1071	#define X86_CR4_MCE_BIT 6
1072	/** Bit 7 - PGE - Page Global Enable. */
1073	#define X86_CR4_PGE RT_BIT_32(7)
1074	#define X86_CR4_PGE_BIT 7
1075	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1076	#define X86_CR4_PCE RT_BIT_32(8)
1077	#define X86_CR4_PCE_BIT 8
1078	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1079	#define X86_CR4_OSFXSR RT_BIT_32(9)
1080	#define X86_CR4_OSFXSR_BIT 9
1081	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1082	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1083	#define X86_CR4_OSXMMEEXCPT_BIT 10
1084	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1085	#define X86_CR4_UMIP RT_BIT_32(11)
1086	#define X86_CR4_UMIP_BIT 11
1087	/** Bit 13 - VMXE - VMX mode is enabled. */
1088	#define X86_CR4_VMXE RT_BIT_32(13)
1089	#define X86_CR4_VMXE_BIT 13
1090	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1091	#define X86_CR4_SMXE RT_BIT_32(14)
1092	#define X86_CR4_SMXE_BIT 14
1093	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1094	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1095	#define X86_CR4_FSGSBASE_BIT 16
1096	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1097	#define X86_CR4_PCIDE RT_BIT_32(17)
1098	#define X86_CR4_PCIDE_BIT 17
1099	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1100	* extended states. */
1101	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1102	#define X86_CR4_OSXSAVE_BIT 18
1103	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1104	#define X86_CR4_SMEP RT_BIT_32(20)
1105	#define X86_CR4_SMEP_BIt 20
1106	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1107	#define X86_CR4_SMAP RT_BIT_32(21)
1108	#define X86_CR4_SMAP_BIT 21
1109	/** Bit 22 - PKE - Protection Key Enable. */
1110	#define X86_CR4_PKE RT_BIT_32(22)
1111	#define X86_CR4_PKE_BIT 22
1112	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1113	#define X86_CR4_CET RT_BIT_32(23)
1114	#define X86_CR4_CET_BIT 23
1115	/** @} */
1116
1117
1118	/** @name DR6
1119	* @{ */
1120	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1121	#define X86_DR6_B0 RT_BIT_32(0)
1122	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1123	#define X86_DR6_B1 RT_BIT_32(1)
1124	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1125	#define X86_DR6_B2 RT_BIT_32(2)
1126	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1127	#define X86_DR6_B3 RT_BIT_32(3)
1128	/** Mask of all the Bx bits. */
1129	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1130	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1131	#define X86_DR6_BD RT_BIT_32(13)
1132	/** Bit 14 - BS - Single step */
1133	#define X86_DR6_BS RT_BIT_32(14)
1134	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1135	#define X86_DR6_BT RT_BIT_32(15)
1136	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1137	#define X86_DR6_RTM RT_BIT_32(16)
1138	/** Value of DR6 after powerup/reset. */
1139	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1140	/** Bits which must be 1s in DR6. */
1141	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1142	/** Bits which must be 1s in DR6, when RTM is supported. */
1143	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1144	/** Bits which must be 0s in DR6. */
1145	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1146	/** Bits which must be 0s on writes to DR6. */
1147	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1148	/** @} */
1149
1150	/** Get the DR6.Bx bit for a the given breakpoint. */
1151	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1152
1153
1154	/** @name DR7
1155	* @{ */
1156	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1157	#define X86_DR7_L0 RT_BIT_32(0)
1158	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1159	#define X86_DR7_G0 RT_BIT_32(1)
1160	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1161	#define X86_DR7_L1 RT_BIT_32(2)
1162	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1163	#define X86_DR7_G1 RT_BIT_32(3)
1164	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1165	#define X86_DR7_L2 RT_BIT_32(4)
1166	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1167	#define X86_DR7_G2 RT_BIT_32(5)
1168	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1169	#define X86_DR7_L3 RT_BIT_32(6)
1170	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1171	#define X86_DR7_G3 RT_BIT_32(7)
1172	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1173	#define X86_DR7_LE RT_BIT_32(8)
1174	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1175	#define X86_DR7_GE RT_BIT_32(9)
1176
1177	/** L0, L1, L2, and L3. */
1178	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1179	/** L0, L1, L2, and L3. */
1180	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1181
1182	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1183	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1184	#define X86_DR7_RTM RT_BIT_32(11)
1185	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1186	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1187	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1188	* instruction is executed.
1189	* @see http://www.rcollins.org/secrets/DR7.html */
1190	#define X86_DR7_ICE_IR RT_BIT_32(12)
1191	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1192	* any DR register is accessed. */
1193	#define X86_DR7_GD RT_BIT_32(13)
1194	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1195	* Pentium. */
1196	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1197	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1198	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1199	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1200	#define X86_DR7_RW0_MASK (3 << 16)
1201	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1202	#define X86_DR7_LEN0_MASK (3 << 18)
1203	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1204	#define X86_DR7_RW1_MASK (3 << 20)
1205	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1206	#define X86_DR7_LEN1_MASK (3 << 22)
1207	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1208	#define X86_DR7_RW2_MASK (3 << 24)
1209	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1210	#define X86_DR7_LEN2_MASK (3 << 26)
1211	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1212	#define X86_DR7_RW3_MASK (3 << 28)
1213	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1214	#define X86_DR7_LEN3_MASK (3 << 30)
1215
1216	/** Bits which reads as 1s. */
1217	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1218	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1219	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1220	/** Bits which must be 0s when writing to DR7. */
1221	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1222
1223	/** Calcs the L bit of Nth breakpoint.
1224	* @param iBp The breakpoint number [0..3].
1225	*/
1226	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1227
1228	/** Calcs the G bit of Nth breakpoint.
1229	* @param iBp The breakpoint number [0..3].
1230	*/
1231	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1232
1233	/** Calcs the L and G bits of Nth breakpoint.
1234	* @param iBp The breakpoint number [0..3].
1235	*/
1236	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1237
1238	/** @name Read/Write values.
1239	* @{ */
1240	/** Break on instruction fetch only. */
1241	#define X86_DR7_RW_EO UINT32_C(0)
1242	/** Break on write only. */
1243	#define X86_DR7_RW_WO UINT32_C(1)
1244	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1245	#define X86_DR7_RW_IO UINT32_C(2)
1246	/** Break on read or write (but not instruction fetches). */
1247	#define X86_DR7_RW_RW UINT32_C(3)
1248	/** @} */
1249
1250	/** Shifts a X86_DR7_RW_* value to its right place.
1251	* @param iBp The breakpoint number [0..3].
1252	* @param fRw One of the X86_DR7_RW_* value.
1253	*/
1254	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1255
1256	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1257	* one of the X86_DR7_RW_XXX constants).
1258	*
1259	* @returns X86_DR7_RW_XXX
1260	* @param uDR7 DR7 value
1261	* @param iBp The breakpoint number [0..3].
1262	*/
1263	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1264
1265	/** R/W0, R/W1, R/W2, and R/W3. */
1266	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1267
1268	#ifndef VBOX_FOR_DTRACE_LIB
1269	/** Checks if the RW and LEN fields are set up for an instruction breakpoint.
1270	* @note This does not check if it's enabled. */
1271	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1272	/** Checks if an instruction breakpoint is enabled and configured correctly.
1273	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1274	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1275	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1276	/** Checks if there are any instruction fetch breakpoint types configured in
1277	* the RW and LEN registers and enabled in the Lx/Gx bits.
1278	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1279	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1280	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1281	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1282	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1283	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1284
1285	/** Checks if the RW field is set up for a read-write data breakpoint.
1286	* @note This does not check if it's enabled. */
1287	# define X86_DR7_IS_RW_CFG(a_uDR7, a_iBp) ( ~((a_uDR7) & (UINT32_C(0x00030000) << ((a_iBp) * 4))) == 0)
1288
1289	/** Checks if there are any read-write data breakpoint types configured in the
1290	* RW registers and enabled in the Lx/Gx bits.
1291	*
1292	* @note We don't consider the LEN registers here, even if qword isn't
1293	* techincally valid for older processors - see
1294	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1295	*/
1296	# define X86_DR7_ANY_RW_ENABLED(a_uDR7) \
1297	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00030000)) == UINT32_C(0x00030000)) \
1298	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00300000)) == UINT32_C(0x00300000)) \
1299	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x03000000)) == UINT32_C(0x03000000)) \
1300	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x30000000)) == UINT32_C(0x30000000)) )
1301
1302	/** Checks if the RW field is set up for a write-only or read-write data
1303	* breakpoint.
1304	* @note This does not check if it's enabled. */
1305	# define X86_DR7_IS_W_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x00010000) << ((a_iBp) * 4))) != 0)
1306
1307	/** Checks if there are any read-write or write-only data breakpoint types
1308	* configured in the the RW registers and enabled in the Lx/Gx bits.
1309	*
1310	* @note We don't consider the LEN registers here, even if qword isn't
1311	* techincally valid for older processors - see
1312	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1313	*/
1314	# define X86_DR7_ANY_W_ENABLED(a_uDR7) \
1315	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00010000)) != 0) \
1316	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00100000)) != 0) \
1317	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x01000000)) != 0) \
1318	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x10000000)) != 0) )
1319
1320	/** Checks if there are any I/O breakpoint types configured in the RW
1321	* registers. Does NOT check if these are enabled, sorry. */
1322	# define X86_DR7_ANY_RW_IO(uDR7) \
1323	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1324	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1325	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1326	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1327	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1328	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1329	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1330	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1331	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1332	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1333	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1334
1335	#endif /* !VBOX_FOR_DTRACE_LIB */
1336
1337	/** @name Length values.
1338	* @{ */
1339	#define X86_DR7_LEN_BYTE UINT32_C(0)
1340	#define X86_DR7_LEN_WORD UINT32_C(1)
1341	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1342	#define X86_DR7_LEN_DWORD UINT32_C(3)
1343	/** @} */
1344
1345	/** Shifts a X86_DR7_LEN_* value to its right place.
1346	* @param iBp The breakpoint number [0..3].
1347	* @param cb One of the X86_DR7_LEN_* values.
1348	*/
1349	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1350
1351	/** Fetch the breakpoint length bits from the DR7 value.
1352	* @param uDR7 DR7 value
1353	* @param iBp The breakpoint number [0..3].
1354	*/
1355	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1356
1357	/** Mask used to check if any breakpoints are enabled. */
1358	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1359
1360	/** LEN0, LEN1, LEN2, and LEN3. */
1361	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1362	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1363	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1364
1365	/** Value of DR7 after powerup/reset. */
1366	#define X86_DR7_INIT_VAL 0x400
1367	/** @} */
1368
1369
1370	/** @name Machine Specific Registers
1371	* @{
1372	*/
1373	/** Machine check address register (P5). */
1374	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1375	/** Machine check type register (P5). */
1376	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1377	/** Time Stamp Counter. */
1378	#define MSR_IA32_TSC 0x10
1379	#define MSR_IA32_CESR UINT32_C(0x00000011)
1380	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1381	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1382
1383	#define MSR_IA32_PLATFORM_ID 0x17
1384
1385	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1386	# define MSR_IA32_APICBASE 0x1b
1387	/** Local APIC enabled. */
1388	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1389	/** X2APIC enabled (requires the EN bit to be set). */
1390	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1391	/** The processor is the boot strap processor (BSP). */
1392	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1393	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1394	* width. */
1395	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1396	/** The default physical base address of the APIC. */
1397	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1398	/** Gets the physical base address from the MSR. */
1399	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1400	#endif
1401
1402	/** Memory Control (Intel-specific). */
1403	#define MSR_MEMORY_CTRL 0x33
1404	/** Memory Control - UC-store throttle. */
1405	#define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
1406	/** Memory Control - UC-lock disable. */
1407	#define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
1408	/** Memory Control - Split-lock disable. */
1409	#define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
1410
1411	/** Undocumented intel MSR for reporting thread and core counts.
1412	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1413	* first 16 bits is the thread count. The next 16 bits the core count, except
1414	* on Westmere where it seems it's only the next 4 bits for some reason. */
1415	#define MSR_CORE_THREAD_COUNT 0x35
1416
1417	/** CPU Feature control. */
1418	#define MSR_IA32_FEATURE_CONTROL 0x3A
1419	/** Feature control - Lock MSR from writes (R/W0). */
1420	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1421	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1422	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1423	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1424	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1425	/** Feature control - SENTER local functions enable (R/WL). */
1426	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1427	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1428	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1429	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1430	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1431	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1432	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1433	/** Feature control - SENTER global enable (R/WL). */
1434	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1435	/** Feature control - SGX launch control enable (R/WL). */
1436	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1437	/** Feature control - SGX global enable (R/WL). */
1438	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1439	/** Feature control - LMCE on (R/WL). */
1440	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1441
1442	/** Per-processor TSC adjust MSR. */
1443	#define MSR_IA32_TSC_ADJUST 0x3B
1444
1445	/** Spectre control register.
1446	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1447	#define MSR_IA32_SPEC_CTRL 0x48
1448	/** IBRS - Indirect branch restricted speculation. */
1449	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1450	/** STIBP - Single thread indirect branch predictors. */
1451	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1452	/** SSBD - Speculative Store Bypass Disable. */
1453	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1454
1455	/** Prediction command register.
1456	* Write only, logical processor scope, no state since write only. */
1457	#define MSR_IA32_PRED_CMD 0x49
1458	/** IBPB - Indirect branch prediction barrie when written as 1. */
1459	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1460
1461	/** BIOS update trigger (microcode update). */
1462	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1463
1464	/** BIOS update signature (microcode). */
1465	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1466
1467	/** SMM monitor control. */
1468	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1469	/** SMM control - Valid. */
1470	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1471	/** SMM control - VMXOFF unblocks SMI. */
1472	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1473	/** SMM control - MSEG base physical address. */
1474	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1475
1476	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1477	#define MSR_IA32_SMBASE 0x9E
1478
1479	/** General performance counter no. 0. */
1480	#define MSR_IA32_PMC0 0xC1
1481	/** General performance counter no. 1. */
1482	#define MSR_IA32_PMC1 0xC2
1483	/** General performance counter no. 2. */
1484	#define MSR_IA32_PMC2 0xC3
1485	/** General performance counter no. 3. */
1486	#define MSR_IA32_PMC3 0xC4
1487	/** General performance counter no. 4. */
1488	#define MSR_IA32_PMC4 0xC5
1489	/** General performance counter no. 5. */
1490	#define MSR_IA32_PMC5 0xC6
1491	/** General performance counter no. 6. */
1492	#define MSR_IA32_PMC6 0xC7
1493	/** General performance counter no. 7. */
1494	#define MSR_IA32_PMC7 0xC8
1495
1496	/** Nehalem power control. */
1497	#define MSR_IA32_PLATFORM_INFO 0xCE
1498
1499	/** Core Capabilities (Intel-specific). */
1500	#define MSR_IA32_CORE_CAPABILITIES 0xCF
1501	/** STLB QoS feature supported. */
1502	#define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
1503	/** FUSA feature supported. */
1504	#define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
1505	/** RSM instruction only allowed in CPL 0. */
1506	#define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
1507	/** UC lock disable supported. */
1508	#define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
1509	/** Split-lock disable supported. */
1510	#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
1511	/** Snoop filter QoS Mask MSRs supported. */
1512	#define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
1513	/** UC store throttling supported. */
1514	#define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
1515
1516	/** Get FSB clock status (Intel-specific). */
1517	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1518
1519	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1520	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1521
1522	/** C0 Maximum Frequency Clock Count */
1523	#define MSR_IA32_MPERF 0xE7
1524	/** C0 Actual Frequency Clock Count */
1525	#define MSR_IA32_APERF 0xE8
1526
1527	/** MTRR Capabilities. */
1528	#define MSR_IA32_MTRR_CAP 0xFE
1529	/** Bits 0-7 - VCNT - Variable range registers count. */
1530	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1531	/** Bit 8 - FIX - Fixed range registers supported. */
1532	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1533	/** Bit 10 - WC - Write-Combining memory type supported. */
1534	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1535	/** Bit 11 - SMRR - System Management Range Register supported. */
1536	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1537	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1538	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1539
1540
1541	#ifndef __ASSEMBLER__
1542	/**
1543	* Variable-range MTRR MSR pair.
1544	*/
1545	typedef struct X86MTRRVAR
1546	{
1547	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1548	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1549	} X86MTRRVAR;
1550	# ifndef VBOX_FOR_DTRACE_LIB
1551	AssertCompileSize(X86MTRRVAR, 16);
1552	# endif
1553	/** Pointer to a variable-range MTRR MSR pair. */
1554	typedef X86MTRRVAR *PX86MTRRVAR;
1555	/** Pointer to a const variable-range MTRR MSR pair. */
1556	typedef const X86MTRRVAR *PCX86MTRRVAR;
1557	#endif /* __ASSEMBLER__ */
1558
1559
1560	/** Memory types that can be encoded in MTRRs.
1561	* @{ */
1562	/** Uncacheable. */
1563	#define X86_MTRR_MT_UC 0
1564	/** Write Combining. */
1565	#define X86_MTRR_MT_WC 1
1566	/** Write-through. */
1567	#define X86_MTRR_MT_WT 4
1568	/** Write-protected. */
1569	#define X86_MTRR_MT_WP 5
1570	/** Writeback. */
1571	#define X86_MTRR_MT_WB 6
1572	/** @}*/
1573
1574	/** Architecture capabilities (bugfixes). */
1575	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1576	/** CPU is no subject to meltdown problems. */
1577	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1578	/** CPU has better IBRS and you can leave it on all the time. */
1579	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1580	/** CPU has return stack buffer (RSB) override. */
1581	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1582	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1583	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1584	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1585	/** CPU does not suffer from speculative store bypass (SSB) issues. */
1586	#define MSR_IA32_ARCH_CAP_F_SSB_NO RT_BIT_32(4)
1587	/** CPU does not suffer from microarchitectural data sampling (MDS) issues. */
1588	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(5)
1589	/** CPU does not suffer MCE after change code page size w/o invlpg issues. */
1590	#define MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO RT_BIT_32(6)
1591	/** CPU has RTM_DISABLE and TXS_CPUID_CLEAR support. */
1592	#define MSR_IA32_ARCH_CAP_F_TSX_CTRL RT_BIT_32(7)
1593	/** CPU does not suffer from transaction synchronization extensions (TSX)
1594	* asyncrhonous abort (TAA) issues. */
1595	#define MSR_IA32_ARCH_CAP_F_TAA_NO RT_BIT_32(8)
1596	/* 9 is 'reserved' */
1597	#define MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS RT_BIT_32(10)
1598	#define MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL RT_BIT_32(11)
1599	#define MSR_IA32_ARCH_CAP_F_DOITM RT_BIT_32(12)
1600	#define MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO RT_BIT_32(13)
1601	#define MSR_IA32_ARCH_CAP_F_FBSDP_NO RT_BIT_32(14)
1602	#define MSR_IA32_ARCH_CAP_F_PSDP_NO RT_BIT_32(15)
1603	/* 16 is 'reserved' */
1604	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR RT_BIT_32(17)
1605	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL RT_BIT_32(18)
1606	#define MSR_IA32_ARCH_CAP_F_RRSBA RT_BIT_32(19)
1607	#define MSR_IA32_ARCH_CAP_F_BHI_NO RT_BIT_32(20)
1608	#define MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS RT_BIT_32(21)
1609	/* 22 is 'reserved' */
1610	#define MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS RT_BIT_32(22)
1611	#define MSR_IA32_ARCH_CAP_F_PBRSB_NO RT_BIT_32(23)
1612	#define MSR_IA32_ARCH_CAP_F_GDS_CTRL RT_BIT_32(24)
1613	#define MSR_IA32_ARCH_CAP_F_GDS_NO RT_BIT_32(25)
1614	#define MSR_IA32_ARCH_CAP_F_RFDS_NO RT_BIT_32(26)
1615	#define MSR_IA32_ARCH_CAP_F_RFDS_CLEAR RT_BIT_32(27)
1616
1617	/** Flush command register. */
1618	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1619	/** Flush the level 1 data cache when this bit is written. */
1620	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1621
1622	/** Cache control/info. */
1623	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1624
1625	/** Microcode Update Operation Control (R/W). */
1626	#define MSR_IA32_MCU_OPT_CTRL 0x123
1627	#define MSR_IA32_MCU_OPT_CTRL_RNGDS_MITG_DIS RT_BIT_64(0)
1628	#define MSR_IA32_MCU_OPT_CTRL_RTM_ALLOW RT_BIT_64(1)
1629	#define MSR_IA32_MCU_OPT_CTRL_RTM_LOCKED RT_BIT_64(2)
1630	#define MSR_IA32_MCU_OPT_CTRL_FB_CLEAR_DIS RT_BIT_64(3)
1631	#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_DIS RT_BIT_64(4)
1632	#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_LOCK RT_BIT_64(5)
1633	#define MSR_IA32_MCU_OPT_CTRL_IGN_UMONITOR RT_BIT_64(6)
1634	#define MSR_IA32_MCU_OPT_CTRL_MON_UMON_MITG RT_BIT_64(7)
1635	/* Bits 63:7 reserved. */
1636	#define MSR_IA32_MCU_OPT_CTRL_RSVD_MASK UINT64_C(0xffffffffffffff80)
1637
1638	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1639	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1640	* R0 SS == CS + 8
1641	* R3 CS == CS + 16
1642	* R3 SS == CS + 24
1643	*/
1644	#define MSR_IA32_SYSENTER_CS 0x174
1645	/** SYSENTER_ESP - the R0 ESP. */
1646	#define MSR_IA32_SYSENTER_ESP 0x175
1647	/** SYSENTER_EIP - the R0 EIP. */
1648	#define MSR_IA32_SYSENTER_EIP 0x176
1649	#endif
1650
1651	/** Machine Check Global Capabilities Register. */
1652	#define MSR_IA32_MCG_CAP 0x179
1653	/** Machine Check Global Status Register. */
1654	#define MSR_IA32_MCG_STATUS 0x17A
1655	/** Machine Check Global Control Register. */
1656	#define MSR_IA32_MCG_CTRL 0x17B
1657
1658	/** Page Attribute Table. */
1659	#define MSR_IA32_CR_PAT 0x277
1660	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1661	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1662	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1663
1664	/** Memory types that can be encoded in the IA32_PAT MSR.
1665	* @{ */
1666	/** Uncacheable. */
1667	#define MSR_IA32_PAT_MT_UC 0
1668	/** Write Combining. */
1669	#define MSR_IA32_PAT_MT_WC 1
1670	/** Reserved value 2. */
1671	#define MSR_IA32_PAT_MT_RSVD_2 2
1672	/** Reserved value 3. */
1673	#define MSR_IA32_PAT_MT_RSVD_3 3
1674	/** Write-through. */
1675	#define MSR_IA32_PAT_MT_WT 4
1676	/** Write-protected. */
1677	#define MSR_IA32_PAT_MT_WP 5
1678	/** Writeback. */
1679	#define MSR_IA32_PAT_MT_WB 6
1680	/** Uncached (UC-). */
1681	#define MSR_IA32_PAT_MT_UCD 7
1682	/** @}*/
1683
1684
1685	/** Performance event select MSRs. (Intel only) */
1686	#define MSR_IA32_PERFEVTSEL0 0x186
1687	#define MSR_IA32_PERFEVTSEL1 0x187
1688	#define MSR_IA32_PERFEVTSEL2 0x188
1689	#define MSR_IA32_PERFEVTSEL3 0x189
1690
1691	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1692	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1693	* holds a ratio that Apple takes for TSC granularity.
1694	*
1695	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1696	#define MSR_FLEX_RATIO 0x194
1697	/** Performance state value and starting with Intel core more.
1698	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1699	#define MSR_IA32_PERF_STATUS 0x198
1700	#define MSR_IA32_PERF_CTL 0x199
1701	#define MSR_IA32_THERM_STATUS 0x19c
1702
1703	/** Offcore response event select registers. */
1704	#define MSR_OFFCORE_RSP_0 0x1a6
1705	#define MSR_OFFCORE_RSP_1 0x1a7
1706
1707	/** Enable misc. processor features (R/W). */
1708	#define MSR_IA32_MISC_ENABLE 0x1A0
1709	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1710	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1711	/** Automatic Thermal Control Circuit Enable (R/W). */
1712	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1713	/** Performance Monitoring Available (R). */
1714	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1715	/** Branch Trace Storage Unavailable (R/O). */
1716	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1717	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1718	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1719	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1720	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1721	/** If MONITOR/MWAIT is supported (R/W). */
1722	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1723	/** Limit CPUID Maxval to 3 leafs (R/W). */
1724	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1725	/** When set to 1, xTPR messages are disabled (R/W). */
1726	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1727	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1728	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1729
1730	/** Trace/Profile Resource Control (R/W) */
1731	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1732	/** Last branch record. */
1733	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1734	/** Branch trace flag (single step on branches). */
1735	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1736	/** Performance monitoring pin control (AMD only). */
1737	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1738	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1739	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1740	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1741	/** Trace message enable (Intel only). */
1742	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1743	/** Branch trace store (Intel only). */
1744	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1745	/** Branch trace interrupt (Intel only). */
1746	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1747	/** Branch trace off in privileged code (Intel only). */
1748	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1749	/** Branch trace off in user code (Intel only). */
1750	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1751	/** Freeze LBR on PMI flag (Intel only). */
1752	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1753	/** Freeze PERFMON on PMI flag (Intel only). */
1754	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1755	/** Freeze while SMM enabled (Intel only). */
1756	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1757	/** Advanced debugging of RTM regions (Intel only). */
1758	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1759	/** Debug control MSR valid bits (Intel only). */
1760	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1761	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1762	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1763	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1764	\| MSR_IA32_DEBUGCTL_RTM)
1765
1766	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1767	* @{ */
1768	#define MSR_P4_LASTBRANCH_0 0x1db
1769	#define MSR_P4_LASTBRANCH_1 0x1dc
1770	#define MSR_P4_LASTBRANCH_2 0x1dd
1771	#define MSR_P4_LASTBRANCH_3 0x1de
1772
1773	/** LBR Top-of-stack MSR (index to most recent record). */
1774	#define MSR_P4_LASTBRANCH_TOS 0x1da
1775	/** @} */
1776
1777	/** @name Last branch registers for Core 2 and related Xeons.
1778	* @{ */
1779	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1780	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1781	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1782	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1783
1784	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1785	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1786	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1787	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1788
1789	/** LBR Top-of-stack MSR (index to most recent record). */
1790	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1791	/** @} */
1792
1793	/** @name Last branch registers.
1794	* @{ */
1795	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1796	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1797	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1798	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1799	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1800	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1801	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1802	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1803	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1804	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1805	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1806	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1807	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1808	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1809	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1810	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1811	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1812	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1813	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1814	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1815	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1816	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1817	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1818	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1819	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1820	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1821	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1822	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1823	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1824	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1825	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1826	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1827
1828	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1829	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1830	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1831	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1832	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1833	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1834	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1835	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1836	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1837	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1838	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1839	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1840	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1841	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1842	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1843	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1844	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1845	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1846	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1847	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1848	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1849	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1850	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1851	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1852	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1853	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1854	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1855	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1856	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1857	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1858	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1859	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1860
1861	#define MSR_LASTBRANCH_0_INFO 0xdc0
1862	#define MSR_LASTBRANCH_1_INFO 0xdc1
1863	#define MSR_LASTBRANCH_2_INFO 0xdc2
1864	#define MSR_LASTBRANCH_3_INFO 0xdc3
1865	#define MSR_LASTBRANCH_4_INFO 0xdc4
1866	#define MSR_LASTBRANCH_5_INFO 0xdc5
1867	#define MSR_LASTBRANCH_6_INFO 0xdc6
1868	#define MSR_LASTBRANCH_7_INFO 0xdc7
1869	#define MSR_LASTBRANCH_8_INFO 0xdc8
1870	#define MSR_LASTBRANCH_9_INFO 0xdc9
1871	#define MSR_LASTBRANCH_10_INFO 0xdca
1872	#define MSR_LASTBRANCH_11_INFO 0xdcb
1873	#define MSR_LASTBRANCH_12_INFO 0xdcc
1874	#define MSR_LASTBRANCH_13_INFO 0xdcd
1875	#define MSR_LASTBRANCH_14_INFO 0xdce
1876	#define MSR_LASTBRANCH_15_INFO 0xdcf
1877	#define MSR_LASTBRANCH_16_INFO 0xdd0
1878	#define MSR_LASTBRANCH_17_INFO 0xdd1
1879	#define MSR_LASTBRANCH_18_INFO 0xdd2
1880	#define MSR_LASTBRANCH_19_INFO 0xdd3
1881	#define MSR_LASTBRANCH_20_INFO 0xdd4
1882	#define MSR_LASTBRANCH_21_INFO 0xdd5
1883	#define MSR_LASTBRANCH_22_INFO 0xdd6
1884	#define MSR_LASTBRANCH_23_INFO 0xdd7
1885	#define MSR_LASTBRANCH_24_INFO 0xdd8
1886	#define MSR_LASTBRANCH_25_INFO 0xdd9
1887	#define MSR_LASTBRANCH_26_INFO 0xdda
1888	#define MSR_LASTBRANCH_27_INFO 0xddb
1889	#define MSR_LASTBRANCH_28_INFO 0xddc
1890	#define MSR_LASTBRANCH_29_INFO 0xddd
1891	#define MSR_LASTBRANCH_30_INFO 0xdde
1892	#define MSR_LASTBRANCH_31_INFO 0xddf
1893
1894	/** LBR branch tracking selection MSR. */
1895	#define MSR_LASTBRANCH_SELECT 0x1c8
1896	/** LBR Top-of-stack MSR (index to most recent record). */
1897	#define MSR_LASTBRANCH_TOS 0x1c9
1898	/** @} */
1899
1900	/** @name Last event record registers.
1901	* @{ */
1902	/** Last event record source IP register. */
1903	#define MSR_LER_FROM_IP 0x1dd
1904	/** Last event record destination IP register. */
1905	#define MSR_LER_TO_IP 0x1de
1906	/** @} */
1907
1908	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1909	#define MSR_IA32_TSX_CTRL 0x122
1910
1911	/** Variable range MTRRs.
1912	* @{ */
1913	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1914	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1915	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1916	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1917	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1918	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1919	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1920	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1921	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1922	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1923	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1924	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1925	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1926	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1927	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1928	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1929	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1930	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1931	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1932	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1933	/** @} */
1934
1935	/** Fixed range MTRRs.
1936	* @{ */
1937	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1938	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1939	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1940	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1941	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1942	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1943	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1944	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1945	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1946	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1947	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1948	/** @} */
1949
1950	/** MTRR Default Type.
1951	* @{ */
1952	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1953	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1954	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1955	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1956	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1957	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1958	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1959	/** @} */
1960
1961	/** Variable-range MTRR physical mask valid. */
1962	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1963
1964	/** Variable-range MTRR memory type mask. */
1965	#define MSR_IA32_MTRR_PHYSBASE_MT_MASK UINT64_C(0xff)
1966
1967	/** Global performance counter control facilities (Intel only). */
1968	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1969	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1970	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1971
1972	/** Precise Event Based sampling (Intel only). */
1973	#define MSR_IA32_PEBS_ENABLE 0x3F1
1974
1975	#define MSR_IA32_MC0_CTL 0x400
1976	#define MSR_IA32_MC0_STATUS 0x401
1977
1978	/** Basic VMX information. */
1979	#define MSR_IA32_VMX_BASIC 0x480
1980	/** Allowed settings for pin-based VM execution controls. */
1981	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1982	/** Allowed settings for proc-based VM execution controls. */
1983	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1984	/** Allowed settings for the VM-exit controls. */
1985	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1986	/** Allowed settings for the VM-entry controls. */
1987	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1988	/** Misc VMX info. */
1989	#define MSR_IA32_VMX_MISC 0x485
1990	/** Fixed cleared bits in CR0. */
1991	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1992	/** Fixed set bits in CR0. */
1993	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1994	/** Fixed cleared bits in CR4. */
1995	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1996	/** Fixed set bits in CR4. */
1997	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1998	/** Information for enumerating fields in the VMCS. */
1999	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
2000	/** Allowed settings for secondary processor-based VM-execution controls. */
2001	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
2002	/** EPT capabilities. */
2003	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
2004	/** Allowed settings of all pin-based VM execution controls. */
2005	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
2006	/** Allowed settings of all proc-based VM execution controls. */
2007	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
2008	/** Allowed settings of all VMX exit controls. */
2009	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
2010	/** Allowed settings of all VMX entry controls. */
2011	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
2012	/** Allowed settings for the VM-function controls. */
2013	#define MSR_IA32_VMX_VMFUNC 0x491
2014	/** Tertiary processor-based VM execution controls. */
2015	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
2016	/** Secondary VM-exit controls. */
2017	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
2018
2019	/** Intel PT - Enable and control for trace packet generation. */
2020	#define MSR_IA32_RTIT_CTL 0x570
2021
2022	/** DS Save Area (R/W). */
2023	#define MSR_IA32_DS_AREA 0x600
2024	/** Running Average Power Limit (RAPL) power units. */
2025	#define MSR_RAPL_POWER_UNIT 0x606
2026	/** Package C3 Interrupt Response Limit. */
2027	#define MSR_PKGC3_IRTL 0x60a
2028	/** Package C6/C7S Interrupt Response Limit 1. */
2029	#define MSR_PKGC_IRTL1 0x60b
2030	/** Package C6/C7S Interrupt Response Limit 2. */
2031	#define MSR_PKGC_IRTL2 0x60c
2032	/** Package C2 Residency Counter. */
2033	#define MSR_PKG_C2_RESIDENCY 0x60d
2034	/** PKG RAPL Power Limit Control. */
2035	#define MSR_PKG_POWER_LIMIT 0x610
2036	/** PKG Energy Status. */
2037	#define MSR_PKG_ENERGY_STATUS 0x611
2038	/** PKG Perf Status. */
2039	#define MSR_PKG_PERF_STATUS 0x613
2040	/** PKG RAPL Parameters. */
2041	#define MSR_PKG_POWER_INFO 0x614
2042	/** DRAM RAPL Power Limit Control. */
2043	#define MSR_DRAM_POWER_LIMIT 0x618
2044	/** DRAM Energy Status. */
2045	#define MSR_DRAM_ENERGY_STATUS 0x619
2046	/** DRAM Performance Throttling Status. */
2047	#define MSR_DRAM_PERF_STATUS 0x61b
2048	/** DRAM RAPL Parameters. */
2049	#define MSR_DRAM_POWER_INFO 0x61c
2050	/** Package C10 Residency Counter. */
2051	#define MSR_PKG_C10_RESIDENCY 0x632
2052	/** PP0 Energy Status. */
2053	#define MSR_PP0_ENERGY_STATUS 0x639
2054	/** PP1 Energy Status. */
2055	#define MSR_PP1_ENERGY_STATUS 0x641
2056	/** Turbo Activation Ratio. */
2057	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
2058	/** Core Performance Limit Reasons. */
2059	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
2060
2061	/** Userspace Control flow Enforcement Technology setting. */
2062	#define MSR_IA32_U_CET 0x6a0
2063	/** Supervisor space Control flow Enforcement Technology setting. */
2064	#define MSR_IA32_S_CET 0x6a2
2065	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
2066	* @{ */
2067	/** Enables the Shadow stack. */
2068	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
2069	/** Enables WRSS{D,Q}W instructions. */
2070	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
2071	/** Enables indirect branch tracking. */
2072	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
2073	/** Enable legacy compatibility treatment for indirect branch tracking. */
2074	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
2075	/** Enables the use of no-track prefix for indirect branch tracking. */
2076	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
2077	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
2078	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
2079	/** Suppresses indirect branch tracking. */
2080	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
2081	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
2082	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
2083	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
2084	* on a ENDBRANCH instruction. */
2085	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
2086	/** @} */
2087
2088	/** X2APIC MSR range start. */
2089	#define MSR_IA32_X2APIC_START 0x800
2090	/** X2APIC MSR - APIC ID Register. */
2091	#define MSR_IA32_X2APIC_ID 0x802
2092	/** X2APIC MSR - APIC Version Register. */
2093	#define MSR_IA32_X2APIC_VERSION 0x803
2094	/** X2APIC MSR - Task Priority Register. */
2095	#define MSR_IA32_X2APIC_TPR 0x808
2096	/** X2APIC MSR - Processor Priority register. */
2097	#define MSR_IA32_X2APIC_PPR 0x80A
2098	/** X2APIC MSR - End Of Interrupt register. */
2099	#define MSR_IA32_X2APIC_EOI 0x80B
2100	/** X2APIC MSR - Logical Destination Register. */
2101	#define MSR_IA32_X2APIC_LDR 0x80D
2102	/** X2APIC MSR - Spurious Interrupt Vector Register. */
2103	#define MSR_IA32_X2APIC_SVR 0x80F
2104	/** X2APIC MSR - In-service Register (bits 31:0). */
2105	#define MSR_IA32_X2APIC_ISR0 0x810
2106	/** X2APIC MSR - In-service Register (bits 63:32). */
2107	#define MSR_IA32_X2APIC_ISR1 0x811
2108	/** X2APIC MSR - In-service Register (bits 95:64). */
2109	#define MSR_IA32_X2APIC_ISR2 0x812
2110	/** X2APIC MSR - In-service Register (bits 127:96). */
2111	#define MSR_IA32_X2APIC_ISR3 0x813
2112	/** X2APIC MSR - In-service Register (bits 159:128). */
2113	#define MSR_IA32_X2APIC_ISR4 0x814
2114	/** X2APIC MSR - In-service Register (bits 191:160). */
2115	#define MSR_IA32_X2APIC_ISR5 0x815
2116	/** X2APIC MSR - In-service Register (bits 223:192). */
2117	#define MSR_IA32_X2APIC_ISR6 0x816
2118	/** X2APIC MSR - In-service Register (bits 255:224). */
2119	#define MSR_IA32_X2APIC_ISR7 0x817
2120	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
2121	#define MSR_IA32_X2APIC_TMR0 0x818
2122	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
2123	#define MSR_IA32_X2APIC_TMR1 0x819
2124	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
2125	#define MSR_IA32_X2APIC_TMR2 0x81A
2126	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
2127	#define MSR_IA32_X2APIC_TMR3 0x81B
2128	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
2129	#define MSR_IA32_X2APIC_TMR4 0x81C
2130	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
2131	#define MSR_IA32_X2APIC_TMR5 0x81D
2132	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
2133	#define MSR_IA32_X2APIC_TMR6 0x81E
2134	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
2135	#define MSR_IA32_X2APIC_TMR7 0x81F
2136	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
2137	#define MSR_IA32_X2APIC_IRR0 0x820
2138	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
2139	#define MSR_IA32_X2APIC_IRR1 0x821
2140	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
2141	#define MSR_IA32_X2APIC_IRR2 0x822
2142	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
2143	#define MSR_IA32_X2APIC_IRR3 0x823
2144	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
2145	#define MSR_IA32_X2APIC_IRR4 0x824
2146	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
2147	#define MSR_IA32_X2APIC_IRR5 0x825
2148	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
2149	#define MSR_IA32_X2APIC_IRR6 0x826
2150	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
2151	#define MSR_IA32_X2APIC_IRR7 0x827
2152	/** X2APIC MSR - Error Status Register. */
2153	#define MSR_IA32_X2APIC_ESR 0x828
2154	/** X2APIC MSR - LVT CMCI Register. */
2155	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
2156	/** X2APIC MSR - Interrupt Command Register. */
2157	#define MSR_IA32_X2APIC_ICR 0x830
2158	/** X2APIC MSR - LVT Timer Register. */
2159	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
2160	/** X2APIC MSR - LVT Thermal Sensor Register. */
2161	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
2162	/** X2APIC MSR - LVT Performance Counter Register. */
2163	#define MSR_IA32_X2APIC_LVT_PERF 0x834
2164	/** X2APIC MSR - LVT LINT0 Register. */
2165	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2166	/** X2APIC MSR - LVT LINT1 Register. */
2167	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2168	/** X2APIC MSR - LVT Error Register . */
2169	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2170	/** X2APIC MSR - Timer Initial Count Register. */
2171	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2172	/** X2APIC MSR - Timer Current Count Register. */
2173	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2174	/** X2APIC MSR - Timer Divide Configuration Register. */
2175	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2176	/** X2APIC MSR - Self IPI. */
2177	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2178	/** X2APIC MSR range end. */
2179	#define MSR_IA32_X2APIC_END 0x8FF
2180	/** X2APIC MSR - LVT start range. */
2181	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2182	/** X2APIC MSR - LVT end range (inclusive). */
2183	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2184
2185	/** K6 EFER - Extended Feature Enable Register. */
2186	#define MSR_K6_EFER UINT32_C(0xc0000080)
2187	/** @todo document EFER */
2188	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2189	#define MSR_K6_EFER_SCE RT_BIT_32(0)
2190	/** Bit 8 - LME - Long mode enabled. (R/W) */
2191	#define MSR_K6_EFER_LME RT_BIT_32(8)
2192	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
2193	/** Bit 10 - LMA - Long mode active. (R) */
2194	#define MSR_K6_EFER_LMA RT_BIT_32(10)
2195	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
2196	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2197	#define MSR_K6_EFER_NXE RT_BIT_32(11)
2198	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
2199	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2200	#define MSR_K6_EFER_SVME RT_BIT_32(12)
2201	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2202	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2203	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
2204	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2205	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2206	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2207	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2208	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2209
2210	/** K6 STAR - SYSCALL/RET targets. */
2211	#define MSR_K6_STAR UINT32_C(0xc0000081)
2212	/** Shift value for getting the SYSRET CS and SS value. */
2213	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2214	/** Shift value for getting the SYSCALL CS and SS value. */
2215	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2216	/** Selector mask for use after shifting. */
2217	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2218	/** The mask which give the SYSCALL EIP. */
2219	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2220	/** K6 WHCR - Write Handling Control Register. */
2221	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2222	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2223	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2224	/** K6 PSOR - Processor State Observability Register. */
2225	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2226	/** K6 PFIR - Page Flush/Invalidate Register. */
2227	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2228
2229	/** Performance counter MSRs. (AMD only) */
2230	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2231	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2232	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2233	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2234	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2235	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2236	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2237	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2238
2239	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2240	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2241	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2242	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2243	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2244	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2245	/** K8 FS.base - The 64-bit base FS register. */
2246	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2247	/** K8 GS.base - The 64-bit base GS register. */
2248	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2249	/** K8 KernelGSbase - Used with SWAPGS. */
2250	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2251	/** K8 TSC_AUX - Used with RDTSCP. */
2252	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2253	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2254	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2255	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2256	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2257	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2258	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2259	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2260	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2261
2262	/** SMM MSRs. */
2263	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2264	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2265	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2266
2267	/** North bridge config? See BIOS & Kernel dev guides for
2268	* details. */
2269	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2270
2271	/** Hypertransport interrupt pending register.
2272	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2273	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2274
2275	/** SVM Control. */
2276	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2277	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2278	* features. */
2279	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2280	/** If set, non-intercepted INIT signals are converted to \#SX
2281	* exceptions. */
2282	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2283	/** Disables A20 masking. */
2284	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2285	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2286	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2287	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2288	* clear, EFER.SVME can be written normally. */
2289	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2290
2291	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2292	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2293	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2294	* host state during world switch. */
2295	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2296
2297	/** Virtualized speculation control for AMD processors.
2298	*
2299	* Unified interface among different CPU generations.
2300	* The VMM will set any architectural MSRs based on the CPU.
2301	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2302	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2303	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2304	/** Speculative Store Bypass Disable. */
2305	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2306
2307	/** @} */
2308
2309
2310	/** @name Page Table / Directory / Directory Pointers / L4.
2311	* @{
2312	*/
2313
2314	#ifndef __ASSEMBLER__
2315	/** Page table/directory entry as an unsigned integer. */
2316	typedef uint32_t X86PGUINT;
2317	/** Pointer to a page table/directory table entry as an unsigned integer. */
2318	typedef X86PGUINT *PX86PGUINT;
2319	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2320	typedef X86PGUINT const *PCX86PGUINT;
2321	#endif
2322
2323	/** Number of entries in a 32-bit PT/PD. */
2324	#define X86_PG_ENTRIES 1024
2325
2326
2327	#ifndef __ASSEMBLER__
2328	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2329	typedef uint64_t X86PGPAEUINT;
2330	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2331	typedef X86PGPAEUINT *PX86PGPAEUINT;
2332	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2333	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2334	#endif
2335
2336	/** Number of entries in a PAE PT/PD. */
2337	#define X86_PG_PAE_ENTRIES 512
2338	/** Number of entries in a PAE PDPT. */
2339	#define X86_PG_PAE_PDPE_ENTRIES 4
2340
2341	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2342	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2343	/** Number of entries in an AMD64 PDPT.
2344	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2345	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2346
2347	/** The size of a default page. */
2348	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2349	/** The page shift of a default page. */
2350	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2351	/** The default page offset mask. */
2352	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2353	/** The default page base mask for virtual addresses. */
2354	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2355	/** The default page base mask for virtual addresses - 32bit version. */
2356	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2357
2358	/** The size of a 4KB page. */
2359	#define X86_PAGE_4K_SIZE _4K
2360	/** The page shift of a 4KB page. */
2361	#define X86_PAGE_4K_SHIFT 12
2362	/** The 4KB page offset mask. */
2363	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2364	/** The 4KB page base mask for virtual addresses. */
2365	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2366	/** The 4KB page base mask for virtual addresses - 32bit version. */
2367	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2368
2369	/** The size of a 2MB page. */
2370	#define X86_PAGE_2M_SIZE _2M
2371	/** The page shift of a 2MB page. */
2372	#define X86_PAGE_2M_SHIFT 21
2373	/** The 2MB page offset mask. */
2374	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2375	/** The 2MB page base mask for virtual addresses. */
2376	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2377	/** The 2MB page base mask for virtual addresses - 32bit version. */
2378	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2379
2380	/** The size of a 4MB page. */
2381	#define X86_PAGE_4M_SIZE _4M
2382	/** The page shift of a 4MB page. */
2383	#define X86_PAGE_4M_SHIFT 22
2384	/** The 4MB page offset mask. */
2385	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2386	/** The 4MB page base mask for virtual addresses. */
2387	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2388	/** The 4MB page base mask for virtual addresses - 32bit version. */
2389	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2390
2391	/** The size of a 1GB page. */
2392	#define X86_PAGE_1G_SIZE _1G
2393	/** The page shift of a 1GB page. */
2394	#define X86_PAGE_1G_SHIFT 30
2395	/** The 1GB page offset mask. */
2396	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2397	/** The 1GB page base mask for virtual addresses. */
2398	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2399
2400	/**
2401	* Check if the given address is canonical.
2402	*/
2403	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2404
2405	/**
2406	* Gets the page base mask given the page shift.
2407	*/
2408	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2409
2410	/**
2411	* Gets the page offset mask given the page shift.
2412	*/
2413	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2414
2415
2416	/** @name Page Table Entry
2417	* @{
2418	*/
2419	/** Bit 0 - P - Present bit. */
2420	#define X86_PTE_BIT_P 0
2421	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2422	#define X86_PTE_BIT_RW 1
2423	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2424	#define X86_PTE_BIT_US 2
2425	/** Bit 3 - PWT - Page level write thru bit. */
2426	#define X86_PTE_BIT_PWT 3
2427	/** Bit 4 - PCD - Page level cache disable bit. */
2428	#define X86_PTE_BIT_PCD 4
2429	/** Bit 5 - A - Access bit. */
2430	#define X86_PTE_BIT_A 5
2431	/** Bit 6 - D - Dirty bit. */
2432	#define X86_PTE_BIT_D 6
2433	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2434	#define X86_PTE_BIT_PAT 7
2435	/** Bit 8 - G - Global flag. */
2436	#define X86_PTE_BIT_G 8
2437	/** Bits 63 - NX - PAE/LM - No execution flag. */
2438	#define X86_PTE_PAE_BIT_NX 63
2439
2440	/** Bit 0 - P - Present bit mask. */
2441	#define X86_PTE_P RT_BIT_32(0)
2442	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2443	#define X86_PTE_RW RT_BIT_32(1)
2444	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2445	#define X86_PTE_US RT_BIT_32(2)
2446	/** Bit 3 - PWT - Page level write thru bit mask. */
2447	#define X86_PTE_PWT RT_BIT_32(3)
2448	/** Bit 4 - PCD - Page level cache disable bit mask. */
2449	#define X86_PTE_PCD RT_BIT_32(4)
2450	/** Bit 5 - A - Access bit mask. */
2451	#define X86_PTE_A RT_BIT_32(5)
2452	/** Bit 6 - D - Dirty bit mask. */
2453	#define X86_PTE_D RT_BIT_32(6)
2454	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2455	#define X86_PTE_PAT RT_BIT_32(7)
2456	/** Bit 8 - G - Global bit mask. */
2457	#define X86_PTE_G RT_BIT_32(8)
2458
2459	/** Bits 9-11 - - Available for use to system software. */
2460	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2461	/** Bits 12-31 - - Physical Page number of the next level. */
2462	#define X86_PTE_PG_MASK ( 0xfffff000 )
2463
2464	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2465	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2466	/** Bits 63 - NX - PAE/LM - No execution flag. */
2467	#define X86_PTE_PAE_NX RT_BIT_64(63)
2468	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2469	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2470	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2471	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2472	/** No bits - - LM - MBZ bits when NX is active. */
2473	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2474	/** Bits 63 - - LM - MBZ bits when no NX. */
2475	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2476
2477	#ifndef __ASSEMBLER__
2478
2479	/**
2480	* Page table entry.
2481	*/
2482	typedef struct X86PTEBITS
2483	{
2484	/** Flags whether(=1) or not the page is present. */
2485	uint32_t u1Present : 1;
2486	/** Read(=0) / Write(=1) flag. */
2487	uint32_t u1Write : 1;
2488	/** User(=1) / Supervisor (=0) flag. */
2489	uint32_t u1User : 1;
2490	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2491	uint32_t u1WriteThru : 1;
2492	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2493	uint32_t u1CacheDisable : 1;
2494	/** Accessed flag.
2495	* Indicates that the page have been read or written to. */
2496	uint32_t u1Accessed : 1;
2497	/** Dirty flag.
2498	* Indicates that the page has been written to. */
2499	uint32_t u1Dirty : 1;
2500	/** Reserved / If PAT enabled, bit 2 of the index. */
2501	uint32_t u1PAT : 1;
2502	/** Global flag. (Ignored in all but final level.) */
2503	uint32_t u1Global : 1;
2504	/** Available for use to system software. */
2505	uint32_t u3Available : 3;
2506	/** Physical Page number of the next level. */
2507	uint32_t u20PageNo : 20;
2508	} X86PTEBITS;
2509	# ifndef VBOX_FOR_DTRACE_LIB
2510	AssertCompileSize(X86PTEBITS, 4);
2511	# endif
2512	/** Pointer to a page table entry. */
2513	typedef X86PTEBITS *PX86PTEBITS;
2514	/** Pointer to a const page table entry. */
2515	typedef const X86PTEBITS *PCX86PTEBITS;
2516
2517	/**
2518	* Page table entry.
2519	*/
2520	typedef union X86PTE
2521	{
2522	/** Unsigned integer view */
2523	X86PGUINT u;
2524	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2525	/** Bit field view. */
2526	X86PTEBITS n;
2527	# endif
2528	/** 32-bit view. */
2529	uint32_t au32[1];
2530	/** 16-bit view. */
2531	uint16_t au16[2];
2532	/** 8-bit view. */
2533	uint8_t au8[4];
2534	} X86PTE;
2535	# ifndef VBOX_FOR_DTRACE_LIB
2536	AssertCompileSize(X86PTE, 4);
2537	# endif
2538	/** Pointer to a page table entry. */
2539	typedef X86PTE *PX86PTE;
2540	/** Pointer to a const page table entry. */
2541	typedef const X86PTE *PCX86PTE;
2542
2543
2544	/**
2545	* PAE page table entry.
2546	*/
2547	typedef struct X86PTEPAEBITS
2548	{
2549	/** Flags whether(=1) or not the page is present. */
2550	uint32_t u1Present : 1;
2551	/** Read(=0) / Write(=1) flag. */
2552	uint32_t u1Write : 1;
2553	/** User(=1) / Supervisor(=0) flag. */
2554	uint32_t u1User : 1;
2555	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2556	uint32_t u1WriteThru : 1;
2557	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2558	uint32_t u1CacheDisable : 1;
2559	/** Accessed flag.
2560	* Indicates that the page have been read or written to. */
2561	uint32_t u1Accessed : 1;
2562	/** Dirty flag.
2563	* Indicates that the page has been written to. */
2564	uint32_t u1Dirty : 1;
2565	/** Reserved / If PAT enabled, bit 2 of the index. */
2566	uint32_t u1PAT : 1;
2567	/** Global flag. (Ignored in all but final level.) */
2568	uint32_t u1Global : 1;
2569	/** Available for use to system software. */
2570	uint32_t u3Available : 3;
2571	/** Physical Page number of the next level - Low Part. Don't use this. */
2572	uint32_t u20PageNoLow : 20;
2573	/** Physical Page number of the next level - High Part. Don't use this. */
2574	uint32_t u20PageNoHigh : 20;
2575	/** MBZ bits */
2576	uint32_t u11Reserved : 11;
2577	/** No Execute flag. */
2578	uint32_t u1NoExecute : 1;
2579	} X86PTEPAEBITS;
2580	# ifndef VBOX_FOR_DTRACE_LIB
2581	AssertCompileSize(X86PTEPAEBITS, 8);
2582	# endif
2583	/** Pointer to a page table entry. */
2584	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2585	/** Pointer to a page table entry. */
2586	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2587
2588	/**
2589	* PAE Page table entry.
2590	*/
2591	typedef union X86PTEPAE
2592	{
2593	/** Unsigned integer view */
2594	X86PGPAEUINT u;
2595	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2596	/** Bit field view. */
2597	X86PTEPAEBITS n;
2598	# endif
2599	/** 32-bit view. */
2600	uint32_t au32[2];
2601	/** 16-bit view. */
2602	uint16_t au16[4];
2603	/** 8-bit view. */
2604	uint8_t au8[8];
2605	} X86PTEPAE;
2606	# ifndef VBOX_FOR_DTRACE_LIB
2607	AssertCompileSize(X86PTEPAE, 8);
2608	# endif
2609	/** Pointer to a PAE page table entry. */
2610	typedef X86PTEPAE *PX86PTEPAE;
2611	/** Pointer to a const PAE page table entry. */
2612	typedef const X86PTEPAE *PCX86PTEPAE;
2613	/** @} */
2614
2615	/**
2616	* Page table.
2617	*/
2618	typedef struct X86PT
2619	{
2620	/** PTE Array. */
2621	X86PTE a[X86_PG_ENTRIES];
2622	} X86PT;
2623	# ifndef VBOX_FOR_DTRACE_LIB
2624	AssertCompileSize(X86PT, 4096);
2625	# endif
2626	/** Pointer to a page table. */
2627	typedef X86PT *PX86PT;
2628	/** Pointer to a const page table. */
2629	typedef const X86PT *PCX86PT;
2630
2631	#endif /* !__ASSEMBLER__ */
2632
2633	/** The page shift to get the PT index. */
2634	#define X86_PT_SHIFT 12
2635	/** The PT index mask (apply to a shifted page address). */
2636	#define X86_PT_MASK 0x3ff
2637
2638
2639	#ifndef __ASSEMBLER__
2640	/**
2641	* Page directory.
2642	*/
2643	typedef struct X86PTPAE
2644	{
2645	/** PTE Array. */
2646	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2647	} X86PTPAE;
2648	# ifndef VBOX_FOR_DTRACE_LIB
2649	AssertCompileSize(X86PTPAE, 4096);
2650	# endif
2651	/** Pointer to a page table. */
2652	typedef X86PTPAE *PX86PTPAE;
2653	/** Pointer to a const page table. */
2654	typedef const X86PTPAE *PCX86PTPAE;
2655	#endif /* !__ASSEMBLER__ */
2656
2657	/** The page shift to get the PA PTE index. */
2658	#define X86_PT_PAE_SHIFT 12
2659	/** The PAE PT index mask (apply to a shifted page address). */
2660	#define X86_PT_PAE_MASK 0x1ff
2661
2662
2663	/** @name 4KB Page Directory Entry
2664	* @{
2665	*/
2666	/** Bit 0 - P - Present bit. */
2667	#define X86_PDE_P RT_BIT_32(0)
2668	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2669	#define X86_PDE_RW RT_BIT_32(1)
2670	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2671	#define X86_PDE_US RT_BIT_32(2)
2672	/** Bit 3 - PWT - Page level write thru bit. */
2673	#define X86_PDE_PWT RT_BIT_32(3)
2674	/** Bit 4 - PCD - Page level cache disable bit. */
2675	#define X86_PDE_PCD RT_BIT_32(4)
2676	/** Bit 5 - A - Access bit. */
2677	#define X86_PDE_A RT_BIT_32(5)
2678	/** Bit 7 - PS - Page size attribute.
2679	* Clear mean 4KB pages, set means large pages (2/4MB). */
2680	#define X86_PDE_PS RT_BIT_32(7)
2681	/** Bits 9-11 - - Available for use to system software. */
2682	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2683	/** Bits 12-31 - - Physical Page number of the next level. */
2684	#define X86_PDE_PG_MASK ( 0xfffff000 )
2685
2686	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2687	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2688	/** Bits 63 - NX - PAE/LM - No execution flag. */
2689	#define X86_PDE_PAE_NX RT_BIT_64(63)
2690	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2691	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2692	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2693	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2694	/** Bit 7 - - LM - MBZ bits when NX is active. */
2695	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2696	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2697	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2698
2699	#ifndef __ASSEMBLER__
2700
2701	/**
2702	* Page directory entry.
2703	*/
2704	typedef struct X86PDEBITS
2705	{
2706	/** Flags whether(=1) or not the page is present. */
2707	uint32_t u1Present : 1;
2708	/** Read(=0) / Write(=1) flag. */
2709	uint32_t u1Write : 1;
2710	/** User(=1) / Supervisor (=0) flag. */
2711	uint32_t u1User : 1;
2712	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2713	uint32_t u1WriteThru : 1;
2714	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2715	uint32_t u1CacheDisable : 1;
2716	/** Accessed flag.
2717	* Indicates that the page has been read or written to. */
2718	uint32_t u1Accessed : 1;
2719	/** Reserved / Ignored (dirty bit). */
2720	uint32_t u1Reserved0 : 1;
2721	/** Size bit if PSE is enabled - in any event it's 0. */
2722	uint32_t u1Size : 1;
2723	/** Reserved / Ignored (global bit). */
2724	uint32_t u1Reserved1 : 1;
2725	/** Available for use to system software. */
2726	uint32_t u3Available : 3;
2727	/** Physical Page number of the next level. */
2728	uint32_t u20PageNo : 20;
2729	} X86PDEBITS;
2730	# ifndef VBOX_FOR_DTRACE_LIB
2731	AssertCompileSize(X86PDEBITS, 4);
2732	# endif
2733	/** Pointer to a page directory entry. */
2734	typedef X86PDEBITS *PX86PDEBITS;
2735	/** Pointer to a const page directory entry. */
2736	typedef const X86PDEBITS *PCX86PDEBITS;
2737
2738
2739	/**
2740	* PAE page directory entry.
2741	*/
2742	typedef struct X86PDEPAEBITS
2743	{
2744	/** Flags whether(=1) or not the page is present. */
2745	uint32_t u1Present : 1;
2746	/** Read(=0) / Write(=1) flag. */
2747	uint32_t u1Write : 1;
2748	/** User(=1) / Supervisor (=0) flag. */
2749	uint32_t u1User : 1;
2750	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2751	uint32_t u1WriteThru : 1;
2752	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2753	uint32_t u1CacheDisable : 1;
2754	/** Accessed flag.
2755	* Indicates that the page has been read or written to. */
2756	uint32_t u1Accessed : 1;
2757	/** Reserved / Ignored (dirty bit). */
2758	uint32_t u1Reserved0 : 1;
2759	/** Size bit if PSE is enabled - in any event it's 0. */
2760	uint32_t u1Size : 1;
2761	/** Reserved / Ignored (global bit). / */
2762	uint32_t u1Reserved1 : 1;
2763	/** Available for use to system software. */
2764	uint32_t u3Available : 3;
2765	/** Physical Page number of the next level - Low Part. Don't use! */
2766	uint32_t u20PageNoLow : 20;
2767	/** Physical Page number of the next level - High Part. Don't use! */
2768	uint32_t u20PageNoHigh : 20;
2769	/** MBZ bits */
2770	uint32_t u11Reserved : 11;
2771	/** No Execute flag. */
2772	uint32_t u1NoExecute : 1;
2773	} X86PDEPAEBITS;
2774	# ifndef VBOX_FOR_DTRACE_LIB
2775	AssertCompileSize(X86PDEPAEBITS, 8);
2776	# endif
2777	/** Pointer to a page directory entry. */
2778	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2779	/** Pointer to a const page directory entry. */
2780	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2781
2782	#endif /* !__ASSEMBLER__ */
2783
2784	/** @} */
2785
2786
2787	/** @name 2/4MB Page Directory Entry
2788	* @{
2789	*/
2790	/** Bit 0 - P - Present bit. */
2791	#define X86_PDE4M_P RT_BIT_32(0)
2792	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2793	#define X86_PDE4M_RW RT_BIT_32(1)
2794	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2795	#define X86_PDE4M_US RT_BIT_32(2)
2796	/** Bit 3 - PWT - Page level write thru bit. */
2797	#define X86_PDE4M_PWT RT_BIT_32(3)
2798	/** Bit 4 - PCD - Page level cache disable bit. */
2799	#define X86_PDE4M_PCD RT_BIT_32(4)
2800	/** Bit 5 - A - Access bit. */
2801	#define X86_PDE4M_A RT_BIT_32(5)
2802	/** Bit 6 - D - Dirty bit. */
2803	#define X86_PDE4M_D RT_BIT_32(6)
2804	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2805	#define X86_PDE4M_PS RT_BIT_32(7)
2806	/** Bit 8 - G - Global flag. */
2807	#define X86_PDE4M_G RT_BIT_32(8)
2808	/** Bits 9-11 - AVL - Available for use to system software. */
2809	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2810	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2811	#define X86_PDE4M_PAT RT_BIT_32(12)
2812	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2813	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2814	/** Bits 22-31 - - Physical Page number. */
2815	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2816	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2817	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2818	/** The number of bits to the high part of the page number. */
2819	#define X86_PDE4M_PG_HIGH_SHIFT 19
2820	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2821	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2822
2823	/** Bits 21-51 - - PAE/LM - Physical Page number.
2824	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2825	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2826	/** Bits 63 - NX - PAE/LM - No execution flag. */
2827	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2828	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2829	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2830	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2831	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2832	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2833	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2834	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2835	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2836
2837	#ifndef __ASSEMBLER__
2838
2839	/**
2840	* 4MB page directory entry.
2841	*/
2842	typedef struct X86PDE4MBITS
2843	{
2844	/** Flags whether(=1) or not the page is present. */
2845	uint32_t u1Present : 1;
2846	/** Read(=0) / Write(=1) flag. */
2847	uint32_t u1Write : 1;
2848	/** User(=1) / Supervisor (=0) flag. */
2849	uint32_t u1User : 1;
2850	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2851	uint32_t u1WriteThru : 1;
2852	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2853	uint32_t u1CacheDisable : 1;
2854	/** Accessed flag.
2855	* Indicates that the page have been read or written to. */
2856	uint32_t u1Accessed : 1;
2857	/** Dirty flag.
2858	* Indicates that the page has been written to. */
2859	uint32_t u1Dirty : 1;
2860	/** Page size flag - always 1 for 4MB entries. */
2861	uint32_t u1Size : 1;
2862	/** Global flag. */
2863	uint32_t u1Global : 1;
2864	/** Available for use to system software. */
2865	uint32_t u3Available : 3;
2866	/** Reserved / If PAT enabled, bit 2 of the index. */
2867	uint32_t u1PAT : 1;
2868	/** Bits 32-39 of the page number on AMD64.
2869	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2870	uint32_t u8PageNoHigh : 8;
2871	/** Reserved. */
2872	uint32_t u1Reserved : 1;
2873	/** Physical Page number of the page. */
2874	uint32_t u10PageNo : 10;
2875	} X86PDE4MBITS;
2876	# ifndef VBOX_FOR_DTRACE_LIB
2877	AssertCompileSize(X86PDE4MBITS, 4);
2878	# endif
2879	/** Pointer to a page table entry. */
2880	typedef X86PDE4MBITS *PX86PDE4MBITS;
2881	/** Pointer to a const page table entry. */
2882	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2883
2884
2885	/**
2886	* 2MB PAE page directory entry.
2887	*/
2888	typedef struct X86PDE2MPAEBITS
2889	{
2890	/** Flags whether(=1) or not the page is present. */
2891	uint32_t u1Present : 1;
2892	/** Read(=0) / Write(=1) flag. */
2893	uint32_t u1Write : 1;
2894	/** User(=1) / Supervisor(=0) flag. */
2895	uint32_t u1User : 1;
2896	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2897	uint32_t u1WriteThru : 1;
2898	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2899	uint32_t u1CacheDisable : 1;
2900	/** Accessed flag.
2901	* Indicates that the page have been read or written to. */
2902	uint32_t u1Accessed : 1;
2903	/** Dirty flag.
2904	* Indicates that the page has been written to. */
2905	uint32_t u1Dirty : 1;
2906	/** Page size flag - always 1 for 2MB entries. */
2907	uint32_t u1Size : 1;
2908	/** Global flag. */
2909	uint32_t u1Global : 1;
2910	/** Available for use to system software. */
2911	uint32_t u3Available : 3;
2912	/** Reserved / If PAT enabled, bit 2 of the index. */
2913	uint32_t u1PAT : 1;
2914	/** Reserved. */
2915	uint32_t u9Reserved : 9;
2916	/** Physical Page number of the next level - Low part. Don't use! */
2917	uint32_t u10PageNoLow : 10;
2918	/** Physical Page number of the next level - High part. Don't use! */
2919	uint32_t u20PageNoHigh : 20;
2920	/** MBZ bits */
2921	uint32_t u11Reserved : 11;
2922	/** No Execute flag. */
2923	uint32_t u1NoExecute : 1;
2924	} X86PDE2MPAEBITS;
2925	# ifndef VBOX_FOR_DTRACE_LIB
2926	AssertCompileSize(X86PDE2MPAEBITS, 8);
2927	# endif
2928	/** Pointer to a 2MB PAE page table entry. */
2929	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2930	/** Pointer to a 2MB PAE page table entry. */
2931	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2932
2933	#endif /* !__ASSEMBLER__ */
2934
2935	/** @} */
2936
2937	#ifndef __ASSEMBLER__
2938
2939	/**
2940	* Page directory entry.
2941	*/
2942	typedef union X86PDE
2943	{
2944	/** Unsigned integer view. */
2945	X86PGUINT u;
2946	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2947	/** Normal view. */
2948	X86PDEBITS n;
2949	/** 4MB view (big). */
2950	X86PDE4MBITS b;
2951	# endif
2952	/** 8 bit unsigned integer view. */
2953	uint8_t au8[4];
2954	/** 16 bit unsigned integer view. */
2955	uint16_t au16[2];
2956	/** 32 bit unsigned integer view. */
2957	uint32_t au32[1];
2958	} X86PDE;
2959	# ifndef VBOX_FOR_DTRACE_LIB
2960	AssertCompileSize(X86PDE, 4);
2961	# endif
2962	/** Pointer to a page directory entry. */
2963	typedef X86PDE *PX86PDE;
2964	/** Pointer to a const page directory entry. */
2965	typedef const X86PDE *PCX86PDE;
2966
2967	/**
2968	* PAE page directory entry.
2969	*/
2970	typedef union X86PDEPAE
2971	{
2972	/** Unsigned integer view. */
2973	X86PGPAEUINT u;
2974	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2975	/** Normal view. */
2976	X86PDEPAEBITS n;
2977	/** 2MB page view (big). */
2978	X86PDE2MPAEBITS b;
2979	# endif
2980	/** 8 bit unsigned integer view. */
2981	uint8_t au8[8];
2982	/** 16 bit unsigned integer view. */
2983	uint16_t au16[4];
2984	/** 32 bit unsigned integer view. */
2985	uint32_t au32[2];
2986	} X86PDEPAE;
2987	# ifndef VBOX_FOR_DTRACE_LIB
2988	AssertCompileSize(X86PDEPAE, 8);
2989	# endif
2990	/** Pointer to a page directory entry. */
2991	typedef X86PDEPAE *PX86PDEPAE;
2992	/** Pointer to a const page directory entry. */
2993	typedef const X86PDEPAE *PCX86PDEPAE;
2994
2995	/**
2996	* Page directory.
2997	*/
2998	typedef struct X86PD
2999	{
3000	/** PDE Array. */
3001	X86PDE a[X86_PG_ENTRIES];
3002	} X86PD;
3003	# ifndef VBOX_FOR_DTRACE_LIB
3004	AssertCompileSize(X86PD, 4096);
3005	# endif
3006	/** Pointer to a page directory. */
3007	typedef X86PD *PX86PD;
3008	/** Pointer to a const page directory. */
3009	typedef const X86PD *PCX86PD;
3010
3011	#endif /* !__ASSEMBLER__ */
3012
3013	/** The page shift to get the PD index. */
3014	#define X86_PD_SHIFT 22
3015	/** The PD index mask (apply to a shifted page address). */
3016	#define X86_PD_MASK 0x3ff
3017
3018
3019	#ifndef __ASSEMBLER__
3020	/**
3021	* PAE page directory.
3022	*/
3023	typedef struct X86PDPAE
3024	{
3025	/** PDE Array. */
3026	X86PDEPAE a[X86_PG_PAE_ENTRIES];
3027	} X86PDPAE;
3028	# ifndef VBOX_FOR_DTRACE_LIB
3029	AssertCompileSize(X86PDPAE, 4096);
3030	# endif
3031	/** Pointer to a PAE page directory. */
3032	typedef X86PDPAE *PX86PDPAE;
3033	/** Pointer to a const PAE page directory. */
3034	typedef const X86PDPAE *PCX86PDPAE;
3035	#endif /* !__ASSEMBLER__ */
3036
3037	/** The page shift to get the PAE PD index. */
3038	#define X86_PD_PAE_SHIFT 21
3039	/** The PAE PD index mask (apply to a shifted page address). */
3040	#define X86_PD_PAE_MASK 0x1ff
3041
3042
3043	/** @name Page Directory Pointer Table Entry (PAE)
3044	* @{
3045	*/
3046	/** Bit 0 - P - Present bit. */
3047	#define X86_PDPE_P RT_BIT_32(0)
3048	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
3049	#define X86_PDPE_RW RT_BIT_32(1)
3050	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
3051	#define X86_PDPE_US RT_BIT_32(2)
3052	/** Bit 3 - PWT - Page level write thru bit. */
3053	#define X86_PDPE_PWT RT_BIT_32(3)
3054	/** Bit 4 - PCD - Page level cache disable bit. */
3055	#define X86_PDPE_PCD RT_BIT_32(4)
3056	/** Bit 5 - A - Access bit. Long Mode only. */
3057	#define X86_PDPE_A RT_BIT_32(5)
3058	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
3059	#define X86_PDPE_LM_PS RT_BIT_32(7)
3060	/** Bits 9-11 - - Available for use to system software. */
3061	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3062	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3063	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
3064	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
3065	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
3066	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
3067	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
3068	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
3069	#define X86_PDPE_LM_NX RT_BIT_64(63)
3070	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
3071	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
3072	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
3073	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
3074	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
3075	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
3076	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
3077	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
3078
3079	#ifndef __ASSEMBLER__
3080
3081	/**
3082	* Page directory pointer table entry.
3083	*/
3084	typedef struct X86PDPEBITS
3085	{
3086	/** Flags whether(=1) or not the page is present. */
3087	uint32_t u1Present : 1;
3088	/** Chunk of reserved bits. */
3089	uint32_t u2Reserved : 2;
3090	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3091	uint32_t u1WriteThru : 1;
3092	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3093	uint32_t u1CacheDisable : 1;
3094	/** Chunk of reserved bits. */
3095	uint32_t u4Reserved : 4;
3096	/** Available for use to system software. */
3097	uint32_t u3Available : 3;
3098	/** Physical Page number of the next level - Low Part. Don't use! */
3099	uint32_t u20PageNoLow : 20;
3100	/** Physical Page number of the next level - High Part. Don't use! */
3101	uint32_t u20PageNoHigh : 20;
3102	/** MBZ bits */
3103	uint32_t u12Reserved : 12;
3104	} X86PDPEBITS;
3105	# ifndef VBOX_FOR_DTRACE_LIB
3106	AssertCompileSize(X86PDPEBITS, 8);
3107	# endif
3108	/** Pointer to a page directory pointer table entry. */
3109	typedef X86PDPEBITS *PX86PTPEBITS;
3110	/** Pointer to a const page directory pointer table entry. */
3111	typedef const X86PDPEBITS *PCX86PTPEBITS;
3112
3113	/**
3114	* Page directory pointer table entry. AMD64 version
3115	*/
3116	typedef struct X86PDPEAMD64BITS
3117	{
3118	/** Flags whether(=1) or not the page is present. */
3119	uint32_t u1Present : 1;
3120	/** Read(=0) / Write(=1) flag. */
3121	uint32_t u1Write : 1;
3122	/** User(=1) / Supervisor (=0) flag. */
3123	uint32_t u1User : 1;
3124	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3125	uint32_t u1WriteThru : 1;
3126	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3127	uint32_t u1CacheDisable : 1;
3128	/** Accessed flag.
3129	* Indicates that the page have been read or written to. */
3130	uint32_t u1Accessed : 1;
3131	/** Chunk of reserved bits. */
3132	uint32_t u3Reserved : 3;
3133	/** Available for use to system software. */
3134	uint32_t u3Available : 3;
3135	/** Physical Page number of the next level - Low Part. Don't use! */
3136	uint32_t u20PageNoLow : 20;
3137	/** Physical Page number of the next level - High Part. Don't use! */
3138	uint32_t u20PageNoHigh : 20;
3139	/** MBZ bits */
3140	uint32_t u11Reserved : 11;
3141	/** No Execute flag. */
3142	uint32_t u1NoExecute : 1;
3143	} X86PDPEAMD64BITS;
3144	# ifndef VBOX_FOR_DTRACE_LIB
3145	AssertCompileSize(X86PDPEAMD64BITS, 8);
3146	# endif
3147	/** Pointer to a page directory pointer table entry. */
3148	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
3149	/** Pointer to a const page directory pointer table entry. */
3150	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
3151
3152	/**
3153	* Page directory pointer table entry for 1GB page. (AMD64 only)
3154	*/
3155	typedef struct X86PDPE1GB
3156	{
3157	/** 0: Flags whether(=1) or not the page is present. */
3158	uint32_t u1Present : 1;
3159	/** 1: Read(=0) / Write(=1) flag. */
3160	uint32_t u1Write : 1;
3161	/** 2: User(=1) / Supervisor (=0) flag. */
3162	uint32_t u1User : 1;
3163	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
3164	uint32_t u1WriteThru : 1;
3165	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
3166	uint32_t u1CacheDisable : 1;
3167	/** 5: Accessed flag.
3168	* Indicates that the page have been read or written to. */
3169	uint32_t u1Accessed : 1;
3170	/** 6: Dirty flag for 1GB pages. */
3171	uint32_t u1Dirty : 1;
3172	/** 7: Indicates 1GB page if set. */
3173	uint32_t u1Size : 1;
3174	/** 8: Global 1GB page. */
3175	uint32_t u1Global: 1;
3176	/** 9-11: Available for use to system software. */
3177	uint32_t u3Available : 3;
3178	/** 12: PAT bit for 1GB page. */
3179	uint32_t u1PAT : 1;
3180	/** 13-29: MBZ bits. */
3181	uint32_t u17Reserved : 17;
3182	/** 30-31: Physical page number - Low Part. Don't use! */
3183	uint32_t u2PageNoLow : 2;
3184	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
3185	uint32_t u20PageNoHigh : 20;
3186	/** 52-62: MBZ bits */
3187	uint32_t u11Reserved : 11;
3188	/** 63: No Execute flag. */
3189	uint32_t u1NoExecute : 1;
3190	} X86PDPE1GB;
3191	# ifndef VBOX_FOR_DTRACE_LIB
3192	AssertCompileSize(X86PDPE1GB, 8);
3193	# endif
3194	/** Pointer to a page directory pointer table entry for a 1GB page. */
3195	typedef X86PDPE1GB *PX86PDPE1GB;
3196	/** Pointer to a const page directory pointer table entry for a 1GB page. */
3197	typedef const X86PDPE1GB *PCX86PDPE1GB;
3198
3199	/**
3200	* Page directory pointer table entry.
3201	*/
3202	typedef union X86PDPE
3203	{
3204	/** Unsigned integer view. */
3205	X86PGPAEUINT u;
3206	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3207	/** Normal view. */
3208	X86PDPEBITS n;
3209	/** AMD64 view. */
3210	X86PDPEAMD64BITS lm;
3211	/** AMD64 big view. */
3212	X86PDPE1GB b;
3213	# endif
3214	/** 8 bit unsigned integer view. */
3215	uint8_t au8[8];
3216	/** 16 bit unsigned integer view. */
3217	uint16_t au16[4];
3218	/** 32 bit unsigned integer view. */
3219	uint32_t au32[2];
3220	} X86PDPE;
3221	# ifndef VBOX_FOR_DTRACE_LIB
3222	AssertCompileSize(X86PDPE, 8);
3223	# endif
3224	/** Pointer to a page directory pointer table entry. */
3225	typedef X86PDPE *PX86PDPE;
3226	/** Pointer to a const page directory pointer table entry. */
3227	typedef const X86PDPE *PCX86PDPE;
3228
3229
3230	/**
3231	* Page directory pointer table.
3232	*/
3233	typedef struct X86PDPT
3234	{
3235	/** PDE Array. */
3236	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3237	} X86PDPT;
3238	# ifndef VBOX_FOR_DTRACE_LIB
3239	AssertCompileSize(X86PDPT, 4096);
3240	# endif
3241	/** Pointer to a page directory pointer table. */
3242	typedef X86PDPT *PX86PDPT;
3243	/** Pointer to a const page directory pointer table. */
3244	typedef const X86PDPT *PCX86PDPT;
3245
3246	#endif /* !__ASSEMBLER__ */
3247
3248	/** The page shift to get the PDPT index. */
3249	#define X86_PDPT_SHIFT 30
3250	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3251	#define X86_PDPT_MASK_PAE 0x3
3252	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3253	#define X86_PDPT_MASK_AMD64 0x1ff
3254
3255	/** @} */
3256
3257
3258	/** @name Page Map Level-4 Entry (Long Mode PAE)
3259	* @{
3260	*/
3261	/** Bit 0 - P - Present bit. */
3262	#define X86_PML4E_P RT_BIT_32(0)
3263	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3264	#define X86_PML4E_RW RT_BIT_32(1)
3265	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3266	#define X86_PML4E_US RT_BIT_32(2)
3267	/** Bit 3 - PWT - Page level write thru bit. */
3268	#define X86_PML4E_PWT RT_BIT_32(3)
3269	/** Bit 4 - PCD - Page level cache disable bit. */
3270	#define X86_PML4E_PCD RT_BIT_32(4)
3271	/** Bit 5 - A - Access bit. */
3272	#define X86_PML4E_A RT_BIT_32(5)
3273	/** Bits 9-11 - - Available for use to system software. */
3274	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3275	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3276	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3277	/** Bits 8, 7 - - MBZ bits when NX is active. */
3278	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3279	/** Bits 63, 7 - - MBZ bits when no NX. */
3280	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3281	/** Bits 63 - NX - PAE - No execution flag. */
3282	#define X86_PML4E_NX RT_BIT_64(63)
3283
3284	#ifndef __ASSEMBLER__
3285
3286	/**
3287	* Page Map Level-4 Entry
3288	*/
3289	typedef struct X86PML4EBITS
3290	{
3291	/** Flags whether(=1) or not the page is present. */
3292	uint32_t u1Present : 1;
3293	/** Read(=0) / Write(=1) flag. */
3294	uint32_t u1Write : 1;
3295	/** User(=1) / Supervisor (=0) flag. */
3296	uint32_t u1User : 1;
3297	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3298	uint32_t u1WriteThru : 1;
3299	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3300	uint32_t u1CacheDisable : 1;
3301	/** Accessed flag.
3302	* Indicates that the page have been read or written to. */
3303	uint32_t u1Accessed : 1;
3304	/** Chunk of reserved bits. */
3305	uint32_t u3Reserved : 3;
3306	/** Available for use to system software. */
3307	uint32_t u3Available : 3;
3308	/** Physical Page number of the next level - Low Part. Don't use! */
3309	uint32_t u20PageNoLow : 20;
3310	/** Physical Page number of the next level - High Part. Don't use! */
3311	uint32_t u20PageNoHigh : 20;
3312	/** MBZ bits */
3313	uint32_t u11Reserved : 11;
3314	/** No Execute flag. */
3315	uint32_t u1NoExecute : 1;
3316	} X86PML4EBITS;
3317	# ifndef VBOX_FOR_DTRACE_LIB
3318	AssertCompileSize(X86PML4EBITS, 8);
3319	# endif
3320	/** Pointer to a page map level-4 entry. */
3321	typedef X86PML4EBITS *PX86PML4EBITS;
3322	/** Pointer to a const page map level-4 entry. */
3323	typedef const X86PML4EBITS *PCX86PML4EBITS;
3324
3325	/**
3326	* Page Map Level-4 Entry.
3327	*/
3328	typedef union X86PML4E
3329	{
3330	/** Unsigned integer view. */
3331	X86PGPAEUINT u;
3332	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3333	/** Normal view. */
3334	X86PML4EBITS n;
3335	# endif
3336	/** 8 bit unsigned integer view. */
3337	uint8_t au8[8];
3338	/** 16 bit unsigned integer view. */
3339	uint16_t au16[4];
3340	/** 32 bit unsigned integer view. */
3341	uint32_t au32[2];
3342	} X86PML4E;
3343	# ifndef VBOX_FOR_DTRACE_LIB
3344	AssertCompileSize(X86PML4E, 8);
3345	# endif
3346	/** Pointer to a page map level-4 entry. */
3347	typedef X86PML4E *PX86PML4E;
3348	/** Pointer to a const page map level-4 entry. */
3349	typedef const X86PML4E *PCX86PML4E;
3350
3351
3352	/**
3353	* Page Map Level-4.
3354	*/
3355	typedef struct X86PML4
3356	{
3357	/** PDE Array. */
3358	X86PML4E a[X86_PG_PAE_ENTRIES];
3359	} X86PML4;
3360	# ifndef VBOX_FOR_DTRACE_LIB
3361	AssertCompileSize(X86PML4, 4096);
3362	# endif
3363	/** Pointer to a page map level-4. */
3364	typedef X86PML4 *PX86PML4;
3365	/** Pointer to a const page map level-4. */
3366	typedef const X86PML4 *PCX86PML4;
3367
3368	#endif /* !__ASSEMBLER__ */
3369
3370	/** The page shift to get the PML4 index. */
3371	#define X86_PML4_SHIFT 39
3372	/** The PML4 index mask (apply to a shifted page address). */
3373	#define X86_PML4_MASK 0x1ff
3374
3375	/** @} */
3376
3377	/** @} */
3378
3379	/**
3380	* Intel PCID invalidation types.
3381	*/
3382	/** Individual address invalidation. */
3383	#define X86_INVPCID_TYPE_INDV_ADDR 0
3384	/** Single-context invalidation. */
3385	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3386	/** All-context including globals invalidation. */
3387	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3388	/** All-context excluding globals invalidation. */
3389	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3390	/** The maximum valid invalidation type value. */
3391	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3392
3393
3394	/** @name Special FPU integer values.
3395	* @{ */
3396	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3397	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3398	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3399	/** @} */
3400
3401	#ifndef __ASSEMBLER__
3402
3403	/**
3404	* 32-bit protected mode FSTENV image.
3405	*/
3406	typedef struct X86FSTENV32P
3407	{
3408	uint16_t FCW; /*< 0x00 /
3409	uint16_t padding1; /*< 0x02 /
3410	uint16_t FSW; /*< 0x04 /
3411	uint16_t padding2; /*< 0x06 /
3412	uint16_t FTW; /*< 0x08 /
3413	uint16_t padding3; /*< 0x0a /
3414	uint32_t FPUIP; /*< 0x0c /
3415	uint16_t FPUCS; /*< 0x10 /
3416	uint16_t FOP; /*< 0x12 /
3417	uint32_t FPUDP; /*< 0x14 /
3418	uint16_t FPUDS; /*< 0x18 /
3419	uint16_t padding4; /*< 0x1a /
3420	} X86FSTENV32P;
3421	# ifndef VBOX_FOR_DTRACE_LIB
3422	AssertCompileSize(X86FSTENV32P, 0x1c);
3423	# endif
3424	/** Pointer to a 32-bit protected mode FSTENV image. */
3425	typedef X86FSTENV32P *PX86FSTENV32P;
3426	/** Pointer to a const 32-bit protected mode FSTENV image. */
3427	typedef X86FSTENV32P const *PCX86FSTENV32P;
3428
3429
3430	/**
3431	* 80-bit MMX/FPU register type.
3432	*/
3433	typedef struct X86FPUMMX
3434	{
3435	uint8_t reg[10];
3436	} X86FPUMMX;
3437	# ifndef VBOX_FOR_DTRACE_LIB
3438	AssertCompileSize(X86FPUMMX, 10);
3439	# endif
3440	/** Pointer to a 80-bit MMX/FPU register type. */
3441	typedef X86FPUMMX *PX86FPUMMX;
3442	/** Pointer to a const 80-bit MMX/FPU register type. */
3443	typedef const X86FPUMMX *PCX86FPUMMX;
3444
3445	/** FPU (x87) register. */
3446	typedef union X86FPUREG
3447	{
3448	/** MMX view. */
3449	uint64_t mmx;
3450	/** FPU view - todo. */
3451	X86FPUMMX fpu;
3452	/** Extended precision floating point view. */
3453	RTFLOAT80U r80;
3454	/** Extended precision floating point view v2 */
3455	RTFLOAT80U2 r80Ex;
3456	/** 8-bit view. */
3457	uint8_t au8[16];
3458	/** 16-bit view. */
3459	uint16_t au16[8];
3460	/** 32-bit view. */
3461	uint32_t au32[4];
3462	/** 64-bit view. */
3463	uint64_t au64[2];
3464	/** 128-bit view. (yeah, very helpful) */
3465	uint128_t au128[1];
3466	} X86FPUREG;
3467	# ifndef VBOX_FOR_DTRACE_LIB
3468	AssertCompileSize(X86FPUREG, 16);
3469	# endif
3470	/** Pointer to a FPU register. */
3471	typedef X86FPUREG *PX86FPUREG;
3472	/** Pointer to a const FPU register. */
3473	typedef X86FPUREG const *PCX86FPUREG;
3474
3475	/** FPU (x87) register - v2 with correct size. */
3476	# pragma pack(1)
3477	typedef union X86FPUREG2
3478	{
3479	/** MMX view. */
3480	uint64_t mmx;
3481	/** FPU view - todo. */
3482	X86FPUMMX fpu;
3483	/** Extended precision floating point view. */
3484	RTFLOAT80U r80;
3485	/** 8-bit view. */
3486	uint8_t au8[10];
3487	/** 16-bit view. */
3488	uint16_t au16[5];
3489	/** 32-bit view. */
3490	uint32_t au32[2];
3491	/** 64-bit view. */
3492	uint64_t au64[1];
3493	} X86FPUREG2;
3494	# pragma pack()
3495	# ifndef VBOX_FOR_DTRACE_LIB
3496	AssertCompileSize(X86FPUREG2, 10);
3497	# endif
3498	/** Pointer to a FPU register - v2. */
3499	typedef X86FPUREG2 *PX86FPUREG2;
3500	/** Pointer to a const FPU register - v2. */
3501	typedef X86FPUREG2 const *PCX86FPUREG2;
3502
3503	/**
3504	* XMM register union.
3505	*/
3506	typedef union X86XMMREG
3507	{
3508	/** XMM Register view. */
3509	uint128_t xmm;
3510	/** 8-bit view. */
3511	uint8_t au8[16];
3512	/** 16-bit view. */
3513	uint16_t au16[8];
3514	/** 32-bit view. */
3515	uint32_t au32[4];
3516	/** 64-bit view. */
3517	uint64_t au64[2];
3518	/** Signed 8-bit view. */
3519	int8_t ai8[16];
3520	/** Signed 16-bit view. */
3521	int16_t ai16[8];
3522	/** Signed 32-bit view. */
3523	int32_t ai32[4];
3524	/** Signed 64-bit view. */
3525	int64_t ai64[2];
3526	/** 128-bit view. (yeah, very helpful) */
3527	uint128_t au128[1];
3528	/** Single precision floating point view. */
3529	RTFLOAT32U ar32[4];
3530	/** Double precision floating point view. */
3531	RTFLOAT64U ar64[2];
3532	# ifndef VBOX_FOR_DTRACE_LIB
3533	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3534	RTUINT128U uXmm;
3535	# endif
3536	} X86XMMREG;
3537	# ifndef VBOX_FOR_DTRACE_LIB
3538	AssertCompileSize(X86XMMREG, 16);
3539	# endif
3540	/** Pointer to an XMM register state. */
3541	typedef X86XMMREG *PX86XMMREG;
3542	/** Pointer to a const XMM register state. */
3543	typedef X86XMMREG const *PCX86XMMREG;
3544
3545	/**
3546	* YMM register union.
3547	*/
3548	typedef union X86YMMREG
3549	{
3550	/** YMM register view. */
3551	RTUINT256U ymm;
3552	/** 8-bit view. */
3553	uint8_t au8[32];
3554	/** 16-bit view. */
3555	uint16_t au16[16];
3556	/** 32-bit view. */
3557	uint32_t au32[8];
3558	/** 64-bit view. */
3559	uint64_t au64[4];
3560	/** Signed 8-bit view. */
3561	int8_t ai8[32];
3562	/** Signed 16-bit view. */
3563	int16_t ai16[16];
3564	/** Signed 32-bit view. */
3565	int32_t ai32[8];
3566	/** Signed 64-bit view. */
3567	int64_t ai64[4];
3568	/** 128-bit view. (yeah, very helpful) */
3569	uint128_t au128[2];
3570	/** Single precision floating point view. */
3571	RTFLOAT32U ar32[8];
3572	/** Double precision floating point view. */
3573	RTFLOAT64U ar64[4];
3574	/** XMM sub register view. */
3575	X86XMMREG aXmm[2];
3576	} X86YMMREG;
3577	# ifndef VBOX_FOR_DTRACE_LIB
3578	AssertCompileSize(X86YMMREG, 32);
3579	# endif
3580	/** Pointer to an YMM register state. */
3581	typedef X86YMMREG *PX86YMMREG;
3582	/** Pointer to a const YMM register state. */
3583	typedef X86YMMREG const *PCX86YMMREG;
3584
3585	/**
3586	* ZMM register union.
3587	*/
3588	typedef union X86ZMMREG
3589	{
3590	/** 8-bit view. */
3591	uint8_t au8[64];
3592	/** 16-bit view. */
3593	uint16_t au16[32];
3594	/** 32-bit view. */
3595	uint32_t au32[16];
3596	/** 64-bit view. */
3597	uint64_t au64[8];
3598	/** Signed 8-bit view. */
3599	int8_t ai8[64];
3600	/** Signed 16-bit view. */
3601	int16_t ai16[32];
3602	/** Signed 32-bit view. */
3603	int32_t ai32[16];
3604	/** Signed 64-bit view. */
3605	int64_t ai64[8];
3606	/** 128-bit view. (yeah, very helpful) */
3607	uint128_t au128[4];
3608	/** Single precision floating point view. */
3609	RTFLOAT32U ar32[16];
3610	/** Double precision floating point view. */
3611	RTFLOAT64U ar64[8];
3612	/** XMM sub register view. */
3613	X86XMMREG aXmm[4];
3614	/** YMM sub register view. */
3615	X86YMMREG aYmm[2];
3616	} X86ZMMREG;
3617	# ifndef VBOX_FOR_DTRACE_LIB
3618	AssertCompileSize(X86ZMMREG, 64);
3619	# endif
3620	/** Pointer to an ZMM register state. */
3621	typedef X86ZMMREG *PX86ZMMREG;
3622	/** Pointer to a const ZMM register state. */
3623	typedef X86ZMMREG const *PCX86ZMMREG;
3624
3625
3626	/**
3627	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3628	*/
3629	# pragma pack(1)
3630	typedef struct X86FPUSTATE
3631	{
3632	/** 0x00 - Control word. */
3633	uint16_t FCW;
3634	/** 0x02 - Alignment word */
3635	uint16_t Dummy1;
3636	/** 0x04 - Status word. */
3637	uint16_t FSW;
3638	/** 0x06 - Alignment word */
3639	uint16_t Dummy2;
3640	/** 0x08 - Tag word */
3641	uint16_t FTW;
3642	/** 0x0a - Alignment word */
3643	uint16_t Dummy3;
3644
3645	/** 0x0c - Instruction pointer. */
3646	uint32_t FPUIP;
3647	/** 0x10 - Code selector. */
3648	uint16_t CS;
3649	/** 0x12 - Opcode. */
3650	uint16_t FOP;
3651	/** 0x14 - Data pointer. */
3652	uint32_t FPUOO;
3653	/** 0x18 - FOS. */
3654	uint16_t FPUOS;
3655	/** 0x0a - Alignment word */
3656	uint16_t Dummy4;
3657	/** 0x1c - FPU register. */
3658	X86FPUREG2 regs[8];
3659	} X86FPUSTATE;
3660	# pragma pack()
3661	AssertCompileSize(X86FPUSTATE, 108);
3662	/** Pointer to a FPU state. */
3663	typedef X86FPUSTATE *PX86FPUSTATE;
3664	/** Pointer to a const FPU state. */
3665	typedef const X86FPUSTATE *PCX86FPUSTATE;
3666
3667	/**
3668	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3669	*/
3670	# pragma pack(1)
3671	typedef struct X86FXSTATE
3672	{
3673	/** 0x00 - Control word. */
3674	uint16_t FCW;
3675	/** 0x02 - Status word. */
3676	uint16_t FSW;
3677	/** 0x04 - Tag word. (The upper byte is always zero.) */
3678	uint16_t FTW;
3679	/** 0x06 - Opcode. */
3680	uint16_t FOP;
3681	/** 0x08 - Instruction pointer. */
3682	uint32_t FPUIP;
3683	/** 0x0c - Code selector. */
3684	uint16_t CS;
3685	uint16_t Rsrvd1;
3686	/** 0x10 - Data pointer. */
3687	uint32_t FPUDP;
3688	/** 0x14 - Data segment */
3689	uint16_t DS;
3690	/** 0x16 */
3691	uint16_t Rsrvd2;
3692	/** 0x18 */
3693	uint32_t MXCSR;
3694	/** 0x1c */
3695	uint32_t MXCSR_MASK;
3696	/** 0x20 - FPU registers. */
3697	X86FPUREG aRegs[8];
3698	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3699	X86XMMREG aXMM[16];
3700	/* - offset 416 - */
3701	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3702	/* - offset 464 - Software usable reserved bits. */
3703	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3704	} X86FXSTATE;
3705	# pragma pack()
3706	/** Pointer to a FPU Extended state. */
3707	typedef X86FXSTATE *PX86FXSTATE;
3708	/** Pointer to a const FPU Extended state. */
3709	typedef const X86FXSTATE *PCX86FXSTATE;
3710
3711	#endif /* !__ASSEMBLER__ */
3712
3713
3714	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3715	* magic. Don't forget to update x86.mac if you change this! */
3716	#define X86_OFF_FXSTATE_RSVD 0x1d0
3717	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3718	* forget to update x86.mac if you change this!
3719	* @todo r=bird: This has nothing what-so-ever to do here.... */
3720	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3721	#ifndef VBOX_FOR_DTRACE_LIB
3722	AssertCompileSize(X86FXSTATE, 512);
3723	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3724	#endif
3725
3726	/** @name FPU status word flags.
3727	* @{ */
3728	/** Exception Flag: Invalid operation. */
3729	#define X86_FSW_IE RT_BIT_32(0)
3730	#define X86_FSW_IE_BIT 0
3731	/** Exception Flag: Denormalized operand. */
3732	#define X86_FSW_DE RT_BIT_32(1)
3733	#define X86_FSW_DE_BIT 1
3734	/** Exception Flag: Zero divide. */
3735	#define X86_FSW_ZE RT_BIT_32(2)
3736	#define X86_FSW_ZE_BIT 2
3737	/** Exception Flag: Overflow. */
3738	#define X86_FSW_OE RT_BIT_32(3)
3739	#define X86_FSW_OE_BIT 3
3740	/** Exception Flag: Underflow. */
3741	#define X86_FSW_UE RT_BIT_32(4)
3742	#define X86_FSW_UE_BIT 4
3743	/** Exception Flag: Precision. */
3744	#define X86_FSW_PE RT_BIT_32(5)
3745	#define X86_FSW_PE_BIT 5
3746	/** Stack fault. */
3747	#define X86_FSW_SF RT_BIT_32(6)
3748	#define X86_FSW_SF_BIT 6
3749	/** Error summary status. */
3750	#define X86_FSW_ES RT_BIT_32(7)
3751	#define X86_FSW_ES_BIT 7
3752	/** Mask of exceptions flags, excluding the summary bit. */
3753	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3754	/** Mask of exceptions flags, including the summary bit. */
3755	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3756	/** Condition code 0. */
3757	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3758	#define X86_FSW_C0_BIT 8
3759	/** Condition code 1. */
3760	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3761	#define X86_FSW_C1_BIT 9
3762	/** Condition code 2. */
3763	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3764	#define X86_FSW_C2_BIT 10
3765	/** Top of the stack mask. */
3766	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3767	/** TOP shift value. */
3768	#define X86_FSW_TOP_SHIFT 11
3769	/** Mask for getting TOP value after shifting it right. */
3770	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3771	/** Get the TOP value. */
3772	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3773	/** Get the TOP value offsetted by a_iSt (0-7). */
3774	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3775	/** Condition code 3. */
3776	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3777	#define X86_FSW_C3_BIT 14
3778	/** Mask of exceptions flags, including the summary bit. */
3779	#define X86_FSW_C_MASK UINT16_C(0x4700)
3780	/** FPU busy. */
3781	#define X86_FSW_B RT_BIT_32(15)
3782	/** For use with FPREM and FPREM1. */
3783	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3784	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3785	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3786	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3787	/** For use with FPREM and FPREM1. */
3788	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3789	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3790	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3791	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3792	/** @} */
3793
3794
3795	/** @name FPU control word flags.
3796	* @{ */
3797	/** Exception Mask: Invalid operation. */
3798	#define X86_FCW_IM RT_BIT_32(0)
3799	#define X86_FCW_IM_BIT 0
3800	/** Exception Mask: Denormalized operand. */
3801	#define X86_FCW_DM RT_BIT_32(1)
3802	#define X86_FCW_DM_BIT 1
3803	/** Exception Mask: Zero divide. */
3804	#define X86_FCW_ZM RT_BIT_32(2)
3805	#define X86_FCW_ZM_BIT 2
3806	/** Exception Mask: Overflow. */
3807	#define X86_FCW_OM RT_BIT_32(3)
3808	#define X86_FCW_OM_BIT 3
3809	/** Exception Mask: Underflow. */
3810	#define X86_FCW_UM RT_BIT_32(4)
3811	#define X86_FCW_UM_BIT 4
3812	/** Exception Mask: Precision. */
3813	#define X86_FCW_PM RT_BIT_32(5)
3814	#define X86_FCW_PM_BIT 5
3815	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3816	* @remarks This includes reserved bit 6. */
3817	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3818	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3819	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3820	/** Precision control mask. */
3821	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3822	/** Precision control shift. */
3823	#define X86_FCW_PC_SHIFT 8
3824	/** Precision control: 24-bit. */
3825	#define X86_FCW_PC_24 UINT16_C(0x0000)
3826	/** Precision control: Reserved. */
3827	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3828	/** Precision control: 53-bit. */
3829	#define X86_FCW_PC_53 UINT16_C(0x0200)
3830	/** Precision control: 64-bit. */
3831	#define X86_FCW_PC_64 UINT16_C(0x0300)
3832	/** Rounding control mask. */
3833	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3834	/** Rounding control shift. */
3835	#define X86_FCW_RC_SHIFT 10
3836	/** Rounding control: To nearest. */
3837	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3838	/** Rounding control: Down. */
3839	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3840	/** Rounding control: Up. */
3841	#define X86_FCW_RC_UP UINT16_C(0x0800)
3842	/** Rounding control: Towards zero. */
3843	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3844	/** Infinity control mask - obsolete, 8087 & 287 only. */
3845	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3846	/** Infinity control: Affine - positive infinity is distictly different from
3847	* negative infinity.
3848	* @note 8087, 287 only */
3849	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3850	/** Infinity control: Projective - positive and negative infinity are the
3851	* same (sign ignored).
3852	* @note 8087, 287 only */
3853	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3854	/** Bits which should be zero, apparently. */
3855	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3856	/** @} */
3857
3858	/** @name SSE MXCSR
3859	* @{ */
3860	/** Exception Flag: Invalid operation. */
3861	#define X86_MXCSR_IE RT_BIT_32(0)
3862	#define X86_MXCSR_IE_BIT 0
3863	/** Exception Flag: Denormalized operand. */
3864	#define X86_MXCSR_DE RT_BIT_32(1)
3865	#define X86_MXCSR_DE_BIT 1
3866	/** Exception Flag: Zero divide. */
3867	#define X86_MXCSR_ZE RT_BIT_32(2)
3868	#define X86_MXCSR_ZE_BIT 2
3869	/** Exception Flag: Overflow. */
3870	#define X86_MXCSR_OE RT_BIT_32(3)
3871	#define X86_MXCSR_OE_BIT 3
3872	/** Exception Flag: Underflow. */
3873	#define X86_MXCSR_UE RT_BIT_32(4)
3874	#define X86_MXCSR_UE_BIT 4
3875	/** Exception Flag: Precision. */
3876	#define X86_MXCSR_PE RT_BIT_32(5)
3877	#define X86_MXCSR_PE_BIT 5
3878	/** Exception Flags: mask */
3879	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3880
3881	/** Denormals are zero. */
3882	#define X86_MXCSR_DAZ RT_BIT_32(6)
3883	#define X86_MXCSR_DAZ_BIT 6
3884
3885	/** Exception Mask: Invalid operation. */
3886	#define X86_MXCSR_IM RT_BIT_32(7)
3887	#define X86_MXCSR_IM_BIT 7
3888	/** Exception Mask: Denormalized operand. */
3889	#define X86_MXCSR_DM RT_BIT_32(8)
3890	#define X86_MXCSR_DM_BIT 8
3891	/** Exception Mask: Zero divide. */
3892	#define X86_MXCSR_ZM RT_BIT_32(9)
3893	#define X86_MXCSR_ZM_BIT 9
3894	/** Exception Mask: Overflow. */
3895	#define X86_MXCSR_OM RT_BIT_32(10)
3896	#define X86_MXCSR_OM_BIT 10
3897	/** Exception Mask: Underflow. */
3898	#define X86_MXCSR_UM RT_BIT_32(11)
3899	#define X86_MXCSR_UM_BIT 11
3900	/** Exception Mask: Precision. */
3901	#define X86_MXCSR_PM RT_BIT_32(12)
3902	#define X86_MXCSR_PM_BIT 12
3903	/** Exception Mask: mask. */
3904	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3905	/** Exception Mask: shift. */
3906	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3907
3908	/** Rounding control mask. */
3909	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3910	/** Rounding control shift. */
3911	#define X86_MXCSR_RC_SHIFT 13
3912	/** Rounding control: To nearest. */
3913	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3914	/** Rounding control: Down. */
3915	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3916	/** Rounding control: Up. */
3917	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3918	/** Rounding control: Towards zero. */
3919	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3920
3921	/** Flush-to-zero for masked underflow. */
3922	#define X86_MXCSR_FZ RT_BIT_32(15)
3923	#define X86_MXCSR_FZ_BIT 15
3924
3925	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3926	#define X86_MXCSR_MM RT_BIT_32(17)
3927	#define X86_MXCSR_MM_BIT 17
3928	/** Bits which should be zero, apparently. */
3929	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3930	/** @} */
3931
3932	#ifndef __ASSEMBLER__
3933
3934	/**
3935	* XSAVE header.
3936	*/
3937	typedef struct X86XSAVEHDR
3938	{
3939	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3940	uint64_t bmXState;
3941	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3942	uint64_t bmXComp;
3943	/** Reserved for furture extensions, probably MBZ. */
3944	uint64_t au64Reserved[6];
3945	} X86XSAVEHDR;
3946	# ifndef VBOX_FOR_DTRACE_LIB
3947	AssertCompileSize(X86XSAVEHDR, 64);
3948	# endif
3949	/** Pointer to an XSAVE header. */
3950	typedef X86XSAVEHDR *PX86XSAVEHDR;
3951	/** Pointer to a const XSAVE header. */
3952	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3953
3954
3955	/**
3956	* The high 128-bit YMM register state (XSAVE_C_YMM).
3957	* (The lower 128-bits being in X86FXSTATE.)
3958	*/
3959	typedef struct X86XSAVEYMMHI
3960	{
3961	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3962	X86XMMREG aYmmHi[16];
3963	} X86XSAVEYMMHI;
3964	# ifndef VBOX_FOR_DTRACE_LIB
3965	AssertCompileSize(X86XSAVEYMMHI, 256);
3966	# endif
3967	/** Pointer to a high 128-bit YMM register state. */
3968	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3969	/** Pointer to a const high 128-bit YMM register state. */
3970	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3971
3972	/**
3973	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3974	*/
3975	typedef struct X86XSAVEBNDREGS
3976	{
3977	/** Array of registers (BND0...BND3). */
3978	struct
3979	{
3980	/** Lower bound. */
3981	uint64_t uLowerBound;
3982	/** Upper bound. */
3983	uint64_t uUpperBound;
3984	} aRegs[4];
3985	} X86XSAVEBNDREGS;
3986	# ifndef VBOX_FOR_DTRACE_LIB
3987	AssertCompileSize(X86XSAVEBNDREGS, 64);
3988	# endif
3989	/** Pointer to a MPX bound register state. */
3990	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3991	/** Pointer to a const MPX bound register state. */
3992	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3993
3994	/**
3995	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3996	*/
3997	typedef struct X86XSAVEBNDCFG
3998	{
3999	uint64_t fConfig;
4000	uint64_t fStatus;
4001	} X86XSAVEBNDCFG;
4002	# ifndef VBOX_FOR_DTRACE_LIB
4003	AssertCompileSize(X86XSAVEBNDCFG, 16);
4004	# endif
4005	/** Pointer to a MPX bound config and status register state. */
4006	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
4007	/** Pointer to a const MPX bound config and status register state. */
4008	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
4009
4010	/**
4011	* AVX-512 opmask state (XSAVE_C_OPMASK).
4012	*/
4013	typedef struct X86XSAVEOPMASK
4014	{
4015	/** The K0..K7 values. */
4016	uint64_t aKRegs[8];
4017	} X86XSAVEOPMASK;
4018	# ifndef VBOX_FOR_DTRACE_LIB
4019	AssertCompileSize(X86XSAVEOPMASK, 64);
4020	# endif
4021	/** Pointer to a AVX-512 opmask state. */
4022	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
4023	/** Pointer to a const AVX-512 opmask state. */
4024	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
4025
4026	/**
4027	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
4028	*/
4029	typedef struct X86XSAVEZMMHI256
4030	{
4031	/** Upper 256-bits of ZMM0-15. */
4032	X86YMMREG aHi256Regs[16];
4033	} X86XSAVEZMMHI256;
4034	# ifndef VBOX_FOR_DTRACE_LIB
4035	AssertCompileSize(X86XSAVEZMMHI256, 512);
4036	# endif
4037	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
4038	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
4039	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
4040	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
4041
4042	/**
4043	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
4044	*/
4045	typedef struct X86XSAVEZMM16HI
4046	{
4047	/** ZMM16 thru ZMM31. */
4048	X86ZMMREG aRegs[16];
4049	} X86XSAVEZMM16HI;
4050	# ifndef VBOX_FOR_DTRACE_LIB
4051	AssertCompileSize(X86XSAVEZMM16HI, 1024);
4052	# endif
4053	/** Pointer to a state comprising ZMM16-32. */
4054	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
4055	/** Pointer to a const state comprising ZMM16-32. */
4056	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
4057
4058	/**
4059	* AMD Light weight profiling state (XSAVE_C_LWP).
4060	*
4061	* We probably won't play with this as AMD seems to be dropping from their "zen"
4062	* processor micro architecture.
4063	*/
4064	typedef struct X86XSAVELWP
4065	{
4066	/** Details when needed. */
4067	uint64_t auLater[128/8];
4068	} X86XSAVELWP;
4069	# ifndef VBOX_FOR_DTRACE_LIB
4070	AssertCompileSize(X86XSAVELWP, 128);
4071	# endif
4072
4073
4074	/**
4075	* x86 FPU/SSE/AVX/XXXX state.
4076	*
4077	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
4078	* changes to this structure.
4079	*/
4080	typedef struct X86XSAVEAREA
4081	{
4082	/** The x87 and SSE region (or legacy region if you like). */
4083	X86FXSTATE x87;
4084	/** The XSAVE header. */
4085	X86XSAVEHDR Hdr;
4086	/** Beyond the header, there isn't really a fixed layout, but we can
4087	generally assume the YMM (AVX) register extensions are present and
4088	follows immediately. */
4089	union
4090	{
4091	/** The high 128-bit AVX registers for easy access by IEM.
4092	* @note This ASSUMES they will always be here... */
4093	X86XSAVEYMMHI YmmHi;
4094
4095	/** This is a typical layout on intel CPUs (good for debuggers). */
4096	struct
4097	{
4098	X86XSAVEYMMHI YmmHi;
4099	X86XSAVEBNDREGS BndRegs;
4100	X86XSAVEBNDCFG BndCfg;
4101	uint8_t abFudgeToMatchDocs[0xB0];
4102	X86XSAVEOPMASK Opmask;
4103	X86XSAVEZMMHI256 ZmmHi256;
4104	X86XSAVEZMM16HI Zmm16Hi;
4105	} Intel;
4106
4107	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
4108	struct
4109	{
4110	X86XSAVEYMMHI YmmHi;
4111	X86XSAVELWP Lwp;
4112	} AmdBd;
4113
4114	/** To enbling static deployments that have a reasonable chance of working for
4115	* the next 3-6 CPU generations without running short on space, we allocate a
4116	* lot of extra space here, making the structure a round 8KB in size. This
4117	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
4118	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
4119	uint8_t ab[8192 - 512 - 64];
4120	} u;
4121	} X86XSAVEAREA;
4122	# ifndef VBOX_FOR_DTRACE_LIB
4123	AssertCompileSize(X86XSAVEAREA, 8192);
4124	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
4125	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
4126	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
4127	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
4128	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
4129	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
4130	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
4131	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
4132	# endif
4133	/** Pointer to a XSAVE area. */
4134	typedef X86XSAVEAREA *PX86XSAVEAREA;
4135	/** Pointer to a const XSAVE area. */
4136	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
4137
4138	#endif /* __ASSEMBLER__ */
4139
4140
4141	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
4142	* @{ */
4143	/** Bit 0 - x87 - Legacy FPU state (bit number) */
4144	#define XSAVE_C_X87_BIT 0
4145	/** Bit 0 - x87 - Legacy FPU state. */
4146	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
4147	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
4148	#define XSAVE_C_SSE_BIT 1
4149	/** Bit 1 - SSE - 128-bit SSE state. */
4150	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
4151	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
4152	#define XSAVE_C_YMM_BIT 2
4153	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
4154	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
4155	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
4156	#define XSAVE_C_BNDREGS_BIT 3
4157	/** Bit 3 - BNDREGS - MPX bound register state. */
4158	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
4159	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
4160	#define XSAVE_C_BNDCSR_BIT 4
4161	/** Bit 4 - BNDCSR - MPX bound config and status state. */
4162	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
4163	/** Bit 5 - Opmask - opmask state (bit number). */
4164	#define XSAVE_C_OPMASK_BIT 5
4165	/** Bit 5 - Opmask - opmask state. */
4166	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
4167	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
4168	#define XSAVE_C_ZMM_HI256_BIT 6
4169	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
4170	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
4171	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
4172	#define XSAVE_C_ZMM_16HI_BIT 7
4173	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
4174	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
4175	/** Bit 9 - PKRU - Protection-key state (bit number). */
4176	#define XSAVE_C_PKRU_BIT 9
4177	/** Bit 9 - PKRU - Protection-key state. */
4178	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
4179	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
4180	#define XSAVE_C_LWP_BIT 62
4181	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
4182	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
4183	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
4184	#define XSAVE_C_X_BIT 63
4185	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
4186	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
4187	/** @} */
4188
4189
4190
4191	/** @name Selector Descriptor
4192	* @{
4193	*/
4194
4195	#ifndef __ASSEMBLER__
4196	# ifndef VBOX_FOR_DTRACE_LIB
4197	/**
4198	* Descriptor attributes (as seen by VT-x).
4199	*/
4200	typedef struct X86DESCATTRBITS
4201	{
4202	/** 00 - Segment Type. */
4203	unsigned u4Type : 4;
4204	/** 04 - Descriptor Type. System(=0) or code/data selector */
4205	unsigned u1DescType : 1;
4206	/** 05 - Descriptor Privilege level. */
4207	unsigned u2Dpl : 2;
4208	/** 07 - Flags selector present(=1) or not. */
4209	unsigned u1Present : 1;
4210	/** 08 - Segment limit 16-19. */
4211	unsigned u4LimitHigh : 4;
4212	/** 0c - Available for system software. */
4213	unsigned u1Available : 1;
4214	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4215	unsigned u1Long : 1;
4216	/** 0e - This flags meaning depends on the segment type. Try make sense out
4217	* of the intel manual yourself. */
4218	unsigned u1DefBig : 1;
4219	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
4220	* clear byte. */
4221	unsigned u1Granularity : 1;
4222	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
4223	unsigned u1Unusable : 1;
4224	} X86DESCATTRBITS;
4225	# endif /* !VBOX_FOR_DTRACE_LIB */
4226	#endif /* !__ASSEMBLER__ */
4227
4228	/** @name X86DESCATTR masks
4229	* Fields X86DESCGENERIC::u4Type thru X86DESCGENERIC::u1Granularity (or
4230	* bits[55:40] if you like). The X86DESCATTR_UNUSABLE bit is an Intel addition.
4231	* @{ */
4232	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
4233	#define X86DESCATTR_DT UINT32_C(0x00000010) /*< Descriptor type: 0=system, 1=code/data /
4234	#define X86DESCATTR_DPL UINT32_C(0x00000060)
4235	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL bitfield. /
4236	#define X86DESCATTR_P UINT32_C(0x00000080)
4237	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4238	#define X86DESCATTR_AVL UINT32_C(0x00001000)
4239	#define X86DESCATTR_L UINT32_C(0x00002000)
4240	#define X86DESCATTR_D UINT32_C(0x00004000)
4241	#define X86DESCATTR_G UINT32_C(0x00008000)
4242	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4243	/** @} */
4244
4245
4246	#ifndef __ASSEMBLER__
4247	# pragma pack(1)
4248	typedef union X86DESCATTR
4249	{
4250	/** Unsigned integer view. */
4251	uint32_t u;
4252	# ifndef VBOX_FOR_DTRACE_LIB
4253	/** Normal view. */
4254	X86DESCATTRBITS n;
4255	# endif
4256	} X86DESCATTR;
4257	# pragma pack()
4258	/** Pointer to descriptor attributes. */
4259	typedef X86DESCATTR *PX86DESCATTR;
4260	/** Pointer to const descriptor attributes. */
4261	typedef const X86DESCATTR *PCX86DESCATTR;
4262	#endif /* !__ASSEMBLER__ */
4263
4264	#ifndef VBOX_FOR_DTRACE_LIB
4265
4266	#ifndef __ASSEMBLER__
4267	/**
4268	* Generic descriptor table entry
4269	*/
4270	# pragma pack(1)
4271	typedef struct X86DESCGENERIC
4272	{
4273	/** 00 - Limit - Low word. */
4274	unsigned u16LimitLow : 16;
4275	/** 10 - Base address - low word.
4276	* Don't try set this to 24 because MSC is doing stupid things then. */
4277	unsigned u16BaseLow : 16;
4278	/** 20 - Base address - first 8 bits of high word. */
4279	unsigned u8BaseHigh1 : 8;
4280	/** 28 - Segment Type. */
4281	unsigned u4Type : 4;
4282	/** 2c - Descriptor Type. System(=0) or code/data selector */
4283	unsigned u1DescType : 1;
4284	/** 2d - Descriptor Privilege level. */
4285	unsigned u2Dpl : 2;
4286	/** 2f - Flags selector present(=1) or not. */
4287	unsigned u1Present : 1;
4288	/** 30 - Segment limit 16-19. */
4289	unsigned u4LimitHigh : 4;
4290	/** 34 - Available for system software. */
4291	unsigned u1Available : 1;
4292	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4293	unsigned u1Long : 1;
4294	/** 36 - This flags meaning depends on the segment type. Try make sense out
4295	* of the intel manual yourself. */
4296	unsigned u1DefBig : 1;
4297	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4298	* clear byte. */
4299	unsigned u1Granularity : 1;
4300	/** 38 - Base address - highest 8 bits. */
4301	unsigned u8BaseHigh2 : 8;
4302	} X86DESCGENERIC;
4303	# pragma pack()
4304	/** Pointer to a generic descriptor entry. */
4305	typedef X86DESCGENERIC *PX86DESCGENERIC;
4306	/** Pointer to a const generic descriptor entry. */
4307	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4308	# endif /* !__ASSEMBLER__ */
4309
4310
4311	/** @name Bit offsets of X86DESCGENERIC members.
4312	* @{*/
4313	# define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4314	# define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4315	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4316	# define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4317	# define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4318	# define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4319	# define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4320	# define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4321	# define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4322	# define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4323	# define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4324	# define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4325	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4326	/** @} */
4327
4328
4329	/** @name LAR mask
4330	* @{ */
4331	# define X86LAR_F_TYPE UINT16_C( 0x0f00)
4332	# define X86LAR_F_DT UINT16_C( 0x1000)
4333	# define X86LAR_F_DPL UINT16_C( 0x6000)
4334	# define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4335	# define X86LAR_F_P UINT16_C( 0x8000)
4336	# define X86LAR_F_AVL UINT32_C(0x00100000)
4337	# define X86LAR_F_L UINT32_C(0x00200000)
4338	# define X86LAR_F_D UINT32_C(0x00400000)
4339	# define X86LAR_F_G UINT32_C(0x00800000)
4340	/** @} */
4341
4342
4343	# ifndef __ASSEMBLER__
4344	/**
4345	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4346	*/
4347	typedef struct X86DESCGATE
4348	{
4349	/** 00 - Target code segment offset - Low word.
4350	* Ignored if task-gate. */
4351	unsigned u16OffsetLow : 16;
4352	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4353	* TSS selector if task-gate. */
4354	unsigned u16Sel : 16;
4355	/** 20 - Number of parameters for a call-gate.
4356	* Ignored if interrupt-, trap- or task-gate. */
4357	unsigned u5ParmCount : 5;
4358	/** 25 - Reserved / ignored. */
4359	unsigned u3Reserved : 3;
4360	/** 28 - Segment Type. */
4361	unsigned u4Type : 4;
4362	/** 2c - Descriptor Type (0 = system). */
4363	unsigned u1DescType : 1;
4364	/** 2d - Descriptor Privilege level. */
4365	unsigned u2Dpl : 2;
4366	/** 2f - Flags selector present(=1) or not. */
4367	unsigned u1Present : 1;
4368	/** 30 - Target code segment offset - High word.
4369	* Ignored if task-gate. */
4370	unsigned u16OffsetHigh : 16;
4371	} X86DESCGATE;
4372	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4373	typedef X86DESCGATE *PX86DESCGATE;
4374	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4375	typedef const X86DESCGATE *PCX86DESCGATE;
4376	# endif /* !__ASSEMBLER__ */
4377
4378	#endif /* VBOX_FOR_DTRACE_LIB */
4379
4380	#ifndef __ASSEMBLER__
4381	/**
4382	* Descriptor table entry.
4383	*/
4384	# pragma pack(1)
4385	typedef union X86DESC
4386	{
4387	# ifndef VBOX_FOR_DTRACE_LIB
4388	/** Generic descriptor view. */
4389	X86DESCGENERIC Gen;
4390	/** Gate descriptor view. */
4391	X86DESCGATE Gate;
4392	# endif
4393	/** 8 bit unsigned integer view. */
4394	uint8_t au8[8];
4395	/** 16 bit unsigned integer view. */
4396	uint16_t au16[4];
4397	/** 32 bit unsigned integer view. */
4398	uint32_t au32[2];
4399	/** 64 bit unsigned integer view. */
4400	uint64_t au64[1];
4401	/** Unsigned integer view. */
4402	uint64_t u;
4403	} X86DESC;
4404	# ifndef VBOX_FOR_DTRACE_LIB
4405	AssertCompileSize(X86DESC, 8);
4406	# endif
4407	# pragma pack()
4408	/** Pointer to descriptor table entry. */
4409	typedef X86DESC *PX86DESC;
4410	/** Pointer to const descriptor table entry. */
4411	typedef const X86DESC *PCX86DESC;
4412	#endif /* !__ASSEMBLER__ */
4413
4414	/** @def X86DESC_BASE
4415	* Return the base address of a descriptor.
4416	*/
4417	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4418	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4419	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4420	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4421
4422	/** @def X86DESC_LIMIT
4423	* Return the limit of a descriptor.
4424	*/
4425	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4426	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4427	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4428
4429	/** @def X86DESC_LIMIT_G
4430	* Return the limit of a descriptor with the granularity bit taken into account.
4431	* @returns Selector limit (uint32_t).
4432	* @param a_pDesc Pointer to the descriptor.
4433	*/
4434	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4435	( (a_pDesc)->Gen.u1Granularity \
4436	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4437	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4438	)
4439
4440	/** @def X86DESC_GET_HID_ATTR
4441	* Get the descriptor attributes for the hidden register.
4442	*/
4443	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4444	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4445
4446	#ifndef __ASSEMBLER__
4447	# ifndef VBOX_FOR_DTRACE_LIB
4448
4449	/**
4450	* 64 bits generic descriptor table entry
4451	* Note: most of these bits have no meaning in long mode.
4452	*/
4453	# pragma pack(1)
4454	typedef struct X86DESC64GENERIC
4455	{
4456	/** Limit - Low word - IGNORED. */
4457	uint32_t u16LimitLow : 16;
4458	/** Base address - low word. - IGNORED
4459	* Don't try set this to 24 because MSC is doing stupid things then. */
4460	uint32_t u16BaseLow : 16;
4461	/** Base address - first 8 bits of high word. - IGNORED */
4462	uint32_t u8BaseHigh1 : 8;
4463	/** Segment Type. */
4464	uint32_t u4Type : 4;
4465	/** Descriptor Type. System(=0) or code/data selector */
4466	uint32_t u1DescType : 1;
4467	/** Descriptor Privilege level. */
4468	uint32_t u2Dpl : 2;
4469	/** Flags selector present(=1) or not. */
4470	uint32_t u1Present : 1;
4471	/** Segment limit 16-19. - IGNORED */
4472	uint32_t u4LimitHigh : 4;
4473	/** Available for system software. - IGNORED */
4474	uint32_t u1Available : 1;
4475	/** Long mode flag. */
4476	uint32_t u1Long : 1;
4477	/** This flags meaning depends on the segment type. Try make sense out
4478	* of the intel manual yourself. */
4479	uint32_t u1DefBig : 1;
4480	/** Granularity of the limit. If set 4KB granularity is used, if
4481	* clear byte. - IGNORED */
4482	uint32_t u1Granularity : 1;
4483	/** Base address - highest 8 bits. - IGNORED */
4484	uint32_t u8BaseHigh2 : 8;
4485	/** Base address - bits 63-32. */
4486	uint32_t u32BaseHigh3 : 32;
4487	uint32_t u8Reserved : 8;
4488	uint32_t u5Zeros : 5;
4489	uint32_t u19Reserved : 19;
4490	} X86DESC64GENERIC;
4491	# pragma pack()
4492	/** Pointer to a generic descriptor entry. */
4493	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4494	/** Pointer to a const generic descriptor entry. */
4495	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4496
4497	/**
4498	* System descriptor table entry (64 bits)
4499	*
4500	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4501	*/
4502	# pragma pack(1)
4503	typedef struct X86DESC64SYSTEM
4504	{
4505	/** Limit - Low word. */
4506	uint32_t u16LimitLow : 16;
4507	/** Base address - low word.
4508	* Don't try set this to 24 because MSC is doing stupid things then. */
4509	uint32_t u16BaseLow : 16;
4510	/** Base address - first 8 bits of high word. */
4511	uint32_t u8BaseHigh1 : 8;
4512	/** Segment Type. */
4513	uint32_t u4Type : 4;
4514	/** Descriptor Type. System(=0) or code/data selector */
4515	uint32_t u1DescType : 1;
4516	/** Descriptor Privilege level. */
4517	uint32_t u2Dpl : 2;
4518	/** Flags selector present(=1) or not. */
4519	uint32_t u1Present : 1;
4520	/** Segment limit 16-19. */
4521	uint32_t u4LimitHigh : 4;
4522	/** Available for system software. */
4523	uint32_t u1Available : 1;
4524	/** Reserved - 0. */
4525	uint32_t u1Reserved : 1;
4526	/** This flags meaning depends on the segment type. Try make sense out
4527	* of the intel manual yourself. */
4528	uint32_t u1DefBig : 1;
4529	/** Granularity of the limit. If set 4KB granularity is used, if
4530	* clear byte. */
4531	uint32_t u1Granularity : 1;
4532	/** Base address - bits 31-24. */
4533	uint32_t u8BaseHigh2 : 8;
4534	/** Base address - bits 63-32. */
4535	uint32_t u32BaseHigh3 : 32;
4536	uint32_t u8Reserved : 8;
4537	uint32_t u5Zeros : 5;
4538	uint32_t u19Reserved : 19;
4539	} X86DESC64SYSTEM;
4540	# pragma pack()
4541	/** Pointer to a system descriptor entry. */
4542	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4543	/** Pointer to a const system descriptor entry. */
4544	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4545
4546	/**
4547	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4548	*/
4549	typedef struct X86DESC64GATE
4550	{
4551	/** Target code segment offset - Low word. */
4552	uint32_t u16OffsetLow : 16;
4553	/** Target code segment selector. */
4554	uint32_t u16Sel : 16;
4555	/** Interrupt stack table for interrupt- and trap-gates.
4556	* Ignored by call-gates. */
4557	uint32_t u3IST : 3;
4558	/** Reserved / ignored. */
4559	uint32_t u5Reserved : 5;
4560	/** Segment Type. */
4561	uint32_t u4Type : 4;
4562	/** Descriptor Type (0 = system). */
4563	uint32_t u1DescType : 1;
4564	/** Descriptor Privilege level. */
4565	uint32_t u2Dpl : 2;
4566	/** Flags selector present(=1) or not. */
4567	uint32_t u1Present : 1;
4568	/** Target code segment offset - High word.
4569	* Ignored if task-gate. */
4570	uint32_t u16OffsetHigh : 16;
4571	/** Target code segment offset - Top dword.
4572	* Ignored if task-gate. */
4573	uint32_t u32OffsetTop : 32;
4574	/** Reserved / ignored / must be zero.
4575	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4576	uint32_t u32Reserved : 32;
4577	} X86DESC64GATE;
4578	AssertCompileSize(X86DESC64GATE, 16);
4579	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4580	typedef X86DESC64GATE *PX86DESC64GATE;
4581	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4582	typedef const X86DESC64GATE *PCX86DESC64GATE;
4583
4584	# endif /* VBOX_FOR_DTRACE_LIB */
4585
4586	/**
4587	* Descriptor table entry.
4588	*/
4589	# pragma pack(1)
4590	typedef union X86DESC64
4591	{
4592	# ifndef VBOX_FOR_DTRACE_LIB
4593	/** Generic descriptor view. */
4594	X86DESC64GENERIC Gen;
4595	/** System descriptor view. */
4596	X86DESC64SYSTEM System;
4597	/** Gate descriptor view. */
4598	X86DESC64GATE Gate;
4599	# endif
4600
4601	/** 8 bit unsigned integer view. */
4602	uint8_t au8[16];
4603	/** 16 bit unsigned integer view. */
4604	uint16_t au16[8];
4605	/** 32 bit unsigned integer view. */
4606	uint32_t au32[4];
4607	/** 64 bit unsigned integer view. */
4608	uint64_t au64[2];
4609	} X86DESC64;
4610	# ifndef VBOX_FOR_DTRACE_LIB
4611	AssertCompileSize(X86DESC64, 16);
4612	# endif
4613	# pragma pack()
4614	/** Pointer to descriptor table entry. */
4615	typedef X86DESC64 *PX86DESC64;
4616	/** Pointer to const descriptor table entry. */
4617	typedef const X86DESC64 *PCX86DESC64;
4618
4619	/** @def X86DESC64_BASE
4620	* Return the base of a 64-bit descriptor.
4621	*/
4622	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4623	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4624	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4625	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4626	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4627
4628
4629
4630	/** @name Host system descriptor table entry - Use with care!
4631	* @{ */
4632	/** Host system descriptor table entry. */
4633	#if HC_ARCH_BITS == 64
4634	typedef X86DESC64 X86DESCHC;
4635	#else
4636	typedef X86DESC X86DESCHC;
4637	#endif
4638	/** Pointer to a host system descriptor table entry. */
4639	#if HC_ARCH_BITS == 64
4640	typedef PX86DESC64 PX86DESCHC;
4641	#else
4642	typedef PX86DESC PX86DESCHC;
4643	#endif
4644	/** Pointer to a const host system descriptor table entry. */
4645	#if HC_ARCH_BITS == 64
4646	typedef PCX86DESC64 PCX86DESCHC;
4647	#else
4648	typedef PCX86DESC PCX86DESCHC;
4649	#endif
4650	/** @} */
4651
4652	#endif /* !__ASSEMBLER__ */
4653
4654
4655	/** @name Selector Descriptor Types.
4656	* @{
4657	*/
4658
4659	/** @name Non-System Selector Types.
4660	* @{ */
4661	/** Code(=set)/Data(=clear) bit. */
4662	#define X86_SEL_TYPE_CODE 8
4663	/** Memory(=set)/System(=clear) bit. */
4664	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4665	/** Accessed bit. */
4666	#define X86_SEL_TYPE_ACCESSED 1
4667	/** Expand down bit (for data selectors only). */
4668	#define X86_SEL_TYPE_DOWN 4
4669	/** Conforming bit (for code selectors only). */
4670	#define X86_SEL_TYPE_CONF 4
4671	/** Write bit (for data selectors only). */
4672	#define X86_SEL_TYPE_WRITE 2
4673	/** Read bit (for code selectors only). */
4674	#define X86_SEL_TYPE_READ 2
4675	/** The bit number of the code segment read bit (relative to u4Type). */
4676	#define X86_SEL_TYPE_READ_BIT 1
4677
4678	/** Read only selector type. */
4679	#define X86_SEL_TYPE_RO 0
4680	/** Accessed read only selector type. */
4681	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4682	/** Read write selector type. */
4683	#define X86_SEL_TYPE_RW 2
4684	/** Accessed read write selector type. */
4685	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4686	/** Expand down read only selector type. */
4687	#define X86_SEL_TYPE_RO_DOWN 4
4688	/** Accessed expand down read only selector type. */
4689	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4690	/** Expand down read write selector type. */
4691	#define X86_SEL_TYPE_RW_DOWN 6
4692	/** Accessed expand down read write selector type. */
4693	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4694	/** Execute only selector type. */
4695	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4696	/** Accessed execute only selector type. */
4697	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4698	/** Execute and read selector type. */
4699	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4700	/** Accessed execute and read selector type. */
4701	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4702	/** Conforming execute only selector type. */
4703	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4704	/** Accessed Conforming execute only selector type. */
4705	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4706	/** Conforming execute and write selector type. */
4707	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4708	/** Accessed Conforming execute and write selector type. */
4709	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4710	/** @} */
4711
4712
4713	/** @name System Selector Types.
4714	* @{ */
4715	/** The TSS busy bit mask. */
4716	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4717
4718	/** Undefined system selector type. */
4719	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4720	/** 286 TSS selector. */
4721	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4722	/** LDT selector. */
4723	#define X86_SEL_TYPE_SYS_LDT 2
4724	/** 286 TSS selector - Busy. */
4725	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4726	/** 286 Callgate selector. */
4727	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4728	/** Taskgate selector. */
4729	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4730	/** 286 Interrupt gate selector. */
4731	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4732	/** 286 Trapgate selector. */
4733	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4734	/** Undefined system selector. */
4735	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4736	/** 386 TSS selector. */
4737	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4738	/** Undefined system selector. */
4739	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4740	/** 386 TSS selector - Busy. */
4741	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4742	/** 386 Callgate selector. */
4743	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4744	/** Undefined system selector. */
4745	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4746	/** 386 Interruptgate selector. */
4747	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4748	/** 386 Trapgate selector. */
4749	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4750	/** @} */
4751
4752	/** @name AMD64 System Selector Types.
4753	* @{ */
4754	/** LDT selector. */
4755	#define AMD64_SEL_TYPE_SYS_LDT 2
4756	/** TSS selector - Busy. */
4757	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4758	/** TSS selector - Busy. */
4759	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4760	/** Callgate selector. */
4761	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4762	/** Interruptgate selector. */
4763	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4764	/** Trapgate selector. */
4765	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4766	/** @} */
4767
4768	/** @} */
4769
4770
4771	/** @name Descriptor Table Entry Flag Masks.
4772	* These are for the 2nd 32-bit word of a descriptor.
4773	* @{ */
4774	/** Bits 8-11 - TYPE - Descriptor type mask. */
4775	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4776	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4777	#define X86_DESC_S RT_BIT_32(12)
4778	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4779	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4780	/** Bit 15 - P - Present. */
4781	#define X86_DESC_P RT_BIT_32(15)
4782	/** Bit 20 - AVL - Available for system software. */
4783	#define X86_DESC_AVL RT_BIT_32(20)
4784	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4785	#define X86_DESC_DB RT_BIT_32(22)
4786	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4787	* used, if clear byte. */
4788	#define X86_DESC_G RT_BIT_32(23)
4789	/** @} */
4790
4791	/** @} */
4792
4793
4794	/** @name Task Segments.
4795	* @{
4796	*/
4797
4798	/**
4799	* The minimum TSS descriptor limit for 286 tasks.
4800	*/
4801	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4802
4803	/**
4804	* The minimum TSS descriptor segment limit for 386 tasks.
4805	*/
4806	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4807
4808	#ifndef __ASSEMBLER__
4809
4810	/**
4811	* 16-bit Task Segment (TSS).
4812	*/
4813	# pragma pack(1)
4814	typedef struct X86TSS16
4815	{
4816	/** Back link to previous task. (static) */
4817	RTSEL selPrev;
4818	/** Ring-0 stack pointer. (static) */
4819	uint16_t sp0;
4820	/** Ring-0 stack segment. (static) */
4821	RTSEL ss0;
4822	/** Ring-1 stack pointer. (static) */
4823	uint16_t sp1;
4824	/** Ring-1 stack segment. (static) */
4825	RTSEL ss1;
4826	/** Ring-2 stack pointer. (static) */
4827	uint16_t sp2;
4828	/** Ring-2 stack segment. (static) */
4829	RTSEL ss2;
4830	/** IP before task switch. */
4831	uint16_t ip;
4832	/** FLAGS before task switch. */
4833	uint16_t flags;
4834	/** AX before task switch. */
4835	uint16_t ax;
4836	/** CX before task switch. */
4837	uint16_t cx;
4838	/** DX before task switch. */
4839	uint16_t dx;
4840	/** BX before task switch. */
4841	uint16_t bx;
4842	/** SP before task switch. */
4843	uint16_t sp;
4844	/** BP before task switch. */
4845	uint16_t bp;
4846	/** SI before task switch. */
4847	uint16_t si;
4848	/** DI before task switch. */
4849	uint16_t di;
4850	/** ES before task switch. */
4851	RTSEL es;
4852	/** CS before task switch. */
4853	RTSEL cs;
4854	/** SS before task switch. */
4855	RTSEL ss;
4856	/** DS before task switch. */
4857	RTSEL ds;
4858	/** LDTR before task switch. */
4859	RTSEL selLdt;
4860	} X86TSS16;
4861	# ifndef VBOX_FOR_DTRACE_LIB
4862	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4863	# endif
4864	# pragma pack()
4865	/** Pointer to a 16-bit task segment. */
4866	typedef X86TSS16 *PX86TSS16;
4867	/** Pointer to a const 16-bit task segment. */
4868	typedef const X86TSS16 *PCX86TSS16;
4869
4870
4871	/**
4872	* 32-bit Task Segment (TSS).
4873	*/
4874	# pragma pack(1)
4875	typedef struct X86TSS32
4876	{
4877	/** Back link to previous task. (static) */
4878	RTSEL selPrev;
4879	uint16_t padding1;
4880	/** Ring-0 stack pointer. (static) */
4881	uint32_t esp0;
4882	/** Ring-0 stack segment. (static) */
4883	RTSEL ss0;
4884	uint16_t padding_ss0;
4885	/** Ring-1 stack pointer. (static) */
4886	uint32_t esp1;
4887	/** Ring-1 stack segment. (static) */
4888	RTSEL ss1;
4889	uint16_t padding_ss1;
4890	/** Ring-2 stack pointer. (static) */
4891	uint32_t esp2;
4892	/** Ring-2 stack segment. (static) */
4893	RTSEL ss2;
4894	uint16_t padding_ss2;
4895	/** Page directory for the task. (static) */
4896	uint32_t cr3;
4897	/** EIP before task switch. */
4898	uint32_t eip;
4899	/** EFLAGS before task switch. */
4900	uint32_t eflags;
4901	/** EAX before task switch. */
4902	uint32_t eax;
4903	/** ECX before task switch. */
4904	uint32_t ecx;
4905	/** EDX before task switch. */
4906	uint32_t edx;
4907	/** EBX before task switch. */
4908	uint32_t ebx;
4909	/** ESP before task switch. */
4910	uint32_t esp;
4911	/** EBP before task switch. */
4912	uint32_t ebp;
4913	/** ESI before task switch. */
4914	uint32_t esi;
4915	/** EDI before task switch. */
4916	uint32_t edi;
4917	/** ES before task switch. */
4918	RTSEL es;
4919	uint16_t padding_es;
4920	/** CS before task switch. */
4921	RTSEL cs;
4922	uint16_t padding_cs;
4923	/** SS before task switch. */
4924	RTSEL ss;
4925	uint16_t padding_ss;
4926	/** DS before task switch. */
4927	RTSEL ds;
4928	uint16_t padding_ds;
4929	/** FS before task switch. */
4930	RTSEL fs;
4931	uint16_t padding_fs;
4932	/** GS before task switch. */
4933	RTSEL gs;
4934	uint16_t padding_gs;
4935	/** LDTR before task switch. */
4936	RTSEL selLdt;
4937	uint16_t padding_ldt;
4938	/** Debug trap flag */
4939	uint16_t fDebugTrap;
4940	/** Offset relative to the TSS of the start of the I/O Bitmap
4941	* and the end of the interrupt redirection bitmap. */
4942	uint16_t offIoBitmap;
4943	} X86TSS32;
4944	# pragma pack()
4945	/** Pointer to task segment. */
4946	typedef X86TSS32 *PX86TSS32;
4947	/** Pointer to const task segment. */
4948	typedef const X86TSS32 *PCX86TSS32;
4949	# ifndef VBOX_FOR_DTRACE_LIB
4950	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4951	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4952	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4953	# endif
4954
4955	/**
4956	* 64-bit Task segment.
4957	*/
4958	# pragma pack(1)
4959	typedef struct X86TSS64
4960	{
4961	/** Reserved. */
4962	uint32_t u32Reserved;
4963	/** Ring-0 stack pointer. (static) */
4964	uint64_t rsp0;
4965	/** Ring-1 stack pointer. (static) */
4966	uint64_t rsp1;
4967	/** Ring-2 stack pointer. (static) */
4968	uint64_t rsp2;
4969	/** Reserved. */
4970	uint32_t u32Reserved2[2];
4971	/* IST */
4972	uint64_t ist1;
4973	uint64_t ist2;
4974	uint64_t ist3;
4975	uint64_t ist4;
4976	uint64_t ist5;
4977	uint64_t ist6;
4978	uint64_t ist7;
4979	/* Reserved. */
4980	uint16_t u16Reserved[5];
4981	/** Offset relative to the TSS of the start of the I/O Bitmap
4982	* and the end of the interrupt redirection bitmap. */
4983	uint16_t offIoBitmap;
4984	} X86TSS64;
4985	# pragma pack()
4986	/** Pointer to a 64-bit task segment. */
4987	typedef X86TSS64 *PX86TSS64;
4988	/** Pointer to a const 64-bit task segment. */
4989	typedef const X86TSS64 *PCX86TSS64;
4990	# ifndef VBOX_FOR_DTRACE_LIB
4991	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4992	# endif
4993
4994	#endif /* !__ASSEMBLER__ */
4995
4996	/** @} */
4997
4998
4999	/** @name Selectors.
5000	* @{
5001	*/
5002
5003	/**
5004	* The shift used to convert a selector from and to index an index (C).
5005	*/
5006	#define X86_SEL_SHIFT 3
5007
5008	/**
5009	* The mask used to mask off the table indicator and RPL of an selector.
5010	*/
5011	#define X86_SEL_MASK 0xfff8U
5012
5013	/**
5014	* The mask used to mask off the RPL of an selector.
5015	* This is suitable for checking for NULL selectors.
5016	*/
5017	#define X86_SEL_MASK_OFF_RPL 0xfffcU
5018
5019	/**
5020	* The bit indicating that a selector is in the LDT and not in the GDT.
5021	*/
5022	#define X86_SEL_LDT 0x0004U
5023
5024	/**
5025	* The bit mask for getting the RPL of a selector.
5026	*/
5027	#define X86_SEL_RPL 0x0003U
5028
5029	/**
5030	* The mask covering both RPL and LDT.
5031	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
5032	* checks.
5033	*/
5034	#define X86_SEL_RPL_LDT 0x0007U
5035
5036	/** @} */
5037
5038
5039	#ifndef __ASSEMBLER__
5040	/**
5041	* x86 Exceptions/Faults/Traps.
5042	*/
5043	typedef enum X86XCPT
5044	{
5045	/** \#DE - Divide error. */
5046	X86_XCPT_DE = 0x00,
5047	/** \#DB - Debug event (single step, DRx, ..) */
5048	X86_XCPT_DB = 0x01,
5049	/** NMI - Non-Maskable Interrupt */
5050	X86_XCPT_NMI = 0x02,
5051	/** \#BP - Breakpoint (INT3). */
5052	X86_XCPT_BP = 0x03,
5053	/** \#OF - Overflow (INTO). */
5054	X86_XCPT_OF = 0x04,
5055	/** \#BR - Bound range exceeded (BOUND). */
5056	X86_XCPT_BR = 0x05,
5057	/** \#UD - Undefined opcode. */
5058	X86_XCPT_UD = 0x06,
5059	/** \#NM - Device not available (math coprocessor device). */
5060	X86_XCPT_NM = 0x07,
5061	/** \#DF - Double fault. */
5062	X86_XCPT_DF = 0x08,
5063	/** ??? - Coprocessor segment overrun (obsolete). */
5064	X86_XCPT_CO_SEG_OVERRUN = 0x09,
5065	/** \#TS - Taskswitch (TSS). */
5066	X86_XCPT_TS = 0x0a,
5067	/** \#NP - Segment no present. */
5068	X86_XCPT_NP = 0x0b,
5069	/** \#SS - Stack segment fault. */
5070	X86_XCPT_SS = 0x0c,
5071	/** \#GP - General protection fault. */
5072	X86_XCPT_GP = 0x0d,
5073	/** \#PF - Page fault. */
5074	X86_XCPT_PF = 0x0e,
5075	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
5076	/** \#MF - Math fault (FPU). */
5077	X86_XCPT_MF = 0x10,
5078	/** \#AC - Alignment check. */
5079	X86_XCPT_AC = 0x11,
5080	/** \#MC - Machine check. */
5081	X86_XCPT_MC = 0x12,
5082	/** \#XF - SIMD Floating-Point Exception. */
5083	X86_XCPT_XF = 0x13,
5084	/** \#VE - Virtualization Exception (Intel only). */
5085	X86_XCPT_VE = 0x14,
5086	/** \#CP - Control Protection Exception. */
5087	X86_XCPT_CP = 0x15,
5088	/** \#VC - VMM Communication Exception (AMD only). */
5089	X86_XCPT_VC = 0x1d,
5090	/** \#SX - Security Exception (AMD only). */
5091	X86_XCPT_SX = 0x1e
5092	} X86XCPT;
5093	/** Pointer to a x86 exception code. */
5094	typedef X86XCPT *PX86XCPT;
5095	/** Pointer to a const x86 exception code. */
5096	typedef const X86XCPT *PCX86XCPT;
5097	#endif /* !__ASSEMBLER__ */
5098	/** The last valid (currently reserved) exception value. */
5099	#define X86_XCPT_LAST 0x1f
5100
5101
5102	/** @name Trap Error Codes
5103	* @{
5104	*/
5105	/** External indicator. */
5106	#define X86_TRAP_ERR_EXTERNAL 1
5107	/** IDT indicator. */
5108	#define X86_TRAP_ERR_IDT 2
5109	/** Descriptor table indicator - If set LDT, if clear GDT. */
5110	#define X86_TRAP_ERR_TI 4
5111	/** Mask for getting the selector. */
5112	#define X86_TRAP_ERR_SEL_MASK 0xfff8
5113	/** Shift for getting the selector table index (C type index). */
5114	#define X86_TRAP_ERR_SEL_SHIFT 3
5115	/** @} */
5116
5117
5118	/** @name \#PF Trap Error Codes
5119	* @{
5120	*/
5121	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
5122	#define X86_TRAP_PF_P RT_BIT_32(0)
5123	/** Bit 1 - R/W - Read (clear) or write (set) access. */
5124	#define X86_TRAP_PF_RW RT_BIT_32(1)
5125	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
5126	#define X86_TRAP_PF_US RT_BIT_32(2)
5127	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
5128	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
5129	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
5130	#define X86_TRAP_PF_ID RT_BIT_32(4)
5131	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
5132	#define X86_TRAP_PF_PK RT_BIT_32(5)
5133	/** @} */
5134
5135	#ifndef __ASSEMBLER__
5136
5137	# pragma pack(1)
5138	/**
5139	* 16-bit IDTR.
5140	*/
5141	typedef struct X86IDTR16
5142	{
5143	/** Offset. */
5144	uint16_t offSel;
5145	/** Selector. */
5146	uint16_t uSel;
5147	} X86IDTR16, *PX86IDTR16;
5148	# pragma pack()
5149
5150	# pragma pack(1)
5151	/**
5152	* 32-bit IDTR/GDTR.
5153	*/
5154	typedef struct X86XDTR32
5155	{
5156	/** Size of the descriptor table. */
5157	uint16_t cb;
5158	/** Address of the descriptor table. */
5159	# ifndef VBOX_FOR_DTRACE_LIB
5160	uint32_t uAddr;
5161	# else
5162	uint16_t au16Addr[2];
5163	# endif
5164	} X86XDTR32, *PX86XDTR32;
5165	# pragma pack()
5166
5167	# pragma pack(1)
5168	/**
5169	* 64-bit IDTR/GDTR.
5170	*/
5171	typedef struct X86XDTR64
5172	{
5173	/** Size of the descriptor table. */
5174	uint16_t cb;
5175	/** Address of the descriptor table. */
5176	# ifndef VBOX_FOR_DTRACE_LIB
5177	uint64_t uAddr;
5178	# else
5179	uint16_t au16Addr[4];
5180	# endif
5181	} X86XDTR64, *PX86XDTR64;
5182	# pragma pack()
5183
5184	#endif /* !__ASSEMBLER__ */
5185
5186
5187	/** @name ModR/M
5188	* @{ */
5189	#define X86_MODRM_RM_MASK UINT8_C(0x07)
5190	#define X86_MODRM_REG_MASK UINT8_C(0x38)
5191	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
5192	#define X86_MODRM_REG_SHIFT 3
5193	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
5194	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
5195	#define X86_MODRM_MOD_SHIFT 6
5196
5197	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
5198	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
5199	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
5200	#define X86_MOD_REG 3 /*< Registers. /
5201
5202	#ifndef VBOX_FOR_DTRACE_LIB
5203	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
5204	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
5205	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
5206	/** @def X86_MODRM_MAKE
5207	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
5208	* @param a_Reg The register value (0..7).
5209	* @param a_RegMem The register or memory value (0..7). */
5210	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
5211	#endif
5212
5213	/** @} */
5214
5215	/** @name SIB
5216	* @{ */
5217	#define X86_SIB_BASE_MASK UINT8_C(0x07)
5218	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
5219	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
5220	#define X86_SIB_INDEX_SHIFT 3
5221	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
5222	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
5223	#define X86_SIB_SCALE_SHIFT 6
5224	#ifndef VBOX_FOR_DTRACE_LIB
5225	/** @def X86_SIB_MAKE
5226	* @param a_BaseReg The base register value (0..7).
5227	* @param a_IndexReg The index register value (0..7).
5228	* @param a_Scale The left shift (0..3) to be applied to the index
5229	* register (0 = none, 1 = x2, 2 = x4, 3 = x8).
5230	* */
5231	# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
5232	(((a_Scale) << X86_SIB_SCALE_SHIFT) \| ((a_IndexReg) << X86_SIB_INDEX_SHIFT) \| (a_BaseReg))
5233
5234	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
5235	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
5236	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
5237	#endif
5238	/** @} */
5239
5240	/** @name General register indexes.
5241	* @{ */
5242	#define X86_GREG_xAX 0
5243	#define X86_GREG_xCX 1
5244	#define X86_GREG_xDX 2
5245	#define X86_GREG_xBX 3
5246	#define X86_GREG_xSP 4
5247	#define X86_GREG_xBP 5
5248	#define X86_GREG_xSI 6
5249	#define X86_GREG_xDI 7
5250	#define X86_GREG_x8 8
5251	#define X86_GREG_x9 9
5252	#define X86_GREG_x10 10
5253	#define X86_GREG_x11 11
5254	#define X86_GREG_x12 12
5255	#define X86_GREG_x13 13
5256	#define X86_GREG_x14 14
5257	#define X86_GREG_x15 15
5258	/** @} */
5259	/** General register count. */
5260	#define X86_GREG_COUNT 16
5261
5262	/** @name X86_SREG_XXX - Segment register indexes.
5263	* @{ */
5264	#define X86_SREG_ES 0
5265	#define X86_SREG_CS 1
5266	#define X86_SREG_SS 2
5267	#define X86_SREG_DS 3
5268	#define X86_SREG_FS 4
5269	#define X86_SREG_GS 5
5270	/** @} */
5271	/** Segment register count. */
5272	#define X86_SREG_COUNT 6
5273
5274
5275	/** @name X86_OP_XXX - Prefixes
5276	* @{ */
5277	#define X86_OP_PRF_CS UINT8_C(0x2e)
5278	#define X86_OP_PRF_SS UINT8_C(0x36)
5279	#define X86_OP_PRF_DS UINT8_C(0x3e)
5280	#define X86_OP_PRF_ES UINT8_C(0x26)
5281	#define X86_OP_PRF_FS UINT8_C(0x64)
5282	#define X86_OP_PRF_GS UINT8_C(0x65)
5283	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5284	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5285	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5286	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5287	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5288	#define X86_OP_REX UINT8_C(0x40)
5289	#define X86_OP_REX_B UINT8_C(0x41)
5290	#define X86_OP_REX_X UINT8_C(0x42)
5291	#define X86_OP_REX_R UINT8_C(0x44)
5292	#define X86_OP_REX_W UINT8_C(0x48)
5293	#define X86_OP_VEX3 UINT8_C(0xc4)
5294	#define X86_OP_VEX2 UINT8_C(0xc5)
5295	/** @} */
5296
5297	/** @name X86_OP_VEX2_XXX - 2-byte VEX prefix helpers.
5298	* @{ */
5299	#define X86_OP_VEX2_BYTE1_P_MASK 0x3
5300	# define X86_OP_VEX2_BYTE1_P_NO_PRF 0
5301	# define X86_OP_VEX2_BYTE1_P_066H 1
5302	# define X86_OP_VEX2_BYTE1_P_0F3H 2
5303	# define X86_OP_VEX2_BYTE1_P_0F2H 3
5304	#define X86_OP_VEX2_BYTE1_L RT_BIT(2)
5305	#define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78
5306	#define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3
5307	#define X86_OP_VEX2_BYTE1_VVVV_NONE 15
5308	#define X86_OP_VEX2_BYTE1_R RT_BIT(7)
5309
5310	#define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5311	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5312	\| (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5313	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5314	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5315
5316	#define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \
5317	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5318	\| (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5319	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5320	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5321	/** @} */
5322
5323	/** @name X86_OP_VEX3_XXX - 3-byte VEX prefix helpers.
5324	* @{ */
5325	#define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f
5326	#define X86_OP_VEX3_BYTE1_B RT_BIT(5)
5327	#define X86_OP_VEX3_BYTE1_X RT_BIT(6)
5328	#define X86_OP_VEX3_BYTE1_R RT_BIT(7)
5329	#define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \
5330	( (uint8_t)(a_idxMap) \
5331	\| ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \
5332	\| ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \
5333	\| ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R))
5334
5335	#define X86_OP_VEX3_BYTE2_P_MASK 0x3
5336	# define X86_OP_VEX3_BYTE2_P_NO_PRF 0
5337	# define X86_OP_VEX3_BYTE2_P_066H 1
5338	# define X86_OP_VEX3_BYTE2_P_0F3H 2
5339	# define X86_OP_VEX3_BYTE2_P_0F2H 3
5340	#define X86_OP_VEX3_BYTE2_L RT_BIT(2)
5341	#define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78
5342	#define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3
5343	#define X86_OP_VEX3_BYTE2_VVVV_NONE 15
5344	#define X86_OP_VEX3_BYTE2_W RT_BIT(7)
5345
5346	/** @todo r=bird: Is the '& UINT8_C(0xf)' bit needed? You mask it again after
5347	* shifting. */
5348	#define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5349	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5350	\| ((~((uint8_t)(a_iSrcReg) & UINT8_C(0xf)) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \
5351	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5352	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5353
5354	#define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \
5355	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5356	\| (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
5357	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5358	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5359	/** @} */
5360
5361	/** @} */
5362
5363	#endif /* !IPRT_INCLUDED_x86_h */
5364

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source: vbox/trunk/include/iprt/x86.h@ 106967

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