x86.h@ 107807

Last change on this file since 107807 was 107731, checked in by vboxsync, 4 weeks ago
VMM/CPUM: Added some missing CPUID extended feature bits and fixed a couple of bugs in previous x86.h changes. jiraref:VBP-947
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 209.1 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# ifndef __ASSEMBLER__
46	# include <iprt/types.h>
47	# include <iprt/assert.h>
48	# else
49	# include <iprt/stdint.h>
50	# include <iprt/assertcompile.h>
51	# endif
52	#else
53	# pragma D depends_on library vbox-types.d
54	#endif
55
56	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
57	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
58	#ifdef RT_OS_SOLARIS
59	# undef CS
60	# undef DS
61	# undef MSR_IA32_FLUSH_CMD
62	# undef MSR_AMD_VIRT_SPEC_CTL
63	#endif
64
65	/** @defgroup grp_rt_x86 x86 Types and Definitions
66	* @ingroup grp_rt
67	* @{
68	*/
69
70	#ifndef __ASSEMBLER__
71
72	# ifndef VBOX_FOR_DTRACE_LIB
73	/**
74	* EFLAGS Bits.
75	*/
76	typedef struct X86EFLAGSBITS
77	{
78	/** Bit 0 - CF - Carry flag - Status flag. */
79	unsigned u1CF : 1;
80	/** Bit 1 - 1 - Reserved flag. */
81	unsigned u1Reserved0 : 1;
82	/** Bit 2 - PF - Parity flag - Status flag. */
83	unsigned u1PF : 1;
84	/** Bit 3 - 0 - Reserved flag. */
85	unsigned u1Reserved1 : 1;
86	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
87	unsigned u1AF : 1;
88	/** Bit 5 - 0 - Reserved flag. */
89	unsigned u1Reserved2 : 1;
90	/** Bit 6 - ZF - Zero flag - Status flag. */
91	unsigned u1ZF : 1;
92	/** Bit 7 - SF - Signed flag - Status flag. */
93	unsigned u1SF : 1;
94	/** Bit 8 - TF - Trap flag - System flag. */
95	unsigned u1TF : 1;
96	/** Bit 9 - IF - Interrupt flag - System flag. */
97	unsigned u1IF : 1;
98	/** Bit 10 - DF - Direction flag - Control flag. */
99	unsigned u1DF : 1;
100	/** Bit 11 - OF - Overflow flag - Status flag. */
101	unsigned u1OF : 1;
102	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
103	unsigned u2IOPL : 2;
104	/** Bit 14 - NT - Nested task flag - System flag. */
105	unsigned u1NT : 1;
106	/** Bit 15 - 0 - Reserved flag. */
107	unsigned u1Reserved3 : 1;
108	/** Bit 16 - RF - Resume flag - System flag. */
109	unsigned u1RF : 1;
110	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
111	unsigned u1VM : 1;
112	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
113	unsigned u1AC : 1;
114	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
115	unsigned u1VIF : 1;
116	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
117	unsigned u1VIP : 1;
118	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
119	unsigned u1ID : 1;
120	/** Bit 22-31 - 0 - Reserved flag. */
121	unsigned u10Reserved4 : 10;
122	} X86EFLAGSBITS;
123	/** Pointer to EFLAGS bits. */
124	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
125	/** Pointer to const EFLAGS bits. */
126	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
127	# endif /* !VBOX_FOR_DTRACE_LIB */
128
129	/**
130	* EFLAGS.
131	*/
132	typedef union X86EFLAGS
133	{
134	/** The plain unsigned view. */
135	uint32_t u;
136	# ifndef VBOX_FOR_DTRACE_LIB
137	/** The bitfield view. */
138	X86EFLAGSBITS Bits;
139	# endif
140	/** The 8-bit view. */
141	uint8_t au8[4];
142	/** The 16-bit view. */
143	uint16_t au16[2];
144	/** The 32-bit view. */
145	uint32_t au32[1];
146	/** The 32-bit view. */
147	uint32_t u32;
148	} X86EFLAGS;
149	/** Pointer to EFLAGS. */
150	typedef X86EFLAGS *PX86EFLAGS;
151	/** Pointer to const EFLAGS. */
152	typedef const X86EFLAGS *PCX86EFLAGS;
153
154	/**
155	* RFLAGS (32 upper bits are reserved).
156	*/
157	typedef union X86RFLAGS
158	{
159	/** The plain unsigned view. */
160	uint64_t u;
161	# ifndef VBOX_FOR_DTRACE_LIB
162	/** The bitfield view. */
163	X86EFLAGSBITS Bits;
164	# endif
165	/** The 8-bit view. */
166	uint8_t au8[8];
167	/** The 16-bit view. */
168	uint16_t au16[4];
169	/** The 32-bit view. */
170	uint32_t au32[2];
171	/** The 64-bit view. */
172	uint64_t au64[1];
173	/** The 64-bit view. */
174	uint64_t u64;
175	} X86RFLAGS;
176	/** Pointer to RFLAGS. */
177	typedef X86RFLAGS *PX86RFLAGS;
178	/** Pointer to const RFLAGS. */
179	typedef const X86RFLAGS *PCX86RFLAGS;
180
181	#endif /* !__ASSEMBLER__ */
182
183
184	/** @name EFLAGS
185	* @{
186	*/
187	/** Bit 0 - CF - Carry flag - Status flag. */
188	#define X86_EFL_CF RT_BIT_32(0)
189	#define X86_EFL_CF_BIT 0
190	/** Bit 1 - Reserved, reads as 1. */
191	#define X86_EFL_1 RT_BIT_32(1)
192	#define X86_EFL_1_BIT 1
193	/** Bit 2 - PF - Parity flag - Status flag. */
194	#define X86_EFL_PF RT_BIT_32(2)
195	#define X86_EFL_PF_BIT 2
196	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
197	#define X86_EFL_AF RT_BIT_32(4)
198	#define X86_EFL_AF_BIT 4
199	/** Bit 6 - ZF - Zero flag - Status flag. */
200	#define X86_EFL_ZF RT_BIT_32(6)
201	#define X86_EFL_ZF_BIT 6
202	/** Bit 7 - SF - Signed flag - Status flag. */
203	#define X86_EFL_SF RT_BIT_32(7)
204	#define X86_EFL_SF_BIT 7
205	/** Bit 8 - TF - Trap flag - System flag. */
206	#define X86_EFL_TF RT_BIT_32(8)
207	#define X86_EFL_TF_BIT 8
208	/** Bit 9 - IF - Interrupt flag - System flag. */
209	#define X86_EFL_IF RT_BIT_32(9)
210	#define X86_EFL_IF_BIT 9
211	/** Bit 10 - DF - Direction flag - Control flag. */
212	#define X86_EFL_DF RT_BIT_32(10)
213	#define X86_EFL_DF_BIT 10
214	/** Bit 11 - OF - Overflow flag - Status flag. */
215	#define X86_EFL_OF RT_BIT_32(11)
216	#define X86_EFL_OF_BIT 11
217	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
218	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
219	/** Bit 14 - NT - Nested task flag - System flag. */
220	#define X86_EFL_NT RT_BIT_32(14)
221	#define X86_EFL_NT_BIT 14
222	/** Bit 16 - RF - Resume flag - System flag. */
223	#define X86_EFL_RF RT_BIT_32(16)
224	#define X86_EFL_RF_BIT 16
225	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
226	#define X86_EFL_VM RT_BIT_32(17)
227	#define X86_EFL_VM_BIT 17
228	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
229	#define X86_EFL_AC RT_BIT_32(18)
230	#define X86_EFL_AC_BIT 18
231	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
232	#define X86_EFL_VIF RT_BIT_32(19)
233	#define X86_EFL_VIF_BIT 19
234	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
235	#define X86_EFL_VIP RT_BIT_32(20)
236	#define X86_EFL_VIP_BIT 20
237	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
238	#define X86_EFL_ID RT_BIT_32(21)
239	#define X86_EFL_ID_BIT 21
240	/** All live bits. */
241	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
242	/** Read as 1 bits. */
243	#define X86_EFL_RA1_MASK RT_BIT_32(1)
244	/** Read as 0 bits, excluding bits 31:22.
245	* Bits 3, 5, 15, and 22 thru 31. */
246	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
247	/** Read as 0 bits, excluding bits 31:22.
248	* Bits 3, 5 and 15. */
249	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
250	/** IOPL shift. */
251	#define X86_EFL_IOPL_SHIFT 12
252	/** The IOPL level from the flags. */
253	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
254	/** Bits restored by popf */
255	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
256	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
257	/** Bits restored by popf */
258	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
259	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
260	/** The status bits commonly updated by arithmetic instructions. */
261	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
262	/** @} */
263
264
265	#ifndef __ASSEMBLER__
266
267	/** CPUID Feature information - ECX.
268	* CPUID query with EAX=1.
269	*/
270	# ifndef VBOX_FOR_DTRACE_LIB
271	typedef struct X86CPUIDFEATECX
272	{
273	/** Bit 0 - SSE3 - Supports SSE3 or not. */
274	unsigned u1SSE3 : 1;
275	/** Bit 1 - PCLMULQDQ. */
276	unsigned u1PCLMULQDQ : 1;
277	/** Bit 2 - DS Area 64-bit layout. */
278	unsigned u1DTE64 : 1;
279	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
280	unsigned u1Monitor : 1;
281	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
282	unsigned u1CPLDS : 1;
283	/** Bit 5 - VMX - Virtual Machine Technology. */
284	unsigned u1VMX : 1;
285	/** Bit 6 - SMX: Safer Mode Extensions. */
286	unsigned u1SMX : 1;
287	/** Bit 7 - EST - Enh. SpeedStep Tech. */
288	unsigned u1EST : 1;
289	/** Bit 8 - TM2 - Terminal Monitor 2. */
290	unsigned u1TM2 : 1;
291	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
292	unsigned u1SSSE3 : 1;
293	/** Bit 10 - CNTX-ID - L1 Context ID. */
294	unsigned u1CNTXID : 1;
295	/** Bit 11 - Reserved. */
296	unsigned u1Reserved1 : 1;
297	/** Bit 12 - FMA. */
298	unsigned u1FMA : 1;
299	/** Bit 13 - CX16 - CMPXCHG16B. */
300	unsigned u1CX16 : 1;
301	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
302	unsigned u1TPRUpdate : 1;
303	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
304	unsigned u1PDCM : 1;
305	/** Bit 16 - Reserved. */
306	unsigned u1Reserved2 : 1;
307	/** Bit 17 - PCID - Process-context identifiers. */
308	unsigned u1PCID : 1;
309	/** Bit 18 - Direct Cache Access. */
310	unsigned u1DCA : 1;
311	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
312	unsigned u1SSE4_1 : 1;
313	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
314	unsigned u1SSE4_2 : 1;
315	/** Bit 21 - x2APIC. */
316	unsigned u1x2APIC : 1;
317	/** Bit 22 - MOVBE - Supports MOVBE. */
318	unsigned u1MOVBE : 1;
319	/** Bit 23 - POPCNT - Supports POPCNT. */
320	unsigned u1POPCNT : 1;
321	/** Bit 24 - TSC-Deadline. */
322	unsigned u1TSCDEADLINE : 1;
323	/** Bit 25 - AES. */
324	unsigned u1AES : 1;
325	/** Bit 26 - XSAVE - Supports XSAVE. */
326	unsigned u1XSAVE : 1;
327	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
328	unsigned u1OSXSAVE : 1;
329	/** Bit 28 - AVX - Supports AVX instruction extensions. */
330	unsigned u1AVX : 1;
331	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
332	unsigned u1F16C : 1;
333	/** Bit 30 - RDRAND - Supports RDRAND. */
334	unsigned u1RDRAND : 1;
335	/** Bit 31 - Hypervisor present (we're a guest). */
336	unsigned u1HVP : 1;
337	} X86CPUIDFEATECX;
338	# else /* VBOX_FOR_DTRACE_LIB */
339	typedef uint32_t X86CPUIDFEATECX;
340	# endif /* VBOX_FOR_DTRACE_LIB */
341	/** Pointer to CPUID Feature Information - ECX. */
342	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
343	/** Pointer to const CPUID Feature Information - ECX. */
344	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
345
346
347	/** CPUID Feature Information - EDX.
348	* CPUID query with EAX=1.
349	*/
350	# ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
351	typedef struct X86CPUIDFEATEDX
352	{
353	/** Bit 0 - FPU - x87 FPU on Chip. */
354	unsigned u1FPU : 1;
355	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
356	unsigned u1VME : 1;
357	/** Bit 2 - DE - Debugging extensions. */
358	unsigned u1DE : 1;
359	/** Bit 3 - PSE - Page Size Extension. */
360	unsigned u1PSE : 1;
361	/** Bit 4 - TSC - Time Stamp Counter. */
362	unsigned u1TSC : 1;
363	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
364	unsigned u1MSR : 1;
365	/** Bit 6 - PAE - Physical Address Extension. */
366	unsigned u1PAE : 1;
367	/** Bit 7 - MCE - Machine Check Exception. */
368	unsigned u1MCE : 1;
369	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
370	unsigned u1CX8 : 1;
371	/** Bit 9 - APIC - APIC On-Chip. */
372	unsigned u1APIC : 1;
373	/** Bit 10 - Reserved. */
374	unsigned u1Reserved1 : 1;
375	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
376	unsigned u1SEP : 1;
377	/** Bit 12 - MTRR - Memory Type Range Registers. */
378	unsigned u1MTRR : 1;
379	/** Bit 13 - PGE - PTE Global Bit. */
380	unsigned u1PGE : 1;
381	/** Bit 14 - MCA - Machine Check Architecture. */
382	unsigned u1MCA : 1;
383	/** Bit 15 - CMOV - Conditional Move Instructions. */
384	unsigned u1CMOV : 1;
385	/** Bit 16 - PAT - Page Attribute Table. */
386	unsigned u1PAT : 1;
387	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
388	unsigned u1PSE36 : 1;
389	/** Bit 18 - PSN - Processor Serial Number. */
390	unsigned u1PSN : 1;
391	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
392	unsigned u1CLFSH : 1;
393	/** Bit 20 - Reserved. */
394	unsigned u1Reserved2 : 1;
395	/** Bit 21 - DS - Debug Store. */
396	unsigned u1DS : 1;
397	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
398	unsigned u1ACPI : 1;
399	/** Bit 23 - MMX - Intel MMX 'Technology'. */
400	unsigned u1MMX : 1;
401	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
402	unsigned u1FXSR : 1;
403	/** Bit 25 - SSE - SSE Support. */
404	unsigned u1SSE : 1;
405	/** Bit 26 - SSE2 - SSE2 Support. */
406	unsigned u1SSE2 : 1;
407	/** Bit 27 - SS - Self Snoop. */
408	unsigned u1SS : 1;
409	/** Bit 28 - HTT - Hyper-Threading Technology. */
410	unsigned u1HTT : 1;
411	/** Bit 29 - TM - Thermal Monitor. */
412	unsigned u1TM : 1;
413	/** Bit 30 - Reserved - . */
414	unsigned u1Reserved3 : 1;
415	/** Bit 31 - PBE - Pending Break Enabled. */
416	unsigned u1PBE : 1;
417	} X86CPUIDFEATEDX;
418	# else /* VBOX_FOR_DTRACE_LIB */
419	typedef uint32_t X86CPUIDFEATEDX;
420	# endif /* VBOX_FOR_DTRACE_LIB */
421	/** Pointer to CPUID Feature Information - EDX. */
422	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
423	/** Pointer to const CPUID Feature Information - EDX. */
424	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
425
426	#endif /* !__ASSEMBLER__ */
427
428
429	/** @name CPUID Vendor information.
430	* CPUID query with EAX=0.
431	* @{
432	*/
433	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
434	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
435	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
436
437	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
438	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
439	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
440
441	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
442	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
443	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
444
445	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
446	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
447	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
448
449	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
450	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
451	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
452	/** @} */
453
454
455	/** @name CPUID Feature information.
456	* CPUID query with EAX=1.
457	* @{
458	*/
459	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
460	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
461	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
462	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
463	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
464	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
465	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
466	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
467	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
468	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
469	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
470	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
471	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
472	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
473	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
474	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
475	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
476	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
477	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
478	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
479	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
480	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
481	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
482	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
483	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
484	/** ECX Bit 12 - FMA. */
485	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
486	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
487	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
488	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
489	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
490	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
491	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
492	/** ECX Bit 17 - PCID - Process-context identifiers. */
493	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
494	/** ECX Bit 18 - DCA - Direct Cache Access. */
495	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
496	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
497	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
498	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
499	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
500	/** ECX Bit 21 - x2APIC support. */
501	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
502	/** ECX Bit 22 - MOVBE instruction. */
503	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
504	/** ECX Bit 23 - POPCNT instruction. */
505	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
506	/** ECX Bir 24 - TSC-Deadline. */
507	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
508	/** ECX Bit 25 - AES instructions. */
509	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
510	/** ECX Bit 26 - XSAVE instruction. */
511	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
512	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
513	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
514	/** ECX Bit 28 - AVX. */
515	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
516	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
517	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
518	/** ECX Bit 30 - RDRAND instruction. */
519	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
520	/** ECX Bit 31 - Hypervisor Present (software only). */
521	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
522
523
524	/** Bit 0 - FPU - x87 FPU on Chip. */
525	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
526	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
527	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
528	/** Bit 2 - DE - Debugging extensions. */
529	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
530	/** Bit 3 - PSE - Page Size Extension. */
531	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
532	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
533	/** Bit 4 - TSC - Time Stamp Counter. */
534	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
535	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
536	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
537	/** Bit 6 - PAE - Physical Address Extension. */
538	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
539	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
540	/** Bit 7 - MCE - Machine Check Exception. */
541	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
542	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
543	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
544	/** Bit 9 - APIC - APIC On-Chip. */
545	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
546	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
547	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
548	/** Bit 12 - MTRR - Memory Type Range Registers. */
549	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
550	/** Bit 13 - PGE - PTE Global Bit. */
551	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
552	/** Bit 14 - MCA - Machine Check Architecture. */
553	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
554	/** Bit 15 - CMOV - Conditional Move Instructions. */
555	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
556	/** Bit 16 - PAT - Page Attribute Table. */
557	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
558	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
559	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
560	/** Bit 18 - PSN - Processor Serial Number. */
561	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
562	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
563	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
564	/** Bit 21 - DS - Debug Store. */
565	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
566	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
567	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
568	/** Bit 23 - MMX - Intel MMX Technology. */
569	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
570	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
571	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
572	/** Bit 25 - SSE - SSE Support. */
573	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
574	/** Bit 26 - SSE2 - SSE2 Support. */
575	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
576	/** Bit 27 - SS - Self Snoop. */
577	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
578	/** Bit 28 - HTT - Hyper-Threading Technology. */
579	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
580	/** Bit 29 - TM - Therm. Monitor. */
581	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
582	/** Bit 31 - PBE - Pending Break Enabled. */
583	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
584	/** @} */
585
586	/** @name CPUID mwait/monitor information.
587	* CPUID query with EAX=5.
588	* @{
589	*/
590	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
591	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
592	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
593	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
594	/** @} */
595
596
597	/** @name CPUID Thermal and Power Management information.
598	* Generally Intel only unless noted otherwise.
599	* CPUID query with EAX=5. @{
600	*/
601	/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
602	#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
603	/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
604	#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
605	/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
606	#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
607	/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
608	#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
609	/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
610	#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
611	/** EAX Bit 6 - PTM - Package Thermal Management supported. */
612	#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
613	/** EAX Bit 7 - HWP - HWP base MSRs supported. */
614	#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
615	/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
616	#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
617	/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
618	#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
619	/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
620	#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
621	/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
622	#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
623	/** EAX Bit 13 - HDC - HDC base MSRs supported. */
624	#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
625	/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
626	#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
627	/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
628	#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
629	/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
630	#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
631	/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
632	#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
633
634	/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
635	#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
636	/** @} */
637
638
639	/** @name CPUID Structured Extended Feature information, \#0.
640	* CPUID query with EAX=7 and ECX=0.
641	* @{
642	*/
643	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
644	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
645	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
646	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
647	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
648	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
649	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
650	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
651	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
652	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
653	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
654	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
655	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
656	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
657	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
658	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
659	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
660	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
661	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
662	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
663	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
664	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
665	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
666	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
667	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
668	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
669	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
670	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
671	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
672	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
673	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
674	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
675	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
676	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
677	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
678	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
679	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
680	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
681	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
682	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
683	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
684	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
685	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
686	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
687	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
688	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
689	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
690	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
691	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
692	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
693	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
694	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
695
696	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
697	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
698	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
699	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
700	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
701	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
702	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
703	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
704	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
705	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
706	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
707	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
708	/** ECX Bit 22 - RDPID - Support pread process ID. */
709	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
710	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
711	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
712
713	/** EDX bit 9 - SRBDS_CTRL - (Special Register Buffer Data Sample Control)
714	* Supports IA32_MCU_OPT_CTRL and IA32_MCU_OPT_CTRL.RNGDS_MITG_DIS. */
715	#define X86_CPUID_STEXT_FEATURE_EDX_SRBDS_CTRL RT_BIT_32(9)
716	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
717	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
718	/** EDX Bit 11 - TSX_FORCE_ABORT - Supports for IA32_TSX_FORCE_ABORT MSR. */
719	#define X86_CPUID_STEXT_FEATURE_EDX_TSX_FORCE_ABORT RT_BIT_32(11)
720	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
721	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
722	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
723	* IBPB command in IA32_PRED_CMD. */
724	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
725	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
726	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
727	/** EDX Bit 28 - FLUSH_CMD - Supports the IA32_FLUSH_CMD.L1D_FLUSH command. */
728	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
729	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
730	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
731	/** EDX Bit 30 - CORECAP - Supports the IA32_CORE_CAPABILITIES MSR. */
732	#define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
733	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
734	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
735	/** @} */
736
737	/** @name CPUID Structured Extended Feature information, \#2.
738	* CPUID query with EAX=7 and ECX=2.
739	* @{
740	*/
741	/** EDX Bit 0 - PSFD - IA32_SPEC_CTRL[7] (PSFD) supported. */
742	#define X86_CPUID_STEXT_FEATURE_2_EDX_PSFD RT_BIT_32(0)
743	/** EDX Bit 1 - IPRED_CTRL - IA32_SPEC_CTRL[4:3] (IPRED_DIS_S/U) supported. */
744	#define X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL RT_BIT_32(1)
745	/** EDX Bit 2 - RRSBA_CTRL - IA32_SPEC_CTRL[6:5] (RRSBA_DIS_S/U) supported. */
746	#define X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL RT_BIT_32(2)
747	/** EDX Bit 3 - DDPD_U - IA32_SPEC_CTRL[8] (DDPD_U) supported. */
748	#define X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U RT_BIT_32(3)
749	/** EDX Bit 4 - BHI_CTRL - IA32_SPEC_CTRL[10] (BHI_DIS_S) supported. */
750	#define X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL RT_BIT_32(4)
751	/** EDX Bit 5 - MCDT_NO - No MXCSR Configuration Dependent Timing issues. */
752	#define X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO RT_BIT_32(5)
753	/** EDX Bit 6 - UC_LOCK_DIS - Supports UC-lock disable and causing \#AC. */
754	#define X86_CPUID_STEXT_FEATURE_2_EDX_UC_LOCK_DIS RT_BIT_32(6)
755	/** EDX Bit 7 - MONITOR_MITG_NO - No need for MONITOR/UMONITOR power mitigrations. */
756	#define X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO RT_BIT_32(7)
757	/** @} */
758
759
760	/** @name CPUID Extended Feature information.
761	* CPUID query with EAX=0x80000001.
762	* @{
763	*/
764	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
765	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
766
767	/** EDX Bit 11 - SYSCALL/SYSRET. */
768	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
769	/** EDX Bit 20 - No-Execute/Execute-Disable. */
770	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
771	/** EDX Bit 26 - 1 GB large page. */
772	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
773	/** EDX Bit 27 - RDTSCP. */
774	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
775	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
776	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
777	/** @}*/
778
779	/** @name CPUID AMD Feature information.
780	* CPUID query with EAX=0x80000001.
781	* @{
782	*/
783	/** Bit 0 - FPU - x87 FPU on Chip. */
784	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
785	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
786	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
787	/** Bit 2 - DE - Debugging extensions. */
788	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
789	/** Bit 3 - PSE - Page Size Extension. */
790	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
791	/** Bit 4 - TSC - Time Stamp Counter. */
792	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
793	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
794	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
795	/** Bit 6 - PAE - Physical Address Extension. */
796	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
797	/** Bit 7 - MCE - Machine Check Exception. */
798	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
799	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
800	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
801	/** Bit 9 - APIC - APIC On-Chip. */
802	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
803	/** Bit 12 - MTRR - Memory Type Range Registers. */
804	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
805	/** Bit 13 - PGE - PTE Global Bit. */
806	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
807	/** Bit 14 - MCA - Machine Check Architecture. */
808	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
809	/** Bit 15 - CMOV - Conditional Move Instructions. */
810	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
811	/** Bit 16 - PAT - Page Attribute Table. */
812	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
813	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
814	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
815	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
816	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
817	/** Bit 23 - MMX - Intel MMX Technology. */
818	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
819	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
820	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
821	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
822	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
823	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
824	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
825	/** Bit 31 - 3DNOW - AMD 3DNow. */
826	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
827
828	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
829	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
830	/** Bit 2 - SVM - AMD VM extensions. */
831	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
832	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
833	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
834	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
835	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
836	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
837	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
838	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
839	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
840	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
841	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
842	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
843	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
844	/** Bit 9 - OSVW - AMD OS visible workaround. */
845	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
846	/** Bit 10 - IBS - Instruct based sampling. */
847	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
848	/** Bit 11 - XOP - Extended operation support (see APM6). */
849	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
850	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
851	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
852	/** Bit 13 - WDT - AMD Watchdog timer support. */
853	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
854	/** Bit 15 - LWP - Lightweight profiling support. */
855	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
856	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
857	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
858	/** Bit 19 - NodeId - Indicates support for
859	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
860	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
861	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
862	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
863	/** Bit 22 - TopologyExtensions - . */
864	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
865	/** @} */
866
867
868	/** @name CPUID AMD Feature information.
869	* CPUID query with EAX=0x80000007.
870	* @{
871	*/
872	/** Bit 0 - TS - Temperature Sensor. */
873	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
874	/** Bit 1 - FID - Frequency ID Control. */
875	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
876	/** Bit 2 - VID - Voltage ID Control. */
877	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
878	/** Bit 3 - TTP - THERMTRIP. */
879	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
880	/** Bit 4 - TM - Hardware Thermal Control. */
881	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
882	/** Bit 5 - STC - Software Thermal Control. */
883	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
884	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
885	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
886	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
887	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
888	/** Bit 8 - TSCINVAR - TSC Invariant. */
889	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
890	/** Bit 9 - CPB - TSC Invariant. */
891	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
892	/** Bit 10 - EffFreqRO - MPERF/APERF. */
893	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
894	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
895	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
896	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
897	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
898	/** @} */
899
900
901	/** @name CPUID AMD extended feature extensions ID (EBX).
902	* CPUID query with EAX=0x80000008.
903	* @{
904	*/
905	/** Bit 0 - CLZERO - Clear zero instruction. */
906	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
907	/** Bit 1 - IRPerf - Instructions retired count support. */
908	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
909	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
910	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
911	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
912	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
913	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
914	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
915	/* AMD pipeline length: 9 feature bits ;-) */
916	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
917	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
918	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
919	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
920	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
921	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
922	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
923	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
924	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
925	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
926	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
927	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
928	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
929	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
930	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
931	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
932	/** Bit 26 - Speculative Store Bypass Disable not required. */
933	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
934	/** @} */
935
936
937	/** @name CPUID AMD SVM Feature information.
938	* CPUID query with EAX=0x8000000a.
939	* @{
940	*/
941	/** Bit 0 - NP - Nested Paging supported. */
942	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
943	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
944	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
945	/** Bit 2 - SVML - SVM locking bit supported. */
946	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
947	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
948	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
949	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
950	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
951	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
952	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
953	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
954	* VMCB.TLB_Control is supported. */
955	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
956	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
957	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
958	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
959	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
960	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
961	* intercept filter cycle count threshold. */
962	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
963	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
964	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
965	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
966	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
967	/** Bit 16 - VGIF - Supports virtualized GIF. */
968	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
969	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
970	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
971	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
972	* mode. */
973	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
974	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
975	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
976	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
977	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
978	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
979	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
980	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
981	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
982	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
983	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
984	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
985	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
986	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
987	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
988	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
989	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
990	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
991	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
992	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
993	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
994
995	/** @} */
996
997
998	/** @name CR0
999	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
1000	* reserved flags.
1001	* @{ */
1002	/** Bit 0 - PE - Protection Enabled */
1003	#define X86_CR0_PE RT_BIT_32(0)
1004	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
1005	#define X86_CR0_PE_BIT 0
1006	/** Bit 1 - MP - Monitor Coprocessor */
1007	#define X86_CR0_MP RT_BIT_32(1)
1008	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
1009	#define X86_CR0_MP_BIT 1
1010	/** Bit 2 - EM - Emulation. */
1011	#define X86_CR0_EM RT_BIT_32(2)
1012	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
1013	#define X86_CR0_EM_BIT 2
1014	/** Bit 3 - TS - Task Switch. */
1015	#define X86_CR0_TS RT_BIT_32(3)
1016	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
1017	#define X86_CR0_TS_BIT 3
1018	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
1019	#define X86_CR0_ET RT_BIT_32(4)
1020	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
1021	#define X86_CR0_ET_BIT 4
1022	/** Bit 5 - NE - Numeric error (486+). */
1023	#define X86_CR0_NE RT_BIT_32(5)
1024	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
1025	#define X86_CR0_NE_BIT 5
1026	/** Bit 16 - WP - Write Protect (486+). */
1027	#define X86_CR0_WP RT_BIT_32(16)
1028	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
1029	#define X86_CR0_WP_BIT 16
1030	/** Bit 18 - AM - Alignment Mask (486+). */
1031	#define X86_CR0_AM RT_BIT_32(18)
1032	#define X86_CR0_ALIGNMENT_MASK RT_BIT_32(18)
1033	#define X86_CR0_AM_BIT 18
1034	/** Bit 29 - NW - Not Write-though (486+). */
1035	#define X86_CR0_NW RT_BIT_32(29)
1036	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
1037	#define X86_CR0_NW_BIT 29
1038	/** Bit 30 - WP - Cache Disable (486+). */
1039	#define X86_CR0_CD RT_BIT_32(30)
1040	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
1041	#define X86_CR0_CD_BIT 30
1042	/** Bit 31 - PG - Paging. */
1043	#define X86_CR0_PG RT_BIT_32(31)
1044	#define X86_CR0_PAGING RT_BIT_32(31)
1045	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
1046	/** @} */
1047
1048
1049	/** @name CR3
1050	* @{ */
1051	/** Bit 3 - PWT - Page-level Writes Transparent. */
1052	#define X86_CR3_PWT RT_BIT_32(3)
1053	#define X86_CR3_PWT_BIT 3
1054	/** Bit 4 - PCD - Page-level Cache Disable. */
1055	#define X86_CR3_PCD RT_BIT_32(4)
1056	#define X86_CR3_PCD_BIT 4
1057	/** Bits 12-31 - - Page directory page number. */
1058	#define X86_CR3_PAGE_MASK (0xfffff000)
1059	/** Bits 5-31 - - PAE Page directory page number. */
1060	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1061	/** Bits 12-51 - - AMD64 PML4 page number.
1062	* @note This is a maxed out mask, the actual acceptable CR3 value can
1063	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1064	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1065	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1066	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1067	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1068	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1069	/** @} */
1070
1071
1072	/** @name CR4
1073	* @{ */
1074	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1075	#define X86_CR4_VME RT_BIT_32(0)
1076	#define X86_CR4_VME_BIT 0
1077	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1078	#define X86_CR4_PVI RT_BIT_32(1)
1079	#define X86_CR4_PVI_BIT 1
1080	/** Bit 2 - TSD - Time Stamp Disable. */
1081	#define X86_CR4_TSD RT_BIT_32(2)
1082	#define X86_CR4_TSD_BIT 2
1083	/** Bit 3 - DE - Debugging Extensions. */
1084	#define X86_CR4_DE RT_BIT_32(3)
1085	#define X86_CR4_DE_BIT 3
1086	/** Bit 4 - PSE - Page Size Extension. */
1087	#define X86_CR4_PSE RT_BIT_32(4)
1088	#define X86_CR4_PSE_BIT 4
1089	/** Bit 5 - PAE - Physical Address Extension. */
1090	#define X86_CR4_PAE RT_BIT_32(5)
1091	#define X86_CR4_PAE_BIT 5
1092	/** Bit 6 - MCE - Machine-Check Enable. */
1093	#define X86_CR4_MCE RT_BIT_32(6)
1094	#define X86_CR4_MCE_BIT 6
1095	/** Bit 7 - PGE - Page Global Enable. */
1096	#define X86_CR4_PGE RT_BIT_32(7)
1097	#define X86_CR4_PGE_BIT 7
1098	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1099	#define X86_CR4_PCE RT_BIT_32(8)
1100	#define X86_CR4_PCE_BIT 8
1101	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1102	#define X86_CR4_OSFXSR RT_BIT_32(9)
1103	#define X86_CR4_OSFXSR_BIT 9
1104	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1105	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1106	#define X86_CR4_OSXMMEEXCPT_BIT 10
1107	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1108	#define X86_CR4_UMIP RT_BIT_32(11)
1109	#define X86_CR4_UMIP_BIT 11
1110	/** Bit 13 - VMXE - VMX mode is enabled. */
1111	#define X86_CR4_VMXE RT_BIT_32(13)
1112	#define X86_CR4_VMXE_BIT 13
1113	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1114	#define X86_CR4_SMXE RT_BIT_32(14)
1115	#define X86_CR4_SMXE_BIT 14
1116	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1117	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1118	#define X86_CR4_FSGSBASE_BIT 16
1119	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1120	#define X86_CR4_PCIDE RT_BIT_32(17)
1121	#define X86_CR4_PCIDE_BIT 17
1122	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1123	* extended states. */
1124	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1125	#define X86_CR4_OSXSAVE_BIT 18
1126	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1127	#define X86_CR4_SMEP RT_BIT_32(20)
1128	#define X86_CR4_SMEP_BIt 20
1129	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1130	#define X86_CR4_SMAP RT_BIT_32(21)
1131	#define X86_CR4_SMAP_BIT 21
1132	/** Bit 22 - PKE - Protection Key Enable. */
1133	#define X86_CR4_PKE RT_BIT_32(22)
1134	#define X86_CR4_PKE_BIT 22
1135	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1136	#define X86_CR4_CET RT_BIT_32(23)
1137	#define X86_CR4_CET_BIT 23
1138	/** @} */
1139
1140
1141	/** @name DR6
1142	* @{ */
1143	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1144	#define X86_DR6_B0 RT_BIT_32(0)
1145	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1146	#define X86_DR6_B1 RT_BIT_32(1)
1147	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1148	#define X86_DR6_B2 RT_BIT_32(2)
1149	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1150	#define X86_DR6_B3 RT_BIT_32(3)
1151	/** Mask of all the Bx bits. */
1152	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1153	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1154	#define X86_DR6_BD RT_BIT_32(13)
1155	/** Bit 14 - BS - Single step */
1156	#define X86_DR6_BS RT_BIT_32(14)
1157	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1158	#define X86_DR6_BT RT_BIT_32(15)
1159	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1160	#define X86_DR6_RTM RT_BIT_32(16)
1161	/** Value of DR6 after powerup/reset. */
1162	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1163	/** Bits which must be 1s in DR6. */
1164	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1165	/** Bits which must be 1s in DR6, when RTM is supported. */
1166	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1167	/** Bits which must be 0s in DR6. */
1168	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1169	/** Bits which must be 0s on writes to DR6. */
1170	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1171	/** @} */
1172
1173	/** Get the DR6.Bx bit for a the given breakpoint. */
1174	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1175
1176
1177	/** @name DR7
1178	* @{ */
1179	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1180	#define X86_DR7_L0 RT_BIT_32(0)
1181	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1182	#define X86_DR7_G0 RT_BIT_32(1)
1183	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1184	#define X86_DR7_L1 RT_BIT_32(2)
1185	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1186	#define X86_DR7_G1 RT_BIT_32(3)
1187	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1188	#define X86_DR7_L2 RT_BIT_32(4)
1189	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1190	#define X86_DR7_G2 RT_BIT_32(5)
1191	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1192	#define X86_DR7_L3 RT_BIT_32(6)
1193	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1194	#define X86_DR7_G3 RT_BIT_32(7)
1195	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1196	#define X86_DR7_LE RT_BIT_32(8)
1197	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1198	#define X86_DR7_GE RT_BIT_32(9)
1199
1200	/** L0, L1, L2, and L3. */
1201	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1202	/** L0, L1, L2, and L3. */
1203	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1204
1205	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1206	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1207	#define X86_DR7_RTM RT_BIT_32(11)
1208	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1209	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1210	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1211	* instruction is executed.
1212	* @see http://www.rcollins.org/secrets/DR7.html */
1213	#define X86_DR7_ICE_IR RT_BIT_32(12)
1214	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1215	* any DR register is accessed. */
1216	#define X86_DR7_GD RT_BIT_32(13)
1217	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1218	* Pentium. */
1219	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1220	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1221	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1222	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1223	#define X86_DR7_RW0_MASK (3 << 16)
1224	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1225	#define X86_DR7_LEN0_MASK (3 << 18)
1226	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1227	#define X86_DR7_RW1_MASK (3 << 20)
1228	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1229	#define X86_DR7_LEN1_MASK (3 << 22)
1230	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1231	#define X86_DR7_RW2_MASK (3 << 24)
1232	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1233	#define X86_DR7_LEN2_MASK (3 << 26)
1234	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1235	#define X86_DR7_RW3_MASK (3 << 28)
1236	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1237	#define X86_DR7_LEN3_MASK (3 << 30)
1238
1239	/** Bits which reads as 1s. */
1240	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1241	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1242	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1243	/** Bits which must be 0s when writing to DR7. */
1244	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1245
1246	/** Calcs the L bit of Nth breakpoint.
1247	* @param iBp The breakpoint number [0..3].
1248	*/
1249	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1250
1251	/** Calcs the G bit of Nth breakpoint.
1252	* @param iBp The breakpoint number [0..3].
1253	*/
1254	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1255
1256	/** Calcs the L and G bits of Nth breakpoint.
1257	* @param iBp The breakpoint number [0..3].
1258	*/
1259	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1260
1261	/** @name Read/Write values.
1262	* @{ */
1263	/** Break on instruction fetch only. */
1264	#define X86_DR7_RW_EO UINT32_C(0)
1265	/** Break on write only. */
1266	#define X86_DR7_RW_WO UINT32_C(1)
1267	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1268	#define X86_DR7_RW_IO UINT32_C(2)
1269	/** Break on read or write (but not instruction fetches). */
1270	#define X86_DR7_RW_RW UINT32_C(3)
1271	/** @} */
1272
1273	/** Shifts a X86_DR7_RW_* value to its right place.
1274	* @param iBp The breakpoint number [0..3].
1275	* @param fRw One of the X86_DR7_RW_* value.
1276	*/
1277	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1278
1279	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1280	* one of the X86_DR7_RW_XXX constants).
1281	*
1282	* @returns X86_DR7_RW_XXX
1283	* @param uDR7 DR7 value
1284	* @param iBp The breakpoint number [0..3].
1285	*/
1286	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1287
1288	/** R/W0, R/W1, R/W2, and R/W3. */
1289	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1290
1291	#ifndef VBOX_FOR_DTRACE_LIB
1292	/** Checks if the RW and LEN fields are set up for an instruction breakpoint.
1293	* @note This does not check if it's enabled. */
1294	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1295	/** Checks if an instruction breakpoint is enabled and configured correctly.
1296	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1297	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1298	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1299	/** Checks if there are any instruction fetch breakpoint types configured in
1300	* the RW and LEN registers and enabled in the Lx/Gx bits.
1301	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1302	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1303	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1304	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1305	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1306	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1307
1308	/** Checks if the RW field is set up for a read-write data breakpoint.
1309	* @note This does not check if it's enabled. */
1310	# define X86_DR7_IS_RW_CFG(a_uDR7, a_iBp) ( ~((a_uDR7) & (UINT32_C(0x00030000) << ((a_iBp) * 4))) == 0)
1311
1312	/** Checks if there are any read-write data breakpoint types configured in the
1313	* RW registers and enabled in the Lx/Gx bits.
1314	*
1315	* @note We don't consider the LEN registers here, even if qword isn't
1316	* techincally valid for older processors - see
1317	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1318	*/
1319	# define X86_DR7_ANY_RW_ENABLED(a_uDR7) \
1320	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00030000)) == UINT32_C(0x00030000)) \
1321	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00300000)) == UINT32_C(0x00300000)) \
1322	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x03000000)) == UINT32_C(0x03000000)) \
1323	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x30000000)) == UINT32_C(0x30000000)) )
1324
1325	/** Checks if the RW field is set up for a write-only or read-write data
1326	* breakpoint.
1327	* @note This does not check if it's enabled. */
1328	# define X86_DR7_IS_W_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x00010000) << ((a_iBp) * 4))) != 0)
1329
1330	/** Checks if there are any read-write or write-only data breakpoint types
1331	* configured in the the RW registers and enabled in the Lx/Gx bits.
1332	*
1333	* @note We don't consider the LEN registers here, even if qword isn't
1334	* techincally valid for older processors - see
1335	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1336	*/
1337	# define X86_DR7_ANY_W_ENABLED(a_uDR7) \
1338	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00010000)) != 0) \
1339	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00100000)) != 0) \
1340	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x01000000)) != 0) \
1341	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x10000000)) != 0) )
1342
1343	/** Checks if there are any I/O breakpoint types configured in the RW
1344	* registers. Does NOT check if these are enabled, sorry. */
1345	# define X86_DR7_ANY_RW_IO(uDR7) \
1346	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1347	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1348	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1349	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1350	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1351	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1352	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1353	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1354	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1355	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1356	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1357
1358	#endif /* !VBOX_FOR_DTRACE_LIB */
1359
1360	/** @name Length values.
1361	* @{ */
1362	#define X86_DR7_LEN_BYTE UINT32_C(0)
1363	#define X86_DR7_LEN_WORD UINT32_C(1)
1364	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1365	#define X86_DR7_LEN_DWORD UINT32_C(3)
1366	/** @} */
1367
1368	/** Shifts a X86_DR7_LEN_* value to its right place.
1369	* @param iBp The breakpoint number [0..3].
1370	* @param cb One of the X86_DR7_LEN_* values.
1371	*/
1372	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1373
1374	/** Fetch the breakpoint length bits from the DR7 value.
1375	* @param uDR7 DR7 value
1376	* @param iBp The breakpoint number [0..3].
1377	*/
1378	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1379
1380	/** Mask used to check if any breakpoints are enabled. */
1381	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1382
1383	/** LEN0, LEN1, LEN2, and LEN3. */
1384	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1385	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1386	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1387
1388	/** Value of DR7 after powerup/reset. */
1389	#define X86_DR7_INIT_VAL 0x400
1390	/** @} */
1391
1392
1393	/** @name Machine Specific Registers
1394	* @{
1395	*/
1396	/** Machine check address register (P5). */
1397	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1398	/** Machine check type register (P5). */
1399	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1400	/** Time Stamp Counter. */
1401	#define MSR_IA32_TSC 0x10
1402	#define MSR_IA32_CESR UINT32_C(0x00000011)
1403	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1404	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1405
1406	#define MSR_IA32_PLATFORM_ID 0x17
1407
1408	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1409	# define MSR_IA32_APICBASE 0x1b
1410	/** Local APIC enabled. */
1411	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1412	/** X2APIC enabled (requires the EN bit to be set). */
1413	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1414	/** The processor is the boot strap processor (BSP). */
1415	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1416	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1417	* width. */
1418	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1419	/** The default physical base address of the APIC. */
1420	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1421	/** Gets the physical base address from the MSR. */
1422	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1423	#endif
1424
1425	/** Memory Control (Intel-specific). */
1426	#define MSR_MEMORY_CTRL 0x33
1427	/** Memory Control - UC-store throttle. */
1428	#define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
1429	/** Memory Control - UC-lock disable. */
1430	#define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
1431	/** Memory Control - Split-lock disable. */
1432	#define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
1433
1434	/** Undocumented intel MSR for reporting thread and core counts.
1435	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1436	* first 16 bits is the thread count. The next 16 bits the core count, except
1437	* on Westmere where it seems it's only the next 4 bits for some reason. */
1438	#define MSR_CORE_THREAD_COUNT 0x35
1439
1440	/** CPU Feature control. */
1441	#define MSR_IA32_FEATURE_CONTROL 0x3A
1442	/** Feature control - Lock MSR from writes (R/W0). */
1443	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1444	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1445	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1446	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1447	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1448	/** Feature control - SENTER local functions enable (R/WL). */
1449	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1450	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1451	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1452	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1453	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1454	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1455	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1456	/** Feature control - SENTER global enable (R/WL). */
1457	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1458	/** Feature control - SGX launch control enable (R/WL). */
1459	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1460	/** Feature control - SGX global enable (R/WL). */
1461	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1462	/** Feature control - LMCE on (R/WL). */
1463	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1464
1465	/** Per-processor TSC adjust MSR. */
1466	#define MSR_IA32_TSC_ADJUST 0x3B
1467
1468	/** Spectre control register.
1469	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1470	#define MSR_IA32_SPEC_CTRL 0x48
1471	/** @name MSR_IA32_SPEC_CTRL bits
1472	* @{ */
1473	/** IBRS - Indirect branch restricted speculation. */
1474	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_64(0)
1475	/** STIBP - Single thread indirect branch predictors. */
1476	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_64(1)
1477	/** SSBD - Speculative Store Bypass Disable. */
1478	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_64(2)
1479	#define MSR_IA32_SPEC_CTRL_F_IPRED_DIS_U RT_BIT_64(3)
1480	#define MSR_IA32_SPEC_CTRL_F_IPRED_DIS_S RT_BIT_64(4)
1481	#define MSR_IA32_SPEC_CTRL_F_RRSBA_DIS_U RT_BIT_64(5)
1482	#define MSR_IA32_SPEC_CTRL_F_RRSBA_DIS_S RT_BIT_64(6)
1483	#define MSR_IA32_SPEC_CTRL_F_PSFD RT_BIT_64(7)
1484	#define MSR_IA32_SPEC_CTRL_F_DDPD_U RT_BIT_64(8)
1485	/* 9 is reserved (for DDPD_S?) */
1486	#define MSR_IA32_SPEC_CTRL_F_BHI_DIS_S RT_BIT_64(10)
1487	/** @} */
1488
1489	/** Prediction command register.
1490	* Write only, logical processor scope, no state since write only. */
1491	#define MSR_IA32_PRED_CMD 0x49
1492	/** IBPB - Indirect branch prediction barrie when written as 1. */
1493	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_64(0)
1494
1495	/** BIOS update trigger (microcode update). */
1496	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1497
1498	/** BIOS update signature (microcode). */
1499	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1500
1501	/** SMM monitor control. */
1502	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1503	/** SMM control - Valid. */
1504	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1505	/** SMM control - VMXOFF unblocks SMI. */
1506	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1507	/** SMM control - MSEG base physical address. */
1508	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1509
1510	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1511	#define MSR_IA32_SMBASE 0x9E
1512
1513	/** General performance counter no. 0. */
1514	#define MSR_IA32_PMC0 0xC1
1515	/** General performance counter no. 1. */
1516	#define MSR_IA32_PMC1 0xC2
1517	/** General performance counter no. 2. */
1518	#define MSR_IA32_PMC2 0xC3
1519	/** General performance counter no. 3. */
1520	#define MSR_IA32_PMC3 0xC4
1521	/** General performance counter no. 4. */
1522	#define MSR_IA32_PMC4 0xC5
1523	/** General performance counter no. 5. */
1524	#define MSR_IA32_PMC5 0xC6
1525	/** General performance counter no. 6. */
1526	#define MSR_IA32_PMC6 0xC7
1527	/** General performance counter no. 7. */
1528	#define MSR_IA32_PMC7 0xC8
1529
1530	/** Nehalem power control. */
1531	#define MSR_IA32_PLATFORM_INFO 0xCE
1532
1533	/** Core Capabilities (Intel-specific). */
1534	#define MSR_IA32_CORE_CAPABILITIES 0xCF
1535	/** STLB QoS feature supported. */
1536	#define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
1537	/** FUSA feature supported. */
1538	#define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
1539	/** RSM instruction only allowed in CPL 0. */
1540	#define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
1541	/** UC lock disable supported. */
1542	#define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
1543	/** Split-lock disable supported. */
1544	#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
1545	/** Snoop filter QoS Mask MSRs supported. */
1546	#define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
1547	/** UC store throttling supported. */
1548	#define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
1549
1550	/** Get FSB clock status (Intel-specific). */
1551	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1552
1553	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1554	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1555
1556	/** C0 Maximum Frequency Clock Count */
1557	#define MSR_IA32_MPERF 0xE7
1558	/** C0 Actual Frequency Clock Count */
1559	#define MSR_IA32_APERF 0xE8
1560
1561	/** MTRR Capabilities. */
1562	#define MSR_IA32_MTRR_CAP 0xFE
1563	/** Bits 0-7 - VCNT - Variable range registers count. */
1564	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1565	/** Bit 8 - FIX - Fixed range registers supported. */
1566	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1567	/** Bit 10 - WC - Write-Combining memory type supported. */
1568	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1569	/** Bit 11 - SMRR - System Management Range Register supported. */
1570	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1571	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1572	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1573
1574
1575	#ifndef __ASSEMBLER__
1576	/**
1577	* Variable-range MTRR MSR pair.
1578	*/
1579	typedef struct X86MTRRVAR
1580	{
1581	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1582	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1583	} X86MTRRVAR;
1584	# ifndef VBOX_FOR_DTRACE_LIB
1585	AssertCompileSize(X86MTRRVAR, 16);
1586	# endif
1587	/** Pointer to a variable-range MTRR MSR pair. */
1588	typedef X86MTRRVAR *PX86MTRRVAR;
1589	/** Pointer to a const variable-range MTRR MSR pair. */
1590	typedef const X86MTRRVAR *PCX86MTRRVAR;
1591	#endif /* __ASSEMBLER__ */
1592
1593
1594	/** Memory types that can be encoded in MTRRs.
1595	* @{ */
1596	/** Uncacheable. */
1597	#define X86_MTRR_MT_UC 0
1598	/** Write Combining. */
1599	#define X86_MTRR_MT_WC 1
1600	/** Write-through. */
1601	#define X86_MTRR_MT_WT 4
1602	/** Write-protected. */
1603	#define X86_MTRR_MT_WP 5
1604	/** Writeback. */
1605	#define X86_MTRR_MT_WB 6
1606	/** @}*/
1607
1608	/** Architecture capabilities (bugfixes). */
1609	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1610	/** @name MSR_IA32_ARCH_CAPABILITIES bits
1611	* @{ */
1612	/** CPU is no subject to meltdown problems. */
1613	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_64(0)
1614	/** CPU has better IBRS and you can leave it on all the time. */
1615	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_64(1)
1616	/** CPU has return stack buffer (RSB) override. */
1617	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_64(2)
1618	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1619	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1620	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_64(3)
1621	/** CPU does not suffer from speculative store bypass (SSB) issues. */
1622	#define MSR_IA32_ARCH_CAP_F_SSB_NO RT_BIT_64(4)
1623	/** CPU does not suffer from microarchitectural data sampling (MDS) issues. */
1624	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_64(5)
1625	/** CPU does not suffer MCE after change code page size w/o invlpg issues. */
1626	#define MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO RT_BIT_64(6)
1627	/** CPU has RTM_DISABLE and TXS_CPUID_CLEAR support. */
1628	#define MSR_IA32_ARCH_CAP_F_TSX_CTRL RT_BIT_64(7)
1629	/** CPU does not suffer from transaction synchronization extensions (TSX)
1630	* asyncrhonous abort (TAA) issues. */
1631	#define MSR_IA32_ARCH_CAP_F_TAA_NO RT_BIT_64(8)
1632	/* 9 is 'reserved' */
1633	#define MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS RT_BIT_64(10)
1634	#define MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL RT_BIT_64(11)
1635	#define MSR_IA32_ARCH_CAP_F_DOITM RT_BIT_64(12)
1636	#define MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO RT_BIT_64(13)
1637	#define MSR_IA32_ARCH_CAP_F_FBSDP_NO RT_BIT_64(14)
1638	#define MSR_IA32_ARCH_CAP_F_PSDP_NO RT_BIT_64(15)
1639	/* 16 is 'reserved' */
1640	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR RT_BIT_64(17)
1641	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL RT_BIT_64(18)
1642	#define MSR_IA32_ARCH_CAP_F_RRSBA RT_BIT_64(19)
1643	#define MSR_IA32_ARCH_CAP_F_BHI_NO RT_BIT_64(20)
1644	#define MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS RT_BIT_64(21)
1645	/* 22 is 'reserved' */
1646	#define MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS RT_BIT_64(23)
1647	#define MSR_IA32_ARCH_CAP_F_PBRSB_NO RT_BIT_64(24)
1648	#define MSR_IA32_ARCH_CAP_F_GDS_CTRL RT_BIT_64(25)
1649	#define MSR_IA32_ARCH_CAP_F_GDS_NO RT_BIT_64(26)
1650	#define MSR_IA32_ARCH_CAP_F_RFDS_NO RT_BIT_64(27)
1651	#define MSR_IA32_ARCH_CAP_F_RFDS_CLEAR RT_BIT_64(28)
1652	#define MSR_IA32_ARCH_CAP_F_IGN_UMONITOR_SUPPORT RT_BIT_64(29)
1653	#define MSR_IA32_ARCH_CAP_F_MON_UMON_MITIG_SUPPORT RT_BIT_64(30)
1654	/** @} */
1655
1656	/** Flush command register. */
1657	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1658	/** Flush the level 1 data cache when this bit is written. */
1659	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_64(0)
1660
1661	/** Cache control/info. */
1662	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1663
1664	/** Microcode Update Option Control (R/W). */
1665	#define MSR_IA32_MCU_OPT_CTRL 0x123
1666	/** MSR_IA32_MCU_OPT_CTRL[0]: RNGDS_MITG_DIS - disable SRBDS mitigations
1667	* for RDRAND & RDSEED when set. */
1668	#define MSR_IA32_MCU_OPT_CTRL_RNGDS_MITG_DIS RT_BIT_64(0)
1669	/** MSR_IA32_MCU_OPT_CTRL[1]: RTM_ALLOW - Allow TXS according to IA32_TSX_CTRL. */
1670	#define MSR_IA32_MCU_OPT_CTRL_RTM_ALLOW RT_BIT_64(1)
1671	/** MSR_IA32_MCU_OPT_CTRL[2]: RTM_LOCKED - Lock RTM_ALLOW at zero. */
1672	#define MSR_IA32_MCU_OPT_CTRL_RTM_LOCKED RT_BIT_64(2)
1673	/** MSR_IA32_MCU_OPT_CTRL[3]: FB_CLEAR_DIS - Disables FB_CLEAR part of VERW. */
1674	#define MSR_IA32_MCU_OPT_CTRL_FB_CLEAR_DIS RT_BIT_64(3)
1675	/** MSR_IA32_MCU_OPT_CTRL[4]: GDS_MITG_DIS - Disables GDS mitigation on core. */
1676	#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_DIS RT_BIT_64(4)
1677	/** MSR_IA32_MCU_OPT_CTRL[5]: GDS_MITG_DIS - Disables GDS mitigation on core. */
1678	#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_LOCK RT_BIT_64(5)
1679	/** MSR_IA32_MCU_OPT_CTRL[6]: IGN_UMONITOR - Ignore UMONITOR & fail UMWAIT. */
1680	#define MSR_IA32_MCU_OPT_CTRL_IGN_UMONITOR RT_BIT_64(6)
1681	/** MSR_IA32_MCU_OPT_CTRL[7]: MON_UMON_MITG - UMONITOR/MONITOR mitigation
1682	* (may affect sibling hyperthreads). */
1683	#define MSR_IA32_MCU_OPT_CTRL_MON_UMON_MITG RT_BIT_64(7)
1684	/* Bits 63:7 reserved. */
1685	#define MSR_IA32_MCU_OPT_CTRL_RSVD_MASK UINT64_C(0xffffffffffffff80)
1686
1687	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1688	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1689	* R0 SS == CS + 8
1690	* R3 CS == CS + 16
1691	* R3 SS == CS + 24
1692	*/
1693	#define MSR_IA32_SYSENTER_CS 0x174
1694	/** SYSENTER_ESP - the R0 ESP. */
1695	#define MSR_IA32_SYSENTER_ESP 0x175
1696	/** SYSENTER_EIP - the R0 EIP. */
1697	#define MSR_IA32_SYSENTER_EIP 0x176
1698	#endif
1699
1700	/** Machine Check Global Capabilities Register. */
1701	#define MSR_IA32_MCG_CAP 0x179
1702	/** Machine Check Global Status Register. */
1703	#define MSR_IA32_MCG_STATUS 0x17A
1704	/** Machine Check Global Control Register. */
1705	#define MSR_IA32_MCG_CTRL 0x17B
1706
1707	/** Page Attribute Table. */
1708	#define MSR_IA32_CR_PAT 0x277
1709	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1710	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1711	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1712
1713	/** Memory types that can be encoded in the IA32_PAT MSR.
1714	* @{ */
1715	/** Uncacheable. */
1716	#define MSR_IA32_PAT_MT_UC 0
1717	/** Write Combining. */
1718	#define MSR_IA32_PAT_MT_WC 1
1719	/** Reserved value 2. */
1720	#define MSR_IA32_PAT_MT_RSVD_2 2
1721	/** Reserved value 3. */
1722	#define MSR_IA32_PAT_MT_RSVD_3 3
1723	/** Write-through. */
1724	#define MSR_IA32_PAT_MT_WT 4
1725	/** Write-protected. */
1726	#define MSR_IA32_PAT_MT_WP 5
1727	/** Writeback. */
1728	#define MSR_IA32_PAT_MT_WB 6
1729	/** Uncached (UC-). */
1730	#define MSR_IA32_PAT_MT_UCD 7
1731	/** @}*/
1732
1733
1734	/** Performance event select MSRs. (Intel only) */
1735	#define MSR_IA32_PERFEVTSEL0 0x186
1736	#define MSR_IA32_PERFEVTSEL1 0x187
1737	#define MSR_IA32_PERFEVTSEL2 0x188
1738	#define MSR_IA32_PERFEVTSEL3 0x189
1739
1740	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1741	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1742	* holds a ratio that Apple takes for TSC granularity.
1743	*
1744	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1745	#define MSR_FLEX_RATIO 0x194
1746	/** Performance state value and starting with Intel core more.
1747	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1748	#define MSR_IA32_PERF_STATUS 0x198
1749	#define MSR_IA32_PERF_CTL 0x199
1750	#define MSR_IA32_THERM_STATUS 0x19c
1751
1752	/** Offcore response event select registers. */
1753	#define MSR_OFFCORE_RSP_0 0x1a6
1754	#define MSR_OFFCORE_RSP_1 0x1a7
1755
1756	/** Enable misc. processor features (R/W). */
1757	#define MSR_IA32_MISC_ENABLE 0x1A0
1758	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1759	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1760	/** Automatic Thermal Control Circuit Enable (R/W). */
1761	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1762	/** Performance Monitoring Available (R). */
1763	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1764	/** Branch Trace Storage Unavailable (R/O). */
1765	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1766	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1767	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1768	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1769	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1770	/** If MONITOR/MWAIT is supported (R/W). */
1771	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1772	/** Limit CPUID Maxval to 3 leafs (R/W). */
1773	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1774	/** When set to 1, xTPR messages are disabled (R/W). */
1775	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1776	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1777	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1778
1779	/** Trace/Profile Resource Control (R/W) */
1780	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1781	/** Last branch record. */
1782	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1783	/** Branch trace flag (single step on branches). */
1784	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1785	/** Performance monitoring pin control (AMD only). */
1786	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1787	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1788	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1789	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1790	/** Trace message enable (Intel only). */
1791	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1792	/** Branch trace store (Intel only). */
1793	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1794	/** Branch trace interrupt (Intel only). */
1795	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1796	/** Branch trace off in privileged code (Intel only). */
1797	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1798	/** Branch trace off in user code (Intel only). */
1799	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1800	/** Freeze LBR on PMI flag (Intel only). */
1801	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1802	/** Freeze PERFMON on PMI flag (Intel only). */
1803	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1804	/** Freeze while SMM enabled (Intel only). */
1805	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1806	/** Advanced debugging of RTM regions (Intel only). */
1807	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1808	/** Debug control MSR valid bits (Intel only). */
1809	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1810	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1811	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1812	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1813	\| MSR_IA32_DEBUGCTL_RTM)
1814
1815	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1816	* @{ */
1817	#define MSR_P4_LASTBRANCH_0 0x1db
1818	#define MSR_P4_LASTBRANCH_1 0x1dc
1819	#define MSR_P4_LASTBRANCH_2 0x1dd
1820	#define MSR_P4_LASTBRANCH_3 0x1de
1821
1822	/** LBR Top-of-stack MSR (index to most recent record). */
1823	#define MSR_P4_LASTBRANCH_TOS 0x1da
1824	/** @} */
1825
1826	/** @name Last branch registers for Core 2 and related Xeons.
1827	* @{ */
1828	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1829	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1830	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1831	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1832
1833	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1834	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1835	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1836	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1837
1838	/** LBR Top-of-stack MSR (index to most recent record). */
1839	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1840	/** @} */
1841
1842	/** @name Last branch registers.
1843	* @{ */
1844	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1845	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1846	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1847	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1848	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1849	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1850	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1851	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1852	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1853	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1854	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1855	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1856	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1857	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1858	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1859	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1860	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1861	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1862	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1863	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1864	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1865	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1866	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1867	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1868	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1869	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1870	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1871	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1872	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1873	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1874	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1875	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1876
1877	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1878	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1879	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1880	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1881	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1882	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1883	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1884	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1885	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1886	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1887	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1888	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1889	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1890	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1891	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1892	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1893	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1894	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1895	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1896	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1897	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1898	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1899	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1900	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1901	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1902	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1903	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1904	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1905	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1906	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1907	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1908	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1909
1910	#define MSR_LASTBRANCH_0_INFO 0xdc0
1911	#define MSR_LASTBRANCH_1_INFO 0xdc1
1912	#define MSR_LASTBRANCH_2_INFO 0xdc2
1913	#define MSR_LASTBRANCH_3_INFO 0xdc3
1914	#define MSR_LASTBRANCH_4_INFO 0xdc4
1915	#define MSR_LASTBRANCH_5_INFO 0xdc5
1916	#define MSR_LASTBRANCH_6_INFO 0xdc6
1917	#define MSR_LASTBRANCH_7_INFO 0xdc7
1918	#define MSR_LASTBRANCH_8_INFO 0xdc8
1919	#define MSR_LASTBRANCH_9_INFO 0xdc9
1920	#define MSR_LASTBRANCH_10_INFO 0xdca
1921	#define MSR_LASTBRANCH_11_INFO 0xdcb
1922	#define MSR_LASTBRANCH_12_INFO 0xdcc
1923	#define MSR_LASTBRANCH_13_INFO 0xdcd
1924	#define MSR_LASTBRANCH_14_INFO 0xdce
1925	#define MSR_LASTBRANCH_15_INFO 0xdcf
1926	#define MSR_LASTBRANCH_16_INFO 0xdd0
1927	#define MSR_LASTBRANCH_17_INFO 0xdd1
1928	#define MSR_LASTBRANCH_18_INFO 0xdd2
1929	#define MSR_LASTBRANCH_19_INFO 0xdd3
1930	#define MSR_LASTBRANCH_20_INFO 0xdd4
1931	#define MSR_LASTBRANCH_21_INFO 0xdd5
1932	#define MSR_LASTBRANCH_22_INFO 0xdd6
1933	#define MSR_LASTBRANCH_23_INFO 0xdd7
1934	#define MSR_LASTBRANCH_24_INFO 0xdd8
1935	#define MSR_LASTBRANCH_25_INFO 0xdd9
1936	#define MSR_LASTBRANCH_26_INFO 0xdda
1937	#define MSR_LASTBRANCH_27_INFO 0xddb
1938	#define MSR_LASTBRANCH_28_INFO 0xddc
1939	#define MSR_LASTBRANCH_29_INFO 0xddd
1940	#define MSR_LASTBRANCH_30_INFO 0xdde
1941	#define MSR_LASTBRANCH_31_INFO 0xddf
1942
1943	/** LBR branch tracking selection MSR. */
1944	#define MSR_LASTBRANCH_SELECT 0x1c8
1945	/** LBR Top-of-stack MSR (index to most recent record). */
1946	#define MSR_LASTBRANCH_TOS 0x1c9
1947	/** @} */
1948
1949	/** @name Last event record registers.
1950	* @{ */
1951	/** Last event record source IP register. */
1952	#define MSR_LER_FROM_IP 0x1dd
1953	/** Last event record destination IP register. */
1954	#define MSR_LER_TO_IP 0x1de
1955	/** @} */
1956
1957	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1958	#define MSR_IA32_TSX_CTRL 0x122
1959
1960	/** Variable range MTRRs.
1961	* @{ */
1962	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1963	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1964	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1965	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1966	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1967	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1968	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1969	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1970	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1971	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1972	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1973	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1974	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1975	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1976	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1977	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1978	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1979	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1980	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1981	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1982	/** @} */
1983
1984	/** Fixed range MTRRs.
1985	* @{ */
1986	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1987	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1988	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1989	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1990	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1991	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1992	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1993	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1994	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1995	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1996	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1997	/** @} */
1998
1999	/** MTRR Default Type.
2000	* @{ */
2001	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
2002	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
2003	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
2004	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
2005	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
2006	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
2007	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
2008	/** @} */
2009
2010	/** Variable-range MTRR physical mask valid. */
2011	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
2012
2013	/** Variable-range MTRR memory type mask. */
2014	#define MSR_IA32_MTRR_PHYSBASE_MT_MASK UINT64_C(0xff)
2015
2016	/** Global performance counter control facilities (Intel only). */
2017	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
2018	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
2019	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
2020
2021	/** Precise Event Based sampling (Intel only). */
2022	#define MSR_IA32_PEBS_ENABLE 0x3F1
2023
2024	#define MSR_IA32_MC0_CTL 0x400
2025	#define MSR_IA32_MC0_STATUS 0x401
2026
2027	/** Basic VMX information. */
2028	#define MSR_IA32_VMX_BASIC 0x480
2029	/** Allowed settings for pin-based VM execution controls. */
2030	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
2031	/** Allowed settings for proc-based VM execution controls. */
2032	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
2033	/** Allowed settings for the VM-exit controls. */
2034	#define MSR_IA32_VMX_EXIT_CTLS 0x483
2035	/** Allowed settings for the VM-entry controls. */
2036	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
2037	/** Misc VMX info. */
2038	#define MSR_IA32_VMX_MISC 0x485
2039	/** Fixed cleared bits in CR0. */
2040	#define MSR_IA32_VMX_CR0_FIXED0 0x486
2041	/** Fixed set bits in CR0. */
2042	#define MSR_IA32_VMX_CR0_FIXED1 0x487
2043	/** Fixed cleared bits in CR4. */
2044	#define MSR_IA32_VMX_CR4_FIXED0 0x488
2045	/** Fixed set bits in CR4. */
2046	#define MSR_IA32_VMX_CR4_FIXED1 0x489
2047	/** Information for enumerating fields in the VMCS. */
2048	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
2049	/** Allowed settings for secondary processor-based VM-execution controls. */
2050	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
2051	/** EPT capabilities. */
2052	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
2053	/** Allowed settings of all pin-based VM execution controls. */
2054	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
2055	/** Allowed settings of all proc-based VM execution controls. */
2056	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
2057	/** Allowed settings of all VMX exit controls. */
2058	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
2059	/** Allowed settings of all VMX entry controls. */
2060	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
2061	/** Allowed settings for the VM-function controls. */
2062	#define MSR_IA32_VMX_VMFUNC 0x491
2063	/** Tertiary processor-based VM execution controls. */
2064	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
2065	/** Secondary VM-exit controls. */
2066	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
2067
2068	/** Intel PT - Enable and control for trace packet generation. */
2069	#define MSR_IA32_RTIT_CTL 0x570
2070
2071	/** DS Save Area (R/W). */
2072	#define MSR_IA32_DS_AREA 0x600
2073	/** Running Average Power Limit (RAPL) power units. */
2074	#define MSR_RAPL_POWER_UNIT 0x606
2075	/** Package C3 Interrupt Response Limit. */
2076	#define MSR_PKGC3_IRTL 0x60a
2077	/** Package C6/C7S Interrupt Response Limit 1. */
2078	#define MSR_PKGC_IRTL1 0x60b
2079	/** Package C6/C7S Interrupt Response Limit 2. */
2080	#define MSR_PKGC_IRTL2 0x60c
2081	/** Package C2 Residency Counter. */
2082	#define MSR_PKG_C2_RESIDENCY 0x60d
2083	/** PKG RAPL Power Limit Control. */
2084	#define MSR_PKG_POWER_LIMIT 0x610
2085	/** PKG Energy Status. */
2086	#define MSR_PKG_ENERGY_STATUS 0x611
2087	/** PKG Perf Status. */
2088	#define MSR_PKG_PERF_STATUS 0x613
2089	/** PKG RAPL Parameters. */
2090	#define MSR_PKG_POWER_INFO 0x614
2091	/** DRAM RAPL Power Limit Control. */
2092	#define MSR_DRAM_POWER_LIMIT 0x618
2093	/** DRAM Energy Status. */
2094	#define MSR_DRAM_ENERGY_STATUS 0x619
2095	/** DRAM Performance Throttling Status. */
2096	#define MSR_DRAM_PERF_STATUS 0x61b
2097	/** DRAM RAPL Parameters. */
2098	#define MSR_DRAM_POWER_INFO 0x61c
2099	/** Package C10 Residency Counter. */
2100	#define MSR_PKG_C10_RESIDENCY 0x632
2101	/** PP0 Energy Status. */
2102	#define MSR_PP0_ENERGY_STATUS 0x639
2103	/** PP1 Energy Status. */
2104	#define MSR_PP1_ENERGY_STATUS 0x641
2105	/** Turbo Activation Ratio. */
2106	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
2107	/** Core Performance Limit Reasons. */
2108	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
2109
2110	/** Userspace Control flow Enforcement Technology setting. */
2111	#define MSR_IA32_U_CET 0x6a0
2112	/** Supervisor space Control flow Enforcement Technology setting. */
2113	#define MSR_IA32_S_CET 0x6a2
2114	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
2115	* @{ */
2116	/** Enables the Shadow stack. */
2117	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
2118	/** Enables WRSS{D,Q}W instructions. */
2119	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
2120	/** Enables indirect branch tracking. */
2121	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
2122	/** Enable legacy compatibility treatment for indirect branch tracking. */
2123	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
2124	/** Enables the use of no-track prefix for indirect branch tracking. */
2125	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
2126	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
2127	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
2128	/** Suppresses indirect branch tracking. */
2129	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
2130	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
2131	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
2132	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
2133	* on a ENDBRANCH instruction. */
2134	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
2135	/** @} */
2136
2137	/** X2APIC MSR range start. */
2138	#define MSR_IA32_X2APIC_START 0x800
2139	/** X2APIC MSR - APIC ID Register. */
2140	#define MSR_IA32_X2APIC_ID 0x802
2141	/** X2APIC MSR - APIC Version Register. */
2142	#define MSR_IA32_X2APIC_VERSION 0x803
2143	/** X2APIC MSR - Task Priority Register. */
2144	#define MSR_IA32_X2APIC_TPR 0x808
2145	/** X2APIC MSR - Processor Priority register. */
2146	#define MSR_IA32_X2APIC_PPR 0x80A
2147	/** X2APIC MSR - End Of Interrupt register. */
2148	#define MSR_IA32_X2APIC_EOI 0x80B
2149	/** X2APIC MSR - Logical Destination Register. */
2150	#define MSR_IA32_X2APIC_LDR 0x80D
2151	/** X2APIC MSR - Spurious Interrupt Vector Register. */
2152	#define MSR_IA32_X2APIC_SVR 0x80F
2153	/** X2APIC MSR - In-service Register (bits 31:0). */
2154	#define MSR_IA32_X2APIC_ISR0 0x810
2155	/** X2APIC MSR - In-service Register (bits 63:32). */
2156	#define MSR_IA32_X2APIC_ISR1 0x811
2157	/** X2APIC MSR - In-service Register (bits 95:64). */
2158	#define MSR_IA32_X2APIC_ISR2 0x812
2159	/** X2APIC MSR - In-service Register (bits 127:96). */
2160	#define MSR_IA32_X2APIC_ISR3 0x813
2161	/** X2APIC MSR - In-service Register (bits 159:128). */
2162	#define MSR_IA32_X2APIC_ISR4 0x814
2163	/** X2APIC MSR - In-service Register (bits 191:160). */
2164	#define MSR_IA32_X2APIC_ISR5 0x815
2165	/** X2APIC MSR - In-service Register (bits 223:192). */
2166	#define MSR_IA32_X2APIC_ISR6 0x816
2167	/** X2APIC MSR - In-service Register (bits 255:224). */
2168	#define MSR_IA32_X2APIC_ISR7 0x817
2169	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
2170	#define MSR_IA32_X2APIC_TMR0 0x818
2171	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
2172	#define MSR_IA32_X2APIC_TMR1 0x819
2173	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
2174	#define MSR_IA32_X2APIC_TMR2 0x81A
2175	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
2176	#define MSR_IA32_X2APIC_TMR3 0x81B
2177	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
2178	#define MSR_IA32_X2APIC_TMR4 0x81C
2179	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
2180	#define MSR_IA32_X2APIC_TMR5 0x81D
2181	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
2182	#define MSR_IA32_X2APIC_TMR6 0x81E
2183	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
2184	#define MSR_IA32_X2APIC_TMR7 0x81F
2185	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
2186	#define MSR_IA32_X2APIC_IRR0 0x820
2187	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
2188	#define MSR_IA32_X2APIC_IRR1 0x821
2189	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
2190	#define MSR_IA32_X2APIC_IRR2 0x822
2191	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
2192	#define MSR_IA32_X2APIC_IRR3 0x823
2193	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
2194	#define MSR_IA32_X2APIC_IRR4 0x824
2195	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
2196	#define MSR_IA32_X2APIC_IRR5 0x825
2197	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
2198	#define MSR_IA32_X2APIC_IRR6 0x826
2199	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
2200	#define MSR_IA32_X2APIC_IRR7 0x827
2201	/** X2APIC MSR - Error Status Register. */
2202	#define MSR_IA32_X2APIC_ESR 0x828
2203	/** X2APIC MSR - LVT CMCI Register. */
2204	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
2205	/** X2APIC MSR - Interrupt Command Register. */
2206	#define MSR_IA32_X2APIC_ICR 0x830
2207	/** X2APIC MSR - LVT Timer Register. */
2208	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
2209	/** X2APIC MSR - LVT Thermal Sensor Register. */
2210	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
2211	/** X2APIC MSR - LVT Performance Counter Register. */
2212	#define MSR_IA32_X2APIC_LVT_PERF 0x834
2213	/** X2APIC MSR - LVT LINT0 Register. */
2214	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2215	/** X2APIC MSR - LVT LINT1 Register. */
2216	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2217	/** X2APIC MSR - LVT Error Register . */
2218	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2219	/** X2APIC MSR - Timer Initial Count Register. */
2220	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2221	/** X2APIC MSR - Timer Current Count Register. */
2222	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2223	/** X2APIC MSR - Timer Divide Configuration Register. */
2224	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2225	/** X2APIC MSR - Self IPI. */
2226	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2227	/** X2APIC MSR range end. */
2228	#define MSR_IA32_X2APIC_END 0x8FF
2229	/** X2APIC MSR - LVT start range. */
2230	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2231	/** X2APIC MSR - LVT end range (inclusive). */
2232	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2233
2234	/** K6 EFER - Extended Feature Enable Register. */
2235	#define MSR_K6_EFER UINT32_C(0xc0000080)
2236	/** @todo document EFER */
2237	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2238	#define MSR_K6_EFER_SCE RT_BIT_32(0)
2239	/** Bit 8 - LME - Long mode enabled. (R/W) */
2240	#define MSR_K6_EFER_LME RT_BIT_32(8)
2241	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
2242	/** Bit 10 - LMA - Long mode active. (R) */
2243	#define MSR_K6_EFER_LMA RT_BIT_32(10)
2244	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
2245	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2246	#define MSR_K6_EFER_NXE RT_BIT_32(11)
2247	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
2248	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2249	#define MSR_K6_EFER_SVME RT_BIT_32(12)
2250	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2251	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2252	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
2253	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2254	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2255	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2256	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2257	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2258
2259	/** K6 STAR - SYSCALL/RET targets. */
2260	#define MSR_K6_STAR UINT32_C(0xc0000081)
2261	/** Shift value for getting the SYSRET CS and SS value. */
2262	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2263	/** Shift value for getting the SYSCALL CS and SS value. */
2264	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2265	/** Selector mask for use after shifting. */
2266	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2267	/** The mask which give the SYSCALL EIP. */
2268	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2269	/** K6 WHCR - Write Handling Control Register. */
2270	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2271	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2272	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2273	/** K6 PSOR - Processor State Observability Register. */
2274	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2275	/** K6 PFIR - Page Flush/Invalidate Register. */
2276	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2277
2278	/** Performance counter MSRs. (AMD only) */
2279	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2280	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2281	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2282	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2283	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2284	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2285	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2286	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2287
2288	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2289	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2290	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2291	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2292	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2293	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2294	/** K8 FS.base - The 64-bit base FS register. */
2295	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2296	/** K8 GS.base - The 64-bit base GS register. */
2297	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2298	/** K8 KernelGSbase - Used with SWAPGS. */
2299	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2300	/** K8 TSC_AUX - Used with RDTSCP. */
2301	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2302	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2303	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2304	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2305	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2306	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2307	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2308	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2309	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2310
2311	/** SMM MSRs. */
2312	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2313	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2314	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2315
2316	/** North bridge config? See BIOS & Kernel dev guides for
2317	* details. */
2318	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2319
2320	/** Hypertransport interrupt pending register.
2321	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2322	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2323
2324	/** SVM Control. */
2325	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2326	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2327	* features. */
2328	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2329	/** If set, non-intercepted INIT signals are converted to \#SX
2330	* exceptions. */
2331	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2332	/** Disables A20 masking. */
2333	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2334	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2335	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2336	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2337	* clear, EFER.SVME can be written normally. */
2338	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2339
2340	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2341	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2342	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2343	* host state during world switch. */
2344	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2345
2346	/** Virtualized speculation control for AMD processors.
2347	*
2348	* Unified interface among different CPU generations.
2349	* The VMM will set any architectural MSRs based on the CPU.
2350	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2351	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2352	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2353	/** Speculative Store Bypass Disable. */
2354	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2355
2356	/** @} */
2357
2358
2359	/** @name Page Table / Directory / Directory Pointers / L4.
2360	* @{
2361	*/
2362
2363	#ifndef __ASSEMBLER__
2364	/** Page table/directory entry as an unsigned integer. */
2365	typedef uint32_t X86PGUINT;
2366	/** Pointer to a page table/directory table entry as an unsigned integer. */
2367	typedef X86PGUINT *PX86PGUINT;
2368	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2369	typedef X86PGUINT const *PCX86PGUINT;
2370	#endif
2371
2372	/** Number of entries in a 32-bit PT/PD. */
2373	#define X86_PG_ENTRIES 1024
2374
2375
2376	#ifndef __ASSEMBLER__
2377	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2378	typedef uint64_t X86PGPAEUINT;
2379	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2380	typedef X86PGPAEUINT *PX86PGPAEUINT;
2381	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2382	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2383	#endif
2384
2385	/** Number of entries in a PAE PT/PD. */
2386	#define X86_PG_PAE_ENTRIES 512
2387	/** Number of entries in a PAE PDPT. */
2388	#define X86_PG_PAE_PDPE_ENTRIES 4
2389
2390	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2391	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2392	/** Number of entries in an AMD64 PDPT.
2393	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2394	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2395
2396	/** The size of a default page. */
2397	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2398	/** The page shift of a default page. */
2399	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2400	/** The default page offset mask. */
2401	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2402	/** The default page base mask for virtual addresses. */
2403	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2404	/** The default page base mask for virtual addresses - 32bit version. */
2405	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2406
2407	/** The size of a 4KB page. */
2408	#define X86_PAGE_4K_SIZE _4K
2409	/** The page shift of a 4KB page. */
2410	#define X86_PAGE_4K_SHIFT 12
2411	/** The 4KB page offset mask. */
2412	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2413	/** The 4KB page base mask for virtual addresses. */
2414	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2415	/** The 4KB page base mask for virtual addresses - 32bit version. */
2416	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2417
2418	/** The size of a 2MB page. */
2419	#define X86_PAGE_2M_SIZE _2M
2420	/** The page shift of a 2MB page. */
2421	#define X86_PAGE_2M_SHIFT 21
2422	/** The 2MB page offset mask. */
2423	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2424	/** The 2MB page base mask for virtual addresses. */
2425	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2426	/** The 2MB page base mask for virtual addresses - 32bit version. */
2427	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2428
2429	/** The size of a 4MB page. */
2430	#define X86_PAGE_4M_SIZE _4M
2431	/** The page shift of a 4MB page. */
2432	#define X86_PAGE_4M_SHIFT 22
2433	/** The 4MB page offset mask. */
2434	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2435	/** The 4MB page base mask for virtual addresses. */
2436	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2437	/** The 4MB page base mask for virtual addresses - 32bit version. */
2438	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2439
2440	/** The size of a 1GB page. */
2441	#define X86_PAGE_1G_SIZE _1G
2442	/** The page shift of a 1GB page. */
2443	#define X86_PAGE_1G_SHIFT 30
2444	/** The 1GB page offset mask. */
2445	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2446	/** The 1GB page base mask for virtual addresses. */
2447	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2448
2449	/**
2450	* Check if the given address is canonical.
2451	*/
2452	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2453
2454	/**
2455	* Gets the page base mask given the page shift.
2456	*/
2457	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2458
2459	/**
2460	* Gets the page offset mask given the page shift.
2461	*/
2462	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2463
2464
2465	/** @name Page Table Entry
2466	* @{
2467	*/
2468	/** Bit 0 - P - Present bit. */
2469	#define X86_PTE_BIT_P 0
2470	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2471	#define X86_PTE_BIT_RW 1
2472	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2473	#define X86_PTE_BIT_US 2
2474	/** Bit 3 - PWT - Page level write thru bit. */
2475	#define X86_PTE_BIT_PWT 3
2476	/** Bit 4 - PCD - Page level cache disable bit. */
2477	#define X86_PTE_BIT_PCD 4
2478	/** Bit 5 - A - Access bit. */
2479	#define X86_PTE_BIT_A 5
2480	/** Bit 6 - D - Dirty bit. */
2481	#define X86_PTE_BIT_D 6
2482	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2483	#define X86_PTE_BIT_PAT 7
2484	/** Bit 8 - G - Global flag. */
2485	#define X86_PTE_BIT_G 8
2486	/** Bits 63 - NX - PAE/LM - No execution flag. */
2487	#define X86_PTE_PAE_BIT_NX 63
2488
2489	/** Bit 0 - P - Present bit mask. */
2490	#define X86_PTE_P RT_BIT_32(0)
2491	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2492	#define X86_PTE_RW RT_BIT_32(1)
2493	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2494	#define X86_PTE_US RT_BIT_32(2)
2495	/** Bit 3 - PWT - Page level write thru bit mask. */
2496	#define X86_PTE_PWT RT_BIT_32(3)
2497	/** Bit 4 - PCD - Page level cache disable bit mask. */
2498	#define X86_PTE_PCD RT_BIT_32(4)
2499	/** Bit 5 - A - Access bit mask. */
2500	#define X86_PTE_A RT_BIT_32(5)
2501	/** Bit 6 - D - Dirty bit mask. */
2502	#define X86_PTE_D RT_BIT_32(6)
2503	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2504	#define X86_PTE_PAT RT_BIT_32(7)
2505	/** Bit 8 - G - Global bit mask. */
2506	#define X86_PTE_G RT_BIT_32(8)
2507
2508	/** Bits 9-11 - - Available for use to system software. */
2509	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2510	/** Bits 12-31 - - Physical Page number of the next level. */
2511	#define X86_PTE_PG_MASK ( 0xfffff000 )
2512
2513	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2514	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2515	/** Bits 63 - NX - PAE/LM - No execution flag. */
2516	#define X86_PTE_PAE_NX RT_BIT_64(63)
2517	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2518	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2519	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2520	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2521	/** No bits - - LM - MBZ bits when NX is active. */
2522	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2523	/** Bits 63 - - LM - MBZ bits when no NX. */
2524	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2525
2526	#ifndef __ASSEMBLER__
2527
2528	/**
2529	* Page table entry.
2530	*/
2531	typedef struct X86PTEBITS
2532	{
2533	/** Flags whether(=1) or not the page is present. */
2534	uint32_t u1Present : 1;
2535	/** Read(=0) / Write(=1) flag. */
2536	uint32_t u1Write : 1;
2537	/** User(=1) / Supervisor (=0) flag. */
2538	uint32_t u1User : 1;
2539	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2540	uint32_t u1WriteThru : 1;
2541	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2542	uint32_t u1CacheDisable : 1;
2543	/** Accessed flag.
2544	* Indicates that the page have been read or written to. */
2545	uint32_t u1Accessed : 1;
2546	/** Dirty flag.
2547	* Indicates that the page has been written to. */
2548	uint32_t u1Dirty : 1;
2549	/** Reserved / If PAT enabled, bit 2 of the index. */
2550	uint32_t u1PAT : 1;
2551	/** Global flag. (Ignored in all but final level.) */
2552	uint32_t u1Global : 1;
2553	/** Available for use to system software. */
2554	uint32_t u3Available : 3;
2555	/** Physical Page number of the next level. */
2556	uint32_t u20PageNo : 20;
2557	} X86PTEBITS;
2558	# ifndef VBOX_FOR_DTRACE_LIB
2559	AssertCompileSize(X86PTEBITS, 4);
2560	# endif
2561	/** Pointer to a page table entry. */
2562	typedef X86PTEBITS *PX86PTEBITS;
2563	/** Pointer to a const page table entry. */
2564	typedef const X86PTEBITS *PCX86PTEBITS;
2565
2566	/**
2567	* Page table entry.
2568	*/
2569	typedef union X86PTE
2570	{
2571	/** Unsigned integer view */
2572	X86PGUINT u;
2573	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2574	/** Bit field view. */
2575	X86PTEBITS n;
2576	# endif
2577	/** 32-bit view. */
2578	uint32_t au32[1];
2579	/** 16-bit view. */
2580	uint16_t au16[2];
2581	/** 8-bit view. */
2582	uint8_t au8[4];
2583	} X86PTE;
2584	# ifndef VBOX_FOR_DTRACE_LIB
2585	AssertCompileSize(X86PTE, 4);
2586	# endif
2587	/** Pointer to a page table entry. */
2588	typedef X86PTE *PX86PTE;
2589	/** Pointer to a const page table entry. */
2590	typedef const X86PTE *PCX86PTE;
2591
2592
2593	/**
2594	* PAE page table entry.
2595	*/
2596	typedef struct X86PTEPAEBITS
2597	{
2598	/** Flags whether(=1) or not the page is present. */
2599	uint32_t u1Present : 1;
2600	/** Read(=0) / Write(=1) flag. */
2601	uint32_t u1Write : 1;
2602	/** User(=1) / Supervisor(=0) flag. */
2603	uint32_t u1User : 1;
2604	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2605	uint32_t u1WriteThru : 1;
2606	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2607	uint32_t u1CacheDisable : 1;
2608	/** Accessed flag.
2609	* Indicates that the page have been read or written to. */
2610	uint32_t u1Accessed : 1;
2611	/** Dirty flag.
2612	* Indicates that the page has been written to. */
2613	uint32_t u1Dirty : 1;
2614	/** Reserved / If PAT enabled, bit 2 of the index. */
2615	uint32_t u1PAT : 1;
2616	/** Global flag. (Ignored in all but final level.) */
2617	uint32_t u1Global : 1;
2618	/** Available for use to system software. */
2619	uint32_t u3Available : 3;
2620	/** Physical Page number of the next level - Low Part. Don't use this. */
2621	uint32_t u20PageNoLow : 20;
2622	/** Physical Page number of the next level - High Part. Don't use this. */
2623	uint32_t u20PageNoHigh : 20;
2624	/** MBZ bits */
2625	uint32_t u11Reserved : 11;
2626	/** No Execute flag. */
2627	uint32_t u1NoExecute : 1;
2628	} X86PTEPAEBITS;
2629	# ifndef VBOX_FOR_DTRACE_LIB
2630	AssertCompileSize(X86PTEPAEBITS, 8);
2631	# endif
2632	/** Pointer to a page table entry. */
2633	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2634	/** Pointer to a page table entry. */
2635	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2636
2637	/**
2638	* PAE Page table entry.
2639	*/
2640	typedef union X86PTEPAE
2641	{
2642	/** Unsigned integer view */
2643	X86PGPAEUINT u;
2644	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2645	/** Bit field view. */
2646	X86PTEPAEBITS n;
2647	# endif
2648	/** 32-bit view. */
2649	uint32_t au32[2];
2650	/** 16-bit view. */
2651	uint16_t au16[4];
2652	/** 8-bit view. */
2653	uint8_t au8[8];
2654	} X86PTEPAE;
2655	# ifndef VBOX_FOR_DTRACE_LIB
2656	AssertCompileSize(X86PTEPAE, 8);
2657	# endif
2658	/** Pointer to a PAE page table entry. */
2659	typedef X86PTEPAE *PX86PTEPAE;
2660	/** Pointer to a const PAE page table entry. */
2661	typedef const X86PTEPAE *PCX86PTEPAE;
2662	/** @} */
2663
2664	/**
2665	* Page table.
2666	*/
2667	typedef struct X86PT
2668	{
2669	/** PTE Array. */
2670	X86PTE a[X86_PG_ENTRIES];
2671	} X86PT;
2672	# ifndef VBOX_FOR_DTRACE_LIB
2673	AssertCompileSize(X86PT, 4096);
2674	# endif
2675	/** Pointer to a page table. */
2676	typedef X86PT *PX86PT;
2677	/** Pointer to a const page table. */
2678	typedef const X86PT *PCX86PT;
2679
2680	#endif /* !__ASSEMBLER__ */
2681
2682	/** The page shift to get the PT index. */
2683	#define X86_PT_SHIFT 12
2684	/** The PT index mask (apply to a shifted page address). */
2685	#define X86_PT_MASK 0x3ff
2686
2687
2688	#ifndef __ASSEMBLER__
2689	/**
2690	* Page directory.
2691	*/
2692	typedef struct X86PTPAE
2693	{
2694	/** PTE Array. */
2695	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2696	} X86PTPAE;
2697	# ifndef VBOX_FOR_DTRACE_LIB
2698	AssertCompileSize(X86PTPAE, 4096);
2699	# endif
2700	/** Pointer to a page table. */
2701	typedef X86PTPAE *PX86PTPAE;
2702	/** Pointer to a const page table. */
2703	typedef const X86PTPAE *PCX86PTPAE;
2704	#endif /* !__ASSEMBLER__ */
2705
2706	/** The page shift to get the PA PTE index. */
2707	#define X86_PT_PAE_SHIFT 12
2708	/** The PAE PT index mask (apply to a shifted page address). */
2709	#define X86_PT_PAE_MASK 0x1ff
2710
2711
2712	/** @name 4KB Page Directory Entry
2713	* @{
2714	*/
2715	/** Bit 0 - P - Present bit. */
2716	#define X86_PDE_P RT_BIT_32(0)
2717	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2718	#define X86_PDE_RW RT_BIT_32(1)
2719	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2720	#define X86_PDE_US RT_BIT_32(2)
2721	/** Bit 3 - PWT - Page level write thru bit. */
2722	#define X86_PDE_PWT RT_BIT_32(3)
2723	/** Bit 4 - PCD - Page level cache disable bit. */
2724	#define X86_PDE_PCD RT_BIT_32(4)
2725	/** Bit 5 - A - Access bit. */
2726	#define X86_PDE_A RT_BIT_32(5)
2727	/** Bit 7 - PS - Page size attribute.
2728	* Clear mean 4KB pages, set means large pages (2/4MB). */
2729	#define X86_PDE_PS RT_BIT_32(7)
2730	/** Bits 9-11 - - Available for use to system software. */
2731	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2732	/** Bits 12-31 - - Physical Page number of the next level. */
2733	#define X86_PDE_PG_MASK ( 0xfffff000 )
2734
2735	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2736	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2737	/** Bits 63 - NX - PAE/LM - No execution flag. */
2738	#define X86_PDE_PAE_NX RT_BIT_64(63)
2739	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2740	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2741	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2742	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2743	/** Bit 7 - - LM - MBZ bits when NX is active. */
2744	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2745	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2746	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2747
2748	#ifndef __ASSEMBLER__
2749
2750	/**
2751	* Page directory entry.
2752	*/
2753	typedef struct X86PDEBITS
2754	{
2755	/** Flags whether(=1) or not the page is present. */
2756	uint32_t u1Present : 1;
2757	/** Read(=0) / Write(=1) flag. */
2758	uint32_t u1Write : 1;
2759	/** User(=1) / Supervisor (=0) flag. */
2760	uint32_t u1User : 1;
2761	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2762	uint32_t u1WriteThru : 1;
2763	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2764	uint32_t u1CacheDisable : 1;
2765	/** Accessed flag.
2766	* Indicates that the page has been read or written to. */
2767	uint32_t u1Accessed : 1;
2768	/** Reserved / Ignored (dirty bit). */
2769	uint32_t u1Reserved0 : 1;
2770	/** Size bit if PSE is enabled - in any event it's 0. */
2771	uint32_t u1Size : 1;
2772	/** Reserved / Ignored (global bit). */
2773	uint32_t u1Reserved1 : 1;
2774	/** Available for use to system software. */
2775	uint32_t u3Available : 3;
2776	/** Physical Page number of the next level. */
2777	uint32_t u20PageNo : 20;
2778	} X86PDEBITS;
2779	# ifndef VBOX_FOR_DTRACE_LIB
2780	AssertCompileSize(X86PDEBITS, 4);
2781	# endif
2782	/** Pointer to a page directory entry. */
2783	typedef X86PDEBITS *PX86PDEBITS;
2784	/** Pointer to a const page directory entry. */
2785	typedef const X86PDEBITS *PCX86PDEBITS;
2786
2787
2788	/**
2789	* PAE page directory entry.
2790	*/
2791	typedef struct X86PDEPAEBITS
2792	{
2793	/** Flags whether(=1) or not the page is present. */
2794	uint32_t u1Present : 1;
2795	/** Read(=0) / Write(=1) flag. */
2796	uint32_t u1Write : 1;
2797	/** User(=1) / Supervisor (=0) flag. */
2798	uint32_t u1User : 1;
2799	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2800	uint32_t u1WriteThru : 1;
2801	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2802	uint32_t u1CacheDisable : 1;
2803	/** Accessed flag.
2804	* Indicates that the page has been read or written to. */
2805	uint32_t u1Accessed : 1;
2806	/** Reserved / Ignored (dirty bit). */
2807	uint32_t u1Reserved0 : 1;
2808	/** Size bit if PSE is enabled - in any event it's 0. */
2809	uint32_t u1Size : 1;
2810	/** Reserved / Ignored (global bit). / */
2811	uint32_t u1Reserved1 : 1;
2812	/** Available for use to system software. */
2813	uint32_t u3Available : 3;
2814	/** Physical Page number of the next level - Low Part. Don't use! */
2815	uint32_t u20PageNoLow : 20;
2816	/** Physical Page number of the next level - High Part. Don't use! */
2817	uint32_t u20PageNoHigh : 20;
2818	/** MBZ bits */
2819	uint32_t u11Reserved : 11;
2820	/** No Execute flag. */
2821	uint32_t u1NoExecute : 1;
2822	} X86PDEPAEBITS;
2823	# ifndef VBOX_FOR_DTRACE_LIB
2824	AssertCompileSize(X86PDEPAEBITS, 8);
2825	# endif
2826	/** Pointer to a page directory entry. */
2827	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2828	/** Pointer to a const page directory entry. */
2829	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2830
2831	#endif /* !__ASSEMBLER__ */
2832
2833	/** @} */
2834
2835
2836	/** @name 2/4MB Page Directory Entry
2837	* @{
2838	*/
2839	/** Bit 0 - P - Present bit. */
2840	#define X86_PDE4M_P RT_BIT_32(0)
2841	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2842	#define X86_PDE4M_RW RT_BIT_32(1)
2843	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2844	#define X86_PDE4M_US RT_BIT_32(2)
2845	/** Bit 3 - PWT - Page level write thru bit. */
2846	#define X86_PDE4M_PWT RT_BIT_32(3)
2847	/** Bit 4 - PCD - Page level cache disable bit. */
2848	#define X86_PDE4M_PCD RT_BIT_32(4)
2849	/** Bit 5 - A - Access bit. */
2850	#define X86_PDE4M_A RT_BIT_32(5)
2851	/** Bit 6 - D - Dirty bit. */
2852	#define X86_PDE4M_D RT_BIT_32(6)
2853	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2854	#define X86_PDE4M_PS RT_BIT_32(7)
2855	/** Bit 8 - G - Global flag. */
2856	#define X86_PDE4M_G RT_BIT_32(8)
2857	/** Bits 9-11 - AVL - Available for use to system software. */
2858	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2859	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2860	#define X86_PDE4M_PAT RT_BIT_32(12)
2861	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2862	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2863	/** Bits 22-31 - - Physical Page number. */
2864	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2865	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2866	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2867	/** The number of bits to the high part of the page number. */
2868	#define X86_PDE4M_PG_HIGH_SHIFT 19
2869	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2870	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2871
2872	/** Bits 21-51 - - PAE/LM - Physical Page number.
2873	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2874	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2875	/** Bits 63 - NX - PAE/LM - No execution flag. */
2876	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2877	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2878	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2879	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2880	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2881	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2882	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2883	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2884	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2885
2886	#ifndef __ASSEMBLER__
2887
2888	/**
2889	* 4MB page directory entry.
2890	*/
2891	typedef struct X86PDE4MBITS
2892	{
2893	/** Flags whether(=1) or not the page is present. */
2894	uint32_t u1Present : 1;
2895	/** Read(=0) / Write(=1) flag. */
2896	uint32_t u1Write : 1;
2897	/** User(=1) / Supervisor (=0) flag. */
2898	uint32_t u1User : 1;
2899	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2900	uint32_t u1WriteThru : 1;
2901	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2902	uint32_t u1CacheDisable : 1;
2903	/** Accessed flag.
2904	* Indicates that the page have been read or written to. */
2905	uint32_t u1Accessed : 1;
2906	/** Dirty flag.
2907	* Indicates that the page has been written to. */
2908	uint32_t u1Dirty : 1;
2909	/** Page size flag - always 1 for 4MB entries. */
2910	uint32_t u1Size : 1;
2911	/** Global flag. */
2912	uint32_t u1Global : 1;
2913	/** Available for use to system software. */
2914	uint32_t u3Available : 3;
2915	/** Reserved / If PAT enabled, bit 2 of the index. */
2916	uint32_t u1PAT : 1;
2917	/** Bits 32-39 of the page number on AMD64.
2918	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2919	uint32_t u8PageNoHigh : 8;
2920	/** Reserved. */
2921	uint32_t u1Reserved : 1;
2922	/** Physical Page number of the page. */
2923	uint32_t u10PageNo : 10;
2924	} X86PDE4MBITS;
2925	# ifndef VBOX_FOR_DTRACE_LIB
2926	AssertCompileSize(X86PDE4MBITS, 4);
2927	# endif
2928	/** Pointer to a page table entry. */
2929	typedef X86PDE4MBITS *PX86PDE4MBITS;
2930	/** Pointer to a const page table entry. */
2931	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2932
2933
2934	/**
2935	* 2MB PAE page directory entry.
2936	*/
2937	typedef struct X86PDE2MPAEBITS
2938	{
2939	/** Flags whether(=1) or not the page is present. */
2940	uint32_t u1Present : 1;
2941	/** Read(=0) / Write(=1) flag. */
2942	uint32_t u1Write : 1;
2943	/** User(=1) / Supervisor(=0) flag. */
2944	uint32_t u1User : 1;
2945	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2946	uint32_t u1WriteThru : 1;
2947	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2948	uint32_t u1CacheDisable : 1;
2949	/** Accessed flag.
2950	* Indicates that the page have been read or written to. */
2951	uint32_t u1Accessed : 1;
2952	/** Dirty flag.
2953	* Indicates that the page has been written to. */
2954	uint32_t u1Dirty : 1;
2955	/** Page size flag - always 1 for 2MB entries. */
2956	uint32_t u1Size : 1;
2957	/** Global flag. */
2958	uint32_t u1Global : 1;
2959	/** Available for use to system software. */
2960	uint32_t u3Available : 3;
2961	/** Reserved / If PAT enabled, bit 2 of the index. */
2962	uint32_t u1PAT : 1;
2963	/** Reserved. */
2964	uint32_t u9Reserved : 9;
2965	/** Physical Page number of the next level - Low part. Don't use! */
2966	uint32_t u10PageNoLow : 10;
2967	/** Physical Page number of the next level - High part. Don't use! */
2968	uint32_t u20PageNoHigh : 20;
2969	/** MBZ bits */
2970	uint32_t u11Reserved : 11;
2971	/** No Execute flag. */
2972	uint32_t u1NoExecute : 1;
2973	} X86PDE2MPAEBITS;
2974	# ifndef VBOX_FOR_DTRACE_LIB
2975	AssertCompileSize(X86PDE2MPAEBITS, 8);
2976	# endif
2977	/** Pointer to a 2MB PAE page table entry. */
2978	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2979	/** Pointer to a 2MB PAE page table entry. */
2980	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2981
2982	#endif /* !__ASSEMBLER__ */
2983
2984	/** @} */
2985
2986	#ifndef __ASSEMBLER__
2987
2988	/**
2989	* Page directory entry.
2990	*/
2991	typedef union X86PDE
2992	{
2993	/** Unsigned integer view. */
2994	X86PGUINT u;
2995	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2996	/** Normal view. */
2997	X86PDEBITS n;
2998	/** 4MB view (big). */
2999	X86PDE4MBITS b;
3000	# endif
3001	/** 8 bit unsigned integer view. */
3002	uint8_t au8[4];
3003	/** 16 bit unsigned integer view. */
3004	uint16_t au16[2];
3005	/** 32 bit unsigned integer view. */
3006	uint32_t au32[1];
3007	} X86PDE;
3008	# ifndef VBOX_FOR_DTRACE_LIB
3009	AssertCompileSize(X86PDE, 4);
3010	# endif
3011	/** Pointer to a page directory entry. */
3012	typedef X86PDE *PX86PDE;
3013	/** Pointer to a const page directory entry. */
3014	typedef const X86PDE *PCX86PDE;
3015
3016	/**
3017	* PAE page directory entry.
3018	*/
3019	typedef union X86PDEPAE
3020	{
3021	/** Unsigned integer view. */
3022	X86PGPAEUINT u;
3023	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3024	/** Normal view. */
3025	X86PDEPAEBITS n;
3026	/** 2MB page view (big). */
3027	X86PDE2MPAEBITS b;
3028	# endif
3029	/** 8 bit unsigned integer view. */
3030	uint8_t au8[8];
3031	/** 16 bit unsigned integer view. */
3032	uint16_t au16[4];
3033	/** 32 bit unsigned integer view. */
3034	uint32_t au32[2];
3035	} X86PDEPAE;
3036	# ifndef VBOX_FOR_DTRACE_LIB
3037	AssertCompileSize(X86PDEPAE, 8);
3038	# endif
3039	/** Pointer to a page directory entry. */
3040	typedef X86PDEPAE *PX86PDEPAE;
3041	/** Pointer to a const page directory entry. */
3042	typedef const X86PDEPAE *PCX86PDEPAE;
3043
3044	/**
3045	* Page directory.
3046	*/
3047	typedef struct X86PD
3048	{
3049	/** PDE Array. */
3050	X86PDE a[X86_PG_ENTRIES];
3051	} X86PD;
3052	# ifndef VBOX_FOR_DTRACE_LIB
3053	AssertCompileSize(X86PD, 4096);
3054	# endif
3055	/** Pointer to a page directory. */
3056	typedef X86PD *PX86PD;
3057	/** Pointer to a const page directory. */
3058	typedef const X86PD *PCX86PD;
3059
3060	#endif /* !__ASSEMBLER__ */
3061
3062	/** The page shift to get the PD index. */
3063	#define X86_PD_SHIFT 22
3064	/** The PD index mask (apply to a shifted page address). */
3065	#define X86_PD_MASK 0x3ff
3066
3067
3068	#ifndef __ASSEMBLER__
3069	/**
3070	* PAE page directory.
3071	*/
3072	typedef struct X86PDPAE
3073	{
3074	/** PDE Array. */
3075	X86PDEPAE a[X86_PG_PAE_ENTRIES];
3076	} X86PDPAE;
3077	# ifndef VBOX_FOR_DTRACE_LIB
3078	AssertCompileSize(X86PDPAE, 4096);
3079	# endif
3080	/** Pointer to a PAE page directory. */
3081	typedef X86PDPAE *PX86PDPAE;
3082	/** Pointer to a const PAE page directory. */
3083	typedef const X86PDPAE *PCX86PDPAE;
3084	#endif /* !__ASSEMBLER__ */
3085
3086	/** The page shift to get the PAE PD index. */
3087	#define X86_PD_PAE_SHIFT 21
3088	/** The PAE PD index mask (apply to a shifted page address). */
3089	#define X86_PD_PAE_MASK 0x1ff
3090
3091
3092	/** @name Page Directory Pointer Table Entry (PAE)
3093	* @{
3094	*/
3095	/** Bit 0 - P - Present bit. */
3096	#define X86_PDPE_P RT_BIT_32(0)
3097	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
3098	#define X86_PDPE_RW RT_BIT_32(1)
3099	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
3100	#define X86_PDPE_US RT_BIT_32(2)
3101	/** Bit 3 - PWT - Page level write thru bit. */
3102	#define X86_PDPE_PWT RT_BIT_32(3)
3103	/** Bit 4 - PCD - Page level cache disable bit. */
3104	#define X86_PDPE_PCD RT_BIT_32(4)
3105	/** Bit 5 - A - Access bit. Long Mode only. */
3106	#define X86_PDPE_A RT_BIT_32(5)
3107	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
3108	#define X86_PDPE_LM_PS RT_BIT_32(7)
3109	/** Bits 9-11 - - Available for use to system software. */
3110	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3111	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3112	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
3113	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
3114	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
3115	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
3116	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
3117	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
3118	#define X86_PDPE_LM_NX RT_BIT_64(63)
3119	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
3120	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
3121	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
3122	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
3123	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
3124	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
3125	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
3126	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
3127
3128	#ifndef __ASSEMBLER__
3129
3130	/**
3131	* Page directory pointer table entry.
3132	*/
3133	typedef struct X86PDPEBITS
3134	{
3135	/** Flags whether(=1) or not the page is present. */
3136	uint32_t u1Present : 1;
3137	/** Chunk of reserved bits. */
3138	uint32_t u2Reserved : 2;
3139	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3140	uint32_t u1WriteThru : 1;
3141	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3142	uint32_t u1CacheDisable : 1;
3143	/** Chunk of reserved bits. */
3144	uint32_t u4Reserved : 4;
3145	/** Available for use to system software. */
3146	uint32_t u3Available : 3;
3147	/** Physical Page number of the next level - Low Part. Don't use! */
3148	uint32_t u20PageNoLow : 20;
3149	/** Physical Page number of the next level - High Part. Don't use! */
3150	uint32_t u20PageNoHigh : 20;
3151	/** MBZ bits */
3152	uint32_t u12Reserved : 12;
3153	} X86PDPEBITS;
3154	# ifndef VBOX_FOR_DTRACE_LIB
3155	AssertCompileSize(X86PDPEBITS, 8);
3156	# endif
3157	/** Pointer to a page directory pointer table entry. */
3158	typedef X86PDPEBITS *PX86PTPEBITS;
3159	/** Pointer to a const page directory pointer table entry. */
3160	typedef const X86PDPEBITS *PCX86PTPEBITS;
3161
3162	/**
3163	* Page directory pointer table entry. AMD64 version
3164	*/
3165	typedef struct X86PDPEAMD64BITS
3166	{
3167	/** Flags whether(=1) or not the page is present. */
3168	uint32_t u1Present : 1;
3169	/** Read(=0) / Write(=1) flag. */
3170	uint32_t u1Write : 1;
3171	/** User(=1) / Supervisor (=0) flag. */
3172	uint32_t u1User : 1;
3173	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3174	uint32_t u1WriteThru : 1;
3175	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3176	uint32_t u1CacheDisable : 1;
3177	/** Accessed flag.
3178	* Indicates that the page have been read or written to. */
3179	uint32_t u1Accessed : 1;
3180	/** Chunk of reserved bits. */
3181	uint32_t u3Reserved : 3;
3182	/** Available for use to system software. */
3183	uint32_t u3Available : 3;
3184	/** Physical Page number of the next level - Low Part. Don't use! */
3185	uint32_t u20PageNoLow : 20;
3186	/** Physical Page number of the next level - High Part. Don't use! */
3187	uint32_t u20PageNoHigh : 20;
3188	/** MBZ bits */
3189	uint32_t u11Reserved : 11;
3190	/** No Execute flag. */
3191	uint32_t u1NoExecute : 1;
3192	} X86PDPEAMD64BITS;
3193	# ifndef VBOX_FOR_DTRACE_LIB
3194	AssertCompileSize(X86PDPEAMD64BITS, 8);
3195	# endif
3196	/** Pointer to a page directory pointer table entry. */
3197	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
3198	/** Pointer to a const page directory pointer table entry. */
3199	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
3200
3201	/**
3202	* Page directory pointer table entry for 1GB page. (AMD64 only)
3203	*/
3204	typedef struct X86PDPE1GB
3205	{
3206	/** 0: Flags whether(=1) or not the page is present. */
3207	uint32_t u1Present : 1;
3208	/** 1: Read(=0) / Write(=1) flag. */
3209	uint32_t u1Write : 1;
3210	/** 2: User(=1) / Supervisor (=0) flag. */
3211	uint32_t u1User : 1;
3212	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
3213	uint32_t u1WriteThru : 1;
3214	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
3215	uint32_t u1CacheDisable : 1;
3216	/** 5: Accessed flag.
3217	* Indicates that the page have been read or written to. */
3218	uint32_t u1Accessed : 1;
3219	/** 6: Dirty flag for 1GB pages. */
3220	uint32_t u1Dirty : 1;
3221	/** 7: Indicates 1GB page if set. */
3222	uint32_t u1Size : 1;
3223	/** 8: Global 1GB page. */
3224	uint32_t u1Global: 1;
3225	/** 9-11: Available for use to system software. */
3226	uint32_t u3Available : 3;
3227	/** 12: PAT bit for 1GB page. */
3228	uint32_t u1PAT : 1;
3229	/** 13-29: MBZ bits. */
3230	uint32_t u17Reserved : 17;
3231	/** 30-31: Physical page number - Low Part. Don't use! */
3232	uint32_t u2PageNoLow : 2;
3233	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
3234	uint32_t u20PageNoHigh : 20;
3235	/** 52-62: MBZ bits */
3236	uint32_t u11Reserved : 11;
3237	/** 63: No Execute flag. */
3238	uint32_t u1NoExecute : 1;
3239	} X86PDPE1GB;
3240	# ifndef VBOX_FOR_DTRACE_LIB
3241	AssertCompileSize(X86PDPE1GB, 8);
3242	# endif
3243	/** Pointer to a page directory pointer table entry for a 1GB page. */
3244	typedef X86PDPE1GB *PX86PDPE1GB;
3245	/** Pointer to a const page directory pointer table entry for a 1GB page. */
3246	typedef const X86PDPE1GB *PCX86PDPE1GB;
3247
3248	/**
3249	* Page directory pointer table entry.
3250	*/
3251	typedef union X86PDPE
3252	{
3253	/** Unsigned integer view. */
3254	X86PGPAEUINT u;
3255	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3256	/** Normal view. */
3257	X86PDPEBITS n;
3258	/** AMD64 view. */
3259	X86PDPEAMD64BITS lm;
3260	/** AMD64 big view. */
3261	X86PDPE1GB b;
3262	# endif
3263	/** 8 bit unsigned integer view. */
3264	uint8_t au8[8];
3265	/** 16 bit unsigned integer view. */
3266	uint16_t au16[4];
3267	/** 32 bit unsigned integer view. */
3268	uint32_t au32[2];
3269	} X86PDPE;
3270	# ifndef VBOX_FOR_DTRACE_LIB
3271	AssertCompileSize(X86PDPE, 8);
3272	# endif
3273	/** Pointer to a page directory pointer table entry. */
3274	typedef X86PDPE *PX86PDPE;
3275	/** Pointer to a const page directory pointer table entry. */
3276	typedef const X86PDPE *PCX86PDPE;
3277
3278
3279	/**
3280	* Page directory pointer table.
3281	*/
3282	typedef struct X86PDPT
3283	{
3284	/** PDE Array. */
3285	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3286	} X86PDPT;
3287	# ifndef VBOX_FOR_DTRACE_LIB
3288	AssertCompileSize(X86PDPT, 4096);
3289	# endif
3290	/** Pointer to a page directory pointer table. */
3291	typedef X86PDPT *PX86PDPT;
3292	/** Pointer to a const page directory pointer table. */
3293	typedef const X86PDPT *PCX86PDPT;
3294
3295	#endif /* !__ASSEMBLER__ */
3296
3297	/** The page shift to get the PDPT index. */
3298	#define X86_PDPT_SHIFT 30
3299	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3300	#define X86_PDPT_MASK_PAE 0x3
3301	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3302	#define X86_PDPT_MASK_AMD64 0x1ff
3303
3304	/** @} */
3305
3306
3307	/** @name Page Map Level-4 Entry (Long Mode PAE)
3308	* @{
3309	*/
3310	/** Bit 0 - P - Present bit. */
3311	#define X86_PML4E_P RT_BIT_32(0)
3312	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3313	#define X86_PML4E_RW RT_BIT_32(1)
3314	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3315	#define X86_PML4E_US RT_BIT_32(2)
3316	/** Bit 3 - PWT - Page level write thru bit. */
3317	#define X86_PML4E_PWT RT_BIT_32(3)
3318	/** Bit 4 - PCD - Page level cache disable bit. */
3319	#define X86_PML4E_PCD RT_BIT_32(4)
3320	/** Bit 5 - A - Access bit. */
3321	#define X86_PML4E_A RT_BIT_32(5)
3322	/** Bits 9-11 - - Available for use to system software. */
3323	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3324	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3325	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3326	/** Bits 8, 7 - - MBZ bits when NX is active. */
3327	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3328	/** Bits 63, 7 - - MBZ bits when no NX. */
3329	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3330	/** Bits 63 - NX - PAE - No execution flag. */
3331	#define X86_PML4E_NX RT_BIT_64(63)
3332
3333	#ifndef __ASSEMBLER__
3334
3335	/**
3336	* Page Map Level-4 Entry
3337	*/
3338	typedef struct X86PML4EBITS
3339	{
3340	/** Flags whether(=1) or not the page is present. */
3341	uint32_t u1Present : 1;
3342	/** Read(=0) / Write(=1) flag. */
3343	uint32_t u1Write : 1;
3344	/** User(=1) / Supervisor (=0) flag. */
3345	uint32_t u1User : 1;
3346	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3347	uint32_t u1WriteThru : 1;
3348	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3349	uint32_t u1CacheDisable : 1;
3350	/** Accessed flag.
3351	* Indicates that the page have been read or written to. */
3352	uint32_t u1Accessed : 1;
3353	/** Chunk of reserved bits. */
3354	uint32_t u3Reserved : 3;
3355	/** Available for use to system software. */
3356	uint32_t u3Available : 3;
3357	/** Physical Page number of the next level - Low Part. Don't use! */
3358	uint32_t u20PageNoLow : 20;
3359	/** Physical Page number of the next level - High Part. Don't use! */
3360	uint32_t u20PageNoHigh : 20;
3361	/** MBZ bits */
3362	uint32_t u11Reserved : 11;
3363	/** No Execute flag. */
3364	uint32_t u1NoExecute : 1;
3365	} X86PML4EBITS;
3366	# ifndef VBOX_FOR_DTRACE_LIB
3367	AssertCompileSize(X86PML4EBITS, 8);
3368	# endif
3369	/** Pointer to a page map level-4 entry. */
3370	typedef X86PML4EBITS *PX86PML4EBITS;
3371	/** Pointer to a const page map level-4 entry. */
3372	typedef const X86PML4EBITS *PCX86PML4EBITS;
3373
3374	/**
3375	* Page Map Level-4 Entry.
3376	*/
3377	typedef union X86PML4E
3378	{
3379	/** Unsigned integer view. */
3380	X86PGPAEUINT u;
3381	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3382	/** Normal view. */
3383	X86PML4EBITS n;
3384	# endif
3385	/** 8 bit unsigned integer view. */
3386	uint8_t au8[8];
3387	/** 16 bit unsigned integer view. */
3388	uint16_t au16[4];
3389	/** 32 bit unsigned integer view. */
3390	uint32_t au32[2];
3391	} X86PML4E;
3392	# ifndef VBOX_FOR_DTRACE_LIB
3393	AssertCompileSize(X86PML4E, 8);
3394	# endif
3395	/** Pointer to a page map level-4 entry. */
3396	typedef X86PML4E *PX86PML4E;
3397	/** Pointer to a const page map level-4 entry. */
3398	typedef const X86PML4E *PCX86PML4E;
3399
3400
3401	/**
3402	* Page Map Level-4.
3403	*/
3404	typedef struct X86PML4
3405	{
3406	/** PDE Array. */
3407	X86PML4E a[X86_PG_PAE_ENTRIES];
3408	} X86PML4;
3409	# ifndef VBOX_FOR_DTRACE_LIB
3410	AssertCompileSize(X86PML4, 4096);
3411	# endif
3412	/** Pointer to a page map level-4. */
3413	typedef X86PML4 *PX86PML4;
3414	/** Pointer to a const page map level-4. */
3415	typedef const X86PML4 *PCX86PML4;
3416
3417	#endif /* !__ASSEMBLER__ */
3418
3419	/** The page shift to get the PML4 index. */
3420	#define X86_PML4_SHIFT 39
3421	/** The PML4 index mask (apply to a shifted page address). */
3422	#define X86_PML4_MASK 0x1ff
3423
3424	/** @} */
3425
3426	/** @} */
3427
3428	/**
3429	* Intel PCID invalidation types.
3430	*/
3431	/** Individual address invalidation. */
3432	#define X86_INVPCID_TYPE_INDV_ADDR 0
3433	/** Single-context invalidation. */
3434	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3435	/** All-context including globals invalidation. */
3436	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3437	/** All-context excluding globals invalidation. */
3438	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3439	/** The maximum valid invalidation type value. */
3440	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3441
3442
3443	/** @name Special FPU integer values.
3444	* @{ */
3445	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3446	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3447	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3448	/** @} */
3449
3450	#ifndef __ASSEMBLER__
3451
3452	/**
3453	* 32-bit protected mode FSTENV image.
3454	*/
3455	typedef struct X86FSTENV32P
3456	{
3457	uint16_t FCW; /*< 0x00 /
3458	uint16_t padding1; /*< 0x02 /
3459	uint16_t FSW; /*< 0x04 /
3460	uint16_t padding2; /*< 0x06 /
3461	uint16_t FTW; /*< 0x08 /
3462	uint16_t padding3; /*< 0x0a /
3463	uint32_t FPUIP; /*< 0x0c /
3464	uint16_t FPUCS; /*< 0x10 /
3465	uint16_t FOP; /*< 0x12 /
3466	uint32_t FPUDP; /*< 0x14 /
3467	uint16_t FPUDS; /*< 0x18 /
3468	uint16_t padding4; /*< 0x1a /
3469	} X86FSTENV32P;
3470	# ifndef VBOX_FOR_DTRACE_LIB
3471	AssertCompileSize(X86FSTENV32P, 0x1c);
3472	# endif
3473	/** Pointer to a 32-bit protected mode FSTENV image. */
3474	typedef X86FSTENV32P *PX86FSTENV32P;
3475	/** Pointer to a const 32-bit protected mode FSTENV image. */
3476	typedef X86FSTENV32P const *PCX86FSTENV32P;
3477
3478
3479	/**
3480	* 80-bit MMX/FPU register type.
3481	*/
3482	typedef struct X86FPUMMX
3483	{
3484	uint8_t reg[10];
3485	} X86FPUMMX;
3486	# ifndef VBOX_FOR_DTRACE_LIB
3487	AssertCompileSize(X86FPUMMX, 10);
3488	# endif
3489	/** Pointer to a 80-bit MMX/FPU register type. */
3490	typedef X86FPUMMX *PX86FPUMMX;
3491	/** Pointer to a const 80-bit MMX/FPU register type. */
3492	typedef const X86FPUMMX *PCX86FPUMMX;
3493
3494	/** FPU (x87) register. */
3495	typedef union X86FPUREG
3496	{
3497	/** MMX view. */
3498	uint64_t mmx;
3499	/** FPU view - todo. */
3500	X86FPUMMX fpu;
3501	/** Extended precision floating point view. */
3502	RTFLOAT80U r80;
3503	/** Extended precision floating point view v2 */
3504	RTFLOAT80U2 r80Ex;
3505	/** 8-bit view. */
3506	uint8_t au8[16];
3507	/** 16-bit view. */
3508	uint16_t au16[8];
3509	/** 32-bit view. */
3510	uint32_t au32[4];
3511	/** 64-bit view. */
3512	uint64_t au64[2];
3513	/** 128-bit view. (yeah, very helpful) */
3514	uint128_t au128[1];
3515	} X86FPUREG;
3516	# ifndef VBOX_FOR_DTRACE_LIB
3517	AssertCompileSize(X86FPUREG, 16);
3518	# endif
3519	/** Pointer to a FPU register. */
3520	typedef X86FPUREG *PX86FPUREG;
3521	/** Pointer to a const FPU register. */
3522	typedef X86FPUREG const *PCX86FPUREG;
3523
3524	/** FPU (x87) register - v2 with correct size. */
3525	# pragma pack(1)
3526	typedef union X86FPUREG2
3527	{
3528	/** MMX view. */
3529	uint64_t mmx;
3530	/** FPU view - todo. */
3531	X86FPUMMX fpu;
3532	/** Extended precision floating point view. */
3533	RTFLOAT80U r80;
3534	/** 8-bit view. */
3535	uint8_t au8[10];
3536	/** 16-bit view. */
3537	uint16_t au16[5];
3538	/** 32-bit view. */
3539	uint32_t au32[2];
3540	/** 64-bit view. */
3541	uint64_t au64[1];
3542	} X86FPUREG2;
3543	# pragma pack()
3544	# ifndef VBOX_FOR_DTRACE_LIB
3545	AssertCompileSize(X86FPUREG2, 10);
3546	# endif
3547	/** Pointer to a FPU register - v2. */
3548	typedef X86FPUREG2 *PX86FPUREG2;
3549	/** Pointer to a const FPU register - v2. */
3550	typedef X86FPUREG2 const *PCX86FPUREG2;
3551
3552	/**
3553	* XMM register union.
3554	*/
3555	typedef union X86XMMREG
3556	{
3557	/** XMM Register view. */
3558	uint128_t xmm;
3559	/** 8-bit view. */
3560	uint8_t au8[16];
3561	/** 16-bit view. */
3562	uint16_t au16[8];
3563	/** 32-bit view. */
3564	uint32_t au32[4];
3565	/** 64-bit view. */
3566	uint64_t au64[2];
3567	/** Signed 8-bit view. */
3568	int8_t ai8[16];
3569	/** Signed 16-bit view. */
3570	int16_t ai16[8];
3571	/** Signed 32-bit view. */
3572	int32_t ai32[4];
3573	/** Signed 64-bit view. */
3574	int64_t ai64[2];
3575	/** 128-bit view. (yeah, very helpful) */
3576	uint128_t au128[1];
3577	/** Single precision floating point view. */
3578	RTFLOAT32U ar32[4];
3579	/** Double precision floating point view. */
3580	RTFLOAT64U ar64[2];
3581	# ifndef VBOX_FOR_DTRACE_LIB
3582	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3583	RTUINT128U uXmm;
3584	# endif
3585	} X86XMMREG;
3586	# ifndef VBOX_FOR_DTRACE_LIB
3587	AssertCompileSize(X86XMMREG, 16);
3588	# endif
3589	/** Pointer to an XMM register state. */
3590	typedef X86XMMREG *PX86XMMREG;
3591	/** Pointer to a const XMM register state. */
3592	typedef X86XMMREG const *PCX86XMMREG;
3593
3594	/**
3595	* YMM register union.
3596	*/
3597	typedef union X86YMMREG
3598	{
3599	/** YMM register view. */
3600	RTUINT256U ymm;
3601	/** 8-bit view. */
3602	uint8_t au8[32];
3603	/** 16-bit view. */
3604	uint16_t au16[16];
3605	/** 32-bit view. */
3606	uint32_t au32[8];
3607	/** 64-bit view. */
3608	uint64_t au64[4];
3609	/** Signed 8-bit view. */
3610	int8_t ai8[32];
3611	/** Signed 16-bit view. */
3612	int16_t ai16[16];
3613	/** Signed 32-bit view. */
3614	int32_t ai32[8];
3615	/** Signed 64-bit view. */
3616	int64_t ai64[4];
3617	/** 128-bit view. (yeah, very helpful) */
3618	uint128_t au128[2];
3619	/** Single precision floating point view. */
3620	RTFLOAT32U ar32[8];
3621	/** Double precision floating point view. */
3622	RTFLOAT64U ar64[4];
3623	/** XMM sub register view. */
3624	X86XMMREG aXmm[2];
3625	} X86YMMREG;
3626	# ifndef VBOX_FOR_DTRACE_LIB
3627	AssertCompileSize(X86YMMREG, 32);
3628	# endif
3629	/** Pointer to an YMM register state. */
3630	typedef X86YMMREG *PX86YMMREG;
3631	/** Pointer to a const YMM register state. */
3632	typedef X86YMMREG const *PCX86YMMREG;
3633
3634	/**
3635	* ZMM register union.
3636	*/
3637	typedef union X86ZMMREG
3638	{
3639	/** 8-bit view. */
3640	uint8_t au8[64];
3641	/** 16-bit view. */
3642	uint16_t au16[32];
3643	/** 32-bit view. */
3644	uint32_t au32[16];
3645	/** 64-bit view. */
3646	uint64_t au64[8];
3647	/** Signed 8-bit view. */
3648	int8_t ai8[64];
3649	/** Signed 16-bit view. */
3650	int16_t ai16[32];
3651	/** Signed 32-bit view. */
3652	int32_t ai32[16];
3653	/** Signed 64-bit view. */
3654	int64_t ai64[8];
3655	/** 128-bit view. (yeah, very helpful) */
3656	uint128_t au128[4];
3657	/** Single precision floating point view. */
3658	RTFLOAT32U ar32[16];
3659	/** Double precision floating point view. */
3660	RTFLOAT64U ar64[8];
3661	/** XMM sub register view. */
3662	X86XMMREG aXmm[4];
3663	/** YMM sub register view. */
3664	X86YMMREG aYmm[2];
3665	} X86ZMMREG;
3666	# ifndef VBOX_FOR_DTRACE_LIB
3667	AssertCompileSize(X86ZMMREG, 64);
3668	# endif
3669	/** Pointer to an ZMM register state. */
3670	typedef X86ZMMREG *PX86ZMMREG;
3671	/** Pointer to a const ZMM register state. */
3672	typedef X86ZMMREG const *PCX86ZMMREG;
3673
3674
3675	/**
3676	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3677	*/
3678	# pragma pack(1)
3679	typedef struct X86FPUSTATE
3680	{
3681	/** 0x00 - Control word. */
3682	uint16_t FCW;
3683	/** 0x02 - Alignment word */
3684	uint16_t Dummy1;
3685	/** 0x04 - Status word. */
3686	uint16_t FSW;
3687	/** 0x06 - Alignment word */
3688	uint16_t Dummy2;
3689	/** 0x08 - Tag word */
3690	uint16_t FTW;
3691	/** 0x0a - Alignment word */
3692	uint16_t Dummy3;
3693
3694	/** 0x0c - Instruction pointer. */
3695	uint32_t FPUIP;
3696	/** 0x10 - Code selector. */
3697	uint16_t CS;
3698	/** 0x12 - Opcode. */
3699	uint16_t FOP;
3700	/** 0x14 - Data pointer. */
3701	uint32_t FPUOO;
3702	/** 0x18 - FOS. */
3703	uint16_t FPUOS;
3704	/** 0x0a - Alignment word */
3705	uint16_t Dummy4;
3706	/** 0x1c - FPU register. */
3707	X86FPUREG2 regs[8];
3708	} X86FPUSTATE;
3709	# pragma pack()
3710	AssertCompileSize(X86FPUSTATE, 108);
3711	/** Pointer to a FPU state. */
3712	typedef X86FPUSTATE *PX86FPUSTATE;
3713	/** Pointer to a const FPU state. */
3714	typedef const X86FPUSTATE *PCX86FPUSTATE;
3715
3716	/**
3717	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3718	*/
3719	# pragma pack(1)
3720	typedef struct X86FXSTATE
3721	{
3722	/** 0x00 - Control word. */
3723	uint16_t FCW;
3724	/** 0x02 - Status word. */
3725	uint16_t FSW;
3726	/** 0x04 - Tag word. (The upper byte is always zero.) */
3727	uint16_t FTW;
3728	/** 0x06 - Opcode. */
3729	uint16_t FOP;
3730	/** 0x08 - Instruction pointer. */
3731	uint32_t FPUIP;
3732	/** 0x0c - Code selector. */
3733	uint16_t CS;
3734	uint16_t Rsrvd1;
3735	/** 0x10 - Data pointer. */
3736	uint32_t FPUDP;
3737	/** 0x14 - Data segment */
3738	uint16_t DS;
3739	/** 0x16 */
3740	uint16_t Rsrvd2;
3741	/** 0x18 */
3742	uint32_t MXCSR;
3743	/** 0x1c */
3744	uint32_t MXCSR_MASK;
3745	/** 0x20 - FPU registers. */
3746	X86FPUREG aRegs[8];
3747	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3748	X86XMMREG aXMM[16];
3749	/* - offset 416 - */
3750	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3751	/* - offset 464 - Software usable reserved bits. */
3752	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3753	} X86FXSTATE;
3754	# pragma pack()
3755	/** Pointer to a FPU Extended state. */
3756	typedef X86FXSTATE *PX86FXSTATE;
3757	/** Pointer to a const FPU Extended state. */
3758	typedef const X86FXSTATE *PCX86FXSTATE;
3759
3760	#endif /* !__ASSEMBLER__ */
3761
3762
3763	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3764	* magic. Don't forget to update x86.mac if you change this! */
3765	#define X86_OFF_FXSTATE_RSVD 0x1d0
3766	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3767	* forget to update x86.mac if you change this!
3768	* @todo r=bird: This has nothing what-so-ever to do here.... */
3769	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3770	#ifndef VBOX_FOR_DTRACE_LIB
3771	AssertCompileSize(X86FXSTATE, 512);
3772	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3773	#endif
3774
3775	/** @name FPU status word flags.
3776	* @{ */
3777	/** Exception Flag: Invalid operation. */
3778	#define X86_FSW_IE RT_BIT_32(0)
3779	#define X86_FSW_IE_BIT 0
3780	/** Exception Flag: Denormalized operand. */
3781	#define X86_FSW_DE RT_BIT_32(1)
3782	#define X86_FSW_DE_BIT 1
3783	/** Exception Flag: Zero divide. */
3784	#define X86_FSW_ZE RT_BIT_32(2)
3785	#define X86_FSW_ZE_BIT 2
3786	/** Exception Flag: Overflow. */
3787	#define X86_FSW_OE RT_BIT_32(3)
3788	#define X86_FSW_OE_BIT 3
3789	/** Exception Flag: Underflow. */
3790	#define X86_FSW_UE RT_BIT_32(4)
3791	#define X86_FSW_UE_BIT 4
3792	/** Exception Flag: Precision. */
3793	#define X86_FSW_PE RT_BIT_32(5)
3794	#define X86_FSW_PE_BIT 5
3795	/** Stack fault. */
3796	#define X86_FSW_SF RT_BIT_32(6)
3797	#define X86_FSW_SF_BIT 6
3798	/** Error summary status. */
3799	#define X86_FSW_ES RT_BIT_32(7)
3800	#define X86_FSW_ES_BIT 7
3801	/** Mask of exceptions flags, excluding the summary bit. */
3802	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3803	/** Mask of exceptions flags, including the summary bit. */
3804	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3805	/** Condition code 0. */
3806	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3807	#define X86_FSW_C0_BIT 8
3808	/** Condition code 1. */
3809	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3810	#define X86_FSW_C1_BIT 9
3811	/** Condition code 2. */
3812	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3813	#define X86_FSW_C2_BIT 10
3814	/** Top of the stack mask. */
3815	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3816	/** TOP shift value. */
3817	#define X86_FSW_TOP_SHIFT 11
3818	/** Mask for getting TOP value after shifting it right. */
3819	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3820	/** Get the TOP value. */
3821	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3822	/** Get the TOP value offsetted by a_iSt (0-7). */
3823	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3824	/** Condition code 3. */
3825	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3826	#define X86_FSW_C3_BIT 14
3827	/** Mask of exceptions flags, including the summary bit. */
3828	#define X86_FSW_C_MASK UINT16_C(0x4700)
3829	/** FPU busy. */
3830	#define X86_FSW_B RT_BIT_32(15)
3831	/** For use with FPREM and FPREM1. */
3832	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3833	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3834	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3835	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3836	/** For use with FPREM and FPREM1. */
3837	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3838	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3839	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3840	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3841	/** @} */
3842
3843
3844	/** @name FPU control word flags.
3845	* @{ */
3846	/** Exception Mask: Invalid operation. */
3847	#define X86_FCW_IM RT_BIT_32(0)
3848	#define X86_FCW_IM_BIT 0
3849	/** Exception Mask: Denormalized operand. */
3850	#define X86_FCW_DM RT_BIT_32(1)
3851	#define X86_FCW_DM_BIT 1
3852	/** Exception Mask: Zero divide. */
3853	#define X86_FCW_ZM RT_BIT_32(2)
3854	#define X86_FCW_ZM_BIT 2
3855	/** Exception Mask: Overflow. */
3856	#define X86_FCW_OM RT_BIT_32(3)
3857	#define X86_FCW_OM_BIT 3
3858	/** Exception Mask: Underflow. */
3859	#define X86_FCW_UM RT_BIT_32(4)
3860	#define X86_FCW_UM_BIT 4
3861	/** Exception Mask: Precision. */
3862	#define X86_FCW_PM RT_BIT_32(5)
3863	#define X86_FCW_PM_BIT 5
3864	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3865	* @remarks This includes reserved bit 6. */
3866	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3867	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3868	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3869	/** Precision control mask. */
3870	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3871	/** Precision control shift. */
3872	#define X86_FCW_PC_SHIFT 8
3873	/** Precision control: 24-bit. */
3874	#define X86_FCW_PC_24 UINT16_C(0x0000)
3875	/** Precision control: Reserved. */
3876	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3877	/** Precision control: 53-bit. */
3878	#define X86_FCW_PC_53 UINT16_C(0x0200)
3879	/** Precision control: 64-bit. */
3880	#define X86_FCW_PC_64 UINT16_C(0x0300)
3881	/** Rounding control mask. */
3882	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3883	/** Rounding control shift. */
3884	#define X86_FCW_RC_SHIFT 10
3885	/** Rounding control: To nearest. */
3886	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3887	/** Rounding control: Down. */
3888	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3889	/** Rounding control: Up. */
3890	#define X86_FCW_RC_UP UINT16_C(0x0800)
3891	/** Rounding control: Towards zero. */
3892	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3893	/** Infinity control mask - obsolete, 8087 & 287 only. */
3894	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3895	/** Infinity control: Affine - positive infinity is distictly different from
3896	* negative infinity.
3897	* @note 8087, 287 only */
3898	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3899	/** Infinity control: Projective - positive and negative infinity are the
3900	* same (sign ignored).
3901	* @note 8087, 287 only */
3902	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3903	/** Bits which should be zero, apparently. */
3904	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3905	/** @} */
3906
3907	/** @name SSE MXCSR
3908	* @{ */
3909	/** Exception Flag: Invalid operation. */
3910	#define X86_MXCSR_IE RT_BIT_32(0)
3911	#define X86_MXCSR_IE_BIT 0
3912	/** Exception Flag: Denormalized operand. */
3913	#define X86_MXCSR_DE RT_BIT_32(1)
3914	#define X86_MXCSR_DE_BIT 1
3915	/** Exception Flag: Zero divide. */
3916	#define X86_MXCSR_ZE RT_BIT_32(2)
3917	#define X86_MXCSR_ZE_BIT 2
3918	/** Exception Flag: Overflow. */
3919	#define X86_MXCSR_OE RT_BIT_32(3)
3920	#define X86_MXCSR_OE_BIT 3
3921	/** Exception Flag: Underflow. */
3922	#define X86_MXCSR_UE RT_BIT_32(4)
3923	#define X86_MXCSR_UE_BIT 4
3924	/** Exception Flag: Precision. */
3925	#define X86_MXCSR_PE RT_BIT_32(5)
3926	#define X86_MXCSR_PE_BIT 5
3927	/** Exception Flags: mask */
3928	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3929
3930	/** Denormals are zero. */
3931	#define X86_MXCSR_DAZ RT_BIT_32(6)
3932	#define X86_MXCSR_DAZ_BIT 6
3933
3934	/** Exception Mask: Invalid operation. */
3935	#define X86_MXCSR_IM RT_BIT_32(7)
3936	#define X86_MXCSR_IM_BIT 7
3937	/** Exception Mask: Denormalized operand. */
3938	#define X86_MXCSR_DM RT_BIT_32(8)
3939	#define X86_MXCSR_DM_BIT 8
3940	/** Exception Mask: Zero divide. */
3941	#define X86_MXCSR_ZM RT_BIT_32(9)
3942	#define X86_MXCSR_ZM_BIT 9
3943	/** Exception Mask: Overflow. */
3944	#define X86_MXCSR_OM RT_BIT_32(10)
3945	#define X86_MXCSR_OM_BIT 10
3946	/** Exception Mask: Underflow. */
3947	#define X86_MXCSR_UM RT_BIT_32(11)
3948	#define X86_MXCSR_UM_BIT 11
3949	/** Exception Mask: Precision. */
3950	#define X86_MXCSR_PM RT_BIT_32(12)
3951	#define X86_MXCSR_PM_BIT 12
3952	/** Exception Mask: mask. */
3953	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3954	/** Exception Mask: shift. */
3955	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3956
3957	/** Rounding control mask. */
3958	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3959	/** Rounding control shift. */
3960	#define X86_MXCSR_RC_SHIFT 13
3961	/** Rounding control: To nearest. */
3962	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3963	/** Rounding control: Down. */
3964	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3965	/** Rounding control: Up. */
3966	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3967	/** Rounding control: Towards zero. */
3968	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3969
3970	/** Flush-to-zero for masked underflow. */
3971	#define X86_MXCSR_FZ RT_BIT_32(15)
3972	#define X86_MXCSR_FZ_BIT 15
3973
3974	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3975	#define X86_MXCSR_MM RT_BIT_32(17)
3976	#define X86_MXCSR_MM_BIT 17
3977	/** Bits which should be zero, apparently. */
3978	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3979	/** @} */
3980
3981	#ifndef __ASSEMBLER__
3982
3983	/**
3984	* XSAVE header.
3985	*/
3986	typedef struct X86XSAVEHDR
3987	{
3988	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3989	uint64_t bmXState;
3990	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3991	uint64_t bmXComp;
3992	/** Reserved for furture extensions, probably MBZ. */
3993	uint64_t au64Reserved[6];
3994	} X86XSAVEHDR;
3995	# ifndef VBOX_FOR_DTRACE_LIB
3996	AssertCompileSize(X86XSAVEHDR, 64);
3997	# endif
3998	/** Pointer to an XSAVE header. */
3999	typedef X86XSAVEHDR *PX86XSAVEHDR;
4000	/** Pointer to a const XSAVE header. */
4001	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
4002
4003
4004	/**
4005	* The high 128-bit YMM register state (XSAVE_C_YMM).
4006	* (The lower 128-bits being in X86FXSTATE.)
4007	*/
4008	typedef struct X86XSAVEYMMHI
4009	{
4010	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
4011	X86XMMREG aYmmHi[16];
4012	} X86XSAVEYMMHI;
4013	# ifndef VBOX_FOR_DTRACE_LIB
4014	AssertCompileSize(X86XSAVEYMMHI, 256);
4015	# endif
4016	/** Pointer to a high 128-bit YMM register state. */
4017	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
4018	/** Pointer to a const high 128-bit YMM register state. */
4019	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
4020
4021	/**
4022	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
4023	*/
4024	typedef struct X86XSAVEBNDREGS
4025	{
4026	/** Array of registers (BND0...BND3). */
4027	struct
4028	{
4029	/** Lower bound. */
4030	uint64_t uLowerBound;
4031	/** Upper bound. */
4032	uint64_t uUpperBound;
4033	} aRegs[4];
4034	} X86XSAVEBNDREGS;
4035	# ifndef VBOX_FOR_DTRACE_LIB
4036	AssertCompileSize(X86XSAVEBNDREGS, 64);
4037	# endif
4038	/** Pointer to a MPX bound register state. */
4039	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
4040	/** Pointer to a const MPX bound register state. */
4041	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
4042
4043	/**
4044	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
4045	*/
4046	typedef struct X86XSAVEBNDCFG
4047	{
4048	uint64_t fConfig;
4049	uint64_t fStatus;
4050	} X86XSAVEBNDCFG;
4051	# ifndef VBOX_FOR_DTRACE_LIB
4052	AssertCompileSize(X86XSAVEBNDCFG, 16);
4053	# endif
4054	/** Pointer to a MPX bound config and status register state. */
4055	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
4056	/** Pointer to a const MPX bound config and status register state. */
4057	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
4058
4059	/**
4060	* AVX-512 opmask state (XSAVE_C_OPMASK).
4061	*/
4062	typedef struct X86XSAVEOPMASK
4063	{
4064	/** The K0..K7 values. */
4065	uint64_t aKRegs[8];
4066	} X86XSAVEOPMASK;
4067	# ifndef VBOX_FOR_DTRACE_LIB
4068	AssertCompileSize(X86XSAVEOPMASK, 64);
4069	# endif
4070	/** Pointer to a AVX-512 opmask state. */
4071	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
4072	/** Pointer to a const AVX-512 opmask state. */
4073	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
4074
4075	/**
4076	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
4077	*/
4078	typedef struct X86XSAVEZMMHI256
4079	{
4080	/** Upper 256-bits of ZMM0-15. */
4081	X86YMMREG aHi256Regs[16];
4082	} X86XSAVEZMMHI256;
4083	# ifndef VBOX_FOR_DTRACE_LIB
4084	AssertCompileSize(X86XSAVEZMMHI256, 512);
4085	# endif
4086	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
4087	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
4088	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
4089	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
4090
4091	/**
4092	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
4093	*/
4094	typedef struct X86XSAVEZMM16HI
4095	{
4096	/** ZMM16 thru ZMM31. */
4097	X86ZMMREG aRegs[16];
4098	} X86XSAVEZMM16HI;
4099	# ifndef VBOX_FOR_DTRACE_LIB
4100	AssertCompileSize(X86XSAVEZMM16HI, 1024);
4101	# endif
4102	/** Pointer to a state comprising ZMM16-32. */
4103	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
4104	/** Pointer to a const state comprising ZMM16-32. */
4105	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
4106
4107	/**
4108	* AMD Light weight profiling state (XSAVE_C_LWP).
4109	*
4110	* We probably won't play with this as AMD seems to be dropping from their "zen"
4111	* processor micro architecture.
4112	*/
4113	typedef struct X86XSAVELWP
4114	{
4115	/** Details when needed. */
4116	uint64_t auLater[128/8];
4117	} X86XSAVELWP;
4118	# ifndef VBOX_FOR_DTRACE_LIB
4119	AssertCompileSize(X86XSAVELWP, 128);
4120	# endif
4121
4122
4123	/**
4124	* x86 FPU/SSE/AVX/XXXX state.
4125	*
4126	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
4127	* changes to this structure.
4128	*/
4129	typedef struct X86XSAVEAREA
4130	{
4131	/** The x87 and SSE region (or legacy region if you like). */
4132	X86FXSTATE x87;
4133	/** The XSAVE header. */
4134	X86XSAVEHDR Hdr;
4135	/** Beyond the header, there isn't really a fixed layout, but we can
4136	generally assume the YMM (AVX) register extensions are present and
4137	follows immediately. */
4138	union
4139	{
4140	/** The high 128-bit AVX registers for easy access by IEM.
4141	* @note This ASSUMES they will always be here... */
4142	X86XSAVEYMMHI YmmHi;
4143
4144	/** This is a typical layout on intel CPUs (good for debuggers). */
4145	struct
4146	{
4147	X86XSAVEYMMHI YmmHi;
4148	X86XSAVEBNDREGS BndRegs;
4149	X86XSAVEBNDCFG BndCfg;
4150	uint8_t abFudgeToMatchDocs[0xB0];
4151	X86XSAVEOPMASK Opmask;
4152	X86XSAVEZMMHI256 ZmmHi256;
4153	X86XSAVEZMM16HI Zmm16Hi;
4154	} Intel;
4155
4156	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
4157	struct
4158	{
4159	X86XSAVEYMMHI YmmHi;
4160	X86XSAVELWP Lwp;
4161	} AmdBd;
4162
4163	/** To enbling static deployments that have a reasonable chance of working for
4164	* the next 3-6 CPU generations without running short on space, we allocate a
4165	* lot of extra space here, making the structure a round 8KB in size. This
4166	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
4167	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
4168	uint8_t ab[8192 - 512 - 64];
4169	} u;
4170	} X86XSAVEAREA;
4171	# ifndef VBOX_FOR_DTRACE_LIB
4172	AssertCompileSize(X86XSAVEAREA, 8192);
4173	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
4174	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
4175	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
4176	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
4177	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
4178	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
4179	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
4180	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
4181	# endif
4182	/** Pointer to a XSAVE area. */
4183	typedef X86XSAVEAREA *PX86XSAVEAREA;
4184	/** Pointer to a const XSAVE area. */
4185	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
4186
4187	#endif /* __ASSEMBLER__ */
4188
4189
4190	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
4191	* @{ */
4192	/** Bit 0 - x87 - Legacy FPU state (bit number) */
4193	#define XSAVE_C_X87_BIT 0
4194	/** Bit 0 - x87 - Legacy FPU state. */
4195	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
4196	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
4197	#define XSAVE_C_SSE_BIT 1
4198	/** Bit 1 - SSE - 128-bit SSE state. */
4199	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
4200	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
4201	#define XSAVE_C_YMM_BIT 2
4202	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
4203	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
4204	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
4205	#define XSAVE_C_BNDREGS_BIT 3
4206	/** Bit 3 - BNDREGS - MPX bound register state. */
4207	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
4208	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
4209	#define XSAVE_C_BNDCSR_BIT 4
4210	/** Bit 4 - BNDCSR - MPX bound config and status state. */
4211	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
4212	/** Bit 5 - Opmask - opmask state (bit number). */
4213	#define XSAVE_C_OPMASK_BIT 5
4214	/** Bit 5 - Opmask - opmask state. */
4215	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
4216	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
4217	#define XSAVE_C_ZMM_HI256_BIT 6
4218	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
4219	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
4220	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
4221	#define XSAVE_C_ZMM_16HI_BIT 7
4222	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
4223	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
4224	/** Bit 9 - PKRU - Protection-key state (bit number). */
4225	#define XSAVE_C_PKRU_BIT 9
4226	/** Bit 9 - PKRU - Protection-key state. */
4227	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
4228	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
4229	#define XSAVE_C_LWP_BIT 62
4230	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
4231	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
4232	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
4233	#define XSAVE_C_X_BIT 63
4234	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
4235	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
4236	/** @} */
4237
4238
4239
4240	/** @name Selector Descriptor
4241	* @{
4242	*/
4243
4244	#ifndef __ASSEMBLER__
4245	# ifndef VBOX_FOR_DTRACE_LIB
4246	/**
4247	* Descriptor attributes (as seen by VT-x).
4248	*/
4249	typedef struct X86DESCATTRBITS
4250	{
4251	/** 00 - Segment Type. */
4252	unsigned u4Type : 4;
4253	/** 04 - Descriptor Type. System(=0) or code/data selector */
4254	unsigned u1DescType : 1;
4255	/** 05 - Descriptor Privilege level. */
4256	unsigned u2Dpl : 2;
4257	/** 07 - Flags selector present(=1) or not. */
4258	unsigned u1Present : 1;
4259	/** 08 - Segment limit 16-19. */
4260	unsigned u4LimitHigh : 4;
4261	/** 0c - Available for system software. */
4262	unsigned u1Available : 1;
4263	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4264	unsigned u1Long : 1;
4265	/** 0e - This flags meaning depends on the segment type. Try make sense out
4266	* of the intel manual yourself. */
4267	unsigned u1DefBig : 1;
4268	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
4269	* clear byte. */
4270	unsigned u1Granularity : 1;
4271	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
4272	unsigned u1Unusable : 1;
4273	} X86DESCATTRBITS;
4274	# endif /* !VBOX_FOR_DTRACE_LIB */
4275	#endif /* !__ASSEMBLER__ */
4276
4277	/** @name X86DESCATTR masks
4278	* Fields X86DESCGENERIC::u4Type thru X86DESCGENERIC::u1Granularity (or
4279	* bits[55:40] if you like). The X86DESCATTR_UNUSABLE bit is an Intel addition.
4280	* @{ */
4281	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
4282	#define X86DESCATTR_DT UINT32_C(0x00000010) /*< Descriptor type: 0=system, 1=code/data /
4283	#define X86DESCATTR_DPL UINT32_C(0x00000060)
4284	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL bitfield. /
4285	#define X86DESCATTR_P UINT32_C(0x00000080)
4286	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4287	#define X86DESCATTR_AVL UINT32_C(0x00001000)
4288	#define X86DESCATTR_L UINT32_C(0x00002000)
4289	#define X86DESCATTR_D UINT32_C(0x00004000)
4290	#define X86DESCATTR_G UINT32_C(0x00008000)
4291	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4292	/** @} */
4293
4294
4295	#ifndef __ASSEMBLER__
4296	# pragma pack(1)
4297	typedef union X86DESCATTR
4298	{
4299	/** Unsigned integer view. */
4300	uint32_t u;
4301	# ifndef VBOX_FOR_DTRACE_LIB
4302	/** Normal view. */
4303	X86DESCATTRBITS n;
4304	# endif
4305	} X86DESCATTR;
4306	# pragma pack()
4307	/** Pointer to descriptor attributes. */
4308	typedef X86DESCATTR *PX86DESCATTR;
4309	/** Pointer to const descriptor attributes. */
4310	typedef const X86DESCATTR *PCX86DESCATTR;
4311	#endif /* !__ASSEMBLER__ */
4312
4313	#ifndef VBOX_FOR_DTRACE_LIB
4314
4315	#ifndef __ASSEMBLER__
4316	/**
4317	* Generic descriptor table entry
4318	*/
4319	# pragma pack(1)
4320	typedef struct X86DESCGENERIC
4321	{
4322	/** 00 - Limit - Low word. */
4323	unsigned u16LimitLow : 16;
4324	/** 10 - Base address - low word.
4325	* Don't try set this to 24 because MSC is doing stupid things then. */
4326	unsigned u16BaseLow : 16;
4327	/** 20 - Base address - first 8 bits of high word. */
4328	unsigned u8BaseHigh1 : 8;
4329	/** 28 - Segment Type. */
4330	unsigned u4Type : 4;
4331	/** 2c - Descriptor Type. System(=0) or code/data selector */
4332	unsigned u1DescType : 1;
4333	/** 2d - Descriptor Privilege level. */
4334	unsigned u2Dpl : 2;
4335	/** 2f - Flags selector present(=1) or not. */
4336	unsigned u1Present : 1;
4337	/** 30 - Segment limit 16-19. */
4338	unsigned u4LimitHigh : 4;
4339	/** 34 - Available for system software. */
4340	unsigned u1Available : 1;
4341	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4342	unsigned u1Long : 1;
4343	/** 36 - This flags meaning depends on the segment type. Try make sense out
4344	* of the intel manual yourself. */
4345	unsigned u1DefBig : 1;
4346	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4347	* clear byte. */
4348	unsigned u1Granularity : 1;
4349	/** 38 - Base address - highest 8 bits. */
4350	unsigned u8BaseHigh2 : 8;
4351	} X86DESCGENERIC;
4352	# pragma pack()
4353	/** Pointer to a generic descriptor entry. */
4354	typedef X86DESCGENERIC *PX86DESCGENERIC;
4355	/** Pointer to a const generic descriptor entry. */
4356	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4357	# endif /* !__ASSEMBLER__ */
4358
4359
4360	/** @name Bit offsets of X86DESCGENERIC members.
4361	* @{*/
4362	# define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4363	# define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4364	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4365	# define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4366	# define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4367	# define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4368	# define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4369	# define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4370	# define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4371	# define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4372	# define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4373	# define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4374	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4375	/** @} */
4376
4377
4378	/** @name LAR mask
4379	* @{ */
4380	# define X86LAR_F_TYPE UINT16_C( 0x0f00)
4381	# define X86LAR_F_DT UINT16_C( 0x1000)
4382	# define X86LAR_F_DPL UINT16_C( 0x6000)
4383	# define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4384	# define X86LAR_F_P UINT16_C( 0x8000)
4385	# define X86LAR_F_AVL UINT32_C(0x00100000)
4386	# define X86LAR_F_L UINT32_C(0x00200000)
4387	# define X86LAR_F_D UINT32_C(0x00400000)
4388	# define X86LAR_F_G UINT32_C(0x00800000)
4389	/** @} */
4390
4391
4392	# ifndef __ASSEMBLER__
4393	/**
4394	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4395	*/
4396	typedef struct X86DESCGATE
4397	{
4398	/** 00 - Target code segment offset - Low word.
4399	* Ignored if task-gate. */
4400	unsigned u16OffsetLow : 16;
4401	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4402	* TSS selector if task-gate. */
4403	unsigned u16Sel : 16;
4404	/** 20 - Number of parameters for a call-gate.
4405	* Ignored if interrupt-, trap- or task-gate. */
4406	unsigned u5ParmCount : 5;
4407	/** 25 - Reserved / ignored. */
4408	unsigned u3Reserved : 3;
4409	/** 28 - Segment Type. */
4410	unsigned u4Type : 4;
4411	/** 2c - Descriptor Type (0 = system). */
4412	unsigned u1DescType : 1;
4413	/** 2d - Descriptor Privilege level. */
4414	unsigned u2Dpl : 2;
4415	/** 2f - Flags selector present(=1) or not. */
4416	unsigned u1Present : 1;
4417	/** 30 - Target code segment offset - High word.
4418	* Ignored if task-gate. */
4419	unsigned u16OffsetHigh : 16;
4420	} X86DESCGATE;
4421	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4422	typedef X86DESCGATE *PX86DESCGATE;
4423	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4424	typedef const X86DESCGATE *PCX86DESCGATE;
4425	# endif /* !__ASSEMBLER__ */
4426
4427	#endif /* VBOX_FOR_DTRACE_LIB */
4428
4429	#ifndef __ASSEMBLER__
4430	/**
4431	* Descriptor table entry.
4432	*/
4433	# pragma pack(1)
4434	typedef union X86DESC
4435	{
4436	# ifndef VBOX_FOR_DTRACE_LIB
4437	/** Generic descriptor view. */
4438	X86DESCGENERIC Gen;
4439	/** Gate descriptor view. */
4440	X86DESCGATE Gate;
4441	# endif
4442	/** 8 bit unsigned integer view. */
4443	uint8_t au8[8];
4444	/** 16 bit unsigned integer view. */
4445	uint16_t au16[4];
4446	/** 32 bit unsigned integer view. */
4447	uint32_t au32[2];
4448	/** 64 bit unsigned integer view. */
4449	uint64_t au64[1];
4450	/** Unsigned integer view. */
4451	uint64_t u;
4452	} X86DESC;
4453	# ifndef VBOX_FOR_DTRACE_LIB
4454	AssertCompileSize(X86DESC, 8);
4455	# endif
4456	# pragma pack()
4457	/** Pointer to descriptor table entry. */
4458	typedef X86DESC *PX86DESC;
4459	/** Pointer to const descriptor table entry. */
4460	typedef const X86DESC *PCX86DESC;
4461	#endif /* !__ASSEMBLER__ */
4462
4463	/** @def X86DESC_BASE
4464	* Return the base address of a descriptor.
4465	*/
4466	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4467	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4468	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4469	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4470
4471	/** @def X86DESC_LIMIT
4472	* Return the limit of a descriptor.
4473	*/
4474	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4475	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4476	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4477
4478	/** @def X86DESC_LIMIT_G
4479	* Return the limit of a descriptor with the granularity bit taken into account.
4480	* @returns Selector limit (uint32_t).
4481	* @param a_pDesc Pointer to the descriptor.
4482	*/
4483	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4484	( (a_pDesc)->Gen.u1Granularity \
4485	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4486	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4487	)
4488
4489	/** @def X86DESC_GET_HID_ATTR
4490	* Get the descriptor attributes for the hidden register.
4491	*/
4492	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4493	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4494
4495	#ifndef __ASSEMBLER__
4496	# ifndef VBOX_FOR_DTRACE_LIB
4497
4498	/**
4499	* 64 bits generic descriptor table entry
4500	* Note: most of these bits have no meaning in long mode.
4501	*/
4502	# pragma pack(1)
4503	typedef struct X86DESC64GENERIC
4504	{
4505	/** Limit - Low word - IGNORED. */
4506	uint32_t u16LimitLow : 16;
4507	/** Base address - low word. - IGNORED
4508	* Don't try set this to 24 because MSC is doing stupid things then. */
4509	uint32_t u16BaseLow : 16;
4510	/** Base address - first 8 bits of high word. - IGNORED */
4511	uint32_t u8BaseHigh1 : 8;
4512	/** Segment Type. */
4513	uint32_t u4Type : 4;
4514	/** Descriptor Type. System(=0) or code/data selector */
4515	uint32_t u1DescType : 1;
4516	/** Descriptor Privilege level. */
4517	uint32_t u2Dpl : 2;
4518	/** Flags selector present(=1) or not. */
4519	uint32_t u1Present : 1;
4520	/** Segment limit 16-19. - IGNORED */
4521	uint32_t u4LimitHigh : 4;
4522	/** Available for system software. - IGNORED */
4523	uint32_t u1Available : 1;
4524	/** Long mode flag. */
4525	uint32_t u1Long : 1;
4526	/** This flags meaning depends on the segment type. Try make sense out
4527	* of the intel manual yourself. */
4528	uint32_t u1DefBig : 1;
4529	/** Granularity of the limit. If set 4KB granularity is used, if
4530	* clear byte. - IGNORED */
4531	uint32_t u1Granularity : 1;
4532	/** Base address - highest 8 bits. - IGNORED */
4533	uint32_t u8BaseHigh2 : 8;
4534	/** Base address - bits 63-32. */
4535	uint32_t u32BaseHigh3 : 32;
4536	uint32_t u8Reserved : 8;
4537	uint32_t u5Zeros : 5;
4538	uint32_t u19Reserved : 19;
4539	} X86DESC64GENERIC;
4540	# pragma pack()
4541	/** Pointer to a generic descriptor entry. */
4542	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4543	/** Pointer to a const generic descriptor entry. */
4544	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4545
4546	/**
4547	* System descriptor table entry (64 bits)
4548	*
4549	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4550	*/
4551	# pragma pack(1)
4552	typedef struct X86DESC64SYSTEM
4553	{
4554	/** Limit - Low word. */
4555	uint32_t u16LimitLow : 16;
4556	/** Base address - low word.
4557	* Don't try set this to 24 because MSC is doing stupid things then. */
4558	uint32_t u16BaseLow : 16;
4559	/** Base address - first 8 bits of high word. */
4560	uint32_t u8BaseHigh1 : 8;
4561	/** Segment Type. */
4562	uint32_t u4Type : 4;
4563	/** Descriptor Type. System(=0) or code/data selector */
4564	uint32_t u1DescType : 1;
4565	/** Descriptor Privilege level. */
4566	uint32_t u2Dpl : 2;
4567	/** Flags selector present(=1) or not. */
4568	uint32_t u1Present : 1;
4569	/** Segment limit 16-19. */
4570	uint32_t u4LimitHigh : 4;
4571	/** Available for system software. */
4572	uint32_t u1Available : 1;
4573	/** Reserved - 0. */
4574	uint32_t u1Reserved : 1;
4575	/** This flags meaning depends on the segment type. Try make sense out
4576	* of the intel manual yourself. */
4577	uint32_t u1DefBig : 1;
4578	/** Granularity of the limit. If set 4KB granularity is used, if
4579	* clear byte. */
4580	uint32_t u1Granularity : 1;
4581	/** Base address - bits 31-24. */
4582	uint32_t u8BaseHigh2 : 8;
4583	/** Base address - bits 63-32. */
4584	uint32_t u32BaseHigh3 : 32;
4585	uint32_t u8Reserved : 8;
4586	uint32_t u5Zeros : 5;
4587	uint32_t u19Reserved : 19;
4588	} X86DESC64SYSTEM;
4589	# pragma pack()
4590	/** Pointer to a system descriptor entry. */
4591	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4592	/** Pointer to a const system descriptor entry. */
4593	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4594
4595	/**
4596	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4597	*/
4598	typedef struct X86DESC64GATE
4599	{
4600	/** Target code segment offset - Low word. */
4601	uint32_t u16OffsetLow : 16;
4602	/** Target code segment selector. */
4603	uint32_t u16Sel : 16;
4604	/** Interrupt stack table for interrupt- and trap-gates.
4605	* Ignored by call-gates. */
4606	uint32_t u3IST : 3;
4607	/** Reserved / ignored. */
4608	uint32_t u5Reserved : 5;
4609	/** Segment Type. */
4610	uint32_t u4Type : 4;
4611	/** Descriptor Type (0 = system). */
4612	uint32_t u1DescType : 1;
4613	/** Descriptor Privilege level. */
4614	uint32_t u2Dpl : 2;
4615	/** Flags selector present(=1) or not. */
4616	uint32_t u1Present : 1;
4617	/** Target code segment offset - High word.
4618	* Ignored if task-gate. */
4619	uint32_t u16OffsetHigh : 16;
4620	/** Target code segment offset - Top dword.
4621	* Ignored if task-gate. */
4622	uint32_t u32OffsetTop : 32;
4623	/** Reserved / ignored / must be zero.
4624	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4625	uint32_t u32Reserved : 32;
4626	} X86DESC64GATE;
4627	AssertCompileSize(X86DESC64GATE, 16);
4628	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4629	typedef X86DESC64GATE *PX86DESC64GATE;
4630	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4631	typedef const X86DESC64GATE *PCX86DESC64GATE;
4632
4633	# endif /* VBOX_FOR_DTRACE_LIB */
4634
4635	/**
4636	* Descriptor table entry.
4637	*/
4638	# pragma pack(1)
4639	typedef union X86DESC64
4640	{
4641	# ifndef VBOX_FOR_DTRACE_LIB
4642	/** Generic descriptor view. */
4643	X86DESC64GENERIC Gen;
4644	/** System descriptor view. */
4645	X86DESC64SYSTEM System;
4646	/** Gate descriptor view. */
4647	X86DESC64GATE Gate;
4648	# endif
4649
4650	/** 8 bit unsigned integer view. */
4651	uint8_t au8[16];
4652	/** 16 bit unsigned integer view. */
4653	uint16_t au16[8];
4654	/** 32 bit unsigned integer view. */
4655	uint32_t au32[4];
4656	/** 64 bit unsigned integer view. */
4657	uint64_t au64[2];
4658	} X86DESC64;
4659	# ifndef VBOX_FOR_DTRACE_LIB
4660	AssertCompileSize(X86DESC64, 16);
4661	# endif
4662	# pragma pack()
4663	/** Pointer to descriptor table entry. */
4664	typedef X86DESC64 *PX86DESC64;
4665	/** Pointer to const descriptor table entry. */
4666	typedef const X86DESC64 *PCX86DESC64;
4667
4668	/** @def X86DESC64_BASE
4669	* Return the base of a 64-bit descriptor.
4670	*/
4671	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4672	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4673	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4674	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4675	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4676
4677
4678
4679	/** @name Host system descriptor table entry - Use with care!
4680	* @{ */
4681	/** Host system descriptor table entry. */
4682	#if HC_ARCH_BITS == 64
4683	typedef X86DESC64 X86DESCHC;
4684	#else
4685	typedef X86DESC X86DESCHC;
4686	#endif
4687	/** Pointer to a host system descriptor table entry. */
4688	#if HC_ARCH_BITS == 64
4689	typedef PX86DESC64 PX86DESCHC;
4690	#else
4691	typedef PX86DESC PX86DESCHC;
4692	#endif
4693	/** Pointer to a const host system descriptor table entry. */
4694	#if HC_ARCH_BITS == 64
4695	typedef PCX86DESC64 PCX86DESCHC;
4696	#else
4697	typedef PCX86DESC PCX86DESCHC;
4698	#endif
4699	/** @} */
4700
4701	#endif /* !__ASSEMBLER__ */
4702
4703
4704	/** @name Selector Descriptor Types.
4705	* @{
4706	*/
4707
4708	/** @name Non-System Selector Types.
4709	* @{ */
4710	/** Code(=set)/Data(=clear) bit. */
4711	#define X86_SEL_TYPE_CODE 8
4712	/** Memory(=set)/System(=clear) bit. */
4713	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4714	/** Accessed bit. */
4715	#define X86_SEL_TYPE_ACCESSED 1
4716	/** Expand down bit (for data selectors only). */
4717	#define X86_SEL_TYPE_DOWN 4
4718	/** Conforming bit (for code selectors only). */
4719	#define X86_SEL_TYPE_CONF 4
4720	/** Write bit (for data selectors only). */
4721	#define X86_SEL_TYPE_WRITE 2
4722	/** Read bit (for code selectors only). */
4723	#define X86_SEL_TYPE_READ 2
4724	/** The bit number of the code segment read bit (relative to u4Type). */
4725	#define X86_SEL_TYPE_READ_BIT 1
4726
4727	/** Read only selector type. */
4728	#define X86_SEL_TYPE_RO 0
4729	/** Accessed read only selector type. */
4730	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4731	/** Read write selector type. */
4732	#define X86_SEL_TYPE_RW 2
4733	/** Accessed read write selector type. */
4734	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4735	/** Expand down read only selector type. */
4736	#define X86_SEL_TYPE_RO_DOWN 4
4737	/** Accessed expand down read only selector type. */
4738	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4739	/** Expand down read write selector type. */
4740	#define X86_SEL_TYPE_RW_DOWN 6
4741	/** Accessed expand down read write selector type. */
4742	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4743	/** Execute only selector type. */
4744	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4745	/** Accessed execute only selector type. */
4746	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4747	/** Execute and read selector type. */
4748	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4749	/** Accessed execute and read selector type. */
4750	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4751	/** Conforming execute only selector type. */
4752	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4753	/** Accessed Conforming execute only selector type. */
4754	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4755	/** Conforming execute and write selector type. */
4756	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4757	/** Accessed Conforming execute and write selector type. */
4758	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4759	/** @} */
4760
4761
4762	/** @name System Selector Types.
4763	* @{ */
4764	/** The TSS busy bit mask. */
4765	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4766
4767	/** Undefined system selector type. */
4768	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4769	/** 286 TSS selector. */
4770	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4771	/** LDT selector. */
4772	#define X86_SEL_TYPE_SYS_LDT 2
4773	/** 286 TSS selector - Busy. */
4774	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4775	/** 286 Callgate selector. */
4776	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4777	/** Taskgate selector. */
4778	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4779	/** 286 Interrupt gate selector. */
4780	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4781	/** 286 Trapgate selector. */
4782	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4783	/** Undefined system selector. */
4784	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4785	/** 386 TSS selector. */
4786	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4787	/** Undefined system selector. */
4788	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4789	/** 386 TSS selector - Busy. */
4790	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4791	/** 386 Callgate selector. */
4792	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4793	/** Undefined system selector. */
4794	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4795	/** 386 Interruptgate selector. */
4796	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4797	/** 386 Trapgate selector. */
4798	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4799	/** @} */
4800
4801	/** @name AMD64 System Selector Types.
4802	* @{ */
4803	/** LDT selector. */
4804	#define AMD64_SEL_TYPE_SYS_LDT 2
4805	/** TSS selector - Busy. */
4806	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4807	/** TSS selector - Busy. */
4808	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4809	/** Callgate selector. */
4810	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4811	/** Interruptgate selector. */
4812	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4813	/** Trapgate selector. */
4814	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4815	/** @} */
4816
4817	/** @} */
4818
4819
4820	/** @name Descriptor Table Entry Flag Masks.
4821	* These are for the 2nd 32-bit word of a descriptor.
4822	* @{ */
4823	/** Bits 8-11 - TYPE - Descriptor type mask. */
4824	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4825	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4826	#define X86_DESC_S RT_BIT_32(12)
4827	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4828	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4829	/** Bit 15 - P - Present. */
4830	#define X86_DESC_P RT_BIT_32(15)
4831	/** Bit 20 - AVL - Available for system software. */
4832	#define X86_DESC_AVL RT_BIT_32(20)
4833	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4834	#define X86_DESC_DB RT_BIT_32(22)
4835	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4836	* used, if clear byte. */
4837	#define X86_DESC_G RT_BIT_32(23)
4838	/** @} */
4839
4840	/** @} */
4841
4842
4843	/** @name Task Segments.
4844	* @{
4845	*/
4846
4847	/**
4848	* The minimum TSS descriptor limit for 286 tasks.
4849	*/
4850	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4851
4852	/**
4853	* The minimum TSS descriptor segment limit for 386 tasks.
4854	*/
4855	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4856
4857	#ifndef __ASSEMBLER__
4858
4859	/**
4860	* 16-bit Task Segment (TSS).
4861	*/
4862	# pragma pack(1)
4863	typedef struct X86TSS16
4864	{
4865	/** Back link to previous task. (static) */
4866	RTSEL selPrev;
4867	/** Ring-0 stack pointer. (static) */
4868	uint16_t sp0;
4869	/** Ring-0 stack segment. (static) */
4870	RTSEL ss0;
4871	/** Ring-1 stack pointer. (static) */
4872	uint16_t sp1;
4873	/** Ring-1 stack segment. (static) */
4874	RTSEL ss1;
4875	/** Ring-2 stack pointer. (static) */
4876	uint16_t sp2;
4877	/** Ring-2 stack segment. (static) */
4878	RTSEL ss2;
4879	/** IP before task switch. */
4880	uint16_t ip;
4881	/** FLAGS before task switch. */
4882	uint16_t flags;
4883	/** AX before task switch. */
4884	uint16_t ax;
4885	/** CX before task switch. */
4886	uint16_t cx;
4887	/** DX before task switch. */
4888	uint16_t dx;
4889	/** BX before task switch. */
4890	uint16_t bx;
4891	/** SP before task switch. */
4892	uint16_t sp;
4893	/** BP before task switch. */
4894	uint16_t bp;
4895	/** SI before task switch. */
4896	uint16_t si;
4897	/** DI before task switch. */
4898	uint16_t di;
4899	/** ES before task switch. */
4900	RTSEL es;
4901	/** CS before task switch. */
4902	RTSEL cs;
4903	/** SS before task switch. */
4904	RTSEL ss;
4905	/** DS before task switch. */
4906	RTSEL ds;
4907	/** LDTR before task switch. */
4908	RTSEL selLdt;
4909	} X86TSS16;
4910	# ifndef VBOX_FOR_DTRACE_LIB
4911	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4912	# endif
4913	# pragma pack()
4914	/** Pointer to a 16-bit task segment. */
4915	typedef X86TSS16 *PX86TSS16;
4916	/** Pointer to a const 16-bit task segment. */
4917	typedef const X86TSS16 *PCX86TSS16;
4918
4919
4920	/**
4921	* 32-bit Task Segment (TSS).
4922	*/
4923	# pragma pack(1)
4924	typedef struct X86TSS32
4925	{
4926	/** Back link to previous task. (static) */
4927	RTSEL selPrev;
4928	uint16_t padding1;
4929	/** Ring-0 stack pointer. (static) */
4930	uint32_t esp0;
4931	/** Ring-0 stack segment. (static) */
4932	RTSEL ss0;
4933	uint16_t padding_ss0;
4934	/** Ring-1 stack pointer. (static) */
4935	uint32_t esp1;
4936	/** Ring-1 stack segment. (static) */
4937	RTSEL ss1;
4938	uint16_t padding_ss1;
4939	/** Ring-2 stack pointer. (static) */
4940	uint32_t esp2;
4941	/** Ring-2 stack segment. (static) */
4942	RTSEL ss2;
4943	uint16_t padding_ss2;
4944	/** Page directory for the task. (static) */
4945	uint32_t cr3;
4946	/** EIP before task switch. */
4947	uint32_t eip;
4948	/** EFLAGS before task switch. */
4949	uint32_t eflags;
4950	/** EAX before task switch. */
4951	uint32_t eax;
4952	/** ECX before task switch. */
4953	uint32_t ecx;
4954	/** EDX before task switch. */
4955	uint32_t edx;
4956	/** EBX before task switch. */
4957	uint32_t ebx;
4958	/** ESP before task switch. */
4959	uint32_t esp;
4960	/** EBP before task switch. */
4961	uint32_t ebp;
4962	/** ESI before task switch. */
4963	uint32_t esi;
4964	/** EDI before task switch. */
4965	uint32_t edi;
4966	/** ES before task switch. */
4967	RTSEL es;
4968	uint16_t padding_es;
4969	/** CS before task switch. */
4970	RTSEL cs;
4971	uint16_t padding_cs;
4972	/** SS before task switch. */
4973	RTSEL ss;
4974	uint16_t padding_ss;
4975	/** DS before task switch. */
4976	RTSEL ds;
4977	uint16_t padding_ds;
4978	/** FS before task switch. */
4979	RTSEL fs;
4980	uint16_t padding_fs;
4981	/** GS before task switch. */
4982	RTSEL gs;
4983	uint16_t padding_gs;
4984	/** LDTR before task switch. */
4985	RTSEL selLdt;
4986	uint16_t padding_ldt;
4987	/** Debug trap flag */
4988	uint16_t fDebugTrap;
4989	/** Offset relative to the TSS of the start of the I/O Bitmap
4990	* and the end of the interrupt redirection bitmap. */
4991	uint16_t offIoBitmap;
4992	} X86TSS32;
4993	# pragma pack()
4994	/** Pointer to task segment. */
4995	typedef X86TSS32 *PX86TSS32;
4996	/** Pointer to const task segment. */
4997	typedef const X86TSS32 *PCX86TSS32;
4998	# ifndef VBOX_FOR_DTRACE_LIB
4999	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
5000	AssertCompileMemberOffset(X86TSS32, cr3, 28);
5001	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
5002	# endif
5003
5004	/**
5005	* 64-bit Task segment.
5006	*/
5007	# pragma pack(1)
5008	typedef struct X86TSS64
5009	{
5010	/** Reserved. */
5011	uint32_t u32Reserved;
5012	/** Ring-0 stack pointer. (static) */
5013	uint64_t rsp0;
5014	/** Ring-1 stack pointer. (static) */
5015	uint64_t rsp1;
5016	/** Ring-2 stack pointer. (static) */
5017	uint64_t rsp2;
5018	/** Reserved. */
5019	uint32_t u32Reserved2[2];
5020	/* IST */
5021	uint64_t ist1;
5022	uint64_t ist2;
5023	uint64_t ist3;
5024	uint64_t ist4;
5025	uint64_t ist5;
5026	uint64_t ist6;
5027	uint64_t ist7;
5028	/* Reserved. */
5029	uint16_t u16Reserved[5];
5030	/** Offset relative to the TSS of the start of the I/O Bitmap
5031	* and the end of the interrupt redirection bitmap. */
5032	uint16_t offIoBitmap;
5033	} X86TSS64;
5034	# pragma pack()
5035	/** Pointer to a 64-bit task segment. */
5036	typedef X86TSS64 *PX86TSS64;
5037	/** Pointer to a const 64-bit task segment. */
5038	typedef const X86TSS64 *PCX86TSS64;
5039	# ifndef VBOX_FOR_DTRACE_LIB
5040	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
5041	# endif
5042
5043	#endif /* !__ASSEMBLER__ */
5044
5045	/** @} */
5046
5047
5048	/** @name Selectors.
5049	* @{
5050	*/
5051
5052	/**
5053	* The shift used to convert a selector from and to index an index (C).
5054	*/
5055	#define X86_SEL_SHIFT 3
5056
5057	/**
5058	* The mask used to mask off the table indicator and RPL of an selector.
5059	*/
5060	#define X86_SEL_MASK 0xfff8U
5061
5062	/**
5063	* The mask used to mask off the RPL of an selector.
5064	* This is suitable for checking for NULL selectors.
5065	*/
5066	#define X86_SEL_MASK_OFF_RPL 0xfffcU
5067
5068	/**
5069	* The bit indicating that a selector is in the LDT and not in the GDT.
5070	*/
5071	#define X86_SEL_LDT 0x0004U
5072
5073	/**
5074	* The bit mask for getting the RPL of a selector.
5075	*/
5076	#define X86_SEL_RPL 0x0003U
5077
5078	/**
5079	* The mask covering both RPL and LDT.
5080	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
5081	* checks.
5082	*/
5083	#define X86_SEL_RPL_LDT 0x0007U
5084
5085	/** @} */
5086
5087
5088	#ifndef __ASSEMBLER__
5089	/**
5090	* x86 Exceptions/Faults/Traps.
5091	*/
5092	typedef enum X86XCPT
5093	{
5094	/** \#DE - Divide error. */
5095	X86_XCPT_DE = 0x00,
5096	/** \#DB - Debug event (single step, DRx, ..) */
5097	X86_XCPT_DB = 0x01,
5098	/** NMI - Non-Maskable Interrupt */
5099	X86_XCPT_NMI = 0x02,
5100	/** \#BP - Breakpoint (INT3). */
5101	X86_XCPT_BP = 0x03,
5102	/** \#OF - Overflow (INTO). */
5103	X86_XCPT_OF = 0x04,
5104	/** \#BR - Bound range exceeded (BOUND). */
5105	X86_XCPT_BR = 0x05,
5106	/** \#UD - Undefined opcode. */
5107	X86_XCPT_UD = 0x06,
5108	/** \#NM - Device not available (math coprocessor device). */
5109	X86_XCPT_NM = 0x07,
5110	/** \#DF - Double fault. */
5111	X86_XCPT_DF = 0x08,
5112	/** ??? - Coprocessor segment overrun (obsolete). */
5113	X86_XCPT_CO_SEG_OVERRUN = 0x09,
5114	/** \#TS - Taskswitch (TSS). */
5115	X86_XCPT_TS = 0x0a,
5116	/** \#NP - Segment no present. */
5117	X86_XCPT_NP = 0x0b,
5118	/** \#SS - Stack segment fault. */
5119	X86_XCPT_SS = 0x0c,
5120	/** \#GP - General protection fault. */
5121	X86_XCPT_GP = 0x0d,
5122	/** \#PF - Page fault. */
5123	X86_XCPT_PF = 0x0e,
5124	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
5125	/** \#MF - Math fault (FPU). */
5126	X86_XCPT_MF = 0x10,
5127	/** \#AC - Alignment check. */
5128	X86_XCPT_AC = 0x11,
5129	/** \#MC - Machine check. */
5130	X86_XCPT_MC = 0x12,
5131	/** \#XF - SIMD Floating-Point Exception. */
5132	X86_XCPT_XF = 0x13,
5133	/** \#VE - Virtualization Exception (Intel only). */
5134	X86_XCPT_VE = 0x14,
5135	/** \#CP - Control Protection Exception. */
5136	X86_XCPT_CP = 0x15,
5137	/** \#VC - VMM Communication Exception (AMD only). */
5138	X86_XCPT_VC = 0x1d,
5139	/** \#SX - Security Exception (AMD only). */
5140	X86_XCPT_SX = 0x1e
5141	} X86XCPT;
5142	/** Pointer to a x86 exception code. */
5143	typedef X86XCPT *PX86XCPT;
5144	/** Pointer to a const x86 exception code. */
5145	typedef const X86XCPT *PCX86XCPT;
5146	#endif /* !__ASSEMBLER__ */
5147	/** The last valid (currently reserved) exception value. */
5148	#define X86_XCPT_LAST 0x1f
5149
5150
5151	/** @name Trap Error Codes
5152	* @{
5153	*/
5154	/** External indicator. */
5155	#define X86_TRAP_ERR_EXTERNAL 1
5156	/** IDT indicator. */
5157	#define X86_TRAP_ERR_IDT 2
5158	/** Descriptor table indicator - If set LDT, if clear GDT. */
5159	#define X86_TRAP_ERR_TI 4
5160	/** Mask for getting the selector. */
5161	#define X86_TRAP_ERR_SEL_MASK 0xfff8
5162	/** Shift for getting the selector table index (C type index). */
5163	#define X86_TRAP_ERR_SEL_SHIFT 3
5164	/** @} */
5165
5166
5167	/** @name \#PF Trap Error Codes
5168	* @{
5169	*/
5170	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
5171	#define X86_TRAP_PF_P RT_BIT_32(0)
5172	/** Bit 1 - R/W - Read (clear) or write (set) access. */
5173	#define X86_TRAP_PF_RW RT_BIT_32(1)
5174	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
5175	#define X86_TRAP_PF_US RT_BIT_32(2)
5176	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
5177	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
5178	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
5179	#define X86_TRAP_PF_ID RT_BIT_32(4)
5180	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
5181	#define X86_TRAP_PF_PK RT_BIT_32(5)
5182	/** @} */
5183
5184	#ifndef __ASSEMBLER__
5185
5186	# pragma pack(1)
5187	/**
5188	* 16-bit IDTR.
5189	*/
5190	typedef struct X86IDTR16
5191	{
5192	/** Offset. */
5193	uint16_t offSel;
5194	/** Selector. */
5195	uint16_t uSel;
5196	} X86IDTR16, *PX86IDTR16;
5197	# pragma pack()
5198
5199	# pragma pack(1)
5200	/**
5201	* 32-bit IDTR/GDTR.
5202	*/
5203	typedef struct X86XDTR32
5204	{
5205	/** Size of the descriptor table. */
5206	uint16_t cb;
5207	/** Address of the descriptor table. */
5208	# ifndef VBOX_FOR_DTRACE_LIB
5209	uint32_t uAddr;
5210	# else
5211	uint16_t au16Addr[2];
5212	# endif
5213	} X86XDTR32, *PX86XDTR32;
5214	# pragma pack()
5215
5216	# pragma pack(1)
5217	/**
5218	* 64-bit IDTR/GDTR.
5219	*/
5220	typedef struct X86XDTR64
5221	{
5222	/** Size of the descriptor table. */
5223	uint16_t cb;
5224	/** Address of the descriptor table. */
5225	# ifndef VBOX_FOR_DTRACE_LIB
5226	uint64_t uAddr;
5227	# else
5228	uint16_t au16Addr[4];
5229	# endif
5230	} X86XDTR64, *PX86XDTR64;
5231	# pragma pack()
5232
5233	#endif /* !__ASSEMBLER__ */
5234
5235
5236	/** @name ModR/M
5237	* @{ */
5238	#define X86_MODRM_RM_MASK UINT8_C(0x07)
5239	#define X86_MODRM_REG_MASK UINT8_C(0x38)
5240	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
5241	#define X86_MODRM_REG_SHIFT 3
5242	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
5243	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
5244	#define X86_MODRM_MOD_SHIFT 6
5245
5246	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
5247	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
5248	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
5249	#define X86_MOD_REG 3 /*< Registers. /
5250
5251	#ifndef VBOX_FOR_DTRACE_LIB
5252	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
5253	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
5254	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
5255	/** @def X86_MODRM_MAKE
5256	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
5257	* @param a_Reg The register value (0..7).
5258	* @param a_RegMem The register or memory value (0..7). */
5259	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
5260	#endif
5261
5262	/** @} */
5263
5264	/** @name SIB
5265	* @{ */
5266	#define X86_SIB_BASE_MASK UINT8_C(0x07)
5267	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
5268	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
5269	#define X86_SIB_INDEX_SHIFT 3
5270	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
5271	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
5272	#define X86_SIB_SCALE_SHIFT 6
5273	#ifndef VBOX_FOR_DTRACE_LIB
5274	/** @def X86_SIB_MAKE
5275	* @param a_BaseReg The base register value (0..7).
5276	* @param a_IndexReg The index register value (0..7).
5277	* @param a_Scale The left shift (0..3) to be applied to the index
5278	* register (0 = none, 1 = x2, 2 = x4, 3 = x8).
5279	* */
5280	# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
5281	(((a_Scale) << X86_SIB_SCALE_SHIFT) \| ((a_IndexReg) << X86_SIB_INDEX_SHIFT) \| (a_BaseReg))
5282
5283	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
5284	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
5285	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
5286	#endif
5287	/** @} */
5288
5289	/** @name General register indexes.
5290	* @{ */
5291	#define X86_GREG_xAX 0
5292	#define X86_GREG_xCX 1
5293	#define X86_GREG_xDX 2
5294	#define X86_GREG_xBX 3
5295	#define X86_GREG_xSP 4
5296	#define X86_GREG_xBP 5
5297	#define X86_GREG_xSI 6
5298	#define X86_GREG_xDI 7
5299	#define X86_GREG_x8 8
5300	#define X86_GREG_x9 9
5301	#define X86_GREG_x10 10
5302	#define X86_GREG_x11 11
5303	#define X86_GREG_x12 12
5304	#define X86_GREG_x13 13
5305	#define X86_GREG_x14 14
5306	#define X86_GREG_x15 15
5307	/** @} */
5308	/** General register count. */
5309	#define X86_GREG_COUNT 16
5310
5311	/** @name X86_SREG_XXX - Segment register indexes.
5312	* @{ */
5313	#define X86_SREG_ES 0
5314	#define X86_SREG_CS 1
5315	#define X86_SREG_SS 2
5316	#define X86_SREG_DS 3
5317	#define X86_SREG_FS 4
5318	#define X86_SREG_GS 5
5319	/** @} */
5320	/** Segment register count. */
5321	#define X86_SREG_COUNT 6
5322
5323
5324	/** @name X86_OP_XXX - Prefixes
5325	* @{ */
5326	#define X86_OP_PRF_CS UINT8_C(0x2e)
5327	#define X86_OP_PRF_SS UINT8_C(0x36)
5328	#define X86_OP_PRF_DS UINT8_C(0x3e)
5329	#define X86_OP_PRF_ES UINT8_C(0x26)
5330	#define X86_OP_PRF_FS UINT8_C(0x64)
5331	#define X86_OP_PRF_GS UINT8_C(0x65)
5332	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5333	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5334	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5335	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5336	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5337	#define X86_OP_REX UINT8_C(0x40)
5338	#define X86_OP_REX_B UINT8_C(0x41)
5339	#define X86_OP_REX_X UINT8_C(0x42)
5340	#define X86_OP_REX_R UINT8_C(0x44)
5341	#define X86_OP_REX_W UINT8_C(0x48)
5342	#define X86_OP_VEX3 UINT8_C(0xc4)
5343	#define X86_OP_VEX2 UINT8_C(0xc5)
5344	/** @} */
5345
5346	/** @name X86_OP_VEX2_XXX - 2-byte VEX prefix helpers.
5347	* @{ */
5348	#define X86_OP_VEX2_BYTE1_P_MASK 0x3
5349	# define X86_OP_VEX2_BYTE1_P_NO_PRF 0
5350	# define X86_OP_VEX2_BYTE1_P_066H 1
5351	# define X86_OP_VEX2_BYTE1_P_0F3H 2
5352	# define X86_OP_VEX2_BYTE1_P_0F2H 3
5353	#define X86_OP_VEX2_BYTE1_L RT_BIT(2)
5354	#define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78
5355	#define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3
5356	#define X86_OP_VEX2_BYTE1_VVVV_NONE 15
5357	#define X86_OP_VEX2_BYTE1_R RT_BIT(7)
5358
5359	#define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5360	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5361	\| (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5362	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5363	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5364
5365	#define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \
5366	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5367	\| (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5368	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5369	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5370	/** @} */
5371
5372	/** @name X86_OP_VEX3_XXX - 3-byte VEX prefix helpers.
5373	* @{ */
5374	#define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f
5375	#define X86_OP_VEX3_BYTE1_B RT_BIT(5)
5376	#define X86_OP_VEX3_BYTE1_X RT_BIT(6)
5377	#define X86_OP_VEX3_BYTE1_R RT_BIT(7)
5378	#define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \
5379	( (uint8_t)(a_idxMap) \
5380	\| ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \
5381	\| ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \
5382	\| ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R))
5383
5384	#define X86_OP_VEX3_BYTE2_P_MASK 0x3
5385	# define X86_OP_VEX3_BYTE2_P_NO_PRF 0
5386	# define X86_OP_VEX3_BYTE2_P_066H 1
5387	# define X86_OP_VEX3_BYTE2_P_0F3H 2
5388	# define X86_OP_VEX3_BYTE2_P_0F2H 3
5389	#define X86_OP_VEX3_BYTE2_L RT_BIT(2)
5390	#define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78
5391	#define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3
5392	#define X86_OP_VEX3_BYTE2_VVVV_NONE 15
5393	#define X86_OP_VEX3_BYTE2_W RT_BIT(7)
5394
5395	/** @todo r=bird: Is the '& UINT8_C(0xf)' bit needed? You mask it again after
5396	* shifting. */
5397	#define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5398	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5399	\| ((~((uint8_t)(a_iSrcReg) & UINT8_C(0xf)) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \
5400	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5401	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5402
5403	#define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \
5404	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5405	\| (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
5406	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5407	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5408	/** @} */
5409
5410	/** @} */
5411
5412	#endif /* !IPRT_INCLUDED_x86_h */
5413

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