x86.h@ 38761

Last change on this file since 38761 was 37955, checked in by vboxsync, 13 years ago
Moved VBox/x86.h/mac to iprt/x86.h/mac.
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Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2011 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#include <iprt/types.h>
32	#include <iprt/assert.h>
33
34	/* Workaround for Solaris sys/regset.h defining CS, DS */
35	#ifdef RT_OS_SOLARIS
36	# undef CS
37	# undef DS
38	#endif
39
40	/** @defgroup grp_rt_x86 x86 Types and Definitions
41	* @ingroup grp_rt
42	* @{
43	*/
44
45	/**
46	* EFLAGS Bits.
47	*/
48	typedef struct X86EFLAGSBITS
49	{
50	/** Bit 0 - CF - Carry flag - Status flag. */
51	unsigned u1CF : 1;
52	/** Bit 1 - 1 - Reserved flag. */
53	unsigned u1Reserved0 : 1;
54	/** Bit 2 - PF - Parity flag - Status flag. */
55	unsigned u1PF : 1;
56	/** Bit 3 - 0 - Reserved flag. */
57	unsigned u1Reserved1 : 1;
58	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
59	unsigned u1AF : 1;
60	/** Bit 5 - 0 - Reserved flag. */
61	unsigned u1Reserved2 : 1;
62	/** Bit 6 - ZF - Zero flag - Status flag. */
63	unsigned u1ZF : 1;
64	/** Bit 7 - SF - Signed flag - Status flag. */
65	unsigned u1SF : 1;
66	/** Bit 8 - TF - Trap flag - System flag. */
67	unsigned u1TF : 1;
68	/** Bit 9 - IF - Interrupt flag - System flag. */
69	unsigned u1IF : 1;
70	/** Bit 10 - DF - Direction flag - Control flag. */
71	unsigned u1DF : 1;
72	/** Bit 11 - OF - Overflow flag - Status flag. */
73	unsigned u1OF : 1;
74	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
75	unsigned u2IOPL : 2;
76	/** Bit 14 - NT - Nested task flag - System flag. */
77	unsigned u1NT : 1;
78	/** Bit 15 - 0 - Reserved flag. */
79	unsigned u1Reserved3 : 1;
80	/** Bit 16 - RF - Resume flag - System flag. */
81	unsigned u1RF : 1;
82	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
83	unsigned u1VM : 1;
84	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
85	unsigned u1AC : 1;
86	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
87	unsigned u1VIF : 1;
88	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
89	unsigned u1VIP : 1;
90	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
91	unsigned u1ID : 1;
92	/** Bit 22-31 - 0 - Reserved flag. */
93	unsigned u10Reserved4 : 10;
94	} X86EFLAGSBITS;
95	/** Pointer to EFLAGS bits. */
96	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
97	/** Pointer to const EFLAGS bits. */
98	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
99
100	/**
101	* EFLAGS.
102	*/
103	typedef union X86EFLAGS
104	{
105	/** The plain unsigned view. */
106	uint32_t u;
107	/** The bitfield view. */
108	X86EFLAGSBITS Bits;
109	/** The 8-bit view. */
110	uint8_t au8[4];
111	/** The 16-bit view. */
112	uint16_t au16[2];
113	/** The 32-bit view. */
114	uint32_t au32[1];
115	/** The 32-bit view. */
116	uint32_t u32;
117	} X86EFLAGS;
118	/** Pointer to EFLAGS. */
119	typedef X86EFLAGS *PX86EFLAGS;
120	/** Pointer to const EFLAGS. */
121	typedef const X86EFLAGS *PCX86EFLAGS;
122
123	/**
124	* RFLAGS (32 upper bits are reserved).
125	*/
126	typedef union X86RFLAGS
127	{
128	/** The plain unsigned view. */
129	uint64_t u;
130	/** The bitfield view. */
131	X86EFLAGSBITS Bits;
132	/** The 8-bit view. */
133	uint8_t au8[8];
134	/** The 16-bit view. */
135	uint16_t au16[4];
136	/** The 32-bit view. */
137	uint32_t au32[2];
138	/** The 64-bit view. */
139	uint64_t au64[1];
140	/** The 64-bit view. */
141	uint64_t u64;
142	} X86RFLAGS;
143	/** Pointer to RFLAGS. */
144	typedef X86RFLAGS *PX86RFLAGS;
145	/** Pointer to const RFLAGS. */
146	typedef const X86RFLAGS *PCX86RFLAGS;
147
148
149	/** @name EFLAGS
150	* @{
151	*/
152	/** Bit 0 - CF - Carry flag - Status flag. */
153	#define X86_EFL_CF RT_BIT(0)
154	/** Bit 1 - Reserved, reads as 1. */
155	#define X86_EFL_1 RT_BIT(1)
156	/** Bit 2 - PF - Parity flag - Status flag. */
157	#define X86_EFL_PF RT_BIT(2)
158	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
159	#define X86_EFL_AF RT_BIT(4)
160	/** Bit 6 - ZF - Zero flag - Status flag. */
161	#define X86_EFL_ZF RT_BIT(6)
162	/** Bit 7 - SF - Signed flag - Status flag. */
163	#define X86_EFL_SF RT_BIT(7)
164	/** Bit 8 - TF - Trap flag - System flag. */
165	#define X86_EFL_TF RT_BIT(8)
166	/** Bit 9 - IF - Interrupt flag - System flag. */
167	#define X86_EFL_IF RT_BIT(9)
168	/** Bit 10 - DF - Direction flag - Control flag. */
169	#define X86_EFL_DF RT_BIT(10)
170	/** Bit 11 - OF - Overflow flag - Status flag. */
171	#define X86_EFL_OF RT_BIT(11)
172	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
173	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
174	/** Bit 14 - NT - Nested task flag - System flag. */
175	#define X86_EFL_NT RT_BIT(14)
176	/** Bit 16 - RF - Resume flag - System flag. */
177	#define X86_EFL_RF RT_BIT(16)
178	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
179	#define X86_EFL_VM RT_BIT(17)
180	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
181	#define X86_EFL_AC RT_BIT(18)
182	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
183	#define X86_EFL_VIF RT_BIT(19)
184	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
185	#define X86_EFL_VIP RT_BIT(20)
186	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
187	#define X86_EFL_ID RT_BIT(21)
188	/** IOPL shift. */
189	#define X86_EFL_IOPL_SHIFT 12
190	/** The the IOPL level from the flags. */
191	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
192	/** Bits restored by popf */
193	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
194	/** @} */
195
196
197	/** CPUID Feature information - ECX.
198	* CPUID query with EAX=1.
199	*/
200	typedef struct X86CPUIDFEATECX
201	{
202	/** Bit 0 - SSE3 - Supports SSE3 or not. */
203	unsigned u1SSE3 : 1;
204	/** Bit 1 - PCLMULQDQ. */
205	unsigned u1PCLMULQDQ : 1;
206	/** Bit 2 - DS Area 64-bit layout. */
207	unsigned u1DTE64 : 1;
208	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
209	unsigned u1Monitor : 1;
210	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
211	unsigned u1CPLDS : 1;
212	/** Bit 5 - VMX - Virtual Machine Technology. */
213	unsigned u1VMX : 1;
214	/** Bit 6 - SMX: Safer Mode Extensions. */
215	unsigned u1SMX : 1;
216	/** Bit 7 - EST - Enh. SpeedStep Tech. */
217	unsigned u1EST : 1;
218	/** Bit 8 - TM2 - Terminal Monitor 2. */
219	unsigned u1TM2 : 1;
220	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
221	unsigned u1SSSE3 : 1;
222	/** Bit 10 - CNTX-ID - L1 Context ID. */
223	unsigned u1CNTXID : 1;
224	/** Bit 11 - Reserved. */
225	unsigned u1Reserved1 : 1;
226	/** Bit 12 - FMA. */
227	unsigned u1FMA : 1;
228	/** Bit 13 - CX16 - CMPXCHG16B. */
229	unsigned u1CX16 : 1;
230	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
231	unsigned u1TPRUpdate : 1;
232	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
233	unsigned u1PDCM : 1;
234	/** Bit 16 - Reserved. */
235	unsigned u1Reserved2 : 1;
236	/** Bit 17 - PCID - Process-context identifiers. */
237	unsigned u1PCID : 1;
238	/** Bit 18 - Direct Cache Access. */
239	unsigned u1DCA : 1;
240	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
241	unsigned u1SSE4_1 : 1;
242	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
243	unsigned u1SSE4_2 : 1;
244	/** Bit 21 - x2APIC. */
245	unsigned u1x2APIC : 1;
246	/** Bit 22 - MOVBE - Supports MOVBE. */
247	unsigned u1MOVBE : 1;
248	/** Bit 23 - POPCNT - Supports POPCNT. */
249	unsigned u1POPCNT : 1;
250	/** Bit 24 - TSC-Deadline. */
251	unsigned u1TSCDEADLINE : 1;
252	/** Bit 25 - AES. */
253	unsigned u1AES : 1;
254	/** Bit 26 - XSAVE - Supports XSAVE. */
255	unsigned u1XSAVE : 1;
256	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
257	unsigned u1OSXSAVE : 1;
258	/** Bit 28 - AVX - Supports AVX instruction extensions. */
259	unsigned u1AVX : 1;
260	/** Bit 29 - 30 - Reserved */
261	unsigned u2Reserved3 : 2;
262	/** Bit 31 - Hypervisor present (we're a guest). */
263	unsigned u1HVP : 1;
264	} X86CPUIDFEATECX;
265	/** Pointer to CPUID Feature Information - ECX. */
266	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
267	/** Pointer to const CPUID Feature Information - ECX. */
268	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
269
270
271	/** CPUID Feature Information - EDX.
272	* CPUID query with EAX=1.
273	*/
274	typedef struct X86CPUIDFEATEDX
275	{
276	/** Bit 0 - FPU - x87 FPU on Chip. */
277	unsigned u1FPU : 1;
278	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
279	unsigned u1VME : 1;
280	/** Bit 2 - DE - Debugging extensions. */
281	unsigned u1DE : 1;
282	/** Bit 3 - PSE - Page Size Extension. */
283	unsigned u1PSE : 1;
284	/** Bit 4 - TSC - Time Stamp Counter. */
285	unsigned u1TSC : 1;
286	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
287	unsigned u1MSR : 1;
288	/** Bit 6 - PAE - Physical Address Extension. */
289	unsigned u1PAE : 1;
290	/** Bit 7 - MCE - Machine Check Exception. */
291	unsigned u1MCE : 1;
292	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
293	unsigned u1CX8 : 1;
294	/** Bit 9 - APIC - APIC On-Chip. */
295	unsigned u1APIC : 1;
296	/** Bit 10 - Reserved. */
297	unsigned u1Reserved1 : 1;
298	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
299	unsigned u1SEP : 1;
300	/** Bit 12 - MTRR - Memory Type Range Registers. */
301	unsigned u1MTRR : 1;
302	/** Bit 13 - PGE - PTE Global Bit. */
303	unsigned u1PGE : 1;
304	/** Bit 14 - MCA - Machine Check Architecture. */
305	unsigned u1MCA : 1;
306	/** Bit 15 - CMOV - Conditional Move Instructions. */
307	unsigned u1CMOV : 1;
308	/** Bit 16 - PAT - Page Attribute Table. */
309	unsigned u1PAT : 1;
310	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
311	unsigned u1PSE36 : 1;
312	/** Bit 18 - PSN - Processor Serial Number. */
313	unsigned u1PSN : 1;
314	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
315	unsigned u1CLFSH : 1;
316	/** Bit 20 - Reserved. */
317	unsigned u1Reserved2 : 1;
318	/** Bit 21 - DS - Debug Store. */
319	unsigned u1DS : 1;
320	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
321	unsigned u1ACPI : 1;
322	/** Bit 23 - MMX - Intel MMX 'Technology'. */
323	unsigned u1MMX : 1;
324	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
325	unsigned u1FXSR : 1;
326	/** Bit 25 - SSE - SSE Support. */
327	unsigned u1SSE : 1;
328	/** Bit 26 - SSE2 - SSE2 Support. */
329	unsigned u1SSE2 : 1;
330	/** Bit 27 - SS - Self Snoop. */
331	unsigned u1SS : 1;
332	/** Bit 28 - HTT - Hyper-Threading Technology. */
333	unsigned u1HTT : 1;
334	/** Bit 29 - TM - Thermal Monitor. */
335	unsigned u1TM : 1;
336	/** Bit 30 - Reserved - . */
337	unsigned u1Reserved3 : 1;
338	/** Bit 31 - PBE - Pending Break Enabled. */
339	unsigned u1PBE : 1;
340	} X86CPUIDFEATEDX;
341	/** Pointer to CPUID Feature Information - EDX. */
342	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
343	/** Pointer to const CPUID Feature Information - EDX. */
344	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
345
346	/** @name CPUID Vendor information.
347	* CPUID query with EAX=0.
348	* @{
349	*/
350	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
351	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
352	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
353
354	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
355	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
356	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
357	/** @} */
358
359
360	/** @name CPUID Feature information.
361	* CPUID query with EAX=1.
362	* @{
363	*/
364	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
365	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
366	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
367	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
368	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
369	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
370	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
371	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
372	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
373	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
374	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
375	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
376	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
377	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
378	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
379	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
380	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
381	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
382	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
383	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
384	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
385	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
386	/** ECX Bit 12 - FMA. */
387	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
388	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
389	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
390	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
391	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
392	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
393	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
394	/** ECX Bit 17 - PCID - Process-context identifiers. */
395	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
396	/** ECX Bit 18 - DCA - Direct Cache Access. */
397	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
398	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
399	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
400	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
401	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
402	/** ECX Bit 21 - x2APIC support. */
403	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
404	/** ECX Bit 22 - MOVBE instruction. */
405	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
406	/** ECX Bit 23 - POPCNT instruction. */
407	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
408	/** ECX Bir 24 - TSC-Deadline. */
409	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
410	/** ECX Bit 25 - AES instructions. */
411	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
412	/** ECX Bit 26 - XSAVE instruction. */
413	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
414	/** ECX Bit 27 - OSXSAVE instruction. */
415	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
416	/** ECX Bit 28 - AVX. */
417	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
418	/** ECX Bit 31 - Hypervisor Present (software only). */
419	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
420
421
422	/** Bit 0 - FPU - x87 FPU on Chip. */
423	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
424	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
425	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
426	/** Bit 2 - DE - Debugging extensions. */
427	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
428	/** Bit 3 - PSE - Page Size Extension. */
429	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
430	/** Bit 4 - TSC - Time Stamp Counter. */
431	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
432	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
433	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
434	/** Bit 6 - PAE - Physical Address Extension. */
435	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
436	/** Bit 7 - MCE - Machine Check Exception. */
437	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
438	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
439	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
440	/** Bit 9 - APIC - APIC On-Chip. */
441	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
442	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
443	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
444	/** Bit 12 - MTRR - Memory Type Range Registers. */
445	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
446	/** Bit 13 - PGE - PTE Global Bit. */
447	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
448	/** Bit 14 - MCA - Machine Check Architecture. */
449	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
450	/** Bit 15 - CMOV - Conditional Move Instructions. */
451	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
452	/** Bit 16 - PAT - Page Attribute Table. */
453	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
454	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
455	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
456	/** Bit 18 - PSN - Processor Serial Number. */
457	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
458	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
459	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
460	/** Bit 21 - DS - Debug Store. */
461	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
462	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
463	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
464	/** Bit 23 - MMX - Intel MMX Technology. */
465	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
466	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
467	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
468	/** Bit 25 - SSE - SSE Support. */
469	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
470	/** Bit 26 - SSE2 - SSE2 Support. */
471	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
472	/** Bit 27 - SS - Self Snoop. */
473	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
474	/** Bit 28 - HTT - Hyper-Threading Technology. */
475	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
476	/** Bit 29 - TM - Therm. Monitor. */
477	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
478	/** Bit 31 - PBE - Pending Break Enabled. */
479	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
480	/** @} */
481
482	/** @name CPUID mwait/monitor information.
483	* CPUID query with EAX=5.
484	* @{
485	*/
486	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
487	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
488	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
489	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
490	/** @} */
491
492
493	/** @name CPUID AMD Feature information.
494	* CPUID query with EAX=0x80000001.
495	* @{
496	*/
497	/** Bit 0 - FPU - x87 FPU on Chip. */
498	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
499	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
500	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
501	/** Bit 2 - DE - Debugging extensions. */
502	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
503	/** Bit 3 - PSE - Page Size Extension. */
504	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
505	/** Bit 4 - TSC - Time Stamp Counter. */
506	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
507	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
508	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
509	/** Bit 6 - PAE - Physical Address Extension. */
510	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
511	/** Bit 7 - MCE - Machine Check Exception. */
512	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
513	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
514	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
515	/** Bit 9 - APIC - APIC On-Chip. */
516	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
517	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
518	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
519	/** Bit 12 - MTRR - Memory Type Range Registers. */
520	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
521	/** Bit 13 - PGE - PTE Global Bit. */
522	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
523	/** Bit 14 - MCA - Machine Check Architecture. */
524	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
525	/** Bit 15 - CMOV - Conditional Move Instructions. */
526	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
527	/** Bit 16 - PAT - Page Attribute Table. */
528	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
529	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
530	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
531	/** Bit 20 - NX - AMD No-Execute Page Protection. */
532	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
533	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
534	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
535	/** Bit 23 - MMX - Intel MMX Technology. */
536	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
537	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
538	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
539	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
540	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
541	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
542	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
543	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
544	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
545	/** Bit 29 - LM - AMD Long Mode. */
546	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
547	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
548	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
549	/** Bit 31 - 3DNOW - AMD 3DNow. */
550	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
551
552	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
553	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
554	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
555	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
556	/** Bit 2 - SVM - AMD VM extensions. */
557	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
558	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
559	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
560	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
561	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
562	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
563	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
564	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
565	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
566	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
567	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
568	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
569	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
570	/** Bit 9 - OSVW - AMD OS visible workaround. */
571	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
572	/** Bit 10 - IBS - Instruct based sampling. */
573	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
574	/** Bit 11 - SSE5 - SSE5 instruction support. */
575	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
576	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
577	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
578	/** Bit 13 - WDT - AMD Watchdog timer support. */
579	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
580
581	/** @} */
582
583
584	/** @name CPUID AMD Feature information.
585	* CPUID query with EAX=0x80000007.
586	* @{
587	*/
588	/** Bit 0 - TS - Temperature Sensor. */
589	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
590	/** Bit 1 - FID - Frequency ID Control. */
591	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
592	/** Bit 2 - VID - Voltage ID Control. */
593	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
594	/** Bit 3 - TTP - THERMTRIP. */
595	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
596	/** Bit 4 - TM - Hardware Thermal Control. */
597	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
598	/** Bit 5 - STC - Software Thermal Control. */
599	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
600	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
601	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
602	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
603	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
604	/** Bit 8 - TSCINVAR - TSC Invariant. */
605	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
606	/** @} */
607
608
609	/** @name CR0
610	* @{ */
611	/** Bit 0 - PE - Protection Enabled */
612	#define X86_CR0_PE RT_BIT(0)
613	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
614	/** Bit 1 - MP - Monitor Coprocessor */
615	#define X86_CR0_MP RT_BIT(1)
616	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
617	/** Bit 2 - EM - Emulation. */
618	#define X86_CR0_EM RT_BIT(2)
619	#define X86_CR0_EMULATE_FPU RT_BIT(2)
620	/** Bit 3 - TS - Task Switch. */
621	#define X86_CR0_TS RT_BIT(3)
622	#define X86_CR0_TASK_SWITCH RT_BIT(3)
623	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
624	#define X86_CR0_ET RT_BIT(4)
625	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
626	/** Bit 5 - NE - Numeric error. */
627	#define X86_CR0_NE RT_BIT(5)
628	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
629	/** Bit 16 - WP - Write Protect. */
630	#define X86_CR0_WP RT_BIT(16)
631	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
632	/** Bit 18 - AM - Alignment Mask. */
633	#define X86_CR0_AM RT_BIT(18)
634	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
635	/** Bit 29 - NW - Not Write-though. */
636	#define X86_CR0_NW RT_BIT(29)
637	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
638	/** Bit 30 - WP - Cache Disable. */
639	#define X86_CR0_CD RT_BIT(30)
640	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
641	/** Bit 31 - PG - Paging. */
642	#define X86_CR0_PG RT_BIT(31)
643	#define X86_CR0_PAGING RT_BIT(31)
644	/** @} */
645
646
647	/** @name CR3
648	* @{ */
649	/** Bit 3 - PWT - Page-level Writes Transparent. */
650	#define X86_CR3_PWT RT_BIT(3)
651	/** Bit 4 - PCD - Page-level Cache Disable. */
652	#define X86_CR3_PCD RT_BIT(4)
653	/** Bits 12-31 - - Page directory page number. */
654	#define X86_CR3_PAGE_MASK (0xfffff000)
655	/** Bits 5-31 - - PAE Page directory page number. */
656	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
657	/** Bits 12-51 - - AMD64 Page directory page number. */
658	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
659	/** @} */
660
661
662	/** @name CR4
663	* @{ */
664	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
665	#define X86_CR4_VME RT_BIT(0)
666	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
667	#define X86_CR4_PVI RT_BIT(1)
668	/** Bit 2 - TSD - Time Stamp Disable. */
669	#define X86_CR4_TSD RT_BIT(2)
670	/** Bit 3 - DE - Debugging Extensions. */
671	#define X86_CR4_DE RT_BIT(3)
672	/** Bit 4 - PSE - Page Size Extension. */
673	#define X86_CR4_PSE RT_BIT(4)
674	/** Bit 5 - PAE - Physical Address Extension. */
675	#define X86_CR4_PAE RT_BIT(5)
676	/** Bit 6 - MCE - Machine-Check Enable. */
677	#define X86_CR4_MCE RT_BIT(6)
678	/** Bit 7 - PGE - Page Global Enable. */
679	#define X86_CR4_PGE RT_BIT(7)
680	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
681	#define X86_CR4_PCE RT_BIT(8)
682	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
683	#define X86_CR4_OSFSXR RT_BIT(9)
684	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
685	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
686	/** Bit 13 - VMXE - VMX mode is enabled. */
687	#define X86_CR4_VMXE RT_BIT(13)
688	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
689	#define X86_CR4_SMXE RT_BIT(14)
690	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
691	#define X86_CR4_PCIDE RT_BIT(17)
692	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
693	* extended states. */
694	#define X86_CR4_OSXSAVE RT_BIT(18)
695	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
696	#define X86_CR4_SMEP RT_BIT(20)
697	/** @} */
698
699
700	/** @name DR6
701	* @{ */
702	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
703	#define X86_DR6_B0 RT_BIT(0)
704	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
705	#define X86_DR6_B1 RT_BIT(1)
706	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
707	#define X86_DR6_B2 RT_BIT(2)
708	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
709	#define X86_DR6_B3 RT_BIT(3)
710	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
711	#define X86_DR6_BD RT_BIT(13)
712	/** Bit 14 - BS - Single step */
713	#define X86_DR6_BS RT_BIT(14)
714	/** Bit 15 - BT - Task switch. (TSS T bit.) */
715	#define X86_DR6_BT RT_BIT(15)
716	/** Value of DR6 after powerup/reset. */
717	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
718	/** @} */
719
720
721	/** @name DR7
722	* @{ */
723	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
724	#define X86_DR7_L0 RT_BIT(0)
725	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
726	#define X86_DR7_G0 RT_BIT(1)
727	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
728	#define X86_DR7_L1 RT_BIT(2)
729	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
730	#define X86_DR7_G1 RT_BIT(3)
731	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
732	#define X86_DR7_L2 RT_BIT(4)
733	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
734	#define X86_DR7_G2 RT_BIT(5)
735	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
736	#define X86_DR7_L3 RT_BIT(6)
737	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
738	#define X86_DR7_G3 RT_BIT(7)
739	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
740	#define X86_DR7_LE RT_BIT(8)
741	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
742	#define X86_DR7_GE RT_BIT(9)
743
744	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
745	* any DR register is accessed. */
746	#define X86_DR7_GD RT_BIT(13)
747	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
748	#define X86_DR7_RW0_MASK (3 << 16)
749	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
750	#define X86_DR7_LEN0_MASK (3 << 18)
751	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
752	#define X86_DR7_RW1_MASK (3 << 20)
753	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
754	#define X86_DR7_LEN1_MASK (3 << 22)
755	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
756	#define X86_DR7_RW2_MASK (3 << 24)
757	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
758	#define X86_DR7_LEN2_MASK (3 << 26)
759	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
760	#define X86_DR7_RW3_MASK (3 << 28)
761	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
762	#define X86_DR7_LEN3_MASK (3 << 30)
763
764	/** Bits which must be 1s. */
765	#define X86_DR7_MB1_MASK (RT_BIT(10))
766
767	/** Calcs the L bit of Nth breakpoint.
768	* @param iBp The breakpoint number [0..3].
769	*/
770	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
771
772	/** Calcs the G bit of Nth breakpoint.
773	* @param iBp The breakpoint number [0..3].
774	*/
775	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
776
777	/** @name Read/Write values.
778	* @{ */
779	/** Break on instruction fetch only. */
780	#define X86_DR7_RW_EO 0U
781	/** Break on write only. */
782	#define X86_DR7_RW_WO 1U
783	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
784	#define X86_DR7_RW_IO 2U
785	/** Break on read or write (but not instruction fetches). */
786	#define X86_DR7_RW_RW 3U
787	/** @} */
788
789	/** Shifts a X86_DR7_RW_* value to its right place.
790	* @param iBp The breakpoint number [0..3].
791	* @param fRw One of the X86_DR7_RW_* value.
792	*/
793	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
794
795	/** @name Length values.
796	* @{ */
797	#define X86_DR7_LEN_BYTE 0U
798	#define X86_DR7_LEN_WORD 1U
799	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
800	#define X86_DR7_LEN_DWORD 3U
801	/** @} */
802
803	/** Shifts a X86_DR7_LEN_* value to its right place.
804	* @param iBp The breakpoint number [0..3].
805	* @param cb One of the X86_DR7_LEN_* values.
806	*/
807	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
808
809	/** Fetch the breakpoint length bits from the DR7 value.
810	* @param uDR7 DR7 value
811	* @param iBp The breakpoint number [0..3].
812	*/
813	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
814
815	/** Mask used to check if any breakpoints are enabled. */
816	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
817
818	/** Mask used to check if any io breakpoints are set. */
819	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
820
821	/** Value of DR7 after powerup/reset. */
822	#define X86_DR7_INIT_VAL 0x400
823	/** @} */
824
825
826	/** @name Machine Specific Registers
827	* @{
828	*/
829
830	/** Time Stamp Counter. */
831	#define MSR_IA32_TSC 0x10
832
833	#define MSR_IA32_PLATFORM_ID 0x17
834
835	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
836	#define MSR_IA32_APICBASE 0x1b
837	#endif
838
839	/** CPU Feature control. */
840	#define MSR_IA32_FEATURE_CONTROL 0x3A
841	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
842	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
843
844	/** BIOS update trigger (microcode update). */
845	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
846
847	/** BIOS update signature (microcode). */
848	#define MSR_IA32_BIOS_SIGN_ID 0x8B
849
850	/** General performance counter no. 0. */
851	#define MSR_IA32_PMC0 0xC1
852	/** General performance counter no. 1. */
853	#define MSR_IA32_PMC1 0xC2
854	/** General performance counter no. 2. */
855	#define MSR_IA32_PMC2 0xC3
856	/** General performance counter no. 3. */
857	#define MSR_IA32_PMC3 0xC4
858
859	/** Nehalem power control. */
860	#define MSR_IA32_PLATFORM_INFO 0xCE
861
862	/** Get FSB clock status (Intel-specific). */
863	#define MSR_IA32_FSB_CLOCK_STS 0xCD
864
865	/** MTRR Capabilities. */
866	#define MSR_IA32_MTRR_CAP 0xFE
867
868
869	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
870	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
871	* R0 SS == CS + 8
872	* R3 CS == CS + 16
873	* R3 SS == CS + 24
874	*/
875	#define MSR_IA32_SYSENTER_CS 0x174
876	/** SYSENTER_ESP - the R0 ESP. */
877	#define MSR_IA32_SYSENTER_ESP 0x175
878	/** SYSENTER_EIP - the R0 EIP. */
879	#define MSR_IA32_SYSENTER_EIP 0x176
880	#endif
881
882	/** Machine Check Global Capabilities Register. */
883	#define MSR_IA32_MCP_CAP 0x179
884	/** Machine Check Global Status Register. */
885	#define MSR_IA32_MCP_STATUS 0x17A
886	/** Machine Check Global Control Register. */
887	#define MSR_IA32_MCP_CTRL 0x17B
888
889	/** Trace/Profile Resource Control (R/W) */
890	#define MSR_IA32_DEBUGCTL 0x1D9
891
892	/** Page Attribute Table. */
893	#define MSR_IA32_CR_PAT 0x277
894
895	/** Performance counter MSRs. (Intel only) */
896	#define MSR_IA32_PERFEVTSEL0 0x186
897	#define MSR_IA32_PERFEVTSEL1 0x187
898	#define MSR_IA32_FLEX_RATIO 0x194
899	#define MSR_IA32_PERF_STATUS 0x198
900	#define MSR_IA32_PERF_CTL 0x199
901	#define MSR_IA32_THERM_STATUS 0x19c
902
903	/** Enable misc. processor features (R/W). */
904	#define MSR_IA32_MISC_ENABLE 0x1A0
905	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
906	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
907	/** Automatic Thermal Control Circuit Enable (R/W). */
908	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
909	/** Performance Monitoring Available (R). */
910	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
911	/** Branch Trace Storage Unavailable (R/O). */
912	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
913	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
914	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
915	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
916	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
917	/** If MONITOR/MWAIT is supported (R/W). */
918	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
919	/** Limit CPUID Maxval to 3 leafs (R/W). */
920	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
921	/** When set to 1, xTPR messages are disabled (R/W). */
922	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
923	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
924	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
925
926	/** MTRR Default Range. */
927	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
928
929	#define MSR_IA32_MC0_CTL 0x400
930	#define MSR_IA32_MC0_STATUS 0x401
931
932	/** Basic VMX information. */
933	#define MSR_IA32_VMX_BASIC_INFO 0x480
934	/** Allowed settings for pin-based VM execution controls */
935	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
936	/** Allowed settings for proc-based VM execution controls */
937	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
938	/** Allowed settings for the VMX exit controls. */
939	#define MSR_IA32_VMX_EXIT_CTLS 0x483
940	/** Allowed settings for the VMX entry controls. */
941	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
942	/** Misc VMX info. */
943	#define MSR_IA32_VMX_MISC 0x485
944	/** Fixed cleared bits in CR0. */
945	#define MSR_IA32_VMX_CR0_FIXED0 0x486
946	/** Fixed set bits in CR0. */
947	#define MSR_IA32_VMX_CR0_FIXED1 0x487
948	/** Fixed cleared bits in CR4. */
949	#define MSR_IA32_VMX_CR4_FIXED0 0x488
950	/** Fixed set bits in CR4. */
951	#define MSR_IA32_VMX_CR4_FIXED1 0x489
952	/** Information for enumerating fields in the VMCS. */
953	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
954	/** Allowed settings for secondary proc-based VM execution controls */
955	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
956	/** EPT capabilities. */
957	#define MSR_IA32_VMX_EPT_CAPS 0x48C
958	/** DS Save Area (R/W). */
959	#define MSR_IA32_DS_AREA 0x600
960	/** X2APIC MSR ranges. */
961	#define MSR_IA32_APIC_START 0x800
962	#define MSR_IA32_APIC_END 0x900
963
964	/** K6 EFER - Extended Feature Enable Register. */
965	#define MSR_K6_EFER 0xc0000080
966	/** @todo document EFER */
967	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
968	#define MSR_K6_EFER_SCE RT_BIT(0)
969	/** Bit 8 - LME - Long mode enabled. (R/W) */
970	#define MSR_K6_EFER_LME RT_BIT(8)
971	/** Bit 10 - LMA - Long mode active. (R) */
972	#define MSR_K6_EFER_LMA RT_BIT(10)
973	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
974	#define MSR_K6_EFER_NXE RT_BIT(11)
975	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
976	#define MSR_K6_EFER_SVME RT_BIT(12)
977	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
978	#define MSR_K6_EFER_LMSLE RT_BIT(13)
979	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
980	#define MSR_K6_EFER_FFXSR RT_BIT(14)
981	/** K6 STAR - SYSCALL/RET targets. */
982	#define MSR_K6_STAR 0xc0000081
983	/** Shift value for getting the SYSRET CS and SS value. */
984	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
985	/** Shift value for getting the SYSCALL CS and SS value. */
986	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
987	/** Selector mask for use after shifting. */
988	#define MSR_K6_STAR_SEL_MASK 0xffff
989	/** The mask which give the SYSCALL EIP. */
990	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
991	/** K6 WHCR - Write Handling Control Register. */
992	#define MSR_K6_WHCR 0xc0000082
993	/** K6 UWCCR - UC/WC Cacheability Control Register. */
994	#define MSR_K6_UWCCR 0xc0000085
995	/** K6 PSOR - Processor State Observability Register. */
996	#define MSR_K6_PSOR 0xc0000087
997	/** K6 PFIR - Page Flush/Invalidate Register. */
998	#define MSR_K6_PFIR 0xc0000088
999
1000	/** Performance counter MSRs. (AMD only) */
1001	#define MSR_K7_EVNTSEL0 0xc0010000
1002	#define MSR_K7_EVNTSEL1 0xc0010001
1003	#define MSR_K7_EVNTSEL2 0xc0010002
1004	#define MSR_K7_EVNTSEL3 0xc0010003
1005	#define MSR_K7_PERFCTR0 0xc0010004
1006	#define MSR_K7_PERFCTR1 0xc0010005
1007	#define MSR_K7_PERFCTR2 0xc0010006
1008	#define MSR_K7_PERFCTR3 0xc0010007
1009
1010	#define MSR_K8_HWCR 0xc0010015
1011
1012	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1013	#define MSR_K8_LSTAR 0xc0000082
1014	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1015	#define MSR_K8_CSTAR 0xc0000083
1016	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1017	#define MSR_K8_SF_MASK 0xc0000084
1018	/** K8 FS.base - The 64-bit base FS register. */
1019	#define MSR_K8_FS_BASE 0xc0000100
1020	/** K8 GS.base - The 64-bit base GS register. */
1021	#define MSR_K8_GS_BASE 0xc0000101
1022	/** K8 KernelGSbase - Used with SWAPGS. */
1023	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1024	#define MSR_K8_TSC_AUX 0xc0000103
1025	#define MSR_K8_SYSCFG 0xc0010010
1026	#define MSR_K8_HWCR 0xc0010015
1027	#define MSR_K8_IORRBASE0 0xc0010016
1028	#define MSR_K8_IORRMASK0 0xc0010017
1029	#define MSR_K8_IORRBASE1 0xc0010018
1030	#define MSR_K8_IORRMASK1 0xc0010019
1031	#define MSR_K8_TOP_MEM1 0xc001001a
1032	#define MSR_K8_TOP_MEM2 0xc001001d
1033	#define MSR_K8_VM_CR 0xc0010114
1034	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1035
1036	#define MSR_K8_IGNNE 0xc0010115
1037	#define MSR_K8_SMM_CTL 0xc0010116
1038	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1039	* host state during world switch.
1040	*/
1041	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1042
1043	/** @} */
1044
1045
1046	/** @name Page Table / Directory / Directory Pointers / L4.
1047	* @{
1048	*/
1049
1050	/** Page table/directory entry as an unsigned integer. */
1051	typedef uint32_t X86PGUINT;
1052	/** Pointer to a page table/directory table entry as an unsigned integer. */
1053	typedef X86PGUINT *PX86PGUINT;
1054	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1055	typedef X86PGUINT const *PCX86PGUINT;
1056
1057	/** Number of entries in a 32-bit PT/PD. */
1058	#define X86_PG_ENTRIES 1024
1059
1060
1061	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1062	typedef uint64_t X86PGPAEUINT;
1063	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1064	typedef X86PGPAEUINT *PX86PGPAEUINT;
1065	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1066	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1067
1068	/** Number of entries in a PAE PT/PD. */
1069	#define X86_PG_PAE_ENTRIES 512
1070	/** Number of entries in a PAE PDPT. */
1071	#define X86_PG_PAE_PDPE_ENTRIES 4
1072
1073	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1074	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1075	/** Number of entries in an AMD64 PDPT.
1076	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1077	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1078
1079	/** The size of a 4KB page. */
1080	#define X86_PAGE_4K_SIZE _4K
1081	/** The page shift of a 4KB page. */
1082	#define X86_PAGE_4K_SHIFT 12
1083	/** The 4KB page offset mask. */
1084	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1085	/** The 4KB page base mask for virtual addresses. */
1086	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1087	/** The 4KB page base mask for virtual addresses - 32bit version. */
1088	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1089
1090	/** The size of a 2MB page. */
1091	#define X86_PAGE_2M_SIZE _2M
1092	/** The page shift of a 2MB page. */
1093	#define X86_PAGE_2M_SHIFT 21
1094	/** The 2MB page offset mask. */
1095	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1096	/** The 2MB page base mask for virtual addresses. */
1097	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1098	/** The 2MB page base mask for virtual addresses - 32bit version. */
1099	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1100
1101	/** The size of a 4MB page. */
1102	#define X86_PAGE_4M_SIZE _4M
1103	/** The page shift of a 4MB page. */
1104	#define X86_PAGE_4M_SHIFT 22
1105	/** The 4MB page offset mask. */
1106	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1107	/** The 4MB page base mask for virtual addresses. */
1108	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1109	/** The 4MB page base mask for virtual addresses - 32bit version. */
1110	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1111
1112
1113
1114	/** @name Page Table Entry
1115	* @{
1116	*/
1117	/** Bit 0 - P - Present bit. */
1118	#define X86_PTE_BIT_P 0
1119	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1120	#define X86_PTE_BIT_RW 1
1121	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1122	#define X86_PTE_BIT_US 2
1123	/** Bit 3 - PWT - Page level write thru bit. */
1124	#define X86_PTE_BIT_PWT 3
1125	/** Bit 4 - PCD - Page level cache disable bit. */
1126	#define X86_PTE_BIT_PCD 4
1127	/** Bit 5 - A - Access bit. */
1128	#define X86_PTE_BIT_A 5
1129	/** Bit 6 - D - Dirty bit. */
1130	#define X86_PTE_BIT_D 6
1131	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1132	#define X86_PTE_BIT_PAT 7
1133	/** Bit 8 - G - Global flag. */
1134	#define X86_PTE_BIT_G 8
1135
1136	/** Bit 0 - P - Present bit mask. */
1137	#define X86_PTE_P RT_BIT(0)
1138	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1139	#define X86_PTE_RW RT_BIT(1)
1140	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1141	#define X86_PTE_US RT_BIT(2)
1142	/** Bit 3 - PWT - Page level write thru bit mask. */
1143	#define X86_PTE_PWT RT_BIT(3)
1144	/** Bit 4 - PCD - Page level cache disable bit mask. */
1145	#define X86_PTE_PCD RT_BIT(4)
1146	/** Bit 5 - A - Access bit mask. */
1147	#define X86_PTE_A RT_BIT(5)
1148	/** Bit 6 - D - Dirty bit mask. */
1149	#define X86_PTE_D RT_BIT(6)
1150	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1151	#define X86_PTE_PAT RT_BIT(7)
1152	/** Bit 8 - G - Global bit mask. */
1153	#define X86_PTE_G RT_BIT(8)
1154
1155	/** Bits 9-11 - - Available for use to system software. */
1156	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1157	/** Bits 12-31 - - Physical Page number of the next level. */
1158	#define X86_PTE_PG_MASK ( 0xfffff000 )
1159
1160	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1161	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1162	/** Bits 63 - NX - PAE/LM - No execution flag. */
1163	#define X86_PTE_PAE_NX RT_BIT_64(63)
1164	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1165	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1166	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1167	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1168	/** No bits - - LM - MBZ bits when NX is active. */
1169	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1170	/** Bits 63 - - LM - MBZ bits when no NX. */
1171	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1172
1173	/**
1174	* Page table entry.
1175	*/
1176	typedef struct X86PTEBITS
1177	{
1178	/** Flags whether(=1) or not the page is present. */
1179	unsigned u1Present : 1;
1180	/** Read(=0) / Write(=1) flag. */
1181	unsigned u1Write : 1;
1182	/** User(=1) / Supervisor (=0) flag. */
1183	unsigned u1User : 1;
1184	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1185	unsigned u1WriteThru : 1;
1186	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1187	unsigned u1CacheDisable : 1;
1188	/** Accessed flag.
1189	* Indicates that the page have been read or written to. */
1190	unsigned u1Accessed : 1;
1191	/** Dirty flag.
1192	* Indicates that the page has been written to. */
1193	unsigned u1Dirty : 1;
1194	/** Reserved / If PAT enabled, bit 2 of the index. */
1195	unsigned u1PAT : 1;
1196	/** Global flag. (Ignored in all but final level.) */
1197	unsigned u1Global : 1;
1198	/** Available for use to system software. */
1199	unsigned u3Available : 3;
1200	/** Physical Page number of the next level. */
1201	unsigned u20PageNo : 20;
1202	} X86PTEBITS;
1203	/** Pointer to a page table entry. */
1204	typedef X86PTEBITS *PX86PTEBITS;
1205	/** Pointer to a const page table entry. */
1206	typedef const X86PTEBITS *PCX86PTEBITS;
1207
1208	/**
1209	* Page table entry.
1210	*/
1211	typedef union X86PTE
1212	{
1213	/** Unsigned integer view */
1214	X86PGUINT u;
1215	/** Bit field view. */
1216	X86PTEBITS n;
1217	/** 32-bit view. */
1218	uint32_t au32[1];
1219	/** 16-bit view. */
1220	uint16_t au16[2];
1221	/** 8-bit view. */
1222	uint8_t au8[4];
1223	} X86PTE;
1224	/** Pointer to a page table entry. */
1225	typedef X86PTE *PX86PTE;
1226	/** Pointer to a const page table entry. */
1227	typedef const X86PTE *PCX86PTE;
1228
1229
1230	/**
1231	* PAE page table entry.
1232	*/
1233	typedef struct X86PTEPAEBITS
1234	{
1235	/** Flags whether(=1) or not the page is present. */
1236	uint32_t u1Present : 1;
1237	/** Read(=0) / Write(=1) flag. */
1238	uint32_t u1Write : 1;
1239	/** User(=1) / Supervisor(=0) flag. */
1240	uint32_t u1User : 1;
1241	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1242	uint32_t u1WriteThru : 1;
1243	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1244	uint32_t u1CacheDisable : 1;
1245	/** Accessed flag.
1246	* Indicates that the page have been read or written to. */
1247	uint32_t u1Accessed : 1;
1248	/** Dirty flag.
1249	* Indicates that the page has been written to. */
1250	uint32_t u1Dirty : 1;
1251	/** Reserved / If PAT enabled, bit 2 of the index. */
1252	uint32_t u1PAT : 1;
1253	/** Global flag. (Ignored in all but final level.) */
1254	uint32_t u1Global : 1;
1255	/** Available for use to system software. */
1256	uint32_t u3Available : 3;
1257	/** Physical Page number of the next level - Low Part. Don't use this. */
1258	uint32_t u20PageNoLow : 20;
1259	/** Physical Page number of the next level - High Part. Don't use this. */
1260	uint32_t u20PageNoHigh : 20;
1261	/** MBZ bits */
1262	uint32_t u11Reserved : 11;
1263	/** No Execute flag. */
1264	uint32_t u1NoExecute : 1;
1265	} X86PTEPAEBITS;
1266	/** Pointer to a page table entry. */
1267	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1268	/** Pointer to a page table entry. */
1269	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1270
1271	/**
1272	* PAE Page table entry.
1273	*/
1274	typedef union X86PTEPAE
1275	{
1276	/** Unsigned integer view */
1277	X86PGPAEUINT u;
1278	/** Bit field view. */
1279	X86PTEPAEBITS n;
1280	/** 32-bit view. */
1281	uint32_t au32[2];
1282	/** 16-bit view. */
1283	uint16_t au16[4];
1284	/** 8-bit view. */
1285	uint8_t au8[8];
1286	} X86PTEPAE;
1287	/** Pointer to a PAE page table entry. */
1288	typedef X86PTEPAE *PX86PTEPAE;
1289	/** Pointer to a const PAE page table entry. */
1290	typedef const X86PTEPAE *PCX86PTEPAE;
1291	/** @} */
1292
1293	/**
1294	* Page table.
1295	*/
1296	typedef struct X86PT
1297	{
1298	/** PTE Array. */
1299	X86PTE a[X86_PG_ENTRIES];
1300	} X86PT;
1301	/** Pointer to a page table. */
1302	typedef X86PT *PX86PT;
1303	/** Pointer to a const page table. */
1304	typedef const X86PT *PCX86PT;
1305
1306	/** The page shift to get the PT index. */
1307	#define X86_PT_SHIFT 12
1308	/** The PT index mask (apply to a shifted page address). */
1309	#define X86_PT_MASK 0x3ff
1310
1311
1312	/**
1313	* Page directory.
1314	*/
1315	typedef struct X86PTPAE
1316	{
1317	/** PTE Array. */
1318	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1319	} X86PTPAE;
1320	/** Pointer to a page table. */
1321	typedef X86PTPAE *PX86PTPAE;
1322	/** Pointer to a const page table. */
1323	typedef const X86PTPAE *PCX86PTPAE;
1324
1325	/** The page shift to get the PA PTE index. */
1326	#define X86_PT_PAE_SHIFT 12
1327	/** The PAE PT index mask (apply to a shifted page address). */
1328	#define X86_PT_PAE_MASK 0x1ff
1329
1330
1331	/** @name 4KB Page Directory Entry
1332	* @{
1333	*/
1334	/** Bit 0 - P - Present bit. */
1335	#define X86_PDE_P RT_BIT(0)
1336	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1337	#define X86_PDE_RW RT_BIT(1)
1338	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1339	#define X86_PDE_US RT_BIT(2)
1340	/** Bit 3 - PWT - Page level write thru bit. */
1341	#define X86_PDE_PWT RT_BIT(3)
1342	/** Bit 4 - PCD - Page level cache disable bit. */
1343	#define X86_PDE_PCD RT_BIT(4)
1344	/** Bit 5 - A - Access bit. */
1345	#define X86_PDE_A RT_BIT(5)
1346	/** Bit 7 - PS - Page size attribute.
1347	* Clear mean 4KB pages, set means large pages (2/4MB). */
1348	#define X86_PDE_PS RT_BIT(7)
1349	/** Bits 9-11 - - Available for use to system software. */
1350	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1351	/** Bits 12-31 - - Physical Page number of the next level. */
1352	#define X86_PDE_PG_MASK ( 0xfffff000 )
1353
1354	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1355	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1356	/** Bits 63 - NX - PAE/LM - No execution flag. */
1357	#define X86_PDE_PAE_NX RT_BIT_64(63)
1358	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1359	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1360	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1361	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1362	/** Bit 7 - - LM - MBZ bits when NX is active. */
1363	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1364	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1365	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1366
1367	/**
1368	* Page directory entry.
1369	*/
1370	typedef struct X86PDEBITS
1371	{
1372	/** Flags whether(=1) or not the page is present. */
1373	unsigned u1Present : 1;
1374	/** Read(=0) / Write(=1) flag. */
1375	unsigned u1Write : 1;
1376	/** User(=1) / Supervisor (=0) flag. */
1377	unsigned u1User : 1;
1378	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1379	unsigned u1WriteThru : 1;
1380	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1381	unsigned u1CacheDisable : 1;
1382	/** Accessed flag.
1383	* Indicates that the page has been read or written to. */
1384	unsigned u1Accessed : 1;
1385	/** Reserved / Ignored (dirty bit). */
1386	unsigned u1Reserved0 : 1;
1387	/** Size bit if PSE is enabled - in any event it's 0. */
1388	unsigned u1Size : 1;
1389	/** Reserved / Ignored (global bit). */
1390	unsigned u1Reserved1 : 1;
1391	/** Available for use to system software. */
1392	unsigned u3Available : 3;
1393	/** Physical Page number of the next level. */
1394	unsigned u20PageNo : 20;
1395	} X86PDEBITS;
1396	/** Pointer to a page directory entry. */
1397	typedef X86PDEBITS *PX86PDEBITS;
1398	/** Pointer to a const page directory entry. */
1399	typedef const X86PDEBITS *PCX86PDEBITS;
1400
1401
1402	/**
1403	* PAE page directory entry.
1404	*/
1405	typedef struct X86PDEPAEBITS
1406	{
1407	/** Flags whether(=1) or not the page is present. */
1408	uint32_t u1Present : 1;
1409	/** Read(=0) / Write(=1) flag. */
1410	uint32_t u1Write : 1;
1411	/** User(=1) / Supervisor (=0) flag. */
1412	uint32_t u1User : 1;
1413	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1414	uint32_t u1WriteThru : 1;
1415	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1416	uint32_t u1CacheDisable : 1;
1417	/** Accessed flag.
1418	* Indicates that the page has been read or written to. */
1419	uint32_t u1Accessed : 1;
1420	/** Reserved / Ignored (dirty bit). */
1421	uint32_t u1Reserved0 : 1;
1422	/** Size bit if PSE is enabled - in any event it's 0. */
1423	uint32_t u1Size : 1;
1424	/** Reserved / Ignored (global bit). / */
1425	uint32_t u1Reserved1 : 1;
1426	/** Available for use to system software. */
1427	uint32_t u3Available : 3;
1428	/** Physical Page number of the next level - Low Part. Don't use! */
1429	uint32_t u20PageNoLow : 20;
1430	/** Physical Page number of the next level - High Part. Don't use! */
1431	uint32_t u20PageNoHigh : 20;
1432	/** MBZ bits */
1433	uint32_t u11Reserved : 11;
1434	/** No Execute flag. */
1435	uint32_t u1NoExecute : 1;
1436	} X86PDEPAEBITS;
1437	/** Pointer to a page directory entry. */
1438	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1439	/** Pointer to a const page directory entry. */
1440	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1441
1442	/** @} */
1443
1444
1445	/** @name 2/4MB Page Directory Entry
1446	* @{
1447	*/
1448	/** Bit 0 - P - Present bit. */
1449	#define X86_PDE4M_P RT_BIT(0)
1450	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1451	#define X86_PDE4M_RW RT_BIT(1)
1452	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1453	#define X86_PDE4M_US RT_BIT(2)
1454	/** Bit 3 - PWT - Page level write thru bit. */
1455	#define X86_PDE4M_PWT RT_BIT(3)
1456	/** Bit 4 - PCD - Page level cache disable bit. */
1457	#define X86_PDE4M_PCD RT_BIT(4)
1458	/** Bit 5 - A - Access bit. */
1459	#define X86_PDE4M_A RT_BIT(5)
1460	/** Bit 6 - D - Dirty bit. */
1461	#define X86_PDE4M_D RT_BIT(6)
1462	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1463	#define X86_PDE4M_PS RT_BIT(7)
1464	/** Bit 8 - G - Global flag. */
1465	#define X86_PDE4M_G RT_BIT(8)
1466	/** Bits 9-11 - AVL - Available for use to system software. */
1467	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1468	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1469	#define X86_PDE4M_PAT RT_BIT(12)
1470	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1471	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1472	/** Bits 22-31 - - Physical Page number. */
1473	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1474	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1475	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1476	/** The number of bits to the high part of the page number. */
1477	#define X86_PDE4M_PG_HIGH_SHIFT 19
1478	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1479	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1480
1481	/** Bits 21-51 - - PAE/LM - Physical Page number.
1482	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1483	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1484	/** Bits 63 - NX - PAE/LM - No execution flag. */
1485	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1486	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1487	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1488	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1489	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1490	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1491	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1492	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1493	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1494
1495	/**
1496	* 4MB page directory entry.
1497	*/
1498	typedef struct X86PDE4MBITS
1499	{
1500	/** Flags whether(=1) or not the page is present. */
1501	unsigned u1Present : 1;
1502	/** Read(=0) / Write(=1) flag. */
1503	unsigned u1Write : 1;
1504	/** User(=1) / Supervisor (=0) flag. */
1505	unsigned u1User : 1;
1506	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1507	unsigned u1WriteThru : 1;
1508	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1509	unsigned u1CacheDisable : 1;
1510	/** Accessed flag.
1511	* Indicates that the page have been read or written to. */
1512	unsigned u1Accessed : 1;
1513	/** Dirty flag.
1514	* Indicates that the page has been written to. */
1515	unsigned u1Dirty : 1;
1516	/** Page size flag - always 1 for 4MB entries. */
1517	unsigned u1Size : 1;
1518	/** Global flag. */
1519	unsigned u1Global : 1;
1520	/** Available for use to system software. */
1521	unsigned u3Available : 3;
1522	/** Reserved / If PAT enabled, bit 2 of the index. */
1523	unsigned u1PAT : 1;
1524	/** Bits 32-39 of the page number on AMD64.
1525	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1526	unsigned u8PageNoHigh : 8;
1527	/** Reserved. */
1528	unsigned u1Reserved : 1;
1529	/** Physical Page number of the page. */
1530	unsigned u10PageNo : 10;
1531	} X86PDE4MBITS;
1532	/** Pointer to a page table entry. */
1533	typedef X86PDE4MBITS *PX86PDE4MBITS;
1534	/** Pointer to a const page table entry. */
1535	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1536
1537
1538	/**
1539	* 2MB PAE page directory entry.
1540	*/
1541	typedef struct X86PDE2MPAEBITS
1542	{
1543	/** Flags whether(=1) or not the page is present. */
1544	uint32_t u1Present : 1;
1545	/** Read(=0) / Write(=1) flag. */
1546	uint32_t u1Write : 1;
1547	/** User(=1) / Supervisor(=0) flag. */
1548	uint32_t u1User : 1;
1549	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1550	uint32_t u1WriteThru : 1;
1551	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1552	uint32_t u1CacheDisable : 1;
1553	/** Accessed flag.
1554	* Indicates that the page have been read or written to. */
1555	uint32_t u1Accessed : 1;
1556	/** Dirty flag.
1557	* Indicates that the page has been written to. */
1558	uint32_t u1Dirty : 1;
1559	/** Page size flag - always 1 for 2MB entries. */
1560	uint32_t u1Size : 1;
1561	/** Global flag. */
1562	uint32_t u1Global : 1;
1563	/** Available for use to system software. */
1564	uint32_t u3Available : 3;
1565	/** Reserved / If PAT enabled, bit 2 of the index. */
1566	uint32_t u1PAT : 1;
1567	/** Reserved. */
1568	uint32_t u9Reserved : 9;
1569	/** Physical Page number of the next level - Low part. Don't use! */
1570	uint32_t u10PageNoLow : 10;
1571	/** Physical Page number of the next level - High part. Don't use! */
1572	uint32_t u20PageNoHigh : 20;
1573	/** MBZ bits */
1574	uint32_t u11Reserved : 11;
1575	/** No Execute flag. */
1576	uint32_t u1NoExecute : 1;
1577	} X86PDE2MPAEBITS;
1578	/** Pointer to a 2MB PAE page table entry. */
1579	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1580	/** Pointer to a 2MB PAE page table entry. */
1581	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1582
1583	/** @} */
1584
1585	/**
1586	* Page directory entry.
1587	*/
1588	typedef union X86PDE
1589	{
1590	/** Unsigned integer view. */
1591	X86PGUINT u;
1592	/** Normal view. */
1593	X86PDEBITS n;
1594	/** 4MB view (big). */
1595	X86PDE4MBITS b;
1596	/** 8 bit unsigned integer view. */
1597	uint8_t au8[4];
1598	/** 16 bit unsigned integer view. */
1599	uint16_t au16[2];
1600	/** 32 bit unsigned integer view. */
1601	uint32_t au32[1];
1602	} X86PDE;
1603	/** Pointer to a page directory entry. */
1604	typedef X86PDE *PX86PDE;
1605	/** Pointer to a const page directory entry. */
1606	typedef const X86PDE *PCX86PDE;
1607
1608	/**
1609	* PAE page directory entry.
1610	*/
1611	typedef union X86PDEPAE
1612	{
1613	/** Unsigned integer view. */
1614	X86PGPAEUINT u;
1615	/** Normal view. */
1616	X86PDEPAEBITS n;
1617	/** 2MB page view (big). */
1618	X86PDE2MPAEBITS b;
1619	/** 8 bit unsigned integer view. */
1620	uint8_t au8[8];
1621	/** 16 bit unsigned integer view. */
1622	uint16_t au16[4];
1623	/** 32 bit unsigned integer view. */
1624	uint32_t au32[2];
1625	} X86PDEPAE;
1626	/** Pointer to a page directory entry. */
1627	typedef X86PDEPAE *PX86PDEPAE;
1628	/** Pointer to a const page directory entry. */
1629	typedef const X86PDEPAE *PCX86PDEPAE;
1630
1631	/**
1632	* Page directory.
1633	*/
1634	typedef struct X86PD
1635	{
1636	/** PDE Array. */
1637	X86PDE a[X86_PG_ENTRIES];
1638	} X86PD;
1639	/** Pointer to a page directory. */
1640	typedef X86PD *PX86PD;
1641	/** Pointer to a const page directory. */
1642	typedef const X86PD *PCX86PD;
1643
1644	/** The page shift to get the PD index. */
1645	#define X86_PD_SHIFT 22
1646	/** The PD index mask (apply to a shifted page address). */
1647	#define X86_PD_MASK 0x3ff
1648
1649
1650	/**
1651	* PAE page directory.
1652	*/
1653	typedef struct X86PDPAE
1654	{
1655	/** PDE Array. */
1656	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1657	} X86PDPAE;
1658	/** Pointer to a PAE page directory. */
1659	typedef X86PDPAE *PX86PDPAE;
1660	/** Pointer to a const PAE page directory. */
1661	typedef const X86PDPAE *PCX86PDPAE;
1662
1663	/** The page shift to get the PAE PD index. */
1664	#define X86_PD_PAE_SHIFT 21
1665	/** The PAE PD index mask (apply to a shifted page address). */
1666	#define X86_PD_PAE_MASK 0x1ff
1667
1668
1669	/** @name Page Directory Pointer Table Entry (PAE)
1670	* @{
1671	*/
1672	/** Bit 0 - P - Present bit. */
1673	#define X86_PDPE_P RT_BIT(0)
1674	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1675	#define X86_PDPE_RW RT_BIT(1)
1676	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1677	#define X86_PDPE_US RT_BIT(2)
1678	/** Bit 3 - PWT - Page level write thru bit. */
1679	#define X86_PDPE_PWT RT_BIT(3)
1680	/** Bit 4 - PCD - Page level cache disable bit. */
1681	#define X86_PDPE_PCD RT_BIT(4)
1682	/** Bit 5 - A - Access bit. Long Mode only. */
1683	#define X86_PDPE_A RT_BIT(5)
1684	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1685	#define X86_PDPE_LM_PS RT_BIT(7)
1686	/** Bits 9-11 - - Available for use to system software. */
1687	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1688	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1689	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1690	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1691	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1692	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1693	#define X86_PDPE_LM_NX RT_BIT_64(63)
1694	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1695	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1696	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1697	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1698	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1699	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1700	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1701	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1702
1703
1704	/**
1705	* Page directory pointer table entry.
1706	*/
1707	typedef struct X86PDPEBITS
1708	{
1709	/** Flags whether(=1) or not the page is present. */
1710	uint32_t u1Present : 1;
1711	/** Chunk of reserved bits. */
1712	uint32_t u2Reserved : 2;
1713	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1714	uint32_t u1WriteThru : 1;
1715	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1716	uint32_t u1CacheDisable : 1;
1717	/** Chunk of reserved bits. */
1718	uint32_t u4Reserved : 4;
1719	/** Available for use to system software. */
1720	uint32_t u3Available : 3;
1721	/** Physical Page number of the next level - Low Part. Don't use! */
1722	uint32_t u20PageNoLow : 20;
1723	/** Physical Page number of the next level - High Part. Don't use! */
1724	uint32_t u20PageNoHigh : 20;
1725	/** MBZ bits */
1726	uint32_t u12Reserved : 12;
1727	} X86PDPEBITS;
1728	/** Pointer to a page directory pointer table entry. */
1729	typedef X86PDPEBITS *PX86PTPEBITS;
1730	/** Pointer to a const page directory pointer table entry. */
1731	typedef const X86PDPEBITS *PCX86PTPEBITS;
1732
1733	/**
1734	* Page directory pointer table entry. AMD64 version
1735	*/
1736	typedef struct X86PDPEAMD64BITS
1737	{
1738	/** Flags whether(=1) or not the page is present. */
1739	uint32_t u1Present : 1;
1740	/** Read(=0) / Write(=1) flag. */
1741	uint32_t u1Write : 1;
1742	/** User(=1) / Supervisor (=0) flag. */
1743	uint32_t u1User : 1;
1744	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1745	uint32_t u1WriteThru : 1;
1746	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1747	uint32_t u1CacheDisable : 1;
1748	/** Accessed flag.
1749	* Indicates that the page have been read or written to. */
1750	uint32_t u1Accessed : 1;
1751	/** Chunk of reserved bits. */
1752	uint32_t u3Reserved : 3;
1753	/** Available for use to system software. */
1754	uint32_t u3Available : 3;
1755	/** Physical Page number of the next level - Low Part. Don't use! */
1756	uint32_t u20PageNoLow : 20;
1757	/** Physical Page number of the next level - High Part. Don't use! */
1758	uint32_t u20PageNoHigh : 20;
1759	/** MBZ bits */
1760	uint32_t u11Reserved : 11;
1761	/** No Execute flag. */
1762	uint32_t u1NoExecute : 1;
1763	} X86PDPEAMD64BITS;
1764	/** Pointer to a page directory pointer table entry. */
1765	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1766	/** Pointer to a const page directory pointer table entry. */
1767	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1768
1769	/**
1770	* Page directory pointer table entry.
1771	*/
1772	typedef union X86PDPE
1773	{
1774	/** Unsigned integer view. */
1775	X86PGPAEUINT u;
1776	/** Normal view. */
1777	X86PDPEBITS n;
1778	/** AMD64 view. */
1779	X86PDPEAMD64BITS lm;
1780	/** 8 bit unsigned integer view. */
1781	uint8_t au8[8];
1782	/** 16 bit unsigned integer view. */
1783	uint16_t au16[4];
1784	/** 32 bit unsigned integer view. */
1785	uint32_t au32[2];
1786	} X86PDPE;
1787	/** Pointer to a page directory pointer table entry. */
1788	typedef X86PDPE *PX86PDPE;
1789	/** Pointer to a const page directory pointer table entry. */
1790	typedef const X86PDPE *PCX86PDPE;
1791
1792
1793	/**
1794	* Page directory pointer table.
1795	*/
1796	typedef struct X86PDPT
1797	{
1798	/** PDE Array. */
1799	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1800	} X86PDPT;
1801	/** Pointer to a page directory pointer table. */
1802	typedef X86PDPT *PX86PDPT;
1803	/** Pointer to a const page directory pointer table. */
1804	typedef const X86PDPT *PCX86PDPT;
1805
1806	/** The page shift to get the PDPT index. */
1807	#define X86_PDPT_SHIFT 30
1808	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1809	#define X86_PDPT_MASK_PAE 0x3
1810	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1811	#define X86_PDPT_MASK_AMD64 0x1ff
1812
1813	/** @} */
1814
1815
1816	/** @name Page Map Level-4 Entry (Long Mode PAE)
1817	* @{
1818	*/
1819	/** Bit 0 - P - Present bit. */
1820	#define X86_PML4E_P RT_BIT(0)
1821	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1822	#define X86_PML4E_RW RT_BIT(1)
1823	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1824	#define X86_PML4E_US RT_BIT(2)
1825	/** Bit 3 - PWT - Page level write thru bit. */
1826	#define X86_PML4E_PWT RT_BIT(3)
1827	/** Bit 4 - PCD - Page level cache disable bit. */
1828	#define X86_PML4E_PCD RT_BIT(4)
1829	/** Bit 5 - A - Access bit. */
1830	#define X86_PML4E_A RT_BIT(5)
1831	/** Bits 9-11 - - Available for use to system software. */
1832	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1833	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1834	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1835	/** Bits 8, 7 - - MBZ bits when NX is active. */
1836	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1837	/** Bits 63, 7 - - MBZ bits when no NX. */
1838	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1839	/** Bits 63 - NX - PAE - No execution flag. */
1840	#define X86_PML4E_NX RT_BIT_64(63)
1841
1842	/**
1843	* Page Map Level-4 Entry
1844	*/
1845	typedef struct X86PML4EBITS
1846	{
1847	/** Flags whether(=1) or not the page is present. */
1848	uint32_t u1Present : 1;
1849	/** Read(=0) / Write(=1) flag. */
1850	uint32_t u1Write : 1;
1851	/** User(=1) / Supervisor (=0) flag. */
1852	uint32_t u1User : 1;
1853	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1854	uint32_t u1WriteThru : 1;
1855	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1856	uint32_t u1CacheDisable : 1;
1857	/** Accessed flag.
1858	* Indicates that the page have been read or written to. */
1859	uint32_t u1Accessed : 1;
1860	/** Chunk of reserved bits. */
1861	uint32_t u3Reserved : 3;
1862	/** Available for use to system software. */
1863	uint32_t u3Available : 3;
1864	/** Physical Page number of the next level - Low Part. Don't use! */
1865	uint32_t u20PageNoLow : 20;
1866	/** Physical Page number of the next level - High Part. Don't use! */
1867	uint32_t u20PageNoHigh : 20;
1868	/** MBZ bits */
1869	uint32_t u11Reserved : 11;
1870	/** No Execute flag. */
1871	uint32_t u1NoExecute : 1;
1872	} X86PML4EBITS;
1873	/** Pointer to a page map level-4 entry. */
1874	typedef X86PML4EBITS *PX86PML4EBITS;
1875	/** Pointer to a const page map level-4 entry. */
1876	typedef const X86PML4EBITS *PCX86PML4EBITS;
1877
1878	/**
1879	* Page Map Level-4 Entry.
1880	*/
1881	typedef union X86PML4E
1882	{
1883	/** Unsigned integer view. */
1884	X86PGPAEUINT u;
1885	/** Normal view. */
1886	X86PML4EBITS n;
1887	/** 8 bit unsigned integer view. */
1888	uint8_t au8[8];
1889	/** 16 bit unsigned integer view. */
1890	uint16_t au16[4];
1891	/** 32 bit unsigned integer view. */
1892	uint32_t au32[2];
1893	} X86PML4E;
1894	/** Pointer to a page map level-4 entry. */
1895	typedef X86PML4E *PX86PML4E;
1896	/** Pointer to a const page map level-4 entry. */
1897	typedef const X86PML4E *PCX86PML4E;
1898
1899
1900	/**
1901	* Page Map Level-4.
1902	*/
1903	typedef struct X86PML4
1904	{
1905	/** PDE Array. */
1906	X86PML4E a[X86_PG_PAE_ENTRIES];
1907	} X86PML4;
1908	/** Pointer to a page map level-4. */
1909	typedef X86PML4 *PX86PML4;
1910	/** Pointer to a const page map level-4. */
1911	typedef const X86PML4 *PCX86PML4;
1912
1913	/** The page shift to get the PML4 index. */
1914	#define X86_PML4_SHIFT 39
1915	/** The PML4 index mask (apply to a shifted page address). */
1916	#define X86_PML4_MASK 0x1ff
1917
1918	/** @} */
1919
1920	/** @} */
1921
1922
1923	/**
1924	* 80-bit MMX/FPU register type.
1925	*/
1926	typedef struct X86FPUMMX
1927	{
1928	uint8_t reg[10];
1929	} X86FPUMMX;
1930	/** Pointer to a 80-bit MMX/FPU register type. */
1931	typedef X86FPUMMX *PX86FPUMMX;
1932	/** Pointer to a const 80-bit MMX/FPU register type. */
1933	typedef const X86FPUMMX *PCX86FPUMMX;
1934
1935	/**
1936	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
1937	* @todo verify this...
1938	*/
1939	#pragma pack(1)
1940	typedef struct X86FPUSTATE
1941	{
1942	/** 0x00 - Control word. */
1943	uint16_t FCW;
1944	/** 0x02 - Alignment word */
1945	uint16_t Dummy1;
1946	/** 0x04 - Status word. */
1947	uint16_t FSW;
1948	/** 0x06 - Alignment word */
1949	uint16_t Dummy2;
1950	/** 0x08 - Tag word */
1951	uint16_t FTW;
1952	/** 0x0a - Alignment word */
1953	uint16_t Dummy3;
1954
1955	/** 0x0c - Instruction pointer. */
1956	uint32_t FPUIP;
1957	/** 0x10 - Code selector. */
1958	uint16_t CS;
1959	/** 0x12 - Opcode. */
1960	uint16_t FOP;
1961	/** 0x14 - FOO. */
1962	uint32_t FPUOO;
1963	/** 0x18 - FOS. */
1964	uint32_t FPUOS;
1965	/** 0x1c */
1966	union
1967	{
1968	/** MMX view. */
1969	uint64_t mmx;
1970	/** FPU view - todo. */
1971	X86FPUMMX fpu;
1972	/** Extended precision floating point view. */
1973	RTFLOAT80U2 r80;
1974	/** 8-bit view. */
1975	uint8_t au8[16];
1976	/** 16-bit view. */
1977	uint16_t au16[8];
1978	/** 32-bit view. */
1979	uint32_t au32[4];
1980	/** 64-bit view. */
1981	uint64_t au64[2];
1982	/** 128-bit view. (yeah, very helpful) */
1983	uint128_t au128[1];
1984	} regs[8];
1985	} X86FPUSTATE;
1986	#pragma pack()
1987	/** Pointer to a FPU state. */
1988	typedef X86FPUSTATE *PX86FPUSTATE;
1989	/** Pointer to a const FPU state. */
1990	typedef const X86FPUSTATE *PCX86FPUSTATE;
1991
1992	/**
1993	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1994	*/
1995	#pragma pack(1)
1996	typedef struct X86FXSTATE
1997	{
1998	/** 0x00 - Control word. */
1999	uint16_t FCW;
2000	/** 0x02 - Status word. */
2001	uint16_t FSW;
2002	/** 0x04 - Tag word. (The upper byte is always zero.) */
2003	uint16_t FTW;
2004	/** 0x06 - Opcode. */
2005	uint16_t FOP;
2006	/** 0x08 - Instruction pointer. */
2007	uint32_t FPUIP;
2008	/** 0x0c - Code selector. */
2009	uint16_t CS;
2010	uint16_t Rsrvd1;
2011	/** 0x10 - Data pointer. */
2012	uint32_t FPUDP;
2013	/** 0x14 - Data segment */
2014	uint16_t DS;
2015	/** 0x16 */
2016	uint16_t Rsrvd2;
2017	/** 0x18 */
2018	uint32_t MXCSR;
2019	/** 0x1c */
2020	uint32_t MXCSR_MASK;
2021	/** 0x20 */
2022	union
2023	{
2024	/** MMX view. */
2025	uint64_t mmx;
2026	/** FPU view - todo. */
2027	X86FPUMMX fpu;
2028	/** Extended precision floating point view. */
2029	RTFLOAT80U2 r80;
2030	/** 8-bit view. */
2031	uint8_t au8[16];
2032	/** 16-bit view. */
2033	uint16_t au16[8];
2034	/** 32-bit view. */
2035	uint32_t au32[4];
2036	/** 64-bit view. */
2037	uint64_t au64[2];
2038	/** 128-bit view. (yeah, very helpful) */
2039	uint128_t au128[1];
2040	} aRegs[8];
2041	/* - offset 160 - */
2042	union
2043	{
2044	/** XMM Register view . /
2045	uint128_t xmm;
2046	/** 8-bit view. */
2047	uint8_t au8[16];
2048	/** 16-bit view. */
2049	uint16_t au16[8];
2050	/** 32-bit view. */
2051	uint32_t au32[4];
2052	/** 64-bit view. */
2053	uint64_t au64[2];
2054	/** 128-bit view. (yeah, very helpful) */
2055	uint128_t au128[1];
2056	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2057	/* - offset 416 - */
2058	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2059	} X86FXSTATE;
2060	#pragma pack()
2061	/** Pointer to a FPU Extended state. */
2062	typedef X86FXSTATE *PX86FXSTATE;
2063	/** Pointer to a const FPU Extended state. */
2064	typedef const X86FXSTATE *PCX86FXSTATE;
2065
2066	/** @name FPU status word flags.
2067	* @{ */
2068	/** Exception Flag: Invalid operation. */
2069	#define X86_FSW_IE RT_BIT(0)
2070	/** Exception Flag: Denormalized operand. */
2071	#define X86_FSW_DE RT_BIT(1)
2072	/** Exception Flag: Zero divide. */
2073	#define X86_FSW_ZE RT_BIT(2)
2074	/** Exception Flag: Overflow. */
2075	#define X86_FSW_OE RT_BIT(3)
2076	/** Exception Flag: Underflow. */
2077	#define X86_FSW_UE RT_BIT(4)
2078	/** Exception Flag: Precision. */
2079	#define X86_FSW_PE RT_BIT(5)
2080	/** Stack fault. */
2081	#define X86_FSW_SF RT_BIT(6)
2082	/** Error summary status. */
2083	#define X86_FSW_ES RT_BIT(7)
2084	/** Condition code 0. */
2085	#define X86_FSW_C0 RT_BIT(8)
2086	/** Condition code 1. */
2087	#define X86_FSW_C1 RT_BIT(9)
2088	/** Condition code 2. */
2089	#define X86_FSW_C2 RT_BIT(10)
2090	/** Top of the stack mask. */
2091	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2092	/** TOP shift value. */
2093	#define X86_FSW_TOP_SHIFT 11
2094	/** Mask for getting TOP value after shifting it right. */
2095	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2096	/** Get the TOP value. */
2097	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2098	/** Condition code 3. */
2099	#define X86_FSW_C3 RT_BIT(14)
2100	/** FPU busy. */
2101	#define X86_FSW_B RT_BIT(15)
2102	/** @} */
2103
2104
2105	/** @name Selector Descriptor
2106	* @{
2107	*/
2108
2109	/**
2110	* Descriptor attributes.
2111	*/
2112	typedef struct X86DESCATTRBITS
2113	{
2114	/** 00 - Segment Type. */
2115	unsigned u4Type : 4;
2116	/** 04 - Descriptor Type. System(=0) or code/data selector */
2117	unsigned u1DescType : 1;
2118	/** 05 - Descriptor Privelege level. */
2119	unsigned u2Dpl : 2;
2120	/** 07 - Flags selector present(=1) or not. */
2121	unsigned u1Present : 1;
2122	/** 08 - Segment limit 16-19. */
2123	unsigned u4LimitHigh : 4;
2124	/** 0c - Available for system software. */
2125	unsigned u1Available : 1;
2126	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2127	unsigned u1Long : 1;
2128	/** 0e - This flags meaning depends on the segment type. Try make sense out
2129	* of the intel manual yourself. */
2130	unsigned u1DefBig : 1;
2131	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2132	* clear byte. */
2133	unsigned u1Granularity : 1;
2134	} X86DESCATTRBITS;
2135
2136
2137	#pragma pack(1)
2138	typedef union X86DESCATTR
2139	{
2140	/** Unsigned integer view. */
2141	uint32_t u;
2142	/** Normal view. */
2143	X86DESCATTRBITS n;
2144	} X86DESCATTR;
2145	#pragma pack()
2146	/** Pointer to descriptor attributes. */
2147	typedef X86DESCATTR *PX86DESCATTR;
2148	/** Pointer to const descriptor attributes. */
2149	typedef const X86DESCATTR *PCX86DESCATTR;
2150
2151
2152	/**
2153	* Generic descriptor table entry
2154	*/
2155	#pragma pack(1)
2156	typedef struct X86DESCGENERIC
2157	{
2158	/** Limit - Low word. */
2159	unsigned u16LimitLow : 16;
2160	/** Base address - lowe word.
2161	* Don't try set this to 24 because MSC is doing stupid things then. */
2162	unsigned u16BaseLow : 16;
2163	/** Base address - first 8 bits of high word. */
2164	unsigned u8BaseHigh1 : 8;
2165	/** Segment Type. */
2166	unsigned u4Type : 4;
2167	/** Descriptor Type. System(=0) or code/data selector */
2168	unsigned u1DescType : 1;
2169	/** Descriptor Privelege level. */
2170	unsigned u2Dpl : 2;
2171	/** Flags selector present(=1) or not. */
2172	unsigned u1Present : 1;
2173	/** Segment limit 16-19. */
2174	unsigned u4LimitHigh : 4;
2175	/** Available for system software. */
2176	unsigned u1Available : 1;
2177	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2178	unsigned u1Long : 1;
2179	/** This flags meaning depends on the segment type. Try make sense out
2180	* of the intel manual yourself. */
2181	unsigned u1DefBig : 1;
2182	/** Granularity of the limit. If set 4KB granularity is used, if
2183	* clear byte. */
2184	unsigned u1Granularity : 1;
2185	/** Base address - highest 8 bits. */
2186	unsigned u8BaseHigh2 : 8;
2187	} X86DESCGENERIC;
2188	#pragma pack()
2189	/** Pointer to a generic descriptor entry. */
2190	typedef X86DESCGENERIC *PX86DESCGENERIC;
2191	/** Pointer to a const generic descriptor entry. */
2192	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2193
2194	/**
2195	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2196	*/
2197	typedef struct X86DESCGATE
2198	{
2199	/** 00 - Target code segment offset - Low word.
2200	* Ignored if task-gate. */
2201	unsigned u16OffsetLow : 16;
2202	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2203	* TSS selector if task-gate. */
2204	unsigned u16Sel : 16;
2205	/** 20 - Number of parameters for a call-gate.
2206	* Ignored if interrupt-, trap- or task-gate. */
2207	unsigned u4ParmCount : 4;
2208	/** 24 - Reserved / ignored. */
2209	unsigned u4Reserved : 4;
2210	/** 28 - Segment Type. */
2211	unsigned u4Type : 4;
2212	/** 2c - Descriptor Type (0 = system). */
2213	unsigned u1DescType : 1;
2214	/** 2d - Descriptor Privelege level. */
2215	unsigned u2Dpl : 2;
2216	/** 2f - Flags selector present(=1) or not. */
2217	unsigned u1Present : 1;
2218	/** 30 - Target code segment offset - High word.
2219	* Ignored if task-gate. */
2220	unsigned u16OffsetHigh : 16;
2221	} X86DESCGATE;
2222	AssertCompileSize(X86DESCGATE, 8);
2223	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2224	typedef X86DESCGATE *PX86DESCGATE;
2225	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2226	typedef const X86DESCGATE *PCX86DESCGATE;
2227
2228	/**
2229	* Descriptor table entry.
2230	*/
2231	#pragma pack(1)
2232	typedef union X86DESC
2233	{
2234	/** Generic descriptor view. */
2235	X86DESCGENERIC Gen;
2236	/** Gate descriptor view. */
2237	X86DESCGATE Gate;
2238
2239	/** 8 bit unsigned integer view. */
2240	uint8_t au8[8];
2241	/** 16 bit unsigned integer view. */
2242	uint16_t au16[4];
2243	/** 32 bit unsigned integer view. */
2244	uint32_t au32[2];
2245	/** 64 bit unsigned integer view. */
2246	uint64_t au64[1];
2247	/** Unsigned integer view. */
2248	uint64_t u;
2249	} X86DESC;
2250	AssertCompileSize(X86DESC, 8);
2251	#pragma pack()
2252	/** Pointer to descriptor table entry. */
2253	typedef X86DESC *PX86DESC;
2254	/** Pointer to const descriptor table entry. */
2255	typedef const X86DESC *PCX86DESC;
2256
2257	/** @def X86DESC_BASE
2258	* Return the base address of a descriptor.
2259	*/
2260	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2261	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2262	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2263	\| ( (desc).Gen.u16BaseLow ) )
2264
2265	/** @def X86DESC_LIMIT
2266	* Return the limit of a descriptor.
2267	*/
2268	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2269	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2270	\| ( (desc).Gen.u16LimitLow ) )
2271
2272	/** @def X86DESC_GET_HID_ATTR
2273	* Get the descriptor attributes for the hidden register.
2274	*/
2275	#define X86DESC_GET_HID_ATTR(desc) /ASM-NOINC/ \
2276	( (desc.u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2277
2278
2279	/**
2280	* 64 bits generic descriptor table entry
2281	* Note: most of these bits have no meaning in long mode.
2282	*/
2283	#pragma pack(1)
2284	typedef struct X86DESC64GENERIC
2285	{
2286	/** Limit - Low word - IGNORED. */
2287	unsigned u16LimitLow : 16;
2288	/** Base address - lowe word. - IGNORED
2289	* Don't try set this to 24 because MSC is doing stupid things then. */
2290	unsigned u16BaseLow : 16;
2291	/** Base address - first 8 bits of high word. - IGNORED */
2292	unsigned u8BaseHigh1 : 8;
2293	/** Segment Type. */
2294	unsigned u4Type : 4;
2295	/** Descriptor Type. System(=0) or code/data selector */
2296	unsigned u1DescType : 1;
2297	/** Descriptor Privelege level. */
2298	unsigned u2Dpl : 2;
2299	/** Flags selector present(=1) or not. */
2300	unsigned u1Present : 1;
2301	/** Segment limit 16-19. - IGNORED */
2302	unsigned u4LimitHigh : 4;
2303	/** Available for system software. - IGNORED */
2304	unsigned u1Available : 1;
2305	/** Long mode flag. */
2306	unsigned u1Long : 1;
2307	/** This flags meaning depends on the segment type. Try make sense out
2308	* of the intel manual yourself. */
2309	unsigned u1DefBig : 1;
2310	/** Granularity of the limit. If set 4KB granularity is used, if
2311	* clear byte. - IGNORED */
2312	unsigned u1Granularity : 1;
2313	/** Base address - highest 8 bits. - IGNORED */
2314	unsigned u8BaseHigh2 : 8;
2315	/** Base address - bits 63-32. */
2316	unsigned u32BaseHigh3 : 32;
2317	unsigned u8Reserved : 8;
2318	unsigned u5Zeros : 5;
2319	unsigned u19Reserved : 19;
2320	} X86DESC64GENERIC;
2321	#pragma pack()
2322	/** Pointer to a generic descriptor entry. */
2323	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2324	/** Pointer to a const generic descriptor entry. */
2325	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2326
2327	/**
2328	* System descriptor table entry (64 bits)
2329	*
2330	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2331	*/
2332	#pragma pack(1)
2333	typedef struct X86DESC64SYSTEM
2334	{
2335	/** Limit - Low word. */
2336	unsigned u16LimitLow : 16;
2337	/** Base address - lowe word.
2338	* Don't try set this to 24 because MSC is doing stupid things then. */
2339	unsigned u16BaseLow : 16;
2340	/** Base address - first 8 bits of high word. */
2341	unsigned u8BaseHigh1 : 8;
2342	/** Segment Type. */
2343	unsigned u4Type : 4;
2344	/** Descriptor Type. System(=0) or code/data selector */
2345	unsigned u1DescType : 1;
2346	/** Descriptor Privelege level. */
2347	unsigned u2Dpl : 2;
2348	/** Flags selector present(=1) or not. */
2349	unsigned u1Present : 1;
2350	/** Segment limit 16-19. */
2351	unsigned u4LimitHigh : 4;
2352	/** Available for system software. */
2353	unsigned u1Available : 1;
2354	/** Reserved - 0. */
2355	unsigned u1Reserved : 1;
2356	/** This flags meaning depends on the segment type. Try make sense out
2357	* of the intel manual yourself. */
2358	unsigned u1DefBig : 1;
2359	/** Granularity of the limit. If set 4KB granularity is used, if
2360	* clear byte. */
2361	unsigned u1Granularity : 1;
2362	/** Base address - bits 31-24. */
2363	unsigned u8BaseHigh2 : 8;
2364	/** Base address - bits 63-32. */
2365	unsigned u32BaseHigh3 : 32;
2366	unsigned u8Reserved : 8;
2367	unsigned u5Zeros : 5;
2368	unsigned u19Reserved : 19;
2369	} X86DESC64SYSTEM;
2370	#pragma pack()
2371	/** Pointer to a system descriptor entry. */
2372	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2373	/** Pointer to a const system descriptor entry. */
2374	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2375
2376	/**
2377	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2378	*/
2379	typedef struct X86DESC64GATE
2380	{
2381	/** Target code segment offset - Low word. */
2382	unsigned u16OffsetLow : 16;
2383	/** Target code segment selector. */
2384	unsigned u16Sel : 16;
2385	/** Interrupt stack table for interrupt- and trap-gates.
2386	* Ignored by call-gates. */
2387	unsigned u3IST : 3;
2388	/** Reserved / ignored. */
2389	unsigned u5Reserved : 5;
2390	/** Segment Type. */
2391	unsigned u4Type : 4;
2392	/** Descriptor Type (0 = system). */
2393	unsigned u1DescType : 1;
2394	/** Descriptor Privelege level. */
2395	unsigned u2Dpl : 2;
2396	/** Flags selector present(=1) or not. */
2397	unsigned u1Present : 1;
2398	/** Target code segment offset - High word.
2399	* Ignored if task-gate. */
2400	unsigned u16OffsetHigh : 16;
2401	/** Target code segment offset - Top dword.
2402	* Ignored if task-gate. */
2403	unsigned u32OffsetTop : 32;
2404	/** Reserved / ignored / must be zero.
2405	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2406	unsigned u32Reserved : 32;
2407	} X86DESC64GATE;
2408	AssertCompileSize(X86DESC64GATE, 16);
2409	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2410	typedef X86DESC64GATE *PX86DESC64GATE;
2411	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2412	typedef const X86DESC64GATE *PCX86DESC64GATE;
2413
2414
2415	/**
2416	* Descriptor table entry.
2417	*/
2418	#pragma pack(1)
2419	typedef union X86DESC64
2420	{
2421	/** Generic descriptor view. */
2422	X86DESC64GENERIC Gen;
2423	/** System descriptor view. */
2424	X86DESC64SYSTEM System;
2425	/** Gate descriptor view. */
2426	X86DESC64GATE Gate;
2427
2428	/** 8 bit unsigned integer view. */
2429	uint8_t au8[16];
2430	/** 16 bit unsigned integer view. */
2431	uint16_t au16[8];
2432	/** 32 bit unsigned integer view. */
2433	uint32_t au32[4];
2434	/** 64 bit unsigned integer view. */
2435	uint64_t au64[2];
2436	} X86DESC64;
2437	AssertCompileSize(X86DESC64, 16);
2438	#pragma pack()
2439	/** Pointer to descriptor table entry. */
2440	typedef X86DESC64 *PX86DESC64;
2441	/** Pointer to const descriptor table entry. */
2442	typedef const X86DESC64 *PCX86DESC64;
2443
2444	/** @def X86DESC64_BASE
2445	* Return the base of a 64-bit descriptor.
2446	*/
2447	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2448	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2449	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2450	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2451	\| ( (desc).Gen.u16BaseLow ) )
2452
2453
2454
2455	/** @name Host system descriptor table entry - Use with care!
2456	* @{ */
2457	/** Host system descriptor table entry. */
2458	#if HC_ARCH_BITS == 64
2459	typedef X86DESC64 X86DESCHC;
2460	#else
2461	typedef X86DESC X86DESCHC;
2462	#endif
2463	/** Pointer to a host system descriptor table entry. */
2464	#if HC_ARCH_BITS == 64
2465	typedef PX86DESC64 PX86DESCHC;
2466	#else
2467	typedef PX86DESC PX86DESCHC;
2468	#endif
2469	/** Pointer to a const host system descriptor table entry. */
2470	#if HC_ARCH_BITS == 64
2471	typedef PCX86DESC64 PCX86DESCHC;
2472	#else
2473	typedef PCX86DESC PCX86DESCHC;
2474	#endif
2475	/** @} */
2476
2477
2478	/** @name Selector Descriptor Types.
2479	* @{
2480	*/
2481
2482	/** @name Non-System Selector Types.
2483	* @{ */
2484	/** Code(=set)/Data(=clear) bit. */
2485	#define X86_SEL_TYPE_CODE 8
2486	/** Memory(=set)/System(=clear) bit. */
2487	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2488	/** Accessed bit. */
2489	#define X86_SEL_TYPE_ACCESSED 1
2490	/** Expand down bit (for data selectors only). */
2491	#define X86_SEL_TYPE_DOWN 4
2492	/** Conforming bit (for code selectors only). */
2493	#define X86_SEL_TYPE_CONF 4
2494	/** Write bit (for data selectors only). */
2495	#define X86_SEL_TYPE_WRITE 2
2496	/** Read bit (for code selectors only). */
2497	#define X86_SEL_TYPE_READ 2
2498
2499	/** Read only selector type. */
2500	#define X86_SEL_TYPE_RO 0
2501	/** Accessed read only selector type. */
2502	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2503	/** Read write selector type. */
2504	#define X86_SEL_TYPE_RW 2
2505	/** Accessed read write selector type. */
2506	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2507	/** Expand down read only selector type. */
2508	#define X86_SEL_TYPE_RO_DOWN 4
2509	/** Accessed expand down read only selector type. */
2510	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2511	/** Expand down read write selector type. */
2512	#define X86_SEL_TYPE_RW_DOWN 6
2513	/** Accessed expand down read write selector type. */
2514	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2515	/** Execute only selector type. */
2516	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2517	/** Accessed execute only selector type. */
2518	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2519	/** Execute and read selector type. */
2520	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2521	/** Accessed execute and read selector type. */
2522	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2523	/** Conforming execute only selector type. */
2524	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2525	/** Accessed Conforming execute only selector type. */
2526	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2527	/** Conforming execute and write selector type. */
2528	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2529	/** Accessed Conforming execute and write selector type. */
2530	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2531	/** @} */
2532
2533
2534	/** @name System Selector Types.
2535	* @{ */
2536	/** The TSS busy bit mask. */
2537	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2538
2539	/** Undefined system selector type. */
2540	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2541	/** 286 TSS selector. */
2542	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2543	/** LDT selector. */
2544	#define X86_SEL_TYPE_SYS_LDT 2
2545	/** 286 TSS selector - Busy. */
2546	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2547	/** 286 Callgate selector. */
2548	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2549	/** Taskgate selector. */
2550	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2551	/** 286 Interrupt gate selector. */
2552	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2553	/** 286 Trapgate selector. */
2554	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2555	/** Undefined system selector. */
2556	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2557	/** 386 TSS selector. */
2558	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2559	/** Undefined system selector. */
2560	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2561	/** 386 TSS selector - Busy. */
2562	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2563	/** 386 Callgate selector. */
2564	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2565	/** Undefined system selector. */
2566	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2567	/** 386 Interruptgate selector. */
2568	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2569	/** 386 Trapgate selector. */
2570	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2571	/** @} */
2572
2573	/** @name AMD64 System Selector Types.
2574	* @{ */
2575	/** LDT selector. */
2576	#define AMD64_SEL_TYPE_SYS_LDT 2
2577	/** TSS selector - Busy. */
2578	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2579	/** TSS selector - Busy. */
2580	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2581	/** Callgate selector. */
2582	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2583	/** Interruptgate selector. */
2584	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2585	/** Trapgate selector. */
2586	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2587	/** @} */
2588
2589	/** @} */
2590
2591
2592	/** @name Descriptor Table Entry Flag Masks.
2593	* These are for the 2nd 32-bit word of a descriptor.
2594	* @{ */
2595	/** Bits 8-11 - TYPE - Descriptor type mask. */
2596	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2597	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2598	#define X86_DESC_S RT_BIT(12)
2599	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2600	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2601	/** Bit 15 - P - Present. */
2602	#define X86_DESC_P RT_BIT(15)
2603	/** Bit 20 - AVL - Available for system software. */
2604	#define X86_DESC_AVL RT_BIT(20)
2605	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2606	#define X86_DESC_DB RT_BIT(22)
2607	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2608	* used, if clear byte. */
2609	#define X86_DESC_G RT_BIT(23)
2610	/** @} */
2611
2612	/** @} */
2613
2614
2615	/** @name Task Segments.
2616	* @{
2617	*/
2618
2619	/**
2620	* 16-bit Task Segment (TSS).
2621	*/
2622	#pragma pack(1)
2623	typedef struct X86TSS16
2624	{
2625	/** Back link to previous task. (static) */
2626	RTSEL selPrev;
2627	/** Ring-0 stack pointer. (static) */
2628	uint16_t sp0;
2629	/** Ring-0 stack segment. (static) */
2630	RTSEL ss0;
2631	/** Ring-1 stack pointer. (static) */
2632	uint16_t sp1;
2633	/** Ring-1 stack segment. (static) */
2634	RTSEL ss1;
2635	/** Ring-2 stack pointer. (static) */
2636	uint16_t sp2;
2637	/** Ring-2 stack segment. (static) */
2638	RTSEL ss2;
2639	/** IP before task switch. */
2640	uint16_t ip;
2641	/** FLAGS before task switch. */
2642	uint16_t flags;
2643	/** AX before task switch. */
2644	uint16_t ax;
2645	/** CX before task switch. */
2646	uint16_t cx;
2647	/** DX before task switch. */
2648	uint16_t dx;
2649	/** BX before task switch. */
2650	uint16_t bx;
2651	/** SP before task switch. */
2652	uint16_t sp;
2653	/** BP before task switch. */
2654	uint16_t bp;
2655	/** SI before task switch. */
2656	uint16_t si;
2657	/** DI before task switch. */
2658	uint16_t di;
2659	/** ES before task switch. */
2660	RTSEL es;
2661	/** CS before task switch. */
2662	RTSEL cs;
2663	/** SS before task switch. */
2664	RTSEL ss;
2665	/** DS before task switch. */
2666	RTSEL ds;
2667	/** LDTR before task switch. */
2668	RTSEL selLdt;
2669	} X86TSS16;
2670	AssertCompileSize(X86TSS16, 44);
2671	#pragma pack()
2672	/** Pointer to a 16-bit task segment. */
2673	typedef X86TSS16 *PX86TSS16;
2674	/** Pointer to a const 16-bit task segment. */
2675	typedef const X86TSS16 *PCX86TSS16;
2676
2677
2678	/**
2679	* 32-bit Task Segment (TSS).
2680	*/
2681	#pragma pack(1)
2682	typedef struct X86TSS32
2683	{
2684	/** Back link to previous task. (static) */
2685	RTSEL selPrev;
2686	uint16_t padding1;
2687	/** Ring-0 stack pointer. (static) */
2688	uint32_t esp0;
2689	/** Ring-0 stack segment. (static) */
2690	RTSEL ss0;
2691	uint16_t padding_ss0;
2692	/** Ring-1 stack pointer. (static) */
2693	uint32_t esp1;
2694	/** Ring-1 stack segment. (static) */
2695	RTSEL ss1;
2696	uint16_t padding_ss1;
2697	/** Ring-2 stack pointer. (static) */
2698	uint32_t esp2;
2699	/** Ring-2 stack segment. (static) */
2700	RTSEL ss2;
2701	uint16_t padding_ss2;
2702	/** Page directory for the task. (static) */
2703	uint32_t cr3;
2704	/** EIP before task switch. */
2705	uint32_t eip;
2706	/** EFLAGS before task switch. */
2707	uint32_t eflags;
2708	/** EAX before task switch. */
2709	uint32_t eax;
2710	/** ECX before task switch. */
2711	uint32_t ecx;
2712	/** EDX before task switch. */
2713	uint32_t edx;
2714	/** EBX before task switch. */
2715	uint32_t ebx;
2716	/** ESP before task switch. */
2717	uint32_t esp;
2718	/** EBP before task switch. */
2719	uint32_t ebp;
2720	/** ESI before task switch. */
2721	uint32_t esi;
2722	/** EDI before task switch. */
2723	uint32_t edi;
2724	/** ES before task switch. */
2725	RTSEL es;
2726	uint16_t padding_es;
2727	/** CS before task switch. */
2728	RTSEL cs;
2729	uint16_t padding_cs;
2730	/** SS before task switch. */
2731	RTSEL ss;
2732	uint16_t padding_ss;
2733	/** DS before task switch. */
2734	RTSEL ds;
2735	uint16_t padding_ds;
2736	/** FS before task switch. */
2737	RTSEL fs;
2738	uint16_t padding_fs;
2739	/** GS before task switch. */
2740	RTSEL gs;
2741	uint16_t padding_gs;
2742	/** LDTR before task switch. */
2743	RTSEL selLdt;
2744	uint16_t padding_ldt;
2745	/** Debug trap flag */
2746	uint16_t fDebugTrap;
2747	/** Offset relative to the TSS of the start of the I/O Bitmap
2748	* and the end of the interrupt redirection bitmap. */
2749	uint16_t offIoBitmap;
2750	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2751	uint8_t IntRedirBitmap[32];
2752	} X86TSS32;
2753	#pragma pack()
2754	/** Pointer to task segment. */
2755	typedef X86TSS32 *PX86TSS32;
2756	/** Pointer to const task segment. */
2757	typedef const X86TSS32 *PCX86TSS32;
2758
2759
2760	/**
2761	* 64-bit Task segment.
2762	*/
2763	#pragma pack(1)
2764	typedef struct X86TSS64
2765	{
2766	/** Reserved. */
2767	uint32_t u32Reserved;
2768	/** Ring-0 stack pointer. (static) */
2769	uint64_t rsp0;
2770	/** Ring-1 stack pointer. (static) */
2771	uint64_t rsp1;
2772	/** Ring-2 stack pointer. (static) */
2773	uint64_t rsp2;
2774	/** Reserved. */
2775	uint32_t u32Reserved2[2];
2776	/* IST */
2777	uint64_t ist1;
2778	uint64_t ist2;
2779	uint64_t ist3;
2780	uint64_t ist4;
2781	uint64_t ist5;
2782	uint64_t ist6;
2783	uint64_t ist7;
2784	/* Reserved. */
2785	uint16_t u16Reserved[5];
2786	/** Offset relative to the TSS of the start of the I/O Bitmap
2787	* and the end of the interrupt redirection bitmap. */
2788	uint16_t offIoBitmap;
2789	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2790	uint8_t IntRedirBitmap[32];
2791	} X86TSS64;
2792	#pragma pack()
2793	/** Pointer to a 64-bit task segment. */
2794	typedef X86TSS64 *PX86TSS64;
2795	/** Pointer to a const 64-bit task segment. */
2796	typedef const X86TSS64 *PCX86TSS64;
2797	AssertCompileSize(X86TSS64, 136);
2798
2799	/** @} */
2800
2801
2802	/** @name Selectors.
2803	* @{
2804	*/
2805
2806	/**
2807	* The shift used to convert a selector from and to index an index (C).
2808	*/
2809	#define X86_SEL_SHIFT 3
2810
2811	/**
2812	* The mask used to mask off the table indicator and CPL of an selector.
2813	*/
2814	#define X86_SEL_MASK 0xfff8U
2815
2816	/**
2817	* The bit indicating that a selector is in the LDT and not in the GDT.
2818	*/
2819	#define X86_SEL_LDT 0x0004U
2820	/**
2821	* The bit mask for getting the RPL of a selector.
2822	*/
2823	#define X86_SEL_RPL 0x0003U
2824
2825	/** @} */
2826
2827
2828	/**
2829	* x86 Exceptions/Faults/Traps.
2830	*/
2831	typedef enum X86XCPT
2832	{
2833	/** \#DE - Divide error. */
2834	X86_XCPT_DE = 0x00,
2835	/** \#DB - Debug event (single step, DRx, ..) */
2836	X86_XCPT_DB = 0x01,
2837	/** NMI - Non-Maskable Interrupt */
2838	X86_XCPT_NMI = 0x02,
2839	/** \#BP - Breakpoint (INT3). */
2840	X86_XCPT_BP = 0x03,
2841	/** \#OF - Overflow (INTO). */
2842	X86_XCPT_OF = 0x04,
2843	/** \#BR - Bound range exceeded (BOUND). */
2844	X86_XCPT_BR = 0x05,
2845	/** \#UD - Undefined opcode. */
2846	X86_XCPT_UD = 0x06,
2847	/** \#NM - Device not available (math coprocessor device). */
2848	X86_XCPT_NM = 0x07,
2849	/** \#DF - Double fault. */
2850	X86_XCPT_DF = 0x08,
2851	/** ??? - Coprocessor segment overrun (obsolete). */
2852	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2853	/** \#TS - Taskswitch (TSS). */
2854	X86_XCPT_TS = 0x0a,
2855	/** \#NP - Segment no present. */
2856	X86_XCPT_NP = 0x0b,
2857	/** \#SS - Stack segment fault. */
2858	X86_XCPT_SS = 0x0c,
2859	/** \#GP - General protection fault. */
2860	X86_XCPT_GP = 0x0d,
2861	/** \#PF - Page fault. */
2862	X86_XCPT_PF = 0x0e,
2863	/* 0x0f is reserved. */
2864	/** \#MF - Math fault (FPU). */
2865	X86_XCPT_MF = 0x10,
2866	/** \#AC - Alignment check. */
2867	X86_XCPT_AC = 0x11,
2868	/** \#MC - Machine check. */
2869	X86_XCPT_MC = 0x12,
2870	/** \#XF - SIMD Floating-Pointer Exception. */
2871	X86_XCPT_XF = 0x13
2872	} X86XCPT;
2873	/** Pointer to a x86 exception code. */
2874	typedef X86XCPT *PX86XCPT;
2875	/** Pointer to a const x86 exception code. */
2876	typedef const X86XCPT *PCX86XCPT;
2877
2878
2879	/** @name Trap Error Codes
2880	* @{
2881	*/
2882	/** External indicator. */
2883	#define X86_TRAP_ERR_EXTERNAL 1
2884	/** IDT indicator. */
2885	#define X86_TRAP_ERR_IDT 2
2886	/** Descriptor table indicator - If set LDT, if clear GDT. */
2887	#define X86_TRAP_ERR_TI 4
2888	/** Mask for getting the selector. */
2889	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2890	/** Shift for getting the selector table index (C type index). */
2891	#define X86_TRAP_ERR_SEL_SHIFT 3
2892	/** @} */
2893
2894
2895	/** @name \#PF Trap Error Codes
2896	* @{
2897	*/
2898	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2899	#define X86_TRAP_PF_P RT_BIT(0)
2900	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2901	#define X86_TRAP_PF_RW RT_BIT(1)
2902	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2903	#define X86_TRAP_PF_US RT_BIT(2)
2904	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2905	#define X86_TRAP_PF_RSVD RT_BIT(3)
2906	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2907	#define X86_TRAP_PF_ID RT_BIT(4)
2908	/** @} */
2909
2910	#pragma pack(1)
2911	/**
2912	* 32-bit IDTR/GDTR.
2913	*/
2914	typedef struct X86XDTR32
2915	{
2916	/** Size of the descriptor table. */
2917	uint16_t cb;
2918	/** Address of the descriptor table. */
2919	uint32_t uAddr;
2920	} X86XDTR32, *PX86XDTR32;
2921	#pragma pack()
2922
2923	#pragma pack(1)
2924	/**
2925	* 64-bit IDTR/GDTR.
2926	*/
2927	typedef struct X86XDTR64
2928	{
2929	/** Size of the descriptor table. */
2930	uint16_t cb;
2931	/** Address of the descriptor table. */
2932	uint64_t uAddr;
2933	} X86XDTR64, *PX86XDTR64;
2934	#pragma pack()
2935
2936
2937	/** @name ModR/M
2938	* @{ */
2939	#define X86_MODRM_RM_MASK UINT8_C(0x07)
2940	#define X86_MODRM_REG_MASK UINT8_C(0x38)
2941	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
2942	#define X86_MODRM_REG_SHIFT 3
2943	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
2944	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
2945	#define X86_MODRM_MOD_SHIFT 6
2946	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
2947	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
2948	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
2949	/** @} */
2950
2951	/** @name SIB
2952	* @{ */
2953	#define X86_SIB_BASE_MASK UINT8_C(0x07)
2954	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
2955	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
2956	#define X86_SIB_INDEX_SHIFT 3
2957	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
2958	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
2959	#define X86_SIB_SCALE_SHIFT 6
2960	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
2961	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
2962	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
2963	/** @} */
2964
2965	/** @name General register indexes
2966	* @{ */
2967	#define X86_GREG_xAX 0
2968	#define X86_GREG_xCX 1
2969	#define X86_GREG_xDX 2
2970	#define X86_GREG_xBX 3
2971	#define X86_GREG_xSP 4
2972	#define X86_GREG_xBP 5
2973	#define X86_GREG_xSI 6
2974	#define X86_GREG_xDI 7
2975	#define X86_GREG_x8 8
2976	#define X86_GREG_x9 9
2977	#define X86_GREG_x10 10
2978	#define X86_GREG_x11 11
2979	#define X86_GREG_x12 12
2980	#define X86_GREG_x13 13
2981	#define X86_GREG_x14 14
2982	#define X86_GREG_x15 15
2983	/** @} */
2984
2985	/** @name X86_SREG_XXX - Segment register indexes.
2986	* @{ */
2987	#define X86_SREG_ES 0
2988	#define X86_SREG_CS 1
2989	#define X86_SREG_SS 2
2990	#define X86_SREG_DS 3
2991	#define X86_SREG_FS 4
2992	#define X86_SREG_GS 5
2993	/** @} */
2994
2995
2996	/** @} */
2997
2998	#endif
2999

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