x86.h@ 41247

Last change on this file since 41247 was 41247, checked in by vboxsync, 13 years ago
More dtrace library stuff. On 64-bit solaris dtrace can now grok the library files (point it to them using the -L parameter).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 109.9 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	/**
50	* EFLAGS Bits.
51	*/
52	typedef struct X86EFLAGSBITS
53	{
54	/** Bit 0 - CF - Carry flag - Status flag. */
55	unsigned u1CF : 1;
56	/** Bit 1 - 1 - Reserved flag. */
57	unsigned u1Reserved0 : 1;
58	/** Bit 2 - PF - Parity flag - Status flag. */
59	unsigned u1PF : 1;
60	/** Bit 3 - 0 - Reserved flag. */
61	unsigned u1Reserved1 : 1;
62	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
63	unsigned u1AF : 1;
64	/** Bit 5 - 0 - Reserved flag. */
65	unsigned u1Reserved2 : 1;
66	/** Bit 6 - ZF - Zero flag - Status flag. */
67	unsigned u1ZF : 1;
68	/** Bit 7 - SF - Signed flag - Status flag. */
69	unsigned u1SF : 1;
70	/** Bit 8 - TF - Trap flag - System flag. */
71	unsigned u1TF : 1;
72	/** Bit 9 - IF - Interrupt flag - System flag. */
73	unsigned u1IF : 1;
74	/** Bit 10 - DF - Direction flag - Control flag. */
75	unsigned u1DF : 1;
76	/** Bit 11 - OF - Overflow flag - Status flag. */
77	unsigned u1OF : 1;
78	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
79	unsigned u2IOPL : 2;
80	/** Bit 14 - NT - Nested task flag - System flag. */
81	unsigned u1NT : 1;
82	/** Bit 15 - 0 - Reserved flag. */
83	unsigned u1Reserved3 : 1;
84	/** Bit 16 - RF - Resume flag - System flag. */
85	unsigned u1RF : 1;
86	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
87	unsigned u1VM : 1;
88	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
89	unsigned u1AC : 1;
90	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
91	unsigned u1VIF : 1;
92	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
93	unsigned u1VIP : 1;
94	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
95	unsigned u1ID : 1;
96	/** Bit 22-31 - 0 - Reserved flag. */
97	unsigned u10Reserved4 : 10;
98	} X86EFLAGSBITS;
99	/** Pointer to EFLAGS bits. */
100	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
101	/** Pointer to const EFLAGS bits. */
102	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
103
104	/**
105	* EFLAGS.
106	*/
107	typedef union X86EFLAGS
108	{
109	/** The plain unsigned view. */
110	uint32_t u;
111	/** The bitfield view. */
112	X86EFLAGSBITS Bits;
113	/** The 8-bit view. */
114	uint8_t au8[4];
115	/** The 16-bit view. */
116	uint16_t au16[2];
117	/** The 32-bit view. */
118	uint32_t au32[1];
119	/** The 32-bit view. */
120	uint32_t u32;
121	} X86EFLAGS;
122	/** Pointer to EFLAGS. */
123	typedef X86EFLAGS *PX86EFLAGS;
124	/** Pointer to const EFLAGS. */
125	typedef const X86EFLAGS *PCX86EFLAGS;
126
127	/**
128	* RFLAGS (32 upper bits are reserved).
129	*/
130	typedef union X86RFLAGS
131	{
132	/** The plain unsigned view. */
133	uint64_t u;
134	/** The bitfield view. */
135	X86EFLAGSBITS Bits;
136	/** The 8-bit view. */
137	uint8_t au8[8];
138	/** The 16-bit view. */
139	uint16_t au16[4];
140	/** The 32-bit view. */
141	uint32_t au32[2];
142	/** The 64-bit view. */
143	uint64_t au64[1];
144	/** The 64-bit view. */
145	uint64_t u64;
146	} X86RFLAGS;
147	/** Pointer to RFLAGS. */
148	typedef X86RFLAGS *PX86RFLAGS;
149	/** Pointer to const RFLAGS. */
150	typedef const X86RFLAGS *PCX86RFLAGS;
151
152
153	/** @name EFLAGS
154	* @{
155	*/
156	/** Bit 0 - CF - Carry flag - Status flag. */
157	#define X86_EFL_CF RT_BIT(0)
158	/** Bit 1 - Reserved, reads as 1. */
159	#define X86_EFL_1 RT_BIT(1)
160	/** Bit 2 - PF - Parity flag - Status flag. */
161	#define X86_EFL_PF RT_BIT(2)
162	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
163	#define X86_EFL_AF RT_BIT(4)
164	/** Bit 6 - ZF - Zero flag - Status flag. */
165	#define X86_EFL_ZF RT_BIT(6)
166	/** Bit 7 - SF - Signed flag - Status flag. */
167	#define X86_EFL_SF RT_BIT(7)
168	/** Bit 8 - TF - Trap flag - System flag. */
169	#define X86_EFL_TF RT_BIT(8)
170	/** Bit 9 - IF - Interrupt flag - System flag. */
171	#define X86_EFL_IF RT_BIT(9)
172	/** Bit 10 - DF - Direction flag - Control flag. */
173	#define X86_EFL_DF RT_BIT(10)
174	/** Bit 11 - OF - Overflow flag - Status flag. */
175	#define X86_EFL_OF RT_BIT(11)
176	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
177	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
178	/** Bit 14 - NT - Nested task flag - System flag. */
179	#define X86_EFL_NT RT_BIT(14)
180	/** Bit 16 - RF - Resume flag - System flag. */
181	#define X86_EFL_RF RT_BIT(16)
182	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
183	#define X86_EFL_VM RT_BIT(17)
184	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
185	#define X86_EFL_AC RT_BIT(18)
186	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
187	#define X86_EFL_VIF RT_BIT(19)
188	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
189	#define X86_EFL_VIP RT_BIT(20)
190	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
191	#define X86_EFL_ID RT_BIT(21)
192	/** IOPL shift. */
193	#define X86_EFL_IOPL_SHIFT 12
194	/** The the IOPL level from the flags. */
195	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
196	/** Bits restored by popf */
197	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
198	/** @} */
199
200
201	/** CPUID Feature information - ECX.
202	* CPUID query with EAX=1.
203	*/
204	typedef struct X86CPUIDFEATECX
205	{
206	/** Bit 0 - SSE3 - Supports SSE3 or not. */
207	unsigned u1SSE3 : 1;
208	/** Bit 1 - PCLMULQDQ. */
209	unsigned u1PCLMULQDQ : 1;
210	/** Bit 2 - DS Area 64-bit layout. */
211	unsigned u1DTE64 : 1;
212	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
213	unsigned u1Monitor : 1;
214	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
215	unsigned u1CPLDS : 1;
216	/** Bit 5 - VMX - Virtual Machine Technology. */
217	unsigned u1VMX : 1;
218	/** Bit 6 - SMX: Safer Mode Extensions. */
219	unsigned u1SMX : 1;
220	/** Bit 7 - EST - Enh. SpeedStep Tech. */
221	unsigned u1EST : 1;
222	/** Bit 8 - TM2 - Terminal Monitor 2. */
223	unsigned u1TM2 : 1;
224	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
225	unsigned u1SSSE3 : 1;
226	/** Bit 10 - CNTX-ID - L1 Context ID. */
227	unsigned u1CNTXID : 1;
228	/** Bit 11 - Reserved. */
229	unsigned u1Reserved1 : 1;
230	/** Bit 12 - FMA. */
231	unsigned u1FMA : 1;
232	/** Bit 13 - CX16 - CMPXCHG16B. */
233	unsigned u1CX16 : 1;
234	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
235	unsigned u1TPRUpdate : 1;
236	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
237	unsigned u1PDCM : 1;
238	/** Bit 16 - Reserved. */
239	unsigned u1Reserved2 : 1;
240	/** Bit 17 - PCID - Process-context identifiers. */
241	unsigned u1PCID : 1;
242	/** Bit 18 - Direct Cache Access. */
243	unsigned u1DCA : 1;
244	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
245	unsigned u1SSE4_1 : 1;
246	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
247	unsigned u1SSE4_2 : 1;
248	/** Bit 21 - x2APIC. */
249	unsigned u1x2APIC : 1;
250	/** Bit 22 - MOVBE - Supports MOVBE. */
251	unsigned u1MOVBE : 1;
252	/** Bit 23 - POPCNT - Supports POPCNT. */
253	unsigned u1POPCNT : 1;
254	/** Bit 24 - TSC-Deadline. */
255	unsigned u1TSCDEADLINE : 1;
256	/** Bit 25 - AES. */
257	unsigned u1AES : 1;
258	/** Bit 26 - XSAVE - Supports XSAVE. */
259	unsigned u1XSAVE : 1;
260	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
261	unsigned u1OSXSAVE : 1;
262	/** Bit 28 - AVX - Supports AVX instruction extensions. */
263	unsigned u1AVX : 1;
264	/** Bit 29 - 30 - Reserved */
265	unsigned u2Reserved3 : 2;
266	/** Bit 31 - Hypervisor present (we're a guest). */
267	unsigned u1HVP : 1;
268	} X86CPUIDFEATECX;
269	/** Pointer to CPUID Feature Information - ECX. */
270	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
271	/** Pointer to const CPUID Feature Information - ECX. */
272	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
273
274
275	/** CPUID Feature Information - EDX.
276	* CPUID query with EAX=1.
277	*/
278	typedef struct X86CPUIDFEATEDX
279	{
280	/** Bit 0 - FPU - x87 FPU on Chip. */
281	unsigned u1FPU : 1;
282	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
283	unsigned u1VME : 1;
284	/** Bit 2 - DE - Debugging extensions. */
285	unsigned u1DE : 1;
286	/** Bit 3 - PSE - Page Size Extension. */
287	unsigned u1PSE : 1;
288	/** Bit 4 - TSC - Time Stamp Counter. */
289	unsigned u1TSC : 1;
290	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
291	unsigned u1MSR : 1;
292	/** Bit 6 - PAE - Physical Address Extension. */
293	unsigned u1PAE : 1;
294	/** Bit 7 - MCE - Machine Check Exception. */
295	unsigned u1MCE : 1;
296	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
297	unsigned u1CX8 : 1;
298	/** Bit 9 - APIC - APIC On-Chip. */
299	unsigned u1APIC : 1;
300	/** Bit 10 - Reserved. */
301	unsigned u1Reserved1 : 1;
302	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
303	unsigned u1SEP : 1;
304	/** Bit 12 - MTRR - Memory Type Range Registers. */
305	unsigned u1MTRR : 1;
306	/** Bit 13 - PGE - PTE Global Bit. */
307	unsigned u1PGE : 1;
308	/** Bit 14 - MCA - Machine Check Architecture. */
309	unsigned u1MCA : 1;
310	/** Bit 15 - CMOV - Conditional Move Instructions. */
311	unsigned u1CMOV : 1;
312	/** Bit 16 - PAT - Page Attribute Table. */
313	unsigned u1PAT : 1;
314	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
315	unsigned u1PSE36 : 1;
316	/** Bit 18 - PSN - Processor Serial Number. */
317	unsigned u1PSN : 1;
318	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
319	unsigned u1CLFSH : 1;
320	/** Bit 20 - Reserved. */
321	unsigned u1Reserved2 : 1;
322	/** Bit 21 - DS - Debug Store. */
323	unsigned u1DS : 1;
324	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
325	unsigned u1ACPI : 1;
326	/** Bit 23 - MMX - Intel MMX 'Technology'. */
327	unsigned u1MMX : 1;
328	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
329	unsigned u1FXSR : 1;
330	/** Bit 25 - SSE - SSE Support. */
331	unsigned u1SSE : 1;
332	/** Bit 26 - SSE2 - SSE2 Support. */
333	unsigned u1SSE2 : 1;
334	/** Bit 27 - SS - Self Snoop. */
335	unsigned u1SS : 1;
336	/** Bit 28 - HTT - Hyper-Threading Technology. */
337	unsigned u1HTT : 1;
338	/** Bit 29 - TM - Thermal Monitor. */
339	unsigned u1TM : 1;
340	/** Bit 30 - Reserved - . */
341	unsigned u1Reserved3 : 1;
342	/** Bit 31 - PBE - Pending Break Enabled. */
343	unsigned u1PBE : 1;
344	} X86CPUIDFEATEDX;
345	/** Pointer to CPUID Feature Information - EDX. */
346	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
347	/** Pointer to const CPUID Feature Information - EDX. */
348	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
349
350	/** @name CPUID Vendor information.
351	* CPUID query with EAX=0.
352	* @{
353	*/
354	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
355	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
356	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
357
358	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
359	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
360	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
361	/** @} */
362
363
364	/** @name CPUID Feature information.
365	* CPUID query with EAX=1.
366	* @{
367	*/
368	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
369	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
370	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
371	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
372	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
373	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
374	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
375	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
376	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
377	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
378	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
379	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
380	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
381	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
382	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
383	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
384	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
385	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
386	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
387	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
388	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
389	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
390	/** ECX Bit 12 - FMA. */
391	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
392	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
393	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
394	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
395	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
396	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
397	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
398	/** ECX Bit 17 - PCID - Process-context identifiers. */
399	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
400	/** ECX Bit 18 - DCA - Direct Cache Access. */
401	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
402	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
403	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
404	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
405	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
406	/** ECX Bit 21 - x2APIC support. */
407	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
408	/** ECX Bit 22 - MOVBE instruction. */
409	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
410	/** ECX Bit 23 - POPCNT instruction. */
411	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
412	/** ECX Bir 24 - TSC-Deadline. */
413	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
414	/** ECX Bit 25 - AES instructions. */
415	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
416	/** ECX Bit 26 - XSAVE instruction. */
417	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
418	/** ECX Bit 27 - OSXSAVE instruction. */
419	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
420	/** ECX Bit 28 - AVX. */
421	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
422	/** ECX Bit 31 - Hypervisor Present (software only). */
423	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
424
425
426	/** Bit 0 - FPU - x87 FPU on Chip. */
427	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
428	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
429	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
430	/** Bit 2 - DE - Debugging extensions. */
431	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
432	/** Bit 3 - PSE - Page Size Extension. */
433	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
434	/** Bit 4 - TSC - Time Stamp Counter. */
435	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
436	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
437	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
438	/** Bit 6 - PAE - Physical Address Extension. */
439	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
440	/** Bit 7 - MCE - Machine Check Exception. */
441	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
442	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
443	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
444	/** Bit 9 - APIC - APIC On-Chip. */
445	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
446	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
447	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
448	/** Bit 12 - MTRR - Memory Type Range Registers. */
449	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
450	/** Bit 13 - PGE - PTE Global Bit. */
451	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
452	/** Bit 14 - MCA - Machine Check Architecture. */
453	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
454	/** Bit 15 - CMOV - Conditional Move Instructions. */
455	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
456	/** Bit 16 - PAT - Page Attribute Table. */
457	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
458	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
459	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
460	/** Bit 18 - PSN - Processor Serial Number. */
461	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
462	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
463	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
464	/** Bit 21 - DS - Debug Store. */
465	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
466	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
467	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
468	/** Bit 23 - MMX - Intel MMX Technology. */
469	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
470	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
471	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
472	/** Bit 25 - SSE - SSE Support. */
473	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
474	/** Bit 26 - SSE2 - SSE2 Support. */
475	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
476	/** Bit 27 - SS - Self Snoop. */
477	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
478	/** Bit 28 - HTT - Hyper-Threading Technology. */
479	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
480	/** Bit 29 - TM - Therm. Monitor. */
481	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
482	/** Bit 31 - PBE - Pending Break Enabled. */
483	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
484	/** @} */
485
486	/** @name CPUID mwait/monitor information.
487	* CPUID query with EAX=5.
488	* @{
489	*/
490	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
491	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
492	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
493	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
494	/** @} */
495
496
497	/** @name CPUID AMD Feature information.
498	* CPUID query with EAX=0x80000001.
499	* @{
500	*/
501	/** Bit 0 - FPU - x87 FPU on Chip. */
502	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
503	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
504	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
505	/** Bit 2 - DE - Debugging extensions. */
506	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
507	/** Bit 3 - PSE - Page Size Extension. */
508	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
509	/** Bit 4 - TSC - Time Stamp Counter. */
510	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
511	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
512	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
513	/** Bit 6 - PAE - Physical Address Extension. */
514	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
515	/** Bit 7 - MCE - Machine Check Exception. */
516	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
517	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
518	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
519	/** Bit 9 - APIC - APIC On-Chip. */
520	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
521	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
522	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
523	/** Bit 12 - MTRR - Memory Type Range Registers. */
524	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
525	/** Bit 13 - PGE - PTE Global Bit. */
526	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
527	/** Bit 14 - MCA - Machine Check Architecture. */
528	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
529	/** Bit 15 - CMOV - Conditional Move Instructions. */
530	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
531	/** Bit 16 - PAT - Page Attribute Table. */
532	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
533	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
534	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
535	/** Bit 20 - NX - AMD No-Execute Page Protection. */
536	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
537	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
538	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
539	/** Bit 23 - MMX - Intel MMX Technology. */
540	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
541	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
542	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
543	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
544	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
545	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
546	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
547	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
548	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
549	/** Bit 29 - LM - AMD Long Mode. */
550	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
551	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
552	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
553	/** Bit 31 - 3DNOW - AMD 3DNow. */
554	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
555
556	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
557	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
558	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
559	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
560	/** Bit 2 - SVM - AMD VM extensions. */
561	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
562	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
563	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
564	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
565	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
566	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
567	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
568	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
569	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
570	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
571	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
572	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
573	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
574	/** Bit 9 - OSVW - AMD OS visible workaround. */
575	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
576	/** Bit 10 - IBS - Instruct based sampling. */
577	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
578	/** Bit 11 - SSE5 - SSE5 instruction support. */
579	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
580	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
581	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
582	/** Bit 13 - WDT - AMD Watchdog timer support. */
583	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
584
585	/** @} */
586
587
588	/** @name CPUID AMD Feature information.
589	* CPUID query with EAX=0x80000007.
590	* @{
591	*/
592	/** Bit 0 - TS - Temperature Sensor. */
593	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
594	/** Bit 1 - FID - Frequency ID Control. */
595	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
596	/** Bit 2 - VID - Voltage ID Control. */
597	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
598	/** Bit 3 - TTP - THERMTRIP. */
599	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
600	/** Bit 4 - TM - Hardware Thermal Control. */
601	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
602	/** Bit 5 - STC - Software Thermal Control. */
603	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
604	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
605	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
606	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
607	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
608	/** Bit 8 - TSCINVAR - TSC Invariant. */
609	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
610	/** @} */
611
612
613	/** @name CR0
614	* @{ */
615	/** Bit 0 - PE - Protection Enabled */
616	#define X86_CR0_PE RT_BIT(0)
617	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
618	/** Bit 1 - MP - Monitor Coprocessor */
619	#define X86_CR0_MP RT_BIT(1)
620	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
621	/** Bit 2 - EM - Emulation. */
622	#define X86_CR0_EM RT_BIT(2)
623	#define X86_CR0_EMULATE_FPU RT_BIT(2)
624	/** Bit 3 - TS - Task Switch. */
625	#define X86_CR0_TS RT_BIT(3)
626	#define X86_CR0_TASK_SWITCH RT_BIT(3)
627	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
628	#define X86_CR0_ET RT_BIT(4)
629	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
630	/** Bit 5 - NE - Numeric error. */
631	#define X86_CR0_NE RT_BIT(5)
632	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
633	/** Bit 16 - WP - Write Protect. */
634	#define X86_CR0_WP RT_BIT(16)
635	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
636	/** Bit 18 - AM - Alignment Mask. */
637	#define X86_CR0_AM RT_BIT(18)
638	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
639	/** Bit 29 - NW - Not Write-though. */
640	#define X86_CR0_NW RT_BIT(29)
641	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
642	/** Bit 30 - WP - Cache Disable. */
643	#define X86_CR0_CD RT_BIT(30)
644	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
645	/** Bit 31 - PG - Paging. */
646	#define X86_CR0_PG RT_BIT(31)
647	#define X86_CR0_PAGING RT_BIT(31)
648	/** @} */
649
650
651	/** @name CR3
652	* @{ */
653	/** Bit 3 - PWT - Page-level Writes Transparent. */
654	#define X86_CR3_PWT RT_BIT(3)
655	/** Bit 4 - PCD - Page-level Cache Disable. */
656	#define X86_CR3_PCD RT_BIT(4)
657	/** Bits 12-31 - - Page directory page number. */
658	#define X86_CR3_PAGE_MASK (0xfffff000)
659	/** Bits 5-31 - - PAE Page directory page number. */
660	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
661	/** Bits 12-51 - - AMD64 Page directory page number. */
662	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
663	/** @} */
664
665
666	/** @name CR4
667	* @{ */
668	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
669	#define X86_CR4_VME RT_BIT(0)
670	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
671	#define X86_CR4_PVI RT_BIT(1)
672	/** Bit 2 - TSD - Time Stamp Disable. */
673	#define X86_CR4_TSD RT_BIT(2)
674	/** Bit 3 - DE - Debugging Extensions. */
675	#define X86_CR4_DE RT_BIT(3)
676	/** Bit 4 - PSE - Page Size Extension. */
677	#define X86_CR4_PSE RT_BIT(4)
678	/** Bit 5 - PAE - Physical Address Extension. */
679	#define X86_CR4_PAE RT_BIT(5)
680	/** Bit 6 - MCE - Machine-Check Enable. */
681	#define X86_CR4_MCE RT_BIT(6)
682	/** Bit 7 - PGE - Page Global Enable. */
683	#define X86_CR4_PGE RT_BIT(7)
684	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
685	#define X86_CR4_PCE RT_BIT(8)
686	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
687	#define X86_CR4_OSFSXR RT_BIT(9)
688	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
689	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
690	/** Bit 13 - VMXE - VMX mode is enabled. */
691	#define X86_CR4_VMXE RT_BIT(13)
692	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
693	#define X86_CR4_SMXE RT_BIT(14)
694	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
695	#define X86_CR4_PCIDE RT_BIT(17)
696	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
697	* extended states. */
698	#define X86_CR4_OSXSAVE RT_BIT(18)
699	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
700	#define X86_CR4_SMEP RT_BIT(20)
701	/** @} */
702
703
704	/** @name DR6
705	* @{ */
706	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
707	#define X86_DR6_B0 RT_BIT(0)
708	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
709	#define X86_DR6_B1 RT_BIT(1)
710	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
711	#define X86_DR6_B2 RT_BIT(2)
712	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
713	#define X86_DR6_B3 RT_BIT(3)
714	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
715	#define X86_DR6_BD RT_BIT(13)
716	/** Bit 14 - BS - Single step */
717	#define X86_DR6_BS RT_BIT(14)
718	/** Bit 15 - BT - Task switch. (TSS T bit.) */
719	#define X86_DR6_BT RT_BIT(15)
720	/** Value of DR6 after powerup/reset. */
721	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
722	/** @} */
723
724
725	/** @name DR7
726	* @{ */
727	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
728	#define X86_DR7_L0 RT_BIT(0)
729	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
730	#define X86_DR7_G0 RT_BIT(1)
731	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
732	#define X86_DR7_L1 RT_BIT(2)
733	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
734	#define X86_DR7_G1 RT_BIT(3)
735	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
736	#define X86_DR7_L2 RT_BIT(4)
737	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
738	#define X86_DR7_G2 RT_BIT(5)
739	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
740	#define X86_DR7_L3 RT_BIT(6)
741	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
742	#define X86_DR7_G3 RT_BIT(7)
743	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
744	#define X86_DR7_LE RT_BIT(8)
745	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
746	#define X86_DR7_GE RT_BIT(9)
747
748	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
749	* any DR register is accessed. */
750	#define X86_DR7_GD RT_BIT(13)
751	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
752	#define X86_DR7_RW0_MASK (3 << 16)
753	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
754	#define X86_DR7_LEN0_MASK (3 << 18)
755	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
756	#define X86_DR7_RW1_MASK (3 << 20)
757	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
758	#define X86_DR7_LEN1_MASK (3 << 22)
759	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
760	#define X86_DR7_RW2_MASK (3 << 24)
761	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
762	#define X86_DR7_LEN2_MASK (3 << 26)
763	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
764	#define X86_DR7_RW3_MASK (3 << 28)
765	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
766	#define X86_DR7_LEN3_MASK (3 << 30)
767
768	/** Bits which must be 1s. */
769	#define X86_DR7_MB1_MASK (RT_BIT(10))
770
771	/** Calcs the L bit of Nth breakpoint.
772	* @param iBp The breakpoint number [0..3].
773	*/
774	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
775
776	/** Calcs the G bit of Nth breakpoint.
777	* @param iBp The breakpoint number [0..3].
778	*/
779	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
780
781	/** @name Read/Write values.
782	* @{ */
783	/** Break on instruction fetch only. */
784	#define X86_DR7_RW_EO 0U
785	/** Break on write only. */
786	#define X86_DR7_RW_WO 1U
787	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
788	#define X86_DR7_RW_IO 2U
789	/** Break on read or write (but not instruction fetches). */
790	#define X86_DR7_RW_RW 3U
791	/** @} */
792
793	/** Shifts a X86_DR7_RW_* value to its right place.
794	* @param iBp The breakpoint number [0..3].
795	* @param fRw One of the X86_DR7_RW_* value.
796	*/
797	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
798
799	/** @name Length values.
800	* @{ */
801	#define X86_DR7_LEN_BYTE 0U
802	#define X86_DR7_LEN_WORD 1U
803	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
804	#define X86_DR7_LEN_DWORD 3U
805	/** @} */
806
807	/** Shifts a X86_DR7_LEN_* value to its right place.
808	* @param iBp The breakpoint number [0..3].
809	* @param cb One of the X86_DR7_LEN_* values.
810	*/
811	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
812
813	/** Fetch the breakpoint length bits from the DR7 value.
814	* @param uDR7 DR7 value
815	* @param iBp The breakpoint number [0..3].
816	*/
817	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
818
819	/** Mask used to check if any breakpoints are enabled. */
820	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
821
822	/** Mask used to check if any io breakpoints are set. */
823	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
824
825	/** Value of DR7 after powerup/reset. */
826	#define X86_DR7_INIT_VAL 0x400
827	/** @} */
828
829
830	/** @name Machine Specific Registers
831	* @{
832	*/
833
834	/** Time Stamp Counter. */
835	#define MSR_IA32_TSC 0x10
836
837	#define MSR_IA32_PLATFORM_ID 0x17
838
839	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
840	#define MSR_IA32_APICBASE 0x1b
841	#endif
842
843	/** CPU Feature control. */
844	#define MSR_IA32_FEATURE_CONTROL 0x3A
845	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
846	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
847
848	/** BIOS update trigger (microcode update). */
849	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
850
851	/** BIOS update signature (microcode). */
852	#define MSR_IA32_BIOS_SIGN_ID 0x8B
853
854	/** General performance counter no. 0. */
855	#define MSR_IA32_PMC0 0xC1
856	/** General performance counter no. 1. */
857	#define MSR_IA32_PMC1 0xC2
858	/** General performance counter no. 2. */
859	#define MSR_IA32_PMC2 0xC3
860	/** General performance counter no. 3. */
861	#define MSR_IA32_PMC3 0xC4
862
863	/** Nehalem power control. */
864	#define MSR_IA32_PLATFORM_INFO 0xCE
865
866	/** Get FSB clock status (Intel-specific). */
867	#define MSR_IA32_FSB_CLOCK_STS 0xCD
868
869	/** MTRR Capabilities. */
870	#define MSR_IA32_MTRR_CAP 0xFE
871
872
873	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
874	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
875	* R0 SS == CS + 8
876	* R3 CS == CS + 16
877	* R3 SS == CS + 24
878	*/
879	#define MSR_IA32_SYSENTER_CS 0x174
880	/** SYSENTER_ESP - the R0 ESP. */
881	#define MSR_IA32_SYSENTER_ESP 0x175
882	/** SYSENTER_EIP - the R0 EIP. */
883	#define MSR_IA32_SYSENTER_EIP 0x176
884	#endif
885
886	/** Machine Check Global Capabilities Register. */
887	#define MSR_IA32_MCP_CAP 0x179
888	/** Machine Check Global Status Register. */
889	#define MSR_IA32_MCP_STATUS 0x17A
890	/** Machine Check Global Control Register. */
891	#define MSR_IA32_MCP_CTRL 0x17B
892
893	/** Trace/Profile Resource Control (R/W) */
894	#define MSR_IA32_DEBUGCTL 0x1D9
895
896	/** Page Attribute Table. */
897	#define MSR_IA32_CR_PAT 0x277
898
899	/** Performance counter MSRs. (Intel only) */
900	#define MSR_IA32_PERFEVTSEL0 0x186
901	#define MSR_IA32_PERFEVTSEL1 0x187
902	#define MSR_IA32_FLEX_RATIO 0x194
903	#define MSR_IA32_PERF_STATUS 0x198
904	#define MSR_IA32_PERF_CTL 0x199
905	#define MSR_IA32_THERM_STATUS 0x19c
906
907	/** Enable misc. processor features (R/W). */
908	#define MSR_IA32_MISC_ENABLE 0x1A0
909	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
910	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
911	/** Automatic Thermal Control Circuit Enable (R/W). */
912	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
913	/** Performance Monitoring Available (R). */
914	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
915	/** Branch Trace Storage Unavailable (R/O). */
916	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
917	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
918	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
919	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
920	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
921	/** If MONITOR/MWAIT is supported (R/W). */
922	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
923	/** Limit CPUID Maxval to 3 leafs (R/W). */
924	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
925	/** When set to 1, xTPR messages are disabled (R/W). */
926	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
927	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
928	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
929
930	#define IA32_MTRR_PHYSBASE0 0x200
931	#define IA32_MTRR_PHYSMASK0 0x201
932	#define IA32_MTRR_PHYSBASE1 0x202
933	#define IA32_MTRR_PHYSMASK1 0x203
934	#define IA32_MTRR_PHYSBASE2 0x204
935	#define IA32_MTRR_PHYSMASK2 0x205
936	#define IA32_MTRR_PHYSBASE3 0x206
937	#define IA32_MTRR_PHYSMASK3 0x207
938	#define IA32_MTRR_PHYSBASE4 0x208
939	#define IA32_MTRR_PHYSMASK4 0x209
940	#define IA32_MTRR_PHYSBASE5 0x20a
941	#define IA32_MTRR_PHYSMASK5 0x20b
942	#define IA32_MTRR_PHYSBASE6 0x20c
943	#define IA32_MTRR_PHYSMASK6 0x20d
944	#define IA32_MTRR_PHYSBASE7 0x20e
945	#define IA32_MTRR_PHYSMASK7 0x20f
946	#define IA32_MTRR_PHYSBASE8 0x210
947	#define IA32_MTRR_PHYSMASK8 0x211
948	#define IA32_MTRR_PHYSBASE9 0x212
949	#define IA32_MTRR_PHYSMASK9 0x213
950
951	/** Fixed range MTRRs.
952	* @{ */
953	#define IA32_MTRR_FIX64K_00000 0x250
954	#define IA32_MTRR_FIX16K_80000 0x258
955	#define IA32_MTRR_FIX16K_A0000 0x259
956	#define IA32_MTRR_FIX4K_C0000 0x268
957	#define IA32_MTRR_FIX4K_C8000 0x269
958	#define IA32_MTRR_FIX4K_D0000 0x26a
959	#define IA32_MTRR_FIX4K_D8000 0x26b
960	#define IA32_MTRR_FIX4K_E0000 0x26c
961	#define IA32_MTRR_FIX4K_E8000 0x26d
962	#define IA32_MTRR_FIX4K_F0000 0x26e
963	#define IA32_MTRR_FIX4K_F8000 0x26f
964	/** @} */
965
966	/** MTRR Default Range. */
967	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
968
969	#define MSR_IA32_MC0_CTL 0x400
970	#define MSR_IA32_MC0_STATUS 0x401
971
972	/** Basic VMX information. */
973	#define MSR_IA32_VMX_BASIC_INFO 0x480
974	/** Allowed settings for pin-based VM execution controls */
975	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
976	/** Allowed settings for proc-based VM execution controls */
977	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
978	/** Allowed settings for the VMX exit controls. */
979	#define MSR_IA32_VMX_EXIT_CTLS 0x483
980	/** Allowed settings for the VMX entry controls. */
981	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
982	/** Misc VMX info. */
983	#define MSR_IA32_VMX_MISC 0x485
984	/** Fixed cleared bits in CR0. */
985	#define MSR_IA32_VMX_CR0_FIXED0 0x486
986	/** Fixed set bits in CR0. */
987	#define MSR_IA32_VMX_CR0_FIXED1 0x487
988	/** Fixed cleared bits in CR4. */
989	#define MSR_IA32_VMX_CR4_FIXED0 0x488
990	/** Fixed set bits in CR4. */
991	#define MSR_IA32_VMX_CR4_FIXED1 0x489
992	/** Information for enumerating fields in the VMCS. */
993	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
994	/** Allowed settings for secondary proc-based VM execution controls */
995	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
996	/** EPT capabilities. */
997	#define MSR_IA32_VMX_EPT_CAPS 0x48C
998	/** DS Save Area (R/W). */
999	#define MSR_IA32_DS_AREA 0x600
1000	/** X2APIC MSR ranges. */
1001	#define MSR_IA32_APIC_START 0x800
1002	#define MSR_IA32_APIC_END 0x900
1003
1004	/** K6 EFER - Extended Feature Enable Register. */
1005	#define MSR_K6_EFER 0xc0000080
1006	/** @todo document EFER */
1007	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1008	#define MSR_K6_EFER_SCE RT_BIT(0)
1009	/** Bit 8 - LME - Long mode enabled. (R/W) */
1010	#define MSR_K6_EFER_LME RT_BIT(8)
1011	/** Bit 10 - LMA - Long mode active. (R) */
1012	#define MSR_K6_EFER_LMA RT_BIT(10)
1013	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1014	#define MSR_K6_EFER_NXE RT_BIT(11)
1015	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1016	#define MSR_K6_EFER_SVME RT_BIT(12)
1017	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1018	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1019	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1020	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1021	/** K6 STAR - SYSCALL/RET targets. */
1022	#define MSR_K6_STAR 0xc0000081
1023	/** Shift value for getting the SYSRET CS and SS value. */
1024	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1025	/** Shift value for getting the SYSCALL CS and SS value. */
1026	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1027	/** Selector mask for use after shifting. */
1028	#define MSR_K6_STAR_SEL_MASK 0xffff
1029	/** The mask which give the SYSCALL EIP. */
1030	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1031	/** K6 WHCR - Write Handling Control Register. */
1032	#define MSR_K6_WHCR 0xc0000082
1033	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1034	#define MSR_K6_UWCCR 0xc0000085
1035	/** K6 PSOR - Processor State Observability Register. */
1036	#define MSR_K6_PSOR 0xc0000087
1037	/** K6 PFIR - Page Flush/Invalidate Register. */
1038	#define MSR_K6_PFIR 0xc0000088
1039
1040	/** Performance counter MSRs. (AMD only) */
1041	#define MSR_K7_EVNTSEL0 0xc0010000
1042	#define MSR_K7_EVNTSEL1 0xc0010001
1043	#define MSR_K7_EVNTSEL2 0xc0010002
1044	#define MSR_K7_EVNTSEL3 0xc0010003
1045	#define MSR_K7_PERFCTR0 0xc0010004
1046	#define MSR_K7_PERFCTR1 0xc0010005
1047	#define MSR_K7_PERFCTR2 0xc0010006
1048	#define MSR_K7_PERFCTR3 0xc0010007
1049
1050	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1051	#define MSR_K8_LSTAR 0xc0000082
1052	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1053	#define MSR_K8_CSTAR 0xc0000083
1054	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1055	#define MSR_K8_SF_MASK 0xc0000084
1056	/** K8 FS.base - The 64-bit base FS register. */
1057	#define MSR_K8_FS_BASE 0xc0000100
1058	/** K8 GS.base - The 64-bit base GS register. */
1059	#define MSR_K8_GS_BASE 0xc0000101
1060	/** K8 KernelGSbase - Used with SWAPGS. */
1061	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1062	#define MSR_K8_TSC_AUX 0xc0000103
1063	#define MSR_K8_SYSCFG 0xc0010010
1064	#define MSR_K8_HWCR 0xc0010015
1065	#define MSR_K8_IORRBASE0 0xc0010016
1066	#define MSR_K8_IORRMASK0 0xc0010017
1067	#define MSR_K8_IORRBASE1 0xc0010018
1068	#define MSR_K8_IORRMASK1 0xc0010019
1069	#define MSR_K8_TOP_MEM1 0xc001001a
1070	#define MSR_K8_TOP_MEM2 0xc001001d
1071	#define MSR_K8_VM_CR 0xc0010114
1072	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1073
1074	#define MSR_K8_IGNNE 0xc0010115
1075	#define MSR_K8_SMM_CTL 0xc0010116
1076	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1077	* host state during world switch.
1078	*/
1079	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1080
1081	/** @} */
1082
1083
1084	/** @name Page Table / Directory / Directory Pointers / L4.
1085	* @{
1086	*/
1087
1088	/** Page table/directory entry as an unsigned integer. */
1089	typedef uint32_t X86PGUINT;
1090	/** Pointer to a page table/directory table entry as an unsigned integer. */
1091	typedef X86PGUINT *PX86PGUINT;
1092	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1093	typedef X86PGUINT const *PCX86PGUINT;
1094
1095	/** Number of entries in a 32-bit PT/PD. */
1096	#define X86_PG_ENTRIES 1024
1097
1098
1099	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1100	typedef uint64_t X86PGPAEUINT;
1101	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1102	typedef X86PGPAEUINT *PX86PGPAEUINT;
1103	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1104	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1105
1106	/** Number of entries in a PAE PT/PD. */
1107	#define X86_PG_PAE_ENTRIES 512
1108	/** Number of entries in a PAE PDPT. */
1109	#define X86_PG_PAE_PDPE_ENTRIES 4
1110
1111	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1112	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1113	/** Number of entries in an AMD64 PDPT.
1114	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1115	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1116
1117	/** The size of a 4KB page. */
1118	#define X86_PAGE_4K_SIZE _4K
1119	/** The page shift of a 4KB page. */
1120	#define X86_PAGE_4K_SHIFT 12
1121	/** The 4KB page offset mask. */
1122	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1123	/** The 4KB page base mask for virtual addresses. */
1124	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1125	/** The 4KB page base mask for virtual addresses - 32bit version. */
1126	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1127
1128	/** The size of a 2MB page. */
1129	#define X86_PAGE_2M_SIZE _2M
1130	/** The page shift of a 2MB page. */
1131	#define X86_PAGE_2M_SHIFT 21
1132	/** The 2MB page offset mask. */
1133	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1134	/** The 2MB page base mask for virtual addresses. */
1135	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1136	/** The 2MB page base mask for virtual addresses - 32bit version. */
1137	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1138
1139	/** The size of a 4MB page. */
1140	#define X86_PAGE_4M_SIZE _4M
1141	/** The page shift of a 4MB page. */
1142	#define X86_PAGE_4M_SHIFT 22
1143	/** The 4MB page offset mask. */
1144	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1145	/** The 4MB page base mask for virtual addresses. */
1146	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1147	/** The 4MB page base mask for virtual addresses - 32bit version. */
1148	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1149
1150
1151
1152	/** @name Page Table Entry
1153	* @{
1154	*/
1155	/** Bit 0 - P - Present bit. */
1156	#define X86_PTE_BIT_P 0
1157	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1158	#define X86_PTE_BIT_RW 1
1159	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1160	#define X86_PTE_BIT_US 2
1161	/** Bit 3 - PWT - Page level write thru bit. */
1162	#define X86_PTE_BIT_PWT 3
1163	/** Bit 4 - PCD - Page level cache disable bit. */
1164	#define X86_PTE_BIT_PCD 4
1165	/** Bit 5 - A - Access bit. */
1166	#define X86_PTE_BIT_A 5
1167	/** Bit 6 - D - Dirty bit. */
1168	#define X86_PTE_BIT_D 6
1169	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1170	#define X86_PTE_BIT_PAT 7
1171	/** Bit 8 - G - Global flag. */
1172	#define X86_PTE_BIT_G 8
1173
1174	/** Bit 0 - P - Present bit mask. */
1175	#define X86_PTE_P RT_BIT(0)
1176	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1177	#define X86_PTE_RW RT_BIT(1)
1178	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1179	#define X86_PTE_US RT_BIT(2)
1180	/** Bit 3 - PWT - Page level write thru bit mask. */
1181	#define X86_PTE_PWT RT_BIT(3)
1182	/** Bit 4 - PCD - Page level cache disable bit mask. */
1183	#define X86_PTE_PCD RT_BIT(4)
1184	/** Bit 5 - A - Access bit mask. */
1185	#define X86_PTE_A RT_BIT(5)
1186	/** Bit 6 - D - Dirty bit mask. */
1187	#define X86_PTE_D RT_BIT(6)
1188	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1189	#define X86_PTE_PAT RT_BIT(7)
1190	/** Bit 8 - G - Global bit mask. */
1191	#define X86_PTE_G RT_BIT(8)
1192
1193	/** Bits 9-11 - - Available for use to system software. */
1194	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1195	/** Bits 12-31 - - Physical Page number of the next level. */
1196	#define X86_PTE_PG_MASK ( 0xfffff000 )
1197
1198	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1199	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1200	/** Bits 63 - NX - PAE/LM - No execution flag. */
1201	#define X86_PTE_PAE_NX RT_BIT_64(63)
1202	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1203	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1204	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1205	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1206	/** No bits - - LM - MBZ bits when NX is active. */
1207	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1208	/** Bits 63 - - LM - MBZ bits when no NX. */
1209	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1210
1211	/**
1212	* Page table entry.
1213	*/
1214	typedef struct X86PTEBITS
1215	{
1216	/** Flags whether(=1) or not the page is present. */
1217	unsigned u1Present : 1;
1218	/** Read(=0) / Write(=1) flag. */
1219	unsigned u1Write : 1;
1220	/** User(=1) / Supervisor (=0) flag. */
1221	unsigned u1User : 1;
1222	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1223	unsigned u1WriteThru : 1;
1224	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1225	unsigned u1CacheDisable : 1;
1226	/** Accessed flag.
1227	* Indicates that the page have been read or written to. */
1228	unsigned u1Accessed : 1;
1229	/** Dirty flag.
1230	* Indicates that the page has been written to. */
1231	unsigned u1Dirty : 1;
1232	/** Reserved / If PAT enabled, bit 2 of the index. */
1233	unsigned u1PAT : 1;
1234	/** Global flag. (Ignored in all but final level.) */
1235	unsigned u1Global : 1;
1236	/** Available for use to system software. */
1237	unsigned u3Available : 3;
1238	/** Physical Page number of the next level. */
1239	unsigned u20PageNo : 20;
1240	} X86PTEBITS;
1241	/** Pointer to a page table entry. */
1242	typedef X86PTEBITS *PX86PTEBITS;
1243	/** Pointer to a const page table entry. */
1244	typedef const X86PTEBITS *PCX86PTEBITS;
1245
1246	/**
1247	* Page table entry.
1248	*/
1249	typedef union X86PTE
1250	{
1251	/** Unsigned integer view */
1252	X86PGUINT u;
1253	/** Bit field view. */
1254	X86PTEBITS n;
1255	/** 32-bit view. */
1256	uint32_t au32[1];
1257	/** 16-bit view. */
1258	uint16_t au16[2];
1259	/** 8-bit view. */
1260	uint8_t au8[4];
1261	} X86PTE;
1262	/** Pointer to a page table entry. */
1263	typedef X86PTE *PX86PTE;
1264	/** Pointer to a const page table entry. */
1265	typedef const X86PTE *PCX86PTE;
1266
1267
1268	/**
1269	* PAE page table entry.
1270	*/
1271	typedef struct X86PTEPAEBITS
1272	{
1273	/** Flags whether(=1) or not the page is present. */
1274	uint32_t u1Present : 1;
1275	/** Read(=0) / Write(=1) flag. */
1276	uint32_t u1Write : 1;
1277	/** User(=1) / Supervisor(=0) flag. */
1278	uint32_t u1User : 1;
1279	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1280	uint32_t u1WriteThru : 1;
1281	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1282	uint32_t u1CacheDisable : 1;
1283	/** Accessed flag.
1284	* Indicates that the page have been read or written to. */
1285	uint32_t u1Accessed : 1;
1286	/** Dirty flag.
1287	* Indicates that the page has been written to. */
1288	uint32_t u1Dirty : 1;
1289	/** Reserved / If PAT enabled, bit 2 of the index. */
1290	uint32_t u1PAT : 1;
1291	/** Global flag. (Ignored in all but final level.) */
1292	uint32_t u1Global : 1;
1293	/** Available for use to system software. */
1294	uint32_t u3Available : 3;
1295	/** Physical Page number of the next level - Low Part. Don't use this. */
1296	uint32_t u20PageNoLow : 20;
1297	/** Physical Page number of the next level - High Part. Don't use this. */
1298	uint32_t u20PageNoHigh : 20;
1299	/** MBZ bits */
1300	uint32_t u11Reserved : 11;
1301	/** No Execute flag. */
1302	uint32_t u1NoExecute : 1;
1303	} X86PTEPAEBITS;
1304	/** Pointer to a page table entry. */
1305	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1306	/** Pointer to a page table entry. */
1307	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1308
1309	/**
1310	* PAE Page table entry.
1311	*/
1312	typedef union X86PTEPAE
1313	{
1314	/** Unsigned integer view */
1315	X86PGPAEUINT u;
1316	/** Bit field view. */
1317	X86PTEPAEBITS n;
1318	/** 32-bit view. */
1319	uint32_t au32[2];
1320	/** 16-bit view. */
1321	uint16_t au16[4];
1322	/** 8-bit view. */
1323	uint8_t au8[8];
1324	} X86PTEPAE;
1325	/** Pointer to a PAE page table entry. */
1326	typedef X86PTEPAE *PX86PTEPAE;
1327	/** Pointer to a const PAE page table entry. */
1328	typedef const X86PTEPAE *PCX86PTEPAE;
1329	/** @} */
1330
1331	/**
1332	* Page table.
1333	*/
1334	typedef struct X86PT
1335	{
1336	/** PTE Array. */
1337	X86PTE a[X86_PG_ENTRIES];
1338	} X86PT;
1339	/** Pointer to a page table. */
1340	typedef X86PT *PX86PT;
1341	/** Pointer to a const page table. */
1342	typedef const X86PT *PCX86PT;
1343
1344	/** The page shift to get the PT index. */
1345	#define X86_PT_SHIFT 12
1346	/** The PT index mask (apply to a shifted page address). */
1347	#define X86_PT_MASK 0x3ff
1348
1349
1350	/**
1351	* Page directory.
1352	*/
1353	typedef struct X86PTPAE
1354	{
1355	/** PTE Array. */
1356	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1357	} X86PTPAE;
1358	/** Pointer to a page table. */
1359	typedef X86PTPAE *PX86PTPAE;
1360	/** Pointer to a const page table. */
1361	typedef const X86PTPAE *PCX86PTPAE;
1362
1363	/** The page shift to get the PA PTE index. */
1364	#define X86_PT_PAE_SHIFT 12
1365	/** The PAE PT index mask (apply to a shifted page address). */
1366	#define X86_PT_PAE_MASK 0x1ff
1367
1368
1369	/** @name 4KB Page Directory Entry
1370	* @{
1371	*/
1372	/** Bit 0 - P - Present bit. */
1373	#define X86_PDE_P RT_BIT(0)
1374	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1375	#define X86_PDE_RW RT_BIT(1)
1376	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1377	#define X86_PDE_US RT_BIT(2)
1378	/** Bit 3 - PWT - Page level write thru bit. */
1379	#define X86_PDE_PWT RT_BIT(3)
1380	/** Bit 4 - PCD - Page level cache disable bit. */
1381	#define X86_PDE_PCD RT_BIT(4)
1382	/** Bit 5 - A - Access bit. */
1383	#define X86_PDE_A RT_BIT(5)
1384	/** Bit 7 - PS - Page size attribute.
1385	* Clear mean 4KB pages, set means large pages (2/4MB). */
1386	#define X86_PDE_PS RT_BIT(7)
1387	/** Bits 9-11 - - Available for use to system software. */
1388	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1389	/** Bits 12-31 - - Physical Page number of the next level. */
1390	#define X86_PDE_PG_MASK ( 0xfffff000 )
1391
1392	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1393	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1394	/** Bits 63 - NX - PAE/LM - No execution flag. */
1395	#define X86_PDE_PAE_NX RT_BIT_64(63)
1396	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1397	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1398	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1399	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1400	/** Bit 7 - - LM - MBZ bits when NX is active. */
1401	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1402	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1403	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1404
1405	/**
1406	* Page directory entry.
1407	*/
1408	typedef struct X86PDEBITS
1409	{
1410	/** Flags whether(=1) or not the page is present. */
1411	unsigned u1Present : 1;
1412	/** Read(=0) / Write(=1) flag. */
1413	unsigned u1Write : 1;
1414	/** User(=1) / Supervisor (=0) flag. */
1415	unsigned u1User : 1;
1416	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1417	unsigned u1WriteThru : 1;
1418	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1419	unsigned u1CacheDisable : 1;
1420	/** Accessed flag.
1421	* Indicates that the page has been read or written to. */
1422	unsigned u1Accessed : 1;
1423	/** Reserved / Ignored (dirty bit). */
1424	unsigned u1Reserved0 : 1;
1425	/** Size bit if PSE is enabled - in any event it's 0. */
1426	unsigned u1Size : 1;
1427	/** Reserved / Ignored (global bit). */
1428	unsigned u1Reserved1 : 1;
1429	/** Available for use to system software. */
1430	unsigned u3Available : 3;
1431	/** Physical Page number of the next level. */
1432	unsigned u20PageNo : 20;
1433	} X86PDEBITS;
1434	/** Pointer to a page directory entry. */
1435	typedef X86PDEBITS *PX86PDEBITS;
1436	/** Pointer to a const page directory entry. */
1437	typedef const X86PDEBITS *PCX86PDEBITS;
1438
1439
1440	/**
1441	* PAE page directory entry.
1442	*/
1443	typedef struct X86PDEPAEBITS
1444	{
1445	/** Flags whether(=1) or not the page is present. */
1446	uint32_t u1Present : 1;
1447	/** Read(=0) / Write(=1) flag. */
1448	uint32_t u1Write : 1;
1449	/** User(=1) / Supervisor (=0) flag. */
1450	uint32_t u1User : 1;
1451	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1452	uint32_t u1WriteThru : 1;
1453	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1454	uint32_t u1CacheDisable : 1;
1455	/** Accessed flag.
1456	* Indicates that the page has been read or written to. */
1457	uint32_t u1Accessed : 1;
1458	/** Reserved / Ignored (dirty bit). */
1459	uint32_t u1Reserved0 : 1;
1460	/** Size bit if PSE is enabled - in any event it's 0. */
1461	uint32_t u1Size : 1;
1462	/** Reserved / Ignored (global bit). / */
1463	uint32_t u1Reserved1 : 1;
1464	/** Available for use to system software. */
1465	uint32_t u3Available : 3;
1466	/** Physical Page number of the next level - Low Part. Don't use! */
1467	uint32_t u20PageNoLow : 20;
1468	/** Physical Page number of the next level - High Part. Don't use! */
1469	uint32_t u20PageNoHigh : 20;
1470	/** MBZ bits */
1471	uint32_t u11Reserved : 11;
1472	/** No Execute flag. */
1473	uint32_t u1NoExecute : 1;
1474	} X86PDEPAEBITS;
1475	/** Pointer to a page directory entry. */
1476	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1477	/** Pointer to a const page directory entry. */
1478	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1479
1480	/** @} */
1481
1482
1483	/** @name 2/4MB Page Directory Entry
1484	* @{
1485	*/
1486	/** Bit 0 - P - Present bit. */
1487	#define X86_PDE4M_P RT_BIT(0)
1488	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1489	#define X86_PDE4M_RW RT_BIT(1)
1490	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1491	#define X86_PDE4M_US RT_BIT(2)
1492	/** Bit 3 - PWT - Page level write thru bit. */
1493	#define X86_PDE4M_PWT RT_BIT(3)
1494	/** Bit 4 - PCD - Page level cache disable bit. */
1495	#define X86_PDE4M_PCD RT_BIT(4)
1496	/** Bit 5 - A - Access bit. */
1497	#define X86_PDE4M_A RT_BIT(5)
1498	/** Bit 6 - D - Dirty bit. */
1499	#define X86_PDE4M_D RT_BIT(6)
1500	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1501	#define X86_PDE4M_PS RT_BIT(7)
1502	/** Bit 8 - G - Global flag. */
1503	#define X86_PDE4M_G RT_BIT(8)
1504	/** Bits 9-11 - AVL - Available for use to system software. */
1505	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1506	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1507	#define X86_PDE4M_PAT RT_BIT(12)
1508	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1509	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1510	/** Bits 22-31 - - Physical Page number. */
1511	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1512	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1513	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1514	/** The number of bits to the high part of the page number. */
1515	#define X86_PDE4M_PG_HIGH_SHIFT 19
1516	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1517	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1518
1519	/** Bits 21-51 - - PAE/LM - Physical Page number.
1520	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1521	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1522	/** Bits 63 - NX - PAE/LM - No execution flag. */
1523	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1524	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1525	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1526	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1527	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1528	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1529	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1530	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1531	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1532
1533	/**
1534	* 4MB page directory entry.
1535	*/
1536	typedef struct X86PDE4MBITS
1537	{
1538	/** Flags whether(=1) or not the page is present. */
1539	unsigned u1Present : 1;
1540	/** Read(=0) / Write(=1) flag. */
1541	unsigned u1Write : 1;
1542	/** User(=1) / Supervisor (=0) flag. */
1543	unsigned u1User : 1;
1544	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1545	unsigned u1WriteThru : 1;
1546	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1547	unsigned u1CacheDisable : 1;
1548	/** Accessed flag.
1549	* Indicates that the page have been read or written to. */
1550	unsigned u1Accessed : 1;
1551	/** Dirty flag.
1552	* Indicates that the page has been written to. */
1553	unsigned u1Dirty : 1;
1554	/** Page size flag - always 1 for 4MB entries. */
1555	unsigned u1Size : 1;
1556	/** Global flag. */
1557	unsigned u1Global : 1;
1558	/** Available for use to system software. */
1559	unsigned u3Available : 3;
1560	/** Reserved / If PAT enabled, bit 2 of the index. */
1561	unsigned u1PAT : 1;
1562	/** Bits 32-39 of the page number on AMD64.
1563	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1564	unsigned u8PageNoHigh : 8;
1565	/** Reserved. */
1566	unsigned u1Reserved : 1;
1567	/** Physical Page number of the page. */
1568	unsigned u10PageNo : 10;
1569	} X86PDE4MBITS;
1570	/** Pointer to a page table entry. */
1571	typedef X86PDE4MBITS *PX86PDE4MBITS;
1572	/** Pointer to a const page table entry. */
1573	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1574
1575
1576	/**
1577	* 2MB PAE page directory entry.
1578	*/
1579	typedef struct X86PDE2MPAEBITS
1580	{
1581	/** Flags whether(=1) or not the page is present. */
1582	uint32_t u1Present : 1;
1583	/** Read(=0) / Write(=1) flag. */
1584	uint32_t u1Write : 1;
1585	/** User(=1) / Supervisor(=0) flag. */
1586	uint32_t u1User : 1;
1587	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1588	uint32_t u1WriteThru : 1;
1589	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1590	uint32_t u1CacheDisable : 1;
1591	/** Accessed flag.
1592	* Indicates that the page have been read or written to. */
1593	uint32_t u1Accessed : 1;
1594	/** Dirty flag.
1595	* Indicates that the page has been written to. */
1596	uint32_t u1Dirty : 1;
1597	/** Page size flag - always 1 for 2MB entries. */
1598	uint32_t u1Size : 1;
1599	/** Global flag. */
1600	uint32_t u1Global : 1;
1601	/** Available for use to system software. */
1602	uint32_t u3Available : 3;
1603	/** Reserved / If PAT enabled, bit 2 of the index. */
1604	uint32_t u1PAT : 1;
1605	/** Reserved. */
1606	uint32_t u9Reserved : 9;
1607	/** Physical Page number of the next level - Low part. Don't use! */
1608	uint32_t u10PageNoLow : 10;
1609	/** Physical Page number of the next level - High part. Don't use! */
1610	uint32_t u20PageNoHigh : 20;
1611	/** MBZ bits */
1612	uint32_t u11Reserved : 11;
1613	/** No Execute flag. */
1614	uint32_t u1NoExecute : 1;
1615	} X86PDE2MPAEBITS;
1616	/** Pointer to a 2MB PAE page table entry. */
1617	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1618	/** Pointer to a 2MB PAE page table entry. */
1619	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1620
1621	/** @} */
1622
1623	/**
1624	* Page directory entry.
1625	*/
1626	typedef union X86PDE
1627	{
1628	/** Unsigned integer view. */
1629	X86PGUINT u;
1630	/** Normal view. */
1631	X86PDEBITS n;
1632	/** 4MB view (big). */
1633	X86PDE4MBITS b;
1634	/** 8 bit unsigned integer view. */
1635	uint8_t au8[4];
1636	/** 16 bit unsigned integer view. */
1637	uint16_t au16[2];
1638	/** 32 bit unsigned integer view. */
1639	uint32_t au32[1];
1640	} X86PDE;
1641	/** Pointer to a page directory entry. */
1642	typedef X86PDE *PX86PDE;
1643	/** Pointer to a const page directory entry. */
1644	typedef const X86PDE *PCX86PDE;
1645
1646	/**
1647	* PAE page directory entry.
1648	*/
1649	typedef union X86PDEPAE
1650	{
1651	/** Unsigned integer view. */
1652	X86PGPAEUINT u;
1653	/** Normal view. */
1654	X86PDEPAEBITS n;
1655	/** 2MB page view (big). */
1656	X86PDE2MPAEBITS b;
1657	/** 8 bit unsigned integer view. */
1658	uint8_t au8[8];
1659	/** 16 bit unsigned integer view. */
1660	uint16_t au16[4];
1661	/** 32 bit unsigned integer view. */
1662	uint32_t au32[2];
1663	} X86PDEPAE;
1664	/** Pointer to a page directory entry. */
1665	typedef X86PDEPAE *PX86PDEPAE;
1666	/** Pointer to a const page directory entry. */
1667	typedef const X86PDEPAE *PCX86PDEPAE;
1668
1669	/**
1670	* Page directory.
1671	*/
1672	typedef struct X86PD
1673	{
1674	/** PDE Array. */
1675	X86PDE a[X86_PG_ENTRIES];
1676	} X86PD;
1677	/** Pointer to a page directory. */
1678	typedef X86PD *PX86PD;
1679	/** Pointer to a const page directory. */
1680	typedef const X86PD *PCX86PD;
1681
1682	/** The page shift to get the PD index. */
1683	#define X86_PD_SHIFT 22
1684	/** The PD index mask (apply to a shifted page address). */
1685	#define X86_PD_MASK 0x3ff
1686
1687
1688	/**
1689	* PAE page directory.
1690	*/
1691	typedef struct X86PDPAE
1692	{
1693	/** PDE Array. */
1694	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1695	} X86PDPAE;
1696	/** Pointer to a PAE page directory. */
1697	typedef X86PDPAE *PX86PDPAE;
1698	/** Pointer to a const PAE page directory. */
1699	typedef const X86PDPAE *PCX86PDPAE;
1700
1701	/** The page shift to get the PAE PD index. */
1702	#define X86_PD_PAE_SHIFT 21
1703	/** The PAE PD index mask (apply to a shifted page address). */
1704	#define X86_PD_PAE_MASK 0x1ff
1705
1706
1707	/** @name Page Directory Pointer Table Entry (PAE)
1708	* @{
1709	*/
1710	/** Bit 0 - P - Present bit. */
1711	#define X86_PDPE_P RT_BIT(0)
1712	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1713	#define X86_PDPE_RW RT_BIT(1)
1714	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1715	#define X86_PDPE_US RT_BIT(2)
1716	/** Bit 3 - PWT - Page level write thru bit. */
1717	#define X86_PDPE_PWT RT_BIT(3)
1718	/** Bit 4 - PCD - Page level cache disable bit. */
1719	#define X86_PDPE_PCD RT_BIT(4)
1720	/** Bit 5 - A - Access bit. Long Mode only. */
1721	#define X86_PDPE_A RT_BIT(5)
1722	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1723	#define X86_PDPE_LM_PS RT_BIT(7)
1724	/** Bits 9-11 - - Available for use to system software. */
1725	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1726	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1727	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1728	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1729	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1730	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1731	#define X86_PDPE_LM_NX RT_BIT_64(63)
1732	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1733	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1734	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1735	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1736	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1737	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1738	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1739	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1740
1741
1742	/**
1743	* Page directory pointer table entry.
1744	*/
1745	typedef struct X86PDPEBITS
1746	{
1747	/** Flags whether(=1) or not the page is present. */
1748	uint32_t u1Present : 1;
1749	/** Chunk of reserved bits. */
1750	uint32_t u2Reserved : 2;
1751	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1752	uint32_t u1WriteThru : 1;
1753	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1754	uint32_t u1CacheDisable : 1;
1755	/** Chunk of reserved bits. */
1756	uint32_t u4Reserved : 4;
1757	/** Available for use to system software. */
1758	uint32_t u3Available : 3;
1759	/** Physical Page number of the next level - Low Part. Don't use! */
1760	uint32_t u20PageNoLow : 20;
1761	/** Physical Page number of the next level - High Part. Don't use! */
1762	uint32_t u20PageNoHigh : 20;
1763	/** MBZ bits */
1764	uint32_t u12Reserved : 12;
1765	} X86PDPEBITS;
1766	/** Pointer to a page directory pointer table entry. */
1767	typedef X86PDPEBITS *PX86PTPEBITS;
1768	/** Pointer to a const page directory pointer table entry. */
1769	typedef const X86PDPEBITS *PCX86PTPEBITS;
1770
1771	/**
1772	* Page directory pointer table entry. AMD64 version
1773	*/
1774	typedef struct X86PDPEAMD64BITS
1775	{
1776	/** Flags whether(=1) or not the page is present. */
1777	uint32_t u1Present : 1;
1778	/** Read(=0) / Write(=1) flag. */
1779	uint32_t u1Write : 1;
1780	/** User(=1) / Supervisor (=0) flag. */
1781	uint32_t u1User : 1;
1782	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1783	uint32_t u1WriteThru : 1;
1784	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1785	uint32_t u1CacheDisable : 1;
1786	/** Accessed flag.
1787	* Indicates that the page have been read or written to. */
1788	uint32_t u1Accessed : 1;
1789	/** Chunk of reserved bits. */
1790	uint32_t u3Reserved : 3;
1791	/** Available for use to system software. */
1792	uint32_t u3Available : 3;
1793	/** Physical Page number of the next level - Low Part. Don't use! */
1794	uint32_t u20PageNoLow : 20;
1795	/** Physical Page number of the next level - High Part. Don't use! */
1796	uint32_t u20PageNoHigh : 20;
1797	/** MBZ bits */
1798	uint32_t u11Reserved : 11;
1799	/** No Execute flag. */
1800	uint32_t u1NoExecute : 1;
1801	} X86PDPEAMD64BITS;
1802	/** Pointer to a page directory pointer table entry. */
1803	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1804	/** Pointer to a const page directory pointer table entry. */
1805	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1806
1807	/**
1808	* Page directory pointer table entry.
1809	*/
1810	typedef union X86PDPE
1811	{
1812	/** Unsigned integer view. */
1813	X86PGPAEUINT u;
1814	/** Normal view. */
1815	X86PDPEBITS n;
1816	/** AMD64 view. */
1817	X86PDPEAMD64BITS lm;
1818	/** 8 bit unsigned integer view. */
1819	uint8_t au8[8];
1820	/** 16 bit unsigned integer view. */
1821	uint16_t au16[4];
1822	/** 32 bit unsigned integer view. */
1823	uint32_t au32[2];
1824	} X86PDPE;
1825	/** Pointer to a page directory pointer table entry. */
1826	typedef X86PDPE *PX86PDPE;
1827	/** Pointer to a const page directory pointer table entry. */
1828	typedef const X86PDPE *PCX86PDPE;
1829
1830
1831	/**
1832	* Page directory pointer table.
1833	*/
1834	typedef struct X86PDPT
1835	{
1836	/** PDE Array. */
1837	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1838	} X86PDPT;
1839	/** Pointer to a page directory pointer table. */
1840	typedef X86PDPT *PX86PDPT;
1841	/** Pointer to a const page directory pointer table. */
1842	typedef const X86PDPT *PCX86PDPT;
1843
1844	/** The page shift to get the PDPT index. */
1845	#define X86_PDPT_SHIFT 30
1846	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1847	#define X86_PDPT_MASK_PAE 0x3
1848	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1849	#define X86_PDPT_MASK_AMD64 0x1ff
1850
1851	/** @} */
1852
1853
1854	/** @name Page Map Level-4 Entry (Long Mode PAE)
1855	* @{
1856	*/
1857	/** Bit 0 - P - Present bit. */
1858	#define X86_PML4E_P RT_BIT(0)
1859	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1860	#define X86_PML4E_RW RT_BIT(1)
1861	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1862	#define X86_PML4E_US RT_BIT(2)
1863	/** Bit 3 - PWT - Page level write thru bit. */
1864	#define X86_PML4E_PWT RT_BIT(3)
1865	/** Bit 4 - PCD - Page level cache disable bit. */
1866	#define X86_PML4E_PCD RT_BIT(4)
1867	/** Bit 5 - A - Access bit. */
1868	#define X86_PML4E_A RT_BIT(5)
1869	/** Bits 9-11 - - Available for use to system software. */
1870	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1871	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1872	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1873	/** Bits 8, 7 - - MBZ bits when NX is active. */
1874	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1875	/** Bits 63, 7 - - MBZ bits when no NX. */
1876	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1877	/** Bits 63 - NX - PAE - No execution flag. */
1878	#define X86_PML4E_NX RT_BIT_64(63)
1879
1880	/**
1881	* Page Map Level-4 Entry
1882	*/
1883	typedef struct X86PML4EBITS
1884	{
1885	/** Flags whether(=1) or not the page is present. */
1886	uint32_t u1Present : 1;
1887	/** Read(=0) / Write(=1) flag. */
1888	uint32_t u1Write : 1;
1889	/** User(=1) / Supervisor (=0) flag. */
1890	uint32_t u1User : 1;
1891	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1892	uint32_t u1WriteThru : 1;
1893	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1894	uint32_t u1CacheDisable : 1;
1895	/** Accessed flag.
1896	* Indicates that the page have been read or written to. */
1897	uint32_t u1Accessed : 1;
1898	/** Chunk of reserved bits. */
1899	uint32_t u3Reserved : 3;
1900	/** Available for use to system software. */
1901	uint32_t u3Available : 3;
1902	/** Physical Page number of the next level - Low Part. Don't use! */
1903	uint32_t u20PageNoLow : 20;
1904	/** Physical Page number of the next level - High Part. Don't use! */
1905	uint32_t u20PageNoHigh : 20;
1906	/** MBZ bits */
1907	uint32_t u11Reserved : 11;
1908	/** No Execute flag. */
1909	uint32_t u1NoExecute : 1;
1910	} X86PML4EBITS;
1911	/** Pointer to a page map level-4 entry. */
1912	typedef X86PML4EBITS *PX86PML4EBITS;
1913	/** Pointer to a const page map level-4 entry. */
1914	typedef const X86PML4EBITS *PCX86PML4EBITS;
1915
1916	/**
1917	* Page Map Level-4 Entry.
1918	*/
1919	typedef union X86PML4E
1920	{
1921	/** Unsigned integer view. */
1922	X86PGPAEUINT u;
1923	/** Normal view. */
1924	X86PML4EBITS n;
1925	/** 8 bit unsigned integer view. */
1926	uint8_t au8[8];
1927	/** 16 bit unsigned integer view. */
1928	uint16_t au16[4];
1929	/** 32 bit unsigned integer view. */
1930	uint32_t au32[2];
1931	} X86PML4E;
1932	/** Pointer to a page map level-4 entry. */
1933	typedef X86PML4E *PX86PML4E;
1934	/** Pointer to a const page map level-4 entry. */
1935	typedef const X86PML4E *PCX86PML4E;
1936
1937
1938	/**
1939	* Page Map Level-4.
1940	*/
1941	typedef struct X86PML4
1942	{
1943	/** PDE Array. */
1944	X86PML4E a[X86_PG_PAE_ENTRIES];
1945	} X86PML4;
1946	/** Pointer to a page map level-4. */
1947	typedef X86PML4 *PX86PML4;
1948	/** Pointer to a const page map level-4. */
1949	typedef const X86PML4 *PCX86PML4;
1950
1951	/** The page shift to get the PML4 index. */
1952	#define X86_PML4_SHIFT 39
1953	/** The PML4 index mask (apply to a shifted page address). */
1954	#define X86_PML4_MASK 0x1ff
1955
1956	/** @} */
1957
1958	/** @} */
1959
1960
1961	/**
1962	* 80-bit MMX/FPU register type.
1963	*/
1964	typedef struct X86FPUMMX
1965	{
1966	uint8_t reg[10];
1967	} X86FPUMMX;
1968	/** Pointer to a 80-bit MMX/FPU register type. */
1969	typedef X86FPUMMX *PX86FPUMMX;
1970	/** Pointer to a const 80-bit MMX/FPU register type. */
1971	typedef const X86FPUMMX *PCX86FPUMMX;
1972
1973	/**
1974	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
1975	* @todo verify this...
1976	*/
1977	#pragma pack(1)
1978	typedef struct X86FPUSTATE
1979	{
1980	/** 0x00 - Control word. */
1981	uint16_t FCW;
1982	/** 0x02 - Alignment word */
1983	uint16_t Dummy1;
1984	/** 0x04 - Status word. */
1985	uint16_t FSW;
1986	/** 0x06 - Alignment word */
1987	uint16_t Dummy2;
1988	/** 0x08 - Tag word */
1989	uint16_t FTW;
1990	/** 0x0a - Alignment word */
1991	uint16_t Dummy3;
1992
1993	/** 0x0c - Instruction pointer. */
1994	uint32_t FPUIP;
1995	/** 0x10 - Code selector. */
1996	uint16_t CS;
1997	/** 0x12 - Opcode. */
1998	uint16_t FOP;
1999	/** 0x14 - FOO. */
2000	uint32_t FPUOO;
2001	/** 0x18 - FOS. */
2002	uint32_t FPUOS;
2003	/** 0x1c */
2004	union
2005	{
2006	/** MMX view. */
2007	uint64_t mmx;
2008	/** FPU view - todo. */
2009	X86FPUMMX fpu;
2010	/** Extended precision floating point view. */
2011	RTFLOAT80U r80;
2012	/** Extended precision floating point view v2. */
2013	RTFLOAT80U2 r80Ex;
2014	/** 8-bit view. */
2015	uint8_t au8[16];
2016	/** 16-bit view. */
2017	uint16_t au16[8];
2018	/** 32-bit view. */
2019	uint32_t au32[4];
2020	/** 64-bit view. */
2021	uint64_t au64[2];
2022	/** 128-bit view. (yeah, very helpful) */
2023	uint128_t au128[1];
2024	} regs[8];
2025	} X86FPUSTATE;
2026	#pragma pack()
2027	/** Pointer to a FPU state. */
2028	typedef X86FPUSTATE *PX86FPUSTATE;
2029	/** Pointer to a const FPU state. */
2030	typedef const X86FPUSTATE *PCX86FPUSTATE;
2031
2032	/**
2033	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2034	*/
2035	#pragma pack(1)
2036	typedef struct X86FXSTATE
2037	{
2038	/** 0x00 - Control word. */
2039	uint16_t FCW;
2040	/** 0x02 - Status word. */
2041	uint16_t FSW;
2042	/** 0x04 - Tag word. (The upper byte is always zero.) */
2043	uint16_t FTW;
2044	/** 0x06 - Opcode. */
2045	uint16_t FOP;
2046	/** 0x08 - Instruction pointer. */
2047	uint32_t FPUIP;
2048	/** 0x0c - Code selector. */
2049	uint16_t CS;
2050	uint16_t Rsrvd1;
2051	/** 0x10 - Data pointer. */
2052	uint32_t FPUDP;
2053	/** 0x14 - Data segment */
2054	uint16_t DS;
2055	/** 0x16 */
2056	uint16_t Rsrvd2;
2057	/** 0x18 */
2058	uint32_t MXCSR;
2059	/** 0x1c */
2060	uint32_t MXCSR_MASK;
2061	/** 0x20 */
2062	union
2063	{
2064	/** MMX view. */
2065	uint64_t mmx;
2066	/** FPU view - todo. */
2067	X86FPUMMX fpu;
2068	/** Extended precision floating point view. */
2069	RTFLOAT80U r80;
2070	/** Extended precision floating point view v2 */
2071	RTFLOAT80U2 r80Ex;
2072	/** 8-bit view. */
2073	uint8_t au8[16];
2074	/** 16-bit view. */
2075	uint16_t au16[8];
2076	/** 32-bit view. */
2077	uint32_t au32[4];
2078	/** 64-bit view. */
2079	uint64_t au64[2];
2080	/** 128-bit view. (yeah, very helpful) */
2081	uint128_t au128[1];
2082	} aRegs[8];
2083	/* - offset 160 - */
2084	union
2085	{
2086	/** XMM Register view . /
2087	uint128_t xmm;
2088	/** 8-bit view. */
2089	uint8_t au8[16];
2090	/** 16-bit view. */
2091	uint16_t au16[8];
2092	/** 32-bit view. */
2093	uint32_t au32[4];
2094	/** 64-bit view. */
2095	uint64_t au64[2];
2096	/** 128-bit view. (yeah, very helpful) */
2097	uint128_t au128[1];
2098	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2099	/* - offset 416 - */
2100	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2101	} X86FXSTATE;
2102	#pragma pack()
2103	/** Pointer to a FPU Extended state. */
2104	typedef X86FXSTATE *PX86FXSTATE;
2105	/** Pointer to a const FPU Extended state. */
2106	typedef const X86FXSTATE *PCX86FXSTATE;
2107
2108	/** @name FPU status word flags.
2109	* @{ */
2110	/** Exception Flag: Invalid operation. */
2111	#define X86_FSW_IE RT_BIT(0)
2112	/** Exception Flag: Denormalized operand. */
2113	#define X86_FSW_DE RT_BIT(1)
2114	/** Exception Flag: Zero divide. */
2115	#define X86_FSW_ZE RT_BIT(2)
2116	/** Exception Flag: Overflow. */
2117	#define X86_FSW_OE RT_BIT(3)
2118	/** Exception Flag: Underflow. */
2119	#define X86_FSW_UE RT_BIT(4)
2120	/** Exception Flag: Precision. */
2121	#define X86_FSW_PE RT_BIT(5)
2122	/** Stack fault. */
2123	#define X86_FSW_SF RT_BIT(6)
2124	/** Error summary status. */
2125	#define X86_FSW_ES RT_BIT(7)
2126	/** Mask of exceptions flags, excluding the summary bit. */
2127	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2128	/** Mask of exceptions flags, including the summary bit. */
2129	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2130	/** Condition code 0. */
2131	#define X86_FSW_C0 RT_BIT(8)
2132	/** Condition code 1. */
2133	#define X86_FSW_C1 RT_BIT(9)
2134	/** Condition code 2. */
2135	#define X86_FSW_C2 RT_BIT(10)
2136	/** Top of the stack mask. */
2137	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2138	/** TOP shift value. */
2139	#define X86_FSW_TOP_SHIFT 11
2140	/** Mask for getting TOP value after shifting it right. */
2141	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2142	/** Get the TOP value. */
2143	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2144	/** Condition code 3. */
2145	#define X86_FSW_C3 RT_BIT(14)
2146	/** Mask of exceptions flags, including the summary bit. */
2147	#define X86_FSW_C_MASK UINT16_C(0x4700)
2148	/** FPU busy. */
2149	#define X86_FSW_B RT_BIT(15)
2150	/** @} */
2151
2152
2153	/** @name FPU control word flags.
2154	* @{ */
2155	/** Exception Mask: Invalid operation. */
2156	#define X86_FCW_IM RT_BIT(0)
2157	/** Exception Mask: Denormalized operand. */
2158	#define X86_FCW_DM RT_BIT(1)
2159	/** Exception Mask: Zero divide. */
2160	#define X86_FCW_ZM RT_BIT(2)
2161	/** Exception Mask: Overflow. */
2162	#define X86_FCW_OM RT_BIT(3)
2163	/** Exception Mask: Underflow. */
2164	#define X86_FCW_UM RT_BIT(4)
2165	/** Exception Mask: Precision. */
2166	#define X86_FCW_PM RT_BIT(5)
2167	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2168	* @remarks This includes reserved bit 6. */
2169	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2170	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2171	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2172	/** Precision control mask. */
2173	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2174	/** Precision control: 24-bit. */
2175	#define X86_FCW_PC_24 UINT16_C(0x0000)
2176	/** Precision control: Reserved. */
2177	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2178	/** Precision control: 53-bit. */
2179	#define X86_FCW_PC_53 UINT16_C(0x0200)
2180	/** Precision control: 64-bit. */
2181	#define X86_FCW_PC_64 UINT16_C(0x0300)
2182	/** Rounding control mask. */
2183	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2184	/** Rounding control: To nearest. */
2185	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2186	/** Rounding control: Down. */
2187	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2188	/** Rounding control: Up. */
2189	#define X86_FCW_RC_UP UINT16_C(0x0800)
2190	/** Rounding control: Towards zero. */
2191	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2192	/** Bits which should be zero, apparently. */
2193	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2194	/** @} */
2195
2196
2197	/** @name Selector Descriptor
2198	* @{
2199	*/
2200
2201	/**
2202	* Descriptor attributes.
2203	*/
2204	typedef struct X86DESCATTRBITS
2205	{
2206	/** 00 - Segment Type. */
2207	unsigned u4Type : 4;
2208	/** 04 - Descriptor Type. System(=0) or code/data selector */
2209	unsigned u1DescType : 1;
2210	/** 05 - Descriptor Privelege level. */
2211	unsigned u2Dpl : 2;
2212	/** 07 - Flags selector present(=1) or not. */
2213	unsigned u1Present : 1;
2214	/** 08 - Segment limit 16-19. */
2215	unsigned u4LimitHigh : 4;
2216	/** 0c - Available for system software. */
2217	unsigned u1Available : 1;
2218	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2219	unsigned u1Long : 1;
2220	/** 0e - This flags meaning depends on the segment type. Try make sense out
2221	* of the intel manual yourself. */
2222	unsigned u1DefBig : 1;
2223	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2224	* clear byte. */
2225	unsigned u1Granularity : 1;
2226	} X86DESCATTRBITS;
2227
2228
2229	#pragma pack(1)
2230	typedef union X86DESCATTR
2231	{
2232	/** Unsigned integer view. */
2233	uint32_t u;
2234	/** Normal view. */
2235	X86DESCATTRBITS n;
2236	} X86DESCATTR;
2237	#pragma pack()
2238	/** Pointer to descriptor attributes. */
2239	typedef X86DESCATTR *PX86DESCATTR;
2240	/** Pointer to const descriptor attributes. */
2241	typedef const X86DESCATTR *PCX86DESCATTR;
2242
2243
2244	/**
2245	* Generic descriptor table entry
2246	*/
2247	#pragma pack(1)
2248	typedef struct X86DESCGENERIC
2249	{
2250	/** Limit - Low word. */
2251	unsigned u16LimitLow : 16;
2252	/** Base address - lowe word.
2253	* Don't try set this to 24 because MSC is doing stupid things then. */
2254	unsigned u16BaseLow : 16;
2255	/** Base address - first 8 bits of high word. */
2256	unsigned u8BaseHigh1 : 8;
2257	/** Segment Type. */
2258	unsigned u4Type : 4;
2259	/** Descriptor Type. System(=0) or code/data selector */
2260	unsigned u1DescType : 1;
2261	/** Descriptor Privelege level. */
2262	unsigned u2Dpl : 2;
2263	/** Flags selector present(=1) or not. */
2264	unsigned u1Present : 1;
2265	/** Segment limit 16-19. */
2266	unsigned u4LimitHigh : 4;
2267	/** Available for system software. */
2268	unsigned u1Available : 1;
2269	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2270	unsigned u1Long : 1;
2271	/** This flags meaning depends on the segment type. Try make sense out
2272	* of the intel manual yourself. */
2273	unsigned u1DefBig : 1;
2274	/** Granularity of the limit. If set 4KB granularity is used, if
2275	* clear byte. */
2276	unsigned u1Granularity : 1;
2277	/** Base address - highest 8 bits. */
2278	unsigned u8BaseHigh2 : 8;
2279	} X86DESCGENERIC;
2280	#pragma pack()
2281	/** Pointer to a generic descriptor entry. */
2282	typedef X86DESCGENERIC *PX86DESCGENERIC;
2283	/** Pointer to a const generic descriptor entry. */
2284	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2285
2286	/**
2287	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2288	*/
2289	typedef struct X86DESCGATE
2290	{
2291	/** 00 - Target code segment offset - Low word.
2292	* Ignored if task-gate. */
2293	unsigned u16OffsetLow : 16;
2294	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2295	* TSS selector if task-gate. */
2296	unsigned u16Sel : 16;
2297	/** 20 - Number of parameters for a call-gate.
2298	* Ignored if interrupt-, trap- or task-gate. */
2299	unsigned u4ParmCount : 4;
2300	/** 24 - Reserved / ignored. */
2301	unsigned u4Reserved : 4;
2302	/** 28 - Segment Type. */
2303	unsigned u4Type : 4;
2304	/** 2c - Descriptor Type (0 = system). */
2305	unsigned u1DescType : 1;
2306	/** 2d - Descriptor Privelege level. */
2307	unsigned u2Dpl : 2;
2308	/** 2f - Flags selector present(=1) or not. */
2309	unsigned u1Present : 1;
2310	/** 30 - Target code segment offset - High word.
2311	* Ignored if task-gate. */
2312	unsigned u16OffsetHigh : 16;
2313	} X86DESCGATE;
2314	#ifndef VBOX_FOR_DTRACE_LIB
2315	AssertCompileSize(X86DESCGATE, 8);
2316	#endif
2317	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2318	typedef X86DESCGATE *PX86DESCGATE;
2319	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2320	typedef const X86DESCGATE *PCX86DESCGATE;
2321
2322	/**
2323	* Descriptor table entry.
2324	*/
2325	#pragma pack(1)
2326	typedef union X86DESC
2327	{
2328	/** Generic descriptor view. */
2329	X86DESCGENERIC Gen;
2330	/** Gate descriptor view. */
2331	X86DESCGATE Gate;
2332
2333	/** 8 bit unsigned integer view. */
2334	uint8_t au8[8];
2335	/** 16 bit unsigned integer view. */
2336	uint16_t au16[4];
2337	/** 32 bit unsigned integer view. */
2338	uint32_t au32[2];
2339	/** 64 bit unsigned integer view. */
2340	uint64_t au64[1];
2341	/** Unsigned integer view. */
2342	uint64_t u;
2343	} X86DESC;
2344	#ifndef VBOX_FOR_DTRACE_LIB
2345	AssertCompileSize(X86DESC, 8);
2346	#endif
2347	#pragma pack()
2348	/** Pointer to descriptor table entry. */
2349	typedef X86DESC *PX86DESC;
2350	/** Pointer to const descriptor table entry. */
2351	typedef const X86DESC *PCX86DESC;
2352
2353	/** @def X86DESC_BASE
2354	* Return the base address of a descriptor.
2355	*/
2356	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2357	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2358	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2359	\| ( (desc).Gen.u16BaseLow ) )
2360
2361	/** @def X86DESC_LIMIT
2362	* Return the limit of a descriptor.
2363	*/
2364	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2365	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2366	\| ( (desc).Gen.u16LimitLow ) )
2367
2368	/** @def X86DESC_GET_HID_ATTR
2369	* Get the descriptor attributes for the hidden register.
2370	*/
2371	#define X86DESC_GET_HID_ATTR(desc) /ASM-NOINC/ \
2372	( (desc.u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2373
2374
2375	/**
2376	* 64 bits generic descriptor table entry
2377	* Note: most of these bits have no meaning in long mode.
2378	*/
2379	#pragma pack(1)
2380	typedef struct X86DESC64GENERIC
2381	{
2382	/** Limit - Low word - IGNORED. */
2383	unsigned u16LimitLow : 16;
2384	/** Base address - low word. - IGNORED
2385	* Don't try set this to 24 because MSC is doing stupid things then. */
2386	unsigned u16BaseLow : 16;
2387	/** Base address - first 8 bits of high word. - IGNORED */
2388	unsigned u8BaseHigh1 : 8;
2389	/** Segment Type. */
2390	unsigned u4Type : 4;
2391	/** Descriptor Type. System(=0) or code/data selector */
2392	unsigned u1DescType : 1;
2393	/** Descriptor Privelege level. */
2394	unsigned u2Dpl : 2;
2395	/** Flags selector present(=1) or not. */
2396	unsigned u1Present : 1;
2397	/** Segment limit 16-19. - IGNORED */
2398	unsigned u4LimitHigh : 4;
2399	/** Available for system software. - IGNORED */
2400	unsigned u1Available : 1;
2401	/** Long mode flag. */
2402	unsigned u1Long : 1;
2403	/** This flags meaning depends on the segment type. Try make sense out
2404	* of the intel manual yourself. */
2405	unsigned u1DefBig : 1;
2406	/** Granularity of the limit. If set 4KB granularity is used, if
2407	* clear byte. - IGNORED */
2408	unsigned u1Granularity : 1;
2409	/** Base address - highest 8 bits. - IGNORED */
2410	unsigned u8BaseHigh2 : 8;
2411	/** Base address - bits 63-32. */
2412	unsigned u32BaseHigh3 : 32;
2413	unsigned u8Reserved : 8;
2414	unsigned u5Zeros : 5;
2415	unsigned u19Reserved : 19;
2416	} X86DESC64GENERIC;
2417	#pragma pack()
2418	/** Pointer to a generic descriptor entry. */
2419	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2420	/** Pointer to a const generic descriptor entry. */
2421	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2422
2423	/**
2424	* System descriptor table entry (64 bits)
2425	*
2426	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2427	*/
2428	#pragma pack(1)
2429	typedef struct X86DESC64SYSTEM
2430	{
2431	/** Limit - Low word. */
2432	unsigned u16LimitLow : 16;
2433	/** Base address - lowe word.
2434	* Don't try set this to 24 because MSC is doing stupid things then. */
2435	unsigned u16BaseLow : 16;
2436	/** Base address - first 8 bits of high word. */
2437	unsigned u8BaseHigh1 : 8;
2438	/** Segment Type. */
2439	unsigned u4Type : 4;
2440	/** Descriptor Type. System(=0) or code/data selector */
2441	unsigned u1DescType : 1;
2442	/** Descriptor Privelege level. */
2443	unsigned u2Dpl : 2;
2444	/** Flags selector present(=1) or not. */
2445	unsigned u1Present : 1;
2446	/** Segment limit 16-19. */
2447	unsigned u4LimitHigh : 4;
2448	/** Available for system software. */
2449	unsigned u1Available : 1;
2450	/** Reserved - 0. */
2451	unsigned u1Reserved : 1;
2452	/** This flags meaning depends on the segment type. Try make sense out
2453	* of the intel manual yourself. */
2454	unsigned u1DefBig : 1;
2455	/** Granularity of the limit. If set 4KB granularity is used, if
2456	* clear byte. */
2457	unsigned u1Granularity : 1;
2458	/** Base address - bits 31-24. */
2459	unsigned u8BaseHigh2 : 8;
2460	/** Base address - bits 63-32. */
2461	unsigned u32BaseHigh3 : 32;
2462	unsigned u8Reserved : 8;
2463	unsigned u5Zeros : 5;
2464	unsigned u19Reserved : 19;
2465	} X86DESC64SYSTEM;
2466	#pragma pack()
2467	/** Pointer to a system descriptor entry. */
2468	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2469	/** Pointer to a const system descriptor entry. */
2470	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2471
2472	/**
2473	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2474	*/
2475	typedef struct X86DESC64GATE
2476	{
2477	/** Target code segment offset - Low word. */
2478	unsigned u16OffsetLow : 16;
2479	/** Target code segment selector. */
2480	unsigned u16Sel : 16;
2481	/** Interrupt stack table for interrupt- and trap-gates.
2482	* Ignored by call-gates. */
2483	unsigned u3IST : 3;
2484	/** Reserved / ignored. */
2485	unsigned u5Reserved : 5;
2486	/** Segment Type. */
2487	unsigned u4Type : 4;
2488	/** Descriptor Type (0 = system). */
2489	unsigned u1DescType : 1;
2490	/** Descriptor Privelege level. */
2491	unsigned u2Dpl : 2;
2492	/** Flags selector present(=1) or not. */
2493	unsigned u1Present : 1;
2494	/** Target code segment offset - High word.
2495	* Ignored if task-gate. */
2496	unsigned u16OffsetHigh : 16;
2497	/** Target code segment offset - Top dword.
2498	* Ignored if task-gate. */
2499	unsigned u32OffsetTop : 32;
2500	/** Reserved / ignored / must be zero.
2501	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2502	unsigned u32Reserved : 32;
2503	} X86DESC64GATE;
2504	#ifndef VBOX_FOR_DTRACE_LIB
2505	AssertCompileSize(X86DESC64GATE, 16);
2506	#endif
2507	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2508	typedef X86DESC64GATE *PX86DESC64GATE;
2509	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2510	typedef const X86DESC64GATE *PCX86DESC64GATE;
2511
2512
2513	/**
2514	* Descriptor table entry.
2515	*/
2516	#pragma pack(1)
2517	typedef union X86DESC64
2518	{
2519	/** Generic descriptor view. */
2520	X86DESC64GENERIC Gen;
2521	/** System descriptor view. */
2522	X86DESC64SYSTEM System;
2523	/** Gate descriptor view. */
2524	X86DESC64GATE Gate;
2525
2526	/** 8 bit unsigned integer view. */
2527	uint8_t au8[16];
2528	/** 16 bit unsigned integer view. */
2529	uint16_t au16[8];
2530	/** 32 bit unsigned integer view. */
2531	uint32_t au32[4];
2532	/** 64 bit unsigned integer view. */
2533	uint64_t au64[2];
2534	} X86DESC64;
2535	#ifndef VBOX_FOR_DTRACE_LIB
2536	AssertCompileSize(X86DESC64, 16);
2537	#endif
2538	#pragma pack()
2539	/** Pointer to descriptor table entry. */
2540	typedef X86DESC64 *PX86DESC64;
2541	/** Pointer to const descriptor table entry. */
2542	typedef const X86DESC64 *PCX86DESC64;
2543
2544	/** @def X86DESC64_BASE
2545	* Return the base of a 64-bit descriptor.
2546	*/
2547	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2548	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2549	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2550	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2551	\| ( (desc).Gen.u16BaseLow ) )
2552
2553
2554
2555	/** @name Host system descriptor table entry - Use with care!
2556	* @{ */
2557	/** Host system descriptor table entry. */
2558	#if HC_ARCH_BITS == 64
2559	typedef X86DESC64 X86DESCHC;
2560	#else
2561	typedef X86DESC X86DESCHC;
2562	#endif
2563	/** Pointer to a host system descriptor table entry. */
2564	#if HC_ARCH_BITS == 64
2565	typedef PX86DESC64 PX86DESCHC;
2566	#else
2567	typedef PX86DESC PX86DESCHC;
2568	#endif
2569	/** Pointer to a const host system descriptor table entry. */
2570	#if HC_ARCH_BITS == 64
2571	typedef PCX86DESC64 PCX86DESCHC;
2572	#else
2573	typedef PCX86DESC PCX86DESCHC;
2574	#endif
2575	/** @} */
2576
2577
2578	/** @name Selector Descriptor Types.
2579	* @{
2580	*/
2581
2582	/** @name Non-System Selector Types.
2583	* @{ */
2584	/** Code(=set)/Data(=clear) bit. */
2585	#define X86_SEL_TYPE_CODE 8
2586	/** Memory(=set)/System(=clear) bit. */
2587	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2588	/** Accessed bit. */
2589	#define X86_SEL_TYPE_ACCESSED 1
2590	/** Expand down bit (for data selectors only). */
2591	#define X86_SEL_TYPE_DOWN 4
2592	/** Conforming bit (for code selectors only). */
2593	#define X86_SEL_TYPE_CONF 4
2594	/** Write bit (for data selectors only). */
2595	#define X86_SEL_TYPE_WRITE 2
2596	/** Read bit (for code selectors only). */
2597	#define X86_SEL_TYPE_READ 2
2598
2599	/** Read only selector type. */
2600	#define X86_SEL_TYPE_RO 0
2601	/** Accessed read only selector type. */
2602	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2603	/** Read write selector type. */
2604	#define X86_SEL_TYPE_RW 2
2605	/** Accessed read write selector type. */
2606	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2607	/** Expand down read only selector type. */
2608	#define X86_SEL_TYPE_RO_DOWN 4
2609	/** Accessed expand down read only selector type. */
2610	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2611	/** Expand down read write selector type. */
2612	#define X86_SEL_TYPE_RW_DOWN 6
2613	/** Accessed expand down read write selector type. */
2614	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2615	/** Execute only selector type. */
2616	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2617	/** Accessed execute only selector type. */
2618	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2619	/** Execute and read selector type. */
2620	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2621	/** Accessed execute and read selector type. */
2622	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2623	/** Conforming execute only selector type. */
2624	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2625	/** Accessed Conforming execute only selector type. */
2626	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2627	/** Conforming execute and write selector type. */
2628	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2629	/** Accessed Conforming execute and write selector type. */
2630	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2631	/** @} */
2632
2633
2634	/** @name System Selector Types.
2635	* @{ */
2636	/** The TSS busy bit mask. */
2637	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2638
2639	/** Undefined system selector type. */
2640	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2641	/** 286 TSS selector. */
2642	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2643	/** LDT selector. */
2644	#define X86_SEL_TYPE_SYS_LDT 2
2645	/** 286 TSS selector - Busy. */
2646	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2647	/** 286 Callgate selector. */
2648	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2649	/** Taskgate selector. */
2650	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2651	/** 286 Interrupt gate selector. */
2652	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2653	/** 286 Trapgate selector. */
2654	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2655	/** Undefined system selector. */
2656	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2657	/** 386 TSS selector. */
2658	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2659	/** Undefined system selector. */
2660	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2661	/** 386 TSS selector - Busy. */
2662	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2663	/** 386 Callgate selector. */
2664	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2665	/** Undefined system selector. */
2666	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2667	/** 386 Interruptgate selector. */
2668	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2669	/** 386 Trapgate selector. */
2670	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2671	/** @} */
2672
2673	/** @name AMD64 System Selector Types.
2674	* @{ */
2675	/** LDT selector. */
2676	#define AMD64_SEL_TYPE_SYS_LDT 2
2677	/** TSS selector - Busy. */
2678	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2679	/** TSS selector - Busy. */
2680	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2681	/** Callgate selector. */
2682	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2683	/** Interruptgate selector. */
2684	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2685	/** Trapgate selector. */
2686	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2687	/** @} */
2688
2689	/** @} */
2690
2691
2692	/** @name Descriptor Table Entry Flag Masks.
2693	* These are for the 2nd 32-bit word of a descriptor.
2694	* @{ */
2695	/** Bits 8-11 - TYPE - Descriptor type mask. */
2696	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2697	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2698	#define X86_DESC_S RT_BIT(12)
2699	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2700	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2701	/** Bit 15 - P - Present. */
2702	#define X86_DESC_P RT_BIT(15)
2703	/** Bit 20 - AVL - Available for system software. */
2704	#define X86_DESC_AVL RT_BIT(20)
2705	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2706	#define X86_DESC_DB RT_BIT(22)
2707	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2708	* used, if clear byte. */
2709	#define X86_DESC_G RT_BIT(23)
2710	/** @} */
2711
2712	/** @} */
2713
2714
2715	/** @name Task Segments.
2716	* @{
2717	*/
2718
2719	/**
2720	* 16-bit Task Segment (TSS).
2721	*/
2722	#pragma pack(1)
2723	typedef struct X86TSS16
2724	{
2725	/** Back link to previous task. (static) */
2726	RTSEL selPrev;
2727	/** Ring-0 stack pointer. (static) */
2728	uint16_t sp0;
2729	/** Ring-0 stack segment. (static) */
2730	RTSEL ss0;
2731	/** Ring-1 stack pointer. (static) */
2732	uint16_t sp1;
2733	/** Ring-1 stack segment. (static) */
2734	RTSEL ss1;
2735	/** Ring-2 stack pointer. (static) */
2736	uint16_t sp2;
2737	/** Ring-2 stack segment. (static) */
2738	RTSEL ss2;
2739	/** IP before task switch. */
2740	uint16_t ip;
2741	/** FLAGS before task switch. */
2742	uint16_t flags;
2743	/** AX before task switch. */
2744	uint16_t ax;
2745	/** CX before task switch. */
2746	uint16_t cx;
2747	/** DX before task switch. */
2748	uint16_t dx;
2749	/** BX before task switch. */
2750	uint16_t bx;
2751	/** SP before task switch. */
2752	uint16_t sp;
2753	/** BP before task switch. */
2754	uint16_t bp;
2755	/** SI before task switch. */
2756	uint16_t si;
2757	/** DI before task switch. */
2758	uint16_t di;
2759	/** ES before task switch. */
2760	RTSEL es;
2761	/** CS before task switch. */
2762	RTSEL cs;
2763	/** SS before task switch. */
2764	RTSEL ss;
2765	/** DS before task switch. */
2766	RTSEL ds;
2767	/** LDTR before task switch. */
2768	RTSEL selLdt;
2769	} X86TSS16;
2770	#ifndef VBOX_FOR_DTRACE_LIB
2771	AssertCompileSize(X86TSS16, 44);
2772	#endif
2773	#pragma pack()
2774	/** Pointer to a 16-bit task segment. */
2775	typedef X86TSS16 *PX86TSS16;
2776	/** Pointer to a const 16-bit task segment. */
2777	typedef const X86TSS16 *PCX86TSS16;
2778
2779
2780	/**
2781	* 32-bit Task Segment (TSS).
2782	*/
2783	#pragma pack(1)
2784	typedef struct X86TSS32
2785	{
2786	/** Back link to previous task. (static) */
2787	RTSEL selPrev;
2788	uint16_t padding1;
2789	/** Ring-0 stack pointer. (static) */
2790	uint32_t esp0;
2791	/** Ring-0 stack segment. (static) */
2792	RTSEL ss0;
2793	uint16_t padding_ss0;
2794	/** Ring-1 stack pointer. (static) */
2795	uint32_t esp1;
2796	/** Ring-1 stack segment. (static) */
2797	RTSEL ss1;
2798	uint16_t padding_ss1;
2799	/** Ring-2 stack pointer. (static) */
2800	uint32_t esp2;
2801	/** Ring-2 stack segment. (static) */
2802	RTSEL ss2;
2803	uint16_t padding_ss2;
2804	/** Page directory for the task. (static) */
2805	uint32_t cr3;
2806	/** EIP before task switch. */
2807	uint32_t eip;
2808	/** EFLAGS before task switch. */
2809	uint32_t eflags;
2810	/** EAX before task switch. */
2811	uint32_t eax;
2812	/** ECX before task switch. */
2813	uint32_t ecx;
2814	/** EDX before task switch. */
2815	uint32_t edx;
2816	/** EBX before task switch. */
2817	uint32_t ebx;
2818	/** ESP before task switch. */
2819	uint32_t esp;
2820	/** EBP before task switch. */
2821	uint32_t ebp;
2822	/** ESI before task switch. */
2823	uint32_t esi;
2824	/** EDI before task switch. */
2825	uint32_t edi;
2826	/** ES before task switch. */
2827	RTSEL es;
2828	uint16_t padding_es;
2829	/** CS before task switch. */
2830	RTSEL cs;
2831	uint16_t padding_cs;
2832	/** SS before task switch. */
2833	RTSEL ss;
2834	uint16_t padding_ss;
2835	/** DS before task switch. */
2836	RTSEL ds;
2837	uint16_t padding_ds;
2838	/** FS before task switch. */
2839	RTSEL fs;
2840	uint16_t padding_fs;
2841	/** GS before task switch. */
2842	RTSEL gs;
2843	uint16_t padding_gs;
2844	/** LDTR before task switch. */
2845	RTSEL selLdt;
2846	uint16_t padding_ldt;
2847	/** Debug trap flag */
2848	uint16_t fDebugTrap;
2849	/** Offset relative to the TSS of the start of the I/O Bitmap
2850	* and the end of the interrupt redirection bitmap. */
2851	uint16_t offIoBitmap;
2852	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2853	uint8_t IntRedirBitmap[32];
2854	} X86TSS32;
2855	#pragma pack()
2856	/** Pointer to task segment. */
2857	typedef X86TSS32 *PX86TSS32;
2858	/** Pointer to const task segment. */
2859	typedef const X86TSS32 *PCX86TSS32;
2860
2861
2862	/**
2863	* 64-bit Task segment.
2864	*/
2865	#pragma pack(1)
2866	typedef struct X86TSS64
2867	{
2868	/** Reserved. */
2869	uint32_t u32Reserved;
2870	/** Ring-0 stack pointer. (static) */
2871	uint64_t rsp0;
2872	/** Ring-1 stack pointer. (static) */
2873	uint64_t rsp1;
2874	/** Ring-2 stack pointer. (static) */
2875	uint64_t rsp2;
2876	/** Reserved. */
2877	uint32_t u32Reserved2[2];
2878	/* IST */
2879	uint64_t ist1;
2880	uint64_t ist2;
2881	uint64_t ist3;
2882	uint64_t ist4;
2883	uint64_t ist5;
2884	uint64_t ist6;
2885	uint64_t ist7;
2886	/* Reserved. */
2887	uint16_t u16Reserved[5];
2888	/** Offset relative to the TSS of the start of the I/O Bitmap
2889	* and the end of the interrupt redirection bitmap. */
2890	uint16_t offIoBitmap;
2891	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2892	uint8_t IntRedirBitmap[32];
2893	} X86TSS64;
2894	#pragma pack()
2895	/** Pointer to a 64-bit task segment. */
2896	typedef X86TSS64 *PX86TSS64;
2897	/** Pointer to a const 64-bit task segment. */
2898	typedef const X86TSS64 *PCX86TSS64;
2899	#ifndef VBOX_FOR_DTRACE_LIB
2900	AssertCompileSize(X86TSS64, 136);
2901	#endif
2902
2903	/** @} */
2904
2905
2906	/** @name Selectors.
2907	* @{
2908	*/
2909
2910	/**
2911	* The shift used to convert a selector from and to index an index (C).
2912	*/
2913	#define X86_SEL_SHIFT 3
2914
2915	/**
2916	* The mask used to mask off the table indicator and CPL of an selector.
2917	*/
2918	#define X86_SEL_MASK 0xfff8U
2919
2920	/**
2921	* The bit indicating that a selector is in the LDT and not in the GDT.
2922	*/
2923	#define X86_SEL_LDT 0x0004U
2924	/**
2925	* The bit mask for getting the RPL of a selector.
2926	*/
2927	#define X86_SEL_RPL 0x0003U
2928
2929	/** @} */
2930
2931
2932	/**
2933	* x86 Exceptions/Faults/Traps.
2934	*/
2935	typedef enum X86XCPT
2936	{
2937	/** \#DE - Divide error. */
2938	X86_XCPT_DE = 0x00,
2939	/** \#DB - Debug event (single step, DRx, ..) */
2940	X86_XCPT_DB = 0x01,
2941	/** NMI - Non-Maskable Interrupt */
2942	X86_XCPT_NMI = 0x02,
2943	/** \#BP - Breakpoint (INT3). */
2944	X86_XCPT_BP = 0x03,
2945	/** \#OF - Overflow (INTO). */
2946	X86_XCPT_OF = 0x04,
2947	/** \#BR - Bound range exceeded (BOUND). */
2948	X86_XCPT_BR = 0x05,
2949	/** \#UD - Undefined opcode. */
2950	X86_XCPT_UD = 0x06,
2951	/** \#NM - Device not available (math coprocessor device). */
2952	X86_XCPT_NM = 0x07,
2953	/** \#DF - Double fault. */
2954	X86_XCPT_DF = 0x08,
2955	/** ??? - Coprocessor segment overrun (obsolete). */
2956	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2957	/** \#TS - Taskswitch (TSS). */
2958	X86_XCPT_TS = 0x0a,
2959	/** \#NP - Segment no present. */
2960	X86_XCPT_NP = 0x0b,
2961	/** \#SS - Stack segment fault. */
2962	X86_XCPT_SS = 0x0c,
2963	/** \#GP - General protection fault. */
2964	X86_XCPT_GP = 0x0d,
2965	/** \#PF - Page fault. */
2966	X86_XCPT_PF = 0x0e,
2967	/* 0x0f is reserved. */
2968	/** \#MF - Math fault (FPU). */
2969	X86_XCPT_MF = 0x10,
2970	/** \#AC - Alignment check. */
2971	X86_XCPT_AC = 0x11,
2972	/** \#MC - Machine check. */
2973	X86_XCPT_MC = 0x12,
2974	/** \#XF - SIMD Floating-Pointer Exception. */
2975	X86_XCPT_XF = 0x13
2976	} X86XCPT;
2977	/** Pointer to a x86 exception code. */
2978	typedef X86XCPT *PX86XCPT;
2979	/** Pointer to a const x86 exception code. */
2980	typedef const X86XCPT *PCX86XCPT;
2981
2982
2983	/** @name Trap Error Codes
2984	* @{
2985	*/
2986	/** External indicator. */
2987	#define X86_TRAP_ERR_EXTERNAL 1
2988	/** IDT indicator. */
2989	#define X86_TRAP_ERR_IDT 2
2990	/** Descriptor table indicator - If set LDT, if clear GDT. */
2991	#define X86_TRAP_ERR_TI 4
2992	/** Mask for getting the selector. */
2993	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2994	/** Shift for getting the selector table index (C type index). */
2995	#define X86_TRAP_ERR_SEL_SHIFT 3
2996	/** @} */
2997
2998
2999	/** @name \#PF Trap Error Codes
3000	* @{
3001	*/
3002	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3003	#define X86_TRAP_PF_P RT_BIT(0)
3004	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3005	#define X86_TRAP_PF_RW RT_BIT(1)
3006	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3007	#define X86_TRAP_PF_US RT_BIT(2)
3008	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3009	#define X86_TRAP_PF_RSVD RT_BIT(3)
3010	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3011	#define X86_TRAP_PF_ID RT_BIT(4)
3012	/** @} */
3013
3014	#pragma pack(1)
3015	/**
3016	* 32-bit IDTR/GDTR.
3017	*/
3018	typedef struct X86XDTR32
3019	{
3020	/** Size of the descriptor table. */
3021	uint16_t cb;
3022	/** Address of the descriptor table. */
3023	uint32_t uAddr;
3024	} X86XDTR32, *PX86XDTR32;
3025	#pragma pack()
3026
3027	#pragma pack(1)
3028	/**
3029	* 64-bit IDTR/GDTR.
3030	*/
3031	typedef struct X86XDTR64
3032	{
3033	/** Size of the descriptor table. */
3034	uint16_t cb;
3035	/** Address of the descriptor table. */
3036	uint64_t uAddr;
3037	} X86XDTR64, *PX86XDTR64;
3038	#pragma pack()
3039
3040
3041	/** @name ModR/M
3042	* @{ */
3043	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3044	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3045	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3046	#define X86_MODRM_REG_SHIFT 3
3047	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3048	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3049	#define X86_MODRM_MOD_SHIFT 6
3050	#ifndef VBOX_FOR_DTRACE_LIB
3051	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3052	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3053	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3054	#endif
3055	/** @} */
3056
3057	/** @name SIB
3058	* @{ */
3059	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3060	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3061	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3062	#define X86_SIB_INDEX_SHIFT 3
3063	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3064	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3065	#define X86_SIB_SCALE_SHIFT 6
3066	#ifndef VBOX_FOR_DTRACE_LIB
3067	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3068	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3069	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3070	#endif
3071	/** @} */
3072
3073	/** @name General register indexes
3074	* @{ */
3075	#define X86_GREG_xAX 0
3076	#define X86_GREG_xCX 1
3077	#define X86_GREG_xDX 2
3078	#define X86_GREG_xBX 3
3079	#define X86_GREG_xSP 4
3080	#define X86_GREG_xBP 5
3081	#define X86_GREG_xSI 6
3082	#define X86_GREG_xDI 7
3083	#define X86_GREG_x8 8
3084	#define X86_GREG_x9 9
3085	#define X86_GREG_x10 10
3086	#define X86_GREG_x11 11
3087	#define X86_GREG_x12 12
3088	#define X86_GREG_x13 13
3089	#define X86_GREG_x14 14
3090	#define X86_GREG_x15 15
3091	/** @} */
3092
3093	/** @name X86_SREG_XXX - Segment register indexes.
3094	* @{ */
3095	#define X86_SREG_ES 0
3096	#define X86_SREG_CS 1
3097	#define X86_SREG_SS 2
3098	#define X86_SREG_DS 3
3099	#define X86_SREG_FS 4
3100	#define X86_SREG_GS 5
3101	/** @} */
3102
3103
3104	/** @} */
3105
3106	#endif
3107

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source: vbox/trunk/include/iprt/x86.h@ 41247

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