x86.h@ 42117

Last change on this file since 42117 was 42056, checked in by vboxsync, 13 years ago
VMM/HWVMXR0: Save/restore IA32_TSC_AUX MSR across VMX non-root ops.
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	/** Bit 1 - Reserved, reads as 1. */
165	#define X86_EFL_1 RT_BIT(1)
166	/** Bit 2 - PF - Parity flag - Status flag. */
167	#define X86_EFL_PF RT_BIT(2)
168	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169	#define X86_EFL_AF RT_BIT(4)
170	/** Bit 6 - ZF - Zero flag - Status flag. */
171	#define X86_EFL_ZF RT_BIT(6)
172	/** Bit 7 - SF - Signed flag - Status flag. */
173	#define X86_EFL_SF RT_BIT(7)
174	/** Bit 8 - TF - Trap flag - System flag. */
175	#define X86_EFL_TF RT_BIT(8)
176	/** Bit 9 - IF - Interrupt flag - System flag. */
177	#define X86_EFL_IF RT_BIT(9)
178	/** Bit 10 - DF - Direction flag - Control flag. */
179	#define X86_EFL_DF RT_BIT(10)
180	/** Bit 11 - OF - Overflow flag - Status flag. */
181	#define X86_EFL_OF RT_BIT(11)
182	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
184	/** Bit 14 - NT - Nested task flag - System flag. */
185	#define X86_EFL_NT RT_BIT(14)
186	/** Bit 16 - RF - Resume flag - System flag. */
187	#define X86_EFL_RF RT_BIT(16)
188	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189	#define X86_EFL_VM RT_BIT(17)
190	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191	#define X86_EFL_AC RT_BIT(18)
192	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193	#define X86_EFL_VIF RT_BIT(19)
194	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195	#define X86_EFL_VIP RT_BIT(20)
196	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197	#define X86_EFL_ID RT_BIT(21)
198	/** IOPL shift. */
199	#define X86_EFL_IOPL_SHIFT 12
200	/** The the IOPL level from the flags. */
201	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
202	/** Bits restored by popf */
203	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
204	/** @} */
205
206
207	/** CPUID Feature information - ECX.
208	* CPUID query with EAX=1.
209	*/
210	#ifndef VBOX_FOR_DTRACE_LIB
211	typedef struct X86CPUIDFEATECX
212	{
213	/** Bit 0 - SSE3 - Supports SSE3 or not. */
214	unsigned u1SSE3 : 1;
215	/** Bit 1 - PCLMULQDQ. */
216	unsigned u1PCLMULQDQ : 1;
217	/** Bit 2 - DS Area 64-bit layout. */
218	unsigned u1DTE64 : 1;
219	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
220	unsigned u1Monitor : 1;
221	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
222	unsigned u1CPLDS : 1;
223	/** Bit 5 - VMX - Virtual Machine Technology. */
224	unsigned u1VMX : 1;
225	/** Bit 6 - SMX: Safer Mode Extensions. */
226	unsigned u1SMX : 1;
227	/** Bit 7 - EST - Enh. SpeedStep Tech. */
228	unsigned u1EST : 1;
229	/** Bit 8 - TM2 - Terminal Monitor 2. */
230	unsigned u1TM2 : 1;
231	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
232	unsigned u1SSSE3 : 1;
233	/** Bit 10 - CNTX-ID - L1 Context ID. */
234	unsigned u1CNTXID : 1;
235	/** Bit 11 - Reserved. */
236	unsigned u1Reserved1 : 1;
237	/** Bit 12 - FMA. */
238	unsigned u1FMA : 1;
239	/** Bit 13 - CX16 - CMPXCHG16B. */
240	unsigned u1CX16 : 1;
241	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
242	unsigned u1TPRUpdate : 1;
243	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
244	unsigned u1PDCM : 1;
245	/** Bit 16 - Reserved. */
246	unsigned u1Reserved2 : 1;
247	/** Bit 17 - PCID - Process-context identifiers. */
248	unsigned u1PCID : 1;
249	/** Bit 18 - Direct Cache Access. */
250	unsigned u1DCA : 1;
251	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
252	unsigned u1SSE4_1 : 1;
253	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
254	unsigned u1SSE4_2 : 1;
255	/** Bit 21 - x2APIC. */
256	unsigned u1x2APIC : 1;
257	/** Bit 22 - MOVBE - Supports MOVBE. */
258	unsigned u1MOVBE : 1;
259	/** Bit 23 - POPCNT - Supports POPCNT. */
260	unsigned u1POPCNT : 1;
261	/** Bit 24 - TSC-Deadline. */
262	unsigned u1TSCDEADLINE : 1;
263	/** Bit 25 - AES. */
264	unsigned u1AES : 1;
265	/** Bit 26 - XSAVE - Supports XSAVE. */
266	unsigned u1XSAVE : 1;
267	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
268	unsigned u1OSXSAVE : 1;
269	/** Bit 28 - AVX - Supports AVX instruction extensions. */
270	unsigned u1AVX : 1;
271	/** Bit 29 - 30 - Reserved */
272	unsigned u2Reserved3 : 2;
273	/** Bit 31 - Hypervisor present (we're a guest). */
274	unsigned u1HVP : 1;
275	} X86CPUIDFEATECX;
276	#else /* VBOX_FOR_DTRACE_LIB */
277	typedef uint32_t X86CPUIDFEATECX;
278	#endif /* VBOX_FOR_DTRACE_LIB */
279	/** Pointer to CPUID Feature Information - ECX. */
280	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
281	/** Pointer to const CPUID Feature Information - ECX. */
282	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
283
284
285	/** CPUID Feature Information - EDX.
286	* CPUID query with EAX=1.
287	*/
288	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
289	typedef struct X86CPUIDFEATEDX
290	{
291	/** Bit 0 - FPU - x87 FPU on Chip. */
292	unsigned u1FPU : 1;
293	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
294	unsigned u1VME : 1;
295	/** Bit 2 - DE - Debugging extensions. */
296	unsigned u1DE : 1;
297	/** Bit 3 - PSE - Page Size Extension. */
298	unsigned u1PSE : 1;
299	/** Bit 4 - TSC - Time Stamp Counter. */
300	unsigned u1TSC : 1;
301	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
302	unsigned u1MSR : 1;
303	/** Bit 6 - PAE - Physical Address Extension. */
304	unsigned u1PAE : 1;
305	/** Bit 7 - MCE - Machine Check Exception. */
306	unsigned u1MCE : 1;
307	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
308	unsigned u1CX8 : 1;
309	/** Bit 9 - APIC - APIC On-Chip. */
310	unsigned u1APIC : 1;
311	/** Bit 10 - Reserved. */
312	unsigned u1Reserved1 : 1;
313	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
314	unsigned u1SEP : 1;
315	/** Bit 12 - MTRR - Memory Type Range Registers. */
316	unsigned u1MTRR : 1;
317	/** Bit 13 - PGE - PTE Global Bit. */
318	unsigned u1PGE : 1;
319	/** Bit 14 - MCA - Machine Check Architecture. */
320	unsigned u1MCA : 1;
321	/** Bit 15 - CMOV - Conditional Move Instructions. */
322	unsigned u1CMOV : 1;
323	/** Bit 16 - PAT - Page Attribute Table. */
324	unsigned u1PAT : 1;
325	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
326	unsigned u1PSE36 : 1;
327	/** Bit 18 - PSN - Processor Serial Number. */
328	unsigned u1PSN : 1;
329	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
330	unsigned u1CLFSH : 1;
331	/** Bit 20 - Reserved. */
332	unsigned u1Reserved2 : 1;
333	/** Bit 21 - DS - Debug Store. */
334	unsigned u1DS : 1;
335	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
336	unsigned u1ACPI : 1;
337	/** Bit 23 - MMX - Intel MMX 'Technology'. */
338	unsigned u1MMX : 1;
339	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
340	unsigned u1FXSR : 1;
341	/** Bit 25 - SSE - SSE Support. */
342	unsigned u1SSE : 1;
343	/** Bit 26 - SSE2 - SSE2 Support. */
344	unsigned u1SSE2 : 1;
345	/** Bit 27 - SS - Self Snoop. */
346	unsigned u1SS : 1;
347	/** Bit 28 - HTT - Hyper-Threading Technology. */
348	unsigned u1HTT : 1;
349	/** Bit 29 - TM - Thermal Monitor. */
350	unsigned u1TM : 1;
351	/** Bit 30 - Reserved - . */
352	unsigned u1Reserved3 : 1;
353	/** Bit 31 - PBE - Pending Break Enabled. */
354	unsigned u1PBE : 1;
355	} X86CPUIDFEATEDX;
356	#else /* VBOX_FOR_DTRACE_LIB */
357	typedef uint32_t X86CPUIDFEATEDX;
358	#endif /* VBOX_FOR_DTRACE_LIB */
359	/** Pointer to CPUID Feature Information - EDX. */
360	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
361	/** Pointer to const CPUID Feature Information - EDX. */
362	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
363
364	/** @name CPUID Vendor information.
365	* CPUID query with EAX=0.
366	* @{
367	*/
368	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
369	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
370	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
371
372	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
373	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
374	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
375	/** @} */
376
377
378	/** @name CPUID Feature information.
379	* CPUID query with EAX=1.
380	* @{
381	*/
382	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
383	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
384	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
385	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
386	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
387	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
388	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
389	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
390	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
391	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
392	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
393	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
394	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
395	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
396	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
397	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
398	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
399	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
400	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
401	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
402	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
403	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
404	/** ECX Bit 12 - FMA. */
405	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
406	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
407	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
408	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
409	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
410	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
411	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
412	/** ECX Bit 17 - PCID - Process-context identifiers. */
413	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
414	/** ECX Bit 18 - DCA - Direct Cache Access. */
415	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
416	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
417	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
418	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
419	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
420	/** ECX Bit 21 - x2APIC support. */
421	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
422	/** ECX Bit 22 - MOVBE instruction. */
423	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
424	/** ECX Bit 23 - POPCNT instruction. */
425	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
426	/** ECX Bir 24 - TSC-Deadline. */
427	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
428	/** ECX Bit 25 - AES instructions. */
429	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
430	/** ECX Bit 26 - XSAVE instruction. */
431	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
432	/** ECX Bit 27 - OSXSAVE instruction. */
433	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
434	/** ECX Bit 28 - AVX. */
435	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
436	/** ECX Bit 31 - Hypervisor Present (software only). */
437	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
438
439
440	/** Bit 0 - FPU - x87 FPU on Chip. */
441	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
442	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
443	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
444	/** Bit 2 - DE - Debugging extensions. */
445	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
446	/** Bit 3 - PSE - Page Size Extension. */
447	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
448	/** Bit 4 - TSC - Time Stamp Counter. */
449	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
450	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
451	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
452	/** Bit 6 - PAE - Physical Address Extension. */
453	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
454	/** Bit 7 - MCE - Machine Check Exception. */
455	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
456	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
457	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
458	/** Bit 9 - APIC - APIC On-Chip. */
459	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
460	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
461	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
462	/** Bit 12 - MTRR - Memory Type Range Registers. */
463	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
464	/** Bit 13 - PGE - PTE Global Bit. */
465	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
466	/** Bit 14 - MCA - Machine Check Architecture. */
467	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
468	/** Bit 15 - CMOV - Conditional Move Instructions. */
469	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
470	/** Bit 16 - PAT - Page Attribute Table. */
471	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
472	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
473	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
474	/** Bit 18 - PSN - Processor Serial Number. */
475	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
476	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
477	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
478	/** Bit 21 - DS - Debug Store. */
479	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
480	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
481	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
482	/** Bit 23 - MMX - Intel MMX Technology. */
483	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
484	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
485	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
486	/** Bit 25 - SSE - SSE Support. */
487	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
488	/** Bit 26 - SSE2 - SSE2 Support. */
489	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
490	/** Bit 27 - SS - Self Snoop. */
491	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
492	/** Bit 28 - HTT - Hyper-Threading Technology. */
493	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
494	/** Bit 29 - TM - Therm. Monitor. */
495	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
496	/** Bit 31 - PBE - Pending Break Enabled. */
497	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
498	/** @} */
499
500	/** @name CPUID mwait/monitor information.
501	* CPUID query with EAX=5.
502	* @{
503	*/
504	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
505	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
506	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
507	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
508	/** @} */
509
510
511	/** @name CPUID Extended Feature information.
512	* CPUID query with EAX=0x80000001.
513	* @{
514	*/
515	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
516	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
517
518	/** EDX Bit 11 - SYSCALL/SYSRET. */
519	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
520	/** EDX Bit 20 - No-Execute/Execute-Disable. */
521	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
522	/** EDX Bit 26 - 1 GB large page. */
523	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
524	/** EDX Bit 27 - RDTSCP. */
525	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
526	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
527	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
528	/** @}*/
529
530	/** @name CPUID AMD Feature information.
531	* CPUID query with EAX=0x80000001.
532	* @{
533	*/
534	/** Bit 0 - FPU - x87 FPU on Chip. */
535	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
536	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
537	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
538	/** Bit 2 - DE - Debugging extensions. */
539	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
540	/** Bit 3 - PSE - Page Size Extension. */
541	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
542	/** Bit 4 - TSC - Time Stamp Counter. */
543	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
544	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
545	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
546	/** Bit 6 - PAE - Physical Address Extension. */
547	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
548	/** Bit 7 - MCE - Machine Check Exception. */
549	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
550	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
551	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
552	/** Bit 9 - APIC - APIC On-Chip. */
553	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
554	/** Bit 12 - MTRR - Memory Type Range Registers. */
555	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
556	/** Bit 13 - PGE - PTE Global Bit. */
557	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
558	/** Bit 14 - MCA - Machine Check Architecture. */
559	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
560	/** Bit 15 - CMOV - Conditional Move Instructions. */
561	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
562	/** Bit 16 - PAT - Page Attribute Table. */
563	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
564	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
565	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
566	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
567	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
568	/** Bit 23 - MMX - Intel MMX Technology. */
569	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
570	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
571	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
572	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
573	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
574	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
575	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
576	/** Bit 31 - 3DNOW - AMD 3DNow. */
577	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
578
579	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
580	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
581	/** Bit 2 - SVM - AMD VM extensions. */
582	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
583	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
584	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
585	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
586	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
587	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
588	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
589	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
590	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
591	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
592	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
593	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
594	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
595	/** Bit 9 - OSVW - AMD OS visible workaround. */
596	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
597	/** Bit 10 - IBS - Instruct based sampling. */
598	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
599	/** Bit 11 - SSE5 - SSE5 instruction support. */
600	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
601	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
602	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
603	/** Bit 13 - WDT - AMD Watchdog timer support. */
604	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
605
606	/** @} */
607
608
609	/** @name CPUID AMD Feature information.
610	* CPUID query with EAX=0x80000007.
611	* @{
612	*/
613	/** Bit 0 - TS - Temperature Sensor. */
614	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
615	/** Bit 1 - FID - Frequency ID Control. */
616	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
617	/** Bit 2 - VID - Voltage ID Control. */
618	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
619	/** Bit 3 - TTP - THERMTRIP. */
620	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
621	/** Bit 4 - TM - Hardware Thermal Control. */
622	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
623	/** Bit 5 - STC - Software Thermal Control. */
624	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
625	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
626	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
627	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
628	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
629	/** Bit 8 - TSCINVAR - TSC Invariant. */
630	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
631	/** @} */
632
633
634	/** @name CR0
635	* @{ */
636	/** Bit 0 - PE - Protection Enabled */
637	#define X86_CR0_PE RT_BIT(0)
638	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
639	/** Bit 1 - MP - Monitor Coprocessor */
640	#define X86_CR0_MP RT_BIT(1)
641	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
642	/** Bit 2 - EM - Emulation. */
643	#define X86_CR0_EM RT_BIT(2)
644	#define X86_CR0_EMULATE_FPU RT_BIT(2)
645	/** Bit 3 - TS - Task Switch. */
646	#define X86_CR0_TS RT_BIT(3)
647	#define X86_CR0_TASK_SWITCH RT_BIT(3)
648	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
649	#define X86_CR0_ET RT_BIT(4)
650	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
651	/** Bit 5 - NE - Numeric error. */
652	#define X86_CR0_NE RT_BIT(5)
653	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
654	/** Bit 16 - WP - Write Protect. */
655	#define X86_CR0_WP RT_BIT(16)
656	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
657	/** Bit 18 - AM - Alignment Mask. */
658	#define X86_CR0_AM RT_BIT(18)
659	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
660	/** Bit 29 - NW - Not Write-though. */
661	#define X86_CR0_NW RT_BIT(29)
662	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
663	/** Bit 30 - WP - Cache Disable. */
664	#define X86_CR0_CD RT_BIT(30)
665	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
666	/** Bit 31 - PG - Paging. */
667	#define X86_CR0_PG RT_BIT(31)
668	#define X86_CR0_PAGING RT_BIT(31)
669	/** @} */
670
671
672	/** @name CR3
673	* @{ */
674	/** Bit 3 - PWT - Page-level Writes Transparent. */
675	#define X86_CR3_PWT RT_BIT(3)
676	/** Bit 4 - PCD - Page-level Cache Disable. */
677	#define X86_CR3_PCD RT_BIT(4)
678	/** Bits 12-31 - - Page directory page number. */
679	#define X86_CR3_PAGE_MASK (0xfffff000)
680	/** Bits 5-31 - - PAE Page directory page number. */
681	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
682	/** Bits 12-51 - - AMD64 Page directory page number. */
683	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
684	/** @} */
685
686
687	/** @name CR4
688	* @{ */
689	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
690	#define X86_CR4_VME RT_BIT(0)
691	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
692	#define X86_CR4_PVI RT_BIT(1)
693	/** Bit 2 - TSD - Time Stamp Disable. */
694	#define X86_CR4_TSD RT_BIT(2)
695	/** Bit 3 - DE - Debugging Extensions. */
696	#define X86_CR4_DE RT_BIT(3)
697	/** Bit 4 - PSE - Page Size Extension. */
698	#define X86_CR4_PSE RT_BIT(4)
699	/** Bit 5 - PAE - Physical Address Extension. */
700	#define X86_CR4_PAE RT_BIT(5)
701	/** Bit 6 - MCE - Machine-Check Enable. */
702	#define X86_CR4_MCE RT_BIT(6)
703	/** Bit 7 - PGE - Page Global Enable. */
704	#define X86_CR4_PGE RT_BIT(7)
705	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
706	#define X86_CR4_PCE RT_BIT(8)
707	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
708	#define X86_CR4_OSFSXR RT_BIT(9)
709	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
710	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
711	/** Bit 13 - VMXE - VMX mode is enabled. */
712	#define X86_CR4_VMXE RT_BIT(13)
713	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
714	#define X86_CR4_SMXE RT_BIT(14)
715	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
716	#define X86_CR4_PCIDE RT_BIT(17)
717	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
718	* extended states. */
719	#define X86_CR4_OSXSAVE RT_BIT(18)
720	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
721	#define X86_CR4_SMEP RT_BIT(20)
722	/** @} */
723
724
725	/** @name DR6
726	* @{ */
727	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
728	#define X86_DR6_B0 RT_BIT(0)
729	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
730	#define X86_DR6_B1 RT_BIT(1)
731	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
732	#define X86_DR6_B2 RT_BIT(2)
733	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
734	#define X86_DR6_B3 RT_BIT(3)
735	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
736	#define X86_DR6_BD RT_BIT(13)
737	/** Bit 14 - BS - Single step */
738	#define X86_DR6_BS RT_BIT(14)
739	/** Bit 15 - BT - Task switch. (TSS T bit.) */
740	#define X86_DR6_BT RT_BIT(15)
741	/** Value of DR6 after powerup/reset. */
742	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
743	/** @} */
744
745
746	/** @name DR7
747	* @{ */
748	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
749	#define X86_DR7_L0 RT_BIT(0)
750	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
751	#define X86_DR7_G0 RT_BIT(1)
752	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
753	#define X86_DR7_L1 RT_BIT(2)
754	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
755	#define X86_DR7_G1 RT_BIT(3)
756	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
757	#define X86_DR7_L2 RT_BIT(4)
758	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
759	#define X86_DR7_G2 RT_BIT(5)
760	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
761	#define X86_DR7_L3 RT_BIT(6)
762	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
763	#define X86_DR7_G3 RT_BIT(7)
764	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
765	#define X86_DR7_LE RT_BIT(8)
766	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
767	#define X86_DR7_GE RT_BIT(9)
768
769	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
770	* any DR register is accessed. */
771	#define X86_DR7_GD RT_BIT(13)
772	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
773	#define X86_DR7_RW0_MASK (3 << 16)
774	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
775	#define X86_DR7_LEN0_MASK (3 << 18)
776	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
777	#define X86_DR7_RW1_MASK (3 << 20)
778	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
779	#define X86_DR7_LEN1_MASK (3 << 22)
780	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
781	#define X86_DR7_RW2_MASK (3 << 24)
782	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
783	#define X86_DR7_LEN2_MASK (3 << 26)
784	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
785	#define X86_DR7_RW3_MASK (3 << 28)
786	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
787	#define X86_DR7_LEN3_MASK (3 << 30)
788
789	/** Bits which must be 1s. */
790	#define X86_DR7_MB1_MASK (RT_BIT(10))
791
792	/** Calcs the L bit of Nth breakpoint.
793	* @param iBp The breakpoint number [0..3].
794	*/
795	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
796
797	/** Calcs the G bit of Nth breakpoint.
798	* @param iBp The breakpoint number [0..3].
799	*/
800	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
801
802	/** @name Read/Write values.
803	* @{ */
804	/** Break on instruction fetch only. */
805	#define X86_DR7_RW_EO 0U
806	/** Break on write only. */
807	#define X86_DR7_RW_WO 1U
808	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
809	#define X86_DR7_RW_IO 2U
810	/** Break on read or write (but not instruction fetches). */
811	#define X86_DR7_RW_RW 3U
812	/** @} */
813
814	/** Shifts a X86_DR7_RW_* value to its right place.
815	* @param iBp The breakpoint number [0..3].
816	* @param fRw One of the X86_DR7_RW_* value.
817	*/
818	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
819
820	/** @name Length values.
821	* @{ */
822	#define X86_DR7_LEN_BYTE 0U
823	#define X86_DR7_LEN_WORD 1U
824	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
825	#define X86_DR7_LEN_DWORD 3U
826	/** @} */
827
828	/** Shifts a X86_DR7_LEN_* value to its right place.
829	* @param iBp The breakpoint number [0..3].
830	* @param cb One of the X86_DR7_LEN_* values.
831	*/
832	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
833
834	/** Fetch the breakpoint length bits from the DR7 value.
835	* @param uDR7 DR7 value
836	* @param iBp The breakpoint number [0..3].
837	*/
838	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
839
840	/** Mask used to check if any breakpoints are enabled. */
841	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
842
843	/** Mask used to check if any io breakpoints are set. */
844	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
845
846	/** Value of DR7 after powerup/reset. */
847	#define X86_DR7_INIT_VAL 0x400
848	/** @} */
849
850
851	/** @name Machine Specific Registers
852	* @{
853	*/
854
855	/** Time Stamp Counter. */
856	#define MSR_IA32_TSC 0x10
857
858	#define MSR_IA32_PLATFORM_ID 0x17
859
860	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
861	#define MSR_IA32_APICBASE 0x1b
862	#endif
863
864	/** CPU Feature control. */
865	#define MSR_IA32_FEATURE_CONTROL 0x3A
866	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
867	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
868
869	/** BIOS update trigger (microcode update). */
870	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
871
872	/** BIOS update signature (microcode). */
873	#define MSR_IA32_BIOS_SIGN_ID 0x8B
874
875	/** General performance counter no. 0. */
876	#define MSR_IA32_PMC0 0xC1
877	/** General performance counter no. 1. */
878	#define MSR_IA32_PMC1 0xC2
879	/** General performance counter no. 2. */
880	#define MSR_IA32_PMC2 0xC3
881	/** General performance counter no. 3. */
882	#define MSR_IA32_PMC3 0xC4
883
884	/** Nehalem power control. */
885	#define MSR_IA32_PLATFORM_INFO 0xCE
886
887	/** Get FSB clock status (Intel-specific). */
888	#define MSR_IA32_FSB_CLOCK_STS 0xCD
889
890	/** MTRR Capabilities. */
891	#define MSR_IA32_MTRR_CAP 0xFE
892
893
894	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
895	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
896	* R0 SS == CS + 8
897	* R3 CS == CS + 16
898	* R3 SS == CS + 24
899	*/
900	#define MSR_IA32_SYSENTER_CS 0x174
901	/** SYSENTER_ESP - the R0 ESP. */
902	#define MSR_IA32_SYSENTER_ESP 0x175
903	/** SYSENTER_EIP - the R0 EIP. */
904	#define MSR_IA32_SYSENTER_EIP 0x176
905	#endif
906
907	/** Machine Check Global Capabilities Register. */
908	#define MSR_IA32_MCP_CAP 0x179
909	/** Machine Check Global Status Register. */
910	#define MSR_IA32_MCP_STATUS 0x17A
911	/** Machine Check Global Control Register. */
912	#define MSR_IA32_MCP_CTRL 0x17B
913
914	/** Trace/Profile Resource Control (R/W) */
915	#define MSR_IA32_DEBUGCTL 0x1D9
916
917	/** Page Attribute Table. */
918	#define MSR_IA32_CR_PAT 0x277
919
920	/** Performance counter MSRs. (Intel only) */
921	#define MSR_IA32_PERFEVTSEL0 0x186
922	#define MSR_IA32_PERFEVTSEL1 0x187
923	#define MSR_IA32_FLEX_RATIO 0x194
924	#define MSR_IA32_PERF_STATUS 0x198
925	#define MSR_IA32_PERF_CTL 0x199
926	#define MSR_IA32_THERM_STATUS 0x19c
927
928	/** Enable misc. processor features (R/W). */
929	#define MSR_IA32_MISC_ENABLE 0x1A0
930	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
931	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
932	/** Automatic Thermal Control Circuit Enable (R/W). */
933	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
934	/** Performance Monitoring Available (R). */
935	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
936	/** Branch Trace Storage Unavailable (R/O). */
937	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
938	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
939	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
940	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
941	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
942	/** If MONITOR/MWAIT is supported (R/W). */
943	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
944	/** Limit CPUID Maxval to 3 leafs (R/W). */
945	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
946	/** When set to 1, xTPR messages are disabled (R/W). */
947	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
948	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
949	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
950
951	#define IA32_MTRR_PHYSBASE0 0x200
952	#define IA32_MTRR_PHYSMASK0 0x201
953	#define IA32_MTRR_PHYSBASE1 0x202
954	#define IA32_MTRR_PHYSMASK1 0x203
955	#define IA32_MTRR_PHYSBASE2 0x204
956	#define IA32_MTRR_PHYSMASK2 0x205
957	#define IA32_MTRR_PHYSBASE3 0x206
958	#define IA32_MTRR_PHYSMASK3 0x207
959	#define IA32_MTRR_PHYSBASE4 0x208
960	#define IA32_MTRR_PHYSMASK4 0x209
961	#define IA32_MTRR_PHYSBASE5 0x20a
962	#define IA32_MTRR_PHYSMASK5 0x20b
963	#define IA32_MTRR_PHYSBASE6 0x20c
964	#define IA32_MTRR_PHYSMASK6 0x20d
965	#define IA32_MTRR_PHYSBASE7 0x20e
966	#define IA32_MTRR_PHYSMASK7 0x20f
967	#define IA32_MTRR_PHYSBASE8 0x210
968	#define IA32_MTRR_PHYSMASK8 0x211
969	#define IA32_MTRR_PHYSBASE9 0x212
970	#define IA32_MTRR_PHYSMASK9 0x213
971
972	/** Fixed range MTRRs.
973	* @{ */
974	#define IA32_MTRR_FIX64K_00000 0x250
975	#define IA32_MTRR_FIX16K_80000 0x258
976	#define IA32_MTRR_FIX16K_A0000 0x259
977	#define IA32_MTRR_FIX4K_C0000 0x268
978	#define IA32_MTRR_FIX4K_C8000 0x269
979	#define IA32_MTRR_FIX4K_D0000 0x26a
980	#define IA32_MTRR_FIX4K_D8000 0x26b
981	#define IA32_MTRR_FIX4K_E0000 0x26c
982	#define IA32_MTRR_FIX4K_E8000 0x26d
983	#define IA32_MTRR_FIX4K_F0000 0x26e
984	#define IA32_MTRR_FIX4K_F8000 0x26f
985	/** @} */
986
987	/** MTRR Default Range. */
988	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
989
990	#define MSR_IA32_MC0_CTL 0x400
991	#define MSR_IA32_MC0_STATUS 0x401
992
993	/** Basic VMX information. */
994	#define MSR_IA32_VMX_BASIC_INFO 0x480
995	/** Allowed settings for pin-based VM execution controls */
996	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
997	/** Allowed settings for proc-based VM execution controls */
998	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
999	/** Allowed settings for the VMX exit controls. */
1000	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1001	/** Allowed settings for the VMX entry controls. */
1002	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1003	/** Misc VMX info. */
1004	#define MSR_IA32_VMX_MISC 0x485
1005	/** Fixed cleared bits in CR0. */
1006	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1007	/** Fixed set bits in CR0. */
1008	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1009	/** Fixed cleared bits in CR4. */
1010	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1011	/** Fixed set bits in CR4. */
1012	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1013	/** Information for enumerating fields in the VMCS. */
1014	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1015	/** Allowed settings for secondary proc-based VM execution controls */
1016	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1017	/** EPT capabilities. */
1018	#define MSR_IA32_VMX_EPT_CAPS 0x48C
1019	/** DS Save Area (R/W). */
1020	#define MSR_IA32_DS_AREA 0x600
1021	/** X2APIC MSR ranges. */
1022	#define MSR_IA32_APIC_START 0x800
1023	#define MSR_IA32_APIC_END 0x900
1024
1025	/** K6 EFER - Extended Feature Enable Register. */
1026	#define MSR_K6_EFER 0xc0000080
1027	/** @todo document EFER */
1028	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1029	#define MSR_K6_EFER_SCE RT_BIT(0)
1030	/** Bit 8 - LME - Long mode enabled. (R/W) */
1031	#define MSR_K6_EFER_LME RT_BIT(8)
1032	/** Bit 10 - LMA - Long mode active. (R) */
1033	#define MSR_K6_EFER_LMA RT_BIT(10)
1034	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1035	#define MSR_K6_EFER_NXE RT_BIT(11)
1036	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1037	#define MSR_K6_EFER_SVME RT_BIT(12)
1038	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1039	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1040	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1041	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1042	/** K6 STAR - SYSCALL/RET targets. */
1043	#define MSR_K6_STAR 0xc0000081
1044	/** Shift value for getting the SYSRET CS and SS value. */
1045	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1046	/** Shift value for getting the SYSCALL CS and SS value. */
1047	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1048	/** Selector mask for use after shifting. */
1049	#define MSR_K6_STAR_SEL_MASK 0xffff
1050	/** The mask which give the SYSCALL EIP. */
1051	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1052	/** K6 WHCR - Write Handling Control Register. */
1053	#define MSR_K6_WHCR 0xc0000082
1054	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1055	#define MSR_K6_UWCCR 0xc0000085
1056	/** K6 PSOR - Processor State Observability Register. */
1057	#define MSR_K6_PSOR 0xc0000087
1058	/** K6 PFIR - Page Flush/Invalidate Register. */
1059	#define MSR_K6_PFIR 0xc0000088
1060
1061	/** Performance counter MSRs. (AMD only) */
1062	#define MSR_K7_EVNTSEL0 0xc0010000
1063	#define MSR_K7_EVNTSEL1 0xc0010001
1064	#define MSR_K7_EVNTSEL2 0xc0010002
1065	#define MSR_K7_EVNTSEL3 0xc0010003
1066	#define MSR_K7_PERFCTR0 0xc0010004
1067	#define MSR_K7_PERFCTR1 0xc0010005
1068	#define MSR_K7_PERFCTR2 0xc0010006
1069	#define MSR_K7_PERFCTR3 0xc0010007
1070
1071	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1072	#define MSR_K8_LSTAR 0xc0000082
1073	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1074	#define MSR_K8_CSTAR 0xc0000083
1075	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1076	#define MSR_K8_SF_MASK 0xc0000084
1077	/** K8 FS.base - The 64-bit base FS register. */
1078	#define MSR_K8_FS_BASE 0xc0000100
1079	/** K8 GS.base - The 64-bit base GS register. */
1080	#define MSR_K8_GS_BASE 0xc0000101
1081	/** K8 KernelGSbase - Used with SWAPGS. */
1082	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1083	/** K8 TSC_AUX - Used with RDTSCP. */
1084	#define MSR_K8_TSC_AUX 0xc0000103
1085	#define MSR_K8_SYSCFG 0xc0010010
1086	#define MSR_K8_HWCR 0xc0010015
1087	#define MSR_K8_IORRBASE0 0xc0010016
1088	#define MSR_K8_IORRMASK0 0xc0010017
1089	#define MSR_K8_IORRBASE1 0xc0010018
1090	#define MSR_K8_IORRMASK1 0xc0010019
1091	#define MSR_K8_TOP_MEM1 0xc001001a
1092	#define MSR_K8_TOP_MEM2 0xc001001d
1093	#define MSR_K8_VM_CR 0xc0010114
1094	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1095
1096	#define MSR_K8_IGNNE 0xc0010115
1097	#define MSR_K8_SMM_CTL 0xc0010116
1098	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1099	* host state during world switch.
1100	*/
1101	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1102
1103	/** @} */
1104
1105
1106	/** @name Page Table / Directory / Directory Pointers / L4.
1107	* @{
1108	*/
1109
1110	/** Page table/directory entry as an unsigned integer. */
1111	typedef uint32_t X86PGUINT;
1112	/** Pointer to a page table/directory table entry as an unsigned integer. */
1113	typedef X86PGUINT *PX86PGUINT;
1114	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1115	typedef X86PGUINT const *PCX86PGUINT;
1116
1117	/** Number of entries in a 32-bit PT/PD. */
1118	#define X86_PG_ENTRIES 1024
1119
1120
1121	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1122	typedef uint64_t X86PGPAEUINT;
1123	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1124	typedef X86PGPAEUINT *PX86PGPAEUINT;
1125	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1126	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1127
1128	/** Number of entries in a PAE PT/PD. */
1129	#define X86_PG_PAE_ENTRIES 512
1130	/** Number of entries in a PAE PDPT. */
1131	#define X86_PG_PAE_PDPE_ENTRIES 4
1132
1133	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1134	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1135	/** Number of entries in an AMD64 PDPT.
1136	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1137	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1138
1139	/** The size of a 4KB page. */
1140	#define X86_PAGE_4K_SIZE _4K
1141	/** The page shift of a 4KB page. */
1142	#define X86_PAGE_4K_SHIFT 12
1143	/** The 4KB page offset mask. */
1144	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1145	/** The 4KB page base mask for virtual addresses. */
1146	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1147	/** The 4KB page base mask for virtual addresses - 32bit version. */
1148	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1149
1150	/** The size of a 2MB page. */
1151	#define X86_PAGE_2M_SIZE _2M
1152	/** The page shift of a 2MB page. */
1153	#define X86_PAGE_2M_SHIFT 21
1154	/** The 2MB page offset mask. */
1155	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1156	/** The 2MB page base mask for virtual addresses. */
1157	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1158	/** The 2MB page base mask for virtual addresses - 32bit version. */
1159	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1160
1161	/** The size of a 4MB page. */
1162	#define X86_PAGE_4M_SIZE _4M
1163	/** The page shift of a 4MB page. */
1164	#define X86_PAGE_4M_SHIFT 22
1165	/** The 4MB page offset mask. */
1166	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1167	/** The 4MB page base mask for virtual addresses. */
1168	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1169	/** The 4MB page base mask for virtual addresses - 32bit version. */
1170	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1171
1172
1173
1174	/** @name Page Table Entry
1175	* @{
1176	*/
1177	/** Bit 0 - P - Present bit. */
1178	#define X86_PTE_BIT_P 0
1179	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1180	#define X86_PTE_BIT_RW 1
1181	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1182	#define X86_PTE_BIT_US 2
1183	/** Bit 3 - PWT - Page level write thru bit. */
1184	#define X86_PTE_BIT_PWT 3
1185	/** Bit 4 - PCD - Page level cache disable bit. */
1186	#define X86_PTE_BIT_PCD 4
1187	/** Bit 5 - A - Access bit. */
1188	#define X86_PTE_BIT_A 5
1189	/** Bit 6 - D - Dirty bit. */
1190	#define X86_PTE_BIT_D 6
1191	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1192	#define X86_PTE_BIT_PAT 7
1193	/** Bit 8 - G - Global flag. */
1194	#define X86_PTE_BIT_G 8
1195
1196	/** Bit 0 - P - Present bit mask. */
1197	#define X86_PTE_P RT_BIT(0)
1198	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1199	#define X86_PTE_RW RT_BIT(1)
1200	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1201	#define X86_PTE_US RT_BIT(2)
1202	/** Bit 3 - PWT - Page level write thru bit mask. */
1203	#define X86_PTE_PWT RT_BIT(3)
1204	/** Bit 4 - PCD - Page level cache disable bit mask. */
1205	#define X86_PTE_PCD RT_BIT(4)
1206	/** Bit 5 - A - Access bit mask. */
1207	#define X86_PTE_A RT_BIT(5)
1208	/** Bit 6 - D - Dirty bit mask. */
1209	#define X86_PTE_D RT_BIT(6)
1210	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1211	#define X86_PTE_PAT RT_BIT(7)
1212	/** Bit 8 - G - Global bit mask. */
1213	#define X86_PTE_G RT_BIT(8)
1214
1215	/** Bits 9-11 - - Available for use to system software. */
1216	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1217	/** Bits 12-31 - - Physical Page number of the next level. */
1218	#define X86_PTE_PG_MASK ( 0xfffff000 )
1219
1220	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1221	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1222	/** Bits 63 - NX - PAE/LM - No execution flag. */
1223	#define X86_PTE_PAE_NX RT_BIT_64(63)
1224	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1225	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1226	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1227	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1228	/** No bits - - LM - MBZ bits when NX is active. */
1229	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1230	/** Bits 63 - - LM - MBZ bits when no NX. */
1231	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1232
1233	/**
1234	* Page table entry.
1235	*/
1236	typedef struct X86PTEBITS
1237	{
1238	/** Flags whether(=1) or not the page is present. */
1239	unsigned u1Present : 1;
1240	/** Read(=0) / Write(=1) flag. */
1241	unsigned u1Write : 1;
1242	/** User(=1) / Supervisor (=0) flag. */
1243	unsigned u1User : 1;
1244	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1245	unsigned u1WriteThru : 1;
1246	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1247	unsigned u1CacheDisable : 1;
1248	/** Accessed flag.
1249	* Indicates that the page have been read or written to. */
1250	unsigned u1Accessed : 1;
1251	/** Dirty flag.
1252	* Indicates that the page has been written to. */
1253	unsigned u1Dirty : 1;
1254	/** Reserved / If PAT enabled, bit 2 of the index. */
1255	unsigned u1PAT : 1;
1256	/** Global flag. (Ignored in all but final level.) */
1257	unsigned u1Global : 1;
1258	/** Available for use to system software. */
1259	unsigned u3Available : 3;
1260	/** Physical Page number of the next level. */
1261	unsigned u20PageNo : 20;
1262	} X86PTEBITS;
1263	/** Pointer to a page table entry. */
1264	typedef X86PTEBITS *PX86PTEBITS;
1265	/** Pointer to a const page table entry. */
1266	typedef const X86PTEBITS *PCX86PTEBITS;
1267
1268	/**
1269	* Page table entry.
1270	*/
1271	typedef union X86PTE
1272	{
1273	/** Unsigned integer view */
1274	X86PGUINT u;
1275	/** Bit field view. */
1276	X86PTEBITS n;
1277	/** 32-bit view. */
1278	uint32_t au32[1];
1279	/** 16-bit view. */
1280	uint16_t au16[2];
1281	/** 8-bit view. */
1282	uint8_t au8[4];
1283	} X86PTE;
1284	/** Pointer to a page table entry. */
1285	typedef X86PTE *PX86PTE;
1286	/** Pointer to a const page table entry. */
1287	typedef const X86PTE *PCX86PTE;
1288
1289
1290	/**
1291	* PAE page table entry.
1292	*/
1293	typedef struct X86PTEPAEBITS
1294	{
1295	/** Flags whether(=1) or not the page is present. */
1296	uint32_t u1Present : 1;
1297	/** Read(=0) / Write(=1) flag. */
1298	uint32_t u1Write : 1;
1299	/** User(=1) / Supervisor(=0) flag. */
1300	uint32_t u1User : 1;
1301	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1302	uint32_t u1WriteThru : 1;
1303	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1304	uint32_t u1CacheDisable : 1;
1305	/** Accessed flag.
1306	* Indicates that the page have been read or written to. */
1307	uint32_t u1Accessed : 1;
1308	/** Dirty flag.
1309	* Indicates that the page has been written to. */
1310	uint32_t u1Dirty : 1;
1311	/** Reserved / If PAT enabled, bit 2 of the index. */
1312	uint32_t u1PAT : 1;
1313	/** Global flag. (Ignored in all but final level.) */
1314	uint32_t u1Global : 1;
1315	/** Available for use to system software. */
1316	uint32_t u3Available : 3;
1317	/** Physical Page number of the next level - Low Part. Don't use this. */
1318	uint32_t u20PageNoLow : 20;
1319	/** Physical Page number of the next level - High Part. Don't use this. */
1320	uint32_t u20PageNoHigh : 20;
1321	/** MBZ bits */
1322	uint32_t u11Reserved : 11;
1323	/** No Execute flag. */
1324	uint32_t u1NoExecute : 1;
1325	} X86PTEPAEBITS;
1326	/** Pointer to a page table entry. */
1327	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1328	/** Pointer to a page table entry. */
1329	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1330
1331	/**
1332	* PAE Page table entry.
1333	*/
1334	typedef union X86PTEPAE
1335	{
1336	/** Unsigned integer view */
1337	X86PGPAEUINT u;
1338	/** Bit field view. */
1339	X86PTEPAEBITS n;
1340	/** 32-bit view. */
1341	uint32_t au32[2];
1342	/** 16-bit view. */
1343	uint16_t au16[4];
1344	/** 8-bit view. */
1345	uint8_t au8[8];
1346	} X86PTEPAE;
1347	/** Pointer to a PAE page table entry. */
1348	typedef X86PTEPAE *PX86PTEPAE;
1349	/** Pointer to a const PAE page table entry. */
1350	typedef const X86PTEPAE *PCX86PTEPAE;
1351	/** @} */
1352
1353	/**
1354	* Page table.
1355	*/
1356	typedef struct X86PT
1357	{
1358	/** PTE Array. */
1359	X86PTE a[X86_PG_ENTRIES];
1360	} X86PT;
1361	/** Pointer to a page table. */
1362	typedef X86PT *PX86PT;
1363	/** Pointer to a const page table. */
1364	typedef const X86PT *PCX86PT;
1365
1366	/** The page shift to get the PT index. */
1367	#define X86_PT_SHIFT 12
1368	/** The PT index mask (apply to a shifted page address). */
1369	#define X86_PT_MASK 0x3ff
1370
1371
1372	/**
1373	* Page directory.
1374	*/
1375	typedef struct X86PTPAE
1376	{
1377	/** PTE Array. */
1378	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1379	} X86PTPAE;
1380	/** Pointer to a page table. */
1381	typedef X86PTPAE *PX86PTPAE;
1382	/** Pointer to a const page table. */
1383	typedef const X86PTPAE *PCX86PTPAE;
1384
1385	/** The page shift to get the PA PTE index. */
1386	#define X86_PT_PAE_SHIFT 12
1387	/** The PAE PT index mask (apply to a shifted page address). */
1388	#define X86_PT_PAE_MASK 0x1ff
1389
1390
1391	/** @name 4KB Page Directory Entry
1392	* @{
1393	*/
1394	/** Bit 0 - P - Present bit. */
1395	#define X86_PDE_P RT_BIT(0)
1396	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1397	#define X86_PDE_RW RT_BIT(1)
1398	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1399	#define X86_PDE_US RT_BIT(2)
1400	/** Bit 3 - PWT - Page level write thru bit. */
1401	#define X86_PDE_PWT RT_BIT(3)
1402	/** Bit 4 - PCD - Page level cache disable bit. */
1403	#define X86_PDE_PCD RT_BIT(4)
1404	/** Bit 5 - A - Access bit. */
1405	#define X86_PDE_A RT_BIT(5)
1406	/** Bit 7 - PS - Page size attribute.
1407	* Clear mean 4KB pages, set means large pages (2/4MB). */
1408	#define X86_PDE_PS RT_BIT(7)
1409	/** Bits 9-11 - - Available for use to system software. */
1410	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1411	/** Bits 12-31 - - Physical Page number of the next level. */
1412	#define X86_PDE_PG_MASK ( 0xfffff000 )
1413
1414	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1415	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1416	/** Bits 63 - NX - PAE/LM - No execution flag. */
1417	#define X86_PDE_PAE_NX RT_BIT_64(63)
1418	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1419	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1420	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1421	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1422	/** Bit 7 - - LM - MBZ bits when NX is active. */
1423	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1424	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1425	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1426
1427	/**
1428	* Page directory entry.
1429	*/
1430	typedef struct X86PDEBITS
1431	{
1432	/** Flags whether(=1) or not the page is present. */
1433	unsigned u1Present : 1;
1434	/** Read(=0) / Write(=1) flag. */
1435	unsigned u1Write : 1;
1436	/** User(=1) / Supervisor (=0) flag. */
1437	unsigned u1User : 1;
1438	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1439	unsigned u1WriteThru : 1;
1440	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1441	unsigned u1CacheDisable : 1;
1442	/** Accessed flag.
1443	* Indicates that the page has been read or written to. */
1444	unsigned u1Accessed : 1;
1445	/** Reserved / Ignored (dirty bit). */
1446	unsigned u1Reserved0 : 1;
1447	/** Size bit if PSE is enabled - in any event it's 0. */
1448	unsigned u1Size : 1;
1449	/** Reserved / Ignored (global bit). */
1450	unsigned u1Reserved1 : 1;
1451	/** Available for use to system software. */
1452	unsigned u3Available : 3;
1453	/** Physical Page number of the next level. */
1454	unsigned u20PageNo : 20;
1455	} X86PDEBITS;
1456	/** Pointer to a page directory entry. */
1457	typedef X86PDEBITS *PX86PDEBITS;
1458	/** Pointer to a const page directory entry. */
1459	typedef const X86PDEBITS *PCX86PDEBITS;
1460
1461
1462	/**
1463	* PAE page directory entry.
1464	*/
1465	typedef struct X86PDEPAEBITS
1466	{
1467	/** Flags whether(=1) or not the page is present. */
1468	uint32_t u1Present : 1;
1469	/** Read(=0) / Write(=1) flag. */
1470	uint32_t u1Write : 1;
1471	/** User(=1) / Supervisor (=0) flag. */
1472	uint32_t u1User : 1;
1473	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1474	uint32_t u1WriteThru : 1;
1475	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1476	uint32_t u1CacheDisable : 1;
1477	/** Accessed flag.
1478	* Indicates that the page has been read or written to. */
1479	uint32_t u1Accessed : 1;
1480	/** Reserved / Ignored (dirty bit). */
1481	uint32_t u1Reserved0 : 1;
1482	/** Size bit if PSE is enabled - in any event it's 0. */
1483	uint32_t u1Size : 1;
1484	/** Reserved / Ignored (global bit). / */
1485	uint32_t u1Reserved1 : 1;
1486	/** Available for use to system software. */
1487	uint32_t u3Available : 3;
1488	/** Physical Page number of the next level - Low Part. Don't use! */
1489	uint32_t u20PageNoLow : 20;
1490	/** Physical Page number of the next level - High Part. Don't use! */
1491	uint32_t u20PageNoHigh : 20;
1492	/** MBZ bits */
1493	uint32_t u11Reserved : 11;
1494	/** No Execute flag. */
1495	uint32_t u1NoExecute : 1;
1496	} X86PDEPAEBITS;
1497	/** Pointer to a page directory entry. */
1498	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1499	/** Pointer to a const page directory entry. */
1500	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1501
1502	/** @} */
1503
1504
1505	/** @name 2/4MB Page Directory Entry
1506	* @{
1507	*/
1508	/** Bit 0 - P - Present bit. */
1509	#define X86_PDE4M_P RT_BIT(0)
1510	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1511	#define X86_PDE4M_RW RT_BIT(1)
1512	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1513	#define X86_PDE4M_US RT_BIT(2)
1514	/** Bit 3 - PWT - Page level write thru bit. */
1515	#define X86_PDE4M_PWT RT_BIT(3)
1516	/** Bit 4 - PCD - Page level cache disable bit. */
1517	#define X86_PDE4M_PCD RT_BIT(4)
1518	/** Bit 5 - A - Access bit. */
1519	#define X86_PDE4M_A RT_BIT(5)
1520	/** Bit 6 - D - Dirty bit. */
1521	#define X86_PDE4M_D RT_BIT(6)
1522	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1523	#define X86_PDE4M_PS RT_BIT(7)
1524	/** Bit 8 - G - Global flag. */
1525	#define X86_PDE4M_G RT_BIT(8)
1526	/** Bits 9-11 - AVL - Available for use to system software. */
1527	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1528	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1529	#define X86_PDE4M_PAT RT_BIT(12)
1530	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1531	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1532	/** Bits 22-31 - - Physical Page number. */
1533	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1534	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1535	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1536	/** The number of bits to the high part of the page number. */
1537	#define X86_PDE4M_PG_HIGH_SHIFT 19
1538	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1539	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1540
1541	/** Bits 21-51 - - PAE/LM - Physical Page number.
1542	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1543	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1544	/** Bits 63 - NX - PAE/LM - No execution flag. */
1545	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1546	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1547	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1548	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1549	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1550	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1551	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1552	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1553	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1554
1555	/**
1556	* 4MB page directory entry.
1557	*/
1558	typedef struct X86PDE4MBITS
1559	{
1560	/** Flags whether(=1) or not the page is present. */
1561	unsigned u1Present : 1;
1562	/** Read(=0) / Write(=1) flag. */
1563	unsigned u1Write : 1;
1564	/** User(=1) / Supervisor (=0) flag. */
1565	unsigned u1User : 1;
1566	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1567	unsigned u1WriteThru : 1;
1568	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1569	unsigned u1CacheDisable : 1;
1570	/** Accessed flag.
1571	* Indicates that the page have been read or written to. */
1572	unsigned u1Accessed : 1;
1573	/** Dirty flag.
1574	* Indicates that the page has been written to. */
1575	unsigned u1Dirty : 1;
1576	/** Page size flag - always 1 for 4MB entries. */
1577	unsigned u1Size : 1;
1578	/** Global flag. */
1579	unsigned u1Global : 1;
1580	/** Available for use to system software. */
1581	unsigned u3Available : 3;
1582	/** Reserved / If PAT enabled, bit 2 of the index. */
1583	unsigned u1PAT : 1;
1584	/** Bits 32-39 of the page number on AMD64.
1585	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1586	unsigned u8PageNoHigh : 8;
1587	/** Reserved. */
1588	unsigned u1Reserved : 1;
1589	/** Physical Page number of the page. */
1590	unsigned u10PageNo : 10;
1591	} X86PDE4MBITS;
1592	/** Pointer to a page table entry. */
1593	typedef X86PDE4MBITS *PX86PDE4MBITS;
1594	/** Pointer to a const page table entry. */
1595	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1596
1597
1598	/**
1599	* 2MB PAE page directory entry.
1600	*/
1601	typedef struct X86PDE2MPAEBITS
1602	{
1603	/** Flags whether(=1) or not the page is present. */
1604	uint32_t u1Present : 1;
1605	/** Read(=0) / Write(=1) flag. */
1606	uint32_t u1Write : 1;
1607	/** User(=1) / Supervisor(=0) flag. */
1608	uint32_t u1User : 1;
1609	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1610	uint32_t u1WriteThru : 1;
1611	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1612	uint32_t u1CacheDisable : 1;
1613	/** Accessed flag.
1614	* Indicates that the page have been read or written to. */
1615	uint32_t u1Accessed : 1;
1616	/** Dirty flag.
1617	* Indicates that the page has been written to. */
1618	uint32_t u1Dirty : 1;
1619	/** Page size flag - always 1 for 2MB entries. */
1620	uint32_t u1Size : 1;
1621	/** Global flag. */
1622	uint32_t u1Global : 1;
1623	/** Available for use to system software. */
1624	uint32_t u3Available : 3;
1625	/** Reserved / If PAT enabled, bit 2 of the index. */
1626	uint32_t u1PAT : 1;
1627	/** Reserved. */
1628	uint32_t u9Reserved : 9;
1629	/** Physical Page number of the next level - Low part. Don't use! */
1630	uint32_t u10PageNoLow : 10;
1631	/** Physical Page number of the next level - High part. Don't use! */
1632	uint32_t u20PageNoHigh : 20;
1633	/** MBZ bits */
1634	uint32_t u11Reserved : 11;
1635	/** No Execute flag. */
1636	uint32_t u1NoExecute : 1;
1637	} X86PDE2MPAEBITS;
1638	/** Pointer to a 2MB PAE page table entry. */
1639	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1640	/** Pointer to a 2MB PAE page table entry. */
1641	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1642
1643	/** @} */
1644
1645	/**
1646	* Page directory entry.
1647	*/
1648	typedef union X86PDE
1649	{
1650	/** Unsigned integer view. */
1651	X86PGUINT u;
1652	/** Normal view. */
1653	X86PDEBITS n;
1654	/** 4MB view (big). */
1655	X86PDE4MBITS b;
1656	/** 8 bit unsigned integer view. */
1657	uint8_t au8[4];
1658	/** 16 bit unsigned integer view. */
1659	uint16_t au16[2];
1660	/** 32 bit unsigned integer view. */
1661	uint32_t au32[1];
1662	} X86PDE;
1663	/** Pointer to a page directory entry. */
1664	typedef X86PDE *PX86PDE;
1665	/** Pointer to a const page directory entry. */
1666	typedef const X86PDE *PCX86PDE;
1667
1668	/**
1669	* PAE page directory entry.
1670	*/
1671	typedef union X86PDEPAE
1672	{
1673	/** Unsigned integer view. */
1674	X86PGPAEUINT u;
1675	/** Normal view. */
1676	X86PDEPAEBITS n;
1677	/** 2MB page view (big). */
1678	X86PDE2MPAEBITS b;
1679	/** 8 bit unsigned integer view. */
1680	uint8_t au8[8];
1681	/** 16 bit unsigned integer view. */
1682	uint16_t au16[4];
1683	/** 32 bit unsigned integer view. */
1684	uint32_t au32[2];
1685	} X86PDEPAE;
1686	/** Pointer to a page directory entry. */
1687	typedef X86PDEPAE *PX86PDEPAE;
1688	/** Pointer to a const page directory entry. */
1689	typedef const X86PDEPAE *PCX86PDEPAE;
1690
1691	/**
1692	* Page directory.
1693	*/
1694	typedef struct X86PD
1695	{
1696	/** PDE Array. */
1697	X86PDE a[X86_PG_ENTRIES];
1698	} X86PD;
1699	/** Pointer to a page directory. */
1700	typedef X86PD *PX86PD;
1701	/** Pointer to a const page directory. */
1702	typedef const X86PD *PCX86PD;
1703
1704	/** The page shift to get the PD index. */
1705	#define X86_PD_SHIFT 22
1706	/** The PD index mask (apply to a shifted page address). */
1707	#define X86_PD_MASK 0x3ff
1708
1709
1710	/**
1711	* PAE page directory.
1712	*/
1713	typedef struct X86PDPAE
1714	{
1715	/** PDE Array. */
1716	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1717	} X86PDPAE;
1718	/** Pointer to a PAE page directory. */
1719	typedef X86PDPAE *PX86PDPAE;
1720	/** Pointer to a const PAE page directory. */
1721	typedef const X86PDPAE *PCX86PDPAE;
1722
1723	/** The page shift to get the PAE PD index. */
1724	#define X86_PD_PAE_SHIFT 21
1725	/** The PAE PD index mask (apply to a shifted page address). */
1726	#define X86_PD_PAE_MASK 0x1ff
1727
1728
1729	/** @name Page Directory Pointer Table Entry (PAE)
1730	* @{
1731	*/
1732	/** Bit 0 - P - Present bit. */
1733	#define X86_PDPE_P RT_BIT(0)
1734	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1735	#define X86_PDPE_RW RT_BIT(1)
1736	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1737	#define X86_PDPE_US RT_BIT(2)
1738	/** Bit 3 - PWT - Page level write thru bit. */
1739	#define X86_PDPE_PWT RT_BIT(3)
1740	/** Bit 4 - PCD - Page level cache disable bit. */
1741	#define X86_PDPE_PCD RT_BIT(4)
1742	/** Bit 5 - A - Access bit. Long Mode only. */
1743	#define X86_PDPE_A RT_BIT(5)
1744	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1745	#define X86_PDPE_LM_PS RT_BIT(7)
1746	/** Bits 9-11 - - Available for use to system software. */
1747	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1748	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1749	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1750	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1751	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1752	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1753	#define X86_PDPE_LM_NX RT_BIT_64(63)
1754	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1755	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1756	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1757	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1758	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1759	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1760	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1761	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1762
1763
1764	/**
1765	* Page directory pointer table entry.
1766	*/
1767	typedef struct X86PDPEBITS
1768	{
1769	/** Flags whether(=1) or not the page is present. */
1770	uint32_t u1Present : 1;
1771	/** Chunk of reserved bits. */
1772	uint32_t u2Reserved : 2;
1773	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1774	uint32_t u1WriteThru : 1;
1775	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1776	uint32_t u1CacheDisable : 1;
1777	/** Chunk of reserved bits. */
1778	uint32_t u4Reserved : 4;
1779	/** Available for use to system software. */
1780	uint32_t u3Available : 3;
1781	/** Physical Page number of the next level - Low Part. Don't use! */
1782	uint32_t u20PageNoLow : 20;
1783	/** Physical Page number of the next level - High Part. Don't use! */
1784	uint32_t u20PageNoHigh : 20;
1785	/** MBZ bits */
1786	uint32_t u12Reserved : 12;
1787	} X86PDPEBITS;
1788	/** Pointer to a page directory pointer table entry. */
1789	typedef X86PDPEBITS *PX86PTPEBITS;
1790	/** Pointer to a const page directory pointer table entry. */
1791	typedef const X86PDPEBITS *PCX86PTPEBITS;
1792
1793	/**
1794	* Page directory pointer table entry. AMD64 version
1795	*/
1796	typedef struct X86PDPEAMD64BITS
1797	{
1798	/** Flags whether(=1) or not the page is present. */
1799	uint32_t u1Present : 1;
1800	/** Read(=0) / Write(=1) flag. */
1801	uint32_t u1Write : 1;
1802	/** User(=1) / Supervisor (=0) flag. */
1803	uint32_t u1User : 1;
1804	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1805	uint32_t u1WriteThru : 1;
1806	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1807	uint32_t u1CacheDisable : 1;
1808	/** Accessed flag.
1809	* Indicates that the page have been read or written to. */
1810	uint32_t u1Accessed : 1;
1811	/** Chunk of reserved bits. */
1812	uint32_t u3Reserved : 3;
1813	/** Available for use to system software. */
1814	uint32_t u3Available : 3;
1815	/** Physical Page number of the next level - Low Part. Don't use! */
1816	uint32_t u20PageNoLow : 20;
1817	/** Physical Page number of the next level - High Part. Don't use! */
1818	uint32_t u20PageNoHigh : 20;
1819	/** MBZ bits */
1820	uint32_t u11Reserved : 11;
1821	/** No Execute flag. */
1822	uint32_t u1NoExecute : 1;
1823	} X86PDPEAMD64BITS;
1824	/** Pointer to a page directory pointer table entry. */
1825	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1826	/** Pointer to a const page directory pointer table entry. */
1827	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1828
1829	/**
1830	* Page directory pointer table entry.
1831	*/
1832	typedef union X86PDPE
1833	{
1834	/** Unsigned integer view. */
1835	X86PGPAEUINT u;
1836	/** Normal view. */
1837	X86PDPEBITS n;
1838	/** AMD64 view. */
1839	X86PDPEAMD64BITS lm;
1840	/** 8 bit unsigned integer view. */
1841	uint8_t au8[8];
1842	/** 16 bit unsigned integer view. */
1843	uint16_t au16[4];
1844	/** 32 bit unsigned integer view. */
1845	uint32_t au32[2];
1846	} X86PDPE;
1847	/** Pointer to a page directory pointer table entry. */
1848	typedef X86PDPE *PX86PDPE;
1849	/** Pointer to a const page directory pointer table entry. */
1850	typedef const X86PDPE *PCX86PDPE;
1851
1852
1853	/**
1854	* Page directory pointer table.
1855	*/
1856	typedef struct X86PDPT
1857	{
1858	/** PDE Array. */
1859	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1860	} X86PDPT;
1861	/** Pointer to a page directory pointer table. */
1862	typedef X86PDPT *PX86PDPT;
1863	/** Pointer to a const page directory pointer table. */
1864	typedef const X86PDPT *PCX86PDPT;
1865
1866	/** The page shift to get the PDPT index. */
1867	#define X86_PDPT_SHIFT 30
1868	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1869	#define X86_PDPT_MASK_PAE 0x3
1870	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1871	#define X86_PDPT_MASK_AMD64 0x1ff
1872
1873	/** @} */
1874
1875
1876	/** @name Page Map Level-4 Entry (Long Mode PAE)
1877	* @{
1878	*/
1879	/** Bit 0 - P - Present bit. */
1880	#define X86_PML4E_P RT_BIT(0)
1881	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1882	#define X86_PML4E_RW RT_BIT(1)
1883	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1884	#define X86_PML4E_US RT_BIT(2)
1885	/** Bit 3 - PWT - Page level write thru bit. */
1886	#define X86_PML4E_PWT RT_BIT(3)
1887	/** Bit 4 - PCD - Page level cache disable bit. */
1888	#define X86_PML4E_PCD RT_BIT(4)
1889	/** Bit 5 - A - Access bit. */
1890	#define X86_PML4E_A RT_BIT(5)
1891	/** Bits 9-11 - - Available for use to system software. */
1892	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1893	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1894	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1895	/** Bits 8, 7 - - MBZ bits when NX is active. */
1896	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1897	/** Bits 63, 7 - - MBZ bits when no NX. */
1898	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1899	/** Bits 63 - NX - PAE - No execution flag. */
1900	#define X86_PML4E_NX RT_BIT_64(63)
1901
1902	/**
1903	* Page Map Level-4 Entry
1904	*/
1905	typedef struct X86PML4EBITS
1906	{
1907	/** Flags whether(=1) or not the page is present. */
1908	uint32_t u1Present : 1;
1909	/** Read(=0) / Write(=1) flag. */
1910	uint32_t u1Write : 1;
1911	/** User(=1) / Supervisor (=0) flag. */
1912	uint32_t u1User : 1;
1913	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1914	uint32_t u1WriteThru : 1;
1915	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1916	uint32_t u1CacheDisable : 1;
1917	/** Accessed flag.
1918	* Indicates that the page have been read or written to. */
1919	uint32_t u1Accessed : 1;
1920	/** Chunk of reserved bits. */
1921	uint32_t u3Reserved : 3;
1922	/** Available for use to system software. */
1923	uint32_t u3Available : 3;
1924	/** Physical Page number of the next level - Low Part. Don't use! */
1925	uint32_t u20PageNoLow : 20;
1926	/** Physical Page number of the next level - High Part. Don't use! */
1927	uint32_t u20PageNoHigh : 20;
1928	/** MBZ bits */
1929	uint32_t u11Reserved : 11;
1930	/** No Execute flag. */
1931	uint32_t u1NoExecute : 1;
1932	} X86PML4EBITS;
1933	/** Pointer to a page map level-4 entry. */
1934	typedef X86PML4EBITS *PX86PML4EBITS;
1935	/** Pointer to a const page map level-4 entry. */
1936	typedef const X86PML4EBITS *PCX86PML4EBITS;
1937
1938	/**
1939	* Page Map Level-4 Entry.
1940	*/
1941	typedef union X86PML4E
1942	{
1943	/** Unsigned integer view. */
1944	X86PGPAEUINT u;
1945	/** Normal view. */
1946	X86PML4EBITS n;
1947	/** 8 bit unsigned integer view. */
1948	uint8_t au8[8];
1949	/** 16 bit unsigned integer view. */
1950	uint16_t au16[4];
1951	/** 32 bit unsigned integer view. */
1952	uint32_t au32[2];
1953	} X86PML4E;
1954	/** Pointer to a page map level-4 entry. */
1955	typedef X86PML4E *PX86PML4E;
1956	/** Pointer to a const page map level-4 entry. */
1957	typedef const X86PML4E *PCX86PML4E;
1958
1959
1960	/**
1961	* Page Map Level-4.
1962	*/
1963	typedef struct X86PML4
1964	{
1965	/** PDE Array. */
1966	X86PML4E a[X86_PG_PAE_ENTRIES];
1967	} X86PML4;
1968	/** Pointer to a page map level-4. */
1969	typedef X86PML4 *PX86PML4;
1970	/** Pointer to a const page map level-4. */
1971	typedef const X86PML4 *PCX86PML4;
1972
1973	/** The page shift to get the PML4 index. */
1974	#define X86_PML4_SHIFT 39
1975	/** The PML4 index mask (apply to a shifted page address). */
1976	#define X86_PML4_MASK 0x1ff
1977
1978	/** @} */
1979
1980	/** @} */
1981
1982
1983	/**
1984	* 80-bit MMX/FPU register type.
1985	*/
1986	typedef struct X86FPUMMX
1987	{
1988	uint8_t reg[10];
1989	} X86FPUMMX;
1990	/** Pointer to a 80-bit MMX/FPU register type. */
1991	typedef X86FPUMMX *PX86FPUMMX;
1992	/** Pointer to a const 80-bit MMX/FPU register type. */
1993	typedef const X86FPUMMX *PCX86FPUMMX;
1994
1995	/**
1996	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
1997	* @todo verify this...
1998	*/
1999	#pragma pack(1)
2000	typedef struct X86FPUSTATE
2001	{
2002	/** 0x00 - Control word. */
2003	uint16_t FCW;
2004	/** 0x02 - Alignment word */
2005	uint16_t Dummy1;
2006	/** 0x04 - Status word. */
2007	uint16_t FSW;
2008	/** 0x06 - Alignment word */
2009	uint16_t Dummy2;
2010	/** 0x08 - Tag word */
2011	uint16_t FTW;
2012	/** 0x0a - Alignment word */
2013	uint16_t Dummy3;
2014
2015	/** 0x0c - Instruction pointer. */
2016	uint32_t FPUIP;
2017	/** 0x10 - Code selector. */
2018	uint16_t CS;
2019	/** 0x12 - Opcode. */
2020	uint16_t FOP;
2021	/** 0x14 - FOO. */
2022	uint32_t FPUOO;
2023	/** 0x18 - FOS. */
2024	uint32_t FPUOS;
2025	/** 0x1c */
2026	union
2027	{
2028	/** MMX view. */
2029	uint64_t mmx;
2030	/** FPU view - todo. */
2031	X86FPUMMX fpu;
2032	/** Extended precision floating point view. */
2033	RTFLOAT80U r80;
2034	/** Extended precision floating point view v2. */
2035	RTFLOAT80U2 r80Ex;
2036	/** 8-bit view. */
2037	uint8_t au8[16];
2038	/** 16-bit view. */
2039	uint16_t au16[8];
2040	/** 32-bit view. */
2041	uint32_t au32[4];
2042	/** 64-bit view. */
2043	uint64_t au64[2];
2044	/** 128-bit view. (yeah, very helpful) */
2045	uint128_t au128[1];
2046	} regs[8];
2047	} X86FPUSTATE;
2048	#pragma pack()
2049	/** Pointer to a FPU state. */
2050	typedef X86FPUSTATE *PX86FPUSTATE;
2051	/** Pointer to a const FPU state. */
2052	typedef const X86FPUSTATE *PCX86FPUSTATE;
2053
2054	/**
2055	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2056	*/
2057	#pragma pack(1)
2058	typedef struct X86FXSTATE
2059	{
2060	/** 0x00 - Control word. */
2061	uint16_t FCW;
2062	/** 0x02 - Status word. */
2063	uint16_t FSW;
2064	/** 0x04 - Tag word. (The upper byte is always zero.) */
2065	uint16_t FTW;
2066	/** 0x06 - Opcode. */
2067	uint16_t FOP;
2068	/** 0x08 - Instruction pointer. */
2069	uint32_t FPUIP;
2070	/** 0x0c - Code selector. */
2071	uint16_t CS;
2072	uint16_t Rsrvd1;
2073	/** 0x10 - Data pointer. */
2074	uint32_t FPUDP;
2075	/** 0x14 - Data segment */
2076	uint16_t DS;
2077	/** 0x16 */
2078	uint16_t Rsrvd2;
2079	/** 0x18 */
2080	uint32_t MXCSR;
2081	/** 0x1c */
2082	uint32_t MXCSR_MASK;
2083	/** 0x20 */
2084	union
2085	{
2086	/** MMX view. */
2087	uint64_t mmx;
2088	/** FPU view - todo. */
2089	X86FPUMMX fpu;
2090	/** Extended precision floating point view. */
2091	RTFLOAT80U r80;
2092	/** Extended precision floating point view v2 */
2093	RTFLOAT80U2 r80Ex;
2094	/** 8-bit view. */
2095	uint8_t au8[16];
2096	/** 16-bit view. */
2097	uint16_t au16[8];
2098	/** 32-bit view. */
2099	uint32_t au32[4];
2100	/** 64-bit view. */
2101	uint64_t au64[2];
2102	/** 128-bit view. (yeah, very helpful) */
2103	uint128_t au128[1];
2104	} aRegs[8];
2105	/* - offset 160 - */
2106	union
2107	{
2108	/** XMM Register view . /
2109	uint128_t xmm;
2110	/** 8-bit view. */
2111	uint8_t au8[16];
2112	/** 16-bit view. */
2113	uint16_t au16[8];
2114	/** 32-bit view. */
2115	uint32_t au32[4];
2116	/** 64-bit view. */
2117	uint64_t au64[2];
2118	/** 128-bit view. (yeah, very helpful) */
2119	uint128_t au128[1];
2120	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2121	/* - offset 416 - */
2122	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2123	} X86FXSTATE;
2124	#pragma pack()
2125	/** Pointer to a FPU Extended state. */
2126	typedef X86FXSTATE *PX86FXSTATE;
2127	/** Pointer to a const FPU Extended state. */
2128	typedef const X86FXSTATE *PCX86FXSTATE;
2129
2130	/** @name FPU status word flags.
2131	* @{ */
2132	/** Exception Flag: Invalid operation. */
2133	#define X86_FSW_IE RT_BIT(0)
2134	/** Exception Flag: Denormalized operand. */
2135	#define X86_FSW_DE RT_BIT(1)
2136	/** Exception Flag: Zero divide. */
2137	#define X86_FSW_ZE RT_BIT(2)
2138	/** Exception Flag: Overflow. */
2139	#define X86_FSW_OE RT_BIT(3)
2140	/** Exception Flag: Underflow. */
2141	#define X86_FSW_UE RT_BIT(4)
2142	/** Exception Flag: Precision. */
2143	#define X86_FSW_PE RT_BIT(5)
2144	/** Stack fault. */
2145	#define X86_FSW_SF RT_BIT(6)
2146	/** Error summary status. */
2147	#define X86_FSW_ES RT_BIT(7)
2148	/** Mask of exceptions flags, excluding the summary bit. */
2149	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2150	/** Mask of exceptions flags, including the summary bit. */
2151	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2152	/** Condition code 0. */
2153	#define X86_FSW_C0 RT_BIT(8)
2154	/** Condition code 1. */
2155	#define X86_FSW_C1 RT_BIT(9)
2156	/** Condition code 2. */
2157	#define X86_FSW_C2 RT_BIT(10)
2158	/** Top of the stack mask. */
2159	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2160	/** TOP shift value. */
2161	#define X86_FSW_TOP_SHIFT 11
2162	/** Mask for getting TOP value after shifting it right. */
2163	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2164	/** Get the TOP value. */
2165	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2166	/** Condition code 3. */
2167	#define X86_FSW_C3 RT_BIT(14)
2168	/** Mask of exceptions flags, including the summary bit. */
2169	#define X86_FSW_C_MASK UINT16_C(0x4700)
2170	/** FPU busy. */
2171	#define X86_FSW_B RT_BIT(15)
2172	/** @} */
2173
2174
2175	/** @name FPU control word flags.
2176	* @{ */
2177	/** Exception Mask: Invalid operation. */
2178	#define X86_FCW_IM RT_BIT(0)
2179	/** Exception Mask: Denormalized operand. */
2180	#define X86_FCW_DM RT_BIT(1)
2181	/** Exception Mask: Zero divide. */
2182	#define X86_FCW_ZM RT_BIT(2)
2183	/** Exception Mask: Overflow. */
2184	#define X86_FCW_OM RT_BIT(3)
2185	/** Exception Mask: Underflow. */
2186	#define X86_FCW_UM RT_BIT(4)
2187	/** Exception Mask: Precision. */
2188	#define X86_FCW_PM RT_BIT(5)
2189	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2190	* @remarks This includes reserved bit 6. */
2191	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2192	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2193	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2194	/** Precision control mask. */
2195	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2196	/** Precision control: 24-bit. */
2197	#define X86_FCW_PC_24 UINT16_C(0x0000)
2198	/** Precision control: Reserved. */
2199	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2200	/** Precision control: 53-bit. */
2201	#define X86_FCW_PC_53 UINT16_C(0x0200)
2202	/** Precision control: 64-bit. */
2203	#define X86_FCW_PC_64 UINT16_C(0x0300)
2204	/** Rounding control mask. */
2205	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2206	/** Rounding control: To nearest. */
2207	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2208	/** Rounding control: Down. */
2209	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2210	/** Rounding control: Up. */
2211	#define X86_FCW_RC_UP UINT16_C(0x0800)
2212	/** Rounding control: Towards zero. */
2213	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2214	/** Bits which should be zero, apparently. */
2215	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2216	/** @} */
2217
2218
2219	/** @name Selector Descriptor
2220	* @{
2221	*/
2222
2223	#ifndef VBOX_FOR_DTRACE_LIB
2224	/**
2225	* Descriptor attributes.
2226	*/
2227	typedef struct X86DESCATTRBITS
2228	{
2229	/** 00 - Segment Type. */
2230	unsigned u4Type : 4;
2231	/** 04 - Descriptor Type. System(=0) or code/data selector */
2232	unsigned u1DescType : 1;
2233	/** 05 - Descriptor Privelege level. */
2234	unsigned u2Dpl : 2;
2235	/** 07 - Flags selector present(=1) or not. */
2236	unsigned u1Present : 1;
2237	/** 08 - Segment limit 16-19. */
2238	unsigned u4LimitHigh : 4;
2239	/** 0c - Available for system software. */
2240	unsigned u1Available : 1;
2241	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2242	unsigned u1Long : 1;
2243	/** 0e - This flags meaning depends on the segment type. Try make sense out
2244	* of the intel manual yourself. */
2245	unsigned u1DefBig : 1;
2246	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2247	* clear byte. */
2248	unsigned u1Granularity : 1;
2249	} X86DESCATTRBITS;
2250	#endif /* !VBOX_FOR_DTRACE_LIB */
2251
2252	#pragma pack(1)
2253	typedef union X86DESCATTR
2254	{
2255	/** Unsigned integer view. */
2256	uint32_t u;
2257	#ifndef VBOX_FOR_DTRACE_LIB
2258	/** Normal view. */
2259	X86DESCATTRBITS n;
2260	#endif
2261	} X86DESCATTR;
2262	#pragma pack()
2263	/** Pointer to descriptor attributes. */
2264	typedef X86DESCATTR *PX86DESCATTR;
2265	/** Pointer to const descriptor attributes. */
2266	typedef const X86DESCATTR *PCX86DESCATTR;
2267
2268	#ifndef VBOX_FOR_DTRACE_LIB
2269
2270	/**
2271	* Generic descriptor table entry
2272	*/
2273	#pragma pack(1)
2274	typedef struct X86DESCGENERIC
2275	{
2276	/** Limit - Low word. */
2277	unsigned u16LimitLow : 16;
2278	/** Base address - lowe word.
2279	* Don't try set this to 24 because MSC is doing stupid things then. */
2280	unsigned u16BaseLow : 16;
2281	/** Base address - first 8 bits of high word. */
2282	unsigned u8BaseHigh1 : 8;
2283	/** Segment Type. */
2284	unsigned u4Type : 4;
2285	/** Descriptor Type. System(=0) or code/data selector */
2286	unsigned u1DescType : 1;
2287	/** Descriptor Privelege level. */
2288	unsigned u2Dpl : 2;
2289	/** Flags selector present(=1) or not. */
2290	unsigned u1Present : 1;
2291	/** Segment limit 16-19. */
2292	unsigned u4LimitHigh : 4;
2293	/** Available for system software. */
2294	unsigned u1Available : 1;
2295	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2296	unsigned u1Long : 1;
2297	/** This flags meaning depends on the segment type. Try make sense out
2298	* of the intel manual yourself. */
2299	unsigned u1DefBig : 1;
2300	/** Granularity of the limit. If set 4KB granularity is used, if
2301	* clear byte. */
2302	unsigned u1Granularity : 1;
2303	/** Base address - highest 8 bits. */
2304	unsigned u8BaseHigh2 : 8;
2305	} X86DESCGENERIC;
2306	#pragma pack()
2307	/** Pointer to a generic descriptor entry. */
2308	typedef X86DESCGENERIC *PX86DESCGENERIC;
2309	/** Pointer to a const generic descriptor entry. */
2310	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2311
2312	/**
2313	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2314	*/
2315	typedef struct X86DESCGATE
2316	{
2317	/** 00 - Target code segment offset - Low word.
2318	* Ignored if task-gate. */
2319	unsigned u16OffsetLow : 16;
2320	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2321	* TSS selector if task-gate. */
2322	unsigned u16Sel : 16;
2323	/** 20 - Number of parameters for a call-gate.
2324	* Ignored if interrupt-, trap- or task-gate. */
2325	unsigned u4ParmCount : 4;
2326	/** 24 - Reserved / ignored. */
2327	unsigned u4Reserved : 4;
2328	/** 28 - Segment Type. */
2329	unsigned u4Type : 4;
2330	/** 2c - Descriptor Type (0 = system). */
2331	unsigned u1DescType : 1;
2332	/** 2d - Descriptor Privelege level. */
2333	unsigned u2Dpl : 2;
2334	/** 2f - Flags selector present(=1) or not. */
2335	unsigned u1Present : 1;
2336	/** 30 - Target code segment offset - High word.
2337	* Ignored if task-gate. */
2338	unsigned u16OffsetHigh : 16;
2339	} X86DESCGATE;
2340	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2341	typedef X86DESCGATE *PX86DESCGATE;
2342	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2343	typedef const X86DESCGATE *PCX86DESCGATE;
2344
2345	#endif /* VBOX_FOR_DTRACE_LIB */
2346
2347	/**
2348	* Descriptor table entry.
2349	*/
2350	#pragma pack(1)
2351	typedef union X86DESC
2352	{
2353	#ifndef VBOX_FOR_DTRACE_LIB
2354	/** Generic descriptor view. */
2355	X86DESCGENERIC Gen;
2356	/** Gate descriptor view. */
2357	X86DESCGATE Gate;
2358	#endif
2359
2360	/** 8 bit unsigned integer view. */
2361	uint8_t au8[8];
2362	/** 16 bit unsigned integer view. */
2363	uint16_t au16[4];
2364	/** 32 bit unsigned integer view. */
2365	uint32_t au32[2];
2366	/** 64 bit unsigned integer view. */
2367	uint64_t au64[1];
2368	/** Unsigned integer view. */
2369	uint64_t u;
2370	} X86DESC;
2371	#ifndef VBOX_FOR_DTRACE_LIB
2372	AssertCompileSize(X86DESC, 8);
2373	#endif
2374	#pragma pack()
2375	/** Pointer to descriptor table entry. */
2376	typedef X86DESC *PX86DESC;
2377	/** Pointer to const descriptor table entry. */
2378	typedef const X86DESC *PCX86DESC;
2379
2380	/** @def X86DESC_BASE
2381	* Return the base address of a descriptor.
2382	*/
2383	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2384	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2385	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2386	\| ( (desc).Gen.u16BaseLow ) )
2387
2388	/** @def X86DESC_LIMIT
2389	* Return the limit of a descriptor.
2390	*/
2391	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2392	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2393	\| ( (desc).Gen.u16LimitLow ) )
2394
2395	/** @def X86DESC_GET_HID_ATTR
2396	* Get the descriptor attributes for the hidden register.
2397	*/
2398	#define X86DESC_GET_HID_ATTR(desc) /ASM-NOINC/ \
2399	( (desc.u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2400
2401	#ifndef VBOX_FOR_DTRACE_LIB
2402
2403	/**
2404	* 64 bits generic descriptor table entry
2405	* Note: most of these bits have no meaning in long mode.
2406	*/
2407	#pragma pack(1)
2408	typedef struct X86DESC64GENERIC
2409	{
2410	/** Limit - Low word - IGNORED. */
2411	unsigned u16LimitLow : 16;
2412	/** Base address - low word. - IGNORED
2413	* Don't try set this to 24 because MSC is doing stupid things then. */
2414	unsigned u16BaseLow : 16;
2415	/** Base address - first 8 bits of high word. - IGNORED */
2416	unsigned u8BaseHigh1 : 8;
2417	/** Segment Type. */
2418	unsigned u4Type : 4;
2419	/** Descriptor Type. System(=0) or code/data selector */
2420	unsigned u1DescType : 1;
2421	/** Descriptor Privelege level. */
2422	unsigned u2Dpl : 2;
2423	/** Flags selector present(=1) or not. */
2424	unsigned u1Present : 1;
2425	/** Segment limit 16-19. - IGNORED */
2426	unsigned u4LimitHigh : 4;
2427	/** Available for system software. - IGNORED */
2428	unsigned u1Available : 1;
2429	/** Long mode flag. */
2430	unsigned u1Long : 1;
2431	/** This flags meaning depends on the segment type. Try make sense out
2432	* of the intel manual yourself. */
2433	unsigned u1DefBig : 1;
2434	/** Granularity of the limit. If set 4KB granularity is used, if
2435	* clear byte. - IGNORED */
2436	unsigned u1Granularity : 1;
2437	/** Base address - highest 8 bits. - IGNORED */
2438	unsigned u8BaseHigh2 : 8;
2439	/** Base address - bits 63-32. */
2440	unsigned u32BaseHigh3 : 32;
2441	unsigned u8Reserved : 8;
2442	unsigned u5Zeros : 5;
2443	unsigned u19Reserved : 19;
2444	} X86DESC64GENERIC;
2445	#pragma pack()
2446	/** Pointer to a generic descriptor entry. */
2447	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2448	/** Pointer to a const generic descriptor entry. */
2449	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2450
2451	/**
2452	* System descriptor table entry (64 bits)
2453	*
2454	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2455	*/
2456	#pragma pack(1)
2457	typedef struct X86DESC64SYSTEM
2458	{
2459	/** Limit - Low word. */
2460	unsigned u16LimitLow : 16;
2461	/** Base address - lowe word.
2462	* Don't try set this to 24 because MSC is doing stupid things then. */
2463	unsigned u16BaseLow : 16;
2464	/** Base address - first 8 bits of high word. */
2465	unsigned u8BaseHigh1 : 8;
2466	/** Segment Type. */
2467	unsigned u4Type : 4;
2468	/** Descriptor Type. System(=0) or code/data selector */
2469	unsigned u1DescType : 1;
2470	/** Descriptor Privelege level. */
2471	unsigned u2Dpl : 2;
2472	/** Flags selector present(=1) or not. */
2473	unsigned u1Present : 1;
2474	/** Segment limit 16-19. */
2475	unsigned u4LimitHigh : 4;
2476	/** Available for system software. */
2477	unsigned u1Available : 1;
2478	/** Reserved - 0. */
2479	unsigned u1Reserved : 1;
2480	/** This flags meaning depends on the segment type. Try make sense out
2481	* of the intel manual yourself. */
2482	unsigned u1DefBig : 1;
2483	/** Granularity of the limit. If set 4KB granularity is used, if
2484	* clear byte. */
2485	unsigned u1Granularity : 1;
2486	/** Base address - bits 31-24. */
2487	unsigned u8BaseHigh2 : 8;
2488	/** Base address - bits 63-32. */
2489	unsigned u32BaseHigh3 : 32;
2490	unsigned u8Reserved : 8;
2491	unsigned u5Zeros : 5;
2492	unsigned u19Reserved : 19;
2493	} X86DESC64SYSTEM;
2494	#pragma pack()
2495	/** Pointer to a system descriptor entry. */
2496	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2497	/** Pointer to a const system descriptor entry. */
2498	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2499
2500	/**
2501	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2502	*/
2503	typedef struct X86DESC64GATE
2504	{
2505	/** Target code segment offset - Low word. */
2506	unsigned u16OffsetLow : 16;
2507	/** Target code segment selector. */
2508	unsigned u16Sel : 16;
2509	/** Interrupt stack table for interrupt- and trap-gates.
2510	* Ignored by call-gates. */
2511	unsigned u3IST : 3;
2512	/** Reserved / ignored. */
2513	unsigned u5Reserved : 5;
2514	/** Segment Type. */
2515	unsigned u4Type : 4;
2516	/** Descriptor Type (0 = system). */
2517	unsigned u1DescType : 1;
2518	/** Descriptor Privelege level. */
2519	unsigned u2Dpl : 2;
2520	/** Flags selector present(=1) or not. */
2521	unsigned u1Present : 1;
2522	/** Target code segment offset - High word.
2523	* Ignored if task-gate. */
2524	unsigned u16OffsetHigh : 16;
2525	/** Target code segment offset - Top dword.
2526	* Ignored if task-gate. */
2527	unsigned u32OffsetTop : 32;
2528	/** Reserved / ignored / must be zero.
2529	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2530	unsigned u32Reserved : 32;
2531	} X86DESC64GATE;
2532	AssertCompileSize(X86DESC64GATE, 16);
2533	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2534	typedef X86DESC64GATE *PX86DESC64GATE;
2535	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2536	typedef const X86DESC64GATE *PCX86DESC64GATE;
2537
2538	#endif /* VBOX_FOR_DTRACE_LIB */
2539
2540	/**
2541	* Descriptor table entry.
2542	*/
2543	#pragma pack(1)
2544	typedef union X86DESC64
2545	{
2546	#ifndef VBOX_FOR_DTRACE_LIB
2547	/** Generic descriptor view. */
2548	X86DESC64GENERIC Gen;
2549	/** System descriptor view. */
2550	X86DESC64SYSTEM System;
2551	/** Gate descriptor view. */
2552	X86DESC64GATE Gate;
2553	#endif
2554
2555	/** 8 bit unsigned integer view. */
2556	uint8_t au8[16];
2557	/** 16 bit unsigned integer view. */
2558	uint16_t au16[8];
2559	/** 32 bit unsigned integer view. */
2560	uint32_t au32[4];
2561	/** 64 bit unsigned integer view. */
2562	uint64_t au64[2];
2563	} X86DESC64;
2564	#ifndef VBOX_FOR_DTRACE_LIB
2565	AssertCompileSize(X86DESC64, 16);
2566	#endif
2567	#pragma pack()
2568	/** Pointer to descriptor table entry. */
2569	typedef X86DESC64 *PX86DESC64;
2570	/** Pointer to const descriptor table entry. */
2571	typedef const X86DESC64 *PCX86DESC64;
2572
2573	/** @def X86DESC64_BASE
2574	* Return the base of a 64-bit descriptor.
2575	*/
2576	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2577	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2578	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2579	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2580	\| ( (desc).Gen.u16BaseLow ) )
2581
2582
2583
2584	/** @name Host system descriptor table entry - Use with care!
2585	* @{ */
2586	/** Host system descriptor table entry. */
2587	#if HC_ARCH_BITS == 64
2588	typedef X86DESC64 X86DESCHC;
2589	#else
2590	typedef X86DESC X86DESCHC;
2591	#endif
2592	/** Pointer to a host system descriptor table entry. */
2593	#if HC_ARCH_BITS == 64
2594	typedef PX86DESC64 PX86DESCHC;
2595	#else
2596	typedef PX86DESC PX86DESCHC;
2597	#endif
2598	/** Pointer to a const host system descriptor table entry. */
2599	#if HC_ARCH_BITS == 64
2600	typedef PCX86DESC64 PCX86DESCHC;
2601	#else
2602	typedef PCX86DESC PCX86DESCHC;
2603	#endif
2604	/** @} */
2605
2606
2607	/** @name Selector Descriptor Types.
2608	* @{
2609	*/
2610
2611	/** @name Non-System Selector Types.
2612	* @{ */
2613	/** Code(=set)/Data(=clear) bit. */
2614	#define X86_SEL_TYPE_CODE 8
2615	/** Memory(=set)/System(=clear) bit. */
2616	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2617	/** Accessed bit. */
2618	#define X86_SEL_TYPE_ACCESSED 1
2619	/** Expand down bit (for data selectors only). */
2620	#define X86_SEL_TYPE_DOWN 4
2621	/** Conforming bit (for code selectors only). */
2622	#define X86_SEL_TYPE_CONF 4
2623	/** Write bit (for data selectors only). */
2624	#define X86_SEL_TYPE_WRITE 2
2625	/** Read bit (for code selectors only). */
2626	#define X86_SEL_TYPE_READ 2
2627
2628	/** Read only selector type. */
2629	#define X86_SEL_TYPE_RO 0
2630	/** Accessed read only selector type. */
2631	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2632	/** Read write selector type. */
2633	#define X86_SEL_TYPE_RW 2
2634	/** Accessed read write selector type. */
2635	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2636	/** Expand down read only selector type. */
2637	#define X86_SEL_TYPE_RO_DOWN 4
2638	/** Accessed expand down read only selector type. */
2639	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2640	/** Expand down read write selector type. */
2641	#define X86_SEL_TYPE_RW_DOWN 6
2642	/** Accessed expand down read write selector type. */
2643	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2644	/** Execute only selector type. */
2645	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2646	/** Accessed execute only selector type. */
2647	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2648	/** Execute and read selector type. */
2649	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2650	/** Accessed execute and read selector type. */
2651	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2652	/** Conforming execute only selector type. */
2653	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2654	/** Accessed Conforming execute only selector type. */
2655	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2656	/** Conforming execute and write selector type. */
2657	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2658	/** Accessed Conforming execute and write selector type. */
2659	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2660	/** @} */
2661
2662
2663	/** @name System Selector Types.
2664	* @{ */
2665	/** The TSS busy bit mask. */
2666	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2667
2668	/** Undefined system selector type. */
2669	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2670	/** 286 TSS selector. */
2671	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2672	/** LDT selector. */
2673	#define X86_SEL_TYPE_SYS_LDT 2
2674	/** 286 TSS selector - Busy. */
2675	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2676	/** 286 Callgate selector. */
2677	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2678	/** Taskgate selector. */
2679	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2680	/** 286 Interrupt gate selector. */
2681	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2682	/** 286 Trapgate selector. */
2683	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2684	/** Undefined system selector. */
2685	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2686	/** 386 TSS selector. */
2687	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2688	/** Undefined system selector. */
2689	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2690	/** 386 TSS selector - Busy. */
2691	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2692	/** 386 Callgate selector. */
2693	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2694	/** Undefined system selector. */
2695	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2696	/** 386 Interruptgate selector. */
2697	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2698	/** 386 Trapgate selector. */
2699	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2700	/** @} */
2701
2702	/** @name AMD64 System Selector Types.
2703	* @{ */
2704	/** LDT selector. */
2705	#define AMD64_SEL_TYPE_SYS_LDT 2
2706	/** TSS selector - Busy. */
2707	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2708	/** TSS selector - Busy. */
2709	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2710	/** Callgate selector. */
2711	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2712	/** Interruptgate selector. */
2713	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2714	/** Trapgate selector. */
2715	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2716	/** @} */
2717
2718	/** @} */
2719
2720
2721	/** @name Descriptor Table Entry Flag Masks.
2722	* These are for the 2nd 32-bit word of a descriptor.
2723	* @{ */
2724	/** Bits 8-11 - TYPE - Descriptor type mask. */
2725	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2726	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2727	#define X86_DESC_S RT_BIT(12)
2728	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2729	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2730	/** Bit 15 - P - Present. */
2731	#define X86_DESC_P RT_BIT(15)
2732	/** Bit 20 - AVL - Available for system software. */
2733	#define X86_DESC_AVL RT_BIT(20)
2734	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2735	#define X86_DESC_DB RT_BIT(22)
2736	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2737	* used, if clear byte. */
2738	#define X86_DESC_G RT_BIT(23)
2739	/** @} */
2740
2741	/** @} */
2742
2743
2744	/** @name Task Segments.
2745	* @{
2746	*/
2747
2748	/**
2749	* 16-bit Task Segment (TSS).
2750	*/
2751	#pragma pack(1)
2752	typedef struct X86TSS16
2753	{
2754	/** Back link to previous task. (static) */
2755	RTSEL selPrev;
2756	/** Ring-0 stack pointer. (static) */
2757	uint16_t sp0;
2758	/** Ring-0 stack segment. (static) */
2759	RTSEL ss0;
2760	/** Ring-1 stack pointer. (static) */
2761	uint16_t sp1;
2762	/** Ring-1 stack segment. (static) */
2763	RTSEL ss1;
2764	/** Ring-2 stack pointer. (static) */
2765	uint16_t sp2;
2766	/** Ring-2 stack segment. (static) */
2767	RTSEL ss2;
2768	/** IP before task switch. */
2769	uint16_t ip;
2770	/** FLAGS before task switch. */
2771	uint16_t flags;
2772	/** AX before task switch. */
2773	uint16_t ax;
2774	/** CX before task switch. */
2775	uint16_t cx;
2776	/** DX before task switch. */
2777	uint16_t dx;
2778	/** BX before task switch. */
2779	uint16_t bx;
2780	/** SP before task switch. */
2781	uint16_t sp;
2782	/** BP before task switch. */
2783	uint16_t bp;
2784	/** SI before task switch. */
2785	uint16_t si;
2786	/** DI before task switch. */
2787	uint16_t di;
2788	/** ES before task switch. */
2789	RTSEL es;
2790	/** CS before task switch. */
2791	RTSEL cs;
2792	/** SS before task switch. */
2793	RTSEL ss;
2794	/** DS before task switch. */
2795	RTSEL ds;
2796	/** LDTR before task switch. */
2797	RTSEL selLdt;
2798	} X86TSS16;
2799	#ifndef VBOX_FOR_DTRACE_LIB
2800	AssertCompileSize(X86TSS16, 44);
2801	#endif
2802	#pragma pack()
2803	/** Pointer to a 16-bit task segment. */
2804	typedef X86TSS16 *PX86TSS16;
2805	/** Pointer to a const 16-bit task segment. */
2806	typedef const X86TSS16 *PCX86TSS16;
2807
2808
2809	/**
2810	* 32-bit Task Segment (TSS).
2811	*/
2812	#pragma pack(1)
2813	typedef struct X86TSS32
2814	{
2815	/** Back link to previous task. (static) */
2816	RTSEL selPrev;
2817	uint16_t padding1;
2818	/** Ring-0 stack pointer. (static) */
2819	uint32_t esp0;
2820	/** Ring-0 stack segment. (static) */
2821	RTSEL ss0;
2822	uint16_t padding_ss0;
2823	/** Ring-1 stack pointer. (static) */
2824	uint32_t esp1;
2825	/** Ring-1 stack segment. (static) */
2826	RTSEL ss1;
2827	uint16_t padding_ss1;
2828	/** Ring-2 stack pointer. (static) */
2829	uint32_t esp2;
2830	/** Ring-2 stack segment. (static) */
2831	RTSEL ss2;
2832	uint16_t padding_ss2;
2833	/** Page directory for the task. (static) */
2834	uint32_t cr3;
2835	/** EIP before task switch. */
2836	uint32_t eip;
2837	/** EFLAGS before task switch. */
2838	uint32_t eflags;
2839	/** EAX before task switch. */
2840	uint32_t eax;
2841	/** ECX before task switch. */
2842	uint32_t ecx;
2843	/** EDX before task switch. */
2844	uint32_t edx;
2845	/** EBX before task switch. */
2846	uint32_t ebx;
2847	/** ESP before task switch. */
2848	uint32_t esp;
2849	/** EBP before task switch. */
2850	uint32_t ebp;
2851	/** ESI before task switch. */
2852	uint32_t esi;
2853	/** EDI before task switch. */
2854	uint32_t edi;
2855	/** ES before task switch. */
2856	RTSEL es;
2857	uint16_t padding_es;
2858	/** CS before task switch. */
2859	RTSEL cs;
2860	uint16_t padding_cs;
2861	/** SS before task switch. */
2862	RTSEL ss;
2863	uint16_t padding_ss;
2864	/** DS before task switch. */
2865	RTSEL ds;
2866	uint16_t padding_ds;
2867	/** FS before task switch. */
2868	RTSEL fs;
2869	uint16_t padding_fs;
2870	/** GS before task switch. */
2871	RTSEL gs;
2872	uint16_t padding_gs;
2873	/** LDTR before task switch. */
2874	RTSEL selLdt;
2875	uint16_t padding_ldt;
2876	/** Debug trap flag */
2877	uint16_t fDebugTrap;
2878	/** Offset relative to the TSS of the start of the I/O Bitmap
2879	* and the end of the interrupt redirection bitmap. */
2880	uint16_t offIoBitmap;
2881	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2882	uint8_t IntRedirBitmap[32];
2883	} X86TSS32;
2884	#pragma pack()
2885	/** Pointer to task segment. */
2886	typedef X86TSS32 *PX86TSS32;
2887	/** Pointer to const task segment. */
2888	typedef const X86TSS32 *PCX86TSS32;
2889
2890
2891	/**
2892	* 64-bit Task segment.
2893	*/
2894	#pragma pack(1)
2895	typedef struct X86TSS64
2896	{
2897	/** Reserved. */
2898	uint32_t u32Reserved;
2899	/** Ring-0 stack pointer. (static) */
2900	uint64_t rsp0;
2901	/** Ring-1 stack pointer. (static) */
2902	uint64_t rsp1;
2903	/** Ring-2 stack pointer. (static) */
2904	uint64_t rsp2;
2905	/** Reserved. */
2906	uint32_t u32Reserved2[2];
2907	/* IST */
2908	uint64_t ist1;
2909	uint64_t ist2;
2910	uint64_t ist3;
2911	uint64_t ist4;
2912	uint64_t ist5;
2913	uint64_t ist6;
2914	uint64_t ist7;
2915	/* Reserved. */
2916	uint16_t u16Reserved[5];
2917	/** Offset relative to the TSS of the start of the I/O Bitmap
2918	* and the end of the interrupt redirection bitmap. */
2919	uint16_t offIoBitmap;
2920	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2921	uint8_t IntRedirBitmap[32];
2922	} X86TSS64;
2923	#pragma pack()
2924	/** Pointer to a 64-bit task segment. */
2925	typedef X86TSS64 *PX86TSS64;
2926	/** Pointer to a const 64-bit task segment. */
2927	typedef const X86TSS64 *PCX86TSS64;
2928	#ifndef VBOX_FOR_DTRACE_LIB
2929	AssertCompileSize(X86TSS64, 136);
2930	#endif
2931
2932	/** @} */
2933
2934
2935	/** @name Selectors.
2936	* @{
2937	*/
2938
2939	/**
2940	* The shift used to convert a selector from and to index an index (C).
2941	*/
2942	#define X86_SEL_SHIFT 3
2943
2944	/**
2945	* The mask used to mask off the table indicator and CPL of an selector.
2946	*/
2947	#define X86_SEL_MASK 0xfff8U
2948
2949	/**
2950	* The bit indicating that a selector is in the LDT and not in the GDT.
2951	*/
2952	#define X86_SEL_LDT 0x0004U
2953	/**
2954	* The bit mask for getting the RPL of a selector.
2955	*/
2956	#define X86_SEL_RPL 0x0003U
2957
2958	/** @} */
2959
2960
2961	/**
2962	* x86 Exceptions/Faults/Traps.
2963	*/
2964	typedef enum X86XCPT
2965	{
2966	/** \#DE - Divide error. */
2967	X86_XCPT_DE = 0x00,
2968	/** \#DB - Debug event (single step, DRx, ..) */
2969	X86_XCPT_DB = 0x01,
2970	/** NMI - Non-Maskable Interrupt */
2971	X86_XCPT_NMI = 0x02,
2972	/** \#BP - Breakpoint (INT3). */
2973	X86_XCPT_BP = 0x03,
2974	/** \#OF - Overflow (INTO). */
2975	X86_XCPT_OF = 0x04,
2976	/** \#BR - Bound range exceeded (BOUND). */
2977	X86_XCPT_BR = 0x05,
2978	/** \#UD - Undefined opcode. */
2979	X86_XCPT_UD = 0x06,
2980	/** \#NM - Device not available (math coprocessor device). */
2981	X86_XCPT_NM = 0x07,
2982	/** \#DF - Double fault. */
2983	X86_XCPT_DF = 0x08,
2984	/** ??? - Coprocessor segment overrun (obsolete). */
2985	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2986	/** \#TS - Taskswitch (TSS). */
2987	X86_XCPT_TS = 0x0a,
2988	/** \#NP - Segment no present. */
2989	X86_XCPT_NP = 0x0b,
2990	/** \#SS - Stack segment fault. */
2991	X86_XCPT_SS = 0x0c,
2992	/** \#GP - General protection fault. */
2993	X86_XCPT_GP = 0x0d,
2994	/** \#PF - Page fault. */
2995	X86_XCPT_PF = 0x0e,
2996	/* 0x0f is reserved. */
2997	/** \#MF - Math fault (FPU). */
2998	X86_XCPT_MF = 0x10,
2999	/** \#AC - Alignment check. */
3000	X86_XCPT_AC = 0x11,
3001	/** \#MC - Machine check. */
3002	X86_XCPT_MC = 0x12,
3003	/** \#XF - SIMD Floating-Pointer Exception. */
3004	X86_XCPT_XF = 0x13
3005	} X86XCPT;
3006	/** Pointer to a x86 exception code. */
3007	typedef X86XCPT *PX86XCPT;
3008	/** Pointer to a const x86 exception code. */
3009	typedef const X86XCPT *PCX86XCPT;
3010
3011
3012	/** @name Trap Error Codes
3013	* @{
3014	*/
3015	/** External indicator. */
3016	#define X86_TRAP_ERR_EXTERNAL 1
3017	/** IDT indicator. */
3018	#define X86_TRAP_ERR_IDT 2
3019	/** Descriptor table indicator - If set LDT, if clear GDT. */
3020	#define X86_TRAP_ERR_TI 4
3021	/** Mask for getting the selector. */
3022	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3023	/** Shift for getting the selector table index (C type index). */
3024	#define X86_TRAP_ERR_SEL_SHIFT 3
3025	/** @} */
3026
3027
3028	/** @name \#PF Trap Error Codes
3029	* @{
3030	*/
3031	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3032	#define X86_TRAP_PF_P RT_BIT(0)
3033	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3034	#define X86_TRAP_PF_RW RT_BIT(1)
3035	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3036	#define X86_TRAP_PF_US RT_BIT(2)
3037	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3038	#define X86_TRAP_PF_RSVD RT_BIT(3)
3039	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3040	#define X86_TRAP_PF_ID RT_BIT(4)
3041	/** @} */
3042
3043	#pragma pack(1)
3044	/**
3045	* 32-bit IDTR/GDTR.
3046	*/
3047	typedef struct X86XDTR32
3048	{
3049	/** Size of the descriptor table. */
3050	uint16_t cb;
3051	/** Address of the descriptor table. */
3052	#ifndef VBOX_FOR_DTRACE_LIB
3053	uint32_t uAddr;
3054	#else
3055	uint16_t au16Addr[2];
3056	#endif
3057	} X86XDTR32, *PX86XDTR32;
3058	#pragma pack()
3059
3060	#pragma pack(1)
3061	/**
3062	* 64-bit IDTR/GDTR.
3063	*/
3064	typedef struct X86XDTR64
3065	{
3066	/** Size of the descriptor table. */
3067	uint16_t cb;
3068	/** Address of the descriptor table. */
3069	#ifndef VBOX_FOR_DTRACE_LIB
3070	uint64_t uAddr;
3071	#else
3072	uint16_t au16Addr[4];
3073	#endif
3074	} X86XDTR64, *PX86XDTR64;
3075	#pragma pack()
3076
3077
3078	/** @name ModR/M
3079	* @{ */
3080	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3081	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3082	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3083	#define X86_MODRM_REG_SHIFT 3
3084	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3085	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3086	#define X86_MODRM_MOD_SHIFT 6
3087	#ifndef VBOX_FOR_DTRACE_LIB
3088	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3089	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3090	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3091	#endif
3092	/** @} */
3093
3094	/** @name SIB
3095	* @{ */
3096	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3097	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3098	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3099	#define X86_SIB_INDEX_SHIFT 3
3100	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3101	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3102	#define X86_SIB_SCALE_SHIFT 6
3103	#ifndef VBOX_FOR_DTRACE_LIB
3104	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3105	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3106	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3107	#endif
3108	/** @} */
3109
3110	/** @name General register indexes
3111	* @{ */
3112	#define X86_GREG_xAX 0
3113	#define X86_GREG_xCX 1
3114	#define X86_GREG_xDX 2
3115	#define X86_GREG_xBX 3
3116	#define X86_GREG_xSP 4
3117	#define X86_GREG_xBP 5
3118	#define X86_GREG_xSI 6
3119	#define X86_GREG_xDI 7
3120	#define X86_GREG_x8 8
3121	#define X86_GREG_x9 9
3122	#define X86_GREG_x10 10
3123	#define X86_GREG_x11 11
3124	#define X86_GREG_x12 12
3125	#define X86_GREG_x13 13
3126	#define X86_GREG_x14 14
3127	#define X86_GREG_x15 15
3128	/** @} */
3129
3130	/** @name X86_SREG_XXX - Segment register indexes.
3131	* @{ */
3132	#define X86_SREG_ES 0
3133	#define X86_SREG_CS 1
3134	#define X86_SREG_SS 2
3135	#define X86_SREG_DS 3
3136	#define X86_SREG_FS 4
3137	#define X86_SREG_GS 5
3138	/** @} */
3139
3140
3141	/** @} */
3142
3143	#endif
3144

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source: vbox/trunk/include/iprt/x86.h@ 42117

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