VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 47406

Last change on this file since 47406 was 47406, checked in by vboxsync, 12 years ago

x86.h: Added MSXCR macros.
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2012 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT(0)
164/** Bit 1 - Reserved, reads as 1. */
165#define X86_EFL_1 RT_BIT(1)
166/** Bit 2 - PF - Parity flag - Status flag. */
167#define X86_EFL_PF RT_BIT(2)
168/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169#define X86_EFL_AF RT_BIT(4)
170/** Bit 6 - ZF - Zero flag - Status flag. */
171#define X86_EFL_ZF RT_BIT(6)
172/** Bit 7 - SF - Signed flag - Status flag. */
173#define X86_EFL_SF RT_BIT(7)
174/** Bit 8 - TF - Trap flag - System flag. */
175#define X86_EFL_TF RT_BIT(8)
176/** Bit 9 - IF - Interrupt flag - System flag. */
177#define X86_EFL_IF RT_BIT(9)
178/** Bit 10 - DF - Direction flag - Control flag. */
179#define X86_EFL_DF RT_BIT(10)
180/** Bit 11 - OF - Overflow flag - Status flag. */
181#define X86_EFL_OF RT_BIT(11)
182/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
184/** Bit 14 - NT - Nested task flag - System flag. */
185#define X86_EFL_NT RT_BIT(14)
186/** Bit 16 - RF - Resume flag - System flag. */
187#define X86_EFL_RF RT_BIT(16)
188/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189#define X86_EFL_VM RT_BIT(17)
190/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191#define X86_EFL_AC RT_BIT(18)
192/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193#define X86_EFL_VIF RT_BIT(19)
194/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195#define X86_EFL_VIP RT_BIT(20)
196/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197#define X86_EFL_ID RT_BIT(21)
198/** IOPL shift. */
199#define X86_EFL_IOPL_SHIFT 12
200/** The the IOPL level from the flags. */
201#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
202/** Bits restored by popf */
203#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
204 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
205/** @} */
206
207
208/** CPUID Feature information - ECX.
209 * CPUID query with EAX=1.
210 */
211#ifndef VBOX_FOR_DTRACE_LIB
212typedef struct X86CPUIDFEATECX
213{
214 /** Bit 0 - SSE3 - Supports SSE3 or not. */
215 unsigned u1SSE3 : 1;
216 /** Bit 1 - PCLMULQDQ. */
217 unsigned u1PCLMULQDQ : 1;
218 /** Bit 2 - DS Area 64-bit layout. */
219 unsigned u1DTE64 : 1;
220 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
221 unsigned u1Monitor : 1;
222 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
223 unsigned u1CPLDS : 1;
224 /** Bit 5 - VMX - Virtual Machine Technology. */
225 unsigned u1VMX : 1;
226 /** Bit 6 - SMX: Safer Mode Extensions. */
227 unsigned u1SMX : 1;
228 /** Bit 7 - EST - Enh. SpeedStep Tech. */
229 unsigned u1EST : 1;
230 /** Bit 8 - TM2 - Terminal Monitor 2. */
231 unsigned u1TM2 : 1;
232 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
233 unsigned u1SSSE3 : 1;
234 /** Bit 10 - CNTX-ID - L1 Context ID. */
235 unsigned u1CNTXID : 1;
236 /** Bit 11 - Reserved. */
237 unsigned u1Reserved1 : 1;
238 /** Bit 12 - FMA. */
239 unsigned u1FMA : 1;
240 /** Bit 13 - CX16 - CMPXCHG16B. */
241 unsigned u1CX16 : 1;
242 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
243 unsigned u1TPRUpdate : 1;
244 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
245 unsigned u1PDCM : 1;
246 /** Bit 16 - Reserved. */
247 unsigned u1Reserved2 : 1;
248 /** Bit 17 - PCID - Process-context identifiers. */
249 unsigned u1PCID : 1;
250 /** Bit 18 - Direct Cache Access. */
251 unsigned u1DCA : 1;
252 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
253 unsigned u1SSE4_1 : 1;
254 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
255 unsigned u1SSE4_2 : 1;
256 /** Bit 21 - x2APIC. */
257 unsigned u1x2APIC : 1;
258 /** Bit 22 - MOVBE - Supports MOVBE. */
259 unsigned u1MOVBE : 1;
260 /** Bit 23 - POPCNT - Supports POPCNT. */
261 unsigned u1POPCNT : 1;
262 /** Bit 24 - TSC-Deadline. */
263 unsigned u1TSCDEADLINE : 1;
264 /** Bit 25 - AES. */
265 unsigned u1AES : 1;
266 /** Bit 26 - XSAVE - Supports XSAVE. */
267 unsigned u1XSAVE : 1;
268 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
269 unsigned u1OSXSAVE : 1;
270 /** Bit 28 - AVX - Supports AVX instruction extensions. */
271 unsigned u1AVX : 1;
272 /** Bit 29 - 30 - Reserved */
273 unsigned u2Reserved3 : 2;
274 /** Bit 31 - Hypervisor present (we're a guest). */
275 unsigned u1HVP : 1;
276} X86CPUIDFEATECX;
277#else /* VBOX_FOR_DTRACE_LIB */
278typedef uint32_t X86CPUIDFEATECX;
279#endif /* VBOX_FOR_DTRACE_LIB */
280/** Pointer to CPUID Feature Information - ECX. */
281typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
282/** Pointer to const CPUID Feature Information - ECX. */
283typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
284
285
286/** CPUID Feature Information - EDX.
287 * CPUID query with EAX=1.
288 */
289#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
290typedef struct X86CPUIDFEATEDX
291{
292 /** Bit 0 - FPU - x87 FPU on Chip. */
293 unsigned u1FPU : 1;
294 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
295 unsigned u1VME : 1;
296 /** Bit 2 - DE - Debugging extensions. */
297 unsigned u1DE : 1;
298 /** Bit 3 - PSE - Page Size Extension. */
299 unsigned u1PSE : 1;
300 /** Bit 4 - TSC - Time Stamp Counter. */
301 unsigned u1TSC : 1;
302 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
303 unsigned u1MSR : 1;
304 /** Bit 6 - PAE - Physical Address Extension. */
305 unsigned u1PAE : 1;
306 /** Bit 7 - MCE - Machine Check Exception. */
307 unsigned u1MCE : 1;
308 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
309 unsigned u1CX8 : 1;
310 /** Bit 9 - APIC - APIC On-Chip. */
311 unsigned u1APIC : 1;
312 /** Bit 10 - Reserved. */
313 unsigned u1Reserved1 : 1;
314 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
315 unsigned u1SEP : 1;
316 /** Bit 12 - MTRR - Memory Type Range Registers. */
317 unsigned u1MTRR : 1;
318 /** Bit 13 - PGE - PTE Global Bit. */
319 unsigned u1PGE : 1;
320 /** Bit 14 - MCA - Machine Check Architecture. */
321 unsigned u1MCA : 1;
322 /** Bit 15 - CMOV - Conditional Move Instructions. */
323 unsigned u1CMOV : 1;
324 /** Bit 16 - PAT - Page Attribute Table. */
325 unsigned u1PAT : 1;
326 /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
327 unsigned u1PSE36 : 1;
328 /** Bit 18 - PSN - Processor Serial Number. */
329 unsigned u1PSN : 1;
330 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
331 unsigned u1CLFSH : 1;
332 /** Bit 20 - Reserved. */
333 unsigned u1Reserved2 : 1;
334 /** Bit 21 - DS - Debug Store. */
335 unsigned u1DS : 1;
336 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
337 unsigned u1ACPI : 1;
338 /** Bit 23 - MMX - Intel MMX 'Technology'. */
339 unsigned u1MMX : 1;
340 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
341 unsigned u1FXSR : 1;
342 /** Bit 25 - SSE - SSE Support. */
343 unsigned u1SSE : 1;
344 /** Bit 26 - SSE2 - SSE2 Support. */
345 unsigned u1SSE2 : 1;
346 /** Bit 27 - SS - Self Snoop. */
347 unsigned u1SS : 1;
348 /** Bit 28 - HTT - Hyper-Threading Technology. */
349 unsigned u1HTT : 1;
350 /** Bit 29 - TM - Thermal Monitor. */
351 unsigned u1TM : 1;
352 /** Bit 30 - Reserved - . */
353 unsigned u1Reserved3 : 1;
354 /** Bit 31 - PBE - Pending Break Enabled. */
355 unsigned u1PBE : 1;
356} X86CPUIDFEATEDX;
357#else /* VBOX_FOR_DTRACE_LIB */
358typedef uint32_t X86CPUIDFEATEDX;
359#endif /* VBOX_FOR_DTRACE_LIB */
360/** Pointer to CPUID Feature Information - EDX. */
361typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
362/** Pointer to const CPUID Feature Information - EDX. */
363typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
364
365/** @name CPUID Vendor information.
366 * CPUID query with EAX=0.
367 * @{
368 */
369#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
370#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
371#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
372
373#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
374#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
375#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
376
377#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
378#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
379#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
380/** @} */
381
382
383/** @name CPUID Feature information.
384 * CPUID query with EAX=1.
385 * @{
386 */
387/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
388#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
389/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
390#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
391/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
392#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
393/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
394#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
395/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
396#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
397/** ECX Bit 5 - VMX - Virtual Machine Technology. */
398#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
399/** ECX Bit 6 - SMX - Safer Mode Extensions. */
400#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
401/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
402#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
403/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
404#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
405/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
406#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
407/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
408#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
409/** ECX Bit 12 - FMA. */
410#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
411/** ECX Bit 13 - CX16 - CMPXCHG16B. */
412#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
413/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
414#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
415/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
416#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
417/** ECX Bit 17 - PCID - Process-context identifiers. */
418#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
419/** ECX Bit 18 - DCA - Direct Cache Access. */
420#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
421/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
422#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
423/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
424#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
425/** ECX Bit 21 - x2APIC support. */
426#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
427/** ECX Bit 22 - MOVBE instruction. */
428#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
429/** ECX Bit 23 - POPCNT instruction. */
430#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
431/** ECX Bir 24 - TSC-Deadline. */
432#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
433/** ECX Bit 25 - AES instructions. */
434#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
435/** ECX Bit 26 - XSAVE instruction. */
436#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
437/** ECX Bit 27 - OSXSAVE instruction. */
438#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
439/** ECX Bit 28 - AVX. */
440#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
441/** ECX Bit 31 - Hypervisor Present (software only). */
442#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
443
444
445/** Bit 0 - FPU - x87 FPU on Chip. */
446#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
447/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
448#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
449/** Bit 2 - DE - Debugging extensions. */
450#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
451/** Bit 3 - PSE - Page Size Extension. */
452#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
453/** Bit 4 - TSC - Time Stamp Counter. */
454#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
455/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
456#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
457/** Bit 6 - PAE - Physical Address Extension. */
458#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
459/** Bit 7 - MCE - Machine Check Exception. */
460#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
461/** Bit 8 - CX8 - CMPXCHG8B instruction. */
462#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
463/** Bit 9 - APIC - APIC On-Chip. */
464#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
465/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
466#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
467/** Bit 12 - MTRR - Memory Type Range Registers. */
468#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
469/** Bit 13 - PGE - PTE Global Bit. */
470#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
471/** Bit 14 - MCA - Machine Check Architecture. */
472#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
473/** Bit 15 - CMOV - Conditional Move Instructions. */
474#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
475/** Bit 16 - PAT - Page Attribute Table. */
476#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
477/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
478#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
479/** Bit 18 - PSN - Processor Serial Number. */
480#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
481/** Bit 19 - CLFSH - CLFLUSH Instruction. */
482#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
483/** Bit 21 - DS - Debug Store. */
484#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
485/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
486#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
487/** Bit 23 - MMX - Intel MMX Technology. */
488#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
489/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
490#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
491/** Bit 25 - SSE - SSE Support. */
492#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
493/** Bit 26 - SSE2 - SSE2 Support. */
494#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
495/** Bit 27 - SS - Self Snoop. */
496#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
497/** Bit 28 - HTT - Hyper-Threading Technology. */
498#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
499/** Bit 29 - TM - Therm. Monitor. */
500#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
501/** Bit 31 - PBE - Pending Break Enabled. */
502#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
503/** @} */
504
505/** @name CPUID mwait/monitor information.
506 * CPUID query with EAX=5.
507 * @{
508 */
509/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
510#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
511/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
512#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
513/** @} */
514
515
516/** @name CPUID Extended Feature information.
517 * CPUID query with EAX=0x80000001.
518 * @{
519 */
520/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
521#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
522
523/** EDX Bit 11 - SYSCALL/SYSRET. */
524#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
525/** EDX Bit 20 - No-Execute/Execute-Disable. */
526#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
527/** EDX Bit 26 - 1 GB large page. */
528#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
529/** EDX Bit 27 - RDTSCP. */
530#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
531/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
532#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
533/** @}*/
534
535/** @name CPUID AMD Feature information.
536 * CPUID query with EAX=0x80000001.
537 * @{
538 */
539/** Bit 0 - FPU - x87 FPU on Chip. */
540#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
541/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
542#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
543/** Bit 2 - DE - Debugging extensions. */
544#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
545/** Bit 3 - PSE - Page Size Extension. */
546#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
547/** Bit 4 - TSC - Time Stamp Counter. */
548#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
549/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
550#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
551/** Bit 6 - PAE - Physical Address Extension. */
552#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
553/** Bit 7 - MCE - Machine Check Exception. */
554#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
555/** Bit 8 - CX8 - CMPXCHG8B instruction. */
556#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
557/** Bit 9 - APIC - APIC On-Chip. */
558#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
559/** Bit 12 - MTRR - Memory Type Range Registers. */
560#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
561/** Bit 13 - PGE - PTE Global Bit. */
562#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
563/** Bit 14 - MCA - Machine Check Architecture. */
564#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
565/** Bit 15 - CMOV - Conditional Move Instructions. */
566#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
567/** Bit 16 - PAT - Page Attribute Table. */
568#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
569/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
570#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
571/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
572#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
573/** Bit 23 - MMX - Intel MMX Technology. */
574#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
575/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
576#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
577/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
578#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
579/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
580#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
581/** Bit 31 - 3DNOW - AMD 3DNow. */
582#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
583
584/** Bit 1 - CMPL - Core multi-processing legacy mode. */
585#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
586/** Bit 2 - SVM - AMD VM extensions. */
587#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
588/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
589#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
590/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
591#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
592/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
593#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
594/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
595#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
596/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
597#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
598/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
599#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
600/** Bit 9 - OSVW - AMD OS visible workaround. */
601#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
602/** Bit 10 - IBS - Instruct based sampling. */
603#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
604/** Bit 11 - SSE5 - SSE5 instruction support. */
605#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
606/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
607#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
608/** Bit 13 - WDT - AMD Watchdog timer support. */
609#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
610
611/** @} */
612
613
614/** @name CPUID AMD Feature information.
615 * CPUID query with EAX=0x80000007.
616 * @{
617 */
618/** Bit 0 - TS - Temperature Sensor. */
619#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
620/** Bit 1 - FID - Frequency ID Control. */
621#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
622/** Bit 2 - VID - Voltage ID Control. */
623#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
624/** Bit 3 - TTP - THERMTRIP. */
625#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
626/** Bit 4 - TM - Hardware Thermal Control. */
627#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
628/** Bit 5 - STC - Software Thermal Control. */
629#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
630/** Bit 6 - MC - 100 Mhz Multiplier Control. */
631#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
632/** Bit 7 - HWPSTATE - Hardware P-State Control. */
633#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
634/** Bit 8 - TSCINVAR - TSC Invariant. */
635#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
636/** @} */
637
638
639/** @name CR0
640 * @{ */
641/** Bit 0 - PE - Protection Enabled */
642#define X86_CR0_PE RT_BIT(0)
643#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
644/** Bit 1 - MP - Monitor Coprocessor */
645#define X86_CR0_MP RT_BIT(1)
646#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
647/** Bit 2 - EM - Emulation. */
648#define X86_CR0_EM RT_BIT(2)
649#define X86_CR0_EMULATE_FPU RT_BIT(2)
650/** Bit 3 - TS - Task Switch. */
651#define X86_CR0_TS RT_BIT(3)
652#define X86_CR0_TASK_SWITCH RT_BIT(3)
653/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
654#define X86_CR0_ET RT_BIT(4)
655#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
656/** Bit 5 - NE - Numeric error. */
657#define X86_CR0_NE RT_BIT(5)
658#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
659/** Bit 16 - WP - Write Protect. */
660#define X86_CR0_WP RT_BIT(16)
661#define X86_CR0_WRITE_PROTECT RT_BIT(16)
662/** Bit 18 - AM - Alignment Mask. */
663#define X86_CR0_AM RT_BIT(18)
664#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
665/** Bit 29 - NW - Not Write-though. */
666#define X86_CR0_NW RT_BIT(29)
667#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
668/** Bit 30 - WP - Cache Disable. */
669#define X86_CR0_CD RT_BIT(30)
670#define X86_CR0_CACHE_DISABLE RT_BIT(30)
671/** Bit 31 - PG - Paging. */
672#define X86_CR0_PG RT_BIT(31)
673#define X86_CR0_PAGING RT_BIT(31)
674/** @} */
675
676
677/** @name CR3
678 * @{ */
679/** Bit 3 - PWT - Page-level Writes Transparent. */
680#define X86_CR3_PWT RT_BIT(3)
681/** Bit 4 - PCD - Page-level Cache Disable. */
682#define X86_CR3_PCD RT_BIT(4)
683/** Bits 12-31 - - Page directory page number. */
684#define X86_CR3_PAGE_MASK (0xfffff000)
685/** Bits 5-31 - - PAE Page directory page number. */
686#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
687/** Bits 12-51 - - AMD64 Page directory page number. */
688#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
689/** @} */
690
691
692/** @name CR4
693 * @{ */
694/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
695#define X86_CR4_VME RT_BIT(0)
696/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
697#define X86_CR4_PVI RT_BIT(1)
698/** Bit 2 - TSD - Time Stamp Disable. */
699#define X86_CR4_TSD RT_BIT(2)
700/** Bit 3 - DE - Debugging Extensions. */
701#define X86_CR4_DE RT_BIT(3)
702/** Bit 4 - PSE - Page Size Extension. */
703#define X86_CR4_PSE RT_BIT(4)
704/** Bit 5 - PAE - Physical Address Extension. */
705#define X86_CR4_PAE RT_BIT(5)
706/** Bit 6 - MCE - Machine-Check Enable. */
707#define X86_CR4_MCE RT_BIT(6)
708/** Bit 7 - PGE - Page Global Enable. */
709#define X86_CR4_PGE RT_BIT(7)
710/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
711#define X86_CR4_PCE RT_BIT(8)
712/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
713#define X86_CR4_OSFSXR RT_BIT(9)
714/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
715#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
716/** Bit 13 - VMXE - VMX mode is enabled. */
717#define X86_CR4_VMXE RT_BIT(13)
718/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
719#define X86_CR4_SMXE RT_BIT(14)
720/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
721#define X86_CR4_PCIDE RT_BIT(17)
722/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
723 * extended states. */
724#define X86_CR4_OSXSAVE RT_BIT(18)
725/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
726#define X86_CR4_SMEP RT_BIT(20)
727/** @} */
728
729
730/** @name DR6
731 * @{ */
732/** Bit 0 - B0 - Breakpoint 0 condition detected. */
733#define X86_DR6_B0 RT_BIT(0)
734/** Bit 1 - B1 - Breakpoint 1 condition detected. */
735#define X86_DR6_B1 RT_BIT(1)
736/** Bit 2 - B2 - Breakpoint 2 condition detected. */
737#define X86_DR6_B2 RT_BIT(2)
738/** Bit 3 - B3 - Breakpoint 3 condition detected. */
739#define X86_DR6_B3 RT_BIT(3)
740/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
741#define X86_DR6_BD RT_BIT(13)
742/** Bit 14 - BS - Single step */
743#define X86_DR6_BS RT_BIT(14)
744/** Bit 15 - BT - Task switch. (TSS T bit.) */
745#define X86_DR6_BT RT_BIT(15)
746/** Value of DR6 after powerup/reset. */
747#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
748/** Bits which must be 1s in DR6. */
749#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
750/** Bits which must be 0s in DR6. */
751#define X86_DR6_RAZ_MASK RT_BIT_64(12)
752/** Bits which must be 0s on writes to DR6. */
753#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
754/** @} */
755
756
757/** @name DR7
758 * @{ */
759/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
760#define X86_DR7_L0 RT_BIT(0)
761/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
762#define X86_DR7_G0 RT_BIT(1)
763/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
764#define X86_DR7_L1 RT_BIT(2)
765/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
766#define X86_DR7_G1 RT_BIT(3)
767/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
768#define X86_DR7_L2 RT_BIT(4)
769/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
770#define X86_DR7_G2 RT_BIT(5)
771/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
772#define X86_DR7_L3 RT_BIT(6)
773/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
774#define X86_DR7_G3 RT_BIT(7)
775/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
776#define X86_DR7_LE RT_BIT(8)
777/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
778#define X86_DR7_GE RT_BIT(9)
779
780/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
781 * any DR register is accessed. */
782#define X86_DR7_GD RT_BIT(13)
783/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
784#define X86_DR7_RW0_MASK (3 << 16)
785/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
786#define X86_DR7_LEN0_MASK (3 << 18)
787/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
788#define X86_DR7_RW1_MASK (3 << 20)
789/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
790#define X86_DR7_LEN1_MASK (3 << 22)
791/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
792#define X86_DR7_RW2_MASK (3 << 24)
793/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
794#define X86_DR7_LEN2_MASK (3 << 26)
795/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
796#define X86_DR7_RW3_MASK (3 << 28)
797/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
798#define X86_DR7_LEN3_MASK (3 << 30)
799
800/** Bits which reads as 1s. */
801#define X86_DR7_RA1_MASK (RT_BIT(10))
802/** Bits which reads as zeros. */
803#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
804/** Bits which must be 0s when writing to DR7. */
805#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
806
807/** Calcs the L bit of Nth breakpoint.
808 * @param iBp The breakpoint number [0..3].
809 */
810#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
811
812/** Calcs the G bit of Nth breakpoint.
813 * @param iBp The breakpoint number [0..3].
814 */
815#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
816
817/** @name Read/Write values.
818 * @{ */
819/** Break on instruction fetch only. */
820#define X86_DR7_RW_EO 0U
821/** Break on write only. */
822#define X86_DR7_RW_WO 1U
823/** Break on I/O read/write. This is only defined if CR4.DE is set. */
824#define X86_DR7_RW_IO 2U
825/** Break on read or write (but not instruction fetches). */
826#define X86_DR7_RW_RW 3U
827/** @} */
828
829/** Shifts a X86_DR7_RW_* value to its right place.
830 * @param iBp The breakpoint number [0..3].
831 * @param fRw One of the X86_DR7_RW_* value.
832 */
833#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
834
835/** @name Length values.
836 * @{ */
837#define X86_DR7_LEN_BYTE 0U
838#define X86_DR7_LEN_WORD 1U
839#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
840#define X86_DR7_LEN_DWORD 3U
841/** @} */
842
843/** Shifts a X86_DR7_LEN_* value to its right place.
844 * @param iBp The breakpoint number [0..3].
845 * @param cb One of the X86_DR7_LEN_* values.
846 */
847#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
848
849/** Fetch the breakpoint length bits from the DR7 value.
850 * @param uDR7 DR7 value
851 * @param iBp The breakpoint number [0..3].
852 */
853#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
854
855/** Mask used to check if any breakpoints are enabled. */
856#define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
857
858/** Mask used to check if any io breakpoints are set. */
859#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
860
861/** Value of DR7 after powerup/reset. */
862#define X86_DR7_INIT_VAL 0x400
863/** @} */
864
865
866/** @name Machine Specific Registers
867 * @{
868 */
869
870/** Time Stamp Counter. */
871#define MSR_IA32_TSC 0x10
872
873#define MSR_IA32_PLATFORM_ID 0x17
874
875#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
876#define MSR_IA32_APICBASE 0x1b
877#endif
878
879/** CPU Feature control. */
880#define MSR_IA32_FEATURE_CONTROL 0x3A
881#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
882#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
883
884/** BIOS update trigger (microcode update). */
885#define MSR_IA32_BIOS_UPDT_TRIG 0x79
886
887/** BIOS update signature (microcode). */
888#define MSR_IA32_BIOS_SIGN_ID 0x8B
889
890/** General performance counter no. 0. */
891#define MSR_IA32_PMC0 0xC1
892/** General performance counter no. 1. */
893#define MSR_IA32_PMC1 0xC2
894/** General performance counter no. 2. */
895#define MSR_IA32_PMC2 0xC3
896/** General performance counter no. 3. */
897#define MSR_IA32_PMC3 0xC4
898
899/** Nehalem power control. */
900#define MSR_IA32_PLATFORM_INFO 0xCE
901
902/** Get FSB clock status (Intel-specific). */
903#define MSR_IA32_FSB_CLOCK_STS 0xCD
904
905/** MTRR Capabilities. */
906#define MSR_IA32_MTRR_CAP 0xFE
907
908
909#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
910/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
911 * R0 SS == CS + 8
912 * R3 CS == CS + 16
913 * R3 SS == CS + 24
914 */
915#define MSR_IA32_SYSENTER_CS 0x174
916/** SYSENTER_ESP - the R0 ESP. */
917#define MSR_IA32_SYSENTER_ESP 0x175
918/** SYSENTER_EIP - the R0 EIP. */
919#define MSR_IA32_SYSENTER_EIP 0x176
920#endif
921
922/** Machine Check Global Capabilities Register. */
923#define MSR_IA32_MCP_CAP 0x179
924/** Machine Check Global Status Register. */
925#define MSR_IA32_MCP_STATUS 0x17A
926/** Machine Check Global Control Register. */
927#define MSR_IA32_MCP_CTRL 0x17B
928
929/** Trace/Profile Resource Control (R/W) */
930#define MSR_IA32_DEBUGCTL 0x1D9
931
932/** Page Attribute Table. */
933#define MSR_IA32_CR_PAT 0x277
934
935/** Performance counter MSRs. (Intel only) */
936#define MSR_IA32_PERFEVTSEL0 0x186
937#define MSR_IA32_PERFEVTSEL1 0x187
938#define MSR_IA32_FLEX_RATIO 0x194
939#define MSR_IA32_PERF_STATUS 0x198
940#define MSR_IA32_PERF_CTL 0x199
941#define MSR_IA32_THERM_STATUS 0x19c
942
943/** Enable misc. processor features (R/W). */
944#define MSR_IA32_MISC_ENABLE 0x1A0
945/** Enable fast-strings feature (for REP MOVS and REP STORS). */
946#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
947/** Automatic Thermal Control Circuit Enable (R/W). */
948#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
949/** Performance Monitoring Available (R). */
950#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
951/** Branch Trace Storage Unavailable (R/O). */
952#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
953/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
954#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
955/** Enhanced Intel SpeedStep Technology Enable (R/W). */
956#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
957/** If MONITOR/MWAIT is supported (R/W). */
958#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
959/** Limit CPUID Maxval to 3 leafs (R/W). */
960#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
961/** When set to 1, xTPR messages are disabled (R/W). */
962#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
963/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
964#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
965
966#define IA32_MTRR_PHYSBASE0 0x200
967#define IA32_MTRR_PHYSMASK0 0x201
968#define IA32_MTRR_PHYSBASE1 0x202
969#define IA32_MTRR_PHYSMASK1 0x203
970#define IA32_MTRR_PHYSBASE2 0x204
971#define IA32_MTRR_PHYSMASK2 0x205
972#define IA32_MTRR_PHYSBASE3 0x206
973#define IA32_MTRR_PHYSMASK3 0x207
974#define IA32_MTRR_PHYSBASE4 0x208
975#define IA32_MTRR_PHYSMASK4 0x209
976#define IA32_MTRR_PHYSBASE5 0x20a
977#define IA32_MTRR_PHYSMASK5 0x20b
978#define IA32_MTRR_PHYSBASE6 0x20c
979#define IA32_MTRR_PHYSMASK6 0x20d
980#define IA32_MTRR_PHYSBASE7 0x20e
981#define IA32_MTRR_PHYSMASK7 0x20f
982#define IA32_MTRR_PHYSBASE8 0x210
983#define IA32_MTRR_PHYSMASK8 0x211
984#define IA32_MTRR_PHYSBASE9 0x212
985#define IA32_MTRR_PHYSMASK9 0x213
986
987/** Fixed range MTRRs.
988 * @{ */
989#define IA32_MTRR_FIX64K_00000 0x250
990#define IA32_MTRR_FIX16K_80000 0x258
991#define IA32_MTRR_FIX16K_A0000 0x259
992#define IA32_MTRR_FIX4K_C0000 0x268
993#define IA32_MTRR_FIX4K_C8000 0x269
994#define IA32_MTRR_FIX4K_D0000 0x26a
995#define IA32_MTRR_FIX4K_D8000 0x26b
996#define IA32_MTRR_FIX4K_E0000 0x26c
997#define IA32_MTRR_FIX4K_E8000 0x26d
998#define IA32_MTRR_FIX4K_F0000 0x26e
999#define IA32_MTRR_FIX4K_F8000 0x26f
1000/** @} */
1001
1002/** MTRR Default Range. */
1003#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1004
1005#define MSR_IA32_MC0_CTL 0x400
1006#define MSR_IA32_MC0_STATUS 0x401
1007
1008/** Basic VMX information. */
1009#define MSR_IA32_VMX_BASIC_INFO 0x480
1010/** Allowed settings for pin-based VM execution controls */
1011#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1012/** Allowed settings for proc-based VM execution controls */
1013#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1014/** Allowed settings for the VMX exit controls. */
1015#define MSR_IA32_VMX_EXIT_CTLS 0x483
1016/** Allowed settings for the VMX entry controls. */
1017#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1018/** Misc VMX info. */
1019#define MSR_IA32_VMX_MISC 0x485
1020/** Fixed cleared bits in CR0. */
1021#define MSR_IA32_VMX_CR0_FIXED0 0x486
1022/** Fixed set bits in CR0. */
1023#define MSR_IA32_VMX_CR0_FIXED1 0x487
1024/** Fixed cleared bits in CR4. */
1025#define MSR_IA32_VMX_CR4_FIXED0 0x488
1026/** Fixed set bits in CR4. */
1027#define MSR_IA32_VMX_CR4_FIXED1 0x489
1028/** Information for enumerating fields in the VMCS. */
1029#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1030/** Allowed settings for the VM-functions controls. */
1031#define MSR_IA32_VMX_VMFUNC 0x491
1032/** Allowed settings for secondary proc-based VM execution controls */
1033#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1034/** EPT capabilities. */
1035#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1036/** DS Save Area (R/W). */
1037#define MSR_IA32_DS_AREA 0x600
1038/** X2APIC MSR ranges. */
1039#define MSR_IA32_X2APIC_START 0x800
1040#define MSR_IA32_X2APIC_TPR 0x808
1041#define MSR_IA32_X2APIC_END 0xBFF
1042
1043/** K6 EFER - Extended Feature Enable Register. */
1044#define MSR_K6_EFER 0xc0000080
1045/** @todo document EFER */
1046/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1047#define MSR_K6_EFER_SCE RT_BIT(0)
1048/** Bit 8 - LME - Long mode enabled. (R/W) */
1049#define MSR_K6_EFER_LME RT_BIT(8)
1050/** Bit 10 - LMA - Long mode active. (R) */
1051#define MSR_K6_EFER_LMA RT_BIT(10)
1052/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1053#define MSR_K6_EFER_NXE RT_BIT(11)
1054/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1055#define MSR_K6_EFER_SVME RT_BIT(12)
1056/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1057#define MSR_K6_EFER_LMSLE RT_BIT(13)
1058/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1059#define MSR_K6_EFER_FFXSR RT_BIT(14)
1060/** K6 STAR - SYSCALL/RET targets. */
1061#define MSR_K6_STAR 0xc0000081
1062/** Shift value for getting the SYSRET CS and SS value. */
1063#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1064/** Shift value for getting the SYSCALL CS and SS value. */
1065#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1066/** Selector mask for use after shifting. */
1067#define MSR_K6_STAR_SEL_MASK 0xffff
1068/** The mask which give the SYSCALL EIP. */
1069#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1070/** K6 WHCR - Write Handling Control Register. */
1071#define MSR_K6_WHCR 0xc0000082
1072/** K6 UWCCR - UC/WC Cacheability Control Register. */
1073#define MSR_K6_UWCCR 0xc0000085
1074/** K6 PSOR - Processor State Observability Register. */
1075#define MSR_K6_PSOR 0xc0000087
1076/** K6 PFIR - Page Flush/Invalidate Register. */
1077#define MSR_K6_PFIR 0xc0000088
1078
1079/** Performance counter MSRs. (AMD only) */
1080#define MSR_K7_EVNTSEL0 0xc0010000
1081#define MSR_K7_EVNTSEL1 0xc0010001
1082#define MSR_K7_EVNTSEL2 0xc0010002
1083#define MSR_K7_EVNTSEL3 0xc0010003
1084#define MSR_K7_PERFCTR0 0xc0010004
1085#define MSR_K7_PERFCTR1 0xc0010005
1086#define MSR_K7_PERFCTR2 0xc0010006
1087#define MSR_K7_PERFCTR3 0xc0010007
1088
1089/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1090#define MSR_K8_LSTAR 0xc0000082
1091/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1092#define MSR_K8_CSTAR 0xc0000083
1093/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1094#define MSR_K8_SF_MASK 0xc0000084
1095/** K8 FS.base - The 64-bit base FS register. */
1096#define MSR_K8_FS_BASE 0xc0000100
1097/** K8 GS.base - The 64-bit base GS register. */
1098#define MSR_K8_GS_BASE 0xc0000101
1099/** K8 KernelGSbase - Used with SWAPGS. */
1100#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1101/** K8 TSC_AUX - Used with RDTSCP. */
1102#define MSR_K8_TSC_AUX 0xc0000103
1103#define MSR_K8_SYSCFG 0xc0010010
1104#define MSR_K8_HWCR 0xc0010015
1105#define MSR_K8_IORRBASE0 0xc0010016
1106#define MSR_K8_IORRMASK0 0xc0010017
1107#define MSR_K8_IORRBASE1 0xc0010018
1108#define MSR_K8_IORRMASK1 0xc0010019
1109#define MSR_K8_TOP_MEM1 0xc001001a
1110#define MSR_K8_TOP_MEM2 0xc001001d
1111#define MSR_K8_VM_CR 0xc0010114
1112#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1113
1114#define MSR_K8_IGNNE 0xc0010115
1115#define MSR_K8_SMM_CTL 0xc0010116
1116/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1117 * host state during world switch.
1118 */
1119#define MSR_K8_VM_HSAVE_PA 0xc0010117
1120
1121/** @} */
1122
1123
1124/** @name Page Table / Directory / Directory Pointers / L4.
1125 * @{
1126 */
1127
1128/** Page table/directory entry as an unsigned integer. */
1129typedef uint32_t X86PGUINT;
1130/** Pointer to a page table/directory table entry as an unsigned integer. */
1131typedef X86PGUINT *PX86PGUINT;
1132/** Pointer to an const page table/directory table entry as an unsigned integer. */
1133typedef X86PGUINT const *PCX86PGUINT;
1134
1135/** Number of entries in a 32-bit PT/PD. */
1136#define X86_PG_ENTRIES 1024
1137
1138
1139/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1140typedef uint64_t X86PGPAEUINT;
1141/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1142typedef X86PGPAEUINT *PX86PGPAEUINT;
1143/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1144typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1145
1146/** Number of entries in a PAE PT/PD. */
1147#define X86_PG_PAE_ENTRIES 512
1148/** Number of entries in a PAE PDPT. */
1149#define X86_PG_PAE_PDPE_ENTRIES 4
1150
1151/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1152#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1153/** Number of entries in an AMD64 PDPT.
1154 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1155#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1156
1157/** The size of a 4KB page. */
1158#define X86_PAGE_4K_SIZE _4K
1159/** The page shift of a 4KB page. */
1160#define X86_PAGE_4K_SHIFT 12
1161/** The 4KB page offset mask. */
1162#define X86_PAGE_4K_OFFSET_MASK 0xfff
1163/** The 4KB page base mask for virtual addresses. */
1164#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1165/** The 4KB page base mask for virtual addresses - 32bit version. */
1166#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1167
1168/** The size of a 2MB page. */
1169#define X86_PAGE_2M_SIZE _2M
1170/** The page shift of a 2MB page. */
1171#define X86_PAGE_2M_SHIFT 21
1172/** The 2MB page offset mask. */
1173#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1174/** The 2MB page base mask for virtual addresses. */
1175#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1176/** The 2MB page base mask for virtual addresses - 32bit version. */
1177#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1178
1179/** The size of a 4MB page. */
1180#define X86_PAGE_4M_SIZE _4M
1181/** The page shift of a 4MB page. */
1182#define X86_PAGE_4M_SHIFT 22
1183/** The 4MB page offset mask. */
1184#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1185/** The 4MB page base mask for virtual addresses. */
1186#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1187/** The 4MB page base mask for virtual addresses - 32bit version. */
1188#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1189
1190
1191
1192/** @name Page Table Entry
1193 * @{
1194 */
1195/** Bit 0 - P - Present bit. */
1196#define X86_PTE_BIT_P 0
1197/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1198#define X86_PTE_BIT_RW 1
1199/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1200#define X86_PTE_BIT_US 2
1201/** Bit 3 - PWT - Page level write thru bit. */
1202#define X86_PTE_BIT_PWT 3
1203/** Bit 4 - PCD - Page level cache disable bit. */
1204#define X86_PTE_BIT_PCD 4
1205/** Bit 5 - A - Access bit. */
1206#define X86_PTE_BIT_A 5
1207/** Bit 6 - D - Dirty bit. */
1208#define X86_PTE_BIT_D 6
1209/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1210#define X86_PTE_BIT_PAT 7
1211/** Bit 8 - G - Global flag. */
1212#define X86_PTE_BIT_G 8
1213
1214/** Bit 0 - P - Present bit mask. */
1215#define X86_PTE_P RT_BIT(0)
1216/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1217#define X86_PTE_RW RT_BIT(1)
1218/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1219#define X86_PTE_US RT_BIT(2)
1220/** Bit 3 - PWT - Page level write thru bit mask. */
1221#define X86_PTE_PWT RT_BIT(3)
1222/** Bit 4 - PCD - Page level cache disable bit mask. */
1223#define X86_PTE_PCD RT_BIT(4)
1224/** Bit 5 - A - Access bit mask. */
1225#define X86_PTE_A RT_BIT(5)
1226/** Bit 6 - D - Dirty bit mask. */
1227#define X86_PTE_D RT_BIT(6)
1228/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1229#define X86_PTE_PAT RT_BIT(7)
1230/** Bit 8 - G - Global bit mask. */
1231#define X86_PTE_G RT_BIT(8)
1232
1233/** Bits 9-11 - - Available for use to system software. */
1234#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1235/** Bits 12-31 - - Physical Page number of the next level. */
1236#define X86_PTE_PG_MASK ( 0xfffff000 )
1237
1238/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1239#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1240/** Bits 63 - NX - PAE/LM - No execution flag. */
1241#define X86_PTE_PAE_NX RT_BIT_64(63)
1242/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1243#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1244/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1245#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1246/** No bits - - LM - MBZ bits when NX is active. */
1247#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1248/** Bits 63 - - LM - MBZ bits when no NX. */
1249#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1250
1251/**
1252 * Page table entry.
1253 */
1254typedef struct X86PTEBITS
1255{
1256 /** Flags whether(=1) or not the page is present. */
1257 unsigned u1Present : 1;
1258 /** Read(=0) / Write(=1) flag. */
1259 unsigned u1Write : 1;
1260 /** User(=1) / Supervisor (=0) flag. */
1261 unsigned u1User : 1;
1262 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1263 unsigned u1WriteThru : 1;
1264 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1265 unsigned u1CacheDisable : 1;
1266 /** Accessed flag.
1267 * Indicates that the page have been read or written to. */
1268 unsigned u1Accessed : 1;
1269 /** Dirty flag.
1270 * Indicates that the page has been written to. */
1271 unsigned u1Dirty : 1;
1272 /** Reserved / If PAT enabled, bit 2 of the index. */
1273 unsigned u1PAT : 1;
1274 /** Global flag. (Ignored in all but final level.) */
1275 unsigned u1Global : 1;
1276 /** Available for use to system software. */
1277 unsigned u3Available : 3;
1278 /** Physical Page number of the next level. */
1279 unsigned u20PageNo : 20;
1280} X86PTEBITS;
1281/** Pointer to a page table entry. */
1282typedef X86PTEBITS *PX86PTEBITS;
1283/** Pointer to a const page table entry. */
1284typedef const X86PTEBITS *PCX86PTEBITS;
1285
1286/**
1287 * Page table entry.
1288 */
1289typedef union X86PTE
1290{
1291 /** Unsigned integer view */
1292 X86PGUINT u;
1293 /** Bit field view. */
1294 X86PTEBITS n;
1295 /** 32-bit view. */
1296 uint32_t au32[1];
1297 /** 16-bit view. */
1298 uint16_t au16[2];
1299 /** 8-bit view. */
1300 uint8_t au8[4];
1301} X86PTE;
1302/** Pointer to a page table entry. */
1303typedef X86PTE *PX86PTE;
1304/** Pointer to a const page table entry. */
1305typedef const X86PTE *PCX86PTE;
1306
1307
1308/**
1309 * PAE page table entry.
1310 */
1311typedef struct X86PTEPAEBITS
1312{
1313 /** Flags whether(=1) or not the page is present. */
1314 uint32_t u1Present : 1;
1315 /** Read(=0) / Write(=1) flag. */
1316 uint32_t u1Write : 1;
1317 /** User(=1) / Supervisor(=0) flag. */
1318 uint32_t u1User : 1;
1319 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1320 uint32_t u1WriteThru : 1;
1321 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1322 uint32_t u1CacheDisable : 1;
1323 /** Accessed flag.
1324 * Indicates that the page have been read or written to. */
1325 uint32_t u1Accessed : 1;
1326 /** Dirty flag.
1327 * Indicates that the page has been written to. */
1328 uint32_t u1Dirty : 1;
1329 /** Reserved / If PAT enabled, bit 2 of the index. */
1330 uint32_t u1PAT : 1;
1331 /** Global flag. (Ignored in all but final level.) */
1332 uint32_t u1Global : 1;
1333 /** Available for use to system software. */
1334 uint32_t u3Available : 3;
1335 /** Physical Page number of the next level - Low Part. Don't use this. */
1336 uint32_t u20PageNoLow : 20;
1337 /** Physical Page number of the next level - High Part. Don't use this. */
1338 uint32_t u20PageNoHigh : 20;
1339 /** MBZ bits */
1340 uint32_t u11Reserved : 11;
1341 /** No Execute flag. */
1342 uint32_t u1NoExecute : 1;
1343} X86PTEPAEBITS;
1344/** Pointer to a page table entry. */
1345typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1346/** Pointer to a page table entry. */
1347typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1348
1349/**
1350 * PAE Page table entry.
1351 */
1352typedef union X86PTEPAE
1353{
1354 /** Unsigned integer view */
1355 X86PGPAEUINT u;
1356 /** Bit field view. */
1357 X86PTEPAEBITS n;
1358 /** 32-bit view. */
1359 uint32_t au32[2];
1360 /** 16-bit view. */
1361 uint16_t au16[4];
1362 /** 8-bit view. */
1363 uint8_t au8[8];
1364} X86PTEPAE;
1365/** Pointer to a PAE page table entry. */
1366typedef X86PTEPAE *PX86PTEPAE;
1367/** Pointer to a const PAE page table entry. */
1368typedef const X86PTEPAE *PCX86PTEPAE;
1369/** @} */
1370
1371/**
1372 * Page table.
1373 */
1374typedef struct X86PT
1375{
1376 /** PTE Array. */
1377 X86PTE a[X86_PG_ENTRIES];
1378} X86PT;
1379/** Pointer to a page table. */
1380typedef X86PT *PX86PT;
1381/** Pointer to a const page table. */
1382typedef const X86PT *PCX86PT;
1383
1384/** The page shift to get the PT index. */
1385#define X86_PT_SHIFT 12
1386/** The PT index mask (apply to a shifted page address). */
1387#define X86_PT_MASK 0x3ff
1388
1389
1390/**
1391 * Page directory.
1392 */
1393typedef struct X86PTPAE
1394{
1395 /** PTE Array. */
1396 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1397} X86PTPAE;
1398/** Pointer to a page table. */
1399typedef X86PTPAE *PX86PTPAE;
1400/** Pointer to a const page table. */
1401typedef const X86PTPAE *PCX86PTPAE;
1402
1403/** The page shift to get the PA PTE index. */
1404#define X86_PT_PAE_SHIFT 12
1405/** The PAE PT index mask (apply to a shifted page address). */
1406#define X86_PT_PAE_MASK 0x1ff
1407
1408
1409/** @name 4KB Page Directory Entry
1410 * @{
1411 */
1412/** Bit 0 - P - Present bit. */
1413#define X86_PDE_P RT_BIT(0)
1414/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1415#define X86_PDE_RW RT_BIT(1)
1416/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1417#define X86_PDE_US RT_BIT(2)
1418/** Bit 3 - PWT - Page level write thru bit. */
1419#define X86_PDE_PWT RT_BIT(3)
1420/** Bit 4 - PCD - Page level cache disable bit. */
1421#define X86_PDE_PCD RT_BIT(4)
1422/** Bit 5 - A - Access bit. */
1423#define X86_PDE_A RT_BIT(5)
1424/** Bit 7 - PS - Page size attribute.
1425 * Clear mean 4KB pages, set means large pages (2/4MB). */
1426#define X86_PDE_PS RT_BIT(7)
1427/** Bits 9-11 - - Available for use to system software. */
1428#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1429/** Bits 12-31 - - Physical Page number of the next level. */
1430#define X86_PDE_PG_MASK ( 0xfffff000 )
1431
1432/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1433#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1434/** Bits 63 - NX - PAE/LM - No execution flag. */
1435#define X86_PDE_PAE_NX RT_BIT_64(63)
1436/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1437#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1438/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1439#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1440/** Bit 7 - - LM - MBZ bits when NX is active. */
1441#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1442/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1443#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1444
1445/**
1446 * Page directory entry.
1447 */
1448typedef struct X86PDEBITS
1449{
1450 /** Flags whether(=1) or not the page is present. */
1451 unsigned u1Present : 1;
1452 /** Read(=0) / Write(=1) flag. */
1453 unsigned u1Write : 1;
1454 /** User(=1) / Supervisor (=0) flag. */
1455 unsigned u1User : 1;
1456 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1457 unsigned u1WriteThru : 1;
1458 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1459 unsigned u1CacheDisable : 1;
1460 /** Accessed flag.
1461 * Indicates that the page has been read or written to. */
1462 unsigned u1Accessed : 1;
1463 /** Reserved / Ignored (dirty bit). */
1464 unsigned u1Reserved0 : 1;
1465 /** Size bit if PSE is enabled - in any event it's 0. */
1466 unsigned u1Size : 1;
1467 /** Reserved / Ignored (global bit). */
1468 unsigned u1Reserved1 : 1;
1469 /** Available for use to system software. */
1470 unsigned u3Available : 3;
1471 /** Physical Page number of the next level. */
1472 unsigned u20PageNo : 20;
1473} X86PDEBITS;
1474/** Pointer to a page directory entry. */
1475typedef X86PDEBITS *PX86PDEBITS;
1476/** Pointer to a const page directory entry. */
1477typedef const X86PDEBITS *PCX86PDEBITS;
1478
1479
1480/**
1481 * PAE page directory entry.
1482 */
1483typedef struct X86PDEPAEBITS
1484{
1485 /** Flags whether(=1) or not the page is present. */
1486 uint32_t u1Present : 1;
1487 /** Read(=0) / Write(=1) flag. */
1488 uint32_t u1Write : 1;
1489 /** User(=1) / Supervisor (=0) flag. */
1490 uint32_t u1User : 1;
1491 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1492 uint32_t u1WriteThru : 1;
1493 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1494 uint32_t u1CacheDisable : 1;
1495 /** Accessed flag.
1496 * Indicates that the page has been read or written to. */
1497 uint32_t u1Accessed : 1;
1498 /** Reserved / Ignored (dirty bit). */
1499 uint32_t u1Reserved0 : 1;
1500 /** Size bit if PSE is enabled - in any event it's 0. */
1501 uint32_t u1Size : 1;
1502 /** Reserved / Ignored (global bit). / */
1503 uint32_t u1Reserved1 : 1;
1504 /** Available for use to system software. */
1505 uint32_t u3Available : 3;
1506 /** Physical Page number of the next level - Low Part. Don't use! */
1507 uint32_t u20PageNoLow : 20;
1508 /** Physical Page number of the next level - High Part. Don't use! */
1509 uint32_t u20PageNoHigh : 20;
1510 /** MBZ bits */
1511 uint32_t u11Reserved : 11;
1512 /** No Execute flag. */
1513 uint32_t u1NoExecute : 1;
1514} X86PDEPAEBITS;
1515/** Pointer to a page directory entry. */
1516typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1517/** Pointer to a const page directory entry. */
1518typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1519
1520/** @} */
1521
1522
1523/** @name 2/4MB Page Directory Entry
1524 * @{
1525 */
1526/** Bit 0 - P - Present bit. */
1527#define X86_PDE4M_P RT_BIT(0)
1528/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1529#define X86_PDE4M_RW RT_BIT(1)
1530/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1531#define X86_PDE4M_US RT_BIT(2)
1532/** Bit 3 - PWT - Page level write thru bit. */
1533#define X86_PDE4M_PWT RT_BIT(3)
1534/** Bit 4 - PCD - Page level cache disable bit. */
1535#define X86_PDE4M_PCD RT_BIT(4)
1536/** Bit 5 - A - Access bit. */
1537#define X86_PDE4M_A RT_BIT(5)
1538/** Bit 6 - D - Dirty bit. */
1539#define X86_PDE4M_D RT_BIT(6)
1540/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1541#define X86_PDE4M_PS RT_BIT(7)
1542/** Bit 8 - G - Global flag. */
1543#define X86_PDE4M_G RT_BIT(8)
1544/** Bits 9-11 - AVL - Available for use to system software. */
1545#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1546/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1547#define X86_PDE4M_PAT RT_BIT(12)
1548/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1549#define X86_PDE4M_PAT_SHIFT (12 - 7)
1550/** Bits 22-31 - - Physical Page number. */
1551#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1552/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1553#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1554/** The number of bits to the high part of the page number. */
1555#define X86_PDE4M_PG_HIGH_SHIFT 19
1556/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1557#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1558
1559/** Bits 21-51 - - PAE/LM - Physical Page number.
1560 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1561#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1562/** Bits 63 - NX - PAE/LM - No execution flag. */
1563#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1564/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1565#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1566/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1567#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1568/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1569#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1570/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1571#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1572
1573/**
1574 * 4MB page directory entry.
1575 */
1576typedef struct X86PDE4MBITS
1577{
1578 /** Flags whether(=1) or not the page is present. */
1579 unsigned u1Present : 1;
1580 /** Read(=0) / Write(=1) flag. */
1581 unsigned u1Write : 1;
1582 /** User(=1) / Supervisor (=0) flag. */
1583 unsigned u1User : 1;
1584 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1585 unsigned u1WriteThru : 1;
1586 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1587 unsigned u1CacheDisable : 1;
1588 /** Accessed flag.
1589 * Indicates that the page have been read or written to. */
1590 unsigned u1Accessed : 1;
1591 /** Dirty flag.
1592 * Indicates that the page has been written to. */
1593 unsigned u1Dirty : 1;
1594 /** Page size flag - always 1 for 4MB entries. */
1595 unsigned u1Size : 1;
1596 /** Global flag. */
1597 unsigned u1Global : 1;
1598 /** Available for use to system software. */
1599 unsigned u3Available : 3;
1600 /** Reserved / If PAT enabled, bit 2 of the index. */
1601 unsigned u1PAT : 1;
1602 /** Bits 32-39 of the page number on AMD64.
1603 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1604 unsigned u8PageNoHigh : 8;
1605 /** Reserved. */
1606 unsigned u1Reserved : 1;
1607 /** Physical Page number of the page. */
1608 unsigned u10PageNo : 10;
1609} X86PDE4MBITS;
1610/** Pointer to a page table entry. */
1611typedef X86PDE4MBITS *PX86PDE4MBITS;
1612/** Pointer to a const page table entry. */
1613typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1614
1615
1616/**
1617 * 2MB PAE page directory entry.
1618 */
1619typedef struct X86PDE2MPAEBITS
1620{
1621 /** Flags whether(=1) or not the page is present. */
1622 uint32_t u1Present : 1;
1623 /** Read(=0) / Write(=1) flag. */
1624 uint32_t u1Write : 1;
1625 /** User(=1) / Supervisor(=0) flag. */
1626 uint32_t u1User : 1;
1627 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1628 uint32_t u1WriteThru : 1;
1629 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1630 uint32_t u1CacheDisable : 1;
1631 /** Accessed flag.
1632 * Indicates that the page have been read or written to. */
1633 uint32_t u1Accessed : 1;
1634 /** Dirty flag.
1635 * Indicates that the page has been written to. */
1636 uint32_t u1Dirty : 1;
1637 /** Page size flag - always 1 for 2MB entries. */
1638 uint32_t u1Size : 1;
1639 /** Global flag. */
1640 uint32_t u1Global : 1;
1641 /** Available for use to system software. */
1642 uint32_t u3Available : 3;
1643 /** Reserved / If PAT enabled, bit 2 of the index. */
1644 uint32_t u1PAT : 1;
1645 /** Reserved. */
1646 uint32_t u9Reserved : 9;
1647 /** Physical Page number of the next level - Low part. Don't use! */
1648 uint32_t u10PageNoLow : 10;
1649 /** Physical Page number of the next level - High part. Don't use! */
1650 uint32_t u20PageNoHigh : 20;
1651 /** MBZ bits */
1652 uint32_t u11Reserved : 11;
1653 /** No Execute flag. */
1654 uint32_t u1NoExecute : 1;
1655} X86PDE2MPAEBITS;
1656/** Pointer to a 2MB PAE page table entry. */
1657typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1658/** Pointer to a 2MB PAE page table entry. */
1659typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1660
1661/** @} */
1662
1663/**
1664 * Page directory entry.
1665 */
1666typedef union X86PDE
1667{
1668 /** Unsigned integer view. */
1669 X86PGUINT u;
1670 /** Normal view. */
1671 X86PDEBITS n;
1672 /** 4MB view (big). */
1673 X86PDE4MBITS b;
1674 /** 8 bit unsigned integer view. */
1675 uint8_t au8[4];
1676 /** 16 bit unsigned integer view. */
1677 uint16_t au16[2];
1678 /** 32 bit unsigned integer view. */
1679 uint32_t au32[1];
1680} X86PDE;
1681/** Pointer to a page directory entry. */
1682typedef X86PDE *PX86PDE;
1683/** Pointer to a const page directory entry. */
1684typedef const X86PDE *PCX86PDE;
1685
1686/**
1687 * PAE page directory entry.
1688 */
1689typedef union X86PDEPAE
1690{
1691 /** Unsigned integer view. */
1692 X86PGPAEUINT u;
1693 /** Normal view. */
1694 X86PDEPAEBITS n;
1695 /** 2MB page view (big). */
1696 X86PDE2MPAEBITS b;
1697 /** 8 bit unsigned integer view. */
1698 uint8_t au8[8];
1699 /** 16 bit unsigned integer view. */
1700 uint16_t au16[4];
1701 /** 32 bit unsigned integer view. */
1702 uint32_t au32[2];
1703} X86PDEPAE;
1704/** Pointer to a page directory entry. */
1705typedef X86PDEPAE *PX86PDEPAE;
1706/** Pointer to a const page directory entry. */
1707typedef const X86PDEPAE *PCX86PDEPAE;
1708
1709/**
1710 * Page directory.
1711 */
1712typedef struct X86PD
1713{
1714 /** PDE Array. */
1715 X86PDE a[X86_PG_ENTRIES];
1716} X86PD;
1717/** Pointer to a page directory. */
1718typedef X86PD *PX86PD;
1719/** Pointer to a const page directory. */
1720typedef const X86PD *PCX86PD;
1721
1722/** The page shift to get the PD index. */
1723#define X86_PD_SHIFT 22
1724/** The PD index mask (apply to a shifted page address). */
1725#define X86_PD_MASK 0x3ff
1726
1727
1728/**
1729 * PAE page directory.
1730 */
1731typedef struct X86PDPAE
1732{
1733 /** PDE Array. */
1734 X86PDEPAE a[X86_PG_PAE_ENTRIES];
1735} X86PDPAE;
1736/** Pointer to a PAE page directory. */
1737typedef X86PDPAE *PX86PDPAE;
1738/** Pointer to a const PAE page directory. */
1739typedef const X86PDPAE *PCX86PDPAE;
1740
1741/** The page shift to get the PAE PD index. */
1742#define X86_PD_PAE_SHIFT 21
1743/** The PAE PD index mask (apply to a shifted page address). */
1744#define X86_PD_PAE_MASK 0x1ff
1745
1746
1747/** @name Page Directory Pointer Table Entry (PAE)
1748 * @{
1749 */
1750/** Bit 0 - P - Present bit. */
1751#define X86_PDPE_P RT_BIT(0)
1752/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1753#define X86_PDPE_RW RT_BIT(1)
1754/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1755#define X86_PDPE_US RT_BIT(2)
1756/** Bit 3 - PWT - Page level write thru bit. */
1757#define X86_PDPE_PWT RT_BIT(3)
1758/** Bit 4 - PCD - Page level cache disable bit. */
1759#define X86_PDPE_PCD RT_BIT(4)
1760/** Bit 5 - A - Access bit. Long Mode only. */
1761#define X86_PDPE_A RT_BIT(5)
1762/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1763#define X86_PDPE_LM_PS RT_BIT(7)
1764/** Bits 9-11 - - Available for use to system software. */
1765#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1766/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1767#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1768/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1769#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1770/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1771#define X86_PDPE_LM_NX RT_BIT_64(63)
1772/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1773#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1774/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1775#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1776/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1777#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1778/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1779#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1780
1781
1782/**
1783 * Page directory pointer table entry.
1784 */
1785typedef struct X86PDPEBITS
1786{
1787 /** Flags whether(=1) or not the page is present. */
1788 uint32_t u1Present : 1;
1789 /** Chunk of reserved bits. */
1790 uint32_t u2Reserved : 2;
1791 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1792 uint32_t u1WriteThru : 1;
1793 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1794 uint32_t u1CacheDisable : 1;
1795 /** Chunk of reserved bits. */
1796 uint32_t u4Reserved : 4;
1797 /** Available for use to system software. */
1798 uint32_t u3Available : 3;
1799 /** Physical Page number of the next level - Low Part. Don't use! */
1800 uint32_t u20PageNoLow : 20;
1801 /** Physical Page number of the next level - High Part. Don't use! */
1802 uint32_t u20PageNoHigh : 20;
1803 /** MBZ bits */
1804 uint32_t u12Reserved : 12;
1805} X86PDPEBITS;
1806/** Pointer to a page directory pointer table entry. */
1807typedef X86PDPEBITS *PX86PTPEBITS;
1808/** Pointer to a const page directory pointer table entry. */
1809typedef const X86PDPEBITS *PCX86PTPEBITS;
1810
1811/**
1812 * Page directory pointer table entry. AMD64 version
1813 */
1814typedef struct X86PDPEAMD64BITS
1815{
1816 /** Flags whether(=1) or not the page is present. */
1817 uint32_t u1Present : 1;
1818 /** Read(=0) / Write(=1) flag. */
1819 uint32_t u1Write : 1;
1820 /** User(=1) / Supervisor (=0) flag. */
1821 uint32_t u1User : 1;
1822 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1823 uint32_t u1WriteThru : 1;
1824 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1825 uint32_t u1CacheDisable : 1;
1826 /** Accessed flag.
1827 * Indicates that the page have been read or written to. */
1828 uint32_t u1Accessed : 1;
1829 /** Chunk of reserved bits. */
1830 uint32_t u3Reserved : 3;
1831 /** Available for use to system software. */
1832 uint32_t u3Available : 3;
1833 /** Physical Page number of the next level - Low Part. Don't use! */
1834 uint32_t u20PageNoLow : 20;
1835 /** Physical Page number of the next level - High Part. Don't use! */
1836 uint32_t u20PageNoHigh : 20;
1837 /** MBZ bits */
1838 uint32_t u11Reserved : 11;
1839 /** No Execute flag. */
1840 uint32_t u1NoExecute : 1;
1841} X86PDPEAMD64BITS;
1842/** Pointer to a page directory pointer table entry. */
1843typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1844/** Pointer to a const page directory pointer table entry. */
1845typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1846
1847/**
1848 * Page directory pointer table entry.
1849 */
1850typedef union X86PDPE
1851{
1852 /** Unsigned integer view. */
1853 X86PGPAEUINT u;
1854 /** Normal view. */
1855 X86PDPEBITS n;
1856 /** AMD64 view. */
1857 X86PDPEAMD64BITS lm;
1858 /** 8 bit unsigned integer view. */
1859 uint8_t au8[8];
1860 /** 16 bit unsigned integer view. */
1861 uint16_t au16[4];
1862 /** 32 bit unsigned integer view. */
1863 uint32_t au32[2];
1864} X86PDPE;
1865/** Pointer to a page directory pointer table entry. */
1866typedef X86PDPE *PX86PDPE;
1867/** Pointer to a const page directory pointer table entry. */
1868typedef const X86PDPE *PCX86PDPE;
1869
1870
1871/**
1872 * Page directory pointer table.
1873 */
1874typedef struct X86PDPT
1875{
1876 /** PDE Array. */
1877 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1878} X86PDPT;
1879/** Pointer to a page directory pointer table. */
1880typedef X86PDPT *PX86PDPT;
1881/** Pointer to a const page directory pointer table. */
1882typedef const X86PDPT *PCX86PDPT;
1883
1884/** The page shift to get the PDPT index. */
1885#define X86_PDPT_SHIFT 30
1886/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1887#define X86_PDPT_MASK_PAE 0x3
1888/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1889#define X86_PDPT_MASK_AMD64 0x1ff
1890
1891/** @} */
1892
1893
1894/** @name Page Map Level-4 Entry (Long Mode PAE)
1895 * @{
1896 */
1897/** Bit 0 - P - Present bit. */
1898#define X86_PML4E_P RT_BIT(0)
1899/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1900#define X86_PML4E_RW RT_BIT(1)
1901/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1902#define X86_PML4E_US RT_BIT(2)
1903/** Bit 3 - PWT - Page level write thru bit. */
1904#define X86_PML4E_PWT RT_BIT(3)
1905/** Bit 4 - PCD - Page level cache disable bit. */
1906#define X86_PML4E_PCD RT_BIT(4)
1907/** Bit 5 - A - Access bit. */
1908#define X86_PML4E_A RT_BIT(5)
1909/** Bits 9-11 - - Available for use to system software. */
1910#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1911/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1912#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1913/** Bits 8, 7 - - MBZ bits when NX is active. */
1914#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1915/** Bits 63, 7 - - MBZ bits when no NX. */
1916#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1917/** Bits 63 - NX - PAE - No execution flag. */
1918#define X86_PML4E_NX RT_BIT_64(63)
1919
1920/**
1921 * Page Map Level-4 Entry
1922 */
1923typedef struct X86PML4EBITS
1924{
1925 /** Flags whether(=1) or not the page is present. */
1926 uint32_t u1Present : 1;
1927 /** Read(=0) / Write(=1) flag. */
1928 uint32_t u1Write : 1;
1929 /** User(=1) / Supervisor (=0) flag. */
1930 uint32_t u1User : 1;
1931 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1932 uint32_t u1WriteThru : 1;
1933 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1934 uint32_t u1CacheDisable : 1;
1935 /** Accessed flag.
1936 * Indicates that the page have been read or written to. */
1937 uint32_t u1Accessed : 1;
1938 /** Chunk of reserved bits. */
1939 uint32_t u3Reserved : 3;
1940 /** Available for use to system software. */
1941 uint32_t u3Available : 3;
1942 /** Physical Page number of the next level - Low Part. Don't use! */
1943 uint32_t u20PageNoLow : 20;
1944 /** Physical Page number of the next level - High Part. Don't use! */
1945 uint32_t u20PageNoHigh : 20;
1946 /** MBZ bits */
1947 uint32_t u11Reserved : 11;
1948 /** No Execute flag. */
1949 uint32_t u1NoExecute : 1;
1950} X86PML4EBITS;
1951/** Pointer to a page map level-4 entry. */
1952typedef X86PML4EBITS *PX86PML4EBITS;
1953/** Pointer to a const page map level-4 entry. */
1954typedef const X86PML4EBITS *PCX86PML4EBITS;
1955
1956/**
1957 * Page Map Level-4 Entry.
1958 */
1959typedef union X86PML4E
1960{
1961 /** Unsigned integer view. */
1962 X86PGPAEUINT u;
1963 /** Normal view. */
1964 X86PML4EBITS n;
1965 /** 8 bit unsigned integer view. */
1966 uint8_t au8[8];
1967 /** 16 bit unsigned integer view. */
1968 uint16_t au16[4];
1969 /** 32 bit unsigned integer view. */
1970 uint32_t au32[2];
1971} X86PML4E;
1972/** Pointer to a page map level-4 entry. */
1973typedef X86PML4E *PX86PML4E;
1974/** Pointer to a const page map level-4 entry. */
1975typedef const X86PML4E *PCX86PML4E;
1976
1977
1978/**
1979 * Page Map Level-4.
1980 */
1981typedef struct X86PML4
1982{
1983 /** PDE Array. */
1984 X86PML4E a[X86_PG_PAE_ENTRIES];
1985} X86PML4;
1986/** Pointer to a page map level-4. */
1987typedef X86PML4 *PX86PML4;
1988/** Pointer to a const page map level-4. */
1989typedef const X86PML4 *PCX86PML4;
1990
1991/** The page shift to get the PML4 index. */
1992#define X86_PML4_SHIFT 39
1993/** The PML4 index mask (apply to a shifted page address). */
1994#define X86_PML4_MASK 0x1ff
1995
1996/** @} */
1997
1998/** @} */
1999
2000
2001/**
2002 * 80-bit MMX/FPU register type.
2003 */
2004typedef struct X86FPUMMX
2005{
2006 uint8_t reg[10];
2007} X86FPUMMX;
2008/** Pointer to a 80-bit MMX/FPU register type. */
2009typedef X86FPUMMX *PX86FPUMMX;
2010/** Pointer to a const 80-bit MMX/FPU register type. */
2011typedef const X86FPUMMX *PCX86FPUMMX;
2012
2013/**
2014 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2015 * @todo verify this...
2016 */
2017#pragma pack(1)
2018typedef struct X86FPUSTATE
2019{
2020 /** 0x00 - Control word. */
2021 uint16_t FCW;
2022 /** 0x02 - Alignment word */
2023 uint16_t Dummy1;
2024 /** 0x04 - Status word. */
2025 uint16_t FSW;
2026 /** 0x06 - Alignment word */
2027 uint16_t Dummy2;
2028 /** 0x08 - Tag word */
2029 uint16_t FTW;
2030 /** 0x0a - Alignment word */
2031 uint16_t Dummy3;
2032
2033 /** 0x0c - Instruction pointer. */
2034 uint32_t FPUIP;
2035 /** 0x10 - Code selector. */
2036 uint16_t CS;
2037 /** 0x12 - Opcode. */
2038 uint16_t FOP;
2039 /** 0x14 - FOO. */
2040 uint32_t FPUOO;
2041 /** 0x18 - FOS. */
2042 uint32_t FPUOS;
2043 /** 0x1c */
2044 union
2045 {
2046 /** MMX view. */
2047 uint64_t mmx;
2048 /** FPU view - todo. */
2049 X86FPUMMX fpu;
2050 /** Extended precision floating point view. */
2051 RTFLOAT80U r80;
2052 /** Extended precision floating point view v2. */
2053 RTFLOAT80U2 r80Ex;
2054 /** 8-bit view. */
2055 uint8_t au8[16];
2056 /** 16-bit view. */
2057 uint16_t au16[8];
2058 /** 32-bit view. */
2059 uint32_t au32[4];
2060 /** 64-bit view. */
2061 uint64_t au64[2];
2062 /** 128-bit view. (yeah, very helpful) */
2063 uint128_t au128[1];
2064 } regs[8];
2065} X86FPUSTATE;
2066#pragma pack()
2067/** Pointer to a FPU state. */
2068typedef X86FPUSTATE *PX86FPUSTATE;
2069/** Pointer to a const FPU state. */
2070typedef const X86FPUSTATE *PCX86FPUSTATE;
2071
2072/**
2073 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2074 */
2075#pragma pack(1)
2076typedef struct X86FXSTATE
2077{
2078 /** 0x00 - Control word. */
2079 uint16_t FCW;
2080 /** 0x02 - Status word. */
2081 uint16_t FSW;
2082 /** 0x04 - Tag word. (The upper byte is always zero.) */
2083 uint16_t FTW;
2084 /** 0x06 - Opcode. */
2085 uint16_t FOP;
2086 /** 0x08 - Instruction pointer. */
2087 uint32_t FPUIP;
2088 /** 0x0c - Code selector. */
2089 uint16_t CS;
2090 uint16_t Rsrvd1;
2091 /** 0x10 - Data pointer. */
2092 uint32_t FPUDP;
2093 /** 0x14 - Data segment */
2094 uint16_t DS;
2095 /** 0x16 */
2096 uint16_t Rsrvd2;
2097 /** 0x18 */
2098 uint32_t MXCSR;
2099 /** 0x1c */
2100 uint32_t MXCSR_MASK;
2101 /** 0x20 */
2102 union
2103 {
2104 /** MMX view. */
2105 uint64_t mmx;
2106 /** FPU view - todo. */
2107 X86FPUMMX fpu;
2108 /** Extended precision floating point view. */
2109 RTFLOAT80U r80;
2110 /** Extended precision floating point view v2 */
2111 RTFLOAT80U2 r80Ex;
2112 /** 8-bit view. */
2113 uint8_t au8[16];
2114 /** 16-bit view. */
2115 uint16_t au16[8];
2116 /** 32-bit view. */
2117 uint32_t au32[4];
2118 /** 64-bit view. */
2119 uint64_t au64[2];
2120 /** 128-bit view. (yeah, very helpful) */
2121 uint128_t au128[1];
2122 } aRegs[8];
2123 /* - offset 160 - */
2124 union
2125 {
2126 /** XMM Register view *. */
2127 uint128_t xmm;
2128 /** 8-bit view. */
2129 uint8_t au8[16];
2130 /** 16-bit view. */
2131 uint16_t au16[8];
2132 /** 32-bit view. */
2133 uint32_t au32[4];
2134 /** 64-bit view. */
2135 uint64_t au64[2];
2136 /** 128-bit view. (yeah, very helpful) */
2137 uint128_t au128[1];
2138 } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2139 /* - offset 416 - */
2140 uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2141} X86FXSTATE;
2142#pragma pack()
2143/** Pointer to a FPU Extended state. */
2144typedef X86FXSTATE *PX86FXSTATE;
2145/** Pointer to a const FPU Extended state. */
2146typedef const X86FXSTATE *PCX86FXSTATE;
2147
2148/** @name FPU status word flags.
2149 * @{ */
2150/** Exception Flag: Invalid operation. */
2151#define X86_FSW_IE RT_BIT(0)
2152/** Exception Flag: Denormalized operand. */
2153#define X86_FSW_DE RT_BIT(1)
2154/** Exception Flag: Zero divide. */
2155#define X86_FSW_ZE RT_BIT(2)
2156/** Exception Flag: Overflow. */
2157#define X86_FSW_OE RT_BIT(3)
2158/** Exception Flag: Underflow. */
2159#define X86_FSW_UE RT_BIT(4)
2160/** Exception Flag: Precision. */
2161#define X86_FSW_PE RT_BIT(5)
2162/** Stack fault. */
2163#define X86_FSW_SF RT_BIT(6)
2164/** Error summary status. */
2165#define X86_FSW_ES RT_BIT(7)
2166/** Mask of exceptions flags, excluding the summary bit. */
2167#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2168/** Mask of exceptions flags, including the summary bit. */
2169#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2170/** Condition code 0. */
2171#define X86_FSW_C0 RT_BIT(8)
2172/** Condition code 1. */
2173#define X86_FSW_C1 RT_BIT(9)
2174/** Condition code 2. */
2175#define X86_FSW_C2 RT_BIT(10)
2176/** Top of the stack mask. */
2177#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2178/** TOP shift value. */
2179#define X86_FSW_TOP_SHIFT 11
2180/** Mask for getting TOP value after shifting it right. */
2181#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2182/** Get the TOP value. */
2183#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2184/** Condition code 3. */
2185#define X86_FSW_C3 RT_BIT(14)
2186/** Mask of exceptions flags, including the summary bit. */
2187#define X86_FSW_C_MASK UINT16_C(0x4700)
2188/** FPU busy. */
2189#define X86_FSW_B RT_BIT(15)
2190/** @} */
2191
2192
2193/** @name FPU control word flags.
2194 * @{ */
2195/** Exception Mask: Invalid operation. */
2196#define X86_FCW_IM RT_BIT(0)
2197/** Exception Mask: Denormalized operand. */
2198#define X86_FCW_DM RT_BIT(1)
2199/** Exception Mask: Zero divide. */
2200#define X86_FCW_ZM RT_BIT(2)
2201/** Exception Mask: Overflow. */
2202#define X86_FCW_OM RT_BIT(3)
2203/** Exception Mask: Underflow. */
2204#define X86_FCW_UM RT_BIT(4)
2205/** Exception Mask: Precision. */
2206#define X86_FCW_PM RT_BIT(5)
2207/** Mask all exceptions, the value typically loaded (by for instance fninit).
2208 * @remarks This includes reserved bit 6. */
2209#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2210/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2211#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2212/** Precision control mask. */
2213#define X86_FCW_PC_MASK UINT16_C(0x0300)
2214/** Precision control: 24-bit. */
2215#define X86_FCW_PC_24 UINT16_C(0x0000)
2216/** Precision control: Reserved. */
2217#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2218/** Precision control: 53-bit. */
2219#define X86_FCW_PC_53 UINT16_C(0x0200)
2220/** Precision control: 64-bit. */
2221#define X86_FCW_PC_64 UINT16_C(0x0300)
2222/** Rounding control mask. */
2223#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2224/** Rounding control: To nearest. */
2225#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2226/** Rounding control: Down. */
2227#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2228/** Rounding control: Up. */
2229#define X86_FCW_RC_UP UINT16_C(0x0800)
2230/** Rounding control: Towards zero. */
2231#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2232/** Bits which should be zero, apparently. */
2233#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2234/** @} */
2235
2236/** @name SSE MXCSR
2237 * @{ */
2238/** Exception Flag: Invalid operation. */
2239#define X86_MSXCR_IE RT_BIT(0)
2240/** Exception Flag: Denormalized operand. */
2241#define X86_MSXCR_DE RT_BIT(1)
2242/** Exception Flag: Zero divide. */
2243#define X86_MSXCR_ZE RT_BIT(2)
2244/** Exception Flag: Overflow. */
2245#define X86_MSXCR_OE RT_BIT(3)
2246/** Exception Flag: Underflow. */
2247#define X86_MSXCR_UE RT_BIT(4)
2248/** Exception Flag: Precision. */
2249#define X86_MSXCR_PE RT_BIT(5)
2250
2251/** Denormals are zero. */
2252#define X86_MSXCR_DAZ RT_BIT(6)
2253
2254/** Exception Mask: Invalid operation. */
2255#define X86_MSXCR_IM RT_BIT(7)
2256/** Exception Mask: Denormalized operand. */
2257#define X86_MSXCR_DM RT_BIT(8)
2258/** Exception Mask: Zero divide. */
2259#define X86_MSXCR_ZM RT_BIT(9)
2260/** Exception Mask: Overflow. */
2261#define X86_MSXCR_OM RT_BIT(10)
2262/** Exception Mask: Underflow. */
2263#define X86_MSXCR_UM RT_BIT(11)
2264/** Exception Mask: Precision. */
2265#define X86_MSXCR_PM RT_BIT(12)
2266
2267/** Rounding control mask. */
2268#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2269/** Rounding control: To nearest. */
2270#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2271/** Rounding control: Down. */
2272#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2273/** Rounding control: Up. */
2274#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2275/** Rounding control: Towards zero. */
2276#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2277
2278/** Flush-to-zero for masked underflow. */
2279#define X86_MSXCR_FZ RT_BIT(15)
2280
2281/** Misaligned Exception Mask. */
2282#define X86_MSXCR_MM RT_BIT(16)
2283/** @} */
2284
2285
2286/** @name Selector Descriptor
2287 * @{
2288 */
2289
2290#ifndef VBOX_FOR_DTRACE_LIB
2291/**
2292 * Descriptor attributes (as seen by VT-x).
2293 */
2294typedef struct X86DESCATTRBITS
2295{
2296 /** 00 - Segment Type. */
2297 unsigned u4Type : 4;
2298 /** 04 - Descriptor Type. System(=0) or code/data selector */
2299 unsigned u1DescType : 1;
2300 /** 05 - Descriptor Privelege level. */
2301 unsigned u2Dpl : 2;
2302 /** 07 - Flags selector present(=1) or not. */
2303 unsigned u1Present : 1;
2304 /** 08 - Segment limit 16-19. */
2305 unsigned u4LimitHigh : 4;
2306 /** 0c - Available for system software. */
2307 unsigned u1Available : 1;
2308 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2309 unsigned u1Long : 1;
2310 /** 0e - This flags meaning depends on the segment type. Try make sense out
2311 * of the intel manual yourself. */
2312 unsigned u1DefBig : 1;
2313 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
2314 * clear byte. */
2315 unsigned u1Granularity : 1;
2316 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2317 unsigned u1Unusable : 1;
2318} X86DESCATTRBITS;
2319#endif /* !VBOX_FOR_DTRACE_LIB */
2320
2321/** @name X86DESCATTR masks
2322 * @{ */
2323#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2324#define X86DESCATTR_DT UINT32_C(0x00000010)
2325#define X86DESCATTR_DPL UINT32_C(0x00000060)
2326#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
2327#define X86DESCATTR_P UINT32_C(0x00000800)
2328#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2329#define X86DESCATTR_AVL UINT32_C(0x00001000)
2330#define X86DESCATTR_L UINT32_C(0x00002000)
2331#define X86DESCATTR_D UINT32_C(0x00004000)
2332#define X86DESCATTR_G UINT32_C(0x00008000)
2333#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2334/** @} */
2335
2336#pragma pack(1)
2337typedef union X86DESCATTR
2338{
2339 /** Unsigned integer view. */
2340 uint32_t u;
2341#ifndef VBOX_FOR_DTRACE_LIB
2342 /** Normal view. */
2343 X86DESCATTRBITS n;
2344#endif
2345} X86DESCATTR;
2346#pragma pack()
2347/** Pointer to descriptor attributes. */
2348typedef X86DESCATTR *PX86DESCATTR;
2349/** Pointer to const descriptor attributes. */
2350typedef const X86DESCATTR *PCX86DESCATTR;
2351
2352#ifndef VBOX_FOR_DTRACE_LIB
2353
2354/**
2355 * Generic descriptor table entry
2356 */
2357#pragma pack(1)
2358typedef struct X86DESCGENERIC
2359{
2360 /** 00 - Limit - Low word. */
2361 unsigned u16LimitLow : 16;
2362 /** 10 - Base address - lowe word.
2363 * Don't try set this to 24 because MSC is doing stupid things then. */
2364 unsigned u16BaseLow : 16;
2365 /** 20 - Base address - first 8 bits of high word. */
2366 unsigned u8BaseHigh1 : 8;
2367 /** 28 - Segment Type. */
2368 unsigned u4Type : 4;
2369 /** 2c - Descriptor Type. System(=0) or code/data selector */
2370 unsigned u1DescType : 1;
2371 /** 2d - Descriptor Privelege level. */
2372 unsigned u2Dpl : 2;
2373 /** 2f - Flags selector present(=1) or not. */
2374 unsigned u1Present : 1;
2375 /** 30 - Segment limit 16-19. */
2376 unsigned u4LimitHigh : 4;
2377 /** 34 - Available for system software. */
2378 unsigned u1Available : 1;
2379 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2380 unsigned u1Long : 1;
2381 /** 36 - This flags meaning depends on the segment type. Try make sense out
2382 * of the intel manual yourself. */
2383 unsigned u1DefBig : 1;
2384 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
2385 * clear byte. */
2386 unsigned u1Granularity : 1;
2387 /** 38 - Base address - highest 8 bits. */
2388 unsigned u8BaseHigh2 : 8;
2389} X86DESCGENERIC;
2390#pragma pack()
2391/** Pointer to a generic descriptor entry. */
2392typedef X86DESCGENERIC *PX86DESCGENERIC;
2393/** Pointer to a const generic descriptor entry. */
2394typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2395
2396/** @name Bit offsets of X86DESCGENERIC members.
2397 * @{*/
2398#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
2399#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
2400#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
2401#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
2402#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
2403#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
2404#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
2405#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
2406#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
2407#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
2408#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
2409#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
2410#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
2411/** @} */
2412
2413/**
2414 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2415 */
2416typedef struct X86DESCGATE
2417{
2418 /** 00 - Target code segment offset - Low word.
2419 * Ignored if task-gate. */
2420 unsigned u16OffsetLow : 16;
2421 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2422 * TSS selector if task-gate. */
2423 unsigned u16Sel : 16;
2424 /** 20 - Number of parameters for a call-gate.
2425 * Ignored if interrupt-, trap- or task-gate. */
2426 unsigned u4ParmCount : 4;
2427 /** 24 - Reserved / ignored. */
2428 unsigned u4Reserved : 4;
2429 /** 28 - Segment Type. */
2430 unsigned u4Type : 4;
2431 /** 2c - Descriptor Type (0 = system). */
2432 unsigned u1DescType : 1;
2433 /** 2d - Descriptor Privelege level. */
2434 unsigned u2Dpl : 2;
2435 /** 2f - Flags selector present(=1) or not. */
2436 unsigned u1Present : 1;
2437 /** 30 - Target code segment offset - High word.
2438 * Ignored if task-gate. */
2439 unsigned u16OffsetHigh : 16;
2440} X86DESCGATE;
2441/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2442typedef X86DESCGATE *PX86DESCGATE;
2443/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2444typedef const X86DESCGATE *PCX86DESCGATE;
2445
2446#endif /* VBOX_FOR_DTRACE_LIB */
2447
2448/**
2449 * Descriptor table entry.
2450 */
2451#pragma pack(1)
2452typedef union X86DESC
2453{
2454#ifndef VBOX_FOR_DTRACE_LIB
2455 /** Generic descriptor view. */
2456 X86DESCGENERIC Gen;
2457 /** Gate descriptor view. */
2458 X86DESCGATE Gate;
2459#endif
2460
2461 /** 8 bit unsigned integer view. */
2462 uint8_t au8[8];
2463 /** 16 bit unsigned integer view. */
2464 uint16_t au16[4];
2465 /** 32 bit unsigned integer view. */
2466 uint32_t au32[2];
2467 /** 64 bit unsigned integer view. */
2468 uint64_t au64[1];
2469 /** Unsigned integer view. */
2470 uint64_t u;
2471} X86DESC;
2472#ifndef VBOX_FOR_DTRACE_LIB
2473AssertCompileSize(X86DESC, 8);
2474#endif
2475#pragma pack()
2476/** Pointer to descriptor table entry. */
2477typedef X86DESC *PX86DESC;
2478/** Pointer to const descriptor table entry. */
2479typedef const X86DESC *PCX86DESC;
2480
2481/** @def X86DESC_BASE
2482 * Return the base address of a descriptor.
2483 */
2484#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
2485 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2486 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2487 | ( (a_pDesc)->Gen.u16BaseLow ) )
2488
2489/** @def X86DESC_LIMIT
2490 * Return the limit of a descriptor.
2491 */
2492#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
2493 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2494 | ( (a_pDesc)->Gen.u16LimitLow ) )
2495
2496/** @def X86DESC_LIMIT_G
2497 * Return the limit of a descriptor with the granularity bit taken into account.
2498 * @returns Selector limit (uint32_t).
2499 * @param a_pDesc Pointer to the descriptor.
2500 */
2501#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
2502 ( (a_pDesc)->Gen.u1Granularity \
2503 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
2504 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
2505 )
2506
2507/** @def X86DESC_GET_HID_ATTR
2508 * Get the descriptor attributes for the hidden register.
2509 */
2510#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
2511 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2512
2513#ifndef VBOX_FOR_DTRACE_LIB
2514
2515/**
2516 * 64 bits generic descriptor table entry
2517 * Note: most of these bits have no meaning in long mode.
2518 */
2519#pragma pack(1)
2520typedef struct X86DESC64GENERIC
2521{
2522 /** Limit - Low word - *IGNORED*. */
2523 unsigned u16LimitLow : 16;
2524 /** Base address - low word. - *IGNORED*
2525 * Don't try set this to 24 because MSC is doing stupid things then. */
2526 unsigned u16BaseLow : 16;
2527 /** Base address - first 8 bits of high word. - *IGNORED* */
2528 unsigned u8BaseHigh1 : 8;
2529 /** Segment Type. */
2530 unsigned u4Type : 4;
2531 /** Descriptor Type. System(=0) or code/data selector */
2532 unsigned u1DescType : 1;
2533 /** Descriptor Privelege level. */
2534 unsigned u2Dpl : 2;
2535 /** Flags selector present(=1) or not. */
2536 unsigned u1Present : 1;
2537 /** Segment limit 16-19. - *IGNORED* */
2538 unsigned u4LimitHigh : 4;
2539 /** Available for system software. - *IGNORED* */
2540 unsigned u1Available : 1;
2541 /** Long mode flag. */
2542 unsigned u1Long : 1;
2543 /** This flags meaning depends on the segment type. Try make sense out
2544 * of the intel manual yourself. */
2545 unsigned u1DefBig : 1;
2546 /** Granularity of the limit. If set 4KB granularity is used, if
2547 * clear byte. - *IGNORED* */
2548 unsigned u1Granularity : 1;
2549 /** Base address - highest 8 bits. - *IGNORED* */
2550 unsigned u8BaseHigh2 : 8;
2551 /** Base address - bits 63-32. */
2552 unsigned u32BaseHigh3 : 32;
2553 unsigned u8Reserved : 8;
2554 unsigned u5Zeros : 5;
2555 unsigned u19Reserved : 19;
2556} X86DESC64GENERIC;
2557#pragma pack()
2558/** Pointer to a generic descriptor entry. */
2559typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2560/** Pointer to a const generic descriptor entry. */
2561typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2562
2563/**
2564 * System descriptor table entry (64 bits)
2565 *
2566 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2567 */
2568#pragma pack(1)
2569typedef struct X86DESC64SYSTEM
2570{
2571 /** Limit - Low word. */
2572 unsigned u16LimitLow : 16;
2573 /** Base address - lowe word.
2574 * Don't try set this to 24 because MSC is doing stupid things then. */
2575 unsigned u16BaseLow : 16;
2576 /** Base address - first 8 bits of high word. */
2577 unsigned u8BaseHigh1 : 8;
2578 /** Segment Type. */
2579 unsigned u4Type : 4;
2580 /** Descriptor Type. System(=0) or code/data selector */
2581 unsigned u1DescType : 1;
2582 /** Descriptor Privelege level. */
2583 unsigned u2Dpl : 2;
2584 /** Flags selector present(=1) or not. */
2585 unsigned u1Present : 1;
2586 /** Segment limit 16-19. */
2587 unsigned u4LimitHigh : 4;
2588 /** Available for system software. */
2589 unsigned u1Available : 1;
2590 /** Reserved - 0. */
2591 unsigned u1Reserved : 1;
2592 /** This flags meaning depends on the segment type. Try make sense out
2593 * of the intel manual yourself. */
2594 unsigned u1DefBig : 1;
2595 /** Granularity of the limit. If set 4KB granularity is used, if
2596 * clear byte. */
2597 unsigned u1Granularity : 1;
2598 /** Base address - bits 31-24. */
2599 unsigned u8BaseHigh2 : 8;
2600 /** Base address - bits 63-32. */
2601 unsigned u32BaseHigh3 : 32;
2602 unsigned u8Reserved : 8;
2603 unsigned u5Zeros : 5;
2604 unsigned u19Reserved : 19;
2605} X86DESC64SYSTEM;
2606#pragma pack()
2607/** Pointer to a system descriptor entry. */
2608typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2609/** Pointer to a const system descriptor entry. */
2610typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2611
2612/**
2613 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2614 */
2615typedef struct X86DESC64GATE
2616{
2617 /** Target code segment offset - Low word. */
2618 unsigned u16OffsetLow : 16;
2619 /** Target code segment selector. */
2620 unsigned u16Sel : 16;
2621 /** Interrupt stack table for interrupt- and trap-gates.
2622 * Ignored by call-gates. */
2623 unsigned u3IST : 3;
2624 /** Reserved / ignored. */
2625 unsigned u5Reserved : 5;
2626 /** Segment Type. */
2627 unsigned u4Type : 4;
2628 /** Descriptor Type (0 = system). */
2629 unsigned u1DescType : 1;
2630 /** Descriptor Privelege level. */
2631 unsigned u2Dpl : 2;
2632 /** Flags selector present(=1) or not. */
2633 unsigned u1Present : 1;
2634 /** Target code segment offset - High word.
2635 * Ignored if task-gate. */
2636 unsigned u16OffsetHigh : 16;
2637 /** Target code segment offset - Top dword.
2638 * Ignored if task-gate. */
2639 unsigned u32OffsetTop : 32;
2640 /** Reserved / ignored / must be zero.
2641 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2642 unsigned u32Reserved : 32;
2643} X86DESC64GATE;
2644AssertCompileSize(X86DESC64GATE, 16);
2645/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2646typedef X86DESC64GATE *PX86DESC64GATE;
2647/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2648typedef const X86DESC64GATE *PCX86DESC64GATE;
2649
2650#endif /* VBOX_FOR_DTRACE_LIB */
2651
2652/**
2653 * Descriptor table entry.
2654 */
2655#pragma pack(1)
2656typedef union X86DESC64
2657{
2658#ifndef VBOX_FOR_DTRACE_LIB
2659 /** Generic descriptor view. */
2660 X86DESC64GENERIC Gen;
2661 /** System descriptor view. */
2662 X86DESC64SYSTEM System;
2663 /** Gate descriptor view. */
2664 X86DESC64GATE Gate;
2665#endif
2666
2667 /** 8 bit unsigned integer view. */
2668 uint8_t au8[16];
2669 /** 16 bit unsigned integer view. */
2670 uint16_t au16[8];
2671 /** 32 bit unsigned integer view. */
2672 uint32_t au32[4];
2673 /** 64 bit unsigned integer view. */
2674 uint64_t au64[2];
2675} X86DESC64;
2676#ifndef VBOX_FOR_DTRACE_LIB
2677AssertCompileSize(X86DESC64, 16);
2678#endif
2679#pragma pack()
2680/** Pointer to descriptor table entry. */
2681typedef X86DESC64 *PX86DESC64;
2682/** Pointer to const descriptor table entry. */
2683typedef const X86DESC64 *PCX86DESC64;
2684
2685/** @def X86DESC64_BASE
2686 * Return the base of a 64-bit descriptor.
2687 */
2688#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
2689 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2690 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2691 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2692 | ( (a_pDesc)->Gen.u16BaseLow ) )
2693
2694
2695
2696/** @name Host system descriptor table entry - Use with care!
2697 * @{ */
2698/** Host system descriptor table entry. */
2699#if HC_ARCH_BITS == 64
2700typedef X86DESC64 X86DESCHC;
2701#else
2702typedef X86DESC X86DESCHC;
2703#endif
2704/** Pointer to a host system descriptor table entry. */
2705#if HC_ARCH_BITS == 64
2706typedef PX86DESC64 PX86DESCHC;
2707#else
2708typedef PX86DESC PX86DESCHC;
2709#endif
2710/** Pointer to a const host system descriptor table entry. */
2711#if HC_ARCH_BITS == 64
2712typedef PCX86DESC64 PCX86DESCHC;
2713#else
2714typedef PCX86DESC PCX86DESCHC;
2715#endif
2716/** @} */
2717
2718
2719/** @name Selector Descriptor Types.
2720 * @{
2721 */
2722
2723/** @name Non-System Selector Types.
2724 * @{ */
2725/** Code(=set)/Data(=clear) bit. */
2726#define X86_SEL_TYPE_CODE 8
2727/** Memory(=set)/System(=clear) bit. */
2728#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2729/** Accessed bit. */
2730#define X86_SEL_TYPE_ACCESSED 1
2731/** Expand down bit (for data selectors only). */
2732#define X86_SEL_TYPE_DOWN 4
2733/** Conforming bit (for code selectors only). */
2734#define X86_SEL_TYPE_CONF 4
2735/** Write bit (for data selectors only). */
2736#define X86_SEL_TYPE_WRITE 2
2737/** Read bit (for code selectors only). */
2738#define X86_SEL_TYPE_READ 2
2739/** The bit number of the code segment read bit (relative to u4Type). */
2740#define X86_SEL_TYPE_READ_BIT 1
2741
2742/** Read only selector type. */
2743#define X86_SEL_TYPE_RO 0
2744/** Accessed read only selector type. */
2745#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
2746/** Read write selector type. */
2747#define X86_SEL_TYPE_RW 2
2748/** Accessed read write selector type. */
2749#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
2750/** Expand down read only selector type. */
2751#define X86_SEL_TYPE_RO_DOWN 4
2752/** Accessed expand down read only selector type. */
2753#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
2754/** Expand down read write selector type. */
2755#define X86_SEL_TYPE_RW_DOWN 6
2756/** Accessed expand down read write selector type. */
2757#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
2758/** Execute only selector type. */
2759#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
2760/** Accessed execute only selector type. */
2761#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2762/** Execute and read selector type. */
2763#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
2764/** Accessed execute and read selector type. */
2765#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2766/** Conforming execute only selector type. */
2767#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
2768/** Accessed Conforming execute only selector type. */
2769#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2770/** Conforming execute and write selector type. */
2771#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
2772/** Accessed Conforming execute and write selector type. */
2773#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2774/** @} */
2775
2776
2777/** @name System Selector Types.
2778 * @{ */
2779/** The TSS busy bit mask. */
2780#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2781
2782/** Undefined system selector type. */
2783#define X86_SEL_TYPE_SYS_UNDEFINED 0
2784/** 286 TSS selector. */
2785#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2786/** LDT selector. */
2787#define X86_SEL_TYPE_SYS_LDT 2
2788/** 286 TSS selector - Busy. */
2789#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2790/** 286 Callgate selector. */
2791#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2792/** Taskgate selector. */
2793#define X86_SEL_TYPE_SYS_TASK_GATE 5
2794/** 286 Interrupt gate selector. */
2795#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2796/** 286 Trapgate selector. */
2797#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2798/** Undefined system selector. */
2799#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2800/** 386 TSS selector. */
2801#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2802/** Undefined system selector. */
2803#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2804/** 386 TSS selector - Busy. */
2805#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2806/** 386 Callgate selector. */
2807#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2808/** Undefined system selector. */
2809#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2810/** 386 Interruptgate selector. */
2811#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2812/** 386 Trapgate selector. */
2813#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2814/** @} */
2815
2816/** @name AMD64 System Selector Types.
2817 * @{ */
2818/** LDT selector. */
2819#define AMD64_SEL_TYPE_SYS_LDT 2
2820/** TSS selector - Busy. */
2821#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2822/** TSS selector - Busy. */
2823#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2824/** Callgate selector. */
2825#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2826/** Interruptgate selector. */
2827#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2828/** Trapgate selector. */
2829#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2830/** @} */
2831
2832/** @} */
2833
2834
2835/** @name Descriptor Table Entry Flag Masks.
2836 * These are for the 2nd 32-bit word of a descriptor.
2837 * @{ */
2838/** Bits 8-11 - TYPE - Descriptor type mask. */
2839#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
2840/** Bit 12 - S - System (=0) or Code/Data (=1). */
2841#define X86_DESC_S RT_BIT(12)
2842/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2843#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
2844/** Bit 15 - P - Present. */
2845#define X86_DESC_P RT_BIT(15)
2846/** Bit 20 - AVL - Available for system software. */
2847#define X86_DESC_AVL RT_BIT(20)
2848/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2849#define X86_DESC_DB RT_BIT(22)
2850/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2851 * used, if clear byte. */
2852#define X86_DESC_G RT_BIT(23)
2853/** @} */
2854
2855/** @} */
2856
2857
2858/** @name Task Segments.
2859 * @{
2860 */
2861
2862/**
2863 * 16-bit Task Segment (TSS).
2864 */
2865#pragma pack(1)
2866typedef struct X86TSS16
2867{
2868 /** Back link to previous task. (static) */
2869 RTSEL selPrev;
2870 /** Ring-0 stack pointer. (static) */
2871 uint16_t sp0;
2872 /** Ring-0 stack segment. (static) */
2873 RTSEL ss0;
2874 /** Ring-1 stack pointer. (static) */
2875 uint16_t sp1;
2876 /** Ring-1 stack segment. (static) */
2877 RTSEL ss1;
2878 /** Ring-2 stack pointer. (static) */
2879 uint16_t sp2;
2880 /** Ring-2 stack segment. (static) */
2881 RTSEL ss2;
2882 /** IP before task switch. */
2883 uint16_t ip;
2884 /** FLAGS before task switch. */
2885 uint16_t flags;
2886 /** AX before task switch. */
2887 uint16_t ax;
2888 /** CX before task switch. */
2889 uint16_t cx;
2890 /** DX before task switch. */
2891 uint16_t dx;
2892 /** BX before task switch. */
2893 uint16_t bx;
2894 /** SP before task switch. */
2895 uint16_t sp;
2896 /** BP before task switch. */
2897 uint16_t bp;
2898 /** SI before task switch. */
2899 uint16_t si;
2900 /** DI before task switch. */
2901 uint16_t di;
2902 /** ES before task switch. */
2903 RTSEL es;
2904 /** CS before task switch. */
2905 RTSEL cs;
2906 /** SS before task switch. */
2907 RTSEL ss;
2908 /** DS before task switch. */
2909 RTSEL ds;
2910 /** LDTR before task switch. */
2911 RTSEL selLdt;
2912} X86TSS16;
2913#ifndef VBOX_FOR_DTRACE_LIB
2914AssertCompileSize(X86TSS16, 44);
2915#endif
2916#pragma pack()
2917/** Pointer to a 16-bit task segment. */
2918typedef X86TSS16 *PX86TSS16;
2919/** Pointer to a const 16-bit task segment. */
2920typedef const X86TSS16 *PCX86TSS16;
2921
2922
2923/**
2924 * 32-bit Task Segment (TSS).
2925 */
2926#pragma pack(1)
2927typedef struct X86TSS32
2928{
2929 /** Back link to previous task. (static) */
2930 RTSEL selPrev;
2931 uint16_t padding1;
2932 /** Ring-0 stack pointer. (static) */
2933 uint32_t esp0;
2934 /** Ring-0 stack segment. (static) */
2935 RTSEL ss0;
2936 uint16_t padding_ss0;
2937 /** Ring-1 stack pointer. (static) */
2938 uint32_t esp1;
2939 /** Ring-1 stack segment. (static) */
2940 RTSEL ss1;
2941 uint16_t padding_ss1;
2942 /** Ring-2 stack pointer. (static) */
2943 uint32_t esp2;
2944 /** Ring-2 stack segment. (static) */
2945 RTSEL ss2;
2946 uint16_t padding_ss2;
2947 /** Page directory for the task. (static) */
2948 uint32_t cr3;
2949 /** EIP before task switch. */
2950 uint32_t eip;
2951 /** EFLAGS before task switch. */
2952 uint32_t eflags;
2953 /** EAX before task switch. */
2954 uint32_t eax;
2955 /** ECX before task switch. */
2956 uint32_t ecx;
2957 /** EDX before task switch. */
2958 uint32_t edx;
2959 /** EBX before task switch. */
2960 uint32_t ebx;
2961 /** ESP before task switch. */
2962 uint32_t esp;
2963 /** EBP before task switch. */
2964 uint32_t ebp;
2965 /** ESI before task switch. */
2966 uint32_t esi;
2967 /** EDI before task switch. */
2968 uint32_t edi;
2969 /** ES before task switch. */
2970 RTSEL es;
2971 uint16_t padding_es;
2972 /** CS before task switch. */
2973 RTSEL cs;
2974 uint16_t padding_cs;
2975 /** SS before task switch. */
2976 RTSEL ss;
2977 uint16_t padding_ss;
2978 /** DS before task switch. */
2979 RTSEL ds;
2980 uint16_t padding_ds;
2981 /** FS before task switch. */
2982 RTSEL fs;
2983 uint16_t padding_fs;
2984 /** GS before task switch. */
2985 RTSEL gs;
2986 uint16_t padding_gs;
2987 /** LDTR before task switch. */
2988 RTSEL selLdt;
2989 uint16_t padding_ldt;
2990 /** Debug trap flag */
2991 uint16_t fDebugTrap;
2992 /** Offset relative to the TSS of the start of the I/O Bitmap
2993 * and the end of the interrupt redirection bitmap. */
2994 uint16_t offIoBitmap;
2995 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2996 uint8_t IntRedirBitmap[32];
2997} X86TSS32;
2998#pragma pack()
2999/** Pointer to task segment. */
3000typedef X86TSS32 *PX86TSS32;
3001/** Pointer to const task segment. */
3002typedef const X86TSS32 *PCX86TSS32;
3003
3004
3005/**
3006 * 64-bit Task segment.
3007 */
3008#pragma pack(1)
3009typedef struct X86TSS64
3010{
3011 /** Reserved. */
3012 uint32_t u32Reserved;
3013 /** Ring-0 stack pointer. (static) */
3014 uint64_t rsp0;
3015 /** Ring-1 stack pointer. (static) */
3016 uint64_t rsp1;
3017 /** Ring-2 stack pointer. (static) */
3018 uint64_t rsp2;
3019 /** Reserved. */
3020 uint32_t u32Reserved2[2];
3021 /* IST */
3022 uint64_t ist1;
3023 uint64_t ist2;
3024 uint64_t ist3;
3025 uint64_t ist4;
3026 uint64_t ist5;
3027 uint64_t ist6;
3028 uint64_t ist7;
3029 /* Reserved. */
3030 uint16_t u16Reserved[5];
3031 /** Offset relative to the TSS of the start of the I/O Bitmap
3032 * and the end of the interrupt redirection bitmap. */
3033 uint16_t offIoBitmap;
3034 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3035 uint8_t IntRedirBitmap[32];
3036} X86TSS64;
3037#pragma pack()
3038/** Pointer to a 64-bit task segment. */
3039typedef X86TSS64 *PX86TSS64;
3040/** Pointer to a const 64-bit task segment. */
3041typedef const X86TSS64 *PCX86TSS64;
3042#ifndef VBOX_FOR_DTRACE_LIB
3043AssertCompileSize(X86TSS64, 136);
3044#endif
3045
3046/** @} */
3047
3048
3049/** @name Selectors.
3050 * @{
3051 */
3052
3053/**
3054 * The shift used to convert a selector from and to index an index (C).
3055 */
3056#define X86_SEL_SHIFT 3
3057
3058/**
3059 * The mask used to mask off the table indicator and RPL of an selector.
3060 */
3061#define X86_SEL_MASK 0xfff8U
3062
3063/**
3064 * The mask used to mask off the RPL of an selector.
3065 * This is suitable for checking for NULL selectors.
3066 */
3067#define X86_SEL_MASK_OFF_RPL 0xfffcU
3068
3069/**
3070 * The bit indicating that a selector is in the LDT and not in the GDT.
3071 */
3072#define X86_SEL_LDT 0x0004U
3073
3074/**
3075 * The bit mask for getting the RPL of a selector.
3076 */
3077#define X86_SEL_RPL 0x0003U
3078
3079/**
3080 * The mask covering both RPL and LDT.
3081 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3082 * checks.
3083 */
3084#define X86_SEL_RPL_LDT 0x0007U
3085
3086/** @} */
3087
3088
3089/**
3090 * x86 Exceptions/Faults/Traps.
3091 */
3092typedef enum X86XCPT
3093{
3094 /** \#DE - Divide error. */
3095 X86_XCPT_DE = 0x00,
3096 /** \#DB - Debug event (single step, DRx, ..) */
3097 X86_XCPT_DB = 0x01,
3098 /** NMI - Non-Maskable Interrupt */
3099 X86_XCPT_NMI = 0x02,
3100 /** \#BP - Breakpoint (INT3). */
3101 X86_XCPT_BP = 0x03,
3102 /** \#OF - Overflow (INTO). */
3103 X86_XCPT_OF = 0x04,
3104 /** \#BR - Bound range exceeded (BOUND). */
3105 X86_XCPT_BR = 0x05,
3106 /** \#UD - Undefined opcode. */
3107 X86_XCPT_UD = 0x06,
3108 /** \#NM - Device not available (math coprocessor device). */
3109 X86_XCPT_NM = 0x07,
3110 /** \#DF - Double fault. */
3111 X86_XCPT_DF = 0x08,
3112 /** ??? - Coprocessor segment overrun (obsolete). */
3113 X86_XCPT_CO_SEG_OVERRUN = 0x09,
3114 /** \#TS - Taskswitch (TSS). */
3115 X86_XCPT_TS = 0x0a,
3116 /** \#NP - Segment no present. */
3117 X86_XCPT_NP = 0x0b,
3118 /** \#SS - Stack segment fault. */
3119 X86_XCPT_SS = 0x0c,
3120 /** \#GP - General protection fault. */
3121 X86_XCPT_GP = 0x0d,
3122 /** \#PF - Page fault. */
3123 X86_XCPT_PF = 0x0e,
3124 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3125 /** \#MF - Math fault (FPU). */
3126 X86_XCPT_MF = 0x10,
3127 /** \#AC - Alignment check. */
3128 X86_XCPT_AC = 0x11,
3129 /** \#MC - Machine check. */
3130 X86_XCPT_MC = 0x12,
3131 /** \#XF - SIMD Floating-Pointer Exception. */
3132 X86_XCPT_XF = 0x13,
3133 /** \#VE - Virtualzation Exception. */
3134 X86_XCPT_VE = 0x14,
3135 /** \#SX - Security Exception. */
3136 X86_XCPT_SX = 0x1f
3137} X86XCPT;
3138/** Pointer to a x86 exception code. */
3139typedef X86XCPT *PX86XCPT;
3140/** Pointer to a const x86 exception code. */
3141typedef const X86XCPT *PCX86XCPT;
3142/** The maximum exception value. */
3143#define X86_XCPT_MAX (X86_XCPT_SX)
3144
3145
3146/** @name Trap Error Codes
3147 * @{
3148 */
3149/** External indicator. */
3150#define X86_TRAP_ERR_EXTERNAL 1
3151/** IDT indicator. */
3152#define X86_TRAP_ERR_IDT 2
3153/** Descriptor table indicator - If set LDT, if clear GDT. */
3154#define X86_TRAP_ERR_TI 4
3155/** Mask for getting the selector. */
3156#define X86_TRAP_ERR_SEL_MASK 0xfff8
3157/** Shift for getting the selector table index (C type index). */
3158#define X86_TRAP_ERR_SEL_SHIFT 3
3159/** @} */
3160
3161
3162/** @name \#PF Trap Error Codes
3163 * @{
3164 */
3165/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3166#define X86_TRAP_PF_P RT_BIT(0)
3167/** Bit 1 - R/W - Read (clear) or write (set) access. */
3168#define X86_TRAP_PF_RW RT_BIT(1)
3169/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3170#define X86_TRAP_PF_US RT_BIT(2)
3171/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3172#define X86_TRAP_PF_RSVD RT_BIT(3)
3173/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3174#define X86_TRAP_PF_ID RT_BIT(4)
3175/** @} */
3176
3177#pragma pack(1)
3178/**
3179 * 32-bit IDTR/GDTR.
3180 */
3181typedef struct X86XDTR32
3182{
3183 /** Size of the descriptor table. */
3184 uint16_t cb;
3185 /** Address of the descriptor table. */
3186#ifndef VBOX_FOR_DTRACE_LIB
3187 uint32_t uAddr;
3188#else
3189 uint16_t au16Addr[2];
3190#endif
3191} X86XDTR32, *PX86XDTR32;
3192#pragma pack()
3193
3194#pragma pack(1)
3195/**
3196 * 64-bit IDTR/GDTR.
3197 */
3198typedef struct X86XDTR64
3199{
3200 /** Size of the descriptor table. */
3201 uint16_t cb;
3202 /** Address of the descriptor table. */
3203#ifndef VBOX_FOR_DTRACE_LIB
3204 uint64_t uAddr;
3205#else
3206 uint16_t au16Addr[4];
3207#endif
3208} X86XDTR64, *PX86XDTR64;
3209#pragma pack()
3210
3211
3212/** @name ModR/M
3213 * @{ */
3214#define X86_MODRM_RM_MASK UINT8_C(0x07)
3215#define X86_MODRM_REG_MASK UINT8_C(0x38)
3216#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3217#define X86_MODRM_REG_SHIFT 3
3218#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3219#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3220#define X86_MODRM_MOD_SHIFT 6
3221#ifndef VBOX_FOR_DTRACE_LIB
3222AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
3223AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3224AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3225#endif
3226/** @} */
3227
3228/** @name SIB
3229 * @{ */
3230#define X86_SIB_BASE_MASK UINT8_C(0x07)
3231#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3232#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3233#define X86_SIB_INDEX_SHIFT 3
3234#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3235#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3236#define X86_SIB_SCALE_SHIFT 6
3237#ifndef VBOX_FOR_DTRACE_LIB
3238AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
3239AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3240AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3241#endif
3242/** @} */
3243
3244/** @name General register indexes
3245 * @{ */
3246#define X86_GREG_xAX 0
3247#define X86_GREG_xCX 1
3248#define X86_GREG_xDX 2
3249#define X86_GREG_xBX 3
3250#define X86_GREG_xSP 4
3251#define X86_GREG_xBP 5
3252#define X86_GREG_xSI 6
3253#define X86_GREG_xDI 7
3254#define X86_GREG_x8 8
3255#define X86_GREG_x9 9
3256#define X86_GREG_x10 10
3257#define X86_GREG_x11 11
3258#define X86_GREG_x12 12
3259#define X86_GREG_x13 13
3260#define X86_GREG_x14 14
3261#define X86_GREG_x15 15
3262/** @} */
3263
3264/** @name X86_SREG_XXX - Segment register indexes.
3265 * @{ */
3266#define X86_SREG_ES 0
3267#define X86_SREG_CS 1
3268#define X86_SREG_SS 2
3269#define X86_SREG_DS 3
3270#define X86_SREG_FS 4
3271#define X86_SREG_GS 5
3272/** @} */
3273/** Segment register count. */
3274#define X86_SREG_COUNT 6
3275
3276
3277/** @name X86_OP_XXX - Prefixes
3278 * @{ */
3279#define X86_OP_PRF_CS UINT8_C(0x2e)
3280#define X86_OP_PRF_SS UINT8_C(0x36)
3281#define X86_OP_PRF_DS UINT8_C(0x3e)
3282#define X86_OP_PRF_ES UINT8_C(0x26)
3283#define X86_OP_PRF_FS UINT8_C(0x64)
3284#define X86_OP_PRF_GS UINT8_C(0x65)
3285#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3286#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3287#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3288#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3289#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3290#define X86_OP_REX_B UINT8_C(0x41)
3291#define X86_OP_REX_X UINT8_C(0x42)
3292#define X86_OP_REX_R UINT8_C(0x44)
3293#define X86_OP_REX_W UINT8_C(0x48)
3294/** @} */
3295
3296
3297/** @} */
3298
3299#endif
3300
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