VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 47540

Last change on this file since 47540 was 47432, checked in by vboxsync, 12 years ago

HMR0VMX.cpp: Attempt to fix incorrect DR7 and DR[0-3] checks in I/O port path.
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2012 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT(0)
164/** Bit 1 - Reserved, reads as 1. */
165#define X86_EFL_1 RT_BIT(1)
166/** Bit 2 - PF - Parity flag - Status flag. */
167#define X86_EFL_PF RT_BIT(2)
168/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169#define X86_EFL_AF RT_BIT(4)
170/** Bit 6 - ZF - Zero flag - Status flag. */
171#define X86_EFL_ZF RT_BIT(6)
172/** Bit 7 - SF - Signed flag - Status flag. */
173#define X86_EFL_SF RT_BIT(7)
174/** Bit 8 - TF - Trap flag - System flag. */
175#define X86_EFL_TF RT_BIT(8)
176/** Bit 9 - IF - Interrupt flag - System flag. */
177#define X86_EFL_IF RT_BIT(9)
178/** Bit 10 - DF - Direction flag - Control flag. */
179#define X86_EFL_DF RT_BIT(10)
180/** Bit 11 - OF - Overflow flag - Status flag. */
181#define X86_EFL_OF RT_BIT(11)
182/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
184/** Bit 14 - NT - Nested task flag - System flag. */
185#define X86_EFL_NT RT_BIT(14)
186/** Bit 16 - RF - Resume flag - System flag. */
187#define X86_EFL_RF RT_BIT(16)
188/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189#define X86_EFL_VM RT_BIT(17)
190/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191#define X86_EFL_AC RT_BIT(18)
192/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193#define X86_EFL_VIF RT_BIT(19)
194/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195#define X86_EFL_VIP RT_BIT(20)
196/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197#define X86_EFL_ID RT_BIT(21)
198/** IOPL shift. */
199#define X86_EFL_IOPL_SHIFT 12
200/** The the IOPL level from the flags. */
201#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
202/** Bits restored by popf */
203#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
204 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
205/** @} */
206
207
208/** CPUID Feature information - ECX.
209 * CPUID query with EAX=1.
210 */
211#ifndef VBOX_FOR_DTRACE_LIB
212typedef struct X86CPUIDFEATECX
213{
214 /** Bit 0 - SSE3 - Supports SSE3 or not. */
215 unsigned u1SSE3 : 1;
216 /** Bit 1 - PCLMULQDQ. */
217 unsigned u1PCLMULQDQ : 1;
218 /** Bit 2 - DS Area 64-bit layout. */
219 unsigned u1DTE64 : 1;
220 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
221 unsigned u1Monitor : 1;
222 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
223 unsigned u1CPLDS : 1;
224 /** Bit 5 - VMX - Virtual Machine Technology. */
225 unsigned u1VMX : 1;
226 /** Bit 6 - SMX: Safer Mode Extensions. */
227 unsigned u1SMX : 1;
228 /** Bit 7 - EST - Enh. SpeedStep Tech. */
229 unsigned u1EST : 1;
230 /** Bit 8 - TM2 - Terminal Monitor 2. */
231 unsigned u1TM2 : 1;
232 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
233 unsigned u1SSSE3 : 1;
234 /** Bit 10 - CNTX-ID - L1 Context ID. */
235 unsigned u1CNTXID : 1;
236 /** Bit 11 - Reserved. */
237 unsigned u1Reserved1 : 1;
238 /** Bit 12 - FMA. */
239 unsigned u1FMA : 1;
240 /** Bit 13 - CX16 - CMPXCHG16B. */
241 unsigned u1CX16 : 1;
242 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
243 unsigned u1TPRUpdate : 1;
244 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
245 unsigned u1PDCM : 1;
246 /** Bit 16 - Reserved. */
247 unsigned u1Reserved2 : 1;
248 /** Bit 17 - PCID - Process-context identifiers. */
249 unsigned u1PCID : 1;
250 /** Bit 18 - Direct Cache Access. */
251 unsigned u1DCA : 1;
252 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
253 unsigned u1SSE4_1 : 1;
254 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
255 unsigned u1SSE4_2 : 1;
256 /** Bit 21 - x2APIC. */
257 unsigned u1x2APIC : 1;
258 /** Bit 22 - MOVBE - Supports MOVBE. */
259 unsigned u1MOVBE : 1;
260 /** Bit 23 - POPCNT - Supports POPCNT. */
261 unsigned u1POPCNT : 1;
262 /** Bit 24 - TSC-Deadline. */
263 unsigned u1TSCDEADLINE : 1;
264 /** Bit 25 - AES. */
265 unsigned u1AES : 1;
266 /** Bit 26 - XSAVE - Supports XSAVE. */
267 unsigned u1XSAVE : 1;
268 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
269 unsigned u1OSXSAVE : 1;
270 /** Bit 28 - AVX - Supports AVX instruction extensions. */
271 unsigned u1AVX : 1;
272 /** Bit 29 - 30 - Reserved */
273 unsigned u2Reserved3 : 2;
274 /** Bit 31 - Hypervisor present (we're a guest). */
275 unsigned u1HVP : 1;
276} X86CPUIDFEATECX;
277#else /* VBOX_FOR_DTRACE_LIB */
278typedef uint32_t X86CPUIDFEATECX;
279#endif /* VBOX_FOR_DTRACE_LIB */
280/** Pointer to CPUID Feature Information - ECX. */
281typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
282/** Pointer to const CPUID Feature Information - ECX. */
283typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
284
285
286/** CPUID Feature Information - EDX.
287 * CPUID query with EAX=1.
288 */
289#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
290typedef struct X86CPUIDFEATEDX
291{
292 /** Bit 0 - FPU - x87 FPU on Chip. */
293 unsigned u1FPU : 1;
294 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
295 unsigned u1VME : 1;
296 /** Bit 2 - DE - Debugging extensions. */
297 unsigned u1DE : 1;
298 /** Bit 3 - PSE - Page Size Extension. */
299 unsigned u1PSE : 1;
300 /** Bit 4 - TSC - Time Stamp Counter. */
301 unsigned u1TSC : 1;
302 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
303 unsigned u1MSR : 1;
304 /** Bit 6 - PAE - Physical Address Extension. */
305 unsigned u1PAE : 1;
306 /** Bit 7 - MCE - Machine Check Exception. */
307 unsigned u1MCE : 1;
308 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
309 unsigned u1CX8 : 1;
310 /** Bit 9 - APIC - APIC On-Chip. */
311 unsigned u1APIC : 1;
312 /** Bit 10 - Reserved. */
313 unsigned u1Reserved1 : 1;
314 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
315 unsigned u1SEP : 1;
316 /** Bit 12 - MTRR - Memory Type Range Registers. */
317 unsigned u1MTRR : 1;
318 /** Bit 13 - PGE - PTE Global Bit. */
319 unsigned u1PGE : 1;
320 /** Bit 14 - MCA - Machine Check Architecture. */
321 unsigned u1MCA : 1;
322 /** Bit 15 - CMOV - Conditional Move Instructions. */
323 unsigned u1CMOV : 1;
324 /** Bit 16 - PAT - Page Attribute Table. */
325 unsigned u1PAT : 1;
326 /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
327 unsigned u1PSE36 : 1;
328 /** Bit 18 - PSN - Processor Serial Number. */
329 unsigned u1PSN : 1;
330 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
331 unsigned u1CLFSH : 1;
332 /** Bit 20 - Reserved. */
333 unsigned u1Reserved2 : 1;
334 /** Bit 21 - DS - Debug Store. */
335 unsigned u1DS : 1;
336 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
337 unsigned u1ACPI : 1;
338 /** Bit 23 - MMX - Intel MMX 'Technology'. */
339 unsigned u1MMX : 1;
340 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
341 unsigned u1FXSR : 1;
342 /** Bit 25 - SSE - SSE Support. */
343 unsigned u1SSE : 1;
344 /** Bit 26 - SSE2 - SSE2 Support. */
345 unsigned u1SSE2 : 1;
346 /** Bit 27 - SS - Self Snoop. */
347 unsigned u1SS : 1;
348 /** Bit 28 - HTT - Hyper-Threading Technology. */
349 unsigned u1HTT : 1;
350 /** Bit 29 - TM - Thermal Monitor. */
351 unsigned u1TM : 1;
352 /** Bit 30 - Reserved - . */
353 unsigned u1Reserved3 : 1;
354 /** Bit 31 - PBE - Pending Break Enabled. */
355 unsigned u1PBE : 1;
356} X86CPUIDFEATEDX;
357#else /* VBOX_FOR_DTRACE_LIB */
358typedef uint32_t X86CPUIDFEATEDX;
359#endif /* VBOX_FOR_DTRACE_LIB */
360/** Pointer to CPUID Feature Information - EDX. */
361typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
362/** Pointer to const CPUID Feature Information - EDX. */
363typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
364
365/** @name CPUID Vendor information.
366 * CPUID query with EAX=0.
367 * @{
368 */
369#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
370#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
371#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
372
373#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
374#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
375#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
376
377#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
378#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
379#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
380/** @} */
381
382
383/** @name CPUID Feature information.
384 * CPUID query with EAX=1.
385 * @{
386 */
387/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
388#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
389/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
390#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
391/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
392#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
393/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
394#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
395/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
396#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
397/** ECX Bit 5 - VMX - Virtual Machine Technology. */
398#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
399/** ECX Bit 6 - SMX - Safer Mode Extensions. */
400#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
401/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
402#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
403/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
404#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
405/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
406#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
407/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
408#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
409/** ECX Bit 12 - FMA. */
410#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
411/** ECX Bit 13 - CX16 - CMPXCHG16B. */
412#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
413/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
414#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
415/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
416#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
417/** ECX Bit 17 - PCID - Process-context identifiers. */
418#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
419/** ECX Bit 18 - DCA - Direct Cache Access. */
420#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
421/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
422#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
423/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
424#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
425/** ECX Bit 21 - x2APIC support. */
426#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
427/** ECX Bit 22 - MOVBE instruction. */
428#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
429/** ECX Bit 23 - POPCNT instruction. */
430#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
431/** ECX Bir 24 - TSC-Deadline. */
432#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
433/** ECX Bit 25 - AES instructions. */
434#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
435/** ECX Bit 26 - XSAVE instruction. */
436#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
437/** ECX Bit 27 - OSXSAVE instruction. */
438#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
439/** ECX Bit 28 - AVX. */
440#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
441/** ECX Bit 31 - Hypervisor Present (software only). */
442#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
443
444
445/** Bit 0 - FPU - x87 FPU on Chip. */
446#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
447/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
448#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
449/** Bit 2 - DE - Debugging extensions. */
450#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
451/** Bit 3 - PSE - Page Size Extension. */
452#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
453/** Bit 4 - TSC - Time Stamp Counter. */
454#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
455/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
456#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
457/** Bit 6 - PAE - Physical Address Extension. */
458#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
459/** Bit 7 - MCE - Machine Check Exception. */
460#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
461/** Bit 8 - CX8 - CMPXCHG8B instruction. */
462#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
463/** Bit 9 - APIC - APIC On-Chip. */
464#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
465/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
466#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
467/** Bit 12 - MTRR - Memory Type Range Registers. */
468#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
469/** Bit 13 - PGE - PTE Global Bit. */
470#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
471/** Bit 14 - MCA - Machine Check Architecture. */
472#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
473/** Bit 15 - CMOV - Conditional Move Instructions. */
474#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
475/** Bit 16 - PAT - Page Attribute Table. */
476#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
477/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
478#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
479/** Bit 18 - PSN - Processor Serial Number. */
480#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
481/** Bit 19 - CLFSH - CLFLUSH Instruction. */
482#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
483/** Bit 21 - DS - Debug Store. */
484#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
485/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
486#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
487/** Bit 23 - MMX - Intel MMX Technology. */
488#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
489/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
490#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
491/** Bit 25 - SSE - SSE Support. */
492#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
493/** Bit 26 - SSE2 - SSE2 Support. */
494#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
495/** Bit 27 - SS - Self Snoop. */
496#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
497/** Bit 28 - HTT - Hyper-Threading Technology. */
498#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
499/** Bit 29 - TM - Therm. Monitor. */
500#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
501/** Bit 31 - PBE - Pending Break Enabled. */
502#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
503/** @} */
504
505/** @name CPUID mwait/monitor information.
506 * CPUID query with EAX=5.
507 * @{
508 */
509/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
510#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
511/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
512#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
513/** @} */
514
515
516/** @name CPUID Extended Feature information.
517 * CPUID query with EAX=0x80000001.
518 * @{
519 */
520/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
521#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
522
523/** EDX Bit 11 - SYSCALL/SYSRET. */
524#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
525/** EDX Bit 20 - No-Execute/Execute-Disable. */
526#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
527/** EDX Bit 26 - 1 GB large page. */
528#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
529/** EDX Bit 27 - RDTSCP. */
530#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
531/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
532#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
533/** @}*/
534
535/** @name CPUID AMD Feature information.
536 * CPUID query with EAX=0x80000001.
537 * @{
538 */
539/** Bit 0 - FPU - x87 FPU on Chip. */
540#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
541/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
542#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
543/** Bit 2 - DE - Debugging extensions. */
544#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
545/** Bit 3 - PSE - Page Size Extension. */
546#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
547/** Bit 4 - TSC - Time Stamp Counter. */
548#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
549/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
550#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
551/** Bit 6 - PAE - Physical Address Extension. */
552#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
553/** Bit 7 - MCE - Machine Check Exception. */
554#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
555/** Bit 8 - CX8 - CMPXCHG8B instruction. */
556#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
557/** Bit 9 - APIC - APIC On-Chip. */
558#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
559/** Bit 12 - MTRR - Memory Type Range Registers. */
560#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
561/** Bit 13 - PGE - PTE Global Bit. */
562#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
563/** Bit 14 - MCA - Machine Check Architecture. */
564#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
565/** Bit 15 - CMOV - Conditional Move Instructions. */
566#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
567/** Bit 16 - PAT - Page Attribute Table. */
568#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
569/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
570#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
571/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
572#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
573/** Bit 23 - MMX - Intel MMX Technology. */
574#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
575/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
576#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
577/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
578#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
579/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
580#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
581/** Bit 31 - 3DNOW - AMD 3DNow. */
582#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
583
584/** Bit 1 - CMPL - Core multi-processing legacy mode. */
585#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
586/** Bit 2 - SVM - AMD VM extensions. */
587#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
588/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
589#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
590/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
591#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
592/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
593#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
594/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
595#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
596/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
597#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
598/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
599#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
600/** Bit 9 - OSVW - AMD OS visible workaround. */
601#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
602/** Bit 10 - IBS - Instruct based sampling. */
603#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
604/** Bit 11 - SSE5 - SSE5 instruction support. */
605#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
606/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
607#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
608/** Bit 13 - WDT - AMD Watchdog timer support. */
609#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
610
611/** @} */
612
613
614/** @name CPUID AMD Feature information.
615 * CPUID query with EAX=0x80000007.
616 * @{
617 */
618/** Bit 0 - TS - Temperature Sensor. */
619#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
620/** Bit 1 - FID - Frequency ID Control. */
621#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
622/** Bit 2 - VID - Voltage ID Control. */
623#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
624/** Bit 3 - TTP - THERMTRIP. */
625#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
626/** Bit 4 - TM - Hardware Thermal Control. */
627#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
628/** Bit 5 - STC - Software Thermal Control. */
629#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
630/** Bit 6 - MC - 100 Mhz Multiplier Control. */
631#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
632/** Bit 7 - HWPSTATE - Hardware P-State Control. */
633#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
634/** Bit 8 - TSCINVAR - TSC Invariant. */
635#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
636/** @} */
637
638
639/** @name CR0
640 * @{ */
641/** Bit 0 - PE - Protection Enabled */
642#define X86_CR0_PE RT_BIT(0)
643#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
644/** Bit 1 - MP - Monitor Coprocessor */
645#define X86_CR0_MP RT_BIT(1)
646#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
647/** Bit 2 - EM - Emulation. */
648#define X86_CR0_EM RT_BIT(2)
649#define X86_CR0_EMULATE_FPU RT_BIT(2)
650/** Bit 3 - TS - Task Switch. */
651#define X86_CR0_TS RT_BIT(3)
652#define X86_CR0_TASK_SWITCH RT_BIT(3)
653/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
654#define X86_CR0_ET RT_BIT(4)
655#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
656/** Bit 5 - NE - Numeric error. */
657#define X86_CR0_NE RT_BIT(5)
658#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
659/** Bit 16 - WP - Write Protect. */
660#define X86_CR0_WP RT_BIT(16)
661#define X86_CR0_WRITE_PROTECT RT_BIT(16)
662/** Bit 18 - AM - Alignment Mask. */
663#define X86_CR0_AM RT_BIT(18)
664#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
665/** Bit 29 - NW - Not Write-though. */
666#define X86_CR0_NW RT_BIT(29)
667#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
668/** Bit 30 - WP - Cache Disable. */
669#define X86_CR0_CD RT_BIT(30)
670#define X86_CR0_CACHE_DISABLE RT_BIT(30)
671/** Bit 31 - PG - Paging. */
672#define X86_CR0_PG RT_BIT(31)
673#define X86_CR0_PAGING RT_BIT(31)
674/** @} */
675
676
677/** @name CR3
678 * @{ */
679/** Bit 3 - PWT - Page-level Writes Transparent. */
680#define X86_CR3_PWT RT_BIT(3)
681/** Bit 4 - PCD - Page-level Cache Disable. */
682#define X86_CR3_PCD RT_BIT(4)
683/** Bits 12-31 - - Page directory page number. */
684#define X86_CR3_PAGE_MASK (0xfffff000)
685/** Bits 5-31 - - PAE Page directory page number. */
686#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
687/** Bits 12-51 - - AMD64 Page directory page number. */
688#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
689/** @} */
690
691
692/** @name CR4
693 * @{ */
694/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
695#define X86_CR4_VME RT_BIT(0)
696/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
697#define X86_CR4_PVI RT_BIT(1)
698/** Bit 2 - TSD - Time Stamp Disable. */
699#define X86_CR4_TSD RT_BIT(2)
700/** Bit 3 - DE - Debugging Extensions. */
701#define X86_CR4_DE RT_BIT(3)
702/** Bit 4 - PSE - Page Size Extension. */
703#define X86_CR4_PSE RT_BIT(4)
704/** Bit 5 - PAE - Physical Address Extension. */
705#define X86_CR4_PAE RT_BIT(5)
706/** Bit 6 - MCE - Machine-Check Enable. */
707#define X86_CR4_MCE RT_BIT(6)
708/** Bit 7 - PGE - Page Global Enable. */
709#define X86_CR4_PGE RT_BIT(7)
710/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
711#define X86_CR4_PCE RT_BIT(8)
712/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
713#define X86_CR4_OSFSXR RT_BIT(9)
714/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
715#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
716/** Bit 13 - VMXE - VMX mode is enabled. */
717#define X86_CR4_VMXE RT_BIT(13)
718/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
719#define X86_CR4_SMXE RT_BIT(14)
720/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
721#define X86_CR4_PCIDE RT_BIT(17)
722/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
723 * extended states. */
724#define X86_CR4_OSXSAVE RT_BIT(18)
725/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
726#define X86_CR4_SMEP RT_BIT(20)
727/** @} */
728
729
730/** @name DR6
731 * @{ */
732/** Bit 0 - B0 - Breakpoint 0 condition detected. */
733#define X86_DR6_B0 RT_BIT(0)
734/** Bit 1 - B1 - Breakpoint 1 condition detected. */
735#define X86_DR6_B1 RT_BIT(1)
736/** Bit 2 - B2 - Breakpoint 2 condition detected. */
737#define X86_DR6_B2 RT_BIT(2)
738/** Bit 3 - B3 - Breakpoint 3 condition detected. */
739#define X86_DR6_B3 RT_BIT(3)
740/** Mask of all the Bx bits. */
741#define X86_DR6_B_MASK UINT64_C(0x0000000f)
742/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
743#define X86_DR6_BD RT_BIT(13)
744/** Bit 14 - BS - Single step */
745#define X86_DR6_BS RT_BIT(14)
746/** Bit 15 - BT - Task switch. (TSS T bit.) */
747#define X86_DR6_BT RT_BIT(15)
748/** Value of DR6 after powerup/reset. */
749#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
750/** Bits which must be 1s in DR6. */
751#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
752/** Bits which must be 0s in DR6. */
753#define X86_DR6_RAZ_MASK RT_BIT_64(12)
754/** Bits which must be 0s on writes to DR6. */
755#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
756/** @} */
757
758/** Get the DR6.Bx bit for a the given breakpoint. */
759#define X86_DR6_B(iBp) RT_BIT_64(iBp)
760
761
762/** @name DR7
763 * @{ */
764/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
765#define X86_DR7_L0 RT_BIT(0)
766/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
767#define X86_DR7_G0 RT_BIT(1)
768/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
769#define X86_DR7_L1 RT_BIT(2)
770/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
771#define X86_DR7_G1 RT_BIT(3)
772/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
773#define X86_DR7_L2 RT_BIT(4)
774/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
775#define X86_DR7_G2 RT_BIT(5)
776/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
777#define X86_DR7_L3 RT_BIT(6)
778/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
779#define X86_DR7_G3 RT_BIT(7)
780/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
781#define X86_DR7_LE RT_BIT(8)
782/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
783#define X86_DR7_GE RT_BIT(9)
784
785/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
786 * any DR register is accessed. */
787#define X86_DR7_GD RT_BIT(13)
788/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
789#define X86_DR7_RW0_MASK (3 << 16)
790/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
791#define X86_DR7_LEN0_MASK (3 << 18)
792/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
793#define X86_DR7_RW1_MASK (3 << 20)
794/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
795#define X86_DR7_LEN1_MASK (3 << 22)
796/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
797#define X86_DR7_RW2_MASK (3 << 24)
798/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
799#define X86_DR7_LEN2_MASK (3 << 26)
800/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
801#define X86_DR7_RW3_MASK (3 << 28)
802/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
803#define X86_DR7_LEN3_MASK (3 << 30)
804
805/** Bits which reads as 1s. */
806#define X86_DR7_RA1_MASK (RT_BIT(10))
807/** Bits which reads as zeros. */
808#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
809/** Bits which must be 0s when writing to DR7. */
810#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
811
812/** Calcs the L bit of Nth breakpoint.
813 * @param iBp The breakpoint number [0..3].
814 */
815#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
816
817/** Calcs the G bit of Nth breakpoint.
818 * @param iBp The breakpoint number [0..3].
819 */
820#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
821
822/** Calcs the L and G bits of Nth breakpoint.
823 * @param iBp The breakpoint number [0..3].
824 */
825#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
826
827/** @name Read/Write values.
828 * @{ */
829/** Break on instruction fetch only. */
830#define X86_DR7_RW_EO 0U
831/** Break on write only. */
832#define X86_DR7_RW_WO 1U
833/** Break on I/O read/write. This is only defined if CR4.DE is set. */
834#define X86_DR7_RW_IO 2U
835/** Break on read or write (but not instruction fetches). */
836#define X86_DR7_RW_RW 3U
837/** @} */
838
839/** Shifts a X86_DR7_RW_* value to its right place.
840 * @param iBp The breakpoint number [0..3].
841 * @param fRw One of the X86_DR7_RW_* value.
842 */
843#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
844
845/** Fetch the the R/Wx bits for a given breakpoint (so it can be compared with
846 * one of the X86_DR7_RW_XXX constants).
847 *
848 * @returns X86_DR7_RW_XXX
849 * @param uDR7 DR7 value
850 * @param iBp The breakpoint number [0..3].
851 */
852#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
853
854/** R/W0, R/W1, R/W2, and R/W3. */
855#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
856
857/** Checks if there are any I/O breakpoint types configured in the RW
858 * registers. Does NOT check if these are enabled, sorry. */
859#define X86_DR7_ANY_RW_IO(uDR7) \
860 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
861 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
862AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
863AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
864AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
865AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
866AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
867AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
868AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
869AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
870AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
871
872/** @name Length values.
873 * @{ */
874#define X86_DR7_LEN_BYTE 0U
875#define X86_DR7_LEN_WORD 1U
876#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
877#define X86_DR7_LEN_DWORD 3U
878/** @} */
879
880/** Shifts a X86_DR7_LEN_* value to its right place.
881 * @param iBp The breakpoint number [0..3].
882 * @param cb One of the X86_DR7_LEN_* values.
883 */
884#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
885
886/** Fetch the breakpoint length bits from the DR7 value.
887 * @param uDR7 DR7 value
888 * @param iBp The breakpoint number [0..3].
889 */
890#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
891
892/** Mask used to check if any breakpoints are enabled. */
893#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
894
895/** Value of DR7 after powerup/reset. */
896#define X86_DR7_INIT_VAL 0x400
897/** @} */
898
899
900/** @name Machine Specific Registers
901 * @{
902 */
903
904/** Time Stamp Counter. */
905#define MSR_IA32_TSC 0x10
906
907#define MSR_IA32_PLATFORM_ID 0x17
908
909#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
910#define MSR_IA32_APICBASE 0x1b
911#endif
912
913/** CPU Feature control. */
914#define MSR_IA32_FEATURE_CONTROL 0x3A
915#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
916#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
917
918/** BIOS update trigger (microcode update). */
919#define MSR_IA32_BIOS_UPDT_TRIG 0x79
920
921/** BIOS update signature (microcode). */
922#define MSR_IA32_BIOS_SIGN_ID 0x8B
923
924/** General performance counter no. 0. */
925#define MSR_IA32_PMC0 0xC1
926/** General performance counter no. 1. */
927#define MSR_IA32_PMC1 0xC2
928/** General performance counter no. 2. */
929#define MSR_IA32_PMC2 0xC3
930/** General performance counter no. 3. */
931#define MSR_IA32_PMC3 0xC4
932
933/** Nehalem power control. */
934#define MSR_IA32_PLATFORM_INFO 0xCE
935
936/** Get FSB clock status (Intel-specific). */
937#define MSR_IA32_FSB_CLOCK_STS 0xCD
938
939/** MTRR Capabilities. */
940#define MSR_IA32_MTRR_CAP 0xFE
941
942
943#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
944/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
945 * R0 SS == CS + 8
946 * R3 CS == CS + 16
947 * R3 SS == CS + 24
948 */
949#define MSR_IA32_SYSENTER_CS 0x174
950/** SYSENTER_ESP - the R0 ESP. */
951#define MSR_IA32_SYSENTER_ESP 0x175
952/** SYSENTER_EIP - the R0 EIP. */
953#define MSR_IA32_SYSENTER_EIP 0x176
954#endif
955
956/** Machine Check Global Capabilities Register. */
957#define MSR_IA32_MCP_CAP 0x179
958/** Machine Check Global Status Register. */
959#define MSR_IA32_MCP_STATUS 0x17A
960/** Machine Check Global Control Register. */
961#define MSR_IA32_MCP_CTRL 0x17B
962
963/** Trace/Profile Resource Control (R/W) */
964#define MSR_IA32_DEBUGCTL 0x1D9
965
966/** Page Attribute Table. */
967#define MSR_IA32_CR_PAT 0x277
968
969/** Performance counter MSRs. (Intel only) */
970#define MSR_IA32_PERFEVTSEL0 0x186
971#define MSR_IA32_PERFEVTSEL1 0x187
972#define MSR_IA32_FLEX_RATIO 0x194
973#define MSR_IA32_PERF_STATUS 0x198
974#define MSR_IA32_PERF_CTL 0x199
975#define MSR_IA32_THERM_STATUS 0x19c
976
977/** Enable misc. processor features (R/W). */
978#define MSR_IA32_MISC_ENABLE 0x1A0
979/** Enable fast-strings feature (for REP MOVS and REP STORS). */
980#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
981/** Automatic Thermal Control Circuit Enable (R/W). */
982#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
983/** Performance Monitoring Available (R). */
984#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
985/** Branch Trace Storage Unavailable (R/O). */
986#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
987/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
988#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
989/** Enhanced Intel SpeedStep Technology Enable (R/W). */
990#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
991/** If MONITOR/MWAIT is supported (R/W). */
992#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
993/** Limit CPUID Maxval to 3 leafs (R/W). */
994#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
995/** When set to 1, xTPR messages are disabled (R/W). */
996#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
997/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
998#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
999
1000#define IA32_MTRR_PHYSBASE0 0x200
1001#define IA32_MTRR_PHYSMASK0 0x201
1002#define IA32_MTRR_PHYSBASE1 0x202
1003#define IA32_MTRR_PHYSMASK1 0x203
1004#define IA32_MTRR_PHYSBASE2 0x204
1005#define IA32_MTRR_PHYSMASK2 0x205
1006#define IA32_MTRR_PHYSBASE3 0x206
1007#define IA32_MTRR_PHYSMASK3 0x207
1008#define IA32_MTRR_PHYSBASE4 0x208
1009#define IA32_MTRR_PHYSMASK4 0x209
1010#define IA32_MTRR_PHYSBASE5 0x20a
1011#define IA32_MTRR_PHYSMASK5 0x20b
1012#define IA32_MTRR_PHYSBASE6 0x20c
1013#define IA32_MTRR_PHYSMASK6 0x20d
1014#define IA32_MTRR_PHYSBASE7 0x20e
1015#define IA32_MTRR_PHYSMASK7 0x20f
1016#define IA32_MTRR_PHYSBASE8 0x210
1017#define IA32_MTRR_PHYSMASK8 0x211
1018#define IA32_MTRR_PHYSBASE9 0x212
1019#define IA32_MTRR_PHYSMASK9 0x213
1020
1021/** Fixed range MTRRs.
1022 * @{ */
1023#define IA32_MTRR_FIX64K_00000 0x250
1024#define IA32_MTRR_FIX16K_80000 0x258
1025#define IA32_MTRR_FIX16K_A0000 0x259
1026#define IA32_MTRR_FIX4K_C0000 0x268
1027#define IA32_MTRR_FIX4K_C8000 0x269
1028#define IA32_MTRR_FIX4K_D0000 0x26a
1029#define IA32_MTRR_FIX4K_D8000 0x26b
1030#define IA32_MTRR_FIX4K_E0000 0x26c
1031#define IA32_MTRR_FIX4K_E8000 0x26d
1032#define IA32_MTRR_FIX4K_F0000 0x26e
1033#define IA32_MTRR_FIX4K_F8000 0x26f
1034/** @} */
1035
1036/** MTRR Default Range. */
1037#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1038
1039#define MSR_IA32_MC0_CTL 0x400
1040#define MSR_IA32_MC0_STATUS 0x401
1041
1042/** Basic VMX information. */
1043#define MSR_IA32_VMX_BASIC_INFO 0x480
1044/** Allowed settings for pin-based VM execution controls */
1045#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1046/** Allowed settings for proc-based VM execution controls */
1047#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1048/** Allowed settings for the VMX exit controls. */
1049#define MSR_IA32_VMX_EXIT_CTLS 0x483
1050/** Allowed settings for the VMX entry controls. */
1051#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1052/** Misc VMX info. */
1053#define MSR_IA32_VMX_MISC 0x485
1054/** Fixed cleared bits in CR0. */
1055#define MSR_IA32_VMX_CR0_FIXED0 0x486
1056/** Fixed set bits in CR0. */
1057#define MSR_IA32_VMX_CR0_FIXED1 0x487
1058/** Fixed cleared bits in CR4. */
1059#define MSR_IA32_VMX_CR4_FIXED0 0x488
1060/** Fixed set bits in CR4. */
1061#define MSR_IA32_VMX_CR4_FIXED1 0x489
1062/** Information for enumerating fields in the VMCS. */
1063#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1064/** Allowed settings for the VM-functions controls. */
1065#define MSR_IA32_VMX_VMFUNC 0x491
1066/** Allowed settings for secondary proc-based VM execution controls */
1067#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1068/** EPT capabilities. */
1069#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1070/** DS Save Area (R/W). */
1071#define MSR_IA32_DS_AREA 0x600
1072/** X2APIC MSR ranges. */
1073#define MSR_IA32_X2APIC_START 0x800
1074#define MSR_IA32_X2APIC_TPR 0x808
1075#define MSR_IA32_X2APIC_END 0xBFF
1076
1077/** K6 EFER - Extended Feature Enable Register. */
1078#define MSR_K6_EFER 0xc0000080
1079/** @todo document EFER */
1080/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1081#define MSR_K6_EFER_SCE RT_BIT(0)
1082/** Bit 8 - LME - Long mode enabled. (R/W) */
1083#define MSR_K6_EFER_LME RT_BIT(8)
1084/** Bit 10 - LMA - Long mode active. (R) */
1085#define MSR_K6_EFER_LMA RT_BIT(10)
1086/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1087#define MSR_K6_EFER_NXE RT_BIT(11)
1088/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1089#define MSR_K6_EFER_SVME RT_BIT(12)
1090/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1091#define MSR_K6_EFER_LMSLE RT_BIT(13)
1092/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1093#define MSR_K6_EFER_FFXSR RT_BIT(14)
1094/** K6 STAR - SYSCALL/RET targets. */
1095#define MSR_K6_STAR 0xc0000081
1096/** Shift value for getting the SYSRET CS and SS value. */
1097#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1098/** Shift value for getting the SYSCALL CS and SS value. */
1099#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1100/** Selector mask for use after shifting. */
1101#define MSR_K6_STAR_SEL_MASK 0xffff
1102/** The mask which give the SYSCALL EIP. */
1103#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1104/** K6 WHCR - Write Handling Control Register. */
1105#define MSR_K6_WHCR 0xc0000082
1106/** K6 UWCCR - UC/WC Cacheability Control Register. */
1107#define MSR_K6_UWCCR 0xc0000085
1108/** K6 PSOR - Processor State Observability Register. */
1109#define MSR_K6_PSOR 0xc0000087
1110/** K6 PFIR - Page Flush/Invalidate Register. */
1111#define MSR_K6_PFIR 0xc0000088
1112
1113/** Performance counter MSRs. (AMD only) */
1114#define MSR_K7_EVNTSEL0 0xc0010000
1115#define MSR_K7_EVNTSEL1 0xc0010001
1116#define MSR_K7_EVNTSEL2 0xc0010002
1117#define MSR_K7_EVNTSEL3 0xc0010003
1118#define MSR_K7_PERFCTR0 0xc0010004
1119#define MSR_K7_PERFCTR1 0xc0010005
1120#define MSR_K7_PERFCTR2 0xc0010006
1121#define MSR_K7_PERFCTR3 0xc0010007
1122
1123/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1124#define MSR_K8_LSTAR 0xc0000082
1125/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1126#define MSR_K8_CSTAR 0xc0000083
1127/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1128#define MSR_K8_SF_MASK 0xc0000084
1129/** K8 FS.base - The 64-bit base FS register. */
1130#define MSR_K8_FS_BASE 0xc0000100
1131/** K8 GS.base - The 64-bit base GS register. */
1132#define MSR_K8_GS_BASE 0xc0000101
1133/** K8 KernelGSbase - Used with SWAPGS. */
1134#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1135/** K8 TSC_AUX - Used with RDTSCP. */
1136#define MSR_K8_TSC_AUX 0xc0000103
1137#define MSR_K8_SYSCFG 0xc0010010
1138#define MSR_K8_HWCR 0xc0010015
1139#define MSR_K8_IORRBASE0 0xc0010016
1140#define MSR_K8_IORRMASK0 0xc0010017
1141#define MSR_K8_IORRBASE1 0xc0010018
1142#define MSR_K8_IORRMASK1 0xc0010019
1143#define MSR_K8_TOP_MEM1 0xc001001a
1144#define MSR_K8_TOP_MEM2 0xc001001d
1145#define MSR_K8_VM_CR 0xc0010114
1146#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1147
1148#define MSR_K8_IGNNE 0xc0010115
1149#define MSR_K8_SMM_CTL 0xc0010116
1150/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1151 * host state during world switch.
1152 */
1153#define MSR_K8_VM_HSAVE_PA 0xc0010117
1154
1155/** @} */
1156
1157
1158/** @name Page Table / Directory / Directory Pointers / L4.
1159 * @{
1160 */
1161
1162/** Page table/directory entry as an unsigned integer. */
1163typedef uint32_t X86PGUINT;
1164/** Pointer to a page table/directory table entry as an unsigned integer. */
1165typedef X86PGUINT *PX86PGUINT;
1166/** Pointer to an const page table/directory table entry as an unsigned integer. */
1167typedef X86PGUINT const *PCX86PGUINT;
1168
1169/** Number of entries in a 32-bit PT/PD. */
1170#define X86_PG_ENTRIES 1024
1171
1172
1173/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1174typedef uint64_t X86PGPAEUINT;
1175/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1176typedef X86PGPAEUINT *PX86PGPAEUINT;
1177/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1178typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1179
1180/** Number of entries in a PAE PT/PD. */
1181#define X86_PG_PAE_ENTRIES 512
1182/** Number of entries in a PAE PDPT. */
1183#define X86_PG_PAE_PDPE_ENTRIES 4
1184
1185/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1186#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1187/** Number of entries in an AMD64 PDPT.
1188 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1189#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1190
1191/** The size of a 4KB page. */
1192#define X86_PAGE_4K_SIZE _4K
1193/** The page shift of a 4KB page. */
1194#define X86_PAGE_4K_SHIFT 12
1195/** The 4KB page offset mask. */
1196#define X86_PAGE_4K_OFFSET_MASK 0xfff
1197/** The 4KB page base mask for virtual addresses. */
1198#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1199/** The 4KB page base mask for virtual addresses - 32bit version. */
1200#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1201
1202/** The size of a 2MB page. */
1203#define X86_PAGE_2M_SIZE _2M
1204/** The page shift of a 2MB page. */
1205#define X86_PAGE_2M_SHIFT 21
1206/** The 2MB page offset mask. */
1207#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1208/** The 2MB page base mask for virtual addresses. */
1209#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1210/** The 2MB page base mask for virtual addresses - 32bit version. */
1211#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1212
1213/** The size of a 4MB page. */
1214#define X86_PAGE_4M_SIZE _4M
1215/** The page shift of a 4MB page. */
1216#define X86_PAGE_4M_SHIFT 22
1217/** The 4MB page offset mask. */
1218#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1219/** The 4MB page base mask for virtual addresses. */
1220#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1221/** The 4MB page base mask for virtual addresses - 32bit version. */
1222#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1223
1224
1225
1226/** @name Page Table Entry
1227 * @{
1228 */
1229/** Bit 0 - P - Present bit. */
1230#define X86_PTE_BIT_P 0
1231/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1232#define X86_PTE_BIT_RW 1
1233/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1234#define X86_PTE_BIT_US 2
1235/** Bit 3 - PWT - Page level write thru bit. */
1236#define X86_PTE_BIT_PWT 3
1237/** Bit 4 - PCD - Page level cache disable bit. */
1238#define X86_PTE_BIT_PCD 4
1239/** Bit 5 - A - Access bit. */
1240#define X86_PTE_BIT_A 5
1241/** Bit 6 - D - Dirty bit. */
1242#define X86_PTE_BIT_D 6
1243/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1244#define X86_PTE_BIT_PAT 7
1245/** Bit 8 - G - Global flag. */
1246#define X86_PTE_BIT_G 8
1247
1248/** Bit 0 - P - Present bit mask. */
1249#define X86_PTE_P RT_BIT(0)
1250/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1251#define X86_PTE_RW RT_BIT(1)
1252/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1253#define X86_PTE_US RT_BIT(2)
1254/** Bit 3 - PWT - Page level write thru bit mask. */
1255#define X86_PTE_PWT RT_BIT(3)
1256/** Bit 4 - PCD - Page level cache disable bit mask. */
1257#define X86_PTE_PCD RT_BIT(4)
1258/** Bit 5 - A - Access bit mask. */
1259#define X86_PTE_A RT_BIT(5)
1260/** Bit 6 - D - Dirty bit mask. */
1261#define X86_PTE_D RT_BIT(6)
1262/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1263#define X86_PTE_PAT RT_BIT(7)
1264/** Bit 8 - G - Global bit mask. */
1265#define X86_PTE_G RT_BIT(8)
1266
1267/** Bits 9-11 - - Available for use to system software. */
1268#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1269/** Bits 12-31 - - Physical Page number of the next level. */
1270#define X86_PTE_PG_MASK ( 0xfffff000 )
1271
1272/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1273#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1274/** Bits 63 - NX - PAE/LM - No execution flag. */
1275#define X86_PTE_PAE_NX RT_BIT_64(63)
1276/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1277#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1278/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1279#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1280/** No bits - - LM - MBZ bits when NX is active. */
1281#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1282/** Bits 63 - - LM - MBZ bits when no NX. */
1283#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1284
1285/**
1286 * Page table entry.
1287 */
1288typedef struct X86PTEBITS
1289{
1290 /** Flags whether(=1) or not the page is present. */
1291 unsigned u1Present : 1;
1292 /** Read(=0) / Write(=1) flag. */
1293 unsigned u1Write : 1;
1294 /** User(=1) / Supervisor (=0) flag. */
1295 unsigned u1User : 1;
1296 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1297 unsigned u1WriteThru : 1;
1298 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1299 unsigned u1CacheDisable : 1;
1300 /** Accessed flag.
1301 * Indicates that the page have been read or written to. */
1302 unsigned u1Accessed : 1;
1303 /** Dirty flag.
1304 * Indicates that the page has been written to. */
1305 unsigned u1Dirty : 1;
1306 /** Reserved / If PAT enabled, bit 2 of the index. */
1307 unsigned u1PAT : 1;
1308 /** Global flag. (Ignored in all but final level.) */
1309 unsigned u1Global : 1;
1310 /** Available for use to system software. */
1311 unsigned u3Available : 3;
1312 /** Physical Page number of the next level. */
1313 unsigned u20PageNo : 20;
1314} X86PTEBITS;
1315/** Pointer to a page table entry. */
1316typedef X86PTEBITS *PX86PTEBITS;
1317/** Pointer to a const page table entry. */
1318typedef const X86PTEBITS *PCX86PTEBITS;
1319
1320/**
1321 * Page table entry.
1322 */
1323typedef union X86PTE
1324{
1325 /** Unsigned integer view */
1326 X86PGUINT u;
1327 /** Bit field view. */
1328 X86PTEBITS n;
1329 /** 32-bit view. */
1330 uint32_t au32[1];
1331 /** 16-bit view. */
1332 uint16_t au16[2];
1333 /** 8-bit view. */
1334 uint8_t au8[4];
1335} X86PTE;
1336/** Pointer to a page table entry. */
1337typedef X86PTE *PX86PTE;
1338/** Pointer to a const page table entry. */
1339typedef const X86PTE *PCX86PTE;
1340
1341
1342/**
1343 * PAE page table entry.
1344 */
1345typedef struct X86PTEPAEBITS
1346{
1347 /** Flags whether(=1) or not the page is present. */
1348 uint32_t u1Present : 1;
1349 /** Read(=0) / Write(=1) flag. */
1350 uint32_t u1Write : 1;
1351 /** User(=1) / Supervisor(=0) flag. */
1352 uint32_t u1User : 1;
1353 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1354 uint32_t u1WriteThru : 1;
1355 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1356 uint32_t u1CacheDisable : 1;
1357 /** Accessed flag.
1358 * Indicates that the page have been read or written to. */
1359 uint32_t u1Accessed : 1;
1360 /** Dirty flag.
1361 * Indicates that the page has been written to. */
1362 uint32_t u1Dirty : 1;
1363 /** Reserved / If PAT enabled, bit 2 of the index. */
1364 uint32_t u1PAT : 1;
1365 /** Global flag. (Ignored in all but final level.) */
1366 uint32_t u1Global : 1;
1367 /** Available for use to system software. */
1368 uint32_t u3Available : 3;
1369 /** Physical Page number of the next level - Low Part. Don't use this. */
1370 uint32_t u20PageNoLow : 20;
1371 /** Physical Page number of the next level - High Part. Don't use this. */
1372 uint32_t u20PageNoHigh : 20;
1373 /** MBZ bits */
1374 uint32_t u11Reserved : 11;
1375 /** No Execute flag. */
1376 uint32_t u1NoExecute : 1;
1377} X86PTEPAEBITS;
1378/** Pointer to a page table entry. */
1379typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1380/** Pointer to a page table entry. */
1381typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1382
1383/**
1384 * PAE Page table entry.
1385 */
1386typedef union X86PTEPAE
1387{
1388 /** Unsigned integer view */
1389 X86PGPAEUINT u;
1390 /** Bit field view. */
1391 X86PTEPAEBITS n;
1392 /** 32-bit view. */
1393 uint32_t au32[2];
1394 /** 16-bit view. */
1395 uint16_t au16[4];
1396 /** 8-bit view. */
1397 uint8_t au8[8];
1398} X86PTEPAE;
1399/** Pointer to a PAE page table entry. */
1400typedef X86PTEPAE *PX86PTEPAE;
1401/** Pointer to a const PAE page table entry. */
1402typedef const X86PTEPAE *PCX86PTEPAE;
1403/** @} */
1404
1405/**
1406 * Page table.
1407 */
1408typedef struct X86PT
1409{
1410 /** PTE Array. */
1411 X86PTE a[X86_PG_ENTRIES];
1412} X86PT;
1413/** Pointer to a page table. */
1414typedef X86PT *PX86PT;
1415/** Pointer to a const page table. */
1416typedef const X86PT *PCX86PT;
1417
1418/** The page shift to get the PT index. */
1419#define X86_PT_SHIFT 12
1420/** The PT index mask (apply to a shifted page address). */
1421#define X86_PT_MASK 0x3ff
1422
1423
1424/**
1425 * Page directory.
1426 */
1427typedef struct X86PTPAE
1428{
1429 /** PTE Array. */
1430 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1431} X86PTPAE;
1432/** Pointer to a page table. */
1433typedef X86PTPAE *PX86PTPAE;
1434/** Pointer to a const page table. */
1435typedef const X86PTPAE *PCX86PTPAE;
1436
1437/** The page shift to get the PA PTE index. */
1438#define X86_PT_PAE_SHIFT 12
1439/** The PAE PT index mask (apply to a shifted page address). */
1440#define X86_PT_PAE_MASK 0x1ff
1441
1442
1443/** @name 4KB Page Directory Entry
1444 * @{
1445 */
1446/** Bit 0 - P - Present bit. */
1447#define X86_PDE_P RT_BIT(0)
1448/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1449#define X86_PDE_RW RT_BIT(1)
1450/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1451#define X86_PDE_US RT_BIT(2)
1452/** Bit 3 - PWT - Page level write thru bit. */
1453#define X86_PDE_PWT RT_BIT(3)
1454/** Bit 4 - PCD - Page level cache disable bit. */
1455#define X86_PDE_PCD RT_BIT(4)
1456/** Bit 5 - A - Access bit. */
1457#define X86_PDE_A RT_BIT(5)
1458/** Bit 7 - PS - Page size attribute.
1459 * Clear mean 4KB pages, set means large pages (2/4MB). */
1460#define X86_PDE_PS RT_BIT(7)
1461/** Bits 9-11 - - Available for use to system software. */
1462#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1463/** Bits 12-31 - - Physical Page number of the next level. */
1464#define X86_PDE_PG_MASK ( 0xfffff000 )
1465
1466/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1467#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1468/** Bits 63 - NX - PAE/LM - No execution flag. */
1469#define X86_PDE_PAE_NX RT_BIT_64(63)
1470/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1471#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1472/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1473#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1474/** Bit 7 - - LM - MBZ bits when NX is active. */
1475#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1476/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1477#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1478
1479/**
1480 * Page directory entry.
1481 */
1482typedef struct X86PDEBITS
1483{
1484 /** Flags whether(=1) or not the page is present. */
1485 unsigned u1Present : 1;
1486 /** Read(=0) / Write(=1) flag. */
1487 unsigned u1Write : 1;
1488 /** User(=1) / Supervisor (=0) flag. */
1489 unsigned u1User : 1;
1490 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1491 unsigned u1WriteThru : 1;
1492 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1493 unsigned u1CacheDisable : 1;
1494 /** Accessed flag.
1495 * Indicates that the page has been read or written to. */
1496 unsigned u1Accessed : 1;
1497 /** Reserved / Ignored (dirty bit). */
1498 unsigned u1Reserved0 : 1;
1499 /** Size bit if PSE is enabled - in any event it's 0. */
1500 unsigned u1Size : 1;
1501 /** Reserved / Ignored (global bit). */
1502 unsigned u1Reserved1 : 1;
1503 /** Available for use to system software. */
1504 unsigned u3Available : 3;
1505 /** Physical Page number of the next level. */
1506 unsigned u20PageNo : 20;
1507} X86PDEBITS;
1508/** Pointer to a page directory entry. */
1509typedef X86PDEBITS *PX86PDEBITS;
1510/** Pointer to a const page directory entry. */
1511typedef const X86PDEBITS *PCX86PDEBITS;
1512
1513
1514/**
1515 * PAE page directory entry.
1516 */
1517typedef struct X86PDEPAEBITS
1518{
1519 /** Flags whether(=1) or not the page is present. */
1520 uint32_t u1Present : 1;
1521 /** Read(=0) / Write(=1) flag. */
1522 uint32_t u1Write : 1;
1523 /** User(=1) / Supervisor (=0) flag. */
1524 uint32_t u1User : 1;
1525 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1526 uint32_t u1WriteThru : 1;
1527 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1528 uint32_t u1CacheDisable : 1;
1529 /** Accessed flag.
1530 * Indicates that the page has been read or written to. */
1531 uint32_t u1Accessed : 1;
1532 /** Reserved / Ignored (dirty bit). */
1533 uint32_t u1Reserved0 : 1;
1534 /** Size bit if PSE is enabled - in any event it's 0. */
1535 uint32_t u1Size : 1;
1536 /** Reserved / Ignored (global bit). / */
1537 uint32_t u1Reserved1 : 1;
1538 /** Available for use to system software. */
1539 uint32_t u3Available : 3;
1540 /** Physical Page number of the next level - Low Part. Don't use! */
1541 uint32_t u20PageNoLow : 20;
1542 /** Physical Page number of the next level - High Part. Don't use! */
1543 uint32_t u20PageNoHigh : 20;
1544 /** MBZ bits */
1545 uint32_t u11Reserved : 11;
1546 /** No Execute flag. */
1547 uint32_t u1NoExecute : 1;
1548} X86PDEPAEBITS;
1549/** Pointer to a page directory entry. */
1550typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1551/** Pointer to a const page directory entry. */
1552typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1553
1554/** @} */
1555
1556
1557/** @name 2/4MB Page Directory Entry
1558 * @{
1559 */
1560/** Bit 0 - P - Present bit. */
1561#define X86_PDE4M_P RT_BIT(0)
1562/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1563#define X86_PDE4M_RW RT_BIT(1)
1564/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1565#define X86_PDE4M_US RT_BIT(2)
1566/** Bit 3 - PWT - Page level write thru bit. */
1567#define X86_PDE4M_PWT RT_BIT(3)
1568/** Bit 4 - PCD - Page level cache disable bit. */
1569#define X86_PDE4M_PCD RT_BIT(4)
1570/** Bit 5 - A - Access bit. */
1571#define X86_PDE4M_A RT_BIT(5)
1572/** Bit 6 - D - Dirty bit. */
1573#define X86_PDE4M_D RT_BIT(6)
1574/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1575#define X86_PDE4M_PS RT_BIT(7)
1576/** Bit 8 - G - Global flag. */
1577#define X86_PDE4M_G RT_BIT(8)
1578/** Bits 9-11 - AVL - Available for use to system software. */
1579#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1580/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1581#define X86_PDE4M_PAT RT_BIT(12)
1582/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1583#define X86_PDE4M_PAT_SHIFT (12 - 7)
1584/** Bits 22-31 - - Physical Page number. */
1585#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1586/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1587#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1588/** The number of bits to the high part of the page number. */
1589#define X86_PDE4M_PG_HIGH_SHIFT 19
1590/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1591#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1592
1593/** Bits 21-51 - - PAE/LM - Physical Page number.
1594 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1595#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1596/** Bits 63 - NX - PAE/LM - No execution flag. */
1597#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1598/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1599#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1600/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1601#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1602/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1603#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1604/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1605#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1606
1607/**
1608 * 4MB page directory entry.
1609 */
1610typedef struct X86PDE4MBITS
1611{
1612 /** Flags whether(=1) or not the page is present. */
1613 unsigned u1Present : 1;
1614 /** Read(=0) / Write(=1) flag. */
1615 unsigned u1Write : 1;
1616 /** User(=1) / Supervisor (=0) flag. */
1617 unsigned u1User : 1;
1618 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1619 unsigned u1WriteThru : 1;
1620 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1621 unsigned u1CacheDisable : 1;
1622 /** Accessed flag.
1623 * Indicates that the page have been read or written to. */
1624 unsigned u1Accessed : 1;
1625 /** Dirty flag.
1626 * Indicates that the page has been written to. */
1627 unsigned u1Dirty : 1;
1628 /** Page size flag - always 1 for 4MB entries. */
1629 unsigned u1Size : 1;
1630 /** Global flag. */
1631 unsigned u1Global : 1;
1632 /** Available for use to system software. */
1633 unsigned u3Available : 3;
1634 /** Reserved / If PAT enabled, bit 2 of the index. */
1635 unsigned u1PAT : 1;
1636 /** Bits 32-39 of the page number on AMD64.
1637 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1638 unsigned u8PageNoHigh : 8;
1639 /** Reserved. */
1640 unsigned u1Reserved : 1;
1641 /** Physical Page number of the page. */
1642 unsigned u10PageNo : 10;
1643} X86PDE4MBITS;
1644/** Pointer to a page table entry. */
1645typedef X86PDE4MBITS *PX86PDE4MBITS;
1646/** Pointer to a const page table entry. */
1647typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1648
1649
1650/**
1651 * 2MB PAE page directory entry.
1652 */
1653typedef struct X86PDE2MPAEBITS
1654{
1655 /** Flags whether(=1) or not the page is present. */
1656 uint32_t u1Present : 1;
1657 /** Read(=0) / Write(=1) flag. */
1658 uint32_t u1Write : 1;
1659 /** User(=1) / Supervisor(=0) flag. */
1660 uint32_t u1User : 1;
1661 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1662 uint32_t u1WriteThru : 1;
1663 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1664 uint32_t u1CacheDisable : 1;
1665 /** Accessed flag.
1666 * Indicates that the page have been read or written to. */
1667 uint32_t u1Accessed : 1;
1668 /** Dirty flag.
1669 * Indicates that the page has been written to. */
1670 uint32_t u1Dirty : 1;
1671 /** Page size flag - always 1 for 2MB entries. */
1672 uint32_t u1Size : 1;
1673 /** Global flag. */
1674 uint32_t u1Global : 1;
1675 /** Available for use to system software. */
1676 uint32_t u3Available : 3;
1677 /** Reserved / If PAT enabled, bit 2 of the index. */
1678 uint32_t u1PAT : 1;
1679 /** Reserved. */
1680 uint32_t u9Reserved : 9;
1681 /** Physical Page number of the next level - Low part. Don't use! */
1682 uint32_t u10PageNoLow : 10;
1683 /** Physical Page number of the next level - High part. Don't use! */
1684 uint32_t u20PageNoHigh : 20;
1685 /** MBZ bits */
1686 uint32_t u11Reserved : 11;
1687 /** No Execute flag. */
1688 uint32_t u1NoExecute : 1;
1689} X86PDE2MPAEBITS;
1690/** Pointer to a 2MB PAE page table entry. */
1691typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1692/** Pointer to a 2MB PAE page table entry. */
1693typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1694
1695/** @} */
1696
1697/**
1698 * Page directory entry.
1699 */
1700typedef union X86PDE
1701{
1702 /** Unsigned integer view. */
1703 X86PGUINT u;
1704 /** Normal view. */
1705 X86PDEBITS n;
1706 /** 4MB view (big). */
1707 X86PDE4MBITS b;
1708 /** 8 bit unsigned integer view. */
1709 uint8_t au8[4];
1710 /** 16 bit unsigned integer view. */
1711 uint16_t au16[2];
1712 /** 32 bit unsigned integer view. */
1713 uint32_t au32[1];
1714} X86PDE;
1715/** Pointer to a page directory entry. */
1716typedef X86PDE *PX86PDE;
1717/** Pointer to a const page directory entry. */
1718typedef const X86PDE *PCX86PDE;
1719
1720/**
1721 * PAE page directory entry.
1722 */
1723typedef union X86PDEPAE
1724{
1725 /** Unsigned integer view. */
1726 X86PGPAEUINT u;
1727 /** Normal view. */
1728 X86PDEPAEBITS n;
1729 /** 2MB page view (big). */
1730 X86PDE2MPAEBITS b;
1731 /** 8 bit unsigned integer view. */
1732 uint8_t au8[8];
1733 /** 16 bit unsigned integer view. */
1734 uint16_t au16[4];
1735 /** 32 bit unsigned integer view. */
1736 uint32_t au32[2];
1737} X86PDEPAE;
1738/** Pointer to a page directory entry. */
1739typedef X86PDEPAE *PX86PDEPAE;
1740/** Pointer to a const page directory entry. */
1741typedef const X86PDEPAE *PCX86PDEPAE;
1742
1743/**
1744 * Page directory.
1745 */
1746typedef struct X86PD
1747{
1748 /** PDE Array. */
1749 X86PDE a[X86_PG_ENTRIES];
1750} X86PD;
1751/** Pointer to a page directory. */
1752typedef X86PD *PX86PD;
1753/** Pointer to a const page directory. */
1754typedef const X86PD *PCX86PD;
1755
1756/** The page shift to get the PD index. */
1757#define X86_PD_SHIFT 22
1758/** The PD index mask (apply to a shifted page address). */
1759#define X86_PD_MASK 0x3ff
1760
1761
1762/**
1763 * PAE page directory.
1764 */
1765typedef struct X86PDPAE
1766{
1767 /** PDE Array. */
1768 X86PDEPAE a[X86_PG_PAE_ENTRIES];
1769} X86PDPAE;
1770/** Pointer to a PAE page directory. */
1771typedef X86PDPAE *PX86PDPAE;
1772/** Pointer to a const PAE page directory. */
1773typedef const X86PDPAE *PCX86PDPAE;
1774
1775/** The page shift to get the PAE PD index. */
1776#define X86_PD_PAE_SHIFT 21
1777/** The PAE PD index mask (apply to a shifted page address). */
1778#define X86_PD_PAE_MASK 0x1ff
1779
1780
1781/** @name Page Directory Pointer Table Entry (PAE)
1782 * @{
1783 */
1784/** Bit 0 - P - Present bit. */
1785#define X86_PDPE_P RT_BIT(0)
1786/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1787#define X86_PDPE_RW RT_BIT(1)
1788/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1789#define X86_PDPE_US RT_BIT(2)
1790/** Bit 3 - PWT - Page level write thru bit. */
1791#define X86_PDPE_PWT RT_BIT(3)
1792/** Bit 4 - PCD - Page level cache disable bit. */
1793#define X86_PDPE_PCD RT_BIT(4)
1794/** Bit 5 - A - Access bit. Long Mode only. */
1795#define X86_PDPE_A RT_BIT(5)
1796/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1797#define X86_PDPE_LM_PS RT_BIT(7)
1798/** Bits 9-11 - - Available for use to system software. */
1799#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1800/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1801#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1802/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1803#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1804/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1805#define X86_PDPE_LM_NX RT_BIT_64(63)
1806/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1807#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1808/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1809#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1810/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1811#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1812/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1813#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1814
1815
1816/**
1817 * Page directory pointer table entry.
1818 */
1819typedef struct X86PDPEBITS
1820{
1821 /** Flags whether(=1) or not the page is present. */
1822 uint32_t u1Present : 1;
1823 /** Chunk of reserved bits. */
1824 uint32_t u2Reserved : 2;
1825 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1826 uint32_t u1WriteThru : 1;
1827 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1828 uint32_t u1CacheDisable : 1;
1829 /** Chunk of reserved bits. */
1830 uint32_t u4Reserved : 4;
1831 /** Available for use to system software. */
1832 uint32_t u3Available : 3;
1833 /** Physical Page number of the next level - Low Part. Don't use! */
1834 uint32_t u20PageNoLow : 20;
1835 /** Physical Page number of the next level - High Part. Don't use! */
1836 uint32_t u20PageNoHigh : 20;
1837 /** MBZ bits */
1838 uint32_t u12Reserved : 12;
1839} X86PDPEBITS;
1840/** Pointer to a page directory pointer table entry. */
1841typedef X86PDPEBITS *PX86PTPEBITS;
1842/** Pointer to a const page directory pointer table entry. */
1843typedef const X86PDPEBITS *PCX86PTPEBITS;
1844
1845/**
1846 * Page directory pointer table entry. AMD64 version
1847 */
1848typedef struct X86PDPEAMD64BITS
1849{
1850 /** Flags whether(=1) or not the page is present. */
1851 uint32_t u1Present : 1;
1852 /** Read(=0) / Write(=1) flag. */
1853 uint32_t u1Write : 1;
1854 /** User(=1) / Supervisor (=0) flag. */
1855 uint32_t u1User : 1;
1856 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1857 uint32_t u1WriteThru : 1;
1858 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1859 uint32_t u1CacheDisable : 1;
1860 /** Accessed flag.
1861 * Indicates that the page have been read or written to. */
1862 uint32_t u1Accessed : 1;
1863 /** Chunk of reserved bits. */
1864 uint32_t u3Reserved : 3;
1865 /** Available for use to system software. */
1866 uint32_t u3Available : 3;
1867 /** Physical Page number of the next level - Low Part. Don't use! */
1868 uint32_t u20PageNoLow : 20;
1869 /** Physical Page number of the next level - High Part. Don't use! */
1870 uint32_t u20PageNoHigh : 20;
1871 /** MBZ bits */
1872 uint32_t u11Reserved : 11;
1873 /** No Execute flag. */
1874 uint32_t u1NoExecute : 1;
1875} X86PDPEAMD64BITS;
1876/** Pointer to a page directory pointer table entry. */
1877typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1878/** Pointer to a const page directory pointer table entry. */
1879typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1880
1881/**
1882 * Page directory pointer table entry.
1883 */
1884typedef union X86PDPE
1885{
1886 /** Unsigned integer view. */
1887 X86PGPAEUINT u;
1888 /** Normal view. */
1889 X86PDPEBITS n;
1890 /** AMD64 view. */
1891 X86PDPEAMD64BITS lm;
1892 /** 8 bit unsigned integer view. */
1893 uint8_t au8[8];
1894 /** 16 bit unsigned integer view. */
1895 uint16_t au16[4];
1896 /** 32 bit unsigned integer view. */
1897 uint32_t au32[2];
1898} X86PDPE;
1899/** Pointer to a page directory pointer table entry. */
1900typedef X86PDPE *PX86PDPE;
1901/** Pointer to a const page directory pointer table entry. */
1902typedef const X86PDPE *PCX86PDPE;
1903
1904
1905/**
1906 * Page directory pointer table.
1907 */
1908typedef struct X86PDPT
1909{
1910 /** PDE Array. */
1911 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1912} X86PDPT;
1913/** Pointer to a page directory pointer table. */
1914typedef X86PDPT *PX86PDPT;
1915/** Pointer to a const page directory pointer table. */
1916typedef const X86PDPT *PCX86PDPT;
1917
1918/** The page shift to get the PDPT index. */
1919#define X86_PDPT_SHIFT 30
1920/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1921#define X86_PDPT_MASK_PAE 0x3
1922/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1923#define X86_PDPT_MASK_AMD64 0x1ff
1924
1925/** @} */
1926
1927
1928/** @name Page Map Level-4 Entry (Long Mode PAE)
1929 * @{
1930 */
1931/** Bit 0 - P - Present bit. */
1932#define X86_PML4E_P RT_BIT(0)
1933/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1934#define X86_PML4E_RW RT_BIT(1)
1935/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1936#define X86_PML4E_US RT_BIT(2)
1937/** Bit 3 - PWT - Page level write thru bit. */
1938#define X86_PML4E_PWT RT_BIT(3)
1939/** Bit 4 - PCD - Page level cache disable bit. */
1940#define X86_PML4E_PCD RT_BIT(4)
1941/** Bit 5 - A - Access bit. */
1942#define X86_PML4E_A RT_BIT(5)
1943/** Bits 9-11 - - Available for use to system software. */
1944#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1945/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1946#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1947/** Bits 8, 7 - - MBZ bits when NX is active. */
1948#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1949/** Bits 63, 7 - - MBZ bits when no NX. */
1950#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1951/** Bits 63 - NX - PAE - No execution flag. */
1952#define X86_PML4E_NX RT_BIT_64(63)
1953
1954/**
1955 * Page Map Level-4 Entry
1956 */
1957typedef struct X86PML4EBITS
1958{
1959 /** Flags whether(=1) or not the page is present. */
1960 uint32_t u1Present : 1;
1961 /** Read(=0) / Write(=1) flag. */
1962 uint32_t u1Write : 1;
1963 /** User(=1) / Supervisor (=0) flag. */
1964 uint32_t u1User : 1;
1965 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1966 uint32_t u1WriteThru : 1;
1967 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1968 uint32_t u1CacheDisable : 1;
1969 /** Accessed flag.
1970 * Indicates that the page have been read or written to. */
1971 uint32_t u1Accessed : 1;
1972 /** Chunk of reserved bits. */
1973 uint32_t u3Reserved : 3;
1974 /** Available for use to system software. */
1975 uint32_t u3Available : 3;
1976 /** Physical Page number of the next level - Low Part. Don't use! */
1977 uint32_t u20PageNoLow : 20;
1978 /** Physical Page number of the next level - High Part. Don't use! */
1979 uint32_t u20PageNoHigh : 20;
1980 /** MBZ bits */
1981 uint32_t u11Reserved : 11;
1982 /** No Execute flag. */
1983 uint32_t u1NoExecute : 1;
1984} X86PML4EBITS;
1985/** Pointer to a page map level-4 entry. */
1986typedef X86PML4EBITS *PX86PML4EBITS;
1987/** Pointer to a const page map level-4 entry. */
1988typedef const X86PML4EBITS *PCX86PML4EBITS;
1989
1990/**
1991 * Page Map Level-4 Entry.
1992 */
1993typedef union X86PML4E
1994{
1995 /** Unsigned integer view. */
1996 X86PGPAEUINT u;
1997 /** Normal view. */
1998 X86PML4EBITS n;
1999 /** 8 bit unsigned integer view. */
2000 uint8_t au8[8];
2001 /** 16 bit unsigned integer view. */
2002 uint16_t au16[4];
2003 /** 32 bit unsigned integer view. */
2004 uint32_t au32[2];
2005} X86PML4E;
2006/** Pointer to a page map level-4 entry. */
2007typedef X86PML4E *PX86PML4E;
2008/** Pointer to a const page map level-4 entry. */
2009typedef const X86PML4E *PCX86PML4E;
2010
2011
2012/**
2013 * Page Map Level-4.
2014 */
2015typedef struct X86PML4
2016{
2017 /** PDE Array. */
2018 X86PML4E a[X86_PG_PAE_ENTRIES];
2019} X86PML4;
2020/** Pointer to a page map level-4. */
2021typedef X86PML4 *PX86PML4;
2022/** Pointer to a const page map level-4. */
2023typedef const X86PML4 *PCX86PML4;
2024
2025/** The page shift to get the PML4 index. */
2026#define X86_PML4_SHIFT 39
2027/** The PML4 index mask (apply to a shifted page address). */
2028#define X86_PML4_MASK 0x1ff
2029
2030/** @} */
2031
2032/** @} */
2033
2034
2035/**
2036 * 80-bit MMX/FPU register type.
2037 */
2038typedef struct X86FPUMMX
2039{
2040 uint8_t reg[10];
2041} X86FPUMMX;
2042/** Pointer to a 80-bit MMX/FPU register type. */
2043typedef X86FPUMMX *PX86FPUMMX;
2044/** Pointer to a const 80-bit MMX/FPU register type. */
2045typedef const X86FPUMMX *PCX86FPUMMX;
2046
2047/**
2048 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2049 * @todo verify this...
2050 */
2051#pragma pack(1)
2052typedef struct X86FPUSTATE
2053{
2054 /** 0x00 - Control word. */
2055 uint16_t FCW;
2056 /** 0x02 - Alignment word */
2057 uint16_t Dummy1;
2058 /** 0x04 - Status word. */
2059 uint16_t FSW;
2060 /** 0x06 - Alignment word */
2061 uint16_t Dummy2;
2062 /** 0x08 - Tag word */
2063 uint16_t FTW;
2064 /** 0x0a - Alignment word */
2065 uint16_t Dummy3;
2066
2067 /** 0x0c - Instruction pointer. */
2068 uint32_t FPUIP;
2069 /** 0x10 - Code selector. */
2070 uint16_t CS;
2071 /** 0x12 - Opcode. */
2072 uint16_t FOP;
2073 /** 0x14 - FOO. */
2074 uint32_t FPUOO;
2075 /** 0x18 - FOS. */
2076 uint32_t FPUOS;
2077 /** 0x1c */
2078 union
2079 {
2080 /** MMX view. */
2081 uint64_t mmx;
2082 /** FPU view - todo. */
2083 X86FPUMMX fpu;
2084 /** Extended precision floating point view. */
2085 RTFLOAT80U r80;
2086 /** Extended precision floating point view v2. */
2087 RTFLOAT80U2 r80Ex;
2088 /** 8-bit view. */
2089 uint8_t au8[16];
2090 /** 16-bit view. */
2091 uint16_t au16[8];
2092 /** 32-bit view. */
2093 uint32_t au32[4];
2094 /** 64-bit view. */
2095 uint64_t au64[2];
2096 /** 128-bit view. (yeah, very helpful) */
2097 uint128_t au128[1];
2098 } regs[8];
2099} X86FPUSTATE;
2100#pragma pack()
2101/** Pointer to a FPU state. */
2102typedef X86FPUSTATE *PX86FPUSTATE;
2103/** Pointer to a const FPU state. */
2104typedef const X86FPUSTATE *PCX86FPUSTATE;
2105
2106/**
2107 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2108 */
2109#pragma pack(1)
2110typedef struct X86FXSTATE
2111{
2112 /** 0x00 - Control word. */
2113 uint16_t FCW;
2114 /** 0x02 - Status word. */
2115 uint16_t FSW;
2116 /** 0x04 - Tag word. (The upper byte is always zero.) */
2117 uint16_t FTW;
2118 /** 0x06 - Opcode. */
2119 uint16_t FOP;
2120 /** 0x08 - Instruction pointer. */
2121 uint32_t FPUIP;
2122 /** 0x0c - Code selector. */
2123 uint16_t CS;
2124 uint16_t Rsrvd1;
2125 /** 0x10 - Data pointer. */
2126 uint32_t FPUDP;
2127 /** 0x14 - Data segment */
2128 uint16_t DS;
2129 /** 0x16 */
2130 uint16_t Rsrvd2;
2131 /** 0x18 */
2132 uint32_t MXCSR;
2133 /** 0x1c */
2134 uint32_t MXCSR_MASK;
2135 /** 0x20 */
2136 union
2137 {
2138 /** MMX view. */
2139 uint64_t mmx;
2140 /** FPU view - todo. */
2141 X86FPUMMX fpu;
2142 /** Extended precision floating point view. */
2143 RTFLOAT80U r80;
2144 /** Extended precision floating point view v2 */
2145 RTFLOAT80U2 r80Ex;
2146 /** 8-bit view. */
2147 uint8_t au8[16];
2148 /** 16-bit view. */
2149 uint16_t au16[8];
2150 /** 32-bit view. */
2151 uint32_t au32[4];
2152 /** 64-bit view. */
2153 uint64_t au64[2];
2154 /** 128-bit view. (yeah, very helpful) */
2155 uint128_t au128[1];
2156 } aRegs[8];
2157 /* - offset 160 - */
2158 union
2159 {
2160 /** XMM Register view *. */
2161 uint128_t xmm;
2162 /** 8-bit view. */
2163 uint8_t au8[16];
2164 /** 16-bit view. */
2165 uint16_t au16[8];
2166 /** 32-bit view. */
2167 uint32_t au32[4];
2168 /** 64-bit view. */
2169 uint64_t au64[2];
2170 /** 128-bit view. (yeah, very helpful) */
2171 uint128_t au128[1];
2172 } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2173 /* - offset 416 - */
2174 uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2175} X86FXSTATE;
2176#pragma pack()
2177/** Pointer to a FPU Extended state. */
2178typedef X86FXSTATE *PX86FXSTATE;
2179/** Pointer to a const FPU Extended state. */
2180typedef const X86FXSTATE *PCX86FXSTATE;
2181
2182/** @name FPU status word flags.
2183 * @{ */
2184/** Exception Flag: Invalid operation. */
2185#define X86_FSW_IE RT_BIT(0)
2186/** Exception Flag: Denormalized operand. */
2187#define X86_FSW_DE RT_BIT(1)
2188/** Exception Flag: Zero divide. */
2189#define X86_FSW_ZE RT_BIT(2)
2190/** Exception Flag: Overflow. */
2191#define X86_FSW_OE RT_BIT(3)
2192/** Exception Flag: Underflow. */
2193#define X86_FSW_UE RT_BIT(4)
2194/** Exception Flag: Precision. */
2195#define X86_FSW_PE RT_BIT(5)
2196/** Stack fault. */
2197#define X86_FSW_SF RT_BIT(6)
2198/** Error summary status. */
2199#define X86_FSW_ES RT_BIT(7)
2200/** Mask of exceptions flags, excluding the summary bit. */
2201#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2202/** Mask of exceptions flags, including the summary bit. */
2203#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2204/** Condition code 0. */
2205#define X86_FSW_C0 RT_BIT(8)
2206/** Condition code 1. */
2207#define X86_FSW_C1 RT_BIT(9)
2208/** Condition code 2. */
2209#define X86_FSW_C2 RT_BIT(10)
2210/** Top of the stack mask. */
2211#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2212/** TOP shift value. */
2213#define X86_FSW_TOP_SHIFT 11
2214/** Mask for getting TOP value after shifting it right. */
2215#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2216/** Get the TOP value. */
2217#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2218/** Condition code 3. */
2219#define X86_FSW_C3 RT_BIT(14)
2220/** Mask of exceptions flags, including the summary bit. */
2221#define X86_FSW_C_MASK UINT16_C(0x4700)
2222/** FPU busy. */
2223#define X86_FSW_B RT_BIT(15)
2224/** @} */
2225
2226
2227/** @name FPU control word flags.
2228 * @{ */
2229/** Exception Mask: Invalid operation. */
2230#define X86_FCW_IM RT_BIT(0)
2231/** Exception Mask: Denormalized operand. */
2232#define X86_FCW_DM RT_BIT(1)
2233/** Exception Mask: Zero divide. */
2234#define X86_FCW_ZM RT_BIT(2)
2235/** Exception Mask: Overflow. */
2236#define X86_FCW_OM RT_BIT(3)
2237/** Exception Mask: Underflow. */
2238#define X86_FCW_UM RT_BIT(4)
2239/** Exception Mask: Precision. */
2240#define X86_FCW_PM RT_BIT(5)
2241/** Mask all exceptions, the value typically loaded (by for instance fninit).
2242 * @remarks This includes reserved bit 6. */
2243#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2244/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2245#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2246/** Precision control mask. */
2247#define X86_FCW_PC_MASK UINT16_C(0x0300)
2248/** Precision control: 24-bit. */
2249#define X86_FCW_PC_24 UINT16_C(0x0000)
2250/** Precision control: Reserved. */
2251#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2252/** Precision control: 53-bit. */
2253#define X86_FCW_PC_53 UINT16_C(0x0200)
2254/** Precision control: 64-bit. */
2255#define X86_FCW_PC_64 UINT16_C(0x0300)
2256/** Rounding control mask. */
2257#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2258/** Rounding control: To nearest. */
2259#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2260/** Rounding control: Down. */
2261#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2262/** Rounding control: Up. */
2263#define X86_FCW_RC_UP UINT16_C(0x0800)
2264/** Rounding control: Towards zero. */
2265#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2266/** Bits which should be zero, apparently. */
2267#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2268/** @} */
2269
2270/** @name SSE MXCSR
2271 * @{ */
2272/** Exception Flag: Invalid operation. */
2273#define X86_MSXCR_IE RT_BIT(0)
2274/** Exception Flag: Denormalized operand. */
2275#define X86_MSXCR_DE RT_BIT(1)
2276/** Exception Flag: Zero divide. */
2277#define X86_MSXCR_ZE RT_BIT(2)
2278/** Exception Flag: Overflow. */
2279#define X86_MSXCR_OE RT_BIT(3)
2280/** Exception Flag: Underflow. */
2281#define X86_MSXCR_UE RT_BIT(4)
2282/** Exception Flag: Precision. */
2283#define X86_MSXCR_PE RT_BIT(5)
2284
2285/** Denormals are zero. */
2286#define X86_MSXCR_DAZ RT_BIT(6)
2287
2288/** Exception Mask: Invalid operation. */
2289#define X86_MSXCR_IM RT_BIT(7)
2290/** Exception Mask: Denormalized operand. */
2291#define X86_MSXCR_DM RT_BIT(8)
2292/** Exception Mask: Zero divide. */
2293#define X86_MSXCR_ZM RT_BIT(9)
2294/** Exception Mask: Overflow. */
2295#define X86_MSXCR_OM RT_BIT(10)
2296/** Exception Mask: Underflow. */
2297#define X86_MSXCR_UM RT_BIT(11)
2298/** Exception Mask: Precision. */
2299#define X86_MSXCR_PM RT_BIT(12)
2300
2301/** Rounding control mask. */
2302#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2303/** Rounding control: To nearest. */
2304#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2305/** Rounding control: Down. */
2306#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2307/** Rounding control: Up. */
2308#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2309/** Rounding control: Towards zero. */
2310#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2311
2312/** Flush-to-zero for masked underflow. */
2313#define X86_MSXCR_FZ RT_BIT(15)
2314
2315/** Misaligned Exception Mask. */
2316#define X86_MSXCR_MM RT_BIT(16)
2317/** @} */
2318
2319
2320/** @name Selector Descriptor
2321 * @{
2322 */
2323
2324#ifndef VBOX_FOR_DTRACE_LIB
2325/**
2326 * Descriptor attributes (as seen by VT-x).
2327 */
2328typedef struct X86DESCATTRBITS
2329{
2330 /** 00 - Segment Type. */
2331 unsigned u4Type : 4;
2332 /** 04 - Descriptor Type. System(=0) or code/data selector */
2333 unsigned u1DescType : 1;
2334 /** 05 - Descriptor Privelege level. */
2335 unsigned u2Dpl : 2;
2336 /** 07 - Flags selector present(=1) or not. */
2337 unsigned u1Present : 1;
2338 /** 08 - Segment limit 16-19. */
2339 unsigned u4LimitHigh : 4;
2340 /** 0c - Available for system software. */
2341 unsigned u1Available : 1;
2342 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2343 unsigned u1Long : 1;
2344 /** 0e - This flags meaning depends on the segment type. Try make sense out
2345 * of the intel manual yourself. */
2346 unsigned u1DefBig : 1;
2347 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
2348 * clear byte. */
2349 unsigned u1Granularity : 1;
2350 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2351 unsigned u1Unusable : 1;
2352} X86DESCATTRBITS;
2353#endif /* !VBOX_FOR_DTRACE_LIB */
2354
2355/** @name X86DESCATTR masks
2356 * @{ */
2357#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2358#define X86DESCATTR_DT UINT32_C(0x00000010)
2359#define X86DESCATTR_DPL UINT32_C(0x00000060)
2360#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
2361#define X86DESCATTR_P UINT32_C(0x00000800)
2362#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2363#define X86DESCATTR_AVL UINT32_C(0x00001000)
2364#define X86DESCATTR_L UINT32_C(0x00002000)
2365#define X86DESCATTR_D UINT32_C(0x00004000)
2366#define X86DESCATTR_G UINT32_C(0x00008000)
2367#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2368/** @} */
2369
2370#pragma pack(1)
2371typedef union X86DESCATTR
2372{
2373 /** Unsigned integer view. */
2374 uint32_t u;
2375#ifndef VBOX_FOR_DTRACE_LIB
2376 /** Normal view. */
2377 X86DESCATTRBITS n;
2378#endif
2379} X86DESCATTR;
2380#pragma pack()
2381/** Pointer to descriptor attributes. */
2382typedef X86DESCATTR *PX86DESCATTR;
2383/** Pointer to const descriptor attributes. */
2384typedef const X86DESCATTR *PCX86DESCATTR;
2385
2386#ifndef VBOX_FOR_DTRACE_LIB
2387
2388/**
2389 * Generic descriptor table entry
2390 */
2391#pragma pack(1)
2392typedef struct X86DESCGENERIC
2393{
2394 /** 00 - Limit - Low word. */
2395 unsigned u16LimitLow : 16;
2396 /** 10 - Base address - lowe word.
2397 * Don't try set this to 24 because MSC is doing stupid things then. */
2398 unsigned u16BaseLow : 16;
2399 /** 20 - Base address - first 8 bits of high word. */
2400 unsigned u8BaseHigh1 : 8;
2401 /** 28 - Segment Type. */
2402 unsigned u4Type : 4;
2403 /** 2c - Descriptor Type. System(=0) or code/data selector */
2404 unsigned u1DescType : 1;
2405 /** 2d - Descriptor Privelege level. */
2406 unsigned u2Dpl : 2;
2407 /** 2f - Flags selector present(=1) or not. */
2408 unsigned u1Present : 1;
2409 /** 30 - Segment limit 16-19. */
2410 unsigned u4LimitHigh : 4;
2411 /** 34 - Available for system software. */
2412 unsigned u1Available : 1;
2413 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2414 unsigned u1Long : 1;
2415 /** 36 - This flags meaning depends on the segment type. Try make sense out
2416 * of the intel manual yourself. */
2417 unsigned u1DefBig : 1;
2418 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
2419 * clear byte. */
2420 unsigned u1Granularity : 1;
2421 /** 38 - Base address - highest 8 bits. */
2422 unsigned u8BaseHigh2 : 8;
2423} X86DESCGENERIC;
2424#pragma pack()
2425/** Pointer to a generic descriptor entry. */
2426typedef X86DESCGENERIC *PX86DESCGENERIC;
2427/** Pointer to a const generic descriptor entry. */
2428typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2429
2430/** @name Bit offsets of X86DESCGENERIC members.
2431 * @{*/
2432#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
2433#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
2434#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
2435#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
2436#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
2437#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
2438#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
2439#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
2440#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
2441#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
2442#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
2443#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
2444#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
2445/** @} */
2446
2447/**
2448 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2449 */
2450typedef struct X86DESCGATE
2451{
2452 /** 00 - Target code segment offset - Low word.
2453 * Ignored if task-gate. */
2454 unsigned u16OffsetLow : 16;
2455 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2456 * TSS selector if task-gate. */
2457 unsigned u16Sel : 16;
2458 /** 20 - Number of parameters for a call-gate.
2459 * Ignored if interrupt-, trap- or task-gate. */
2460 unsigned u4ParmCount : 4;
2461 /** 24 - Reserved / ignored. */
2462 unsigned u4Reserved : 4;
2463 /** 28 - Segment Type. */
2464 unsigned u4Type : 4;
2465 /** 2c - Descriptor Type (0 = system). */
2466 unsigned u1DescType : 1;
2467 /** 2d - Descriptor Privelege level. */
2468 unsigned u2Dpl : 2;
2469 /** 2f - Flags selector present(=1) or not. */
2470 unsigned u1Present : 1;
2471 /** 30 - Target code segment offset - High word.
2472 * Ignored if task-gate. */
2473 unsigned u16OffsetHigh : 16;
2474} X86DESCGATE;
2475/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2476typedef X86DESCGATE *PX86DESCGATE;
2477/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2478typedef const X86DESCGATE *PCX86DESCGATE;
2479
2480#endif /* VBOX_FOR_DTRACE_LIB */
2481
2482/**
2483 * Descriptor table entry.
2484 */
2485#pragma pack(1)
2486typedef union X86DESC
2487{
2488#ifndef VBOX_FOR_DTRACE_LIB
2489 /** Generic descriptor view. */
2490 X86DESCGENERIC Gen;
2491 /** Gate descriptor view. */
2492 X86DESCGATE Gate;
2493#endif
2494
2495 /** 8 bit unsigned integer view. */
2496 uint8_t au8[8];
2497 /** 16 bit unsigned integer view. */
2498 uint16_t au16[4];
2499 /** 32 bit unsigned integer view. */
2500 uint32_t au32[2];
2501 /** 64 bit unsigned integer view. */
2502 uint64_t au64[1];
2503 /** Unsigned integer view. */
2504 uint64_t u;
2505} X86DESC;
2506#ifndef VBOX_FOR_DTRACE_LIB
2507AssertCompileSize(X86DESC, 8);
2508#endif
2509#pragma pack()
2510/** Pointer to descriptor table entry. */
2511typedef X86DESC *PX86DESC;
2512/** Pointer to const descriptor table entry. */
2513typedef const X86DESC *PCX86DESC;
2514
2515/** @def X86DESC_BASE
2516 * Return the base address of a descriptor.
2517 */
2518#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
2519 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2520 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2521 | ( (a_pDesc)->Gen.u16BaseLow ) )
2522
2523/** @def X86DESC_LIMIT
2524 * Return the limit of a descriptor.
2525 */
2526#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
2527 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2528 | ( (a_pDesc)->Gen.u16LimitLow ) )
2529
2530/** @def X86DESC_LIMIT_G
2531 * Return the limit of a descriptor with the granularity bit taken into account.
2532 * @returns Selector limit (uint32_t).
2533 * @param a_pDesc Pointer to the descriptor.
2534 */
2535#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
2536 ( (a_pDesc)->Gen.u1Granularity \
2537 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
2538 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
2539 )
2540
2541/** @def X86DESC_GET_HID_ATTR
2542 * Get the descriptor attributes for the hidden register.
2543 */
2544#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
2545 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2546
2547#ifndef VBOX_FOR_DTRACE_LIB
2548
2549/**
2550 * 64 bits generic descriptor table entry
2551 * Note: most of these bits have no meaning in long mode.
2552 */
2553#pragma pack(1)
2554typedef struct X86DESC64GENERIC
2555{
2556 /** Limit - Low word - *IGNORED*. */
2557 unsigned u16LimitLow : 16;
2558 /** Base address - low word. - *IGNORED*
2559 * Don't try set this to 24 because MSC is doing stupid things then. */
2560 unsigned u16BaseLow : 16;
2561 /** Base address - first 8 bits of high word. - *IGNORED* */
2562 unsigned u8BaseHigh1 : 8;
2563 /** Segment Type. */
2564 unsigned u4Type : 4;
2565 /** Descriptor Type. System(=0) or code/data selector */
2566 unsigned u1DescType : 1;
2567 /** Descriptor Privelege level. */
2568 unsigned u2Dpl : 2;
2569 /** Flags selector present(=1) or not. */
2570 unsigned u1Present : 1;
2571 /** Segment limit 16-19. - *IGNORED* */
2572 unsigned u4LimitHigh : 4;
2573 /** Available for system software. - *IGNORED* */
2574 unsigned u1Available : 1;
2575 /** Long mode flag. */
2576 unsigned u1Long : 1;
2577 /** This flags meaning depends on the segment type. Try make sense out
2578 * of the intel manual yourself. */
2579 unsigned u1DefBig : 1;
2580 /** Granularity of the limit. If set 4KB granularity is used, if
2581 * clear byte. - *IGNORED* */
2582 unsigned u1Granularity : 1;
2583 /** Base address - highest 8 bits. - *IGNORED* */
2584 unsigned u8BaseHigh2 : 8;
2585 /** Base address - bits 63-32. */
2586 unsigned u32BaseHigh3 : 32;
2587 unsigned u8Reserved : 8;
2588 unsigned u5Zeros : 5;
2589 unsigned u19Reserved : 19;
2590} X86DESC64GENERIC;
2591#pragma pack()
2592/** Pointer to a generic descriptor entry. */
2593typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2594/** Pointer to a const generic descriptor entry. */
2595typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2596
2597/**
2598 * System descriptor table entry (64 bits)
2599 *
2600 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2601 */
2602#pragma pack(1)
2603typedef struct X86DESC64SYSTEM
2604{
2605 /** Limit - Low word. */
2606 unsigned u16LimitLow : 16;
2607 /** Base address - lowe word.
2608 * Don't try set this to 24 because MSC is doing stupid things then. */
2609 unsigned u16BaseLow : 16;
2610 /** Base address - first 8 bits of high word. */
2611 unsigned u8BaseHigh1 : 8;
2612 /** Segment Type. */
2613 unsigned u4Type : 4;
2614 /** Descriptor Type. System(=0) or code/data selector */
2615 unsigned u1DescType : 1;
2616 /** Descriptor Privelege level. */
2617 unsigned u2Dpl : 2;
2618 /** Flags selector present(=1) or not. */
2619 unsigned u1Present : 1;
2620 /** Segment limit 16-19. */
2621 unsigned u4LimitHigh : 4;
2622 /** Available for system software. */
2623 unsigned u1Available : 1;
2624 /** Reserved - 0. */
2625 unsigned u1Reserved : 1;
2626 /** This flags meaning depends on the segment type. Try make sense out
2627 * of the intel manual yourself. */
2628 unsigned u1DefBig : 1;
2629 /** Granularity of the limit. If set 4KB granularity is used, if
2630 * clear byte. */
2631 unsigned u1Granularity : 1;
2632 /** Base address - bits 31-24. */
2633 unsigned u8BaseHigh2 : 8;
2634 /** Base address - bits 63-32. */
2635 unsigned u32BaseHigh3 : 32;
2636 unsigned u8Reserved : 8;
2637 unsigned u5Zeros : 5;
2638 unsigned u19Reserved : 19;
2639} X86DESC64SYSTEM;
2640#pragma pack()
2641/** Pointer to a system descriptor entry. */
2642typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2643/** Pointer to a const system descriptor entry. */
2644typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2645
2646/**
2647 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2648 */
2649typedef struct X86DESC64GATE
2650{
2651 /** Target code segment offset - Low word. */
2652 unsigned u16OffsetLow : 16;
2653 /** Target code segment selector. */
2654 unsigned u16Sel : 16;
2655 /** Interrupt stack table for interrupt- and trap-gates.
2656 * Ignored by call-gates. */
2657 unsigned u3IST : 3;
2658 /** Reserved / ignored. */
2659 unsigned u5Reserved : 5;
2660 /** Segment Type. */
2661 unsigned u4Type : 4;
2662 /** Descriptor Type (0 = system). */
2663 unsigned u1DescType : 1;
2664 /** Descriptor Privelege level. */
2665 unsigned u2Dpl : 2;
2666 /** Flags selector present(=1) or not. */
2667 unsigned u1Present : 1;
2668 /** Target code segment offset - High word.
2669 * Ignored if task-gate. */
2670 unsigned u16OffsetHigh : 16;
2671 /** Target code segment offset - Top dword.
2672 * Ignored if task-gate. */
2673 unsigned u32OffsetTop : 32;
2674 /** Reserved / ignored / must be zero.
2675 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2676 unsigned u32Reserved : 32;
2677} X86DESC64GATE;
2678AssertCompileSize(X86DESC64GATE, 16);
2679/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2680typedef X86DESC64GATE *PX86DESC64GATE;
2681/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2682typedef const X86DESC64GATE *PCX86DESC64GATE;
2683
2684#endif /* VBOX_FOR_DTRACE_LIB */
2685
2686/**
2687 * Descriptor table entry.
2688 */
2689#pragma pack(1)
2690typedef union X86DESC64
2691{
2692#ifndef VBOX_FOR_DTRACE_LIB
2693 /** Generic descriptor view. */
2694 X86DESC64GENERIC Gen;
2695 /** System descriptor view. */
2696 X86DESC64SYSTEM System;
2697 /** Gate descriptor view. */
2698 X86DESC64GATE Gate;
2699#endif
2700
2701 /** 8 bit unsigned integer view. */
2702 uint8_t au8[16];
2703 /** 16 bit unsigned integer view. */
2704 uint16_t au16[8];
2705 /** 32 bit unsigned integer view. */
2706 uint32_t au32[4];
2707 /** 64 bit unsigned integer view. */
2708 uint64_t au64[2];
2709} X86DESC64;
2710#ifndef VBOX_FOR_DTRACE_LIB
2711AssertCompileSize(X86DESC64, 16);
2712#endif
2713#pragma pack()
2714/** Pointer to descriptor table entry. */
2715typedef X86DESC64 *PX86DESC64;
2716/** Pointer to const descriptor table entry. */
2717typedef const X86DESC64 *PCX86DESC64;
2718
2719/** @def X86DESC64_BASE
2720 * Return the base of a 64-bit descriptor.
2721 */
2722#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
2723 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2724 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2725 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2726 | ( (a_pDesc)->Gen.u16BaseLow ) )
2727
2728
2729
2730/** @name Host system descriptor table entry - Use with care!
2731 * @{ */
2732/** Host system descriptor table entry. */
2733#if HC_ARCH_BITS == 64
2734typedef X86DESC64 X86DESCHC;
2735#else
2736typedef X86DESC X86DESCHC;
2737#endif
2738/** Pointer to a host system descriptor table entry. */
2739#if HC_ARCH_BITS == 64
2740typedef PX86DESC64 PX86DESCHC;
2741#else
2742typedef PX86DESC PX86DESCHC;
2743#endif
2744/** Pointer to a const host system descriptor table entry. */
2745#if HC_ARCH_BITS == 64
2746typedef PCX86DESC64 PCX86DESCHC;
2747#else
2748typedef PCX86DESC PCX86DESCHC;
2749#endif
2750/** @} */
2751
2752
2753/** @name Selector Descriptor Types.
2754 * @{
2755 */
2756
2757/** @name Non-System Selector Types.
2758 * @{ */
2759/** Code(=set)/Data(=clear) bit. */
2760#define X86_SEL_TYPE_CODE 8
2761/** Memory(=set)/System(=clear) bit. */
2762#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2763/** Accessed bit. */
2764#define X86_SEL_TYPE_ACCESSED 1
2765/** Expand down bit (for data selectors only). */
2766#define X86_SEL_TYPE_DOWN 4
2767/** Conforming bit (for code selectors only). */
2768#define X86_SEL_TYPE_CONF 4
2769/** Write bit (for data selectors only). */
2770#define X86_SEL_TYPE_WRITE 2
2771/** Read bit (for code selectors only). */
2772#define X86_SEL_TYPE_READ 2
2773/** The bit number of the code segment read bit (relative to u4Type). */
2774#define X86_SEL_TYPE_READ_BIT 1
2775
2776/** Read only selector type. */
2777#define X86_SEL_TYPE_RO 0
2778/** Accessed read only selector type. */
2779#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
2780/** Read write selector type. */
2781#define X86_SEL_TYPE_RW 2
2782/** Accessed read write selector type. */
2783#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
2784/** Expand down read only selector type. */
2785#define X86_SEL_TYPE_RO_DOWN 4
2786/** Accessed expand down read only selector type. */
2787#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
2788/** Expand down read write selector type. */
2789#define X86_SEL_TYPE_RW_DOWN 6
2790/** Accessed expand down read write selector type. */
2791#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
2792/** Execute only selector type. */
2793#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
2794/** Accessed execute only selector type. */
2795#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2796/** Execute and read selector type. */
2797#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
2798/** Accessed execute and read selector type. */
2799#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2800/** Conforming execute only selector type. */
2801#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
2802/** Accessed Conforming execute only selector type. */
2803#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2804/** Conforming execute and write selector type. */
2805#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
2806/** Accessed Conforming execute and write selector type. */
2807#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2808/** @} */
2809
2810
2811/** @name System Selector Types.
2812 * @{ */
2813/** The TSS busy bit mask. */
2814#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2815
2816/** Undefined system selector type. */
2817#define X86_SEL_TYPE_SYS_UNDEFINED 0
2818/** 286 TSS selector. */
2819#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2820/** LDT selector. */
2821#define X86_SEL_TYPE_SYS_LDT 2
2822/** 286 TSS selector - Busy. */
2823#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2824/** 286 Callgate selector. */
2825#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2826/** Taskgate selector. */
2827#define X86_SEL_TYPE_SYS_TASK_GATE 5
2828/** 286 Interrupt gate selector. */
2829#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2830/** 286 Trapgate selector. */
2831#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2832/** Undefined system selector. */
2833#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2834/** 386 TSS selector. */
2835#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2836/** Undefined system selector. */
2837#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2838/** 386 TSS selector - Busy. */
2839#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2840/** 386 Callgate selector. */
2841#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2842/** Undefined system selector. */
2843#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2844/** 386 Interruptgate selector. */
2845#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2846/** 386 Trapgate selector. */
2847#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2848/** @} */
2849
2850/** @name AMD64 System Selector Types.
2851 * @{ */
2852/** LDT selector. */
2853#define AMD64_SEL_TYPE_SYS_LDT 2
2854/** TSS selector - Busy. */
2855#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2856/** TSS selector - Busy. */
2857#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2858/** Callgate selector. */
2859#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2860/** Interruptgate selector. */
2861#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2862/** Trapgate selector. */
2863#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2864/** @} */
2865
2866/** @} */
2867
2868
2869/** @name Descriptor Table Entry Flag Masks.
2870 * These are for the 2nd 32-bit word of a descriptor.
2871 * @{ */
2872/** Bits 8-11 - TYPE - Descriptor type mask. */
2873#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
2874/** Bit 12 - S - System (=0) or Code/Data (=1). */
2875#define X86_DESC_S RT_BIT(12)
2876/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2877#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
2878/** Bit 15 - P - Present. */
2879#define X86_DESC_P RT_BIT(15)
2880/** Bit 20 - AVL - Available for system software. */
2881#define X86_DESC_AVL RT_BIT(20)
2882/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2883#define X86_DESC_DB RT_BIT(22)
2884/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2885 * used, if clear byte. */
2886#define X86_DESC_G RT_BIT(23)
2887/** @} */
2888
2889/** @} */
2890
2891
2892/** @name Task Segments.
2893 * @{
2894 */
2895
2896/**
2897 * 16-bit Task Segment (TSS).
2898 */
2899#pragma pack(1)
2900typedef struct X86TSS16
2901{
2902 /** Back link to previous task. (static) */
2903 RTSEL selPrev;
2904 /** Ring-0 stack pointer. (static) */
2905 uint16_t sp0;
2906 /** Ring-0 stack segment. (static) */
2907 RTSEL ss0;
2908 /** Ring-1 stack pointer. (static) */
2909 uint16_t sp1;
2910 /** Ring-1 stack segment. (static) */
2911 RTSEL ss1;
2912 /** Ring-2 stack pointer. (static) */
2913 uint16_t sp2;
2914 /** Ring-2 stack segment. (static) */
2915 RTSEL ss2;
2916 /** IP before task switch. */
2917 uint16_t ip;
2918 /** FLAGS before task switch. */
2919 uint16_t flags;
2920 /** AX before task switch. */
2921 uint16_t ax;
2922 /** CX before task switch. */
2923 uint16_t cx;
2924 /** DX before task switch. */
2925 uint16_t dx;
2926 /** BX before task switch. */
2927 uint16_t bx;
2928 /** SP before task switch. */
2929 uint16_t sp;
2930 /** BP before task switch. */
2931 uint16_t bp;
2932 /** SI before task switch. */
2933 uint16_t si;
2934 /** DI before task switch. */
2935 uint16_t di;
2936 /** ES before task switch. */
2937 RTSEL es;
2938 /** CS before task switch. */
2939 RTSEL cs;
2940 /** SS before task switch. */
2941 RTSEL ss;
2942 /** DS before task switch. */
2943 RTSEL ds;
2944 /** LDTR before task switch. */
2945 RTSEL selLdt;
2946} X86TSS16;
2947#ifndef VBOX_FOR_DTRACE_LIB
2948AssertCompileSize(X86TSS16, 44);
2949#endif
2950#pragma pack()
2951/** Pointer to a 16-bit task segment. */
2952typedef X86TSS16 *PX86TSS16;
2953/** Pointer to a const 16-bit task segment. */
2954typedef const X86TSS16 *PCX86TSS16;
2955
2956
2957/**
2958 * 32-bit Task Segment (TSS).
2959 */
2960#pragma pack(1)
2961typedef struct X86TSS32
2962{
2963 /** Back link to previous task. (static) */
2964 RTSEL selPrev;
2965 uint16_t padding1;
2966 /** Ring-0 stack pointer. (static) */
2967 uint32_t esp0;
2968 /** Ring-0 stack segment. (static) */
2969 RTSEL ss0;
2970 uint16_t padding_ss0;
2971 /** Ring-1 stack pointer. (static) */
2972 uint32_t esp1;
2973 /** Ring-1 stack segment. (static) */
2974 RTSEL ss1;
2975 uint16_t padding_ss1;
2976 /** Ring-2 stack pointer. (static) */
2977 uint32_t esp2;
2978 /** Ring-2 stack segment. (static) */
2979 RTSEL ss2;
2980 uint16_t padding_ss2;
2981 /** Page directory for the task. (static) */
2982 uint32_t cr3;
2983 /** EIP before task switch. */
2984 uint32_t eip;
2985 /** EFLAGS before task switch. */
2986 uint32_t eflags;
2987 /** EAX before task switch. */
2988 uint32_t eax;
2989 /** ECX before task switch. */
2990 uint32_t ecx;
2991 /** EDX before task switch. */
2992 uint32_t edx;
2993 /** EBX before task switch. */
2994 uint32_t ebx;
2995 /** ESP before task switch. */
2996 uint32_t esp;
2997 /** EBP before task switch. */
2998 uint32_t ebp;
2999 /** ESI before task switch. */
3000 uint32_t esi;
3001 /** EDI before task switch. */
3002 uint32_t edi;
3003 /** ES before task switch. */
3004 RTSEL es;
3005 uint16_t padding_es;
3006 /** CS before task switch. */
3007 RTSEL cs;
3008 uint16_t padding_cs;
3009 /** SS before task switch. */
3010 RTSEL ss;
3011 uint16_t padding_ss;
3012 /** DS before task switch. */
3013 RTSEL ds;
3014 uint16_t padding_ds;
3015 /** FS before task switch. */
3016 RTSEL fs;
3017 uint16_t padding_fs;
3018 /** GS before task switch. */
3019 RTSEL gs;
3020 uint16_t padding_gs;
3021 /** LDTR before task switch. */
3022 RTSEL selLdt;
3023 uint16_t padding_ldt;
3024 /** Debug trap flag */
3025 uint16_t fDebugTrap;
3026 /** Offset relative to the TSS of the start of the I/O Bitmap
3027 * and the end of the interrupt redirection bitmap. */
3028 uint16_t offIoBitmap;
3029 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3030 uint8_t IntRedirBitmap[32];
3031} X86TSS32;
3032#pragma pack()
3033/** Pointer to task segment. */
3034typedef X86TSS32 *PX86TSS32;
3035/** Pointer to const task segment. */
3036typedef const X86TSS32 *PCX86TSS32;
3037
3038
3039/**
3040 * 64-bit Task segment.
3041 */
3042#pragma pack(1)
3043typedef struct X86TSS64
3044{
3045 /** Reserved. */
3046 uint32_t u32Reserved;
3047 /** Ring-0 stack pointer. (static) */
3048 uint64_t rsp0;
3049 /** Ring-1 stack pointer. (static) */
3050 uint64_t rsp1;
3051 /** Ring-2 stack pointer. (static) */
3052 uint64_t rsp2;
3053 /** Reserved. */
3054 uint32_t u32Reserved2[2];
3055 /* IST */
3056 uint64_t ist1;
3057 uint64_t ist2;
3058 uint64_t ist3;
3059 uint64_t ist4;
3060 uint64_t ist5;
3061 uint64_t ist6;
3062 uint64_t ist7;
3063 /* Reserved. */
3064 uint16_t u16Reserved[5];
3065 /** Offset relative to the TSS of the start of the I/O Bitmap
3066 * and the end of the interrupt redirection bitmap. */
3067 uint16_t offIoBitmap;
3068 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3069 uint8_t IntRedirBitmap[32];
3070} X86TSS64;
3071#pragma pack()
3072/** Pointer to a 64-bit task segment. */
3073typedef X86TSS64 *PX86TSS64;
3074/** Pointer to a const 64-bit task segment. */
3075typedef const X86TSS64 *PCX86TSS64;
3076#ifndef VBOX_FOR_DTRACE_LIB
3077AssertCompileSize(X86TSS64, 136);
3078#endif
3079
3080/** @} */
3081
3082
3083/** @name Selectors.
3084 * @{
3085 */
3086
3087/**
3088 * The shift used to convert a selector from and to index an index (C).
3089 */
3090#define X86_SEL_SHIFT 3
3091
3092/**
3093 * The mask used to mask off the table indicator and RPL of an selector.
3094 */
3095#define X86_SEL_MASK 0xfff8U
3096
3097/**
3098 * The mask used to mask off the RPL of an selector.
3099 * This is suitable for checking for NULL selectors.
3100 */
3101#define X86_SEL_MASK_OFF_RPL 0xfffcU
3102
3103/**
3104 * The bit indicating that a selector is in the LDT and not in the GDT.
3105 */
3106#define X86_SEL_LDT 0x0004U
3107
3108/**
3109 * The bit mask for getting the RPL of a selector.
3110 */
3111#define X86_SEL_RPL 0x0003U
3112
3113/**
3114 * The mask covering both RPL and LDT.
3115 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3116 * checks.
3117 */
3118#define X86_SEL_RPL_LDT 0x0007U
3119
3120/** @} */
3121
3122
3123/**
3124 * x86 Exceptions/Faults/Traps.
3125 */
3126typedef enum X86XCPT
3127{
3128 /** \#DE - Divide error. */
3129 X86_XCPT_DE = 0x00,
3130 /** \#DB - Debug event (single step, DRx, ..) */
3131 X86_XCPT_DB = 0x01,
3132 /** NMI - Non-Maskable Interrupt */
3133 X86_XCPT_NMI = 0x02,
3134 /** \#BP - Breakpoint (INT3). */
3135 X86_XCPT_BP = 0x03,
3136 /** \#OF - Overflow (INTO). */
3137 X86_XCPT_OF = 0x04,
3138 /** \#BR - Bound range exceeded (BOUND). */
3139 X86_XCPT_BR = 0x05,
3140 /** \#UD - Undefined opcode. */
3141 X86_XCPT_UD = 0x06,
3142 /** \#NM - Device not available (math coprocessor device). */
3143 X86_XCPT_NM = 0x07,
3144 /** \#DF - Double fault. */
3145 X86_XCPT_DF = 0x08,
3146 /** ??? - Coprocessor segment overrun (obsolete). */
3147 X86_XCPT_CO_SEG_OVERRUN = 0x09,
3148 /** \#TS - Taskswitch (TSS). */
3149 X86_XCPT_TS = 0x0a,
3150 /** \#NP - Segment no present. */
3151 X86_XCPT_NP = 0x0b,
3152 /** \#SS - Stack segment fault. */
3153 X86_XCPT_SS = 0x0c,
3154 /** \#GP - General protection fault. */
3155 X86_XCPT_GP = 0x0d,
3156 /** \#PF - Page fault. */
3157 X86_XCPT_PF = 0x0e,
3158 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3159 /** \#MF - Math fault (FPU). */
3160 X86_XCPT_MF = 0x10,
3161 /** \#AC - Alignment check. */
3162 X86_XCPT_AC = 0x11,
3163 /** \#MC - Machine check. */
3164 X86_XCPT_MC = 0x12,
3165 /** \#XF - SIMD Floating-Pointer Exception. */
3166 X86_XCPT_XF = 0x13,
3167 /** \#VE - Virtualzation Exception. */
3168 X86_XCPT_VE = 0x14,
3169 /** \#SX - Security Exception. */
3170 X86_XCPT_SX = 0x1f
3171} X86XCPT;
3172/** Pointer to a x86 exception code. */
3173typedef X86XCPT *PX86XCPT;
3174/** Pointer to a const x86 exception code. */
3175typedef const X86XCPT *PCX86XCPT;
3176/** The maximum exception value. */
3177#define X86_XCPT_MAX (X86_XCPT_SX)
3178
3179
3180/** @name Trap Error Codes
3181 * @{
3182 */
3183/** External indicator. */
3184#define X86_TRAP_ERR_EXTERNAL 1
3185/** IDT indicator. */
3186#define X86_TRAP_ERR_IDT 2
3187/** Descriptor table indicator - If set LDT, if clear GDT. */
3188#define X86_TRAP_ERR_TI 4
3189/** Mask for getting the selector. */
3190#define X86_TRAP_ERR_SEL_MASK 0xfff8
3191/** Shift for getting the selector table index (C type index). */
3192#define X86_TRAP_ERR_SEL_SHIFT 3
3193/** @} */
3194
3195
3196/** @name \#PF Trap Error Codes
3197 * @{
3198 */
3199/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3200#define X86_TRAP_PF_P RT_BIT(0)
3201/** Bit 1 - R/W - Read (clear) or write (set) access. */
3202#define X86_TRAP_PF_RW RT_BIT(1)
3203/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3204#define X86_TRAP_PF_US RT_BIT(2)
3205/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3206#define X86_TRAP_PF_RSVD RT_BIT(3)
3207/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3208#define X86_TRAP_PF_ID RT_BIT(4)
3209/** @} */
3210
3211#pragma pack(1)
3212/**
3213 * 32-bit IDTR/GDTR.
3214 */
3215typedef struct X86XDTR32
3216{
3217 /** Size of the descriptor table. */
3218 uint16_t cb;
3219 /** Address of the descriptor table. */
3220#ifndef VBOX_FOR_DTRACE_LIB
3221 uint32_t uAddr;
3222#else
3223 uint16_t au16Addr[2];
3224#endif
3225} X86XDTR32, *PX86XDTR32;
3226#pragma pack()
3227
3228#pragma pack(1)
3229/**
3230 * 64-bit IDTR/GDTR.
3231 */
3232typedef struct X86XDTR64
3233{
3234 /** Size of the descriptor table. */
3235 uint16_t cb;
3236 /** Address of the descriptor table. */
3237#ifndef VBOX_FOR_DTRACE_LIB
3238 uint64_t uAddr;
3239#else
3240 uint16_t au16Addr[4];
3241#endif
3242} X86XDTR64, *PX86XDTR64;
3243#pragma pack()
3244
3245
3246/** @name ModR/M
3247 * @{ */
3248#define X86_MODRM_RM_MASK UINT8_C(0x07)
3249#define X86_MODRM_REG_MASK UINT8_C(0x38)
3250#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3251#define X86_MODRM_REG_SHIFT 3
3252#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3253#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3254#define X86_MODRM_MOD_SHIFT 6
3255#ifndef VBOX_FOR_DTRACE_LIB
3256AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
3257AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3258AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3259#endif
3260/** @} */
3261
3262/** @name SIB
3263 * @{ */
3264#define X86_SIB_BASE_MASK UINT8_C(0x07)
3265#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3266#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3267#define X86_SIB_INDEX_SHIFT 3
3268#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3269#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3270#define X86_SIB_SCALE_SHIFT 6
3271#ifndef VBOX_FOR_DTRACE_LIB
3272AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
3273AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3274AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3275#endif
3276/** @} */
3277
3278/** @name General register indexes
3279 * @{ */
3280#define X86_GREG_xAX 0
3281#define X86_GREG_xCX 1
3282#define X86_GREG_xDX 2
3283#define X86_GREG_xBX 3
3284#define X86_GREG_xSP 4
3285#define X86_GREG_xBP 5
3286#define X86_GREG_xSI 6
3287#define X86_GREG_xDI 7
3288#define X86_GREG_x8 8
3289#define X86_GREG_x9 9
3290#define X86_GREG_x10 10
3291#define X86_GREG_x11 11
3292#define X86_GREG_x12 12
3293#define X86_GREG_x13 13
3294#define X86_GREG_x14 14
3295#define X86_GREG_x15 15
3296/** @} */
3297
3298/** @name X86_SREG_XXX - Segment register indexes.
3299 * @{ */
3300#define X86_SREG_ES 0
3301#define X86_SREG_CS 1
3302#define X86_SREG_SS 2
3303#define X86_SREG_DS 3
3304#define X86_SREG_FS 4
3305#define X86_SREG_GS 5
3306/** @} */
3307/** Segment register count. */
3308#define X86_SREG_COUNT 6
3309
3310
3311/** @name X86_OP_XXX - Prefixes
3312 * @{ */
3313#define X86_OP_PRF_CS UINT8_C(0x2e)
3314#define X86_OP_PRF_SS UINT8_C(0x36)
3315#define X86_OP_PRF_DS UINT8_C(0x3e)
3316#define X86_OP_PRF_ES UINT8_C(0x26)
3317#define X86_OP_PRF_FS UINT8_C(0x64)
3318#define X86_OP_PRF_GS UINT8_C(0x65)
3319#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3320#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3321#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3322#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3323#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3324#define X86_OP_REX_B UINT8_C(0x41)
3325#define X86_OP_REX_X UINT8_C(0x42)
3326#define X86_OP_REX_R UINT8_C(0x44)
3327#define X86_OP_REX_W UINT8_C(0x48)
3328/** @} */
3329
3330
3331/** @} */
3332
3333#endif
3334
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