x86.h@ 47660

Last change on this file since 47660 was 47660, checked in by vboxsync, 11 years ago
VMM: Debug register handling redo. (only partly tested on AMD-V so far.)
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 119.3 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	/** Bit 1 - Reserved, reads as 1. */
165	#define X86_EFL_1 RT_BIT(1)
166	/** Bit 2 - PF - Parity flag - Status flag. */
167	#define X86_EFL_PF RT_BIT(2)
168	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169	#define X86_EFL_AF RT_BIT(4)
170	/** Bit 6 - ZF - Zero flag - Status flag. */
171	#define X86_EFL_ZF RT_BIT(6)
172	/** Bit 7 - SF - Signed flag - Status flag. */
173	#define X86_EFL_SF RT_BIT(7)
174	/** Bit 8 - TF - Trap flag - System flag. */
175	#define X86_EFL_TF RT_BIT(8)
176	/** Bit 9 - IF - Interrupt flag - System flag. */
177	#define X86_EFL_IF RT_BIT(9)
178	/** Bit 10 - DF - Direction flag - Control flag. */
179	#define X86_EFL_DF RT_BIT(10)
180	/** Bit 11 - OF - Overflow flag - Status flag. */
181	#define X86_EFL_OF RT_BIT(11)
182	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
184	/** Bit 14 - NT - Nested task flag - System flag. */
185	#define X86_EFL_NT RT_BIT(14)
186	/** Bit 16 - RF - Resume flag - System flag. */
187	#define X86_EFL_RF RT_BIT(16)
188	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189	#define X86_EFL_VM RT_BIT(17)
190	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191	#define X86_EFL_AC RT_BIT(18)
192	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193	#define X86_EFL_VIF RT_BIT(19)
194	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195	#define X86_EFL_VIP RT_BIT(20)
196	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197	#define X86_EFL_ID RT_BIT(21)
198	/** All live bits. */
199	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
200	/** Read as 1 bits. */
201	#define X86_EFL_RA1_MASK RT_BIT_32(1)
202	/** IOPL shift. */
203	#define X86_EFL_IOPL_SHIFT 12
204	/** The the IOPL level from the flags. */
205	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
206	/** Bits restored by popf */
207	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
208	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
209	/** @} */
210
211
212	/** CPUID Feature information - ECX.
213	* CPUID query with EAX=1.
214	*/
215	#ifndef VBOX_FOR_DTRACE_LIB
216	typedef struct X86CPUIDFEATECX
217	{
218	/** Bit 0 - SSE3 - Supports SSE3 or not. */
219	unsigned u1SSE3 : 1;
220	/** Bit 1 - PCLMULQDQ. */
221	unsigned u1PCLMULQDQ : 1;
222	/** Bit 2 - DS Area 64-bit layout. */
223	unsigned u1DTE64 : 1;
224	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
225	unsigned u1Monitor : 1;
226	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
227	unsigned u1CPLDS : 1;
228	/** Bit 5 - VMX - Virtual Machine Technology. */
229	unsigned u1VMX : 1;
230	/** Bit 6 - SMX: Safer Mode Extensions. */
231	unsigned u1SMX : 1;
232	/** Bit 7 - EST - Enh. SpeedStep Tech. */
233	unsigned u1EST : 1;
234	/** Bit 8 - TM2 - Terminal Monitor 2. */
235	unsigned u1TM2 : 1;
236	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
237	unsigned u1SSSE3 : 1;
238	/** Bit 10 - CNTX-ID - L1 Context ID. */
239	unsigned u1CNTXID : 1;
240	/** Bit 11 - Reserved. */
241	unsigned u1Reserved1 : 1;
242	/** Bit 12 - FMA. */
243	unsigned u1FMA : 1;
244	/** Bit 13 - CX16 - CMPXCHG16B. */
245	unsigned u1CX16 : 1;
246	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
247	unsigned u1TPRUpdate : 1;
248	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
249	unsigned u1PDCM : 1;
250	/** Bit 16 - Reserved. */
251	unsigned u1Reserved2 : 1;
252	/** Bit 17 - PCID - Process-context identifiers. */
253	unsigned u1PCID : 1;
254	/** Bit 18 - Direct Cache Access. */
255	unsigned u1DCA : 1;
256	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
257	unsigned u1SSE4_1 : 1;
258	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
259	unsigned u1SSE4_2 : 1;
260	/** Bit 21 - x2APIC. */
261	unsigned u1x2APIC : 1;
262	/** Bit 22 - MOVBE - Supports MOVBE. */
263	unsigned u1MOVBE : 1;
264	/** Bit 23 - POPCNT - Supports POPCNT. */
265	unsigned u1POPCNT : 1;
266	/** Bit 24 - TSC-Deadline. */
267	unsigned u1TSCDEADLINE : 1;
268	/** Bit 25 - AES. */
269	unsigned u1AES : 1;
270	/** Bit 26 - XSAVE - Supports XSAVE. */
271	unsigned u1XSAVE : 1;
272	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
273	unsigned u1OSXSAVE : 1;
274	/** Bit 28 - AVX - Supports AVX instruction extensions. */
275	unsigned u1AVX : 1;
276	/** Bit 29 - 30 - Reserved */
277	unsigned u2Reserved3 : 2;
278	/** Bit 31 - Hypervisor present (we're a guest). */
279	unsigned u1HVP : 1;
280	} X86CPUIDFEATECX;
281	#else /* VBOX_FOR_DTRACE_LIB */
282	typedef uint32_t X86CPUIDFEATECX;
283	#endif /* VBOX_FOR_DTRACE_LIB */
284	/** Pointer to CPUID Feature Information - ECX. */
285	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
286	/** Pointer to const CPUID Feature Information - ECX. */
287	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
288
289
290	/** CPUID Feature Information - EDX.
291	* CPUID query with EAX=1.
292	*/
293	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
294	typedef struct X86CPUIDFEATEDX
295	{
296	/** Bit 0 - FPU - x87 FPU on Chip. */
297	unsigned u1FPU : 1;
298	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
299	unsigned u1VME : 1;
300	/** Bit 2 - DE - Debugging extensions. */
301	unsigned u1DE : 1;
302	/** Bit 3 - PSE - Page Size Extension. */
303	unsigned u1PSE : 1;
304	/** Bit 4 - TSC - Time Stamp Counter. */
305	unsigned u1TSC : 1;
306	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
307	unsigned u1MSR : 1;
308	/** Bit 6 - PAE - Physical Address Extension. */
309	unsigned u1PAE : 1;
310	/** Bit 7 - MCE - Machine Check Exception. */
311	unsigned u1MCE : 1;
312	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
313	unsigned u1CX8 : 1;
314	/** Bit 9 - APIC - APIC On-Chip. */
315	unsigned u1APIC : 1;
316	/** Bit 10 - Reserved. */
317	unsigned u1Reserved1 : 1;
318	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
319	unsigned u1SEP : 1;
320	/** Bit 12 - MTRR - Memory Type Range Registers. */
321	unsigned u1MTRR : 1;
322	/** Bit 13 - PGE - PTE Global Bit. */
323	unsigned u1PGE : 1;
324	/** Bit 14 - MCA - Machine Check Architecture. */
325	unsigned u1MCA : 1;
326	/** Bit 15 - CMOV - Conditional Move Instructions. */
327	unsigned u1CMOV : 1;
328	/** Bit 16 - PAT - Page Attribute Table. */
329	unsigned u1PAT : 1;
330	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
331	unsigned u1PSE36 : 1;
332	/** Bit 18 - PSN - Processor Serial Number. */
333	unsigned u1PSN : 1;
334	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
335	unsigned u1CLFSH : 1;
336	/** Bit 20 - Reserved. */
337	unsigned u1Reserved2 : 1;
338	/** Bit 21 - DS - Debug Store. */
339	unsigned u1DS : 1;
340	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
341	unsigned u1ACPI : 1;
342	/** Bit 23 - MMX - Intel MMX 'Technology'. */
343	unsigned u1MMX : 1;
344	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
345	unsigned u1FXSR : 1;
346	/** Bit 25 - SSE - SSE Support. */
347	unsigned u1SSE : 1;
348	/** Bit 26 - SSE2 - SSE2 Support. */
349	unsigned u1SSE2 : 1;
350	/** Bit 27 - SS - Self Snoop. */
351	unsigned u1SS : 1;
352	/** Bit 28 - HTT - Hyper-Threading Technology. */
353	unsigned u1HTT : 1;
354	/** Bit 29 - TM - Thermal Monitor. */
355	unsigned u1TM : 1;
356	/** Bit 30 - Reserved - . */
357	unsigned u1Reserved3 : 1;
358	/** Bit 31 - PBE - Pending Break Enabled. */
359	unsigned u1PBE : 1;
360	} X86CPUIDFEATEDX;
361	#else /* VBOX_FOR_DTRACE_LIB */
362	typedef uint32_t X86CPUIDFEATEDX;
363	#endif /* VBOX_FOR_DTRACE_LIB */
364	/** Pointer to CPUID Feature Information - EDX. */
365	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
366	/** Pointer to const CPUID Feature Information - EDX. */
367	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
368
369	/** @name CPUID Vendor information.
370	* CPUID query with EAX=0.
371	* @{
372	*/
373	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
374	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
375	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
376
377	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
378	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
379	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
380
381	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
382	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
383	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
384	/** @} */
385
386
387	/** @name CPUID Feature information.
388	* CPUID query with EAX=1.
389	* @{
390	*/
391	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
392	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
393	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
394	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
395	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
396	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
397	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
398	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
399	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
400	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
401	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
402	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
403	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
404	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
405	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
406	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
407	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
408	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
409	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
410	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
411	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
412	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
413	/** ECX Bit 12 - FMA. */
414	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
415	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
416	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
417	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
418	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
419	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
420	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
421	/** ECX Bit 17 - PCID - Process-context identifiers. */
422	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
423	/** ECX Bit 18 - DCA - Direct Cache Access. */
424	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
425	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
426	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
427	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
428	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
429	/** ECX Bit 21 - x2APIC support. */
430	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
431	/** ECX Bit 22 - MOVBE instruction. */
432	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
433	/** ECX Bit 23 - POPCNT instruction. */
434	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
435	/** ECX Bir 24 - TSC-Deadline. */
436	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
437	/** ECX Bit 25 - AES instructions. */
438	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
439	/** ECX Bit 26 - XSAVE instruction. */
440	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
441	/** ECX Bit 27 - OSXSAVE instruction. */
442	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
443	/** ECX Bit 28 - AVX. */
444	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
445	/** ECX Bit 31 - Hypervisor Present (software only). */
446	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
447
448
449	/** Bit 0 - FPU - x87 FPU on Chip. */
450	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
451	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
452	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
453	/** Bit 2 - DE - Debugging extensions. */
454	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
455	/** Bit 3 - PSE - Page Size Extension. */
456	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
457	/** Bit 4 - TSC - Time Stamp Counter. */
458	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
459	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
460	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
461	/** Bit 6 - PAE - Physical Address Extension. */
462	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
463	/** Bit 7 - MCE - Machine Check Exception. */
464	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
465	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
466	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
467	/** Bit 9 - APIC - APIC On-Chip. */
468	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
469	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
470	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
471	/** Bit 12 - MTRR - Memory Type Range Registers. */
472	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
473	/** Bit 13 - PGE - PTE Global Bit. */
474	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
475	/** Bit 14 - MCA - Machine Check Architecture. */
476	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
477	/** Bit 15 - CMOV - Conditional Move Instructions. */
478	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
479	/** Bit 16 - PAT - Page Attribute Table. */
480	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
481	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
482	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
483	/** Bit 18 - PSN - Processor Serial Number. */
484	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
485	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
486	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
487	/** Bit 21 - DS - Debug Store. */
488	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
489	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
490	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
491	/** Bit 23 - MMX - Intel MMX Technology. */
492	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
493	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
494	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
495	/** Bit 25 - SSE - SSE Support. */
496	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
497	/** Bit 26 - SSE2 - SSE2 Support. */
498	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
499	/** Bit 27 - SS - Self Snoop. */
500	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
501	/** Bit 28 - HTT - Hyper-Threading Technology. */
502	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
503	/** Bit 29 - TM - Therm. Monitor. */
504	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
505	/** Bit 31 - PBE - Pending Break Enabled. */
506	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
507	/** @} */
508
509	/** @name CPUID mwait/monitor information.
510	* CPUID query with EAX=5.
511	* @{
512	*/
513	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
514	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
515	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
516	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
517	/** @} */
518
519
520	/** @name CPUID Extended Feature information.
521	* CPUID query with EAX=0x80000001.
522	* @{
523	*/
524	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
525	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
526
527	/** EDX Bit 11 - SYSCALL/SYSRET. */
528	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
529	/** EDX Bit 20 - No-Execute/Execute-Disable. */
530	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
531	/** EDX Bit 26 - 1 GB large page. */
532	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
533	/** EDX Bit 27 - RDTSCP. */
534	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
535	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
536	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
537	/** @}*/
538
539	/** @name CPUID AMD Feature information.
540	* CPUID query with EAX=0x80000001.
541	* @{
542	*/
543	/** Bit 0 - FPU - x87 FPU on Chip. */
544	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
545	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
546	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
547	/** Bit 2 - DE - Debugging extensions. */
548	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
549	/** Bit 3 - PSE - Page Size Extension. */
550	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
551	/** Bit 4 - TSC - Time Stamp Counter. */
552	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
553	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
554	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
555	/** Bit 6 - PAE - Physical Address Extension. */
556	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
557	/** Bit 7 - MCE - Machine Check Exception. */
558	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
559	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
560	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
561	/** Bit 9 - APIC - APIC On-Chip. */
562	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
563	/** Bit 12 - MTRR - Memory Type Range Registers. */
564	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
565	/** Bit 13 - PGE - PTE Global Bit. */
566	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
567	/** Bit 14 - MCA - Machine Check Architecture. */
568	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
569	/** Bit 15 - CMOV - Conditional Move Instructions. */
570	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
571	/** Bit 16 - PAT - Page Attribute Table. */
572	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
573	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
574	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
575	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
576	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
577	/** Bit 23 - MMX - Intel MMX Technology. */
578	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
579	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
580	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
581	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
582	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
583	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
584	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
585	/** Bit 31 - 3DNOW - AMD 3DNow. */
586	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
587
588	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
589	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
590	/** Bit 2 - SVM - AMD VM extensions. */
591	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
592	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
593	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
594	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
595	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
596	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
597	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
598	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
599	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
600	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
601	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
602	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
603	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
604	/** Bit 9 - OSVW - AMD OS visible workaround. */
605	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
606	/** Bit 10 - IBS - Instruct based sampling. */
607	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
608	/** Bit 11 - SSE5 - SSE5 instruction support. */
609	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
610	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
611	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
612	/** Bit 13 - WDT - AMD Watchdog timer support. */
613	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
614
615	/** @} */
616
617
618	/** @name CPUID AMD Feature information.
619	* CPUID query with EAX=0x80000007.
620	* @{
621	*/
622	/** Bit 0 - TS - Temperature Sensor. */
623	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
624	/** Bit 1 - FID - Frequency ID Control. */
625	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
626	/** Bit 2 - VID - Voltage ID Control. */
627	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
628	/** Bit 3 - TTP - THERMTRIP. */
629	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
630	/** Bit 4 - TM - Hardware Thermal Control. */
631	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
632	/** Bit 5 - STC - Software Thermal Control. */
633	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
634	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
635	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
636	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
637	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
638	/** Bit 8 - TSCINVAR - TSC Invariant. */
639	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
640	/** @} */
641
642
643	/** @name CR0
644	* @{ */
645	/** Bit 0 - PE - Protection Enabled */
646	#define X86_CR0_PE RT_BIT(0)
647	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
648	/** Bit 1 - MP - Monitor Coprocessor */
649	#define X86_CR0_MP RT_BIT(1)
650	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
651	/** Bit 2 - EM - Emulation. */
652	#define X86_CR0_EM RT_BIT(2)
653	#define X86_CR0_EMULATE_FPU RT_BIT(2)
654	/** Bit 3 - TS - Task Switch. */
655	#define X86_CR0_TS RT_BIT(3)
656	#define X86_CR0_TASK_SWITCH RT_BIT(3)
657	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
658	#define X86_CR0_ET RT_BIT(4)
659	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
660	/** Bit 5 - NE - Numeric error. */
661	#define X86_CR0_NE RT_BIT(5)
662	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
663	/** Bit 16 - WP - Write Protect. */
664	#define X86_CR0_WP RT_BIT(16)
665	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
666	/** Bit 18 - AM - Alignment Mask. */
667	#define X86_CR0_AM RT_BIT(18)
668	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
669	/** Bit 29 - NW - Not Write-though. */
670	#define X86_CR0_NW RT_BIT(29)
671	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
672	/** Bit 30 - WP - Cache Disable. */
673	#define X86_CR0_CD RT_BIT(30)
674	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
675	/** Bit 31 - PG - Paging. */
676	#define X86_CR0_PG RT_BIT(31)
677	#define X86_CR0_PAGING RT_BIT(31)
678	/** @} */
679
680
681	/** @name CR3
682	* @{ */
683	/** Bit 3 - PWT - Page-level Writes Transparent. */
684	#define X86_CR3_PWT RT_BIT(3)
685	/** Bit 4 - PCD - Page-level Cache Disable. */
686	#define X86_CR3_PCD RT_BIT(4)
687	/** Bits 12-31 - - Page directory page number. */
688	#define X86_CR3_PAGE_MASK (0xfffff000)
689	/** Bits 5-31 - - PAE Page directory page number. */
690	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
691	/** Bits 12-51 - - AMD64 Page directory page number. */
692	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
693	/** @} */
694
695
696	/** @name CR4
697	* @{ */
698	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
699	#define X86_CR4_VME RT_BIT(0)
700	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
701	#define X86_CR4_PVI RT_BIT(1)
702	/** Bit 2 - TSD - Time Stamp Disable. */
703	#define X86_CR4_TSD RT_BIT(2)
704	/** Bit 3 - DE - Debugging Extensions. */
705	#define X86_CR4_DE RT_BIT(3)
706	/** Bit 4 - PSE - Page Size Extension. */
707	#define X86_CR4_PSE RT_BIT(4)
708	/** Bit 5 - PAE - Physical Address Extension. */
709	#define X86_CR4_PAE RT_BIT(5)
710	/** Bit 6 - MCE - Machine-Check Enable. */
711	#define X86_CR4_MCE RT_BIT(6)
712	/** Bit 7 - PGE - Page Global Enable. */
713	#define X86_CR4_PGE RT_BIT(7)
714	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
715	#define X86_CR4_PCE RT_BIT(8)
716	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
717	#define X86_CR4_OSFSXR RT_BIT(9)
718	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
719	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
720	/** Bit 13 - VMXE - VMX mode is enabled. */
721	#define X86_CR4_VMXE RT_BIT(13)
722	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
723	#define X86_CR4_SMXE RT_BIT(14)
724	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
725	#define X86_CR4_PCIDE RT_BIT(17)
726	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
727	* extended states. */
728	#define X86_CR4_OSXSAVE RT_BIT(18)
729	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
730	#define X86_CR4_SMEP RT_BIT(20)
731	/** @} */
732
733
734	/** @name DR6
735	* @{ */
736	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
737	#define X86_DR6_B0 RT_BIT(0)
738	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
739	#define X86_DR6_B1 RT_BIT(1)
740	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
741	#define X86_DR6_B2 RT_BIT(2)
742	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
743	#define X86_DR6_B3 RT_BIT(3)
744	/** Mask of all the Bx bits. */
745	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
746	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
747	#define X86_DR6_BD RT_BIT(13)
748	/** Bit 14 - BS - Single step */
749	#define X86_DR6_BS RT_BIT(14)
750	/** Bit 15 - BT - Task switch. (TSS T bit.) */
751	#define X86_DR6_BT RT_BIT(15)
752	/** Value of DR6 after powerup/reset. */
753	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
754	/** Bits which must be 1s in DR6. */
755	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
756	/** Bits which must be 0s in DR6. */
757	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
758	/** Bits which must be 0s on writes to DR6. */
759	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
760	/** @} */
761
762	/** Get the DR6.Bx bit for a the given breakpoint. */
763	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
764
765
766	/** @name DR7
767	* @{ */
768	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
769	#define X86_DR7_L0 RT_BIT(0)
770	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
771	#define X86_DR7_G0 RT_BIT(1)
772	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
773	#define X86_DR7_L1 RT_BIT(2)
774	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
775	#define X86_DR7_G1 RT_BIT(3)
776	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
777	#define X86_DR7_L2 RT_BIT(4)
778	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
779	#define X86_DR7_G2 RT_BIT(5)
780	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
781	#define X86_DR7_L3 RT_BIT(6)
782	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
783	#define X86_DR7_G3 RT_BIT(7)
784	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
785	#define X86_DR7_LE RT_BIT(8)
786	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
787	#define X86_DR7_GE RT_BIT(9)
788
789	/** L0, L1, L2, and L3. */
790	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
791	/** L0, L1, L2, and L3. */
792	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
793
794	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
795	* any DR register is accessed. */
796	#define X86_DR7_GD RT_BIT(13)
797	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
798	#define X86_DR7_RW0_MASK (3 << 16)
799	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
800	#define X86_DR7_LEN0_MASK (3 << 18)
801	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
802	#define X86_DR7_RW1_MASK (3 << 20)
803	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
804	#define X86_DR7_LEN1_MASK (3 << 22)
805	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
806	#define X86_DR7_RW2_MASK (3 << 24)
807	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
808	#define X86_DR7_LEN2_MASK (3 << 26)
809	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
810	#define X86_DR7_RW3_MASK (3 << 28)
811	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
812	#define X86_DR7_LEN3_MASK (3 << 30)
813
814	/** Bits which reads as 1s. */
815	#define X86_DR7_RA1_MASK (RT_BIT(10))
816	/** Bits which reads as zeros. */
817	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
818	/** Bits which must be 0s when writing to DR7. */
819	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
820
821	/** Calcs the L bit of Nth breakpoint.
822	* @param iBp The breakpoint number [0..3].
823	*/
824	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
825
826	/** Calcs the G bit of Nth breakpoint.
827	* @param iBp The breakpoint number [0..3].
828	*/
829	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
830
831	/** Calcs the L and G bits of Nth breakpoint.
832	* @param iBp The breakpoint number [0..3].
833	*/
834	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
835
836	/** @name Read/Write values.
837	* @{ */
838	/** Break on instruction fetch only. */
839	#define X86_DR7_RW_EO 0U
840	/** Break on write only. */
841	#define X86_DR7_RW_WO 1U
842	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
843	#define X86_DR7_RW_IO 2U
844	/** Break on read or write (but not instruction fetches). */
845	#define X86_DR7_RW_RW 3U
846	/** @} */
847
848	/** Shifts a X86_DR7_RW_* value to its right place.
849	* @param iBp The breakpoint number [0..3].
850	* @param fRw One of the X86_DR7_RW_* value.
851	*/
852	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
853
854	/** Fetch the the R/Wx bits for a given breakpoint (so it can be compared with
855	* one of the X86_DR7_RW_XXX constants).
856	*
857	* @returns X86_DR7_RW_XXX
858	* @param uDR7 DR7 value
859	* @param iBp The breakpoint number [0..3].
860	*/
861	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
862
863	/** R/W0, R/W1, R/W2, and R/W3. */
864	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
865
866	/** Checks if there are any I/O breakpoint types configured in the RW
867	* registers. Does NOT check if these are enabled, sorry. */
868	#define X86_DR7_ANY_RW_IO(uDR7) \
869	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
870	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
871	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
872	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
873	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
874	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
875	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
876	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
877	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
878	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
879	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
880
881	/** @name Length values.
882	* @{ */
883	#define X86_DR7_LEN_BYTE 0U
884	#define X86_DR7_LEN_WORD 1U
885	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
886	#define X86_DR7_LEN_DWORD 3U
887	/** @} */
888
889	/** Shifts a X86_DR7_LEN_* value to its right place.
890	* @param iBp The breakpoint number [0..3].
891	* @param cb One of the X86_DR7_LEN_* values.
892	*/
893	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
894
895	/** Fetch the breakpoint length bits from the DR7 value.
896	* @param uDR7 DR7 value
897	* @param iBp The breakpoint number [0..3].
898	*/
899	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
900
901	/** Mask used to check if any breakpoints are enabled. */
902	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
903
904	/** Value of DR7 after powerup/reset. */
905	#define X86_DR7_INIT_VAL 0x400
906	/** @} */
907
908
909	/** @name Machine Specific Registers
910	* @{
911	*/
912
913	/** Time Stamp Counter. */
914	#define MSR_IA32_TSC 0x10
915
916	#define MSR_IA32_PLATFORM_ID 0x17
917
918	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
919	#define MSR_IA32_APICBASE 0x1b
920	#endif
921
922	/** CPU Feature control. */
923	#define MSR_IA32_FEATURE_CONTROL 0x3A
924	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
925	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
926
927	/** BIOS update trigger (microcode update). */
928	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
929
930	/** BIOS update signature (microcode). */
931	#define MSR_IA32_BIOS_SIGN_ID 0x8B
932
933	/** General performance counter no. 0. */
934	#define MSR_IA32_PMC0 0xC1
935	/** General performance counter no. 1. */
936	#define MSR_IA32_PMC1 0xC2
937	/** General performance counter no. 2. */
938	#define MSR_IA32_PMC2 0xC3
939	/** General performance counter no. 3. */
940	#define MSR_IA32_PMC3 0xC4
941
942	/** Nehalem power control. */
943	#define MSR_IA32_PLATFORM_INFO 0xCE
944
945	/** Get FSB clock status (Intel-specific). */
946	#define MSR_IA32_FSB_CLOCK_STS 0xCD
947
948	/** MTRR Capabilities. */
949	#define MSR_IA32_MTRR_CAP 0xFE
950
951
952	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
953	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
954	* R0 SS == CS + 8
955	* R3 CS == CS + 16
956	* R3 SS == CS + 24
957	*/
958	#define MSR_IA32_SYSENTER_CS 0x174
959	/** SYSENTER_ESP - the R0 ESP. */
960	#define MSR_IA32_SYSENTER_ESP 0x175
961	/** SYSENTER_EIP - the R0 EIP. */
962	#define MSR_IA32_SYSENTER_EIP 0x176
963	#endif
964
965	/** Machine Check Global Capabilities Register. */
966	#define MSR_IA32_MCP_CAP 0x179
967	/** Machine Check Global Status Register. */
968	#define MSR_IA32_MCP_STATUS 0x17A
969	/** Machine Check Global Control Register. */
970	#define MSR_IA32_MCP_CTRL 0x17B
971
972	/** Trace/Profile Resource Control (R/W) */
973	#define MSR_IA32_DEBUGCTL 0x1D9
974
975	/** Page Attribute Table. */
976	#define MSR_IA32_CR_PAT 0x277
977
978	/** Performance counter MSRs. (Intel only) */
979	#define MSR_IA32_PERFEVTSEL0 0x186
980	#define MSR_IA32_PERFEVTSEL1 0x187
981	#define MSR_IA32_FLEX_RATIO 0x194
982	#define MSR_IA32_PERF_STATUS 0x198
983	#define MSR_IA32_PERF_CTL 0x199
984	#define MSR_IA32_THERM_STATUS 0x19c
985
986	/** Enable misc. processor features (R/W). */
987	#define MSR_IA32_MISC_ENABLE 0x1A0
988	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
989	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
990	/** Automatic Thermal Control Circuit Enable (R/W). */
991	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
992	/** Performance Monitoring Available (R). */
993	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
994	/** Branch Trace Storage Unavailable (R/O). */
995	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
996	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
997	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
998	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
999	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
1000	/** If MONITOR/MWAIT is supported (R/W). */
1001	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
1002	/** Limit CPUID Maxval to 3 leafs (R/W). */
1003	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
1004	/** When set to 1, xTPR messages are disabled (R/W). */
1005	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
1006	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1007	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
1008
1009	#define IA32_MTRR_PHYSBASE0 0x200
1010	#define IA32_MTRR_PHYSMASK0 0x201
1011	#define IA32_MTRR_PHYSBASE1 0x202
1012	#define IA32_MTRR_PHYSMASK1 0x203
1013	#define IA32_MTRR_PHYSBASE2 0x204
1014	#define IA32_MTRR_PHYSMASK2 0x205
1015	#define IA32_MTRR_PHYSBASE3 0x206
1016	#define IA32_MTRR_PHYSMASK3 0x207
1017	#define IA32_MTRR_PHYSBASE4 0x208
1018	#define IA32_MTRR_PHYSMASK4 0x209
1019	#define IA32_MTRR_PHYSBASE5 0x20a
1020	#define IA32_MTRR_PHYSMASK5 0x20b
1021	#define IA32_MTRR_PHYSBASE6 0x20c
1022	#define IA32_MTRR_PHYSMASK6 0x20d
1023	#define IA32_MTRR_PHYSBASE7 0x20e
1024	#define IA32_MTRR_PHYSMASK7 0x20f
1025	#define IA32_MTRR_PHYSBASE8 0x210
1026	#define IA32_MTRR_PHYSMASK8 0x211
1027	#define IA32_MTRR_PHYSBASE9 0x212
1028	#define IA32_MTRR_PHYSMASK9 0x213
1029
1030	/** Fixed range MTRRs.
1031	* @{ */
1032	#define IA32_MTRR_FIX64K_00000 0x250
1033	#define IA32_MTRR_FIX16K_80000 0x258
1034	#define IA32_MTRR_FIX16K_A0000 0x259
1035	#define IA32_MTRR_FIX4K_C0000 0x268
1036	#define IA32_MTRR_FIX4K_C8000 0x269
1037	#define IA32_MTRR_FIX4K_D0000 0x26a
1038	#define IA32_MTRR_FIX4K_D8000 0x26b
1039	#define IA32_MTRR_FIX4K_E0000 0x26c
1040	#define IA32_MTRR_FIX4K_E8000 0x26d
1041	#define IA32_MTRR_FIX4K_F0000 0x26e
1042	#define IA32_MTRR_FIX4K_F8000 0x26f
1043	/** @} */
1044
1045	/** MTRR Default Range. */
1046	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1047
1048	#define MSR_IA32_MC0_CTL 0x400
1049	#define MSR_IA32_MC0_STATUS 0x401
1050
1051	/** Basic VMX information. */
1052	#define MSR_IA32_VMX_BASIC_INFO 0x480
1053	/** Allowed settings for pin-based VM execution controls */
1054	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1055	/** Allowed settings for proc-based VM execution controls */
1056	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1057	/** Allowed settings for the VMX exit controls. */
1058	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1059	/** Allowed settings for the VMX entry controls. */
1060	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1061	/** Misc VMX info. */
1062	#define MSR_IA32_VMX_MISC 0x485
1063	/** Fixed cleared bits in CR0. */
1064	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1065	/** Fixed set bits in CR0. */
1066	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1067	/** Fixed cleared bits in CR4. */
1068	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1069	/** Fixed set bits in CR4. */
1070	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1071	/** Information for enumerating fields in the VMCS. */
1072	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1073	/** Allowed settings for the VM-functions controls. */
1074	#define MSR_IA32_VMX_VMFUNC 0x491
1075	/** Allowed settings for secondary proc-based VM execution controls */
1076	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1077	/** EPT capabilities. */
1078	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1079	/** DS Save Area (R/W). */
1080	#define MSR_IA32_DS_AREA 0x600
1081	/** X2APIC MSR ranges. */
1082	#define MSR_IA32_X2APIC_START 0x800
1083	#define MSR_IA32_X2APIC_TPR 0x808
1084	#define MSR_IA32_X2APIC_END 0xBFF
1085
1086	/** K6 EFER - Extended Feature Enable Register. */
1087	#define MSR_K6_EFER 0xc0000080
1088	/** @todo document EFER */
1089	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1090	#define MSR_K6_EFER_SCE RT_BIT(0)
1091	/** Bit 8 - LME - Long mode enabled. (R/W) */
1092	#define MSR_K6_EFER_LME RT_BIT(8)
1093	/** Bit 10 - LMA - Long mode active. (R) */
1094	#define MSR_K6_EFER_LMA RT_BIT(10)
1095	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1096	#define MSR_K6_EFER_NXE RT_BIT(11)
1097	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1098	#define MSR_K6_EFER_SVME RT_BIT(12)
1099	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1100	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1101	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1102	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1103	/** K6 STAR - SYSCALL/RET targets. */
1104	#define MSR_K6_STAR 0xc0000081
1105	/** Shift value for getting the SYSRET CS and SS value. */
1106	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1107	/** Shift value for getting the SYSCALL CS and SS value. */
1108	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1109	/** Selector mask for use after shifting. */
1110	#define MSR_K6_STAR_SEL_MASK 0xffff
1111	/** The mask which give the SYSCALL EIP. */
1112	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1113	/** K6 WHCR - Write Handling Control Register. */
1114	#define MSR_K6_WHCR 0xc0000082
1115	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1116	#define MSR_K6_UWCCR 0xc0000085
1117	/** K6 PSOR - Processor State Observability Register. */
1118	#define MSR_K6_PSOR 0xc0000087
1119	/** K6 PFIR - Page Flush/Invalidate Register. */
1120	#define MSR_K6_PFIR 0xc0000088
1121
1122	/** Performance counter MSRs. (AMD only) */
1123	#define MSR_K7_EVNTSEL0 0xc0010000
1124	#define MSR_K7_EVNTSEL1 0xc0010001
1125	#define MSR_K7_EVNTSEL2 0xc0010002
1126	#define MSR_K7_EVNTSEL3 0xc0010003
1127	#define MSR_K7_PERFCTR0 0xc0010004
1128	#define MSR_K7_PERFCTR1 0xc0010005
1129	#define MSR_K7_PERFCTR2 0xc0010006
1130	#define MSR_K7_PERFCTR3 0xc0010007
1131
1132	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1133	#define MSR_K8_LSTAR 0xc0000082
1134	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1135	#define MSR_K8_CSTAR 0xc0000083
1136	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1137	#define MSR_K8_SF_MASK 0xc0000084
1138	/** K8 FS.base - The 64-bit base FS register. */
1139	#define MSR_K8_FS_BASE 0xc0000100
1140	/** K8 GS.base - The 64-bit base GS register. */
1141	#define MSR_K8_GS_BASE 0xc0000101
1142	/** K8 KernelGSbase - Used with SWAPGS. */
1143	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1144	/** K8 TSC_AUX - Used with RDTSCP. */
1145	#define MSR_K8_TSC_AUX 0xc0000103
1146	#define MSR_K8_SYSCFG 0xc0010010
1147	#define MSR_K8_HWCR 0xc0010015
1148	#define MSR_K8_IORRBASE0 0xc0010016
1149	#define MSR_K8_IORRMASK0 0xc0010017
1150	#define MSR_K8_IORRBASE1 0xc0010018
1151	#define MSR_K8_IORRMASK1 0xc0010019
1152	#define MSR_K8_TOP_MEM1 0xc001001a
1153	#define MSR_K8_TOP_MEM2 0xc001001d
1154	#define MSR_K8_VM_CR 0xc0010114
1155	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1156
1157	#define MSR_K8_IGNNE 0xc0010115
1158	#define MSR_K8_SMM_CTL 0xc0010116
1159	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1160	* host state during world switch.
1161	*/
1162	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1163
1164	/** @} */
1165
1166
1167	/** @name Page Table / Directory / Directory Pointers / L4.
1168	* @{
1169	*/
1170
1171	/** Page table/directory entry as an unsigned integer. */
1172	typedef uint32_t X86PGUINT;
1173	/** Pointer to a page table/directory table entry as an unsigned integer. */
1174	typedef X86PGUINT *PX86PGUINT;
1175	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1176	typedef X86PGUINT const *PCX86PGUINT;
1177
1178	/** Number of entries in a 32-bit PT/PD. */
1179	#define X86_PG_ENTRIES 1024
1180
1181
1182	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1183	typedef uint64_t X86PGPAEUINT;
1184	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1185	typedef X86PGPAEUINT *PX86PGPAEUINT;
1186	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1187	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1188
1189	/** Number of entries in a PAE PT/PD. */
1190	#define X86_PG_PAE_ENTRIES 512
1191	/** Number of entries in a PAE PDPT. */
1192	#define X86_PG_PAE_PDPE_ENTRIES 4
1193
1194	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1195	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1196	/** Number of entries in an AMD64 PDPT.
1197	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1198	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1199
1200	/** The size of a 4KB page. */
1201	#define X86_PAGE_4K_SIZE _4K
1202	/** The page shift of a 4KB page. */
1203	#define X86_PAGE_4K_SHIFT 12
1204	/** The 4KB page offset mask. */
1205	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1206	/** The 4KB page base mask for virtual addresses. */
1207	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1208	/** The 4KB page base mask for virtual addresses - 32bit version. */
1209	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1210
1211	/** The size of a 2MB page. */
1212	#define X86_PAGE_2M_SIZE _2M
1213	/** The page shift of a 2MB page. */
1214	#define X86_PAGE_2M_SHIFT 21
1215	/** The 2MB page offset mask. */
1216	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1217	/** The 2MB page base mask for virtual addresses. */
1218	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1219	/** The 2MB page base mask for virtual addresses - 32bit version. */
1220	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1221
1222	/** The size of a 4MB page. */
1223	#define X86_PAGE_4M_SIZE _4M
1224	/** The page shift of a 4MB page. */
1225	#define X86_PAGE_4M_SHIFT 22
1226	/** The 4MB page offset mask. */
1227	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1228	/** The 4MB page base mask for virtual addresses. */
1229	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1230	/** The 4MB page base mask for virtual addresses - 32bit version. */
1231	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1232
1233
1234
1235	/** @name Page Table Entry
1236	* @{
1237	*/
1238	/** Bit 0 - P - Present bit. */
1239	#define X86_PTE_BIT_P 0
1240	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1241	#define X86_PTE_BIT_RW 1
1242	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1243	#define X86_PTE_BIT_US 2
1244	/** Bit 3 - PWT - Page level write thru bit. */
1245	#define X86_PTE_BIT_PWT 3
1246	/** Bit 4 - PCD - Page level cache disable bit. */
1247	#define X86_PTE_BIT_PCD 4
1248	/** Bit 5 - A - Access bit. */
1249	#define X86_PTE_BIT_A 5
1250	/** Bit 6 - D - Dirty bit. */
1251	#define X86_PTE_BIT_D 6
1252	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1253	#define X86_PTE_BIT_PAT 7
1254	/** Bit 8 - G - Global flag. */
1255	#define X86_PTE_BIT_G 8
1256
1257	/** Bit 0 - P - Present bit mask. */
1258	#define X86_PTE_P RT_BIT(0)
1259	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1260	#define X86_PTE_RW RT_BIT(1)
1261	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1262	#define X86_PTE_US RT_BIT(2)
1263	/** Bit 3 - PWT - Page level write thru bit mask. */
1264	#define X86_PTE_PWT RT_BIT(3)
1265	/** Bit 4 - PCD - Page level cache disable bit mask. */
1266	#define X86_PTE_PCD RT_BIT(4)
1267	/** Bit 5 - A - Access bit mask. */
1268	#define X86_PTE_A RT_BIT(5)
1269	/** Bit 6 - D - Dirty bit mask. */
1270	#define X86_PTE_D RT_BIT(6)
1271	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1272	#define X86_PTE_PAT RT_BIT(7)
1273	/** Bit 8 - G - Global bit mask. */
1274	#define X86_PTE_G RT_BIT(8)
1275
1276	/** Bits 9-11 - - Available for use to system software. */
1277	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1278	/** Bits 12-31 - - Physical Page number of the next level. */
1279	#define X86_PTE_PG_MASK ( 0xfffff000 )
1280
1281	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1282	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1283	/** Bits 63 - NX - PAE/LM - No execution flag. */
1284	#define X86_PTE_PAE_NX RT_BIT_64(63)
1285	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1286	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1287	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1288	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1289	/** No bits - - LM - MBZ bits when NX is active. */
1290	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1291	/** Bits 63 - - LM - MBZ bits when no NX. */
1292	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1293
1294	/**
1295	* Page table entry.
1296	*/
1297	typedef struct X86PTEBITS
1298	{
1299	/** Flags whether(=1) or not the page is present. */
1300	unsigned u1Present : 1;
1301	/** Read(=0) / Write(=1) flag. */
1302	unsigned u1Write : 1;
1303	/** User(=1) / Supervisor (=0) flag. */
1304	unsigned u1User : 1;
1305	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1306	unsigned u1WriteThru : 1;
1307	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1308	unsigned u1CacheDisable : 1;
1309	/** Accessed flag.
1310	* Indicates that the page have been read or written to. */
1311	unsigned u1Accessed : 1;
1312	/** Dirty flag.
1313	* Indicates that the page has been written to. */
1314	unsigned u1Dirty : 1;
1315	/** Reserved / If PAT enabled, bit 2 of the index. */
1316	unsigned u1PAT : 1;
1317	/** Global flag. (Ignored in all but final level.) */
1318	unsigned u1Global : 1;
1319	/** Available for use to system software. */
1320	unsigned u3Available : 3;
1321	/** Physical Page number of the next level. */
1322	unsigned u20PageNo : 20;
1323	} X86PTEBITS;
1324	/** Pointer to a page table entry. */
1325	typedef X86PTEBITS *PX86PTEBITS;
1326	/** Pointer to a const page table entry. */
1327	typedef const X86PTEBITS *PCX86PTEBITS;
1328
1329	/**
1330	* Page table entry.
1331	*/
1332	typedef union X86PTE
1333	{
1334	/** Unsigned integer view */
1335	X86PGUINT u;
1336	/** Bit field view. */
1337	X86PTEBITS n;
1338	/** 32-bit view. */
1339	uint32_t au32[1];
1340	/** 16-bit view. */
1341	uint16_t au16[2];
1342	/** 8-bit view. */
1343	uint8_t au8[4];
1344	} X86PTE;
1345	/** Pointer to a page table entry. */
1346	typedef X86PTE *PX86PTE;
1347	/** Pointer to a const page table entry. */
1348	typedef const X86PTE *PCX86PTE;
1349
1350
1351	/**
1352	* PAE page table entry.
1353	*/
1354	typedef struct X86PTEPAEBITS
1355	{
1356	/** Flags whether(=1) or not the page is present. */
1357	uint32_t u1Present : 1;
1358	/** Read(=0) / Write(=1) flag. */
1359	uint32_t u1Write : 1;
1360	/** User(=1) / Supervisor(=0) flag. */
1361	uint32_t u1User : 1;
1362	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1363	uint32_t u1WriteThru : 1;
1364	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1365	uint32_t u1CacheDisable : 1;
1366	/** Accessed flag.
1367	* Indicates that the page have been read or written to. */
1368	uint32_t u1Accessed : 1;
1369	/** Dirty flag.
1370	* Indicates that the page has been written to. */
1371	uint32_t u1Dirty : 1;
1372	/** Reserved / If PAT enabled, bit 2 of the index. */
1373	uint32_t u1PAT : 1;
1374	/** Global flag. (Ignored in all but final level.) */
1375	uint32_t u1Global : 1;
1376	/** Available for use to system software. */
1377	uint32_t u3Available : 3;
1378	/** Physical Page number of the next level - Low Part. Don't use this. */
1379	uint32_t u20PageNoLow : 20;
1380	/** Physical Page number of the next level - High Part. Don't use this. */
1381	uint32_t u20PageNoHigh : 20;
1382	/** MBZ bits */
1383	uint32_t u11Reserved : 11;
1384	/** No Execute flag. */
1385	uint32_t u1NoExecute : 1;
1386	} X86PTEPAEBITS;
1387	/** Pointer to a page table entry. */
1388	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1389	/** Pointer to a page table entry. */
1390	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1391
1392	/**
1393	* PAE Page table entry.
1394	*/
1395	typedef union X86PTEPAE
1396	{
1397	/** Unsigned integer view */
1398	X86PGPAEUINT u;
1399	/** Bit field view. */
1400	X86PTEPAEBITS n;
1401	/** 32-bit view. */
1402	uint32_t au32[2];
1403	/** 16-bit view. */
1404	uint16_t au16[4];
1405	/** 8-bit view. */
1406	uint8_t au8[8];
1407	} X86PTEPAE;
1408	/** Pointer to a PAE page table entry. */
1409	typedef X86PTEPAE *PX86PTEPAE;
1410	/** Pointer to a const PAE page table entry. */
1411	typedef const X86PTEPAE *PCX86PTEPAE;
1412	/** @} */
1413
1414	/**
1415	* Page table.
1416	*/
1417	typedef struct X86PT
1418	{
1419	/** PTE Array. */
1420	X86PTE a[X86_PG_ENTRIES];
1421	} X86PT;
1422	/** Pointer to a page table. */
1423	typedef X86PT *PX86PT;
1424	/** Pointer to a const page table. */
1425	typedef const X86PT *PCX86PT;
1426
1427	/** The page shift to get the PT index. */
1428	#define X86_PT_SHIFT 12
1429	/** The PT index mask (apply to a shifted page address). */
1430	#define X86_PT_MASK 0x3ff
1431
1432
1433	/**
1434	* Page directory.
1435	*/
1436	typedef struct X86PTPAE
1437	{
1438	/** PTE Array. */
1439	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1440	} X86PTPAE;
1441	/** Pointer to a page table. */
1442	typedef X86PTPAE *PX86PTPAE;
1443	/** Pointer to a const page table. */
1444	typedef const X86PTPAE *PCX86PTPAE;
1445
1446	/** The page shift to get the PA PTE index. */
1447	#define X86_PT_PAE_SHIFT 12
1448	/** The PAE PT index mask (apply to a shifted page address). */
1449	#define X86_PT_PAE_MASK 0x1ff
1450
1451
1452	/** @name 4KB Page Directory Entry
1453	* @{
1454	*/
1455	/** Bit 0 - P - Present bit. */
1456	#define X86_PDE_P RT_BIT(0)
1457	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1458	#define X86_PDE_RW RT_BIT(1)
1459	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1460	#define X86_PDE_US RT_BIT(2)
1461	/** Bit 3 - PWT - Page level write thru bit. */
1462	#define X86_PDE_PWT RT_BIT(3)
1463	/** Bit 4 - PCD - Page level cache disable bit. */
1464	#define X86_PDE_PCD RT_BIT(4)
1465	/** Bit 5 - A - Access bit. */
1466	#define X86_PDE_A RT_BIT(5)
1467	/** Bit 7 - PS - Page size attribute.
1468	* Clear mean 4KB pages, set means large pages (2/4MB). */
1469	#define X86_PDE_PS RT_BIT(7)
1470	/** Bits 9-11 - - Available for use to system software. */
1471	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1472	/** Bits 12-31 - - Physical Page number of the next level. */
1473	#define X86_PDE_PG_MASK ( 0xfffff000 )
1474
1475	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1476	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1477	/** Bits 63 - NX - PAE/LM - No execution flag. */
1478	#define X86_PDE_PAE_NX RT_BIT_64(63)
1479	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1480	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1481	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1482	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1483	/** Bit 7 - - LM - MBZ bits when NX is active. */
1484	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1485	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1486	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1487
1488	/**
1489	* Page directory entry.
1490	*/
1491	typedef struct X86PDEBITS
1492	{
1493	/** Flags whether(=1) or not the page is present. */
1494	unsigned u1Present : 1;
1495	/** Read(=0) / Write(=1) flag. */
1496	unsigned u1Write : 1;
1497	/** User(=1) / Supervisor (=0) flag. */
1498	unsigned u1User : 1;
1499	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1500	unsigned u1WriteThru : 1;
1501	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1502	unsigned u1CacheDisable : 1;
1503	/** Accessed flag.
1504	* Indicates that the page has been read or written to. */
1505	unsigned u1Accessed : 1;
1506	/** Reserved / Ignored (dirty bit). */
1507	unsigned u1Reserved0 : 1;
1508	/** Size bit if PSE is enabled - in any event it's 0. */
1509	unsigned u1Size : 1;
1510	/** Reserved / Ignored (global bit). */
1511	unsigned u1Reserved1 : 1;
1512	/** Available for use to system software. */
1513	unsigned u3Available : 3;
1514	/** Physical Page number of the next level. */
1515	unsigned u20PageNo : 20;
1516	} X86PDEBITS;
1517	/** Pointer to a page directory entry. */
1518	typedef X86PDEBITS *PX86PDEBITS;
1519	/** Pointer to a const page directory entry. */
1520	typedef const X86PDEBITS *PCX86PDEBITS;
1521
1522
1523	/**
1524	* PAE page directory entry.
1525	*/
1526	typedef struct X86PDEPAEBITS
1527	{
1528	/** Flags whether(=1) or not the page is present. */
1529	uint32_t u1Present : 1;
1530	/** Read(=0) / Write(=1) flag. */
1531	uint32_t u1Write : 1;
1532	/** User(=1) / Supervisor (=0) flag. */
1533	uint32_t u1User : 1;
1534	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1535	uint32_t u1WriteThru : 1;
1536	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1537	uint32_t u1CacheDisable : 1;
1538	/** Accessed flag.
1539	* Indicates that the page has been read or written to. */
1540	uint32_t u1Accessed : 1;
1541	/** Reserved / Ignored (dirty bit). */
1542	uint32_t u1Reserved0 : 1;
1543	/** Size bit if PSE is enabled - in any event it's 0. */
1544	uint32_t u1Size : 1;
1545	/** Reserved / Ignored (global bit). / */
1546	uint32_t u1Reserved1 : 1;
1547	/** Available for use to system software. */
1548	uint32_t u3Available : 3;
1549	/** Physical Page number of the next level - Low Part. Don't use! */
1550	uint32_t u20PageNoLow : 20;
1551	/** Physical Page number of the next level - High Part. Don't use! */
1552	uint32_t u20PageNoHigh : 20;
1553	/** MBZ bits */
1554	uint32_t u11Reserved : 11;
1555	/** No Execute flag. */
1556	uint32_t u1NoExecute : 1;
1557	} X86PDEPAEBITS;
1558	/** Pointer to a page directory entry. */
1559	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1560	/** Pointer to a const page directory entry. */
1561	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1562
1563	/** @} */
1564
1565
1566	/** @name 2/4MB Page Directory Entry
1567	* @{
1568	*/
1569	/** Bit 0 - P - Present bit. */
1570	#define X86_PDE4M_P RT_BIT(0)
1571	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1572	#define X86_PDE4M_RW RT_BIT(1)
1573	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1574	#define X86_PDE4M_US RT_BIT(2)
1575	/** Bit 3 - PWT - Page level write thru bit. */
1576	#define X86_PDE4M_PWT RT_BIT(3)
1577	/** Bit 4 - PCD - Page level cache disable bit. */
1578	#define X86_PDE4M_PCD RT_BIT(4)
1579	/** Bit 5 - A - Access bit. */
1580	#define X86_PDE4M_A RT_BIT(5)
1581	/** Bit 6 - D - Dirty bit. */
1582	#define X86_PDE4M_D RT_BIT(6)
1583	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1584	#define X86_PDE4M_PS RT_BIT(7)
1585	/** Bit 8 - G - Global flag. */
1586	#define X86_PDE4M_G RT_BIT(8)
1587	/** Bits 9-11 - AVL - Available for use to system software. */
1588	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1589	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1590	#define X86_PDE4M_PAT RT_BIT(12)
1591	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1592	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1593	/** Bits 22-31 - - Physical Page number. */
1594	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1595	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1596	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1597	/** The number of bits to the high part of the page number. */
1598	#define X86_PDE4M_PG_HIGH_SHIFT 19
1599	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1600	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1601
1602	/** Bits 21-51 - - PAE/LM - Physical Page number.
1603	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1604	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1605	/** Bits 63 - NX - PAE/LM - No execution flag. */
1606	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1607	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1608	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1609	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1610	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1611	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1612	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1613	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1614	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1615
1616	/**
1617	* 4MB page directory entry.
1618	*/
1619	typedef struct X86PDE4MBITS
1620	{
1621	/** Flags whether(=1) or not the page is present. */
1622	unsigned u1Present : 1;
1623	/** Read(=0) / Write(=1) flag. */
1624	unsigned u1Write : 1;
1625	/** User(=1) / Supervisor (=0) flag. */
1626	unsigned u1User : 1;
1627	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1628	unsigned u1WriteThru : 1;
1629	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1630	unsigned u1CacheDisable : 1;
1631	/** Accessed flag.
1632	* Indicates that the page have been read or written to. */
1633	unsigned u1Accessed : 1;
1634	/** Dirty flag.
1635	* Indicates that the page has been written to. */
1636	unsigned u1Dirty : 1;
1637	/** Page size flag - always 1 for 4MB entries. */
1638	unsigned u1Size : 1;
1639	/** Global flag. */
1640	unsigned u1Global : 1;
1641	/** Available for use to system software. */
1642	unsigned u3Available : 3;
1643	/** Reserved / If PAT enabled, bit 2 of the index. */
1644	unsigned u1PAT : 1;
1645	/** Bits 32-39 of the page number on AMD64.
1646	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1647	unsigned u8PageNoHigh : 8;
1648	/** Reserved. */
1649	unsigned u1Reserved : 1;
1650	/** Physical Page number of the page. */
1651	unsigned u10PageNo : 10;
1652	} X86PDE4MBITS;
1653	/** Pointer to a page table entry. */
1654	typedef X86PDE4MBITS *PX86PDE4MBITS;
1655	/** Pointer to a const page table entry. */
1656	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1657
1658
1659	/**
1660	* 2MB PAE page directory entry.
1661	*/
1662	typedef struct X86PDE2MPAEBITS
1663	{
1664	/** Flags whether(=1) or not the page is present. */
1665	uint32_t u1Present : 1;
1666	/** Read(=0) / Write(=1) flag. */
1667	uint32_t u1Write : 1;
1668	/** User(=1) / Supervisor(=0) flag. */
1669	uint32_t u1User : 1;
1670	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1671	uint32_t u1WriteThru : 1;
1672	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1673	uint32_t u1CacheDisable : 1;
1674	/** Accessed flag.
1675	* Indicates that the page have been read or written to. */
1676	uint32_t u1Accessed : 1;
1677	/** Dirty flag.
1678	* Indicates that the page has been written to. */
1679	uint32_t u1Dirty : 1;
1680	/** Page size flag - always 1 for 2MB entries. */
1681	uint32_t u1Size : 1;
1682	/** Global flag. */
1683	uint32_t u1Global : 1;
1684	/** Available for use to system software. */
1685	uint32_t u3Available : 3;
1686	/** Reserved / If PAT enabled, bit 2 of the index. */
1687	uint32_t u1PAT : 1;
1688	/** Reserved. */
1689	uint32_t u9Reserved : 9;
1690	/** Physical Page number of the next level - Low part. Don't use! */
1691	uint32_t u10PageNoLow : 10;
1692	/** Physical Page number of the next level - High part. Don't use! */
1693	uint32_t u20PageNoHigh : 20;
1694	/** MBZ bits */
1695	uint32_t u11Reserved : 11;
1696	/** No Execute flag. */
1697	uint32_t u1NoExecute : 1;
1698	} X86PDE2MPAEBITS;
1699	/** Pointer to a 2MB PAE page table entry. */
1700	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1701	/** Pointer to a 2MB PAE page table entry. */
1702	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1703
1704	/** @} */
1705
1706	/**
1707	* Page directory entry.
1708	*/
1709	typedef union X86PDE
1710	{
1711	/** Unsigned integer view. */
1712	X86PGUINT u;
1713	/** Normal view. */
1714	X86PDEBITS n;
1715	/** 4MB view (big). */
1716	X86PDE4MBITS b;
1717	/** 8 bit unsigned integer view. */
1718	uint8_t au8[4];
1719	/** 16 bit unsigned integer view. */
1720	uint16_t au16[2];
1721	/** 32 bit unsigned integer view. */
1722	uint32_t au32[1];
1723	} X86PDE;
1724	/** Pointer to a page directory entry. */
1725	typedef X86PDE *PX86PDE;
1726	/** Pointer to a const page directory entry. */
1727	typedef const X86PDE *PCX86PDE;
1728
1729	/**
1730	* PAE page directory entry.
1731	*/
1732	typedef union X86PDEPAE
1733	{
1734	/** Unsigned integer view. */
1735	X86PGPAEUINT u;
1736	/** Normal view. */
1737	X86PDEPAEBITS n;
1738	/** 2MB page view (big). */
1739	X86PDE2MPAEBITS b;
1740	/** 8 bit unsigned integer view. */
1741	uint8_t au8[8];
1742	/** 16 bit unsigned integer view. */
1743	uint16_t au16[4];
1744	/** 32 bit unsigned integer view. */
1745	uint32_t au32[2];
1746	} X86PDEPAE;
1747	/** Pointer to a page directory entry. */
1748	typedef X86PDEPAE *PX86PDEPAE;
1749	/** Pointer to a const page directory entry. */
1750	typedef const X86PDEPAE *PCX86PDEPAE;
1751
1752	/**
1753	* Page directory.
1754	*/
1755	typedef struct X86PD
1756	{
1757	/** PDE Array. */
1758	X86PDE a[X86_PG_ENTRIES];
1759	} X86PD;
1760	/** Pointer to a page directory. */
1761	typedef X86PD *PX86PD;
1762	/** Pointer to a const page directory. */
1763	typedef const X86PD *PCX86PD;
1764
1765	/** The page shift to get the PD index. */
1766	#define X86_PD_SHIFT 22
1767	/** The PD index mask (apply to a shifted page address). */
1768	#define X86_PD_MASK 0x3ff
1769
1770
1771	/**
1772	* PAE page directory.
1773	*/
1774	typedef struct X86PDPAE
1775	{
1776	/** PDE Array. */
1777	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1778	} X86PDPAE;
1779	/** Pointer to a PAE page directory. */
1780	typedef X86PDPAE *PX86PDPAE;
1781	/** Pointer to a const PAE page directory. */
1782	typedef const X86PDPAE *PCX86PDPAE;
1783
1784	/** The page shift to get the PAE PD index. */
1785	#define X86_PD_PAE_SHIFT 21
1786	/** The PAE PD index mask (apply to a shifted page address). */
1787	#define X86_PD_PAE_MASK 0x1ff
1788
1789
1790	/** @name Page Directory Pointer Table Entry (PAE)
1791	* @{
1792	*/
1793	/** Bit 0 - P - Present bit. */
1794	#define X86_PDPE_P RT_BIT(0)
1795	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1796	#define X86_PDPE_RW RT_BIT(1)
1797	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1798	#define X86_PDPE_US RT_BIT(2)
1799	/** Bit 3 - PWT - Page level write thru bit. */
1800	#define X86_PDPE_PWT RT_BIT(3)
1801	/** Bit 4 - PCD - Page level cache disable bit. */
1802	#define X86_PDPE_PCD RT_BIT(4)
1803	/** Bit 5 - A - Access bit. Long Mode only. */
1804	#define X86_PDPE_A RT_BIT(5)
1805	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1806	#define X86_PDPE_LM_PS RT_BIT(7)
1807	/** Bits 9-11 - - Available for use to system software. */
1808	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1809	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1810	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1811	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1812	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1813	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1814	#define X86_PDPE_LM_NX RT_BIT_64(63)
1815	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1816	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1817	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1818	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1819	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1820	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1821	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1822	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1823
1824
1825	/**
1826	* Page directory pointer table entry.
1827	*/
1828	typedef struct X86PDPEBITS
1829	{
1830	/** Flags whether(=1) or not the page is present. */
1831	uint32_t u1Present : 1;
1832	/** Chunk of reserved bits. */
1833	uint32_t u2Reserved : 2;
1834	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1835	uint32_t u1WriteThru : 1;
1836	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1837	uint32_t u1CacheDisable : 1;
1838	/** Chunk of reserved bits. */
1839	uint32_t u4Reserved : 4;
1840	/** Available for use to system software. */
1841	uint32_t u3Available : 3;
1842	/** Physical Page number of the next level - Low Part. Don't use! */
1843	uint32_t u20PageNoLow : 20;
1844	/** Physical Page number of the next level - High Part. Don't use! */
1845	uint32_t u20PageNoHigh : 20;
1846	/** MBZ bits */
1847	uint32_t u12Reserved : 12;
1848	} X86PDPEBITS;
1849	/** Pointer to a page directory pointer table entry. */
1850	typedef X86PDPEBITS *PX86PTPEBITS;
1851	/** Pointer to a const page directory pointer table entry. */
1852	typedef const X86PDPEBITS *PCX86PTPEBITS;
1853
1854	/**
1855	* Page directory pointer table entry. AMD64 version
1856	*/
1857	typedef struct X86PDPEAMD64BITS
1858	{
1859	/** Flags whether(=1) or not the page is present. */
1860	uint32_t u1Present : 1;
1861	/** Read(=0) / Write(=1) flag. */
1862	uint32_t u1Write : 1;
1863	/** User(=1) / Supervisor (=0) flag. */
1864	uint32_t u1User : 1;
1865	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1866	uint32_t u1WriteThru : 1;
1867	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1868	uint32_t u1CacheDisable : 1;
1869	/** Accessed flag.
1870	* Indicates that the page have been read or written to. */
1871	uint32_t u1Accessed : 1;
1872	/** Chunk of reserved bits. */
1873	uint32_t u3Reserved : 3;
1874	/** Available for use to system software. */
1875	uint32_t u3Available : 3;
1876	/** Physical Page number of the next level - Low Part. Don't use! */
1877	uint32_t u20PageNoLow : 20;
1878	/** Physical Page number of the next level - High Part. Don't use! */
1879	uint32_t u20PageNoHigh : 20;
1880	/** MBZ bits */
1881	uint32_t u11Reserved : 11;
1882	/** No Execute flag. */
1883	uint32_t u1NoExecute : 1;
1884	} X86PDPEAMD64BITS;
1885	/** Pointer to a page directory pointer table entry. */
1886	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1887	/** Pointer to a const page directory pointer table entry. */
1888	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1889
1890	/**
1891	* Page directory pointer table entry.
1892	*/
1893	typedef union X86PDPE
1894	{
1895	/** Unsigned integer view. */
1896	X86PGPAEUINT u;
1897	/** Normal view. */
1898	X86PDPEBITS n;
1899	/** AMD64 view. */
1900	X86PDPEAMD64BITS lm;
1901	/** 8 bit unsigned integer view. */
1902	uint8_t au8[8];
1903	/** 16 bit unsigned integer view. */
1904	uint16_t au16[4];
1905	/** 32 bit unsigned integer view. */
1906	uint32_t au32[2];
1907	} X86PDPE;
1908	/** Pointer to a page directory pointer table entry. */
1909	typedef X86PDPE *PX86PDPE;
1910	/** Pointer to a const page directory pointer table entry. */
1911	typedef const X86PDPE *PCX86PDPE;
1912
1913
1914	/**
1915	* Page directory pointer table.
1916	*/
1917	typedef struct X86PDPT
1918	{
1919	/** PDE Array. */
1920	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1921	} X86PDPT;
1922	/** Pointer to a page directory pointer table. */
1923	typedef X86PDPT *PX86PDPT;
1924	/** Pointer to a const page directory pointer table. */
1925	typedef const X86PDPT *PCX86PDPT;
1926
1927	/** The page shift to get the PDPT index. */
1928	#define X86_PDPT_SHIFT 30
1929	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1930	#define X86_PDPT_MASK_PAE 0x3
1931	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1932	#define X86_PDPT_MASK_AMD64 0x1ff
1933
1934	/** @} */
1935
1936
1937	/** @name Page Map Level-4 Entry (Long Mode PAE)
1938	* @{
1939	*/
1940	/** Bit 0 - P - Present bit. */
1941	#define X86_PML4E_P RT_BIT(0)
1942	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1943	#define X86_PML4E_RW RT_BIT(1)
1944	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1945	#define X86_PML4E_US RT_BIT(2)
1946	/** Bit 3 - PWT - Page level write thru bit. */
1947	#define X86_PML4E_PWT RT_BIT(3)
1948	/** Bit 4 - PCD - Page level cache disable bit. */
1949	#define X86_PML4E_PCD RT_BIT(4)
1950	/** Bit 5 - A - Access bit. */
1951	#define X86_PML4E_A RT_BIT(5)
1952	/** Bits 9-11 - - Available for use to system software. */
1953	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1954	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1955	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1956	/** Bits 8, 7 - - MBZ bits when NX is active. */
1957	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1958	/** Bits 63, 7 - - MBZ bits when no NX. */
1959	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1960	/** Bits 63 - NX - PAE - No execution flag. */
1961	#define X86_PML4E_NX RT_BIT_64(63)
1962
1963	/**
1964	* Page Map Level-4 Entry
1965	*/
1966	typedef struct X86PML4EBITS
1967	{
1968	/** Flags whether(=1) or not the page is present. */
1969	uint32_t u1Present : 1;
1970	/** Read(=0) / Write(=1) flag. */
1971	uint32_t u1Write : 1;
1972	/** User(=1) / Supervisor (=0) flag. */
1973	uint32_t u1User : 1;
1974	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1975	uint32_t u1WriteThru : 1;
1976	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1977	uint32_t u1CacheDisable : 1;
1978	/** Accessed flag.
1979	* Indicates that the page have been read or written to. */
1980	uint32_t u1Accessed : 1;
1981	/** Chunk of reserved bits. */
1982	uint32_t u3Reserved : 3;
1983	/** Available for use to system software. */
1984	uint32_t u3Available : 3;
1985	/** Physical Page number of the next level - Low Part. Don't use! */
1986	uint32_t u20PageNoLow : 20;
1987	/** Physical Page number of the next level - High Part. Don't use! */
1988	uint32_t u20PageNoHigh : 20;
1989	/** MBZ bits */
1990	uint32_t u11Reserved : 11;
1991	/** No Execute flag. */
1992	uint32_t u1NoExecute : 1;
1993	} X86PML4EBITS;
1994	/** Pointer to a page map level-4 entry. */
1995	typedef X86PML4EBITS *PX86PML4EBITS;
1996	/** Pointer to a const page map level-4 entry. */
1997	typedef const X86PML4EBITS *PCX86PML4EBITS;
1998
1999	/**
2000	* Page Map Level-4 Entry.
2001	*/
2002	typedef union X86PML4E
2003	{
2004	/** Unsigned integer view. */
2005	X86PGPAEUINT u;
2006	/** Normal view. */
2007	X86PML4EBITS n;
2008	/** 8 bit unsigned integer view. */
2009	uint8_t au8[8];
2010	/** 16 bit unsigned integer view. */
2011	uint16_t au16[4];
2012	/** 32 bit unsigned integer view. */
2013	uint32_t au32[2];
2014	} X86PML4E;
2015	/** Pointer to a page map level-4 entry. */
2016	typedef X86PML4E *PX86PML4E;
2017	/** Pointer to a const page map level-4 entry. */
2018	typedef const X86PML4E *PCX86PML4E;
2019
2020
2021	/**
2022	* Page Map Level-4.
2023	*/
2024	typedef struct X86PML4
2025	{
2026	/** PDE Array. */
2027	X86PML4E a[X86_PG_PAE_ENTRIES];
2028	} X86PML4;
2029	/** Pointer to a page map level-4. */
2030	typedef X86PML4 *PX86PML4;
2031	/** Pointer to a const page map level-4. */
2032	typedef const X86PML4 *PCX86PML4;
2033
2034	/** The page shift to get the PML4 index. */
2035	#define X86_PML4_SHIFT 39
2036	/** The PML4 index mask (apply to a shifted page address). */
2037	#define X86_PML4_MASK 0x1ff
2038
2039	/** @} */
2040
2041	/** @} */
2042
2043
2044	/**
2045	* 80-bit MMX/FPU register type.
2046	*/
2047	typedef struct X86FPUMMX
2048	{
2049	uint8_t reg[10];
2050	} X86FPUMMX;
2051	/** Pointer to a 80-bit MMX/FPU register type. */
2052	typedef X86FPUMMX *PX86FPUMMX;
2053	/** Pointer to a const 80-bit MMX/FPU register type. */
2054	typedef const X86FPUMMX *PCX86FPUMMX;
2055
2056	/**
2057	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2058	* @todo verify this...
2059	*/
2060	#pragma pack(1)
2061	typedef struct X86FPUSTATE
2062	{
2063	/** 0x00 - Control word. */
2064	uint16_t FCW;
2065	/** 0x02 - Alignment word */
2066	uint16_t Dummy1;
2067	/** 0x04 - Status word. */
2068	uint16_t FSW;
2069	/** 0x06 - Alignment word */
2070	uint16_t Dummy2;
2071	/** 0x08 - Tag word */
2072	uint16_t FTW;
2073	/** 0x0a - Alignment word */
2074	uint16_t Dummy3;
2075
2076	/** 0x0c - Instruction pointer. */
2077	uint32_t FPUIP;
2078	/** 0x10 - Code selector. */
2079	uint16_t CS;
2080	/** 0x12 - Opcode. */
2081	uint16_t FOP;
2082	/** 0x14 - FOO. */
2083	uint32_t FPUOO;
2084	/** 0x18 - FOS. */
2085	uint32_t FPUOS;
2086	/** 0x1c */
2087	union
2088	{
2089	/** MMX view. */
2090	uint64_t mmx;
2091	/** FPU view - todo. */
2092	X86FPUMMX fpu;
2093	/** Extended precision floating point view. */
2094	RTFLOAT80U r80;
2095	/** Extended precision floating point view v2. */
2096	RTFLOAT80U2 r80Ex;
2097	/** 8-bit view. */
2098	uint8_t au8[16];
2099	/** 16-bit view. */
2100	uint16_t au16[8];
2101	/** 32-bit view. */
2102	uint32_t au32[4];
2103	/** 64-bit view. */
2104	uint64_t au64[2];
2105	/** 128-bit view. (yeah, very helpful) */
2106	uint128_t au128[1];
2107	} regs[8];
2108	} X86FPUSTATE;
2109	#pragma pack()
2110	/** Pointer to a FPU state. */
2111	typedef X86FPUSTATE *PX86FPUSTATE;
2112	/** Pointer to a const FPU state. */
2113	typedef const X86FPUSTATE *PCX86FPUSTATE;
2114
2115	/**
2116	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2117	*/
2118	#pragma pack(1)
2119	typedef struct X86FXSTATE
2120	{
2121	/** 0x00 - Control word. */
2122	uint16_t FCW;
2123	/** 0x02 - Status word. */
2124	uint16_t FSW;
2125	/** 0x04 - Tag word. (The upper byte is always zero.) */
2126	uint16_t FTW;
2127	/** 0x06 - Opcode. */
2128	uint16_t FOP;
2129	/** 0x08 - Instruction pointer. */
2130	uint32_t FPUIP;
2131	/** 0x0c - Code selector. */
2132	uint16_t CS;
2133	uint16_t Rsrvd1;
2134	/** 0x10 - Data pointer. */
2135	uint32_t FPUDP;
2136	/** 0x14 - Data segment */
2137	uint16_t DS;
2138	/** 0x16 */
2139	uint16_t Rsrvd2;
2140	/** 0x18 */
2141	uint32_t MXCSR;
2142	/** 0x1c */
2143	uint32_t MXCSR_MASK;
2144	/** 0x20 */
2145	union
2146	{
2147	/** MMX view. */
2148	uint64_t mmx;
2149	/** FPU view - todo. */
2150	X86FPUMMX fpu;
2151	/** Extended precision floating point view. */
2152	RTFLOAT80U r80;
2153	/** Extended precision floating point view v2 */
2154	RTFLOAT80U2 r80Ex;
2155	/** 8-bit view. */
2156	uint8_t au8[16];
2157	/** 16-bit view. */
2158	uint16_t au16[8];
2159	/** 32-bit view. */
2160	uint32_t au32[4];
2161	/** 64-bit view. */
2162	uint64_t au64[2];
2163	/** 128-bit view. (yeah, very helpful) */
2164	uint128_t au128[1];
2165	} aRegs[8];
2166	/* - offset 160 - */
2167	union
2168	{
2169	/** XMM Register view . /
2170	uint128_t xmm;
2171	/** 8-bit view. */
2172	uint8_t au8[16];
2173	/** 16-bit view. */
2174	uint16_t au16[8];
2175	/** 32-bit view. */
2176	uint32_t au32[4];
2177	/** 64-bit view. */
2178	uint64_t au64[2];
2179	/** 128-bit view. (yeah, very helpful) */
2180	uint128_t au128[1];
2181	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2182	/* - offset 416 - */
2183	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2184	} X86FXSTATE;
2185	#pragma pack()
2186	/** Pointer to a FPU Extended state. */
2187	typedef X86FXSTATE *PX86FXSTATE;
2188	/** Pointer to a const FPU Extended state. */
2189	typedef const X86FXSTATE *PCX86FXSTATE;
2190
2191	/** @name FPU status word flags.
2192	* @{ */
2193	/** Exception Flag: Invalid operation. */
2194	#define X86_FSW_IE RT_BIT(0)
2195	/** Exception Flag: Denormalized operand. */
2196	#define X86_FSW_DE RT_BIT(1)
2197	/** Exception Flag: Zero divide. */
2198	#define X86_FSW_ZE RT_BIT(2)
2199	/** Exception Flag: Overflow. */
2200	#define X86_FSW_OE RT_BIT(3)
2201	/** Exception Flag: Underflow. */
2202	#define X86_FSW_UE RT_BIT(4)
2203	/** Exception Flag: Precision. */
2204	#define X86_FSW_PE RT_BIT(5)
2205	/** Stack fault. */
2206	#define X86_FSW_SF RT_BIT(6)
2207	/** Error summary status. */
2208	#define X86_FSW_ES RT_BIT(7)
2209	/** Mask of exceptions flags, excluding the summary bit. */
2210	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2211	/** Mask of exceptions flags, including the summary bit. */
2212	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2213	/** Condition code 0. */
2214	#define X86_FSW_C0 RT_BIT(8)
2215	/** Condition code 1. */
2216	#define X86_FSW_C1 RT_BIT(9)
2217	/** Condition code 2. */
2218	#define X86_FSW_C2 RT_BIT(10)
2219	/** Top of the stack mask. */
2220	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2221	/** TOP shift value. */
2222	#define X86_FSW_TOP_SHIFT 11
2223	/** Mask for getting TOP value after shifting it right. */
2224	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2225	/** Get the TOP value. */
2226	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2227	/** Condition code 3. */
2228	#define X86_FSW_C3 RT_BIT(14)
2229	/** Mask of exceptions flags, including the summary bit. */
2230	#define X86_FSW_C_MASK UINT16_C(0x4700)
2231	/** FPU busy. */
2232	#define X86_FSW_B RT_BIT(15)
2233	/** @} */
2234
2235
2236	/** @name FPU control word flags.
2237	* @{ */
2238	/** Exception Mask: Invalid operation. */
2239	#define X86_FCW_IM RT_BIT(0)
2240	/** Exception Mask: Denormalized operand. */
2241	#define X86_FCW_DM RT_BIT(1)
2242	/** Exception Mask: Zero divide. */
2243	#define X86_FCW_ZM RT_BIT(2)
2244	/** Exception Mask: Overflow. */
2245	#define X86_FCW_OM RT_BIT(3)
2246	/** Exception Mask: Underflow. */
2247	#define X86_FCW_UM RT_BIT(4)
2248	/** Exception Mask: Precision. */
2249	#define X86_FCW_PM RT_BIT(5)
2250	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2251	* @remarks This includes reserved bit 6. */
2252	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2253	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2254	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2255	/** Precision control mask. */
2256	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2257	/** Precision control: 24-bit. */
2258	#define X86_FCW_PC_24 UINT16_C(0x0000)
2259	/** Precision control: Reserved. */
2260	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2261	/** Precision control: 53-bit. */
2262	#define X86_FCW_PC_53 UINT16_C(0x0200)
2263	/** Precision control: 64-bit. */
2264	#define X86_FCW_PC_64 UINT16_C(0x0300)
2265	/** Rounding control mask. */
2266	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2267	/** Rounding control: To nearest. */
2268	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2269	/** Rounding control: Down. */
2270	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2271	/** Rounding control: Up. */
2272	#define X86_FCW_RC_UP UINT16_C(0x0800)
2273	/** Rounding control: Towards zero. */
2274	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2275	/** Bits which should be zero, apparently. */
2276	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2277	/** @} */
2278
2279	/** @name SSE MXCSR
2280	* @{ */
2281	/** Exception Flag: Invalid operation. */
2282	#define X86_MSXCR_IE RT_BIT(0)
2283	/** Exception Flag: Denormalized operand. */
2284	#define X86_MSXCR_DE RT_BIT(1)
2285	/** Exception Flag: Zero divide. */
2286	#define X86_MSXCR_ZE RT_BIT(2)
2287	/** Exception Flag: Overflow. */
2288	#define X86_MSXCR_OE RT_BIT(3)
2289	/** Exception Flag: Underflow. */
2290	#define X86_MSXCR_UE RT_BIT(4)
2291	/** Exception Flag: Precision. */
2292	#define X86_MSXCR_PE RT_BIT(5)
2293
2294	/** Denormals are zero. */
2295	#define X86_MSXCR_DAZ RT_BIT(6)
2296
2297	/** Exception Mask: Invalid operation. */
2298	#define X86_MSXCR_IM RT_BIT(7)
2299	/** Exception Mask: Denormalized operand. */
2300	#define X86_MSXCR_DM RT_BIT(8)
2301	/** Exception Mask: Zero divide. */
2302	#define X86_MSXCR_ZM RT_BIT(9)
2303	/** Exception Mask: Overflow. */
2304	#define X86_MSXCR_OM RT_BIT(10)
2305	/** Exception Mask: Underflow. */
2306	#define X86_MSXCR_UM RT_BIT(11)
2307	/** Exception Mask: Precision. */
2308	#define X86_MSXCR_PM RT_BIT(12)
2309
2310	/** Rounding control mask. */
2311	#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2312	/** Rounding control: To nearest. */
2313	#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2314	/** Rounding control: Down. */
2315	#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2316	/** Rounding control: Up. */
2317	#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2318	/** Rounding control: Towards zero. */
2319	#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2320
2321	/** Flush-to-zero for masked underflow. */
2322	#define X86_MSXCR_FZ RT_BIT(15)
2323
2324	/** Misaligned Exception Mask. */
2325	#define X86_MSXCR_MM RT_BIT(16)
2326	/** @} */
2327
2328
2329	/** @name Selector Descriptor
2330	* @{
2331	*/
2332
2333	#ifndef VBOX_FOR_DTRACE_LIB
2334	/**
2335	* Descriptor attributes (as seen by VT-x).
2336	*/
2337	typedef struct X86DESCATTRBITS
2338	{
2339	/** 00 - Segment Type. */
2340	unsigned u4Type : 4;
2341	/** 04 - Descriptor Type. System(=0) or code/data selector */
2342	unsigned u1DescType : 1;
2343	/** 05 - Descriptor Privelege level. */
2344	unsigned u2Dpl : 2;
2345	/** 07 - Flags selector present(=1) or not. */
2346	unsigned u1Present : 1;
2347	/** 08 - Segment limit 16-19. */
2348	unsigned u4LimitHigh : 4;
2349	/** 0c - Available for system software. */
2350	unsigned u1Available : 1;
2351	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2352	unsigned u1Long : 1;
2353	/** 0e - This flags meaning depends on the segment type. Try make sense out
2354	* of the intel manual yourself. */
2355	unsigned u1DefBig : 1;
2356	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2357	* clear byte. */
2358	unsigned u1Granularity : 1;
2359	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2360	unsigned u1Unusable : 1;
2361	} X86DESCATTRBITS;
2362	#endif /* !VBOX_FOR_DTRACE_LIB */
2363
2364	/** @name X86DESCATTR masks
2365	* @{ */
2366	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2367	#define X86DESCATTR_DT UINT32_C(0x00000010)
2368	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2369	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2370	#define X86DESCATTR_P UINT32_C(0x00000800)
2371	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2372	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2373	#define X86DESCATTR_L UINT32_C(0x00002000)
2374	#define X86DESCATTR_D UINT32_C(0x00004000)
2375	#define X86DESCATTR_G UINT32_C(0x00008000)
2376	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2377	/** @} */
2378
2379	#pragma pack(1)
2380	typedef union X86DESCATTR
2381	{
2382	/** Unsigned integer view. */
2383	uint32_t u;
2384	#ifndef VBOX_FOR_DTRACE_LIB
2385	/** Normal view. */
2386	X86DESCATTRBITS n;
2387	#endif
2388	} X86DESCATTR;
2389	#pragma pack()
2390	/** Pointer to descriptor attributes. */
2391	typedef X86DESCATTR *PX86DESCATTR;
2392	/** Pointer to const descriptor attributes. */
2393	typedef const X86DESCATTR *PCX86DESCATTR;
2394
2395	#ifndef VBOX_FOR_DTRACE_LIB
2396
2397	/**
2398	* Generic descriptor table entry
2399	*/
2400	#pragma pack(1)
2401	typedef struct X86DESCGENERIC
2402	{
2403	/** 00 - Limit - Low word. */
2404	unsigned u16LimitLow : 16;
2405	/** 10 - Base address - lowe word.
2406	* Don't try set this to 24 because MSC is doing stupid things then. */
2407	unsigned u16BaseLow : 16;
2408	/** 20 - Base address - first 8 bits of high word. */
2409	unsigned u8BaseHigh1 : 8;
2410	/** 28 - Segment Type. */
2411	unsigned u4Type : 4;
2412	/** 2c - Descriptor Type. System(=0) or code/data selector */
2413	unsigned u1DescType : 1;
2414	/** 2d - Descriptor Privelege level. */
2415	unsigned u2Dpl : 2;
2416	/** 2f - Flags selector present(=1) or not. */
2417	unsigned u1Present : 1;
2418	/** 30 - Segment limit 16-19. */
2419	unsigned u4LimitHigh : 4;
2420	/** 34 - Available for system software. */
2421	unsigned u1Available : 1;
2422	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2423	unsigned u1Long : 1;
2424	/** 36 - This flags meaning depends on the segment type. Try make sense out
2425	* of the intel manual yourself. */
2426	unsigned u1DefBig : 1;
2427	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
2428	* clear byte. */
2429	unsigned u1Granularity : 1;
2430	/** 38 - Base address - highest 8 bits. */
2431	unsigned u8BaseHigh2 : 8;
2432	} X86DESCGENERIC;
2433	#pragma pack()
2434	/** Pointer to a generic descriptor entry. */
2435	typedef X86DESCGENERIC *PX86DESCGENERIC;
2436	/** Pointer to a const generic descriptor entry. */
2437	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2438
2439	/** @name Bit offsets of X86DESCGENERIC members.
2440	* @{*/
2441	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
2442	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
2443	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
2444	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
2445	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
2446	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
2447	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
2448	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
2449	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
2450	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
2451	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
2452	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
2453	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
2454	/** @} */
2455
2456	/**
2457	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2458	*/
2459	typedef struct X86DESCGATE
2460	{
2461	/** 00 - Target code segment offset - Low word.
2462	* Ignored if task-gate. */
2463	unsigned u16OffsetLow : 16;
2464	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2465	* TSS selector if task-gate. */
2466	unsigned u16Sel : 16;
2467	/** 20 - Number of parameters for a call-gate.
2468	* Ignored if interrupt-, trap- or task-gate. */
2469	unsigned u4ParmCount : 4;
2470	/** 24 - Reserved / ignored. */
2471	unsigned u4Reserved : 4;
2472	/** 28 - Segment Type. */
2473	unsigned u4Type : 4;
2474	/** 2c - Descriptor Type (0 = system). */
2475	unsigned u1DescType : 1;
2476	/** 2d - Descriptor Privelege level. */
2477	unsigned u2Dpl : 2;
2478	/** 2f - Flags selector present(=1) or not. */
2479	unsigned u1Present : 1;
2480	/** 30 - Target code segment offset - High word.
2481	* Ignored if task-gate. */
2482	unsigned u16OffsetHigh : 16;
2483	} X86DESCGATE;
2484	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2485	typedef X86DESCGATE *PX86DESCGATE;
2486	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2487	typedef const X86DESCGATE *PCX86DESCGATE;
2488
2489	#endif /* VBOX_FOR_DTRACE_LIB */
2490
2491	/**
2492	* Descriptor table entry.
2493	*/
2494	#pragma pack(1)
2495	typedef union X86DESC
2496	{
2497	#ifndef VBOX_FOR_DTRACE_LIB
2498	/** Generic descriptor view. */
2499	X86DESCGENERIC Gen;
2500	/** Gate descriptor view. */
2501	X86DESCGATE Gate;
2502	#endif
2503
2504	/** 8 bit unsigned integer view. */
2505	uint8_t au8[8];
2506	/** 16 bit unsigned integer view. */
2507	uint16_t au16[4];
2508	/** 32 bit unsigned integer view. */
2509	uint32_t au32[2];
2510	/** 64 bit unsigned integer view. */
2511	uint64_t au64[1];
2512	/** Unsigned integer view. */
2513	uint64_t u;
2514	} X86DESC;
2515	#ifndef VBOX_FOR_DTRACE_LIB
2516	AssertCompileSize(X86DESC, 8);
2517	#endif
2518	#pragma pack()
2519	/** Pointer to descriptor table entry. */
2520	typedef X86DESC *PX86DESC;
2521	/** Pointer to const descriptor table entry. */
2522	typedef const X86DESC *PCX86DESC;
2523
2524	/** @def X86DESC_BASE
2525	* Return the base address of a descriptor.
2526	*/
2527	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
2528	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2529	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2530	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2531
2532	/** @def X86DESC_LIMIT
2533	* Return the limit of a descriptor.
2534	*/
2535	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
2536	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2537	\| ( (a_pDesc)->Gen.u16LimitLow ) )
2538
2539	/** @def X86DESC_LIMIT_G
2540	* Return the limit of a descriptor with the granularity bit taken into account.
2541	* @returns Selector limit (uint32_t).
2542	* @param a_pDesc Pointer to the descriptor.
2543	*/
2544	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
2545	( (a_pDesc)->Gen.u1Granularity \
2546	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
2547	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
2548	)
2549
2550	/** @def X86DESC_GET_HID_ATTR
2551	* Get the descriptor attributes for the hidden register.
2552	*/
2553	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
2554	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2555
2556	#ifndef VBOX_FOR_DTRACE_LIB
2557
2558	/**
2559	* 64 bits generic descriptor table entry
2560	* Note: most of these bits have no meaning in long mode.
2561	*/
2562	#pragma pack(1)
2563	typedef struct X86DESC64GENERIC
2564	{
2565	/** Limit - Low word - IGNORED. */
2566	unsigned u16LimitLow : 16;
2567	/** Base address - low word. - IGNORED
2568	* Don't try set this to 24 because MSC is doing stupid things then. */
2569	unsigned u16BaseLow : 16;
2570	/** Base address - first 8 bits of high word. - IGNORED */
2571	unsigned u8BaseHigh1 : 8;
2572	/** Segment Type. */
2573	unsigned u4Type : 4;
2574	/** Descriptor Type. System(=0) or code/data selector */
2575	unsigned u1DescType : 1;
2576	/** Descriptor Privelege level. */
2577	unsigned u2Dpl : 2;
2578	/** Flags selector present(=1) or not. */
2579	unsigned u1Present : 1;
2580	/** Segment limit 16-19. - IGNORED */
2581	unsigned u4LimitHigh : 4;
2582	/** Available for system software. - IGNORED */
2583	unsigned u1Available : 1;
2584	/** Long mode flag. */
2585	unsigned u1Long : 1;
2586	/** This flags meaning depends on the segment type. Try make sense out
2587	* of the intel manual yourself. */
2588	unsigned u1DefBig : 1;
2589	/** Granularity of the limit. If set 4KB granularity is used, if
2590	* clear byte. - IGNORED */
2591	unsigned u1Granularity : 1;
2592	/** Base address - highest 8 bits. - IGNORED */
2593	unsigned u8BaseHigh2 : 8;
2594	/** Base address - bits 63-32. */
2595	unsigned u32BaseHigh3 : 32;
2596	unsigned u8Reserved : 8;
2597	unsigned u5Zeros : 5;
2598	unsigned u19Reserved : 19;
2599	} X86DESC64GENERIC;
2600	#pragma pack()
2601	/** Pointer to a generic descriptor entry. */
2602	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2603	/** Pointer to a const generic descriptor entry. */
2604	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2605
2606	/**
2607	* System descriptor table entry (64 bits)
2608	*
2609	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2610	*/
2611	#pragma pack(1)
2612	typedef struct X86DESC64SYSTEM
2613	{
2614	/** Limit - Low word. */
2615	unsigned u16LimitLow : 16;
2616	/** Base address - lowe word.
2617	* Don't try set this to 24 because MSC is doing stupid things then. */
2618	unsigned u16BaseLow : 16;
2619	/** Base address - first 8 bits of high word. */
2620	unsigned u8BaseHigh1 : 8;
2621	/** Segment Type. */
2622	unsigned u4Type : 4;
2623	/** Descriptor Type. System(=0) or code/data selector */
2624	unsigned u1DescType : 1;
2625	/** Descriptor Privelege level. */
2626	unsigned u2Dpl : 2;
2627	/** Flags selector present(=1) or not. */
2628	unsigned u1Present : 1;
2629	/** Segment limit 16-19. */
2630	unsigned u4LimitHigh : 4;
2631	/** Available for system software. */
2632	unsigned u1Available : 1;
2633	/** Reserved - 0. */
2634	unsigned u1Reserved : 1;
2635	/** This flags meaning depends on the segment type. Try make sense out
2636	* of the intel manual yourself. */
2637	unsigned u1DefBig : 1;
2638	/** Granularity of the limit. If set 4KB granularity is used, if
2639	* clear byte. */
2640	unsigned u1Granularity : 1;
2641	/** Base address - bits 31-24. */
2642	unsigned u8BaseHigh2 : 8;
2643	/** Base address - bits 63-32. */
2644	unsigned u32BaseHigh3 : 32;
2645	unsigned u8Reserved : 8;
2646	unsigned u5Zeros : 5;
2647	unsigned u19Reserved : 19;
2648	} X86DESC64SYSTEM;
2649	#pragma pack()
2650	/** Pointer to a system descriptor entry. */
2651	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2652	/** Pointer to a const system descriptor entry. */
2653	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2654
2655	/**
2656	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2657	*/
2658	typedef struct X86DESC64GATE
2659	{
2660	/** Target code segment offset - Low word. */
2661	unsigned u16OffsetLow : 16;
2662	/** Target code segment selector. */
2663	unsigned u16Sel : 16;
2664	/** Interrupt stack table for interrupt- and trap-gates.
2665	* Ignored by call-gates. */
2666	unsigned u3IST : 3;
2667	/** Reserved / ignored. */
2668	unsigned u5Reserved : 5;
2669	/** Segment Type. */
2670	unsigned u4Type : 4;
2671	/** Descriptor Type (0 = system). */
2672	unsigned u1DescType : 1;
2673	/** Descriptor Privelege level. */
2674	unsigned u2Dpl : 2;
2675	/** Flags selector present(=1) or not. */
2676	unsigned u1Present : 1;
2677	/** Target code segment offset - High word.
2678	* Ignored if task-gate. */
2679	unsigned u16OffsetHigh : 16;
2680	/** Target code segment offset - Top dword.
2681	* Ignored if task-gate. */
2682	unsigned u32OffsetTop : 32;
2683	/** Reserved / ignored / must be zero.
2684	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2685	unsigned u32Reserved : 32;
2686	} X86DESC64GATE;
2687	AssertCompileSize(X86DESC64GATE, 16);
2688	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2689	typedef X86DESC64GATE *PX86DESC64GATE;
2690	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2691	typedef const X86DESC64GATE *PCX86DESC64GATE;
2692
2693	#endif /* VBOX_FOR_DTRACE_LIB */
2694
2695	/**
2696	* Descriptor table entry.
2697	*/
2698	#pragma pack(1)
2699	typedef union X86DESC64
2700	{
2701	#ifndef VBOX_FOR_DTRACE_LIB
2702	/** Generic descriptor view. */
2703	X86DESC64GENERIC Gen;
2704	/** System descriptor view. */
2705	X86DESC64SYSTEM System;
2706	/** Gate descriptor view. */
2707	X86DESC64GATE Gate;
2708	#endif
2709
2710	/** 8 bit unsigned integer view. */
2711	uint8_t au8[16];
2712	/** 16 bit unsigned integer view. */
2713	uint16_t au16[8];
2714	/** 32 bit unsigned integer view. */
2715	uint32_t au32[4];
2716	/** 64 bit unsigned integer view. */
2717	uint64_t au64[2];
2718	} X86DESC64;
2719	#ifndef VBOX_FOR_DTRACE_LIB
2720	AssertCompileSize(X86DESC64, 16);
2721	#endif
2722	#pragma pack()
2723	/** Pointer to descriptor table entry. */
2724	typedef X86DESC64 *PX86DESC64;
2725	/** Pointer to const descriptor table entry. */
2726	typedef const X86DESC64 *PCX86DESC64;
2727
2728	/** @def X86DESC64_BASE
2729	* Return the base of a 64-bit descriptor.
2730	*/
2731	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
2732	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2733	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2734	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2735	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2736
2737
2738
2739	/** @name Host system descriptor table entry - Use with care!
2740	* @{ */
2741	/** Host system descriptor table entry. */
2742	#if HC_ARCH_BITS == 64
2743	typedef X86DESC64 X86DESCHC;
2744	#else
2745	typedef X86DESC X86DESCHC;
2746	#endif
2747	/** Pointer to a host system descriptor table entry. */
2748	#if HC_ARCH_BITS == 64
2749	typedef PX86DESC64 PX86DESCHC;
2750	#else
2751	typedef PX86DESC PX86DESCHC;
2752	#endif
2753	/** Pointer to a const host system descriptor table entry. */
2754	#if HC_ARCH_BITS == 64
2755	typedef PCX86DESC64 PCX86DESCHC;
2756	#else
2757	typedef PCX86DESC PCX86DESCHC;
2758	#endif
2759	/** @} */
2760
2761
2762	/** @name Selector Descriptor Types.
2763	* @{
2764	*/
2765
2766	/** @name Non-System Selector Types.
2767	* @{ */
2768	/** Code(=set)/Data(=clear) bit. */
2769	#define X86_SEL_TYPE_CODE 8
2770	/** Memory(=set)/System(=clear) bit. */
2771	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2772	/** Accessed bit. */
2773	#define X86_SEL_TYPE_ACCESSED 1
2774	/** Expand down bit (for data selectors only). */
2775	#define X86_SEL_TYPE_DOWN 4
2776	/** Conforming bit (for code selectors only). */
2777	#define X86_SEL_TYPE_CONF 4
2778	/** Write bit (for data selectors only). */
2779	#define X86_SEL_TYPE_WRITE 2
2780	/** Read bit (for code selectors only). */
2781	#define X86_SEL_TYPE_READ 2
2782	/** The bit number of the code segment read bit (relative to u4Type). */
2783	#define X86_SEL_TYPE_READ_BIT 1
2784
2785	/** Read only selector type. */
2786	#define X86_SEL_TYPE_RO 0
2787	/** Accessed read only selector type. */
2788	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2789	/** Read write selector type. */
2790	#define X86_SEL_TYPE_RW 2
2791	/** Accessed read write selector type. */
2792	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2793	/** Expand down read only selector type. */
2794	#define X86_SEL_TYPE_RO_DOWN 4
2795	/** Accessed expand down read only selector type. */
2796	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2797	/** Expand down read write selector type. */
2798	#define X86_SEL_TYPE_RW_DOWN 6
2799	/** Accessed expand down read write selector type. */
2800	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2801	/** Execute only selector type. */
2802	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2803	/** Accessed execute only selector type. */
2804	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2805	/** Execute and read selector type. */
2806	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2807	/** Accessed execute and read selector type. */
2808	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2809	/** Conforming execute only selector type. */
2810	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2811	/** Accessed Conforming execute only selector type. */
2812	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2813	/** Conforming execute and write selector type. */
2814	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2815	/** Accessed Conforming execute and write selector type. */
2816	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2817	/** @} */
2818
2819
2820	/** @name System Selector Types.
2821	* @{ */
2822	/** The TSS busy bit mask. */
2823	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2824
2825	/** Undefined system selector type. */
2826	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2827	/** 286 TSS selector. */
2828	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2829	/** LDT selector. */
2830	#define X86_SEL_TYPE_SYS_LDT 2
2831	/** 286 TSS selector - Busy. */
2832	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2833	/** 286 Callgate selector. */
2834	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2835	/** Taskgate selector. */
2836	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2837	/** 286 Interrupt gate selector. */
2838	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2839	/** 286 Trapgate selector. */
2840	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2841	/** Undefined system selector. */
2842	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2843	/** 386 TSS selector. */
2844	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2845	/** Undefined system selector. */
2846	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2847	/** 386 TSS selector - Busy. */
2848	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2849	/** 386 Callgate selector. */
2850	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2851	/** Undefined system selector. */
2852	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2853	/** 386 Interruptgate selector. */
2854	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2855	/** 386 Trapgate selector. */
2856	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2857	/** @} */
2858
2859	/** @name AMD64 System Selector Types.
2860	* @{ */
2861	/** LDT selector. */
2862	#define AMD64_SEL_TYPE_SYS_LDT 2
2863	/** TSS selector - Busy. */
2864	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2865	/** TSS selector - Busy. */
2866	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2867	/** Callgate selector. */
2868	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2869	/** Interruptgate selector. */
2870	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2871	/** Trapgate selector. */
2872	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2873	/** @} */
2874
2875	/** @} */
2876
2877
2878	/** @name Descriptor Table Entry Flag Masks.
2879	* These are for the 2nd 32-bit word of a descriptor.
2880	* @{ */
2881	/** Bits 8-11 - TYPE - Descriptor type mask. */
2882	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2883	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2884	#define X86_DESC_S RT_BIT(12)
2885	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2886	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2887	/** Bit 15 - P - Present. */
2888	#define X86_DESC_P RT_BIT(15)
2889	/** Bit 20 - AVL - Available for system software. */
2890	#define X86_DESC_AVL RT_BIT(20)
2891	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2892	#define X86_DESC_DB RT_BIT(22)
2893	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2894	* used, if clear byte. */
2895	#define X86_DESC_G RT_BIT(23)
2896	/** @} */
2897
2898	/** @} */
2899
2900
2901	/** @name Task Segments.
2902	* @{
2903	*/
2904
2905	/**
2906	* 16-bit Task Segment (TSS).
2907	*/
2908	#pragma pack(1)
2909	typedef struct X86TSS16
2910	{
2911	/** Back link to previous task. (static) */
2912	RTSEL selPrev;
2913	/** Ring-0 stack pointer. (static) */
2914	uint16_t sp0;
2915	/** Ring-0 stack segment. (static) */
2916	RTSEL ss0;
2917	/** Ring-1 stack pointer. (static) */
2918	uint16_t sp1;
2919	/** Ring-1 stack segment. (static) */
2920	RTSEL ss1;
2921	/** Ring-2 stack pointer. (static) */
2922	uint16_t sp2;
2923	/** Ring-2 stack segment. (static) */
2924	RTSEL ss2;
2925	/** IP before task switch. */
2926	uint16_t ip;
2927	/** FLAGS before task switch. */
2928	uint16_t flags;
2929	/** AX before task switch. */
2930	uint16_t ax;
2931	/** CX before task switch. */
2932	uint16_t cx;
2933	/** DX before task switch. */
2934	uint16_t dx;
2935	/** BX before task switch. */
2936	uint16_t bx;
2937	/** SP before task switch. */
2938	uint16_t sp;
2939	/** BP before task switch. */
2940	uint16_t bp;
2941	/** SI before task switch. */
2942	uint16_t si;
2943	/** DI before task switch. */
2944	uint16_t di;
2945	/** ES before task switch. */
2946	RTSEL es;
2947	/** CS before task switch. */
2948	RTSEL cs;
2949	/** SS before task switch. */
2950	RTSEL ss;
2951	/** DS before task switch. */
2952	RTSEL ds;
2953	/** LDTR before task switch. */
2954	RTSEL selLdt;
2955	} X86TSS16;
2956	#ifndef VBOX_FOR_DTRACE_LIB
2957	AssertCompileSize(X86TSS16, 44);
2958	#endif
2959	#pragma pack()
2960	/** Pointer to a 16-bit task segment. */
2961	typedef X86TSS16 *PX86TSS16;
2962	/** Pointer to a const 16-bit task segment. */
2963	typedef const X86TSS16 *PCX86TSS16;
2964
2965
2966	/**
2967	* 32-bit Task Segment (TSS).
2968	*/
2969	#pragma pack(1)
2970	typedef struct X86TSS32
2971	{
2972	/** Back link to previous task. (static) */
2973	RTSEL selPrev;
2974	uint16_t padding1;
2975	/** Ring-0 stack pointer. (static) */
2976	uint32_t esp0;
2977	/** Ring-0 stack segment. (static) */
2978	RTSEL ss0;
2979	uint16_t padding_ss0;
2980	/** Ring-1 stack pointer. (static) */
2981	uint32_t esp1;
2982	/** Ring-1 stack segment. (static) */
2983	RTSEL ss1;
2984	uint16_t padding_ss1;
2985	/** Ring-2 stack pointer. (static) */
2986	uint32_t esp2;
2987	/** Ring-2 stack segment. (static) */
2988	RTSEL ss2;
2989	uint16_t padding_ss2;
2990	/** Page directory for the task. (static) */
2991	uint32_t cr3;
2992	/** EIP before task switch. */
2993	uint32_t eip;
2994	/** EFLAGS before task switch. */
2995	uint32_t eflags;
2996	/** EAX before task switch. */
2997	uint32_t eax;
2998	/** ECX before task switch. */
2999	uint32_t ecx;
3000	/** EDX before task switch. */
3001	uint32_t edx;
3002	/** EBX before task switch. */
3003	uint32_t ebx;
3004	/** ESP before task switch. */
3005	uint32_t esp;
3006	/** EBP before task switch. */
3007	uint32_t ebp;
3008	/** ESI before task switch. */
3009	uint32_t esi;
3010	/** EDI before task switch. */
3011	uint32_t edi;
3012	/** ES before task switch. */
3013	RTSEL es;
3014	uint16_t padding_es;
3015	/** CS before task switch. */
3016	RTSEL cs;
3017	uint16_t padding_cs;
3018	/** SS before task switch. */
3019	RTSEL ss;
3020	uint16_t padding_ss;
3021	/** DS before task switch. */
3022	RTSEL ds;
3023	uint16_t padding_ds;
3024	/** FS before task switch. */
3025	RTSEL fs;
3026	uint16_t padding_fs;
3027	/** GS before task switch. */
3028	RTSEL gs;
3029	uint16_t padding_gs;
3030	/** LDTR before task switch. */
3031	RTSEL selLdt;
3032	uint16_t padding_ldt;
3033	/** Debug trap flag */
3034	uint16_t fDebugTrap;
3035	/** Offset relative to the TSS of the start of the I/O Bitmap
3036	* and the end of the interrupt redirection bitmap. */
3037	uint16_t offIoBitmap;
3038	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3039	uint8_t IntRedirBitmap[32];
3040	} X86TSS32;
3041	#pragma pack()
3042	/** Pointer to task segment. */
3043	typedef X86TSS32 *PX86TSS32;
3044	/** Pointer to const task segment. */
3045	typedef const X86TSS32 *PCX86TSS32;
3046
3047
3048	/**
3049	* 64-bit Task segment.
3050	*/
3051	#pragma pack(1)
3052	typedef struct X86TSS64
3053	{
3054	/** Reserved. */
3055	uint32_t u32Reserved;
3056	/** Ring-0 stack pointer. (static) */
3057	uint64_t rsp0;
3058	/** Ring-1 stack pointer. (static) */
3059	uint64_t rsp1;
3060	/** Ring-2 stack pointer. (static) */
3061	uint64_t rsp2;
3062	/** Reserved. */
3063	uint32_t u32Reserved2[2];
3064	/* IST */
3065	uint64_t ist1;
3066	uint64_t ist2;
3067	uint64_t ist3;
3068	uint64_t ist4;
3069	uint64_t ist5;
3070	uint64_t ist6;
3071	uint64_t ist7;
3072	/* Reserved. */
3073	uint16_t u16Reserved[5];
3074	/** Offset relative to the TSS of the start of the I/O Bitmap
3075	* and the end of the interrupt redirection bitmap. */
3076	uint16_t offIoBitmap;
3077	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3078	uint8_t IntRedirBitmap[32];
3079	} X86TSS64;
3080	#pragma pack()
3081	/** Pointer to a 64-bit task segment. */
3082	typedef X86TSS64 *PX86TSS64;
3083	/** Pointer to a const 64-bit task segment. */
3084	typedef const X86TSS64 *PCX86TSS64;
3085	#ifndef VBOX_FOR_DTRACE_LIB
3086	AssertCompileSize(X86TSS64, 136);
3087	#endif
3088
3089	/** @} */
3090
3091
3092	/** @name Selectors.
3093	* @{
3094	*/
3095
3096	/**
3097	* The shift used to convert a selector from and to index an index (C).
3098	*/
3099	#define X86_SEL_SHIFT 3
3100
3101	/**
3102	* The mask used to mask off the table indicator and RPL of an selector.
3103	*/
3104	#define X86_SEL_MASK 0xfff8U
3105
3106	/**
3107	* The mask used to mask off the RPL of an selector.
3108	* This is suitable for checking for NULL selectors.
3109	*/
3110	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3111
3112	/**
3113	* The bit indicating that a selector is in the LDT and not in the GDT.
3114	*/
3115	#define X86_SEL_LDT 0x0004U
3116
3117	/**
3118	* The bit mask for getting the RPL of a selector.
3119	*/
3120	#define X86_SEL_RPL 0x0003U
3121
3122	/**
3123	* The mask covering both RPL and LDT.
3124	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3125	* checks.
3126	*/
3127	#define X86_SEL_RPL_LDT 0x0007U
3128
3129	/** @} */
3130
3131
3132	/**
3133	* x86 Exceptions/Faults/Traps.
3134	*/
3135	typedef enum X86XCPT
3136	{
3137	/** \#DE - Divide error. */
3138	X86_XCPT_DE = 0x00,
3139	/** \#DB - Debug event (single step, DRx, ..) */
3140	X86_XCPT_DB = 0x01,
3141	/** NMI - Non-Maskable Interrupt */
3142	X86_XCPT_NMI = 0x02,
3143	/** \#BP - Breakpoint (INT3). */
3144	X86_XCPT_BP = 0x03,
3145	/** \#OF - Overflow (INTO). */
3146	X86_XCPT_OF = 0x04,
3147	/** \#BR - Bound range exceeded (BOUND). */
3148	X86_XCPT_BR = 0x05,
3149	/** \#UD - Undefined opcode. */
3150	X86_XCPT_UD = 0x06,
3151	/** \#NM - Device not available (math coprocessor device). */
3152	X86_XCPT_NM = 0x07,
3153	/** \#DF - Double fault. */
3154	X86_XCPT_DF = 0x08,
3155	/** ??? - Coprocessor segment overrun (obsolete). */
3156	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3157	/** \#TS - Taskswitch (TSS). */
3158	X86_XCPT_TS = 0x0a,
3159	/** \#NP - Segment no present. */
3160	X86_XCPT_NP = 0x0b,
3161	/** \#SS - Stack segment fault. */
3162	X86_XCPT_SS = 0x0c,
3163	/** \#GP - General protection fault. */
3164	X86_XCPT_GP = 0x0d,
3165	/** \#PF - Page fault. */
3166	X86_XCPT_PF = 0x0e,
3167	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3168	/** \#MF - Math fault (FPU). */
3169	X86_XCPT_MF = 0x10,
3170	/** \#AC - Alignment check. */
3171	X86_XCPT_AC = 0x11,
3172	/** \#MC - Machine check. */
3173	X86_XCPT_MC = 0x12,
3174	/** \#XF - SIMD Floating-Pointer Exception. */
3175	X86_XCPT_XF = 0x13,
3176	/** \#VE - Virtualzation Exception. */
3177	X86_XCPT_VE = 0x14,
3178	/** \#SX - Security Exception. */
3179	X86_XCPT_SX = 0x1f
3180	} X86XCPT;
3181	/** Pointer to a x86 exception code. */
3182	typedef X86XCPT *PX86XCPT;
3183	/** Pointer to a const x86 exception code. */
3184	typedef const X86XCPT *PCX86XCPT;
3185	/** The maximum exception value. */
3186	#define X86_XCPT_MAX (X86_XCPT_SX)
3187
3188
3189	/** @name Trap Error Codes
3190	* @{
3191	*/
3192	/** External indicator. */
3193	#define X86_TRAP_ERR_EXTERNAL 1
3194	/** IDT indicator. */
3195	#define X86_TRAP_ERR_IDT 2
3196	/** Descriptor table indicator - If set LDT, if clear GDT. */
3197	#define X86_TRAP_ERR_TI 4
3198	/** Mask for getting the selector. */
3199	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3200	/** Shift for getting the selector table index (C type index). */
3201	#define X86_TRAP_ERR_SEL_SHIFT 3
3202	/** @} */
3203
3204
3205	/** @name \#PF Trap Error Codes
3206	* @{
3207	*/
3208	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3209	#define X86_TRAP_PF_P RT_BIT(0)
3210	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3211	#define X86_TRAP_PF_RW RT_BIT(1)
3212	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3213	#define X86_TRAP_PF_US RT_BIT(2)
3214	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3215	#define X86_TRAP_PF_RSVD RT_BIT(3)
3216	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3217	#define X86_TRAP_PF_ID RT_BIT(4)
3218	/** @} */
3219
3220	#pragma pack(1)
3221	/**
3222	* 32-bit IDTR/GDTR.
3223	*/
3224	typedef struct X86XDTR32
3225	{
3226	/** Size of the descriptor table. */
3227	uint16_t cb;
3228	/** Address of the descriptor table. */
3229	#ifndef VBOX_FOR_DTRACE_LIB
3230	uint32_t uAddr;
3231	#else
3232	uint16_t au16Addr[2];
3233	#endif
3234	} X86XDTR32, *PX86XDTR32;
3235	#pragma pack()
3236
3237	#pragma pack(1)
3238	/**
3239	* 64-bit IDTR/GDTR.
3240	*/
3241	typedef struct X86XDTR64
3242	{
3243	/** Size of the descriptor table. */
3244	uint16_t cb;
3245	/** Address of the descriptor table. */
3246	#ifndef VBOX_FOR_DTRACE_LIB
3247	uint64_t uAddr;
3248	#else
3249	uint16_t au16Addr[4];
3250	#endif
3251	} X86XDTR64, *PX86XDTR64;
3252	#pragma pack()
3253
3254
3255	/** @name ModR/M
3256	* @{ */
3257	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3258	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3259	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3260	#define X86_MODRM_REG_SHIFT 3
3261	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3262	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3263	#define X86_MODRM_MOD_SHIFT 6
3264	#ifndef VBOX_FOR_DTRACE_LIB
3265	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3266	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3267	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3268	#endif
3269	/** @} */
3270
3271	/** @name SIB
3272	* @{ */
3273	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3274	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3275	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3276	#define X86_SIB_INDEX_SHIFT 3
3277	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3278	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3279	#define X86_SIB_SCALE_SHIFT 6
3280	#ifndef VBOX_FOR_DTRACE_LIB
3281	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3282	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3283	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3284	#endif
3285	/** @} */
3286
3287	/** @name General register indexes
3288	* @{ */
3289	#define X86_GREG_xAX 0
3290	#define X86_GREG_xCX 1
3291	#define X86_GREG_xDX 2
3292	#define X86_GREG_xBX 3
3293	#define X86_GREG_xSP 4
3294	#define X86_GREG_xBP 5
3295	#define X86_GREG_xSI 6
3296	#define X86_GREG_xDI 7
3297	#define X86_GREG_x8 8
3298	#define X86_GREG_x9 9
3299	#define X86_GREG_x10 10
3300	#define X86_GREG_x11 11
3301	#define X86_GREG_x12 12
3302	#define X86_GREG_x13 13
3303	#define X86_GREG_x14 14
3304	#define X86_GREG_x15 15
3305	/** @} */
3306
3307	/** @name X86_SREG_XXX - Segment register indexes.
3308	* @{ */
3309	#define X86_SREG_ES 0
3310	#define X86_SREG_CS 1
3311	#define X86_SREG_SS 2
3312	#define X86_SREG_DS 3
3313	#define X86_SREG_FS 4
3314	#define X86_SREG_GS 5
3315	/** @} */
3316	/** Segment register count. */
3317	#define X86_SREG_COUNT 6
3318
3319
3320	/** @name X86_OP_XXX - Prefixes
3321	* @{ */
3322	#define X86_OP_PRF_CS UINT8_C(0x2e)
3323	#define X86_OP_PRF_SS UINT8_C(0x36)
3324	#define X86_OP_PRF_DS UINT8_C(0x3e)
3325	#define X86_OP_PRF_ES UINT8_C(0x26)
3326	#define X86_OP_PRF_FS UINT8_C(0x64)
3327	#define X86_OP_PRF_GS UINT8_C(0x65)
3328	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3329	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3330	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3331	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3332	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3333	#define X86_OP_REX_B UINT8_C(0x41)
3334	#define X86_OP_REX_X UINT8_C(0x42)
3335	#define X86_OP_REX_R UINT8_C(0x44)
3336	#define X86_OP_REX_W UINT8_C(0x48)
3337	/** @} */
3338
3339
3340	/** @} */
3341
3342	#endif
3343

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source: vbox/trunk/include/iprt/x86.h@ 47660

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