x86.h@ 47667

Last change on this file since 47667 was 47667, checked in by vboxsync, 11 years ago
x86.h: A couple of DR7 macros.
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	/** Bit 1 - Reserved, reads as 1. */
165	#define X86_EFL_1 RT_BIT(1)
166	/** Bit 2 - PF - Parity flag - Status flag. */
167	#define X86_EFL_PF RT_BIT(2)
168	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169	#define X86_EFL_AF RT_BIT(4)
170	/** Bit 6 - ZF - Zero flag - Status flag. */
171	#define X86_EFL_ZF RT_BIT(6)
172	/** Bit 7 - SF - Signed flag - Status flag. */
173	#define X86_EFL_SF RT_BIT(7)
174	/** Bit 8 - TF - Trap flag - System flag. */
175	#define X86_EFL_TF RT_BIT(8)
176	/** Bit 9 - IF - Interrupt flag - System flag. */
177	#define X86_EFL_IF RT_BIT(9)
178	/** Bit 10 - DF - Direction flag - Control flag. */
179	#define X86_EFL_DF RT_BIT(10)
180	/** Bit 11 - OF - Overflow flag - Status flag. */
181	#define X86_EFL_OF RT_BIT(11)
182	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
184	/** Bit 14 - NT - Nested task flag - System flag. */
185	#define X86_EFL_NT RT_BIT(14)
186	/** Bit 16 - RF - Resume flag - System flag. */
187	#define X86_EFL_RF RT_BIT(16)
188	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189	#define X86_EFL_VM RT_BIT(17)
190	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191	#define X86_EFL_AC RT_BIT(18)
192	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193	#define X86_EFL_VIF RT_BIT(19)
194	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195	#define X86_EFL_VIP RT_BIT(20)
196	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197	#define X86_EFL_ID RT_BIT(21)
198	/** All live bits. */
199	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
200	/** Read as 1 bits. */
201	#define X86_EFL_RA1_MASK RT_BIT_32(1)
202	/** IOPL shift. */
203	#define X86_EFL_IOPL_SHIFT 12
204	/** The the IOPL level from the flags. */
205	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
206	/** Bits restored by popf */
207	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
208	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
209	/** @} */
210
211
212	/** CPUID Feature information - ECX.
213	* CPUID query with EAX=1.
214	*/
215	#ifndef VBOX_FOR_DTRACE_LIB
216	typedef struct X86CPUIDFEATECX
217	{
218	/** Bit 0 - SSE3 - Supports SSE3 or not. */
219	unsigned u1SSE3 : 1;
220	/** Bit 1 - PCLMULQDQ. */
221	unsigned u1PCLMULQDQ : 1;
222	/** Bit 2 - DS Area 64-bit layout. */
223	unsigned u1DTE64 : 1;
224	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
225	unsigned u1Monitor : 1;
226	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
227	unsigned u1CPLDS : 1;
228	/** Bit 5 - VMX - Virtual Machine Technology. */
229	unsigned u1VMX : 1;
230	/** Bit 6 - SMX: Safer Mode Extensions. */
231	unsigned u1SMX : 1;
232	/** Bit 7 - EST - Enh. SpeedStep Tech. */
233	unsigned u1EST : 1;
234	/** Bit 8 - TM2 - Terminal Monitor 2. */
235	unsigned u1TM2 : 1;
236	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
237	unsigned u1SSSE3 : 1;
238	/** Bit 10 - CNTX-ID - L1 Context ID. */
239	unsigned u1CNTXID : 1;
240	/** Bit 11 - Reserved. */
241	unsigned u1Reserved1 : 1;
242	/** Bit 12 - FMA. */
243	unsigned u1FMA : 1;
244	/** Bit 13 - CX16 - CMPXCHG16B. */
245	unsigned u1CX16 : 1;
246	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
247	unsigned u1TPRUpdate : 1;
248	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
249	unsigned u1PDCM : 1;
250	/** Bit 16 - Reserved. */
251	unsigned u1Reserved2 : 1;
252	/** Bit 17 - PCID - Process-context identifiers. */
253	unsigned u1PCID : 1;
254	/** Bit 18 - Direct Cache Access. */
255	unsigned u1DCA : 1;
256	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
257	unsigned u1SSE4_1 : 1;
258	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
259	unsigned u1SSE4_2 : 1;
260	/** Bit 21 - x2APIC. */
261	unsigned u1x2APIC : 1;
262	/** Bit 22 - MOVBE - Supports MOVBE. */
263	unsigned u1MOVBE : 1;
264	/** Bit 23 - POPCNT - Supports POPCNT. */
265	unsigned u1POPCNT : 1;
266	/** Bit 24 - TSC-Deadline. */
267	unsigned u1TSCDEADLINE : 1;
268	/** Bit 25 - AES. */
269	unsigned u1AES : 1;
270	/** Bit 26 - XSAVE - Supports XSAVE. */
271	unsigned u1XSAVE : 1;
272	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
273	unsigned u1OSXSAVE : 1;
274	/** Bit 28 - AVX - Supports AVX instruction extensions. */
275	unsigned u1AVX : 1;
276	/** Bit 29 - 30 - Reserved */
277	unsigned u2Reserved3 : 2;
278	/** Bit 31 - Hypervisor present (we're a guest). */
279	unsigned u1HVP : 1;
280	} X86CPUIDFEATECX;
281	#else /* VBOX_FOR_DTRACE_LIB */
282	typedef uint32_t X86CPUIDFEATECX;
283	#endif /* VBOX_FOR_DTRACE_LIB */
284	/** Pointer to CPUID Feature Information - ECX. */
285	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
286	/** Pointer to const CPUID Feature Information - ECX. */
287	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
288
289
290	/** CPUID Feature Information - EDX.
291	* CPUID query with EAX=1.
292	*/
293	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
294	typedef struct X86CPUIDFEATEDX
295	{
296	/** Bit 0 - FPU - x87 FPU on Chip. */
297	unsigned u1FPU : 1;
298	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
299	unsigned u1VME : 1;
300	/** Bit 2 - DE - Debugging extensions. */
301	unsigned u1DE : 1;
302	/** Bit 3 - PSE - Page Size Extension. */
303	unsigned u1PSE : 1;
304	/** Bit 4 - TSC - Time Stamp Counter. */
305	unsigned u1TSC : 1;
306	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
307	unsigned u1MSR : 1;
308	/** Bit 6 - PAE - Physical Address Extension. */
309	unsigned u1PAE : 1;
310	/** Bit 7 - MCE - Machine Check Exception. */
311	unsigned u1MCE : 1;
312	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
313	unsigned u1CX8 : 1;
314	/** Bit 9 - APIC - APIC On-Chip. */
315	unsigned u1APIC : 1;
316	/** Bit 10 - Reserved. */
317	unsigned u1Reserved1 : 1;
318	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
319	unsigned u1SEP : 1;
320	/** Bit 12 - MTRR - Memory Type Range Registers. */
321	unsigned u1MTRR : 1;
322	/** Bit 13 - PGE - PTE Global Bit. */
323	unsigned u1PGE : 1;
324	/** Bit 14 - MCA - Machine Check Architecture. */
325	unsigned u1MCA : 1;
326	/** Bit 15 - CMOV - Conditional Move Instructions. */
327	unsigned u1CMOV : 1;
328	/** Bit 16 - PAT - Page Attribute Table. */
329	unsigned u1PAT : 1;
330	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
331	unsigned u1PSE36 : 1;
332	/** Bit 18 - PSN - Processor Serial Number. */
333	unsigned u1PSN : 1;
334	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
335	unsigned u1CLFSH : 1;
336	/** Bit 20 - Reserved. */
337	unsigned u1Reserved2 : 1;
338	/** Bit 21 - DS - Debug Store. */
339	unsigned u1DS : 1;
340	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
341	unsigned u1ACPI : 1;
342	/** Bit 23 - MMX - Intel MMX 'Technology'. */
343	unsigned u1MMX : 1;
344	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
345	unsigned u1FXSR : 1;
346	/** Bit 25 - SSE - SSE Support. */
347	unsigned u1SSE : 1;
348	/** Bit 26 - SSE2 - SSE2 Support. */
349	unsigned u1SSE2 : 1;
350	/** Bit 27 - SS - Self Snoop. */
351	unsigned u1SS : 1;
352	/** Bit 28 - HTT - Hyper-Threading Technology. */
353	unsigned u1HTT : 1;
354	/** Bit 29 - TM - Thermal Monitor. */
355	unsigned u1TM : 1;
356	/** Bit 30 - Reserved - . */
357	unsigned u1Reserved3 : 1;
358	/** Bit 31 - PBE - Pending Break Enabled. */
359	unsigned u1PBE : 1;
360	} X86CPUIDFEATEDX;
361	#else /* VBOX_FOR_DTRACE_LIB */
362	typedef uint32_t X86CPUIDFEATEDX;
363	#endif /* VBOX_FOR_DTRACE_LIB */
364	/** Pointer to CPUID Feature Information - EDX. */
365	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
366	/** Pointer to const CPUID Feature Information - EDX. */
367	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
368
369	/** @name CPUID Vendor information.
370	* CPUID query with EAX=0.
371	* @{
372	*/
373	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
374	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
375	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
376
377	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
378	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
379	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
380
381	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
382	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
383	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
384	/** @} */
385
386
387	/** @name CPUID Feature information.
388	* CPUID query with EAX=1.
389	* @{
390	*/
391	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
392	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
393	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
394	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
395	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
396	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
397	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
398	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
399	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
400	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
401	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
402	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
403	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
404	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
405	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
406	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
407	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
408	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
409	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
410	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
411	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
412	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
413	/** ECX Bit 12 - FMA. */
414	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
415	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
416	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
417	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
418	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
419	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
420	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
421	/** ECX Bit 17 - PCID - Process-context identifiers. */
422	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
423	/** ECX Bit 18 - DCA - Direct Cache Access. */
424	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
425	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
426	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
427	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
428	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
429	/** ECX Bit 21 - x2APIC support. */
430	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
431	/** ECX Bit 22 - MOVBE instruction. */
432	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
433	/** ECX Bit 23 - POPCNT instruction. */
434	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
435	/** ECX Bir 24 - TSC-Deadline. */
436	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
437	/** ECX Bit 25 - AES instructions. */
438	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
439	/** ECX Bit 26 - XSAVE instruction. */
440	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
441	/** ECX Bit 27 - OSXSAVE instruction. */
442	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
443	/** ECX Bit 28 - AVX. */
444	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
445	/** ECX Bit 31 - Hypervisor Present (software only). */
446	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
447
448
449	/** Bit 0 - FPU - x87 FPU on Chip. */
450	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
451	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
452	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
453	/** Bit 2 - DE - Debugging extensions. */
454	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
455	/** Bit 3 - PSE - Page Size Extension. */
456	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
457	/** Bit 4 - TSC - Time Stamp Counter. */
458	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
459	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
460	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
461	/** Bit 6 - PAE - Physical Address Extension. */
462	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
463	/** Bit 7 - MCE - Machine Check Exception. */
464	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
465	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
466	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
467	/** Bit 9 - APIC - APIC On-Chip. */
468	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
469	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
470	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
471	/** Bit 12 - MTRR - Memory Type Range Registers. */
472	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
473	/** Bit 13 - PGE - PTE Global Bit. */
474	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
475	/** Bit 14 - MCA - Machine Check Architecture. */
476	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
477	/** Bit 15 - CMOV - Conditional Move Instructions. */
478	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
479	/** Bit 16 - PAT - Page Attribute Table. */
480	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
481	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
482	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
483	/** Bit 18 - PSN - Processor Serial Number. */
484	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
485	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
486	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
487	/** Bit 21 - DS - Debug Store. */
488	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
489	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
490	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
491	/** Bit 23 - MMX - Intel MMX Technology. */
492	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
493	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
494	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
495	/** Bit 25 - SSE - SSE Support. */
496	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
497	/** Bit 26 - SSE2 - SSE2 Support. */
498	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
499	/** Bit 27 - SS - Self Snoop. */
500	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
501	/** Bit 28 - HTT - Hyper-Threading Technology. */
502	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
503	/** Bit 29 - TM - Therm. Monitor. */
504	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
505	/** Bit 31 - PBE - Pending Break Enabled. */
506	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
507	/** @} */
508
509	/** @name CPUID mwait/monitor information.
510	* CPUID query with EAX=5.
511	* @{
512	*/
513	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
514	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
515	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
516	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
517	/** @} */
518
519
520	/** @name CPUID Extended Feature information.
521	* CPUID query with EAX=0x80000001.
522	* @{
523	*/
524	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
525	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
526
527	/** EDX Bit 11 - SYSCALL/SYSRET. */
528	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
529	/** EDX Bit 20 - No-Execute/Execute-Disable. */
530	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
531	/** EDX Bit 26 - 1 GB large page. */
532	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
533	/** EDX Bit 27 - RDTSCP. */
534	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
535	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
536	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
537	/** @}*/
538
539	/** @name CPUID AMD Feature information.
540	* CPUID query with EAX=0x80000001.
541	* @{
542	*/
543	/** Bit 0 - FPU - x87 FPU on Chip. */
544	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
545	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
546	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
547	/** Bit 2 - DE - Debugging extensions. */
548	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
549	/** Bit 3 - PSE - Page Size Extension. */
550	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
551	/** Bit 4 - TSC - Time Stamp Counter. */
552	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
553	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
554	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
555	/** Bit 6 - PAE - Physical Address Extension. */
556	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
557	/** Bit 7 - MCE - Machine Check Exception. */
558	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
559	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
560	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
561	/** Bit 9 - APIC - APIC On-Chip. */
562	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
563	/** Bit 12 - MTRR - Memory Type Range Registers. */
564	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
565	/** Bit 13 - PGE - PTE Global Bit. */
566	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
567	/** Bit 14 - MCA - Machine Check Architecture. */
568	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
569	/** Bit 15 - CMOV - Conditional Move Instructions. */
570	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
571	/** Bit 16 - PAT - Page Attribute Table. */
572	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
573	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
574	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
575	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
576	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
577	/** Bit 23 - MMX - Intel MMX Technology. */
578	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
579	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
580	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
581	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
582	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
583	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
584	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
585	/** Bit 31 - 3DNOW - AMD 3DNow. */
586	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
587
588	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
589	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
590	/** Bit 2 - SVM - AMD VM extensions. */
591	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
592	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
593	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
594	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
595	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
596	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
597	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
598	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
599	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
600	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
601	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
602	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
603	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
604	/** Bit 9 - OSVW - AMD OS visible workaround. */
605	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
606	/** Bit 10 - IBS - Instruct based sampling. */
607	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
608	/** Bit 11 - SSE5 - SSE5 instruction support. */
609	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
610	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
611	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
612	/** Bit 13 - WDT - AMD Watchdog timer support. */
613	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
614
615	/** @} */
616
617
618	/** @name CPUID AMD Feature information.
619	* CPUID query with EAX=0x80000007.
620	* @{
621	*/
622	/** Bit 0 - TS - Temperature Sensor. */
623	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
624	/** Bit 1 - FID - Frequency ID Control. */
625	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
626	/** Bit 2 - VID - Voltage ID Control. */
627	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
628	/** Bit 3 - TTP - THERMTRIP. */
629	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
630	/** Bit 4 - TM - Hardware Thermal Control. */
631	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
632	/** Bit 5 - STC - Software Thermal Control. */
633	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
634	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
635	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
636	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
637	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
638	/** Bit 8 - TSCINVAR - TSC Invariant. */
639	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
640	/** @} */
641
642
643	/** @name CR0
644	* @{ */
645	/** Bit 0 - PE - Protection Enabled */
646	#define X86_CR0_PE RT_BIT(0)
647	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
648	/** Bit 1 - MP - Monitor Coprocessor */
649	#define X86_CR0_MP RT_BIT(1)
650	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
651	/** Bit 2 - EM - Emulation. */
652	#define X86_CR0_EM RT_BIT(2)
653	#define X86_CR0_EMULATE_FPU RT_BIT(2)
654	/** Bit 3 - TS - Task Switch. */
655	#define X86_CR0_TS RT_BIT(3)
656	#define X86_CR0_TASK_SWITCH RT_BIT(3)
657	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
658	#define X86_CR0_ET RT_BIT(4)
659	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
660	/** Bit 5 - NE - Numeric error. */
661	#define X86_CR0_NE RT_BIT(5)
662	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
663	/** Bit 16 - WP - Write Protect. */
664	#define X86_CR0_WP RT_BIT(16)
665	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
666	/** Bit 18 - AM - Alignment Mask. */
667	#define X86_CR0_AM RT_BIT(18)
668	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
669	/** Bit 29 - NW - Not Write-though. */
670	#define X86_CR0_NW RT_BIT(29)
671	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
672	/** Bit 30 - WP - Cache Disable. */
673	#define X86_CR0_CD RT_BIT(30)
674	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
675	/** Bit 31 - PG - Paging. */
676	#define X86_CR0_PG RT_BIT(31)
677	#define X86_CR0_PAGING RT_BIT(31)
678	/** @} */
679
680
681	/** @name CR3
682	* @{ */
683	/** Bit 3 - PWT - Page-level Writes Transparent. */
684	#define X86_CR3_PWT RT_BIT(3)
685	/** Bit 4 - PCD - Page-level Cache Disable. */
686	#define X86_CR3_PCD RT_BIT(4)
687	/** Bits 12-31 - - Page directory page number. */
688	#define X86_CR3_PAGE_MASK (0xfffff000)
689	/** Bits 5-31 - - PAE Page directory page number. */
690	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
691	/** Bits 12-51 - - AMD64 Page directory page number. */
692	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
693	/** @} */
694
695
696	/** @name CR4
697	* @{ */
698	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
699	#define X86_CR4_VME RT_BIT(0)
700	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
701	#define X86_CR4_PVI RT_BIT(1)
702	/** Bit 2 - TSD - Time Stamp Disable. */
703	#define X86_CR4_TSD RT_BIT(2)
704	/** Bit 3 - DE - Debugging Extensions. */
705	#define X86_CR4_DE RT_BIT(3)
706	/** Bit 4 - PSE - Page Size Extension. */
707	#define X86_CR4_PSE RT_BIT(4)
708	/** Bit 5 - PAE - Physical Address Extension. */
709	#define X86_CR4_PAE RT_BIT(5)
710	/** Bit 6 - MCE - Machine-Check Enable. */
711	#define X86_CR4_MCE RT_BIT(6)
712	/** Bit 7 - PGE - Page Global Enable. */
713	#define X86_CR4_PGE RT_BIT(7)
714	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
715	#define X86_CR4_PCE RT_BIT(8)
716	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
717	#define X86_CR4_OSFSXR RT_BIT(9)
718	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
719	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
720	/** Bit 13 - VMXE - VMX mode is enabled. */
721	#define X86_CR4_VMXE RT_BIT(13)
722	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
723	#define X86_CR4_SMXE RT_BIT(14)
724	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
725	#define X86_CR4_PCIDE RT_BIT(17)
726	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
727	* extended states. */
728	#define X86_CR4_OSXSAVE RT_BIT(18)
729	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
730	#define X86_CR4_SMEP RT_BIT(20)
731	/** @} */
732
733
734	/** @name DR6
735	* @{ */
736	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
737	#define X86_DR6_B0 RT_BIT(0)
738	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
739	#define X86_DR6_B1 RT_BIT(1)
740	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
741	#define X86_DR6_B2 RT_BIT(2)
742	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
743	#define X86_DR6_B3 RT_BIT(3)
744	/** Mask of all the Bx bits. */
745	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
746	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
747	#define X86_DR6_BD RT_BIT(13)
748	/** Bit 14 - BS - Single step */
749	#define X86_DR6_BS RT_BIT(14)
750	/** Bit 15 - BT - Task switch. (TSS T bit.) */
751	#define X86_DR6_BT RT_BIT(15)
752	/** Value of DR6 after powerup/reset. */
753	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
754	/** Bits which must be 1s in DR6. */
755	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
756	/** Bits which must be 0s in DR6. */
757	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
758	/** Bits which must be 0s on writes to DR6. */
759	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
760	/** @} */
761
762	/** Get the DR6.Bx bit for a the given breakpoint. */
763	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
764
765
766	/** @name DR7
767	* @{ */
768	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
769	#define X86_DR7_L0 RT_BIT(0)
770	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
771	#define X86_DR7_G0 RT_BIT(1)
772	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
773	#define X86_DR7_L1 RT_BIT(2)
774	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
775	#define X86_DR7_G1 RT_BIT(3)
776	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
777	#define X86_DR7_L2 RT_BIT(4)
778	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
779	#define X86_DR7_G2 RT_BIT(5)
780	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
781	#define X86_DR7_L3 RT_BIT(6)
782	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
783	#define X86_DR7_G3 RT_BIT(7)
784	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
785	#define X86_DR7_LE RT_BIT(8)
786	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
787	#define X86_DR7_GE RT_BIT(9)
788
789	/** L0, L1, L2, and L3. */
790	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
791	/** L0, L1, L2, and L3. */
792	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
793
794	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
795	* any DR register is accessed. */
796	#define X86_DR7_GD RT_BIT(13)
797	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
798	#define X86_DR7_RW0_MASK (3 << 16)
799	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
800	#define X86_DR7_LEN0_MASK (3 << 18)
801	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
802	#define X86_DR7_RW1_MASK (3 << 20)
803	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
804	#define X86_DR7_LEN1_MASK (3 << 22)
805	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
806	#define X86_DR7_RW2_MASK (3 << 24)
807	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
808	#define X86_DR7_LEN2_MASK (3 << 26)
809	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
810	#define X86_DR7_RW3_MASK (3 << 28)
811	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
812	#define X86_DR7_LEN3_MASK (3 << 30)
813
814	/** Bits which reads as 1s. */
815	#define X86_DR7_RA1_MASK (RT_BIT(10))
816	/** Bits which reads as zeros. */
817	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
818	/** Bits which must be 0s when writing to DR7. */
819	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
820
821	/** Calcs the L bit of Nth breakpoint.
822	* @param iBp The breakpoint number [0..3].
823	*/
824	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
825
826	/** Calcs the G bit of Nth breakpoint.
827	* @param iBp The breakpoint number [0..3].
828	*/
829	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
830
831	/** Calcs the L and G bits of Nth breakpoint.
832	* @param iBp The breakpoint number [0..3].
833	*/
834	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
835
836	/** @name Read/Write values.
837	* @{ */
838	/** Break on instruction fetch only. */
839	#define X86_DR7_RW_EO 0U
840	/** Break on write only. */
841	#define X86_DR7_RW_WO 1U
842	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
843	#define X86_DR7_RW_IO 2U
844	/** Break on read or write (but not instruction fetches). */
845	#define X86_DR7_RW_RW 3U
846	/** @} */
847
848	/** Shifts a X86_DR7_RW_* value to its right place.
849	* @param iBp The breakpoint number [0..3].
850	* @param fRw One of the X86_DR7_RW_* value.
851	*/
852	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
853
854	/** Fetch the the R/Wx bits for a given breakpoint (so it can be compared with
855	* one of the X86_DR7_RW_XXX constants).
856	*
857	* @returns X86_DR7_RW_XXX
858	* @param uDR7 DR7 value
859	* @param iBp The breakpoint number [0..3].
860	*/
861	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
862
863	/** R/W0, R/W1, R/W2, and R/W3. */
864	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
865
866	/** Checks if there are any I/O breakpoint types configured in the RW
867	* registers. Does NOT check if these are enabled, sorry. */
868	#define X86_DR7_ANY_RW_IO(uDR7) \
869	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
870	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
871	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
872	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
873	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
874	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
875	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
876	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
877	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
878	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
879	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
880
881	/** @name Length values.
882	* @{ */
883	#define X86_DR7_LEN_BYTE 0U
884	#define X86_DR7_LEN_WORD 1U
885	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
886	#define X86_DR7_LEN_DWORD 3U
887	/** @} */
888
889	/** Shifts a X86_DR7_LEN_* value to its right place.
890	* @param iBp The breakpoint number [0..3].
891	* @param cb One of the X86_DR7_LEN_* values.
892	*/
893	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
894
895	/** Fetch the breakpoint length bits from the DR7 value.
896	* @param uDR7 DR7 value
897	* @param iBp The breakpoint number [0..3].
898	*/
899	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
900
901	/** Mask used to check if any breakpoints are enabled. */
902	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
903
904	/** LEN0, LEN1, LEN2, and LEN3. */
905	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
906	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
907	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
908
909	/** Value of DR7 after powerup/reset. */
910	#define X86_DR7_INIT_VAL 0x400
911	/** @} */
912
913
914	/** @name Machine Specific Registers
915	* @{
916	*/
917
918	/** Time Stamp Counter. */
919	#define MSR_IA32_TSC 0x10
920
921	#define MSR_IA32_PLATFORM_ID 0x17
922
923	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
924	#define MSR_IA32_APICBASE 0x1b
925	#endif
926
927	/** CPU Feature control. */
928	#define MSR_IA32_FEATURE_CONTROL 0x3A
929	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
930	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
931
932	/** BIOS update trigger (microcode update). */
933	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
934
935	/** BIOS update signature (microcode). */
936	#define MSR_IA32_BIOS_SIGN_ID 0x8B
937
938	/** General performance counter no. 0. */
939	#define MSR_IA32_PMC0 0xC1
940	/** General performance counter no. 1. */
941	#define MSR_IA32_PMC1 0xC2
942	/** General performance counter no. 2. */
943	#define MSR_IA32_PMC2 0xC3
944	/** General performance counter no. 3. */
945	#define MSR_IA32_PMC3 0xC4
946
947	/** Nehalem power control. */
948	#define MSR_IA32_PLATFORM_INFO 0xCE
949
950	/** Get FSB clock status (Intel-specific). */
951	#define MSR_IA32_FSB_CLOCK_STS 0xCD
952
953	/** MTRR Capabilities. */
954	#define MSR_IA32_MTRR_CAP 0xFE
955
956
957	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
958	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
959	* R0 SS == CS + 8
960	* R3 CS == CS + 16
961	* R3 SS == CS + 24
962	*/
963	#define MSR_IA32_SYSENTER_CS 0x174
964	/** SYSENTER_ESP - the R0 ESP. */
965	#define MSR_IA32_SYSENTER_ESP 0x175
966	/** SYSENTER_EIP - the R0 EIP. */
967	#define MSR_IA32_SYSENTER_EIP 0x176
968	#endif
969
970	/** Machine Check Global Capabilities Register. */
971	#define MSR_IA32_MCP_CAP 0x179
972	/** Machine Check Global Status Register. */
973	#define MSR_IA32_MCP_STATUS 0x17A
974	/** Machine Check Global Control Register. */
975	#define MSR_IA32_MCP_CTRL 0x17B
976
977	/** Trace/Profile Resource Control (R/W) */
978	#define MSR_IA32_DEBUGCTL 0x1D9
979
980	/** Page Attribute Table. */
981	#define MSR_IA32_CR_PAT 0x277
982
983	/** Performance counter MSRs. (Intel only) */
984	#define MSR_IA32_PERFEVTSEL0 0x186
985	#define MSR_IA32_PERFEVTSEL1 0x187
986	#define MSR_IA32_FLEX_RATIO 0x194
987	#define MSR_IA32_PERF_STATUS 0x198
988	#define MSR_IA32_PERF_CTL 0x199
989	#define MSR_IA32_THERM_STATUS 0x19c
990
991	/** Enable misc. processor features (R/W). */
992	#define MSR_IA32_MISC_ENABLE 0x1A0
993	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
994	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
995	/** Automatic Thermal Control Circuit Enable (R/W). */
996	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
997	/** Performance Monitoring Available (R). */
998	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
999	/** Branch Trace Storage Unavailable (R/O). */
1000	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
1001	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1002	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
1003	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1004	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
1005	/** If MONITOR/MWAIT is supported (R/W). */
1006	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
1007	/** Limit CPUID Maxval to 3 leafs (R/W). */
1008	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
1009	/** When set to 1, xTPR messages are disabled (R/W). */
1010	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
1011	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1012	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
1013
1014	#define IA32_MTRR_PHYSBASE0 0x200
1015	#define IA32_MTRR_PHYSMASK0 0x201
1016	#define IA32_MTRR_PHYSBASE1 0x202
1017	#define IA32_MTRR_PHYSMASK1 0x203
1018	#define IA32_MTRR_PHYSBASE2 0x204
1019	#define IA32_MTRR_PHYSMASK2 0x205
1020	#define IA32_MTRR_PHYSBASE3 0x206
1021	#define IA32_MTRR_PHYSMASK3 0x207
1022	#define IA32_MTRR_PHYSBASE4 0x208
1023	#define IA32_MTRR_PHYSMASK4 0x209
1024	#define IA32_MTRR_PHYSBASE5 0x20a
1025	#define IA32_MTRR_PHYSMASK5 0x20b
1026	#define IA32_MTRR_PHYSBASE6 0x20c
1027	#define IA32_MTRR_PHYSMASK6 0x20d
1028	#define IA32_MTRR_PHYSBASE7 0x20e
1029	#define IA32_MTRR_PHYSMASK7 0x20f
1030	#define IA32_MTRR_PHYSBASE8 0x210
1031	#define IA32_MTRR_PHYSMASK8 0x211
1032	#define IA32_MTRR_PHYSBASE9 0x212
1033	#define IA32_MTRR_PHYSMASK9 0x213
1034
1035	/** Fixed range MTRRs.
1036	* @{ */
1037	#define IA32_MTRR_FIX64K_00000 0x250
1038	#define IA32_MTRR_FIX16K_80000 0x258
1039	#define IA32_MTRR_FIX16K_A0000 0x259
1040	#define IA32_MTRR_FIX4K_C0000 0x268
1041	#define IA32_MTRR_FIX4K_C8000 0x269
1042	#define IA32_MTRR_FIX4K_D0000 0x26a
1043	#define IA32_MTRR_FIX4K_D8000 0x26b
1044	#define IA32_MTRR_FIX4K_E0000 0x26c
1045	#define IA32_MTRR_FIX4K_E8000 0x26d
1046	#define IA32_MTRR_FIX4K_F0000 0x26e
1047	#define IA32_MTRR_FIX4K_F8000 0x26f
1048	/** @} */
1049
1050	/** MTRR Default Range. */
1051	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1052
1053	#define MSR_IA32_MC0_CTL 0x400
1054	#define MSR_IA32_MC0_STATUS 0x401
1055
1056	/** Basic VMX information. */
1057	#define MSR_IA32_VMX_BASIC_INFO 0x480
1058	/** Allowed settings for pin-based VM execution controls */
1059	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1060	/** Allowed settings for proc-based VM execution controls */
1061	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1062	/** Allowed settings for the VMX exit controls. */
1063	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1064	/** Allowed settings for the VMX entry controls. */
1065	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1066	/** Misc VMX info. */
1067	#define MSR_IA32_VMX_MISC 0x485
1068	/** Fixed cleared bits in CR0. */
1069	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1070	/** Fixed set bits in CR0. */
1071	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1072	/** Fixed cleared bits in CR4. */
1073	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1074	/** Fixed set bits in CR4. */
1075	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1076	/** Information for enumerating fields in the VMCS. */
1077	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1078	/** Allowed settings for the VM-functions controls. */
1079	#define MSR_IA32_VMX_VMFUNC 0x491
1080	/** Allowed settings for secondary proc-based VM execution controls */
1081	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1082	/** EPT capabilities. */
1083	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1084	/** DS Save Area (R/W). */
1085	#define MSR_IA32_DS_AREA 0x600
1086	/** X2APIC MSR ranges. */
1087	#define MSR_IA32_X2APIC_START 0x800
1088	#define MSR_IA32_X2APIC_TPR 0x808
1089	#define MSR_IA32_X2APIC_END 0xBFF
1090
1091	/** K6 EFER - Extended Feature Enable Register. */
1092	#define MSR_K6_EFER 0xc0000080
1093	/** @todo document EFER */
1094	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1095	#define MSR_K6_EFER_SCE RT_BIT(0)
1096	/** Bit 8 - LME - Long mode enabled. (R/W) */
1097	#define MSR_K6_EFER_LME RT_BIT(8)
1098	/** Bit 10 - LMA - Long mode active. (R) */
1099	#define MSR_K6_EFER_LMA RT_BIT(10)
1100	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1101	#define MSR_K6_EFER_NXE RT_BIT(11)
1102	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1103	#define MSR_K6_EFER_SVME RT_BIT(12)
1104	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1105	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1106	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1107	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1108	/** K6 STAR - SYSCALL/RET targets. */
1109	#define MSR_K6_STAR 0xc0000081
1110	/** Shift value for getting the SYSRET CS and SS value. */
1111	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1112	/** Shift value for getting the SYSCALL CS and SS value. */
1113	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1114	/** Selector mask for use after shifting. */
1115	#define MSR_K6_STAR_SEL_MASK 0xffff
1116	/** The mask which give the SYSCALL EIP. */
1117	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1118	/** K6 WHCR - Write Handling Control Register. */
1119	#define MSR_K6_WHCR 0xc0000082
1120	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1121	#define MSR_K6_UWCCR 0xc0000085
1122	/** K6 PSOR - Processor State Observability Register. */
1123	#define MSR_K6_PSOR 0xc0000087
1124	/** K6 PFIR - Page Flush/Invalidate Register. */
1125	#define MSR_K6_PFIR 0xc0000088
1126
1127	/** Performance counter MSRs. (AMD only) */
1128	#define MSR_K7_EVNTSEL0 0xc0010000
1129	#define MSR_K7_EVNTSEL1 0xc0010001
1130	#define MSR_K7_EVNTSEL2 0xc0010002
1131	#define MSR_K7_EVNTSEL3 0xc0010003
1132	#define MSR_K7_PERFCTR0 0xc0010004
1133	#define MSR_K7_PERFCTR1 0xc0010005
1134	#define MSR_K7_PERFCTR2 0xc0010006
1135	#define MSR_K7_PERFCTR3 0xc0010007
1136
1137	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1138	#define MSR_K8_LSTAR 0xc0000082
1139	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1140	#define MSR_K8_CSTAR 0xc0000083
1141	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1142	#define MSR_K8_SF_MASK 0xc0000084
1143	/** K8 FS.base - The 64-bit base FS register. */
1144	#define MSR_K8_FS_BASE 0xc0000100
1145	/** K8 GS.base - The 64-bit base GS register. */
1146	#define MSR_K8_GS_BASE 0xc0000101
1147	/** K8 KernelGSbase - Used with SWAPGS. */
1148	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1149	/** K8 TSC_AUX - Used with RDTSCP. */
1150	#define MSR_K8_TSC_AUX 0xc0000103
1151	#define MSR_K8_SYSCFG 0xc0010010
1152	#define MSR_K8_HWCR 0xc0010015
1153	#define MSR_K8_IORRBASE0 0xc0010016
1154	#define MSR_K8_IORRMASK0 0xc0010017
1155	#define MSR_K8_IORRBASE1 0xc0010018
1156	#define MSR_K8_IORRMASK1 0xc0010019
1157	#define MSR_K8_TOP_MEM1 0xc001001a
1158	#define MSR_K8_TOP_MEM2 0xc001001d
1159	#define MSR_K8_VM_CR 0xc0010114
1160	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1161
1162	#define MSR_K8_IGNNE 0xc0010115
1163	#define MSR_K8_SMM_CTL 0xc0010116
1164	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1165	* host state during world switch.
1166	*/
1167	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1168
1169	/** @} */
1170
1171
1172	/** @name Page Table / Directory / Directory Pointers / L4.
1173	* @{
1174	*/
1175
1176	/** Page table/directory entry as an unsigned integer. */
1177	typedef uint32_t X86PGUINT;
1178	/** Pointer to a page table/directory table entry as an unsigned integer. */
1179	typedef X86PGUINT *PX86PGUINT;
1180	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1181	typedef X86PGUINT const *PCX86PGUINT;
1182
1183	/** Number of entries in a 32-bit PT/PD. */
1184	#define X86_PG_ENTRIES 1024
1185
1186
1187	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1188	typedef uint64_t X86PGPAEUINT;
1189	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1190	typedef X86PGPAEUINT *PX86PGPAEUINT;
1191	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1192	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1193
1194	/** Number of entries in a PAE PT/PD. */
1195	#define X86_PG_PAE_ENTRIES 512
1196	/** Number of entries in a PAE PDPT. */
1197	#define X86_PG_PAE_PDPE_ENTRIES 4
1198
1199	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1200	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1201	/** Number of entries in an AMD64 PDPT.
1202	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1203	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1204
1205	/** The size of a 4KB page. */
1206	#define X86_PAGE_4K_SIZE _4K
1207	/** The page shift of a 4KB page. */
1208	#define X86_PAGE_4K_SHIFT 12
1209	/** The 4KB page offset mask. */
1210	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1211	/** The 4KB page base mask for virtual addresses. */
1212	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1213	/** The 4KB page base mask for virtual addresses - 32bit version. */
1214	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1215
1216	/** The size of a 2MB page. */
1217	#define X86_PAGE_2M_SIZE _2M
1218	/** The page shift of a 2MB page. */
1219	#define X86_PAGE_2M_SHIFT 21
1220	/** The 2MB page offset mask. */
1221	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1222	/** The 2MB page base mask for virtual addresses. */
1223	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1224	/** The 2MB page base mask for virtual addresses - 32bit version. */
1225	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1226
1227	/** The size of a 4MB page. */
1228	#define X86_PAGE_4M_SIZE _4M
1229	/** The page shift of a 4MB page. */
1230	#define X86_PAGE_4M_SHIFT 22
1231	/** The 4MB page offset mask. */
1232	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1233	/** The 4MB page base mask for virtual addresses. */
1234	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1235	/** The 4MB page base mask for virtual addresses - 32bit version. */
1236	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1237
1238
1239
1240	/** @name Page Table Entry
1241	* @{
1242	*/
1243	/** Bit 0 - P - Present bit. */
1244	#define X86_PTE_BIT_P 0
1245	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1246	#define X86_PTE_BIT_RW 1
1247	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1248	#define X86_PTE_BIT_US 2
1249	/** Bit 3 - PWT - Page level write thru bit. */
1250	#define X86_PTE_BIT_PWT 3
1251	/** Bit 4 - PCD - Page level cache disable bit. */
1252	#define X86_PTE_BIT_PCD 4
1253	/** Bit 5 - A - Access bit. */
1254	#define X86_PTE_BIT_A 5
1255	/** Bit 6 - D - Dirty bit. */
1256	#define X86_PTE_BIT_D 6
1257	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1258	#define X86_PTE_BIT_PAT 7
1259	/** Bit 8 - G - Global flag. */
1260	#define X86_PTE_BIT_G 8
1261
1262	/** Bit 0 - P - Present bit mask. */
1263	#define X86_PTE_P RT_BIT(0)
1264	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1265	#define X86_PTE_RW RT_BIT(1)
1266	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1267	#define X86_PTE_US RT_BIT(2)
1268	/** Bit 3 - PWT - Page level write thru bit mask. */
1269	#define X86_PTE_PWT RT_BIT(3)
1270	/** Bit 4 - PCD - Page level cache disable bit mask. */
1271	#define X86_PTE_PCD RT_BIT(4)
1272	/** Bit 5 - A - Access bit mask. */
1273	#define X86_PTE_A RT_BIT(5)
1274	/** Bit 6 - D - Dirty bit mask. */
1275	#define X86_PTE_D RT_BIT(6)
1276	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1277	#define X86_PTE_PAT RT_BIT(7)
1278	/** Bit 8 - G - Global bit mask. */
1279	#define X86_PTE_G RT_BIT(8)
1280
1281	/** Bits 9-11 - - Available for use to system software. */
1282	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1283	/** Bits 12-31 - - Physical Page number of the next level. */
1284	#define X86_PTE_PG_MASK ( 0xfffff000 )
1285
1286	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1287	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1288	/** Bits 63 - NX - PAE/LM - No execution flag. */
1289	#define X86_PTE_PAE_NX RT_BIT_64(63)
1290	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1291	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1292	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1293	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1294	/** No bits - - LM - MBZ bits when NX is active. */
1295	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1296	/** Bits 63 - - LM - MBZ bits when no NX. */
1297	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1298
1299	/**
1300	* Page table entry.
1301	*/
1302	typedef struct X86PTEBITS
1303	{
1304	/** Flags whether(=1) or not the page is present. */
1305	unsigned u1Present : 1;
1306	/** Read(=0) / Write(=1) flag. */
1307	unsigned u1Write : 1;
1308	/** User(=1) / Supervisor (=0) flag. */
1309	unsigned u1User : 1;
1310	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1311	unsigned u1WriteThru : 1;
1312	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1313	unsigned u1CacheDisable : 1;
1314	/** Accessed flag.
1315	* Indicates that the page have been read or written to. */
1316	unsigned u1Accessed : 1;
1317	/** Dirty flag.
1318	* Indicates that the page has been written to. */
1319	unsigned u1Dirty : 1;
1320	/** Reserved / If PAT enabled, bit 2 of the index. */
1321	unsigned u1PAT : 1;
1322	/** Global flag. (Ignored in all but final level.) */
1323	unsigned u1Global : 1;
1324	/** Available for use to system software. */
1325	unsigned u3Available : 3;
1326	/** Physical Page number of the next level. */
1327	unsigned u20PageNo : 20;
1328	} X86PTEBITS;
1329	/** Pointer to a page table entry. */
1330	typedef X86PTEBITS *PX86PTEBITS;
1331	/** Pointer to a const page table entry. */
1332	typedef const X86PTEBITS *PCX86PTEBITS;
1333
1334	/**
1335	* Page table entry.
1336	*/
1337	typedef union X86PTE
1338	{
1339	/** Unsigned integer view */
1340	X86PGUINT u;
1341	/** Bit field view. */
1342	X86PTEBITS n;
1343	/** 32-bit view. */
1344	uint32_t au32[1];
1345	/** 16-bit view. */
1346	uint16_t au16[2];
1347	/** 8-bit view. */
1348	uint8_t au8[4];
1349	} X86PTE;
1350	/** Pointer to a page table entry. */
1351	typedef X86PTE *PX86PTE;
1352	/** Pointer to a const page table entry. */
1353	typedef const X86PTE *PCX86PTE;
1354
1355
1356	/**
1357	* PAE page table entry.
1358	*/
1359	typedef struct X86PTEPAEBITS
1360	{
1361	/** Flags whether(=1) or not the page is present. */
1362	uint32_t u1Present : 1;
1363	/** Read(=0) / Write(=1) flag. */
1364	uint32_t u1Write : 1;
1365	/** User(=1) / Supervisor(=0) flag. */
1366	uint32_t u1User : 1;
1367	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1368	uint32_t u1WriteThru : 1;
1369	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1370	uint32_t u1CacheDisable : 1;
1371	/** Accessed flag.
1372	* Indicates that the page have been read or written to. */
1373	uint32_t u1Accessed : 1;
1374	/** Dirty flag.
1375	* Indicates that the page has been written to. */
1376	uint32_t u1Dirty : 1;
1377	/** Reserved / If PAT enabled, bit 2 of the index. */
1378	uint32_t u1PAT : 1;
1379	/** Global flag. (Ignored in all but final level.) */
1380	uint32_t u1Global : 1;
1381	/** Available for use to system software. */
1382	uint32_t u3Available : 3;
1383	/** Physical Page number of the next level - Low Part. Don't use this. */
1384	uint32_t u20PageNoLow : 20;
1385	/** Physical Page number of the next level - High Part. Don't use this. */
1386	uint32_t u20PageNoHigh : 20;
1387	/** MBZ bits */
1388	uint32_t u11Reserved : 11;
1389	/** No Execute flag. */
1390	uint32_t u1NoExecute : 1;
1391	} X86PTEPAEBITS;
1392	/** Pointer to a page table entry. */
1393	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1394	/** Pointer to a page table entry. */
1395	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1396
1397	/**
1398	* PAE Page table entry.
1399	*/
1400	typedef union X86PTEPAE
1401	{
1402	/** Unsigned integer view */
1403	X86PGPAEUINT u;
1404	/** Bit field view. */
1405	X86PTEPAEBITS n;
1406	/** 32-bit view. */
1407	uint32_t au32[2];
1408	/** 16-bit view. */
1409	uint16_t au16[4];
1410	/** 8-bit view. */
1411	uint8_t au8[8];
1412	} X86PTEPAE;
1413	/** Pointer to a PAE page table entry. */
1414	typedef X86PTEPAE *PX86PTEPAE;
1415	/** Pointer to a const PAE page table entry. */
1416	typedef const X86PTEPAE *PCX86PTEPAE;
1417	/** @} */
1418
1419	/**
1420	* Page table.
1421	*/
1422	typedef struct X86PT
1423	{
1424	/** PTE Array. */
1425	X86PTE a[X86_PG_ENTRIES];
1426	} X86PT;
1427	/** Pointer to a page table. */
1428	typedef X86PT *PX86PT;
1429	/** Pointer to a const page table. */
1430	typedef const X86PT *PCX86PT;
1431
1432	/** The page shift to get the PT index. */
1433	#define X86_PT_SHIFT 12
1434	/** The PT index mask (apply to a shifted page address). */
1435	#define X86_PT_MASK 0x3ff
1436
1437
1438	/**
1439	* Page directory.
1440	*/
1441	typedef struct X86PTPAE
1442	{
1443	/** PTE Array. */
1444	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1445	} X86PTPAE;
1446	/** Pointer to a page table. */
1447	typedef X86PTPAE *PX86PTPAE;
1448	/** Pointer to a const page table. */
1449	typedef const X86PTPAE *PCX86PTPAE;
1450
1451	/** The page shift to get the PA PTE index. */
1452	#define X86_PT_PAE_SHIFT 12
1453	/** The PAE PT index mask (apply to a shifted page address). */
1454	#define X86_PT_PAE_MASK 0x1ff
1455
1456
1457	/** @name 4KB Page Directory Entry
1458	* @{
1459	*/
1460	/** Bit 0 - P - Present bit. */
1461	#define X86_PDE_P RT_BIT(0)
1462	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1463	#define X86_PDE_RW RT_BIT(1)
1464	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1465	#define X86_PDE_US RT_BIT(2)
1466	/** Bit 3 - PWT - Page level write thru bit. */
1467	#define X86_PDE_PWT RT_BIT(3)
1468	/** Bit 4 - PCD - Page level cache disable bit. */
1469	#define X86_PDE_PCD RT_BIT(4)
1470	/** Bit 5 - A - Access bit. */
1471	#define X86_PDE_A RT_BIT(5)
1472	/** Bit 7 - PS - Page size attribute.
1473	* Clear mean 4KB pages, set means large pages (2/4MB). */
1474	#define X86_PDE_PS RT_BIT(7)
1475	/** Bits 9-11 - - Available for use to system software. */
1476	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1477	/** Bits 12-31 - - Physical Page number of the next level. */
1478	#define X86_PDE_PG_MASK ( 0xfffff000 )
1479
1480	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1481	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1482	/** Bits 63 - NX - PAE/LM - No execution flag. */
1483	#define X86_PDE_PAE_NX RT_BIT_64(63)
1484	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1485	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1486	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1487	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1488	/** Bit 7 - - LM - MBZ bits when NX is active. */
1489	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1490	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1491	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1492
1493	/**
1494	* Page directory entry.
1495	*/
1496	typedef struct X86PDEBITS
1497	{
1498	/** Flags whether(=1) or not the page is present. */
1499	unsigned u1Present : 1;
1500	/** Read(=0) / Write(=1) flag. */
1501	unsigned u1Write : 1;
1502	/** User(=1) / Supervisor (=0) flag. */
1503	unsigned u1User : 1;
1504	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1505	unsigned u1WriteThru : 1;
1506	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1507	unsigned u1CacheDisable : 1;
1508	/** Accessed flag.
1509	* Indicates that the page has been read or written to. */
1510	unsigned u1Accessed : 1;
1511	/** Reserved / Ignored (dirty bit). */
1512	unsigned u1Reserved0 : 1;
1513	/** Size bit if PSE is enabled - in any event it's 0. */
1514	unsigned u1Size : 1;
1515	/** Reserved / Ignored (global bit). */
1516	unsigned u1Reserved1 : 1;
1517	/** Available for use to system software. */
1518	unsigned u3Available : 3;
1519	/** Physical Page number of the next level. */
1520	unsigned u20PageNo : 20;
1521	} X86PDEBITS;
1522	/** Pointer to a page directory entry. */
1523	typedef X86PDEBITS *PX86PDEBITS;
1524	/** Pointer to a const page directory entry. */
1525	typedef const X86PDEBITS *PCX86PDEBITS;
1526
1527
1528	/**
1529	* PAE page directory entry.
1530	*/
1531	typedef struct X86PDEPAEBITS
1532	{
1533	/** Flags whether(=1) or not the page is present. */
1534	uint32_t u1Present : 1;
1535	/** Read(=0) / Write(=1) flag. */
1536	uint32_t u1Write : 1;
1537	/** User(=1) / Supervisor (=0) flag. */
1538	uint32_t u1User : 1;
1539	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1540	uint32_t u1WriteThru : 1;
1541	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1542	uint32_t u1CacheDisable : 1;
1543	/** Accessed flag.
1544	* Indicates that the page has been read or written to. */
1545	uint32_t u1Accessed : 1;
1546	/** Reserved / Ignored (dirty bit). */
1547	uint32_t u1Reserved0 : 1;
1548	/** Size bit if PSE is enabled - in any event it's 0. */
1549	uint32_t u1Size : 1;
1550	/** Reserved / Ignored (global bit). / */
1551	uint32_t u1Reserved1 : 1;
1552	/** Available for use to system software. */
1553	uint32_t u3Available : 3;
1554	/** Physical Page number of the next level - Low Part. Don't use! */
1555	uint32_t u20PageNoLow : 20;
1556	/** Physical Page number of the next level - High Part. Don't use! */
1557	uint32_t u20PageNoHigh : 20;
1558	/** MBZ bits */
1559	uint32_t u11Reserved : 11;
1560	/** No Execute flag. */
1561	uint32_t u1NoExecute : 1;
1562	} X86PDEPAEBITS;
1563	/** Pointer to a page directory entry. */
1564	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1565	/** Pointer to a const page directory entry. */
1566	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1567
1568	/** @} */
1569
1570
1571	/** @name 2/4MB Page Directory Entry
1572	* @{
1573	*/
1574	/** Bit 0 - P - Present bit. */
1575	#define X86_PDE4M_P RT_BIT(0)
1576	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1577	#define X86_PDE4M_RW RT_BIT(1)
1578	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1579	#define X86_PDE4M_US RT_BIT(2)
1580	/** Bit 3 - PWT - Page level write thru bit. */
1581	#define X86_PDE4M_PWT RT_BIT(3)
1582	/** Bit 4 - PCD - Page level cache disable bit. */
1583	#define X86_PDE4M_PCD RT_BIT(4)
1584	/** Bit 5 - A - Access bit. */
1585	#define X86_PDE4M_A RT_BIT(5)
1586	/** Bit 6 - D - Dirty bit. */
1587	#define X86_PDE4M_D RT_BIT(6)
1588	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1589	#define X86_PDE4M_PS RT_BIT(7)
1590	/** Bit 8 - G - Global flag. */
1591	#define X86_PDE4M_G RT_BIT(8)
1592	/** Bits 9-11 - AVL - Available for use to system software. */
1593	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1594	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1595	#define X86_PDE4M_PAT RT_BIT(12)
1596	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1597	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1598	/** Bits 22-31 - - Physical Page number. */
1599	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1600	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1601	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1602	/** The number of bits to the high part of the page number. */
1603	#define X86_PDE4M_PG_HIGH_SHIFT 19
1604	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1605	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1606
1607	/** Bits 21-51 - - PAE/LM - Physical Page number.
1608	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1609	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1610	/** Bits 63 - NX - PAE/LM - No execution flag. */
1611	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1612	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1613	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1614	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1615	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1616	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1617	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1618	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1619	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1620
1621	/**
1622	* 4MB page directory entry.
1623	*/
1624	typedef struct X86PDE4MBITS
1625	{
1626	/** Flags whether(=1) or not the page is present. */
1627	unsigned u1Present : 1;
1628	/** Read(=0) / Write(=1) flag. */
1629	unsigned u1Write : 1;
1630	/** User(=1) / Supervisor (=0) flag. */
1631	unsigned u1User : 1;
1632	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1633	unsigned u1WriteThru : 1;
1634	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1635	unsigned u1CacheDisable : 1;
1636	/** Accessed flag.
1637	* Indicates that the page have been read or written to. */
1638	unsigned u1Accessed : 1;
1639	/** Dirty flag.
1640	* Indicates that the page has been written to. */
1641	unsigned u1Dirty : 1;
1642	/** Page size flag - always 1 for 4MB entries. */
1643	unsigned u1Size : 1;
1644	/** Global flag. */
1645	unsigned u1Global : 1;
1646	/** Available for use to system software. */
1647	unsigned u3Available : 3;
1648	/** Reserved / If PAT enabled, bit 2 of the index. */
1649	unsigned u1PAT : 1;
1650	/** Bits 32-39 of the page number on AMD64.
1651	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1652	unsigned u8PageNoHigh : 8;
1653	/** Reserved. */
1654	unsigned u1Reserved : 1;
1655	/** Physical Page number of the page. */
1656	unsigned u10PageNo : 10;
1657	} X86PDE4MBITS;
1658	/** Pointer to a page table entry. */
1659	typedef X86PDE4MBITS *PX86PDE4MBITS;
1660	/** Pointer to a const page table entry. */
1661	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1662
1663
1664	/**
1665	* 2MB PAE page directory entry.
1666	*/
1667	typedef struct X86PDE2MPAEBITS
1668	{
1669	/** Flags whether(=1) or not the page is present. */
1670	uint32_t u1Present : 1;
1671	/** Read(=0) / Write(=1) flag. */
1672	uint32_t u1Write : 1;
1673	/** User(=1) / Supervisor(=0) flag. */
1674	uint32_t u1User : 1;
1675	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1676	uint32_t u1WriteThru : 1;
1677	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1678	uint32_t u1CacheDisable : 1;
1679	/** Accessed flag.
1680	* Indicates that the page have been read or written to. */
1681	uint32_t u1Accessed : 1;
1682	/** Dirty flag.
1683	* Indicates that the page has been written to. */
1684	uint32_t u1Dirty : 1;
1685	/** Page size flag - always 1 for 2MB entries. */
1686	uint32_t u1Size : 1;
1687	/** Global flag. */
1688	uint32_t u1Global : 1;
1689	/** Available for use to system software. */
1690	uint32_t u3Available : 3;
1691	/** Reserved / If PAT enabled, bit 2 of the index. */
1692	uint32_t u1PAT : 1;
1693	/** Reserved. */
1694	uint32_t u9Reserved : 9;
1695	/** Physical Page number of the next level - Low part. Don't use! */
1696	uint32_t u10PageNoLow : 10;
1697	/** Physical Page number of the next level - High part. Don't use! */
1698	uint32_t u20PageNoHigh : 20;
1699	/** MBZ bits */
1700	uint32_t u11Reserved : 11;
1701	/** No Execute flag. */
1702	uint32_t u1NoExecute : 1;
1703	} X86PDE2MPAEBITS;
1704	/** Pointer to a 2MB PAE page table entry. */
1705	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1706	/** Pointer to a 2MB PAE page table entry. */
1707	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1708
1709	/** @} */
1710
1711	/**
1712	* Page directory entry.
1713	*/
1714	typedef union X86PDE
1715	{
1716	/** Unsigned integer view. */
1717	X86PGUINT u;
1718	/** Normal view. */
1719	X86PDEBITS n;
1720	/** 4MB view (big). */
1721	X86PDE4MBITS b;
1722	/** 8 bit unsigned integer view. */
1723	uint8_t au8[4];
1724	/** 16 bit unsigned integer view. */
1725	uint16_t au16[2];
1726	/** 32 bit unsigned integer view. */
1727	uint32_t au32[1];
1728	} X86PDE;
1729	/** Pointer to a page directory entry. */
1730	typedef X86PDE *PX86PDE;
1731	/** Pointer to a const page directory entry. */
1732	typedef const X86PDE *PCX86PDE;
1733
1734	/**
1735	* PAE page directory entry.
1736	*/
1737	typedef union X86PDEPAE
1738	{
1739	/** Unsigned integer view. */
1740	X86PGPAEUINT u;
1741	/** Normal view. */
1742	X86PDEPAEBITS n;
1743	/** 2MB page view (big). */
1744	X86PDE2MPAEBITS b;
1745	/** 8 bit unsigned integer view. */
1746	uint8_t au8[8];
1747	/** 16 bit unsigned integer view. */
1748	uint16_t au16[4];
1749	/** 32 bit unsigned integer view. */
1750	uint32_t au32[2];
1751	} X86PDEPAE;
1752	/** Pointer to a page directory entry. */
1753	typedef X86PDEPAE *PX86PDEPAE;
1754	/** Pointer to a const page directory entry. */
1755	typedef const X86PDEPAE *PCX86PDEPAE;
1756
1757	/**
1758	* Page directory.
1759	*/
1760	typedef struct X86PD
1761	{
1762	/** PDE Array. */
1763	X86PDE a[X86_PG_ENTRIES];
1764	} X86PD;
1765	/** Pointer to a page directory. */
1766	typedef X86PD *PX86PD;
1767	/** Pointer to a const page directory. */
1768	typedef const X86PD *PCX86PD;
1769
1770	/** The page shift to get the PD index. */
1771	#define X86_PD_SHIFT 22
1772	/** The PD index mask (apply to a shifted page address). */
1773	#define X86_PD_MASK 0x3ff
1774
1775
1776	/**
1777	* PAE page directory.
1778	*/
1779	typedef struct X86PDPAE
1780	{
1781	/** PDE Array. */
1782	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1783	} X86PDPAE;
1784	/** Pointer to a PAE page directory. */
1785	typedef X86PDPAE *PX86PDPAE;
1786	/** Pointer to a const PAE page directory. */
1787	typedef const X86PDPAE *PCX86PDPAE;
1788
1789	/** The page shift to get the PAE PD index. */
1790	#define X86_PD_PAE_SHIFT 21
1791	/** The PAE PD index mask (apply to a shifted page address). */
1792	#define X86_PD_PAE_MASK 0x1ff
1793
1794
1795	/** @name Page Directory Pointer Table Entry (PAE)
1796	* @{
1797	*/
1798	/** Bit 0 - P - Present bit. */
1799	#define X86_PDPE_P RT_BIT(0)
1800	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1801	#define X86_PDPE_RW RT_BIT(1)
1802	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1803	#define X86_PDPE_US RT_BIT(2)
1804	/** Bit 3 - PWT - Page level write thru bit. */
1805	#define X86_PDPE_PWT RT_BIT(3)
1806	/** Bit 4 - PCD - Page level cache disable bit. */
1807	#define X86_PDPE_PCD RT_BIT(4)
1808	/** Bit 5 - A - Access bit. Long Mode only. */
1809	#define X86_PDPE_A RT_BIT(5)
1810	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1811	#define X86_PDPE_LM_PS RT_BIT(7)
1812	/** Bits 9-11 - - Available for use to system software. */
1813	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1814	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1815	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1816	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1817	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1818	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1819	#define X86_PDPE_LM_NX RT_BIT_64(63)
1820	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1821	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1822	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1823	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1824	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1825	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1826	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1827	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1828
1829
1830	/**
1831	* Page directory pointer table entry.
1832	*/
1833	typedef struct X86PDPEBITS
1834	{
1835	/** Flags whether(=1) or not the page is present. */
1836	uint32_t u1Present : 1;
1837	/** Chunk of reserved bits. */
1838	uint32_t u2Reserved : 2;
1839	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1840	uint32_t u1WriteThru : 1;
1841	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1842	uint32_t u1CacheDisable : 1;
1843	/** Chunk of reserved bits. */
1844	uint32_t u4Reserved : 4;
1845	/** Available for use to system software. */
1846	uint32_t u3Available : 3;
1847	/** Physical Page number of the next level - Low Part. Don't use! */
1848	uint32_t u20PageNoLow : 20;
1849	/** Physical Page number of the next level - High Part. Don't use! */
1850	uint32_t u20PageNoHigh : 20;
1851	/** MBZ bits */
1852	uint32_t u12Reserved : 12;
1853	} X86PDPEBITS;
1854	/** Pointer to a page directory pointer table entry. */
1855	typedef X86PDPEBITS *PX86PTPEBITS;
1856	/** Pointer to a const page directory pointer table entry. */
1857	typedef const X86PDPEBITS *PCX86PTPEBITS;
1858
1859	/**
1860	* Page directory pointer table entry. AMD64 version
1861	*/
1862	typedef struct X86PDPEAMD64BITS
1863	{
1864	/** Flags whether(=1) or not the page is present. */
1865	uint32_t u1Present : 1;
1866	/** Read(=0) / Write(=1) flag. */
1867	uint32_t u1Write : 1;
1868	/** User(=1) / Supervisor (=0) flag. */
1869	uint32_t u1User : 1;
1870	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1871	uint32_t u1WriteThru : 1;
1872	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1873	uint32_t u1CacheDisable : 1;
1874	/** Accessed flag.
1875	* Indicates that the page have been read or written to. */
1876	uint32_t u1Accessed : 1;
1877	/** Chunk of reserved bits. */
1878	uint32_t u3Reserved : 3;
1879	/** Available for use to system software. */
1880	uint32_t u3Available : 3;
1881	/** Physical Page number of the next level - Low Part. Don't use! */
1882	uint32_t u20PageNoLow : 20;
1883	/** Physical Page number of the next level - High Part. Don't use! */
1884	uint32_t u20PageNoHigh : 20;
1885	/** MBZ bits */
1886	uint32_t u11Reserved : 11;
1887	/** No Execute flag. */
1888	uint32_t u1NoExecute : 1;
1889	} X86PDPEAMD64BITS;
1890	/** Pointer to a page directory pointer table entry. */
1891	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1892	/** Pointer to a const page directory pointer table entry. */
1893	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1894
1895	/**
1896	* Page directory pointer table entry.
1897	*/
1898	typedef union X86PDPE
1899	{
1900	/** Unsigned integer view. */
1901	X86PGPAEUINT u;
1902	/** Normal view. */
1903	X86PDPEBITS n;
1904	/** AMD64 view. */
1905	X86PDPEAMD64BITS lm;
1906	/** 8 bit unsigned integer view. */
1907	uint8_t au8[8];
1908	/** 16 bit unsigned integer view. */
1909	uint16_t au16[4];
1910	/** 32 bit unsigned integer view. */
1911	uint32_t au32[2];
1912	} X86PDPE;
1913	/** Pointer to a page directory pointer table entry. */
1914	typedef X86PDPE *PX86PDPE;
1915	/** Pointer to a const page directory pointer table entry. */
1916	typedef const X86PDPE *PCX86PDPE;
1917
1918
1919	/**
1920	* Page directory pointer table.
1921	*/
1922	typedef struct X86PDPT
1923	{
1924	/** PDE Array. */
1925	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1926	} X86PDPT;
1927	/** Pointer to a page directory pointer table. */
1928	typedef X86PDPT *PX86PDPT;
1929	/** Pointer to a const page directory pointer table. */
1930	typedef const X86PDPT *PCX86PDPT;
1931
1932	/** The page shift to get the PDPT index. */
1933	#define X86_PDPT_SHIFT 30
1934	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1935	#define X86_PDPT_MASK_PAE 0x3
1936	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1937	#define X86_PDPT_MASK_AMD64 0x1ff
1938
1939	/** @} */
1940
1941
1942	/** @name Page Map Level-4 Entry (Long Mode PAE)
1943	* @{
1944	*/
1945	/** Bit 0 - P - Present bit. */
1946	#define X86_PML4E_P RT_BIT(0)
1947	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1948	#define X86_PML4E_RW RT_BIT(1)
1949	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1950	#define X86_PML4E_US RT_BIT(2)
1951	/** Bit 3 - PWT - Page level write thru bit. */
1952	#define X86_PML4E_PWT RT_BIT(3)
1953	/** Bit 4 - PCD - Page level cache disable bit. */
1954	#define X86_PML4E_PCD RT_BIT(4)
1955	/** Bit 5 - A - Access bit. */
1956	#define X86_PML4E_A RT_BIT(5)
1957	/** Bits 9-11 - - Available for use to system software. */
1958	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1959	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1960	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1961	/** Bits 8, 7 - - MBZ bits when NX is active. */
1962	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1963	/** Bits 63, 7 - - MBZ bits when no NX. */
1964	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1965	/** Bits 63 - NX - PAE - No execution flag. */
1966	#define X86_PML4E_NX RT_BIT_64(63)
1967
1968	/**
1969	* Page Map Level-4 Entry
1970	*/
1971	typedef struct X86PML4EBITS
1972	{
1973	/** Flags whether(=1) or not the page is present. */
1974	uint32_t u1Present : 1;
1975	/** Read(=0) / Write(=1) flag. */
1976	uint32_t u1Write : 1;
1977	/** User(=1) / Supervisor (=0) flag. */
1978	uint32_t u1User : 1;
1979	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1980	uint32_t u1WriteThru : 1;
1981	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1982	uint32_t u1CacheDisable : 1;
1983	/** Accessed flag.
1984	* Indicates that the page have been read or written to. */
1985	uint32_t u1Accessed : 1;
1986	/** Chunk of reserved bits. */
1987	uint32_t u3Reserved : 3;
1988	/** Available for use to system software. */
1989	uint32_t u3Available : 3;
1990	/** Physical Page number of the next level - Low Part. Don't use! */
1991	uint32_t u20PageNoLow : 20;
1992	/** Physical Page number of the next level - High Part. Don't use! */
1993	uint32_t u20PageNoHigh : 20;
1994	/** MBZ bits */
1995	uint32_t u11Reserved : 11;
1996	/** No Execute flag. */
1997	uint32_t u1NoExecute : 1;
1998	} X86PML4EBITS;
1999	/** Pointer to a page map level-4 entry. */
2000	typedef X86PML4EBITS *PX86PML4EBITS;
2001	/** Pointer to a const page map level-4 entry. */
2002	typedef const X86PML4EBITS *PCX86PML4EBITS;
2003
2004	/**
2005	* Page Map Level-4 Entry.
2006	*/
2007	typedef union X86PML4E
2008	{
2009	/** Unsigned integer view. */
2010	X86PGPAEUINT u;
2011	/** Normal view. */
2012	X86PML4EBITS n;
2013	/** 8 bit unsigned integer view. */
2014	uint8_t au8[8];
2015	/** 16 bit unsigned integer view. */
2016	uint16_t au16[4];
2017	/** 32 bit unsigned integer view. */
2018	uint32_t au32[2];
2019	} X86PML4E;
2020	/** Pointer to a page map level-4 entry. */
2021	typedef X86PML4E *PX86PML4E;
2022	/** Pointer to a const page map level-4 entry. */
2023	typedef const X86PML4E *PCX86PML4E;
2024
2025
2026	/**
2027	* Page Map Level-4.
2028	*/
2029	typedef struct X86PML4
2030	{
2031	/** PDE Array. */
2032	X86PML4E a[X86_PG_PAE_ENTRIES];
2033	} X86PML4;
2034	/** Pointer to a page map level-4. */
2035	typedef X86PML4 *PX86PML4;
2036	/** Pointer to a const page map level-4. */
2037	typedef const X86PML4 *PCX86PML4;
2038
2039	/** The page shift to get the PML4 index. */
2040	#define X86_PML4_SHIFT 39
2041	/** The PML4 index mask (apply to a shifted page address). */
2042	#define X86_PML4_MASK 0x1ff
2043
2044	/** @} */
2045
2046	/** @} */
2047
2048
2049	/**
2050	* 80-bit MMX/FPU register type.
2051	*/
2052	typedef struct X86FPUMMX
2053	{
2054	uint8_t reg[10];
2055	} X86FPUMMX;
2056	/** Pointer to a 80-bit MMX/FPU register type. */
2057	typedef X86FPUMMX *PX86FPUMMX;
2058	/** Pointer to a const 80-bit MMX/FPU register type. */
2059	typedef const X86FPUMMX *PCX86FPUMMX;
2060
2061	/**
2062	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2063	* @todo verify this...
2064	*/
2065	#pragma pack(1)
2066	typedef struct X86FPUSTATE
2067	{
2068	/** 0x00 - Control word. */
2069	uint16_t FCW;
2070	/** 0x02 - Alignment word */
2071	uint16_t Dummy1;
2072	/** 0x04 - Status word. */
2073	uint16_t FSW;
2074	/** 0x06 - Alignment word */
2075	uint16_t Dummy2;
2076	/** 0x08 - Tag word */
2077	uint16_t FTW;
2078	/** 0x0a - Alignment word */
2079	uint16_t Dummy3;
2080
2081	/** 0x0c - Instruction pointer. */
2082	uint32_t FPUIP;
2083	/** 0x10 - Code selector. */
2084	uint16_t CS;
2085	/** 0x12 - Opcode. */
2086	uint16_t FOP;
2087	/** 0x14 - FOO. */
2088	uint32_t FPUOO;
2089	/** 0x18 - FOS. */
2090	uint32_t FPUOS;
2091	/** 0x1c */
2092	union
2093	{
2094	/** MMX view. */
2095	uint64_t mmx;
2096	/** FPU view - todo. */
2097	X86FPUMMX fpu;
2098	/** Extended precision floating point view. */
2099	RTFLOAT80U r80;
2100	/** Extended precision floating point view v2. */
2101	RTFLOAT80U2 r80Ex;
2102	/** 8-bit view. */
2103	uint8_t au8[16];
2104	/** 16-bit view. */
2105	uint16_t au16[8];
2106	/** 32-bit view. */
2107	uint32_t au32[4];
2108	/** 64-bit view. */
2109	uint64_t au64[2];
2110	/** 128-bit view. (yeah, very helpful) */
2111	uint128_t au128[1];
2112	} regs[8];
2113	} X86FPUSTATE;
2114	#pragma pack()
2115	/** Pointer to a FPU state. */
2116	typedef X86FPUSTATE *PX86FPUSTATE;
2117	/** Pointer to a const FPU state. */
2118	typedef const X86FPUSTATE *PCX86FPUSTATE;
2119
2120	/**
2121	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2122	*/
2123	#pragma pack(1)
2124	typedef struct X86FXSTATE
2125	{
2126	/** 0x00 - Control word. */
2127	uint16_t FCW;
2128	/** 0x02 - Status word. */
2129	uint16_t FSW;
2130	/** 0x04 - Tag word. (The upper byte is always zero.) */
2131	uint16_t FTW;
2132	/** 0x06 - Opcode. */
2133	uint16_t FOP;
2134	/** 0x08 - Instruction pointer. */
2135	uint32_t FPUIP;
2136	/** 0x0c - Code selector. */
2137	uint16_t CS;
2138	uint16_t Rsrvd1;
2139	/** 0x10 - Data pointer. */
2140	uint32_t FPUDP;
2141	/** 0x14 - Data segment */
2142	uint16_t DS;
2143	/** 0x16 */
2144	uint16_t Rsrvd2;
2145	/** 0x18 */
2146	uint32_t MXCSR;
2147	/** 0x1c */
2148	uint32_t MXCSR_MASK;
2149	/** 0x20 */
2150	union
2151	{
2152	/** MMX view. */
2153	uint64_t mmx;
2154	/** FPU view - todo. */
2155	X86FPUMMX fpu;
2156	/** Extended precision floating point view. */
2157	RTFLOAT80U r80;
2158	/** Extended precision floating point view v2 */
2159	RTFLOAT80U2 r80Ex;
2160	/** 8-bit view. */
2161	uint8_t au8[16];
2162	/** 16-bit view. */
2163	uint16_t au16[8];
2164	/** 32-bit view. */
2165	uint32_t au32[4];
2166	/** 64-bit view. */
2167	uint64_t au64[2];
2168	/** 128-bit view. (yeah, very helpful) */
2169	uint128_t au128[1];
2170	} aRegs[8];
2171	/* - offset 160 - */
2172	union
2173	{
2174	/** XMM Register view . /
2175	uint128_t xmm;
2176	/** 8-bit view. */
2177	uint8_t au8[16];
2178	/** 16-bit view. */
2179	uint16_t au16[8];
2180	/** 32-bit view. */
2181	uint32_t au32[4];
2182	/** 64-bit view. */
2183	uint64_t au64[2];
2184	/** 128-bit view. (yeah, very helpful) */
2185	uint128_t au128[1];
2186	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2187	/* - offset 416 - */
2188	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2189	} X86FXSTATE;
2190	#pragma pack()
2191	/** Pointer to a FPU Extended state. */
2192	typedef X86FXSTATE *PX86FXSTATE;
2193	/** Pointer to a const FPU Extended state. */
2194	typedef const X86FXSTATE *PCX86FXSTATE;
2195
2196	/** @name FPU status word flags.
2197	* @{ */
2198	/** Exception Flag: Invalid operation. */
2199	#define X86_FSW_IE RT_BIT(0)
2200	/** Exception Flag: Denormalized operand. */
2201	#define X86_FSW_DE RT_BIT(1)
2202	/** Exception Flag: Zero divide. */
2203	#define X86_FSW_ZE RT_BIT(2)
2204	/** Exception Flag: Overflow. */
2205	#define X86_FSW_OE RT_BIT(3)
2206	/** Exception Flag: Underflow. */
2207	#define X86_FSW_UE RT_BIT(4)
2208	/** Exception Flag: Precision. */
2209	#define X86_FSW_PE RT_BIT(5)
2210	/** Stack fault. */
2211	#define X86_FSW_SF RT_BIT(6)
2212	/** Error summary status. */
2213	#define X86_FSW_ES RT_BIT(7)
2214	/** Mask of exceptions flags, excluding the summary bit. */
2215	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2216	/** Mask of exceptions flags, including the summary bit. */
2217	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2218	/** Condition code 0. */
2219	#define X86_FSW_C0 RT_BIT(8)
2220	/** Condition code 1. */
2221	#define X86_FSW_C1 RT_BIT(9)
2222	/** Condition code 2. */
2223	#define X86_FSW_C2 RT_BIT(10)
2224	/** Top of the stack mask. */
2225	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2226	/** TOP shift value. */
2227	#define X86_FSW_TOP_SHIFT 11
2228	/** Mask for getting TOP value after shifting it right. */
2229	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2230	/** Get the TOP value. */
2231	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2232	/** Condition code 3. */
2233	#define X86_FSW_C3 RT_BIT(14)
2234	/** Mask of exceptions flags, including the summary bit. */
2235	#define X86_FSW_C_MASK UINT16_C(0x4700)
2236	/** FPU busy. */
2237	#define X86_FSW_B RT_BIT(15)
2238	/** @} */
2239
2240
2241	/** @name FPU control word flags.
2242	* @{ */
2243	/** Exception Mask: Invalid operation. */
2244	#define X86_FCW_IM RT_BIT(0)
2245	/** Exception Mask: Denormalized operand. */
2246	#define X86_FCW_DM RT_BIT(1)
2247	/** Exception Mask: Zero divide. */
2248	#define X86_FCW_ZM RT_BIT(2)
2249	/** Exception Mask: Overflow. */
2250	#define X86_FCW_OM RT_BIT(3)
2251	/** Exception Mask: Underflow. */
2252	#define X86_FCW_UM RT_BIT(4)
2253	/** Exception Mask: Precision. */
2254	#define X86_FCW_PM RT_BIT(5)
2255	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2256	* @remarks This includes reserved bit 6. */
2257	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2258	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2259	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2260	/** Precision control mask. */
2261	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2262	/** Precision control: 24-bit. */
2263	#define X86_FCW_PC_24 UINT16_C(0x0000)
2264	/** Precision control: Reserved. */
2265	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2266	/** Precision control: 53-bit. */
2267	#define X86_FCW_PC_53 UINT16_C(0x0200)
2268	/** Precision control: 64-bit. */
2269	#define X86_FCW_PC_64 UINT16_C(0x0300)
2270	/** Rounding control mask. */
2271	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2272	/** Rounding control: To nearest. */
2273	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2274	/** Rounding control: Down. */
2275	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2276	/** Rounding control: Up. */
2277	#define X86_FCW_RC_UP UINT16_C(0x0800)
2278	/** Rounding control: Towards zero. */
2279	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2280	/** Bits which should be zero, apparently. */
2281	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2282	/** @} */
2283
2284	/** @name SSE MXCSR
2285	* @{ */
2286	/** Exception Flag: Invalid operation. */
2287	#define X86_MSXCR_IE RT_BIT(0)
2288	/** Exception Flag: Denormalized operand. */
2289	#define X86_MSXCR_DE RT_BIT(1)
2290	/** Exception Flag: Zero divide. */
2291	#define X86_MSXCR_ZE RT_BIT(2)
2292	/** Exception Flag: Overflow. */
2293	#define X86_MSXCR_OE RT_BIT(3)
2294	/** Exception Flag: Underflow. */
2295	#define X86_MSXCR_UE RT_BIT(4)
2296	/** Exception Flag: Precision. */
2297	#define X86_MSXCR_PE RT_BIT(5)
2298
2299	/** Denormals are zero. */
2300	#define X86_MSXCR_DAZ RT_BIT(6)
2301
2302	/** Exception Mask: Invalid operation. */
2303	#define X86_MSXCR_IM RT_BIT(7)
2304	/** Exception Mask: Denormalized operand. */
2305	#define X86_MSXCR_DM RT_BIT(8)
2306	/** Exception Mask: Zero divide. */
2307	#define X86_MSXCR_ZM RT_BIT(9)
2308	/** Exception Mask: Overflow. */
2309	#define X86_MSXCR_OM RT_BIT(10)
2310	/** Exception Mask: Underflow. */
2311	#define X86_MSXCR_UM RT_BIT(11)
2312	/** Exception Mask: Precision. */
2313	#define X86_MSXCR_PM RT_BIT(12)
2314
2315	/** Rounding control mask. */
2316	#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2317	/** Rounding control: To nearest. */
2318	#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2319	/** Rounding control: Down. */
2320	#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2321	/** Rounding control: Up. */
2322	#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2323	/** Rounding control: Towards zero. */
2324	#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2325
2326	/** Flush-to-zero for masked underflow. */
2327	#define X86_MSXCR_FZ RT_BIT(15)
2328
2329	/** Misaligned Exception Mask. */
2330	#define X86_MSXCR_MM RT_BIT(16)
2331	/** @} */
2332
2333
2334	/** @name Selector Descriptor
2335	* @{
2336	*/
2337
2338	#ifndef VBOX_FOR_DTRACE_LIB
2339	/**
2340	* Descriptor attributes (as seen by VT-x).
2341	*/
2342	typedef struct X86DESCATTRBITS
2343	{
2344	/** 00 - Segment Type. */
2345	unsigned u4Type : 4;
2346	/** 04 - Descriptor Type. System(=0) or code/data selector */
2347	unsigned u1DescType : 1;
2348	/** 05 - Descriptor Privelege level. */
2349	unsigned u2Dpl : 2;
2350	/** 07 - Flags selector present(=1) or not. */
2351	unsigned u1Present : 1;
2352	/** 08 - Segment limit 16-19. */
2353	unsigned u4LimitHigh : 4;
2354	/** 0c - Available for system software. */
2355	unsigned u1Available : 1;
2356	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2357	unsigned u1Long : 1;
2358	/** 0e - This flags meaning depends on the segment type. Try make sense out
2359	* of the intel manual yourself. */
2360	unsigned u1DefBig : 1;
2361	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2362	* clear byte. */
2363	unsigned u1Granularity : 1;
2364	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2365	unsigned u1Unusable : 1;
2366	} X86DESCATTRBITS;
2367	#endif /* !VBOX_FOR_DTRACE_LIB */
2368
2369	/** @name X86DESCATTR masks
2370	* @{ */
2371	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2372	#define X86DESCATTR_DT UINT32_C(0x00000010)
2373	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2374	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2375	#define X86DESCATTR_P UINT32_C(0x00000800)
2376	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2377	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2378	#define X86DESCATTR_L UINT32_C(0x00002000)
2379	#define X86DESCATTR_D UINT32_C(0x00004000)
2380	#define X86DESCATTR_G UINT32_C(0x00008000)
2381	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2382	/** @} */
2383
2384	#pragma pack(1)
2385	typedef union X86DESCATTR
2386	{
2387	/** Unsigned integer view. */
2388	uint32_t u;
2389	#ifndef VBOX_FOR_DTRACE_LIB
2390	/** Normal view. */
2391	X86DESCATTRBITS n;
2392	#endif
2393	} X86DESCATTR;
2394	#pragma pack()
2395	/** Pointer to descriptor attributes. */
2396	typedef X86DESCATTR *PX86DESCATTR;
2397	/** Pointer to const descriptor attributes. */
2398	typedef const X86DESCATTR *PCX86DESCATTR;
2399
2400	#ifndef VBOX_FOR_DTRACE_LIB
2401
2402	/**
2403	* Generic descriptor table entry
2404	*/
2405	#pragma pack(1)
2406	typedef struct X86DESCGENERIC
2407	{
2408	/** 00 - Limit - Low word. */
2409	unsigned u16LimitLow : 16;
2410	/** 10 - Base address - lowe word.
2411	* Don't try set this to 24 because MSC is doing stupid things then. */
2412	unsigned u16BaseLow : 16;
2413	/** 20 - Base address - first 8 bits of high word. */
2414	unsigned u8BaseHigh1 : 8;
2415	/** 28 - Segment Type. */
2416	unsigned u4Type : 4;
2417	/** 2c - Descriptor Type. System(=0) or code/data selector */
2418	unsigned u1DescType : 1;
2419	/** 2d - Descriptor Privelege level. */
2420	unsigned u2Dpl : 2;
2421	/** 2f - Flags selector present(=1) or not. */
2422	unsigned u1Present : 1;
2423	/** 30 - Segment limit 16-19. */
2424	unsigned u4LimitHigh : 4;
2425	/** 34 - Available for system software. */
2426	unsigned u1Available : 1;
2427	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2428	unsigned u1Long : 1;
2429	/** 36 - This flags meaning depends on the segment type. Try make sense out
2430	* of the intel manual yourself. */
2431	unsigned u1DefBig : 1;
2432	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
2433	* clear byte. */
2434	unsigned u1Granularity : 1;
2435	/** 38 - Base address - highest 8 bits. */
2436	unsigned u8BaseHigh2 : 8;
2437	} X86DESCGENERIC;
2438	#pragma pack()
2439	/** Pointer to a generic descriptor entry. */
2440	typedef X86DESCGENERIC *PX86DESCGENERIC;
2441	/** Pointer to a const generic descriptor entry. */
2442	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2443
2444	/** @name Bit offsets of X86DESCGENERIC members.
2445	* @{*/
2446	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
2447	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
2448	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
2449	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
2450	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
2451	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
2452	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
2453	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
2454	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
2455	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
2456	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
2457	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
2458	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
2459	/** @} */
2460
2461	/**
2462	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2463	*/
2464	typedef struct X86DESCGATE
2465	{
2466	/** 00 - Target code segment offset - Low word.
2467	* Ignored if task-gate. */
2468	unsigned u16OffsetLow : 16;
2469	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2470	* TSS selector if task-gate. */
2471	unsigned u16Sel : 16;
2472	/** 20 - Number of parameters for a call-gate.
2473	* Ignored if interrupt-, trap- or task-gate. */
2474	unsigned u4ParmCount : 4;
2475	/** 24 - Reserved / ignored. */
2476	unsigned u4Reserved : 4;
2477	/** 28 - Segment Type. */
2478	unsigned u4Type : 4;
2479	/** 2c - Descriptor Type (0 = system). */
2480	unsigned u1DescType : 1;
2481	/** 2d - Descriptor Privelege level. */
2482	unsigned u2Dpl : 2;
2483	/** 2f - Flags selector present(=1) or not. */
2484	unsigned u1Present : 1;
2485	/** 30 - Target code segment offset - High word.
2486	* Ignored if task-gate. */
2487	unsigned u16OffsetHigh : 16;
2488	} X86DESCGATE;
2489	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2490	typedef X86DESCGATE *PX86DESCGATE;
2491	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2492	typedef const X86DESCGATE *PCX86DESCGATE;
2493
2494	#endif /* VBOX_FOR_DTRACE_LIB */
2495
2496	/**
2497	* Descriptor table entry.
2498	*/
2499	#pragma pack(1)
2500	typedef union X86DESC
2501	{
2502	#ifndef VBOX_FOR_DTRACE_LIB
2503	/** Generic descriptor view. */
2504	X86DESCGENERIC Gen;
2505	/** Gate descriptor view. */
2506	X86DESCGATE Gate;
2507	#endif
2508
2509	/** 8 bit unsigned integer view. */
2510	uint8_t au8[8];
2511	/** 16 bit unsigned integer view. */
2512	uint16_t au16[4];
2513	/** 32 bit unsigned integer view. */
2514	uint32_t au32[2];
2515	/** 64 bit unsigned integer view. */
2516	uint64_t au64[1];
2517	/** Unsigned integer view. */
2518	uint64_t u;
2519	} X86DESC;
2520	#ifndef VBOX_FOR_DTRACE_LIB
2521	AssertCompileSize(X86DESC, 8);
2522	#endif
2523	#pragma pack()
2524	/** Pointer to descriptor table entry. */
2525	typedef X86DESC *PX86DESC;
2526	/** Pointer to const descriptor table entry. */
2527	typedef const X86DESC *PCX86DESC;
2528
2529	/** @def X86DESC_BASE
2530	* Return the base address of a descriptor.
2531	*/
2532	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
2533	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2534	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2535	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2536
2537	/** @def X86DESC_LIMIT
2538	* Return the limit of a descriptor.
2539	*/
2540	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
2541	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2542	\| ( (a_pDesc)->Gen.u16LimitLow ) )
2543
2544	/** @def X86DESC_LIMIT_G
2545	* Return the limit of a descriptor with the granularity bit taken into account.
2546	* @returns Selector limit (uint32_t).
2547	* @param a_pDesc Pointer to the descriptor.
2548	*/
2549	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
2550	( (a_pDesc)->Gen.u1Granularity \
2551	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
2552	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
2553	)
2554
2555	/** @def X86DESC_GET_HID_ATTR
2556	* Get the descriptor attributes for the hidden register.
2557	*/
2558	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
2559	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2560
2561	#ifndef VBOX_FOR_DTRACE_LIB
2562
2563	/**
2564	* 64 bits generic descriptor table entry
2565	* Note: most of these bits have no meaning in long mode.
2566	*/
2567	#pragma pack(1)
2568	typedef struct X86DESC64GENERIC
2569	{
2570	/** Limit - Low word - IGNORED. */
2571	unsigned u16LimitLow : 16;
2572	/** Base address - low word. - IGNORED
2573	* Don't try set this to 24 because MSC is doing stupid things then. */
2574	unsigned u16BaseLow : 16;
2575	/** Base address - first 8 bits of high word. - IGNORED */
2576	unsigned u8BaseHigh1 : 8;
2577	/** Segment Type. */
2578	unsigned u4Type : 4;
2579	/** Descriptor Type. System(=0) or code/data selector */
2580	unsigned u1DescType : 1;
2581	/** Descriptor Privelege level. */
2582	unsigned u2Dpl : 2;
2583	/** Flags selector present(=1) or not. */
2584	unsigned u1Present : 1;
2585	/** Segment limit 16-19. - IGNORED */
2586	unsigned u4LimitHigh : 4;
2587	/** Available for system software. - IGNORED */
2588	unsigned u1Available : 1;
2589	/** Long mode flag. */
2590	unsigned u1Long : 1;
2591	/** This flags meaning depends on the segment type. Try make sense out
2592	* of the intel manual yourself. */
2593	unsigned u1DefBig : 1;
2594	/** Granularity of the limit. If set 4KB granularity is used, if
2595	* clear byte. - IGNORED */
2596	unsigned u1Granularity : 1;
2597	/** Base address - highest 8 bits. - IGNORED */
2598	unsigned u8BaseHigh2 : 8;
2599	/** Base address - bits 63-32. */
2600	unsigned u32BaseHigh3 : 32;
2601	unsigned u8Reserved : 8;
2602	unsigned u5Zeros : 5;
2603	unsigned u19Reserved : 19;
2604	} X86DESC64GENERIC;
2605	#pragma pack()
2606	/** Pointer to a generic descriptor entry. */
2607	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2608	/** Pointer to a const generic descriptor entry. */
2609	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2610
2611	/**
2612	* System descriptor table entry (64 bits)
2613	*
2614	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2615	*/
2616	#pragma pack(1)
2617	typedef struct X86DESC64SYSTEM
2618	{
2619	/** Limit - Low word. */
2620	unsigned u16LimitLow : 16;
2621	/** Base address - lowe word.
2622	* Don't try set this to 24 because MSC is doing stupid things then. */
2623	unsigned u16BaseLow : 16;
2624	/** Base address - first 8 bits of high word. */
2625	unsigned u8BaseHigh1 : 8;
2626	/** Segment Type. */
2627	unsigned u4Type : 4;
2628	/** Descriptor Type. System(=0) or code/data selector */
2629	unsigned u1DescType : 1;
2630	/** Descriptor Privelege level. */
2631	unsigned u2Dpl : 2;
2632	/** Flags selector present(=1) or not. */
2633	unsigned u1Present : 1;
2634	/** Segment limit 16-19. */
2635	unsigned u4LimitHigh : 4;
2636	/** Available for system software. */
2637	unsigned u1Available : 1;
2638	/** Reserved - 0. */
2639	unsigned u1Reserved : 1;
2640	/** This flags meaning depends on the segment type. Try make sense out
2641	* of the intel manual yourself. */
2642	unsigned u1DefBig : 1;
2643	/** Granularity of the limit. If set 4KB granularity is used, if
2644	* clear byte. */
2645	unsigned u1Granularity : 1;
2646	/** Base address - bits 31-24. */
2647	unsigned u8BaseHigh2 : 8;
2648	/** Base address - bits 63-32. */
2649	unsigned u32BaseHigh3 : 32;
2650	unsigned u8Reserved : 8;
2651	unsigned u5Zeros : 5;
2652	unsigned u19Reserved : 19;
2653	} X86DESC64SYSTEM;
2654	#pragma pack()
2655	/** Pointer to a system descriptor entry. */
2656	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2657	/** Pointer to a const system descriptor entry. */
2658	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2659
2660	/**
2661	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2662	*/
2663	typedef struct X86DESC64GATE
2664	{
2665	/** Target code segment offset - Low word. */
2666	unsigned u16OffsetLow : 16;
2667	/** Target code segment selector. */
2668	unsigned u16Sel : 16;
2669	/** Interrupt stack table for interrupt- and trap-gates.
2670	* Ignored by call-gates. */
2671	unsigned u3IST : 3;
2672	/** Reserved / ignored. */
2673	unsigned u5Reserved : 5;
2674	/** Segment Type. */
2675	unsigned u4Type : 4;
2676	/** Descriptor Type (0 = system). */
2677	unsigned u1DescType : 1;
2678	/** Descriptor Privelege level. */
2679	unsigned u2Dpl : 2;
2680	/** Flags selector present(=1) or not. */
2681	unsigned u1Present : 1;
2682	/** Target code segment offset - High word.
2683	* Ignored if task-gate. */
2684	unsigned u16OffsetHigh : 16;
2685	/** Target code segment offset - Top dword.
2686	* Ignored if task-gate. */
2687	unsigned u32OffsetTop : 32;
2688	/** Reserved / ignored / must be zero.
2689	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2690	unsigned u32Reserved : 32;
2691	} X86DESC64GATE;
2692	AssertCompileSize(X86DESC64GATE, 16);
2693	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2694	typedef X86DESC64GATE *PX86DESC64GATE;
2695	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2696	typedef const X86DESC64GATE *PCX86DESC64GATE;
2697
2698	#endif /* VBOX_FOR_DTRACE_LIB */
2699
2700	/**
2701	* Descriptor table entry.
2702	*/
2703	#pragma pack(1)
2704	typedef union X86DESC64
2705	{
2706	#ifndef VBOX_FOR_DTRACE_LIB
2707	/** Generic descriptor view. */
2708	X86DESC64GENERIC Gen;
2709	/** System descriptor view. */
2710	X86DESC64SYSTEM System;
2711	/** Gate descriptor view. */
2712	X86DESC64GATE Gate;
2713	#endif
2714
2715	/** 8 bit unsigned integer view. */
2716	uint8_t au8[16];
2717	/** 16 bit unsigned integer view. */
2718	uint16_t au16[8];
2719	/** 32 bit unsigned integer view. */
2720	uint32_t au32[4];
2721	/** 64 bit unsigned integer view. */
2722	uint64_t au64[2];
2723	} X86DESC64;
2724	#ifndef VBOX_FOR_DTRACE_LIB
2725	AssertCompileSize(X86DESC64, 16);
2726	#endif
2727	#pragma pack()
2728	/** Pointer to descriptor table entry. */
2729	typedef X86DESC64 *PX86DESC64;
2730	/** Pointer to const descriptor table entry. */
2731	typedef const X86DESC64 *PCX86DESC64;
2732
2733	/** @def X86DESC64_BASE
2734	* Return the base of a 64-bit descriptor.
2735	*/
2736	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
2737	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2738	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2739	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2740	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2741
2742
2743
2744	/** @name Host system descriptor table entry - Use with care!
2745	* @{ */
2746	/** Host system descriptor table entry. */
2747	#if HC_ARCH_BITS == 64
2748	typedef X86DESC64 X86DESCHC;
2749	#else
2750	typedef X86DESC X86DESCHC;
2751	#endif
2752	/** Pointer to a host system descriptor table entry. */
2753	#if HC_ARCH_BITS == 64
2754	typedef PX86DESC64 PX86DESCHC;
2755	#else
2756	typedef PX86DESC PX86DESCHC;
2757	#endif
2758	/** Pointer to a const host system descriptor table entry. */
2759	#if HC_ARCH_BITS == 64
2760	typedef PCX86DESC64 PCX86DESCHC;
2761	#else
2762	typedef PCX86DESC PCX86DESCHC;
2763	#endif
2764	/** @} */
2765
2766
2767	/** @name Selector Descriptor Types.
2768	* @{
2769	*/
2770
2771	/** @name Non-System Selector Types.
2772	* @{ */
2773	/** Code(=set)/Data(=clear) bit. */
2774	#define X86_SEL_TYPE_CODE 8
2775	/** Memory(=set)/System(=clear) bit. */
2776	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2777	/** Accessed bit. */
2778	#define X86_SEL_TYPE_ACCESSED 1
2779	/** Expand down bit (for data selectors only). */
2780	#define X86_SEL_TYPE_DOWN 4
2781	/** Conforming bit (for code selectors only). */
2782	#define X86_SEL_TYPE_CONF 4
2783	/** Write bit (for data selectors only). */
2784	#define X86_SEL_TYPE_WRITE 2
2785	/** Read bit (for code selectors only). */
2786	#define X86_SEL_TYPE_READ 2
2787	/** The bit number of the code segment read bit (relative to u4Type). */
2788	#define X86_SEL_TYPE_READ_BIT 1
2789
2790	/** Read only selector type. */
2791	#define X86_SEL_TYPE_RO 0
2792	/** Accessed read only selector type. */
2793	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2794	/** Read write selector type. */
2795	#define X86_SEL_TYPE_RW 2
2796	/** Accessed read write selector type. */
2797	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2798	/** Expand down read only selector type. */
2799	#define X86_SEL_TYPE_RO_DOWN 4
2800	/** Accessed expand down read only selector type. */
2801	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2802	/** Expand down read write selector type. */
2803	#define X86_SEL_TYPE_RW_DOWN 6
2804	/** Accessed expand down read write selector type. */
2805	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2806	/** Execute only selector type. */
2807	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2808	/** Accessed execute only selector type. */
2809	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2810	/** Execute and read selector type. */
2811	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2812	/** Accessed execute and read selector type. */
2813	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2814	/** Conforming execute only selector type. */
2815	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2816	/** Accessed Conforming execute only selector type. */
2817	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2818	/** Conforming execute and write selector type. */
2819	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2820	/** Accessed Conforming execute and write selector type. */
2821	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2822	/** @} */
2823
2824
2825	/** @name System Selector Types.
2826	* @{ */
2827	/** The TSS busy bit mask. */
2828	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2829
2830	/** Undefined system selector type. */
2831	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2832	/** 286 TSS selector. */
2833	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2834	/** LDT selector. */
2835	#define X86_SEL_TYPE_SYS_LDT 2
2836	/** 286 TSS selector - Busy. */
2837	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2838	/** 286 Callgate selector. */
2839	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2840	/** Taskgate selector. */
2841	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2842	/** 286 Interrupt gate selector. */
2843	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2844	/** 286 Trapgate selector. */
2845	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2846	/** Undefined system selector. */
2847	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2848	/** 386 TSS selector. */
2849	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2850	/** Undefined system selector. */
2851	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2852	/** 386 TSS selector - Busy. */
2853	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2854	/** 386 Callgate selector. */
2855	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2856	/** Undefined system selector. */
2857	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2858	/** 386 Interruptgate selector. */
2859	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2860	/** 386 Trapgate selector. */
2861	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2862	/** @} */
2863
2864	/** @name AMD64 System Selector Types.
2865	* @{ */
2866	/** LDT selector. */
2867	#define AMD64_SEL_TYPE_SYS_LDT 2
2868	/** TSS selector - Busy. */
2869	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2870	/** TSS selector - Busy. */
2871	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2872	/** Callgate selector. */
2873	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2874	/** Interruptgate selector. */
2875	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2876	/** Trapgate selector. */
2877	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2878	/** @} */
2879
2880	/** @} */
2881
2882
2883	/** @name Descriptor Table Entry Flag Masks.
2884	* These are for the 2nd 32-bit word of a descriptor.
2885	* @{ */
2886	/** Bits 8-11 - TYPE - Descriptor type mask. */
2887	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2888	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2889	#define X86_DESC_S RT_BIT(12)
2890	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2891	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2892	/** Bit 15 - P - Present. */
2893	#define X86_DESC_P RT_BIT(15)
2894	/** Bit 20 - AVL - Available for system software. */
2895	#define X86_DESC_AVL RT_BIT(20)
2896	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2897	#define X86_DESC_DB RT_BIT(22)
2898	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2899	* used, if clear byte. */
2900	#define X86_DESC_G RT_BIT(23)
2901	/** @} */
2902
2903	/** @} */
2904
2905
2906	/** @name Task Segments.
2907	* @{
2908	*/
2909
2910	/**
2911	* 16-bit Task Segment (TSS).
2912	*/
2913	#pragma pack(1)
2914	typedef struct X86TSS16
2915	{
2916	/** Back link to previous task. (static) */
2917	RTSEL selPrev;
2918	/** Ring-0 stack pointer. (static) */
2919	uint16_t sp0;
2920	/** Ring-0 stack segment. (static) */
2921	RTSEL ss0;
2922	/** Ring-1 stack pointer. (static) */
2923	uint16_t sp1;
2924	/** Ring-1 stack segment. (static) */
2925	RTSEL ss1;
2926	/** Ring-2 stack pointer. (static) */
2927	uint16_t sp2;
2928	/** Ring-2 stack segment. (static) */
2929	RTSEL ss2;
2930	/** IP before task switch. */
2931	uint16_t ip;
2932	/** FLAGS before task switch. */
2933	uint16_t flags;
2934	/** AX before task switch. */
2935	uint16_t ax;
2936	/** CX before task switch. */
2937	uint16_t cx;
2938	/** DX before task switch. */
2939	uint16_t dx;
2940	/** BX before task switch. */
2941	uint16_t bx;
2942	/** SP before task switch. */
2943	uint16_t sp;
2944	/** BP before task switch. */
2945	uint16_t bp;
2946	/** SI before task switch. */
2947	uint16_t si;
2948	/** DI before task switch. */
2949	uint16_t di;
2950	/** ES before task switch. */
2951	RTSEL es;
2952	/** CS before task switch. */
2953	RTSEL cs;
2954	/** SS before task switch. */
2955	RTSEL ss;
2956	/** DS before task switch. */
2957	RTSEL ds;
2958	/** LDTR before task switch. */
2959	RTSEL selLdt;
2960	} X86TSS16;
2961	#ifndef VBOX_FOR_DTRACE_LIB
2962	AssertCompileSize(X86TSS16, 44);
2963	#endif
2964	#pragma pack()
2965	/** Pointer to a 16-bit task segment. */
2966	typedef X86TSS16 *PX86TSS16;
2967	/** Pointer to a const 16-bit task segment. */
2968	typedef const X86TSS16 *PCX86TSS16;
2969
2970
2971	/**
2972	* 32-bit Task Segment (TSS).
2973	*/
2974	#pragma pack(1)
2975	typedef struct X86TSS32
2976	{
2977	/** Back link to previous task. (static) */
2978	RTSEL selPrev;
2979	uint16_t padding1;
2980	/** Ring-0 stack pointer. (static) */
2981	uint32_t esp0;
2982	/** Ring-0 stack segment. (static) */
2983	RTSEL ss0;
2984	uint16_t padding_ss0;
2985	/** Ring-1 stack pointer. (static) */
2986	uint32_t esp1;
2987	/** Ring-1 stack segment. (static) */
2988	RTSEL ss1;
2989	uint16_t padding_ss1;
2990	/** Ring-2 stack pointer. (static) */
2991	uint32_t esp2;
2992	/** Ring-2 stack segment. (static) */
2993	RTSEL ss2;
2994	uint16_t padding_ss2;
2995	/** Page directory for the task. (static) */
2996	uint32_t cr3;
2997	/** EIP before task switch. */
2998	uint32_t eip;
2999	/** EFLAGS before task switch. */
3000	uint32_t eflags;
3001	/** EAX before task switch. */
3002	uint32_t eax;
3003	/** ECX before task switch. */
3004	uint32_t ecx;
3005	/** EDX before task switch. */
3006	uint32_t edx;
3007	/** EBX before task switch. */
3008	uint32_t ebx;
3009	/** ESP before task switch. */
3010	uint32_t esp;
3011	/** EBP before task switch. */
3012	uint32_t ebp;
3013	/** ESI before task switch. */
3014	uint32_t esi;
3015	/** EDI before task switch. */
3016	uint32_t edi;
3017	/** ES before task switch. */
3018	RTSEL es;
3019	uint16_t padding_es;
3020	/** CS before task switch. */
3021	RTSEL cs;
3022	uint16_t padding_cs;
3023	/** SS before task switch. */
3024	RTSEL ss;
3025	uint16_t padding_ss;
3026	/** DS before task switch. */
3027	RTSEL ds;
3028	uint16_t padding_ds;
3029	/** FS before task switch. */
3030	RTSEL fs;
3031	uint16_t padding_fs;
3032	/** GS before task switch. */
3033	RTSEL gs;
3034	uint16_t padding_gs;
3035	/** LDTR before task switch. */
3036	RTSEL selLdt;
3037	uint16_t padding_ldt;
3038	/** Debug trap flag */
3039	uint16_t fDebugTrap;
3040	/** Offset relative to the TSS of the start of the I/O Bitmap
3041	* and the end of the interrupt redirection bitmap. */
3042	uint16_t offIoBitmap;
3043	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3044	uint8_t IntRedirBitmap[32];
3045	} X86TSS32;
3046	#pragma pack()
3047	/** Pointer to task segment. */
3048	typedef X86TSS32 *PX86TSS32;
3049	/** Pointer to const task segment. */
3050	typedef const X86TSS32 *PCX86TSS32;
3051
3052
3053	/**
3054	* 64-bit Task segment.
3055	*/
3056	#pragma pack(1)
3057	typedef struct X86TSS64
3058	{
3059	/** Reserved. */
3060	uint32_t u32Reserved;
3061	/** Ring-0 stack pointer. (static) */
3062	uint64_t rsp0;
3063	/** Ring-1 stack pointer. (static) */
3064	uint64_t rsp1;
3065	/** Ring-2 stack pointer. (static) */
3066	uint64_t rsp2;
3067	/** Reserved. */
3068	uint32_t u32Reserved2[2];
3069	/* IST */
3070	uint64_t ist1;
3071	uint64_t ist2;
3072	uint64_t ist3;
3073	uint64_t ist4;
3074	uint64_t ist5;
3075	uint64_t ist6;
3076	uint64_t ist7;
3077	/* Reserved. */
3078	uint16_t u16Reserved[5];
3079	/** Offset relative to the TSS of the start of the I/O Bitmap
3080	* and the end of the interrupt redirection bitmap. */
3081	uint16_t offIoBitmap;
3082	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3083	uint8_t IntRedirBitmap[32];
3084	} X86TSS64;
3085	#pragma pack()
3086	/** Pointer to a 64-bit task segment. */
3087	typedef X86TSS64 *PX86TSS64;
3088	/** Pointer to a const 64-bit task segment. */
3089	typedef const X86TSS64 *PCX86TSS64;
3090	#ifndef VBOX_FOR_DTRACE_LIB
3091	AssertCompileSize(X86TSS64, 136);
3092	#endif
3093
3094	/** @} */
3095
3096
3097	/** @name Selectors.
3098	* @{
3099	*/
3100
3101	/**
3102	* The shift used to convert a selector from and to index an index (C).
3103	*/
3104	#define X86_SEL_SHIFT 3
3105
3106	/**
3107	* The mask used to mask off the table indicator and RPL of an selector.
3108	*/
3109	#define X86_SEL_MASK 0xfff8U
3110
3111	/**
3112	* The mask used to mask off the RPL of an selector.
3113	* This is suitable for checking for NULL selectors.
3114	*/
3115	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3116
3117	/**
3118	* The bit indicating that a selector is in the LDT and not in the GDT.
3119	*/
3120	#define X86_SEL_LDT 0x0004U
3121
3122	/**
3123	* The bit mask for getting the RPL of a selector.
3124	*/
3125	#define X86_SEL_RPL 0x0003U
3126
3127	/**
3128	* The mask covering both RPL and LDT.
3129	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3130	* checks.
3131	*/
3132	#define X86_SEL_RPL_LDT 0x0007U
3133
3134	/** @} */
3135
3136
3137	/**
3138	* x86 Exceptions/Faults/Traps.
3139	*/
3140	typedef enum X86XCPT
3141	{
3142	/** \#DE - Divide error. */
3143	X86_XCPT_DE = 0x00,
3144	/** \#DB - Debug event (single step, DRx, ..) */
3145	X86_XCPT_DB = 0x01,
3146	/** NMI - Non-Maskable Interrupt */
3147	X86_XCPT_NMI = 0x02,
3148	/** \#BP - Breakpoint (INT3). */
3149	X86_XCPT_BP = 0x03,
3150	/** \#OF - Overflow (INTO). */
3151	X86_XCPT_OF = 0x04,
3152	/** \#BR - Bound range exceeded (BOUND). */
3153	X86_XCPT_BR = 0x05,
3154	/** \#UD - Undefined opcode. */
3155	X86_XCPT_UD = 0x06,
3156	/** \#NM - Device not available (math coprocessor device). */
3157	X86_XCPT_NM = 0x07,
3158	/** \#DF - Double fault. */
3159	X86_XCPT_DF = 0x08,
3160	/** ??? - Coprocessor segment overrun (obsolete). */
3161	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3162	/** \#TS - Taskswitch (TSS). */
3163	X86_XCPT_TS = 0x0a,
3164	/** \#NP - Segment no present. */
3165	X86_XCPT_NP = 0x0b,
3166	/** \#SS - Stack segment fault. */
3167	X86_XCPT_SS = 0x0c,
3168	/** \#GP - General protection fault. */
3169	X86_XCPT_GP = 0x0d,
3170	/** \#PF - Page fault. */
3171	X86_XCPT_PF = 0x0e,
3172	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3173	/** \#MF - Math fault (FPU). */
3174	X86_XCPT_MF = 0x10,
3175	/** \#AC - Alignment check. */
3176	X86_XCPT_AC = 0x11,
3177	/** \#MC - Machine check. */
3178	X86_XCPT_MC = 0x12,
3179	/** \#XF - SIMD Floating-Pointer Exception. */
3180	X86_XCPT_XF = 0x13,
3181	/** \#VE - Virtualzation Exception. */
3182	X86_XCPT_VE = 0x14,
3183	/** \#SX - Security Exception. */
3184	X86_XCPT_SX = 0x1f
3185	} X86XCPT;
3186	/** Pointer to a x86 exception code. */
3187	typedef X86XCPT *PX86XCPT;
3188	/** Pointer to a const x86 exception code. */
3189	typedef const X86XCPT *PCX86XCPT;
3190	/** The maximum exception value. */
3191	#define X86_XCPT_MAX (X86_XCPT_SX)
3192
3193
3194	/** @name Trap Error Codes
3195	* @{
3196	*/
3197	/** External indicator. */
3198	#define X86_TRAP_ERR_EXTERNAL 1
3199	/** IDT indicator. */
3200	#define X86_TRAP_ERR_IDT 2
3201	/** Descriptor table indicator - If set LDT, if clear GDT. */
3202	#define X86_TRAP_ERR_TI 4
3203	/** Mask for getting the selector. */
3204	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3205	/** Shift for getting the selector table index (C type index). */
3206	#define X86_TRAP_ERR_SEL_SHIFT 3
3207	/** @} */
3208
3209
3210	/** @name \#PF Trap Error Codes
3211	* @{
3212	*/
3213	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3214	#define X86_TRAP_PF_P RT_BIT(0)
3215	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3216	#define X86_TRAP_PF_RW RT_BIT(1)
3217	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3218	#define X86_TRAP_PF_US RT_BIT(2)
3219	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3220	#define X86_TRAP_PF_RSVD RT_BIT(3)
3221	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3222	#define X86_TRAP_PF_ID RT_BIT(4)
3223	/** @} */
3224
3225	#pragma pack(1)
3226	/**
3227	* 32-bit IDTR/GDTR.
3228	*/
3229	typedef struct X86XDTR32
3230	{
3231	/** Size of the descriptor table. */
3232	uint16_t cb;
3233	/** Address of the descriptor table. */
3234	#ifndef VBOX_FOR_DTRACE_LIB
3235	uint32_t uAddr;
3236	#else
3237	uint16_t au16Addr[2];
3238	#endif
3239	} X86XDTR32, *PX86XDTR32;
3240	#pragma pack()
3241
3242	#pragma pack(1)
3243	/**
3244	* 64-bit IDTR/GDTR.
3245	*/
3246	typedef struct X86XDTR64
3247	{
3248	/** Size of the descriptor table. */
3249	uint16_t cb;
3250	/** Address of the descriptor table. */
3251	#ifndef VBOX_FOR_DTRACE_LIB
3252	uint64_t uAddr;
3253	#else
3254	uint16_t au16Addr[4];
3255	#endif
3256	} X86XDTR64, *PX86XDTR64;
3257	#pragma pack()
3258
3259
3260	/** @name ModR/M
3261	* @{ */
3262	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3263	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3264	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3265	#define X86_MODRM_REG_SHIFT 3
3266	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3267	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3268	#define X86_MODRM_MOD_SHIFT 6
3269	#ifndef VBOX_FOR_DTRACE_LIB
3270	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3271	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3272	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3273	#endif
3274	/** @} */
3275
3276	/** @name SIB
3277	* @{ */
3278	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3279	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3280	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3281	#define X86_SIB_INDEX_SHIFT 3
3282	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3283	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3284	#define X86_SIB_SCALE_SHIFT 6
3285	#ifndef VBOX_FOR_DTRACE_LIB
3286	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3287	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3288	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3289	#endif
3290	/** @} */
3291
3292	/** @name General register indexes
3293	* @{ */
3294	#define X86_GREG_xAX 0
3295	#define X86_GREG_xCX 1
3296	#define X86_GREG_xDX 2
3297	#define X86_GREG_xBX 3
3298	#define X86_GREG_xSP 4
3299	#define X86_GREG_xBP 5
3300	#define X86_GREG_xSI 6
3301	#define X86_GREG_xDI 7
3302	#define X86_GREG_x8 8
3303	#define X86_GREG_x9 9
3304	#define X86_GREG_x10 10
3305	#define X86_GREG_x11 11
3306	#define X86_GREG_x12 12
3307	#define X86_GREG_x13 13
3308	#define X86_GREG_x14 14
3309	#define X86_GREG_x15 15
3310	/** @} */
3311
3312	/** @name X86_SREG_XXX - Segment register indexes.
3313	* @{ */
3314	#define X86_SREG_ES 0
3315	#define X86_SREG_CS 1
3316	#define X86_SREG_SS 2
3317	#define X86_SREG_DS 3
3318	#define X86_SREG_FS 4
3319	#define X86_SREG_GS 5
3320	/** @} */
3321	/** Segment register count. */
3322	#define X86_SREG_COUNT 6
3323
3324
3325	/** @name X86_OP_XXX - Prefixes
3326	* @{ */
3327	#define X86_OP_PRF_CS UINT8_C(0x2e)
3328	#define X86_OP_PRF_SS UINT8_C(0x36)
3329	#define X86_OP_PRF_DS UINT8_C(0x3e)
3330	#define X86_OP_PRF_ES UINT8_C(0x26)
3331	#define X86_OP_PRF_FS UINT8_C(0x64)
3332	#define X86_OP_PRF_GS UINT8_C(0x65)
3333	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3334	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3335	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3336	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3337	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3338	#define X86_OP_REX_B UINT8_C(0x41)
3339	#define X86_OP_REX_X UINT8_C(0x42)
3340	#define X86_OP_REX_R UINT8_C(0x44)
3341	#define X86_OP_REX_W UINT8_C(0x48)
3342	/** @} */
3343
3344
3345	/** @} */
3346
3347	#endif
3348

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source: vbox/trunk/include/iprt/x86.h@ 47667

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