VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 47988

Last change on this file since 47988 was 47988, checked in by vboxsync, 12 years ago

Solaris reads MSR_RAPL_POWER_UNIT, give it some fake values.
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File size: 120.2 KB
Line 
1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2012 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT(0)
164/** Bit 1 - Reserved, reads as 1. */
165#define X86_EFL_1 RT_BIT(1)
166/** Bit 2 - PF - Parity flag - Status flag. */
167#define X86_EFL_PF RT_BIT(2)
168/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169#define X86_EFL_AF RT_BIT(4)
170/** Bit 6 - ZF - Zero flag - Status flag. */
171#define X86_EFL_ZF RT_BIT(6)
172/** Bit 7 - SF - Signed flag - Status flag. */
173#define X86_EFL_SF RT_BIT(7)
174/** Bit 8 - TF - Trap flag - System flag. */
175#define X86_EFL_TF RT_BIT(8)
176/** Bit 9 - IF - Interrupt flag - System flag. */
177#define X86_EFL_IF RT_BIT(9)
178/** Bit 10 - DF - Direction flag - Control flag. */
179#define X86_EFL_DF RT_BIT(10)
180/** Bit 11 - OF - Overflow flag - Status flag. */
181#define X86_EFL_OF RT_BIT(11)
182/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
184/** Bit 14 - NT - Nested task flag - System flag. */
185#define X86_EFL_NT RT_BIT(14)
186/** Bit 16 - RF - Resume flag - System flag. */
187#define X86_EFL_RF RT_BIT(16)
188/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189#define X86_EFL_VM RT_BIT(17)
190/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191#define X86_EFL_AC RT_BIT(18)
192/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193#define X86_EFL_VIF RT_BIT(19)
194/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195#define X86_EFL_VIP RT_BIT(20)
196/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197#define X86_EFL_ID RT_BIT(21)
198/** All live bits. */
199#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
200/** Read as 1 bits. */
201#define X86_EFL_RA1_MASK RT_BIT_32(1)
202/** IOPL shift. */
203#define X86_EFL_IOPL_SHIFT 12
204/** The the IOPL level from the flags. */
205#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
206/** Bits restored by popf */
207#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
208 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
209/** @} */
210
211
212/** CPUID Feature information - ECX.
213 * CPUID query with EAX=1.
214 */
215#ifndef VBOX_FOR_DTRACE_LIB
216typedef struct X86CPUIDFEATECX
217{
218 /** Bit 0 - SSE3 - Supports SSE3 or not. */
219 unsigned u1SSE3 : 1;
220 /** Bit 1 - PCLMULQDQ. */
221 unsigned u1PCLMULQDQ : 1;
222 /** Bit 2 - DS Area 64-bit layout. */
223 unsigned u1DTE64 : 1;
224 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
225 unsigned u1Monitor : 1;
226 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
227 unsigned u1CPLDS : 1;
228 /** Bit 5 - VMX - Virtual Machine Technology. */
229 unsigned u1VMX : 1;
230 /** Bit 6 - SMX: Safer Mode Extensions. */
231 unsigned u1SMX : 1;
232 /** Bit 7 - EST - Enh. SpeedStep Tech. */
233 unsigned u1EST : 1;
234 /** Bit 8 - TM2 - Terminal Monitor 2. */
235 unsigned u1TM2 : 1;
236 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
237 unsigned u1SSSE3 : 1;
238 /** Bit 10 - CNTX-ID - L1 Context ID. */
239 unsigned u1CNTXID : 1;
240 /** Bit 11 - Reserved. */
241 unsigned u1Reserved1 : 1;
242 /** Bit 12 - FMA. */
243 unsigned u1FMA : 1;
244 /** Bit 13 - CX16 - CMPXCHG16B. */
245 unsigned u1CX16 : 1;
246 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
247 unsigned u1TPRUpdate : 1;
248 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
249 unsigned u1PDCM : 1;
250 /** Bit 16 - Reserved. */
251 unsigned u1Reserved2 : 1;
252 /** Bit 17 - PCID - Process-context identifiers. */
253 unsigned u1PCID : 1;
254 /** Bit 18 - Direct Cache Access. */
255 unsigned u1DCA : 1;
256 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
257 unsigned u1SSE4_1 : 1;
258 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
259 unsigned u1SSE4_2 : 1;
260 /** Bit 21 - x2APIC. */
261 unsigned u1x2APIC : 1;
262 /** Bit 22 - MOVBE - Supports MOVBE. */
263 unsigned u1MOVBE : 1;
264 /** Bit 23 - POPCNT - Supports POPCNT. */
265 unsigned u1POPCNT : 1;
266 /** Bit 24 - TSC-Deadline. */
267 unsigned u1TSCDEADLINE : 1;
268 /** Bit 25 - AES. */
269 unsigned u1AES : 1;
270 /** Bit 26 - XSAVE - Supports XSAVE. */
271 unsigned u1XSAVE : 1;
272 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
273 unsigned u1OSXSAVE : 1;
274 /** Bit 28 - AVX - Supports AVX instruction extensions. */
275 unsigned u1AVX : 1;
276 /** Bit 29 - 30 - Reserved */
277 unsigned u2Reserved3 : 2;
278 /** Bit 31 - Hypervisor present (we're a guest). */
279 unsigned u1HVP : 1;
280} X86CPUIDFEATECX;
281#else /* VBOX_FOR_DTRACE_LIB */
282typedef uint32_t X86CPUIDFEATECX;
283#endif /* VBOX_FOR_DTRACE_LIB */
284/** Pointer to CPUID Feature Information - ECX. */
285typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
286/** Pointer to const CPUID Feature Information - ECX. */
287typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
288
289
290/** CPUID Feature Information - EDX.
291 * CPUID query with EAX=1.
292 */
293#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
294typedef struct X86CPUIDFEATEDX
295{
296 /** Bit 0 - FPU - x87 FPU on Chip. */
297 unsigned u1FPU : 1;
298 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
299 unsigned u1VME : 1;
300 /** Bit 2 - DE - Debugging extensions. */
301 unsigned u1DE : 1;
302 /** Bit 3 - PSE - Page Size Extension. */
303 unsigned u1PSE : 1;
304 /** Bit 4 - TSC - Time Stamp Counter. */
305 unsigned u1TSC : 1;
306 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
307 unsigned u1MSR : 1;
308 /** Bit 6 - PAE - Physical Address Extension. */
309 unsigned u1PAE : 1;
310 /** Bit 7 - MCE - Machine Check Exception. */
311 unsigned u1MCE : 1;
312 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
313 unsigned u1CX8 : 1;
314 /** Bit 9 - APIC - APIC On-Chip. */
315 unsigned u1APIC : 1;
316 /** Bit 10 - Reserved. */
317 unsigned u1Reserved1 : 1;
318 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
319 unsigned u1SEP : 1;
320 /** Bit 12 - MTRR - Memory Type Range Registers. */
321 unsigned u1MTRR : 1;
322 /** Bit 13 - PGE - PTE Global Bit. */
323 unsigned u1PGE : 1;
324 /** Bit 14 - MCA - Machine Check Architecture. */
325 unsigned u1MCA : 1;
326 /** Bit 15 - CMOV - Conditional Move Instructions. */
327 unsigned u1CMOV : 1;
328 /** Bit 16 - PAT - Page Attribute Table. */
329 unsigned u1PAT : 1;
330 /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
331 unsigned u1PSE36 : 1;
332 /** Bit 18 - PSN - Processor Serial Number. */
333 unsigned u1PSN : 1;
334 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
335 unsigned u1CLFSH : 1;
336 /** Bit 20 - Reserved. */
337 unsigned u1Reserved2 : 1;
338 /** Bit 21 - DS - Debug Store. */
339 unsigned u1DS : 1;
340 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
341 unsigned u1ACPI : 1;
342 /** Bit 23 - MMX - Intel MMX 'Technology'. */
343 unsigned u1MMX : 1;
344 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
345 unsigned u1FXSR : 1;
346 /** Bit 25 - SSE - SSE Support. */
347 unsigned u1SSE : 1;
348 /** Bit 26 - SSE2 - SSE2 Support. */
349 unsigned u1SSE2 : 1;
350 /** Bit 27 - SS - Self Snoop. */
351 unsigned u1SS : 1;
352 /** Bit 28 - HTT - Hyper-Threading Technology. */
353 unsigned u1HTT : 1;
354 /** Bit 29 - TM - Thermal Monitor. */
355 unsigned u1TM : 1;
356 /** Bit 30 - Reserved - . */
357 unsigned u1Reserved3 : 1;
358 /** Bit 31 - PBE - Pending Break Enabled. */
359 unsigned u1PBE : 1;
360} X86CPUIDFEATEDX;
361#else /* VBOX_FOR_DTRACE_LIB */
362typedef uint32_t X86CPUIDFEATEDX;
363#endif /* VBOX_FOR_DTRACE_LIB */
364/** Pointer to CPUID Feature Information - EDX. */
365typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
366/** Pointer to const CPUID Feature Information - EDX. */
367typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
368
369/** @name CPUID Vendor information.
370 * CPUID query with EAX=0.
371 * @{
372 */
373#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
374#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
375#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
376
377#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
378#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
379#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
380
381#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
382#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
383#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
384/** @} */
385
386
387/** @name CPUID Feature information.
388 * CPUID query with EAX=1.
389 * @{
390 */
391/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
392#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
393/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
394#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
395/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
396#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
397/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
398#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
399/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
400#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
401/** ECX Bit 5 - VMX - Virtual Machine Technology. */
402#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
403/** ECX Bit 6 - SMX - Safer Mode Extensions. */
404#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
405/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
406#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
407/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
408#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
409/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
410#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
411/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
412#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
413/** ECX Bit 12 - FMA. */
414#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
415/** ECX Bit 13 - CX16 - CMPXCHG16B. */
416#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
417/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
418#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
419/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
420#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
421/** ECX Bit 17 - PCID - Process-context identifiers. */
422#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
423/** ECX Bit 18 - DCA - Direct Cache Access. */
424#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
425/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
426#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
427/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
428#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
429/** ECX Bit 21 - x2APIC support. */
430#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
431/** ECX Bit 22 - MOVBE instruction. */
432#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
433/** ECX Bit 23 - POPCNT instruction. */
434#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
435/** ECX Bir 24 - TSC-Deadline. */
436#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
437/** ECX Bit 25 - AES instructions. */
438#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
439/** ECX Bit 26 - XSAVE instruction. */
440#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
441/** ECX Bit 27 - OSXSAVE instruction. */
442#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
443/** ECX Bit 28 - AVX. */
444#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
445/** ECX Bit 31 - Hypervisor Present (software only). */
446#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
447
448
449/** Bit 0 - FPU - x87 FPU on Chip. */
450#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
451/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
452#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
453/** Bit 2 - DE - Debugging extensions. */
454#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
455/** Bit 3 - PSE - Page Size Extension. */
456#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
457/** Bit 4 - TSC - Time Stamp Counter. */
458#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
459/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
460#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
461/** Bit 6 - PAE - Physical Address Extension. */
462#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
463/** Bit 7 - MCE - Machine Check Exception. */
464#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
465/** Bit 8 - CX8 - CMPXCHG8B instruction. */
466#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
467/** Bit 9 - APIC - APIC On-Chip. */
468#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
469/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
470#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
471/** Bit 12 - MTRR - Memory Type Range Registers. */
472#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
473/** Bit 13 - PGE - PTE Global Bit. */
474#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
475/** Bit 14 - MCA - Machine Check Architecture. */
476#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
477/** Bit 15 - CMOV - Conditional Move Instructions. */
478#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
479/** Bit 16 - PAT - Page Attribute Table. */
480#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
481/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
482#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
483/** Bit 18 - PSN - Processor Serial Number. */
484#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
485/** Bit 19 - CLFSH - CLFLUSH Instruction. */
486#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
487/** Bit 21 - DS - Debug Store. */
488#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
489/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
490#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
491/** Bit 23 - MMX - Intel MMX Technology. */
492#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
493/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
494#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
495/** Bit 25 - SSE - SSE Support. */
496#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
497/** Bit 26 - SSE2 - SSE2 Support. */
498#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
499/** Bit 27 - SS - Self Snoop. */
500#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
501/** Bit 28 - HTT - Hyper-Threading Technology. */
502#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
503/** Bit 29 - TM - Therm. Monitor. */
504#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
505/** Bit 31 - PBE - Pending Break Enabled. */
506#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
507/** @} */
508
509/** @name CPUID mwait/monitor information.
510 * CPUID query with EAX=5.
511 * @{
512 */
513/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
514#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
515/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
516#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
517/** @} */
518
519
520/** @name CPUID Extended Feature information.
521 * CPUID query with EAX=0x80000001.
522 * @{
523 */
524/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
525#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
526
527/** EDX Bit 11 - SYSCALL/SYSRET. */
528#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
529/** EDX Bit 20 - No-Execute/Execute-Disable. */
530#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
531/** EDX Bit 26 - 1 GB large page. */
532#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
533/** EDX Bit 27 - RDTSCP. */
534#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
535/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
536#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
537/** @}*/
538
539/** @name CPUID AMD Feature information.
540 * CPUID query with EAX=0x80000001.
541 * @{
542 */
543/** Bit 0 - FPU - x87 FPU on Chip. */
544#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
545/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
546#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
547/** Bit 2 - DE - Debugging extensions. */
548#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
549/** Bit 3 - PSE - Page Size Extension. */
550#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
551/** Bit 4 - TSC - Time Stamp Counter. */
552#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
553/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
554#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
555/** Bit 6 - PAE - Physical Address Extension. */
556#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
557/** Bit 7 - MCE - Machine Check Exception. */
558#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
559/** Bit 8 - CX8 - CMPXCHG8B instruction. */
560#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
561/** Bit 9 - APIC - APIC On-Chip. */
562#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
563/** Bit 12 - MTRR - Memory Type Range Registers. */
564#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
565/** Bit 13 - PGE - PTE Global Bit. */
566#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
567/** Bit 14 - MCA - Machine Check Architecture. */
568#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
569/** Bit 15 - CMOV - Conditional Move Instructions. */
570#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
571/** Bit 16 - PAT - Page Attribute Table. */
572#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
573/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
574#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
575/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
576#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
577/** Bit 23 - MMX - Intel MMX Technology. */
578#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
579/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
580#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
581/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
582#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
583/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
584#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
585/** Bit 31 - 3DNOW - AMD 3DNow. */
586#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
587
588/** Bit 1 - CMPL - Core multi-processing legacy mode. */
589#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
590/** Bit 2 - SVM - AMD VM extensions. */
591#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
592/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
593#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
594/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
595#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
596/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
597#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
598/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
599#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
600/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
601#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
602/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
603#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
604/** Bit 9 - OSVW - AMD OS visible workaround. */
605#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
606/** Bit 10 - IBS - Instruct based sampling. */
607#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
608/** Bit 11 - SSE5 - SSE5 instruction support. */
609#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
610/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
611#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
612/** Bit 13 - WDT - AMD Watchdog timer support. */
613#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
614
615/** @} */
616
617
618/** @name CPUID AMD Feature information.
619 * CPUID query with EAX=0x80000007.
620 * @{
621 */
622/** Bit 0 - TS - Temperature Sensor. */
623#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
624/** Bit 1 - FID - Frequency ID Control. */
625#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
626/** Bit 2 - VID - Voltage ID Control. */
627#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
628/** Bit 3 - TTP - THERMTRIP. */
629#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
630/** Bit 4 - TM - Hardware Thermal Control. */
631#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
632/** Bit 5 - STC - Software Thermal Control. */
633#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
634/** Bit 6 - MC - 100 Mhz Multiplier Control. */
635#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
636/** Bit 7 - HWPSTATE - Hardware P-State Control. */
637#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
638/** Bit 8 - TSCINVAR - TSC Invariant. */
639#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
640/** @} */
641
642
643/** @name CR0
644 * @{ */
645/** Bit 0 - PE - Protection Enabled */
646#define X86_CR0_PE RT_BIT(0)
647#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
648/** Bit 1 - MP - Monitor Coprocessor */
649#define X86_CR0_MP RT_BIT(1)
650#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
651/** Bit 2 - EM - Emulation. */
652#define X86_CR0_EM RT_BIT(2)
653#define X86_CR0_EMULATE_FPU RT_BIT(2)
654/** Bit 3 - TS - Task Switch. */
655#define X86_CR0_TS RT_BIT(3)
656#define X86_CR0_TASK_SWITCH RT_BIT(3)
657/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
658#define X86_CR0_ET RT_BIT(4)
659#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
660/** Bit 5 - NE - Numeric error. */
661#define X86_CR0_NE RT_BIT(5)
662#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
663/** Bit 16 - WP - Write Protect. */
664#define X86_CR0_WP RT_BIT(16)
665#define X86_CR0_WRITE_PROTECT RT_BIT(16)
666/** Bit 18 - AM - Alignment Mask. */
667#define X86_CR0_AM RT_BIT(18)
668#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
669/** Bit 29 - NW - Not Write-though. */
670#define X86_CR0_NW RT_BIT(29)
671#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
672/** Bit 30 - WP - Cache Disable. */
673#define X86_CR0_CD RT_BIT(30)
674#define X86_CR0_CACHE_DISABLE RT_BIT(30)
675/** Bit 31 - PG - Paging. */
676#define X86_CR0_PG RT_BIT(31)
677#define X86_CR0_PAGING RT_BIT(31)
678/** @} */
679
680
681/** @name CR3
682 * @{ */
683/** Bit 3 - PWT - Page-level Writes Transparent. */
684#define X86_CR3_PWT RT_BIT(3)
685/** Bit 4 - PCD - Page-level Cache Disable. */
686#define X86_CR3_PCD RT_BIT(4)
687/** Bits 12-31 - - Page directory page number. */
688#define X86_CR3_PAGE_MASK (0xfffff000)
689/** Bits 5-31 - - PAE Page directory page number. */
690#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
691/** Bits 12-51 - - AMD64 Page directory page number. */
692#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
693/** @} */
694
695
696/** @name CR4
697 * @{ */
698/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
699#define X86_CR4_VME RT_BIT(0)
700/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
701#define X86_CR4_PVI RT_BIT(1)
702/** Bit 2 - TSD - Time Stamp Disable. */
703#define X86_CR4_TSD RT_BIT(2)
704/** Bit 3 - DE - Debugging Extensions. */
705#define X86_CR4_DE RT_BIT(3)
706/** Bit 4 - PSE - Page Size Extension. */
707#define X86_CR4_PSE RT_BIT(4)
708/** Bit 5 - PAE - Physical Address Extension. */
709#define X86_CR4_PAE RT_BIT(5)
710/** Bit 6 - MCE - Machine-Check Enable. */
711#define X86_CR4_MCE RT_BIT(6)
712/** Bit 7 - PGE - Page Global Enable. */
713#define X86_CR4_PGE RT_BIT(7)
714/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
715#define X86_CR4_PCE RT_BIT(8)
716/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
717#define X86_CR4_OSFSXR RT_BIT(9)
718/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
719#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
720/** Bit 13 - VMXE - VMX mode is enabled. */
721#define X86_CR4_VMXE RT_BIT(13)
722/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
723#define X86_CR4_SMXE RT_BIT(14)
724/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
725#define X86_CR4_PCIDE RT_BIT(17)
726/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
727 * extended states. */
728#define X86_CR4_OSXSAVE RT_BIT(18)
729/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
730#define X86_CR4_SMEP RT_BIT(20)
731/** @} */
732
733
734/** @name DR6
735 * @{ */
736/** Bit 0 - B0 - Breakpoint 0 condition detected. */
737#define X86_DR6_B0 RT_BIT(0)
738/** Bit 1 - B1 - Breakpoint 1 condition detected. */
739#define X86_DR6_B1 RT_BIT(1)
740/** Bit 2 - B2 - Breakpoint 2 condition detected. */
741#define X86_DR6_B2 RT_BIT(2)
742/** Bit 3 - B3 - Breakpoint 3 condition detected. */
743#define X86_DR6_B3 RT_BIT(3)
744/** Mask of all the Bx bits. */
745#define X86_DR6_B_MASK UINT64_C(0x0000000f)
746/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
747#define X86_DR6_BD RT_BIT(13)
748/** Bit 14 - BS - Single step */
749#define X86_DR6_BS RT_BIT(14)
750/** Bit 15 - BT - Task switch. (TSS T bit.) */
751#define X86_DR6_BT RT_BIT(15)
752/** Value of DR6 after powerup/reset. */
753#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
754/** Bits which must be 1s in DR6. */
755#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
756/** Bits which must be 0s in DR6. */
757#define X86_DR6_RAZ_MASK RT_BIT_64(12)
758/** Bits which must be 0s on writes to DR6. */
759#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
760/** @} */
761
762/** Get the DR6.Bx bit for a the given breakpoint. */
763#define X86_DR6_B(iBp) RT_BIT_64(iBp)
764
765
766/** @name DR7
767 * @{ */
768/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
769#define X86_DR7_L0 RT_BIT(0)
770/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
771#define X86_DR7_G0 RT_BIT(1)
772/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
773#define X86_DR7_L1 RT_BIT(2)
774/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
775#define X86_DR7_G1 RT_BIT(3)
776/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
777#define X86_DR7_L2 RT_BIT(4)
778/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
779#define X86_DR7_G2 RT_BIT(5)
780/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
781#define X86_DR7_L3 RT_BIT(6)
782/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
783#define X86_DR7_G3 RT_BIT(7)
784/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
785#define X86_DR7_LE RT_BIT(8)
786/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
787#define X86_DR7_GE RT_BIT(9)
788
789/** L0, L1, L2, and L3. */
790#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
791/** L0, L1, L2, and L3. */
792#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
793
794/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
795 * any DR register is accessed. */
796#define X86_DR7_GD RT_BIT(13)
797/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
798#define X86_DR7_RW0_MASK (3 << 16)
799/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
800#define X86_DR7_LEN0_MASK (3 << 18)
801/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
802#define X86_DR7_RW1_MASK (3 << 20)
803/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
804#define X86_DR7_LEN1_MASK (3 << 22)
805/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
806#define X86_DR7_RW2_MASK (3 << 24)
807/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
808#define X86_DR7_LEN2_MASK (3 << 26)
809/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
810#define X86_DR7_RW3_MASK (3 << 28)
811/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
812#define X86_DR7_LEN3_MASK (3 << 30)
813
814/** Bits which reads as 1s. */
815#define X86_DR7_RA1_MASK (RT_BIT(10))
816/** Bits which reads as zeros. */
817#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
818/** Bits which must be 0s when writing to DR7. */
819#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
820
821/** Calcs the L bit of Nth breakpoint.
822 * @param iBp The breakpoint number [0..3].
823 */
824#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
825
826/** Calcs the G bit of Nth breakpoint.
827 * @param iBp The breakpoint number [0..3].
828 */
829#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
830
831/** Calcs the L and G bits of Nth breakpoint.
832 * @param iBp The breakpoint number [0..3].
833 */
834#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
835
836/** @name Read/Write values.
837 * @{ */
838/** Break on instruction fetch only. */
839#define X86_DR7_RW_EO 0U
840/** Break on write only. */
841#define X86_DR7_RW_WO 1U
842/** Break on I/O read/write. This is only defined if CR4.DE is set. */
843#define X86_DR7_RW_IO 2U
844/** Break on read or write (but not instruction fetches). */
845#define X86_DR7_RW_RW 3U
846/** @} */
847
848/** Shifts a X86_DR7_RW_* value to its right place.
849 * @param iBp The breakpoint number [0..3].
850 * @param fRw One of the X86_DR7_RW_* value.
851 */
852#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
853
854/** Fetch the the R/Wx bits for a given breakpoint (so it can be compared with
855 * one of the X86_DR7_RW_XXX constants).
856 *
857 * @returns X86_DR7_RW_XXX
858 * @param uDR7 DR7 value
859 * @param iBp The breakpoint number [0..3].
860 */
861#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
862
863/** R/W0, R/W1, R/W2, and R/W3. */
864#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
865
866/** Checks if there are any I/O breakpoint types configured in the RW
867 * registers. Does NOT check if these are enabled, sorry. */
868#define X86_DR7_ANY_RW_IO(uDR7) \
869 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
870 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
871AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
872AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
873AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
874AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
875AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
876AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
877AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
878AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
879AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
880
881/** @name Length values.
882 * @{ */
883#define X86_DR7_LEN_BYTE 0U
884#define X86_DR7_LEN_WORD 1U
885#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
886#define X86_DR7_LEN_DWORD 3U
887/** @} */
888
889/** Shifts a X86_DR7_LEN_* value to its right place.
890 * @param iBp The breakpoint number [0..3].
891 * @param cb One of the X86_DR7_LEN_* values.
892 */
893#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
894
895/** Fetch the breakpoint length bits from the DR7 value.
896 * @param uDR7 DR7 value
897 * @param iBp The breakpoint number [0..3].
898 */
899#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
900
901/** Mask used to check if any breakpoints are enabled. */
902#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
903
904/** LEN0, LEN1, LEN2, and LEN3. */
905#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
906/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
907#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
908
909/** Value of DR7 after powerup/reset. */
910#define X86_DR7_INIT_VAL 0x400
911/** @} */
912
913
914/** @name Machine Specific Registers
915 * @{
916 */
917
918/** Time Stamp Counter. */
919#define MSR_IA32_TSC 0x10
920
921#define MSR_IA32_PLATFORM_ID 0x17
922
923#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
924# define MSR_IA32_APICBASE 0x1b
925/** Local APIC enabled. */
926# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
927/** X2APIC enabled (requires the EN bit to be set). */
928# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
929/** The processor is the boot strap processor (BSP). */
930# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
931/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
932 * width. */
933# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
934#endif
935
936/** CPU Feature control. */
937#define MSR_IA32_FEATURE_CONTROL 0x3A
938#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
939#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
940
941/** BIOS update trigger (microcode update). */
942#define MSR_IA32_BIOS_UPDT_TRIG 0x79
943
944/** BIOS update signature (microcode). */
945#define MSR_IA32_BIOS_SIGN_ID 0x8B
946
947/** General performance counter no. 0. */
948#define MSR_IA32_PMC0 0xC1
949/** General performance counter no. 1. */
950#define MSR_IA32_PMC1 0xC2
951/** General performance counter no. 2. */
952#define MSR_IA32_PMC2 0xC3
953/** General performance counter no. 3. */
954#define MSR_IA32_PMC3 0xC4
955
956/** Nehalem power control. */
957#define MSR_IA32_PLATFORM_INFO 0xCE
958
959/** Get FSB clock status (Intel-specific). */
960#define MSR_IA32_FSB_CLOCK_STS 0xCD
961
962/** MTRR Capabilities. */
963#define MSR_IA32_MTRR_CAP 0xFE
964
965
966#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
967/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
968 * R0 SS == CS + 8
969 * R3 CS == CS + 16
970 * R3 SS == CS + 24
971 */
972#define MSR_IA32_SYSENTER_CS 0x174
973/** SYSENTER_ESP - the R0 ESP. */
974#define MSR_IA32_SYSENTER_ESP 0x175
975/** SYSENTER_EIP - the R0 EIP. */
976#define MSR_IA32_SYSENTER_EIP 0x176
977#endif
978
979/** Machine Check Global Capabilities Register. */
980#define MSR_IA32_MCP_CAP 0x179
981/** Machine Check Global Status Register. */
982#define MSR_IA32_MCP_STATUS 0x17A
983/** Machine Check Global Control Register. */
984#define MSR_IA32_MCP_CTRL 0x17B
985
986/** Trace/Profile Resource Control (R/W) */
987#define MSR_IA32_DEBUGCTL 0x1D9
988
989/** Page Attribute Table. */
990#define MSR_IA32_CR_PAT 0x277
991
992/** Performance counter MSRs. (Intel only) */
993#define MSR_IA32_PERFEVTSEL0 0x186
994#define MSR_IA32_PERFEVTSEL1 0x187
995#define MSR_IA32_FLEX_RATIO 0x194
996#define MSR_IA32_PERF_STATUS 0x198
997#define MSR_IA32_PERF_CTL 0x199
998#define MSR_IA32_THERM_STATUS 0x19c
999
1000/** Enable misc. processor features (R/W). */
1001#define MSR_IA32_MISC_ENABLE 0x1A0
1002/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1003#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
1004/** Automatic Thermal Control Circuit Enable (R/W). */
1005#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
1006/** Performance Monitoring Available (R). */
1007#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
1008/** Branch Trace Storage Unavailable (R/O). */
1009#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
1010/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1011#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
1012/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1013#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
1014/** If MONITOR/MWAIT is supported (R/W). */
1015#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
1016/** Limit CPUID Maxval to 3 leafs (R/W). */
1017#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
1018/** When set to 1, xTPR messages are disabled (R/W). */
1019#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
1020/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1021#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
1022
1023#define IA32_MTRR_PHYSBASE0 0x200
1024#define IA32_MTRR_PHYSMASK0 0x201
1025#define IA32_MTRR_PHYSBASE1 0x202
1026#define IA32_MTRR_PHYSMASK1 0x203
1027#define IA32_MTRR_PHYSBASE2 0x204
1028#define IA32_MTRR_PHYSMASK2 0x205
1029#define IA32_MTRR_PHYSBASE3 0x206
1030#define IA32_MTRR_PHYSMASK3 0x207
1031#define IA32_MTRR_PHYSBASE4 0x208
1032#define IA32_MTRR_PHYSMASK4 0x209
1033#define IA32_MTRR_PHYSBASE5 0x20a
1034#define IA32_MTRR_PHYSMASK5 0x20b
1035#define IA32_MTRR_PHYSBASE6 0x20c
1036#define IA32_MTRR_PHYSMASK6 0x20d
1037#define IA32_MTRR_PHYSBASE7 0x20e
1038#define IA32_MTRR_PHYSMASK7 0x20f
1039#define IA32_MTRR_PHYSBASE8 0x210
1040#define IA32_MTRR_PHYSMASK8 0x211
1041#define IA32_MTRR_PHYSBASE9 0x212
1042#define IA32_MTRR_PHYSMASK9 0x213
1043
1044/** Fixed range MTRRs.
1045 * @{ */
1046#define IA32_MTRR_FIX64K_00000 0x250
1047#define IA32_MTRR_FIX16K_80000 0x258
1048#define IA32_MTRR_FIX16K_A0000 0x259
1049#define IA32_MTRR_FIX4K_C0000 0x268
1050#define IA32_MTRR_FIX4K_C8000 0x269
1051#define IA32_MTRR_FIX4K_D0000 0x26a
1052#define IA32_MTRR_FIX4K_D8000 0x26b
1053#define IA32_MTRR_FIX4K_E0000 0x26c
1054#define IA32_MTRR_FIX4K_E8000 0x26d
1055#define IA32_MTRR_FIX4K_F0000 0x26e
1056#define IA32_MTRR_FIX4K_F8000 0x26f
1057/** @} */
1058
1059/** MTRR Default Range. */
1060#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1061
1062#define MSR_IA32_MC0_CTL 0x400
1063#define MSR_IA32_MC0_STATUS 0x401
1064
1065/** Basic VMX information. */
1066#define MSR_IA32_VMX_BASIC_INFO 0x480
1067/** Allowed settings for pin-based VM execution controls */
1068#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1069/** Allowed settings for proc-based VM execution controls */
1070#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1071/** Allowed settings for the VMX exit controls. */
1072#define MSR_IA32_VMX_EXIT_CTLS 0x483
1073/** Allowed settings for the VMX entry controls. */
1074#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1075/** Misc VMX info. */
1076#define MSR_IA32_VMX_MISC 0x485
1077/** Fixed cleared bits in CR0. */
1078#define MSR_IA32_VMX_CR0_FIXED0 0x486
1079/** Fixed set bits in CR0. */
1080#define MSR_IA32_VMX_CR0_FIXED1 0x487
1081/** Fixed cleared bits in CR4. */
1082#define MSR_IA32_VMX_CR4_FIXED0 0x488
1083/** Fixed set bits in CR4. */
1084#define MSR_IA32_VMX_CR4_FIXED1 0x489
1085/** Information for enumerating fields in the VMCS. */
1086#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1087/** Allowed settings for the VM-functions controls. */
1088#define MSR_IA32_VMX_VMFUNC 0x491
1089/** Allowed settings for secondary proc-based VM execution controls */
1090#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1091/** EPT capabilities. */
1092#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1093/** DS Save Area (R/W). */
1094#define MSR_IA32_DS_AREA 0x600
1095/** Running Average Power Limit (RAPL) power units. */
1096#define MSR_RAPL_POWER_UNIT 0x606
1097/** X2APIC MSR ranges. */
1098#define MSR_IA32_X2APIC_START 0x800
1099#define MSR_IA32_X2APIC_TPR 0x808
1100#define MSR_IA32_X2APIC_END 0xBFF
1101
1102/** K6 EFER - Extended Feature Enable Register. */
1103#define MSR_K6_EFER 0xc0000080
1104/** @todo document EFER */
1105/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1106#define MSR_K6_EFER_SCE RT_BIT(0)
1107/** Bit 8 - LME - Long mode enabled. (R/W) */
1108#define MSR_K6_EFER_LME RT_BIT(8)
1109/** Bit 10 - LMA - Long mode active. (R) */
1110#define MSR_K6_EFER_LMA RT_BIT(10)
1111/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1112#define MSR_K6_EFER_NXE RT_BIT(11)
1113/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1114#define MSR_K6_EFER_SVME RT_BIT(12)
1115/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1116#define MSR_K6_EFER_LMSLE RT_BIT(13)
1117/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1118#define MSR_K6_EFER_FFXSR RT_BIT(14)
1119/** K6 STAR - SYSCALL/RET targets. */
1120#define MSR_K6_STAR 0xc0000081
1121/** Shift value for getting the SYSRET CS and SS value. */
1122#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1123/** Shift value for getting the SYSCALL CS and SS value. */
1124#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1125/** Selector mask for use after shifting. */
1126#define MSR_K6_STAR_SEL_MASK 0xffff
1127/** The mask which give the SYSCALL EIP. */
1128#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1129/** K6 WHCR - Write Handling Control Register. */
1130#define MSR_K6_WHCR 0xc0000082
1131/** K6 UWCCR - UC/WC Cacheability Control Register. */
1132#define MSR_K6_UWCCR 0xc0000085
1133/** K6 PSOR - Processor State Observability Register. */
1134#define MSR_K6_PSOR 0xc0000087
1135/** K6 PFIR - Page Flush/Invalidate Register. */
1136#define MSR_K6_PFIR 0xc0000088
1137
1138/** Performance counter MSRs. (AMD only) */
1139#define MSR_K7_EVNTSEL0 0xc0010000
1140#define MSR_K7_EVNTSEL1 0xc0010001
1141#define MSR_K7_EVNTSEL2 0xc0010002
1142#define MSR_K7_EVNTSEL3 0xc0010003
1143#define MSR_K7_PERFCTR0 0xc0010004
1144#define MSR_K7_PERFCTR1 0xc0010005
1145#define MSR_K7_PERFCTR2 0xc0010006
1146#define MSR_K7_PERFCTR3 0xc0010007
1147
1148/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1149#define MSR_K8_LSTAR 0xc0000082
1150/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1151#define MSR_K8_CSTAR 0xc0000083
1152/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1153#define MSR_K8_SF_MASK 0xc0000084
1154/** K8 FS.base - The 64-bit base FS register. */
1155#define MSR_K8_FS_BASE 0xc0000100
1156/** K8 GS.base - The 64-bit base GS register. */
1157#define MSR_K8_GS_BASE 0xc0000101
1158/** K8 KernelGSbase - Used with SWAPGS. */
1159#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1160/** K8 TSC_AUX - Used with RDTSCP. */
1161#define MSR_K8_TSC_AUX 0xc0000103
1162#define MSR_K8_SYSCFG 0xc0010010
1163#define MSR_K8_HWCR 0xc0010015
1164#define MSR_K8_IORRBASE0 0xc0010016
1165#define MSR_K8_IORRMASK0 0xc0010017
1166#define MSR_K8_IORRBASE1 0xc0010018
1167#define MSR_K8_IORRMASK1 0xc0010019
1168#define MSR_K8_TOP_MEM1 0xc001001a
1169#define MSR_K8_TOP_MEM2 0xc001001d
1170/** Hypertransport interrupt pending register.
1171 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1172#define MSR_K8_INT_PENDING 0xc0010055
1173#define MSR_K8_VM_CR 0xc0010114
1174#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1175
1176#define MSR_K8_IGNNE 0xc0010115
1177#define MSR_K8_SMM_CTL 0xc0010116
1178/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1179 * host state during world switch.
1180 */
1181#define MSR_K8_VM_HSAVE_PA 0xc0010117
1182
1183/** @} */
1184
1185
1186/** @name Page Table / Directory / Directory Pointers / L4.
1187 * @{
1188 */
1189
1190/** Page table/directory entry as an unsigned integer. */
1191typedef uint32_t X86PGUINT;
1192/** Pointer to a page table/directory table entry as an unsigned integer. */
1193typedef X86PGUINT *PX86PGUINT;
1194/** Pointer to an const page table/directory table entry as an unsigned integer. */
1195typedef X86PGUINT const *PCX86PGUINT;
1196
1197/** Number of entries in a 32-bit PT/PD. */
1198#define X86_PG_ENTRIES 1024
1199
1200
1201/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1202typedef uint64_t X86PGPAEUINT;
1203/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1204typedef X86PGPAEUINT *PX86PGPAEUINT;
1205/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1206typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1207
1208/** Number of entries in a PAE PT/PD. */
1209#define X86_PG_PAE_ENTRIES 512
1210/** Number of entries in a PAE PDPT. */
1211#define X86_PG_PAE_PDPE_ENTRIES 4
1212
1213/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1214#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1215/** Number of entries in an AMD64 PDPT.
1216 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1217#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1218
1219/** The size of a 4KB page. */
1220#define X86_PAGE_4K_SIZE _4K
1221/** The page shift of a 4KB page. */
1222#define X86_PAGE_4K_SHIFT 12
1223/** The 4KB page offset mask. */
1224#define X86_PAGE_4K_OFFSET_MASK 0xfff
1225/** The 4KB page base mask for virtual addresses. */
1226#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1227/** The 4KB page base mask for virtual addresses - 32bit version. */
1228#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1229
1230/** The size of a 2MB page. */
1231#define X86_PAGE_2M_SIZE _2M
1232/** The page shift of a 2MB page. */
1233#define X86_PAGE_2M_SHIFT 21
1234/** The 2MB page offset mask. */
1235#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1236/** The 2MB page base mask for virtual addresses. */
1237#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1238/** The 2MB page base mask for virtual addresses - 32bit version. */
1239#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1240
1241/** The size of a 4MB page. */
1242#define X86_PAGE_4M_SIZE _4M
1243/** The page shift of a 4MB page. */
1244#define X86_PAGE_4M_SHIFT 22
1245/** The 4MB page offset mask. */
1246#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1247/** The 4MB page base mask for virtual addresses. */
1248#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1249/** The 4MB page base mask for virtual addresses - 32bit version. */
1250#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1251
1252
1253
1254/** @name Page Table Entry
1255 * @{
1256 */
1257/** Bit 0 - P - Present bit. */
1258#define X86_PTE_BIT_P 0
1259/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1260#define X86_PTE_BIT_RW 1
1261/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1262#define X86_PTE_BIT_US 2
1263/** Bit 3 - PWT - Page level write thru bit. */
1264#define X86_PTE_BIT_PWT 3
1265/** Bit 4 - PCD - Page level cache disable bit. */
1266#define X86_PTE_BIT_PCD 4
1267/** Bit 5 - A - Access bit. */
1268#define X86_PTE_BIT_A 5
1269/** Bit 6 - D - Dirty bit. */
1270#define X86_PTE_BIT_D 6
1271/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1272#define X86_PTE_BIT_PAT 7
1273/** Bit 8 - G - Global flag. */
1274#define X86_PTE_BIT_G 8
1275
1276/** Bit 0 - P - Present bit mask. */
1277#define X86_PTE_P RT_BIT(0)
1278/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1279#define X86_PTE_RW RT_BIT(1)
1280/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1281#define X86_PTE_US RT_BIT(2)
1282/** Bit 3 - PWT - Page level write thru bit mask. */
1283#define X86_PTE_PWT RT_BIT(3)
1284/** Bit 4 - PCD - Page level cache disable bit mask. */
1285#define X86_PTE_PCD RT_BIT(4)
1286/** Bit 5 - A - Access bit mask. */
1287#define X86_PTE_A RT_BIT(5)
1288/** Bit 6 - D - Dirty bit mask. */
1289#define X86_PTE_D RT_BIT(6)
1290/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1291#define X86_PTE_PAT RT_BIT(7)
1292/** Bit 8 - G - Global bit mask. */
1293#define X86_PTE_G RT_BIT(8)
1294
1295/** Bits 9-11 - - Available for use to system software. */
1296#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1297/** Bits 12-31 - - Physical Page number of the next level. */
1298#define X86_PTE_PG_MASK ( 0xfffff000 )
1299
1300/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1301#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1302/** Bits 63 - NX - PAE/LM - No execution flag. */
1303#define X86_PTE_PAE_NX RT_BIT_64(63)
1304/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1305#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1306/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1307#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1308/** No bits - - LM - MBZ bits when NX is active. */
1309#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1310/** Bits 63 - - LM - MBZ bits when no NX. */
1311#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1312
1313/**
1314 * Page table entry.
1315 */
1316typedef struct X86PTEBITS
1317{
1318 /** Flags whether(=1) or not the page is present. */
1319 unsigned u1Present : 1;
1320 /** Read(=0) / Write(=1) flag. */
1321 unsigned u1Write : 1;
1322 /** User(=1) / Supervisor (=0) flag. */
1323 unsigned u1User : 1;
1324 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1325 unsigned u1WriteThru : 1;
1326 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1327 unsigned u1CacheDisable : 1;
1328 /** Accessed flag.
1329 * Indicates that the page have been read or written to. */
1330 unsigned u1Accessed : 1;
1331 /** Dirty flag.
1332 * Indicates that the page has been written to. */
1333 unsigned u1Dirty : 1;
1334 /** Reserved / If PAT enabled, bit 2 of the index. */
1335 unsigned u1PAT : 1;
1336 /** Global flag. (Ignored in all but final level.) */
1337 unsigned u1Global : 1;
1338 /** Available for use to system software. */
1339 unsigned u3Available : 3;
1340 /** Physical Page number of the next level. */
1341 unsigned u20PageNo : 20;
1342} X86PTEBITS;
1343/** Pointer to a page table entry. */
1344typedef X86PTEBITS *PX86PTEBITS;
1345/** Pointer to a const page table entry. */
1346typedef const X86PTEBITS *PCX86PTEBITS;
1347
1348/**
1349 * Page table entry.
1350 */
1351typedef union X86PTE
1352{
1353 /** Unsigned integer view */
1354 X86PGUINT u;
1355 /** Bit field view. */
1356 X86PTEBITS n;
1357 /** 32-bit view. */
1358 uint32_t au32[1];
1359 /** 16-bit view. */
1360 uint16_t au16[2];
1361 /** 8-bit view. */
1362 uint8_t au8[4];
1363} X86PTE;
1364/** Pointer to a page table entry. */
1365typedef X86PTE *PX86PTE;
1366/** Pointer to a const page table entry. */
1367typedef const X86PTE *PCX86PTE;
1368
1369
1370/**
1371 * PAE page table entry.
1372 */
1373typedef struct X86PTEPAEBITS
1374{
1375 /** Flags whether(=1) or not the page is present. */
1376 uint32_t u1Present : 1;
1377 /** Read(=0) / Write(=1) flag. */
1378 uint32_t u1Write : 1;
1379 /** User(=1) / Supervisor(=0) flag. */
1380 uint32_t u1User : 1;
1381 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1382 uint32_t u1WriteThru : 1;
1383 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1384 uint32_t u1CacheDisable : 1;
1385 /** Accessed flag.
1386 * Indicates that the page have been read or written to. */
1387 uint32_t u1Accessed : 1;
1388 /** Dirty flag.
1389 * Indicates that the page has been written to. */
1390 uint32_t u1Dirty : 1;
1391 /** Reserved / If PAT enabled, bit 2 of the index. */
1392 uint32_t u1PAT : 1;
1393 /** Global flag. (Ignored in all but final level.) */
1394 uint32_t u1Global : 1;
1395 /** Available for use to system software. */
1396 uint32_t u3Available : 3;
1397 /** Physical Page number of the next level - Low Part. Don't use this. */
1398 uint32_t u20PageNoLow : 20;
1399 /** Physical Page number of the next level - High Part. Don't use this. */
1400 uint32_t u20PageNoHigh : 20;
1401 /** MBZ bits */
1402 uint32_t u11Reserved : 11;
1403 /** No Execute flag. */
1404 uint32_t u1NoExecute : 1;
1405} X86PTEPAEBITS;
1406/** Pointer to a page table entry. */
1407typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1408/** Pointer to a page table entry. */
1409typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1410
1411/**
1412 * PAE Page table entry.
1413 */
1414typedef union X86PTEPAE
1415{
1416 /** Unsigned integer view */
1417 X86PGPAEUINT u;
1418 /** Bit field view. */
1419 X86PTEPAEBITS n;
1420 /** 32-bit view. */
1421 uint32_t au32[2];
1422 /** 16-bit view. */
1423 uint16_t au16[4];
1424 /** 8-bit view. */
1425 uint8_t au8[8];
1426} X86PTEPAE;
1427/** Pointer to a PAE page table entry. */
1428typedef X86PTEPAE *PX86PTEPAE;
1429/** Pointer to a const PAE page table entry. */
1430typedef const X86PTEPAE *PCX86PTEPAE;
1431/** @} */
1432
1433/**
1434 * Page table.
1435 */
1436typedef struct X86PT
1437{
1438 /** PTE Array. */
1439 X86PTE a[X86_PG_ENTRIES];
1440} X86PT;
1441/** Pointer to a page table. */
1442typedef X86PT *PX86PT;
1443/** Pointer to a const page table. */
1444typedef const X86PT *PCX86PT;
1445
1446/** The page shift to get the PT index. */
1447#define X86_PT_SHIFT 12
1448/** The PT index mask (apply to a shifted page address). */
1449#define X86_PT_MASK 0x3ff
1450
1451
1452/**
1453 * Page directory.
1454 */
1455typedef struct X86PTPAE
1456{
1457 /** PTE Array. */
1458 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1459} X86PTPAE;
1460/** Pointer to a page table. */
1461typedef X86PTPAE *PX86PTPAE;
1462/** Pointer to a const page table. */
1463typedef const X86PTPAE *PCX86PTPAE;
1464
1465/** The page shift to get the PA PTE index. */
1466#define X86_PT_PAE_SHIFT 12
1467/** The PAE PT index mask (apply to a shifted page address). */
1468#define X86_PT_PAE_MASK 0x1ff
1469
1470
1471/** @name 4KB Page Directory Entry
1472 * @{
1473 */
1474/** Bit 0 - P - Present bit. */
1475#define X86_PDE_P RT_BIT(0)
1476/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1477#define X86_PDE_RW RT_BIT(1)
1478/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1479#define X86_PDE_US RT_BIT(2)
1480/** Bit 3 - PWT - Page level write thru bit. */
1481#define X86_PDE_PWT RT_BIT(3)
1482/** Bit 4 - PCD - Page level cache disable bit. */
1483#define X86_PDE_PCD RT_BIT(4)
1484/** Bit 5 - A - Access bit. */
1485#define X86_PDE_A RT_BIT(5)
1486/** Bit 7 - PS - Page size attribute.
1487 * Clear mean 4KB pages, set means large pages (2/4MB). */
1488#define X86_PDE_PS RT_BIT(7)
1489/** Bits 9-11 - - Available for use to system software. */
1490#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1491/** Bits 12-31 - - Physical Page number of the next level. */
1492#define X86_PDE_PG_MASK ( 0xfffff000 )
1493
1494/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1495#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1496/** Bits 63 - NX - PAE/LM - No execution flag. */
1497#define X86_PDE_PAE_NX RT_BIT_64(63)
1498/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1499#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1500/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1501#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1502/** Bit 7 - - LM - MBZ bits when NX is active. */
1503#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1504/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1505#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1506
1507/**
1508 * Page directory entry.
1509 */
1510typedef struct X86PDEBITS
1511{
1512 /** Flags whether(=1) or not the page is present. */
1513 unsigned u1Present : 1;
1514 /** Read(=0) / Write(=1) flag. */
1515 unsigned u1Write : 1;
1516 /** User(=1) / Supervisor (=0) flag. */
1517 unsigned u1User : 1;
1518 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1519 unsigned u1WriteThru : 1;
1520 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1521 unsigned u1CacheDisable : 1;
1522 /** Accessed flag.
1523 * Indicates that the page has been read or written to. */
1524 unsigned u1Accessed : 1;
1525 /** Reserved / Ignored (dirty bit). */
1526 unsigned u1Reserved0 : 1;
1527 /** Size bit if PSE is enabled - in any event it's 0. */
1528 unsigned u1Size : 1;
1529 /** Reserved / Ignored (global bit). */
1530 unsigned u1Reserved1 : 1;
1531 /** Available for use to system software. */
1532 unsigned u3Available : 3;
1533 /** Physical Page number of the next level. */
1534 unsigned u20PageNo : 20;
1535} X86PDEBITS;
1536/** Pointer to a page directory entry. */
1537typedef X86PDEBITS *PX86PDEBITS;
1538/** Pointer to a const page directory entry. */
1539typedef const X86PDEBITS *PCX86PDEBITS;
1540
1541
1542/**
1543 * PAE page directory entry.
1544 */
1545typedef struct X86PDEPAEBITS
1546{
1547 /** Flags whether(=1) or not the page is present. */
1548 uint32_t u1Present : 1;
1549 /** Read(=0) / Write(=1) flag. */
1550 uint32_t u1Write : 1;
1551 /** User(=1) / Supervisor (=0) flag. */
1552 uint32_t u1User : 1;
1553 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1554 uint32_t u1WriteThru : 1;
1555 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1556 uint32_t u1CacheDisable : 1;
1557 /** Accessed flag.
1558 * Indicates that the page has been read or written to. */
1559 uint32_t u1Accessed : 1;
1560 /** Reserved / Ignored (dirty bit). */
1561 uint32_t u1Reserved0 : 1;
1562 /** Size bit if PSE is enabled - in any event it's 0. */
1563 uint32_t u1Size : 1;
1564 /** Reserved / Ignored (global bit). / */
1565 uint32_t u1Reserved1 : 1;
1566 /** Available for use to system software. */
1567 uint32_t u3Available : 3;
1568 /** Physical Page number of the next level - Low Part. Don't use! */
1569 uint32_t u20PageNoLow : 20;
1570 /** Physical Page number of the next level - High Part. Don't use! */
1571 uint32_t u20PageNoHigh : 20;
1572 /** MBZ bits */
1573 uint32_t u11Reserved : 11;
1574 /** No Execute flag. */
1575 uint32_t u1NoExecute : 1;
1576} X86PDEPAEBITS;
1577/** Pointer to a page directory entry. */
1578typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1579/** Pointer to a const page directory entry. */
1580typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1581
1582/** @} */
1583
1584
1585/** @name 2/4MB Page Directory Entry
1586 * @{
1587 */
1588/** Bit 0 - P - Present bit. */
1589#define X86_PDE4M_P RT_BIT(0)
1590/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1591#define X86_PDE4M_RW RT_BIT(1)
1592/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1593#define X86_PDE4M_US RT_BIT(2)
1594/** Bit 3 - PWT - Page level write thru bit. */
1595#define X86_PDE4M_PWT RT_BIT(3)
1596/** Bit 4 - PCD - Page level cache disable bit. */
1597#define X86_PDE4M_PCD RT_BIT(4)
1598/** Bit 5 - A - Access bit. */
1599#define X86_PDE4M_A RT_BIT(5)
1600/** Bit 6 - D - Dirty bit. */
1601#define X86_PDE4M_D RT_BIT(6)
1602/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1603#define X86_PDE4M_PS RT_BIT(7)
1604/** Bit 8 - G - Global flag. */
1605#define X86_PDE4M_G RT_BIT(8)
1606/** Bits 9-11 - AVL - Available for use to system software. */
1607#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1608/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1609#define X86_PDE4M_PAT RT_BIT(12)
1610/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1611#define X86_PDE4M_PAT_SHIFT (12 - 7)
1612/** Bits 22-31 - - Physical Page number. */
1613#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1614/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1615#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1616/** The number of bits to the high part of the page number. */
1617#define X86_PDE4M_PG_HIGH_SHIFT 19
1618/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1619#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1620
1621/** Bits 21-51 - - PAE/LM - Physical Page number.
1622 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1623#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1624/** Bits 63 - NX - PAE/LM - No execution flag. */
1625#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1626/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1627#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1628/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1629#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1630/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1631#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1632/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1633#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1634
1635/**
1636 * 4MB page directory entry.
1637 */
1638typedef struct X86PDE4MBITS
1639{
1640 /** Flags whether(=1) or not the page is present. */
1641 unsigned u1Present : 1;
1642 /** Read(=0) / Write(=1) flag. */
1643 unsigned u1Write : 1;
1644 /** User(=1) / Supervisor (=0) flag. */
1645 unsigned u1User : 1;
1646 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1647 unsigned u1WriteThru : 1;
1648 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1649 unsigned u1CacheDisable : 1;
1650 /** Accessed flag.
1651 * Indicates that the page have been read or written to. */
1652 unsigned u1Accessed : 1;
1653 /** Dirty flag.
1654 * Indicates that the page has been written to. */
1655 unsigned u1Dirty : 1;
1656 /** Page size flag - always 1 for 4MB entries. */
1657 unsigned u1Size : 1;
1658 /** Global flag. */
1659 unsigned u1Global : 1;
1660 /** Available for use to system software. */
1661 unsigned u3Available : 3;
1662 /** Reserved / If PAT enabled, bit 2 of the index. */
1663 unsigned u1PAT : 1;
1664 /** Bits 32-39 of the page number on AMD64.
1665 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1666 unsigned u8PageNoHigh : 8;
1667 /** Reserved. */
1668 unsigned u1Reserved : 1;
1669 /** Physical Page number of the page. */
1670 unsigned u10PageNo : 10;
1671} X86PDE4MBITS;
1672/** Pointer to a page table entry. */
1673typedef X86PDE4MBITS *PX86PDE4MBITS;
1674/** Pointer to a const page table entry. */
1675typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1676
1677
1678/**
1679 * 2MB PAE page directory entry.
1680 */
1681typedef struct X86PDE2MPAEBITS
1682{
1683 /** Flags whether(=1) or not the page is present. */
1684 uint32_t u1Present : 1;
1685 /** Read(=0) / Write(=1) flag. */
1686 uint32_t u1Write : 1;
1687 /** User(=1) / Supervisor(=0) flag. */
1688 uint32_t u1User : 1;
1689 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1690 uint32_t u1WriteThru : 1;
1691 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1692 uint32_t u1CacheDisable : 1;
1693 /** Accessed flag.
1694 * Indicates that the page have been read or written to. */
1695 uint32_t u1Accessed : 1;
1696 /** Dirty flag.
1697 * Indicates that the page has been written to. */
1698 uint32_t u1Dirty : 1;
1699 /** Page size flag - always 1 for 2MB entries. */
1700 uint32_t u1Size : 1;
1701 /** Global flag. */
1702 uint32_t u1Global : 1;
1703 /** Available for use to system software. */
1704 uint32_t u3Available : 3;
1705 /** Reserved / If PAT enabled, bit 2 of the index. */
1706 uint32_t u1PAT : 1;
1707 /** Reserved. */
1708 uint32_t u9Reserved : 9;
1709 /** Physical Page number of the next level - Low part. Don't use! */
1710 uint32_t u10PageNoLow : 10;
1711 /** Physical Page number of the next level - High part. Don't use! */
1712 uint32_t u20PageNoHigh : 20;
1713 /** MBZ bits */
1714 uint32_t u11Reserved : 11;
1715 /** No Execute flag. */
1716 uint32_t u1NoExecute : 1;
1717} X86PDE2MPAEBITS;
1718/** Pointer to a 2MB PAE page table entry. */
1719typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1720/** Pointer to a 2MB PAE page table entry. */
1721typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1722
1723/** @} */
1724
1725/**
1726 * Page directory entry.
1727 */
1728typedef union X86PDE
1729{
1730 /** Unsigned integer view. */
1731 X86PGUINT u;
1732 /** Normal view. */
1733 X86PDEBITS n;
1734 /** 4MB view (big). */
1735 X86PDE4MBITS b;
1736 /** 8 bit unsigned integer view. */
1737 uint8_t au8[4];
1738 /** 16 bit unsigned integer view. */
1739 uint16_t au16[2];
1740 /** 32 bit unsigned integer view. */
1741 uint32_t au32[1];
1742} X86PDE;
1743/** Pointer to a page directory entry. */
1744typedef X86PDE *PX86PDE;
1745/** Pointer to a const page directory entry. */
1746typedef const X86PDE *PCX86PDE;
1747
1748/**
1749 * PAE page directory entry.
1750 */
1751typedef union X86PDEPAE
1752{
1753 /** Unsigned integer view. */
1754 X86PGPAEUINT u;
1755 /** Normal view. */
1756 X86PDEPAEBITS n;
1757 /** 2MB page view (big). */
1758 X86PDE2MPAEBITS b;
1759 /** 8 bit unsigned integer view. */
1760 uint8_t au8[8];
1761 /** 16 bit unsigned integer view. */
1762 uint16_t au16[4];
1763 /** 32 bit unsigned integer view. */
1764 uint32_t au32[2];
1765} X86PDEPAE;
1766/** Pointer to a page directory entry. */
1767typedef X86PDEPAE *PX86PDEPAE;
1768/** Pointer to a const page directory entry. */
1769typedef const X86PDEPAE *PCX86PDEPAE;
1770
1771/**
1772 * Page directory.
1773 */
1774typedef struct X86PD
1775{
1776 /** PDE Array. */
1777 X86PDE a[X86_PG_ENTRIES];
1778} X86PD;
1779/** Pointer to a page directory. */
1780typedef X86PD *PX86PD;
1781/** Pointer to a const page directory. */
1782typedef const X86PD *PCX86PD;
1783
1784/** The page shift to get the PD index. */
1785#define X86_PD_SHIFT 22
1786/** The PD index mask (apply to a shifted page address). */
1787#define X86_PD_MASK 0x3ff
1788
1789
1790/**
1791 * PAE page directory.
1792 */
1793typedef struct X86PDPAE
1794{
1795 /** PDE Array. */
1796 X86PDEPAE a[X86_PG_PAE_ENTRIES];
1797} X86PDPAE;
1798/** Pointer to a PAE page directory. */
1799typedef X86PDPAE *PX86PDPAE;
1800/** Pointer to a const PAE page directory. */
1801typedef const X86PDPAE *PCX86PDPAE;
1802
1803/** The page shift to get the PAE PD index. */
1804#define X86_PD_PAE_SHIFT 21
1805/** The PAE PD index mask (apply to a shifted page address). */
1806#define X86_PD_PAE_MASK 0x1ff
1807
1808
1809/** @name Page Directory Pointer Table Entry (PAE)
1810 * @{
1811 */
1812/** Bit 0 - P - Present bit. */
1813#define X86_PDPE_P RT_BIT(0)
1814/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1815#define X86_PDPE_RW RT_BIT(1)
1816/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1817#define X86_PDPE_US RT_BIT(2)
1818/** Bit 3 - PWT - Page level write thru bit. */
1819#define X86_PDPE_PWT RT_BIT(3)
1820/** Bit 4 - PCD - Page level cache disable bit. */
1821#define X86_PDPE_PCD RT_BIT(4)
1822/** Bit 5 - A - Access bit. Long Mode only. */
1823#define X86_PDPE_A RT_BIT(5)
1824/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1825#define X86_PDPE_LM_PS RT_BIT(7)
1826/** Bits 9-11 - - Available for use to system software. */
1827#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1828/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1829#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1830/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1831#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1832/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1833#define X86_PDPE_LM_NX RT_BIT_64(63)
1834/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1835#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1836/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1837#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1838/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1839#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1840/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1841#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1842
1843
1844/**
1845 * Page directory pointer table entry.
1846 */
1847typedef struct X86PDPEBITS
1848{
1849 /** Flags whether(=1) or not the page is present. */
1850 uint32_t u1Present : 1;
1851 /** Chunk of reserved bits. */
1852 uint32_t u2Reserved : 2;
1853 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1854 uint32_t u1WriteThru : 1;
1855 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1856 uint32_t u1CacheDisable : 1;
1857 /** Chunk of reserved bits. */
1858 uint32_t u4Reserved : 4;
1859 /** Available for use to system software. */
1860 uint32_t u3Available : 3;
1861 /** Physical Page number of the next level - Low Part. Don't use! */
1862 uint32_t u20PageNoLow : 20;
1863 /** Physical Page number of the next level - High Part. Don't use! */
1864 uint32_t u20PageNoHigh : 20;
1865 /** MBZ bits */
1866 uint32_t u12Reserved : 12;
1867} X86PDPEBITS;
1868/** Pointer to a page directory pointer table entry. */
1869typedef X86PDPEBITS *PX86PTPEBITS;
1870/** Pointer to a const page directory pointer table entry. */
1871typedef const X86PDPEBITS *PCX86PTPEBITS;
1872
1873/**
1874 * Page directory pointer table entry. AMD64 version
1875 */
1876typedef struct X86PDPEAMD64BITS
1877{
1878 /** Flags whether(=1) or not the page is present. */
1879 uint32_t u1Present : 1;
1880 /** Read(=0) / Write(=1) flag. */
1881 uint32_t u1Write : 1;
1882 /** User(=1) / Supervisor (=0) flag. */
1883 uint32_t u1User : 1;
1884 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1885 uint32_t u1WriteThru : 1;
1886 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1887 uint32_t u1CacheDisable : 1;
1888 /** Accessed flag.
1889 * Indicates that the page have been read or written to. */
1890 uint32_t u1Accessed : 1;
1891 /** Chunk of reserved bits. */
1892 uint32_t u3Reserved : 3;
1893 /** Available for use to system software. */
1894 uint32_t u3Available : 3;
1895 /** Physical Page number of the next level - Low Part. Don't use! */
1896 uint32_t u20PageNoLow : 20;
1897 /** Physical Page number of the next level - High Part. Don't use! */
1898 uint32_t u20PageNoHigh : 20;
1899 /** MBZ bits */
1900 uint32_t u11Reserved : 11;
1901 /** No Execute flag. */
1902 uint32_t u1NoExecute : 1;
1903} X86PDPEAMD64BITS;
1904/** Pointer to a page directory pointer table entry. */
1905typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1906/** Pointer to a const page directory pointer table entry. */
1907typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1908
1909/**
1910 * Page directory pointer table entry.
1911 */
1912typedef union X86PDPE
1913{
1914 /** Unsigned integer view. */
1915 X86PGPAEUINT u;
1916 /** Normal view. */
1917 X86PDPEBITS n;
1918 /** AMD64 view. */
1919 X86PDPEAMD64BITS lm;
1920 /** 8 bit unsigned integer view. */
1921 uint8_t au8[8];
1922 /** 16 bit unsigned integer view. */
1923 uint16_t au16[4];
1924 /** 32 bit unsigned integer view. */
1925 uint32_t au32[2];
1926} X86PDPE;
1927/** Pointer to a page directory pointer table entry. */
1928typedef X86PDPE *PX86PDPE;
1929/** Pointer to a const page directory pointer table entry. */
1930typedef const X86PDPE *PCX86PDPE;
1931
1932
1933/**
1934 * Page directory pointer table.
1935 */
1936typedef struct X86PDPT
1937{
1938 /** PDE Array. */
1939 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1940} X86PDPT;
1941/** Pointer to a page directory pointer table. */
1942typedef X86PDPT *PX86PDPT;
1943/** Pointer to a const page directory pointer table. */
1944typedef const X86PDPT *PCX86PDPT;
1945
1946/** The page shift to get the PDPT index. */
1947#define X86_PDPT_SHIFT 30
1948/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1949#define X86_PDPT_MASK_PAE 0x3
1950/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1951#define X86_PDPT_MASK_AMD64 0x1ff
1952
1953/** @} */
1954
1955
1956/** @name Page Map Level-4 Entry (Long Mode PAE)
1957 * @{
1958 */
1959/** Bit 0 - P - Present bit. */
1960#define X86_PML4E_P RT_BIT(0)
1961/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1962#define X86_PML4E_RW RT_BIT(1)
1963/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1964#define X86_PML4E_US RT_BIT(2)
1965/** Bit 3 - PWT - Page level write thru bit. */
1966#define X86_PML4E_PWT RT_BIT(3)
1967/** Bit 4 - PCD - Page level cache disable bit. */
1968#define X86_PML4E_PCD RT_BIT(4)
1969/** Bit 5 - A - Access bit. */
1970#define X86_PML4E_A RT_BIT(5)
1971/** Bits 9-11 - - Available for use to system software. */
1972#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1973/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1974#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1975/** Bits 8, 7 - - MBZ bits when NX is active. */
1976#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1977/** Bits 63, 7 - - MBZ bits when no NX. */
1978#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1979/** Bits 63 - NX - PAE - No execution flag. */
1980#define X86_PML4E_NX RT_BIT_64(63)
1981
1982/**
1983 * Page Map Level-4 Entry
1984 */
1985typedef struct X86PML4EBITS
1986{
1987 /** Flags whether(=1) or not the page is present. */
1988 uint32_t u1Present : 1;
1989 /** Read(=0) / Write(=1) flag. */
1990 uint32_t u1Write : 1;
1991 /** User(=1) / Supervisor (=0) flag. */
1992 uint32_t u1User : 1;
1993 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1994 uint32_t u1WriteThru : 1;
1995 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1996 uint32_t u1CacheDisable : 1;
1997 /** Accessed flag.
1998 * Indicates that the page have been read or written to. */
1999 uint32_t u1Accessed : 1;
2000 /** Chunk of reserved bits. */
2001 uint32_t u3Reserved : 3;
2002 /** Available for use to system software. */
2003 uint32_t u3Available : 3;
2004 /** Physical Page number of the next level - Low Part. Don't use! */
2005 uint32_t u20PageNoLow : 20;
2006 /** Physical Page number of the next level - High Part. Don't use! */
2007 uint32_t u20PageNoHigh : 20;
2008 /** MBZ bits */
2009 uint32_t u11Reserved : 11;
2010 /** No Execute flag. */
2011 uint32_t u1NoExecute : 1;
2012} X86PML4EBITS;
2013/** Pointer to a page map level-4 entry. */
2014typedef X86PML4EBITS *PX86PML4EBITS;
2015/** Pointer to a const page map level-4 entry. */
2016typedef const X86PML4EBITS *PCX86PML4EBITS;
2017
2018/**
2019 * Page Map Level-4 Entry.
2020 */
2021typedef union X86PML4E
2022{
2023 /** Unsigned integer view. */
2024 X86PGPAEUINT u;
2025 /** Normal view. */
2026 X86PML4EBITS n;
2027 /** 8 bit unsigned integer view. */
2028 uint8_t au8[8];
2029 /** 16 bit unsigned integer view. */
2030 uint16_t au16[4];
2031 /** 32 bit unsigned integer view. */
2032 uint32_t au32[2];
2033} X86PML4E;
2034/** Pointer to a page map level-4 entry. */
2035typedef X86PML4E *PX86PML4E;
2036/** Pointer to a const page map level-4 entry. */
2037typedef const X86PML4E *PCX86PML4E;
2038
2039
2040/**
2041 * Page Map Level-4.
2042 */
2043typedef struct X86PML4
2044{
2045 /** PDE Array. */
2046 X86PML4E a[X86_PG_PAE_ENTRIES];
2047} X86PML4;
2048/** Pointer to a page map level-4. */
2049typedef X86PML4 *PX86PML4;
2050/** Pointer to a const page map level-4. */
2051typedef const X86PML4 *PCX86PML4;
2052
2053/** The page shift to get the PML4 index. */
2054#define X86_PML4_SHIFT 39
2055/** The PML4 index mask (apply to a shifted page address). */
2056#define X86_PML4_MASK 0x1ff
2057
2058/** @} */
2059
2060/** @} */
2061
2062
2063/**
2064 * 80-bit MMX/FPU register type.
2065 */
2066typedef struct X86FPUMMX
2067{
2068 uint8_t reg[10];
2069} X86FPUMMX;
2070/** Pointer to a 80-bit MMX/FPU register type. */
2071typedef X86FPUMMX *PX86FPUMMX;
2072/** Pointer to a const 80-bit MMX/FPU register type. */
2073typedef const X86FPUMMX *PCX86FPUMMX;
2074
2075/**
2076 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2077 * @todo verify this...
2078 */
2079#pragma pack(1)
2080typedef struct X86FPUSTATE
2081{
2082 /** 0x00 - Control word. */
2083 uint16_t FCW;
2084 /** 0x02 - Alignment word */
2085 uint16_t Dummy1;
2086 /** 0x04 - Status word. */
2087 uint16_t FSW;
2088 /** 0x06 - Alignment word */
2089 uint16_t Dummy2;
2090 /** 0x08 - Tag word */
2091 uint16_t FTW;
2092 /** 0x0a - Alignment word */
2093 uint16_t Dummy3;
2094
2095 /** 0x0c - Instruction pointer. */
2096 uint32_t FPUIP;
2097 /** 0x10 - Code selector. */
2098 uint16_t CS;
2099 /** 0x12 - Opcode. */
2100 uint16_t FOP;
2101 /** 0x14 - FOO. */
2102 uint32_t FPUOO;
2103 /** 0x18 - FOS. */
2104 uint32_t FPUOS;
2105 /** 0x1c */
2106 union
2107 {
2108 /** MMX view. */
2109 uint64_t mmx;
2110 /** FPU view - todo. */
2111 X86FPUMMX fpu;
2112 /** Extended precision floating point view. */
2113 RTFLOAT80U r80;
2114 /** Extended precision floating point view v2. */
2115 RTFLOAT80U2 r80Ex;
2116 /** 8-bit view. */
2117 uint8_t au8[16];
2118 /** 16-bit view. */
2119 uint16_t au16[8];
2120 /** 32-bit view. */
2121 uint32_t au32[4];
2122 /** 64-bit view. */
2123 uint64_t au64[2];
2124 /** 128-bit view. (yeah, very helpful) */
2125 uint128_t au128[1];
2126 } regs[8];
2127} X86FPUSTATE;
2128#pragma pack()
2129/** Pointer to a FPU state. */
2130typedef X86FPUSTATE *PX86FPUSTATE;
2131/** Pointer to a const FPU state. */
2132typedef const X86FPUSTATE *PCX86FPUSTATE;
2133
2134/**
2135 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2136 */
2137#pragma pack(1)
2138typedef struct X86FXSTATE
2139{
2140 /** 0x00 - Control word. */
2141 uint16_t FCW;
2142 /** 0x02 - Status word. */
2143 uint16_t FSW;
2144 /** 0x04 - Tag word. (The upper byte is always zero.) */
2145 uint16_t FTW;
2146 /** 0x06 - Opcode. */
2147 uint16_t FOP;
2148 /** 0x08 - Instruction pointer. */
2149 uint32_t FPUIP;
2150 /** 0x0c - Code selector. */
2151 uint16_t CS;
2152 uint16_t Rsrvd1;
2153 /** 0x10 - Data pointer. */
2154 uint32_t FPUDP;
2155 /** 0x14 - Data segment */
2156 uint16_t DS;
2157 /** 0x16 */
2158 uint16_t Rsrvd2;
2159 /** 0x18 */
2160 uint32_t MXCSR;
2161 /** 0x1c */
2162 uint32_t MXCSR_MASK;
2163 /** 0x20 */
2164 union
2165 {
2166 /** MMX view. */
2167 uint64_t mmx;
2168 /** FPU view - todo. */
2169 X86FPUMMX fpu;
2170 /** Extended precision floating point view. */
2171 RTFLOAT80U r80;
2172 /** Extended precision floating point view v2 */
2173 RTFLOAT80U2 r80Ex;
2174 /** 8-bit view. */
2175 uint8_t au8[16];
2176 /** 16-bit view. */
2177 uint16_t au16[8];
2178 /** 32-bit view. */
2179 uint32_t au32[4];
2180 /** 64-bit view. */
2181 uint64_t au64[2];
2182 /** 128-bit view. (yeah, very helpful) */
2183 uint128_t au128[1];
2184 } aRegs[8];
2185 /* - offset 160 - */
2186 union
2187 {
2188 /** XMM Register view *. */
2189 uint128_t xmm;
2190 /** 8-bit view. */
2191 uint8_t au8[16];
2192 /** 16-bit view. */
2193 uint16_t au16[8];
2194 /** 32-bit view. */
2195 uint32_t au32[4];
2196 /** 64-bit view. */
2197 uint64_t au64[2];
2198 /** 128-bit view. (yeah, very helpful) */
2199 uint128_t au128[1];
2200 } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2201 /* - offset 416 - */
2202 uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2203} X86FXSTATE;
2204#pragma pack()
2205/** Pointer to a FPU Extended state. */
2206typedef X86FXSTATE *PX86FXSTATE;
2207/** Pointer to a const FPU Extended state. */
2208typedef const X86FXSTATE *PCX86FXSTATE;
2209
2210/** @name FPU status word flags.
2211 * @{ */
2212/** Exception Flag: Invalid operation. */
2213#define X86_FSW_IE RT_BIT(0)
2214/** Exception Flag: Denormalized operand. */
2215#define X86_FSW_DE RT_BIT(1)
2216/** Exception Flag: Zero divide. */
2217#define X86_FSW_ZE RT_BIT(2)
2218/** Exception Flag: Overflow. */
2219#define X86_FSW_OE RT_BIT(3)
2220/** Exception Flag: Underflow. */
2221#define X86_FSW_UE RT_BIT(4)
2222/** Exception Flag: Precision. */
2223#define X86_FSW_PE RT_BIT(5)
2224/** Stack fault. */
2225#define X86_FSW_SF RT_BIT(6)
2226/** Error summary status. */
2227#define X86_FSW_ES RT_BIT(7)
2228/** Mask of exceptions flags, excluding the summary bit. */
2229#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2230/** Mask of exceptions flags, including the summary bit. */
2231#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2232/** Condition code 0. */
2233#define X86_FSW_C0 RT_BIT(8)
2234/** Condition code 1. */
2235#define X86_FSW_C1 RT_BIT(9)
2236/** Condition code 2. */
2237#define X86_FSW_C2 RT_BIT(10)
2238/** Top of the stack mask. */
2239#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2240/** TOP shift value. */
2241#define X86_FSW_TOP_SHIFT 11
2242/** Mask for getting TOP value after shifting it right. */
2243#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2244/** Get the TOP value. */
2245#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2246/** Condition code 3. */
2247#define X86_FSW_C3 RT_BIT(14)
2248/** Mask of exceptions flags, including the summary bit. */
2249#define X86_FSW_C_MASK UINT16_C(0x4700)
2250/** FPU busy. */
2251#define X86_FSW_B RT_BIT(15)
2252/** @} */
2253
2254
2255/** @name FPU control word flags.
2256 * @{ */
2257/** Exception Mask: Invalid operation. */
2258#define X86_FCW_IM RT_BIT(0)
2259/** Exception Mask: Denormalized operand. */
2260#define X86_FCW_DM RT_BIT(1)
2261/** Exception Mask: Zero divide. */
2262#define X86_FCW_ZM RT_BIT(2)
2263/** Exception Mask: Overflow. */
2264#define X86_FCW_OM RT_BIT(3)
2265/** Exception Mask: Underflow. */
2266#define X86_FCW_UM RT_BIT(4)
2267/** Exception Mask: Precision. */
2268#define X86_FCW_PM RT_BIT(5)
2269/** Mask all exceptions, the value typically loaded (by for instance fninit).
2270 * @remarks This includes reserved bit 6. */
2271#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2272/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2273#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2274/** Precision control mask. */
2275#define X86_FCW_PC_MASK UINT16_C(0x0300)
2276/** Precision control: 24-bit. */
2277#define X86_FCW_PC_24 UINT16_C(0x0000)
2278/** Precision control: Reserved. */
2279#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2280/** Precision control: 53-bit. */
2281#define X86_FCW_PC_53 UINT16_C(0x0200)
2282/** Precision control: 64-bit. */
2283#define X86_FCW_PC_64 UINT16_C(0x0300)
2284/** Rounding control mask. */
2285#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2286/** Rounding control: To nearest. */
2287#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2288/** Rounding control: Down. */
2289#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2290/** Rounding control: Up. */
2291#define X86_FCW_RC_UP UINT16_C(0x0800)
2292/** Rounding control: Towards zero. */
2293#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2294/** Bits which should be zero, apparently. */
2295#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2296/** @} */
2297
2298/** @name SSE MXCSR
2299 * @{ */
2300/** Exception Flag: Invalid operation. */
2301#define X86_MSXCR_IE RT_BIT(0)
2302/** Exception Flag: Denormalized operand. */
2303#define X86_MSXCR_DE RT_BIT(1)
2304/** Exception Flag: Zero divide. */
2305#define X86_MSXCR_ZE RT_BIT(2)
2306/** Exception Flag: Overflow. */
2307#define X86_MSXCR_OE RT_BIT(3)
2308/** Exception Flag: Underflow. */
2309#define X86_MSXCR_UE RT_BIT(4)
2310/** Exception Flag: Precision. */
2311#define X86_MSXCR_PE RT_BIT(5)
2312
2313/** Denormals are zero. */
2314#define X86_MSXCR_DAZ RT_BIT(6)
2315
2316/** Exception Mask: Invalid operation. */
2317#define X86_MSXCR_IM RT_BIT(7)
2318/** Exception Mask: Denormalized operand. */
2319#define X86_MSXCR_DM RT_BIT(8)
2320/** Exception Mask: Zero divide. */
2321#define X86_MSXCR_ZM RT_BIT(9)
2322/** Exception Mask: Overflow. */
2323#define X86_MSXCR_OM RT_BIT(10)
2324/** Exception Mask: Underflow. */
2325#define X86_MSXCR_UM RT_BIT(11)
2326/** Exception Mask: Precision. */
2327#define X86_MSXCR_PM RT_BIT(12)
2328
2329/** Rounding control mask. */
2330#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2331/** Rounding control: To nearest. */
2332#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2333/** Rounding control: Down. */
2334#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2335/** Rounding control: Up. */
2336#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2337/** Rounding control: Towards zero. */
2338#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2339
2340/** Flush-to-zero for masked underflow. */
2341#define X86_MSXCR_FZ RT_BIT(15)
2342
2343/** Misaligned Exception Mask. */
2344#define X86_MSXCR_MM RT_BIT(16)
2345/** @} */
2346
2347
2348/** @name Selector Descriptor
2349 * @{
2350 */
2351
2352#ifndef VBOX_FOR_DTRACE_LIB
2353/**
2354 * Descriptor attributes (as seen by VT-x).
2355 */
2356typedef struct X86DESCATTRBITS
2357{
2358 /** 00 - Segment Type. */
2359 unsigned u4Type : 4;
2360 /** 04 - Descriptor Type. System(=0) or code/data selector */
2361 unsigned u1DescType : 1;
2362 /** 05 - Descriptor Privelege level. */
2363 unsigned u2Dpl : 2;
2364 /** 07 - Flags selector present(=1) or not. */
2365 unsigned u1Present : 1;
2366 /** 08 - Segment limit 16-19. */
2367 unsigned u4LimitHigh : 4;
2368 /** 0c - Available for system software. */
2369 unsigned u1Available : 1;
2370 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2371 unsigned u1Long : 1;
2372 /** 0e - This flags meaning depends on the segment type. Try make sense out
2373 * of the intel manual yourself. */
2374 unsigned u1DefBig : 1;
2375 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
2376 * clear byte. */
2377 unsigned u1Granularity : 1;
2378 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2379 unsigned u1Unusable : 1;
2380} X86DESCATTRBITS;
2381#endif /* !VBOX_FOR_DTRACE_LIB */
2382
2383/** @name X86DESCATTR masks
2384 * @{ */
2385#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2386#define X86DESCATTR_DT UINT32_C(0x00000010)
2387#define X86DESCATTR_DPL UINT32_C(0x00000060)
2388#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
2389#define X86DESCATTR_P UINT32_C(0x00000080)
2390#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2391#define X86DESCATTR_AVL UINT32_C(0x00001000)
2392#define X86DESCATTR_L UINT32_C(0x00002000)
2393#define X86DESCATTR_D UINT32_C(0x00004000)
2394#define X86DESCATTR_G UINT32_C(0x00008000)
2395#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2396/** @} */
2397
2398#pragma pack(1)
2399typedef union X86DESCATTR
2400{
2401 /** Unsigned integer view. */
2402 uint32_t u;
2403#ifndef VBOX_FOR_DTRACE_LIB
2404 /** Normal view. */
2405 X86DESCATTRBITS n;
2406#endif
2407} X86DESCATTR;
2408#pragma pack()
2409/** Pointer to descriptor attributes. */
2410typedef X86DESCATTR *PX86DESCATTR;
2411/** Pointer to const descriptor attributes. */
2412typedef const X86DESCATTR *PCX86DESCATTR;
2413
2414#ifndef VBOX_FOR_DTRACE_LIB
2415
2416/**
2417 * Generic descriptor table entry
2418 */
2419#pragma pack(1)
2420typedef struct X86DESCGENERIC
2421{
2422 /** 00 - Limit - Low word. */
2423 unsigned u16LimitLow : 16;
2424 /** 10 - Base address - lowe word.
2425 * Don't try set this to 24 because MSC is doing stupid things then. */
2426 unsigned u16BaseLow : 16;
2427 /** 20 - Base address - first 8 bits of high word. */
2428 unsigned u8BaseHigh1 : 8;
2429 /** 28 - Segment Type. */
2430 unsigned u4Type : 4;
2431 /** 2c - Descriptor Type. System(=0) or code/data selector */
2432 unsigned u1DescType : 1;
2433 /** 2d - Descriptor Privelege level. */
2434 unsigned u2Dpl : 2;
2435 /** 2f - Flags selector present(=1) or not. */
2436 unsigned u1Present : 1;
2437 /** 30 - Segment limit 16-19. */
2438 unsigned u4LimitHigh : 4;
2439 /** 34 - Available for system software. */
2440 unsigned u1Available : 1;
2441 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2442 unsigned u1Long : 1;
2443 /** 36 - This flags meaning depends on the segment type. Try make sense out
2444 * of the intel manual yourself. */
2445 unsigned u1DefBig : 1;
2446 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
2447 * clear byte. */
2448 unsigned u1Granularity : 1;
2449 /** 38 - Base address - highest 8 bits. */
2450 unsigned u8BaseHigh2 : 8;
2451} X86DESCGENERIC;
2452#pragma pack()
2453/** Pointer to a generic descriptor entry. */
2454typedef X86DESCGENERIC *PX86DESCGENERIC;
2455/** Pointer to a const generic descriptor entry. */
2456typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2457
2458/** @name Bit offsets of X86DESCGENERIC members.
2459 * @{*/
2460#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
2461#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
2462#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
2463#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
2464#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
2465#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
2466#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
2467#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
2468#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
2469#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
2470#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
2471#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
2472#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
2473/** @} */
2474
2475/**
2476 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2477 */
2478typedef struct X86DESCGATE
2479{
2480 /** 00 - Target code segment offset - Low word.
2481 * Ignored if task-gate. */
2482 unsigned u16OffsetLow : 16;
2483 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2484 * TSS selector if task-gate. */
2485 unsigned u16Sel : 16;
2486 /** 20 - Number of parameters for a call-gate.
2487 * Ignored if interrupt-, trap- or task-gate. */
2488 unsigned u4ParmCount : 4;
2489 /** 24 - Reserved / ignored. */
2490 unsigned u4Reserved : 4;
2491 /** 28 - Segment Type. */
2492 unsigned u4Type : 4;
2493 /** 2c - Descriptor Type (0 = system). */
2494 unsigned u1DescType : 1;
2495 /** 2d - Descriptor Privelege level. */
2496 unsigned u2Dpl : 2;
2497 /** 2f - Flags selector present(=1) or not. */
2498 unsigned u1Present : 1;
2499 /** 30 - Target code segment offset - High word.
2500 * Ignored if task-gate. */
2501 unsigned u16OffsetHigh : 16;
2502} X86DESCGATE;
2503/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2504typedef X86DESCGATE *PX86DESCGATE;
2505/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2506typedef const X86DESCGATE *PCX86DESCGATE;
2507
2508#endif /* VBOX_FOR_DTRACE_LIB */
2509
2510/**
2511 * Descriptor table entry.
2512 */
2513#pragma pack(1)
2514typedef union X86DESC
2515{
2516#ifndef VBOX_FOR_DTRACE_LIB
2517 /** Generic descriptor view. */
2518 X86DESCGENERIC Gen;
2519 /** Gate descriptor view. */
2520 X86DESCGATE Gate;
2521#endif
2522
2523 /** 8 bit unsigned integer view. */
2524 uint8_t au8[8];
2525 /** 16 bit unsigned integer view. */
2526 uint16_t au16[4];
2527 /** 32 bit unsigned integer view. */
2528 uint32_t au32[2];
2529 /** 64 bit unsigned integer view. */
2530 uint64_t au64[1];
2531 /** Unsigned integer view. */
2532 uint64_t u;
2533} X86DESC;
2534#ifndef VBOX_FOR_DTRACE_LIB
2535AssertCompileSize(X86DESC, 8);
2536#endif
2537#pragma pack()
2538/** Pointer to descriptor table entry. */
2539typedef X86DESC *PX86DESC;
2540/** Pointer to const descriptor table entry. */
2541typedef const X86DESC *PCX86DESC;
2542
2543/** @def X86DESC_BASE
2544 * Return the base address of a descriptor.
2545 */
2546#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
2547 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2548 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2549 | ( (a_pDesc)->Gen.u16BaseLow ) )
2550
2551/** @def X86DESC_LIMIT
2552 * Return the limit of a descriptor.
2553 */
2554#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
2555 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2556 | ( (a_pDesc)->Gen.u16LimitLow ) )
2557
2558/** @def X86DESC_LIMIT_G
2559 * Return the limit of a descriptor with the granularity bit taken into account.
2560 * @returns Selector limit (uint32_t).
2561 * @param a_pDesc Pointer to the descriptor.
2562 */
2563#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
2564 ( (a_pDesc)->Gen.u1Granularity \
2565 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
2566 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
2567 )
2568
2569/** @def X86DESC_GET_HID_ATTR
2570 * Get the descriptor attributes for the hidden register.
2571 */
2572#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
2573 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2574
2575#ifndef VBOX_FOR_DTRACE_LIB
2576
2577/**
2578 * 64 bits generic descriptor table entry
2579 * Note: most of these bits have no meaning in long mode.
2580 */
2581#pragma pack(1)
2582typedef struct X86DESC64GENERIC
2583{
2584 /** Limit - Low word - *IGNORED*. */
2585 unsigned u16LimitLow : 16;
2586 /** Base address - low word. - *IGNORED*
2587 * Don't try set this to 24 because MSC is doing stupid things then. */
2588 unsigned u16BaseLow : 16;
2589 /** Base address - first 8 bits of high word. - *IGNORED* */
2590 unsigned u8BaseHigh1 : 8;
2591 /** Segment Type. */
2592 unsigned u4Type : 4;
2593 /** Descriptor Type. System(=0) or code/data selector */
2594 unsigned u1DescType : 1;
2595 /** Descriptor Privelege level. */
2596 unsigned u2Dpl : 2;
2597 /** Flags selector present(=1) or not. */
2598 unsigned u1Present : 1;
2599 /** Segment limit 16-19. - *IGNORED* */
2600 unsigned u4LimitHigh : 4;
2601 /** Available for system software. - *IGNORED* */
2602 unsigned u1Available : 1;
2603 /** Long mode flag. */
2604 unsigned u1Long : 1;
2605 /** This flags meaning depends on the segment type. Try make sense out
2606 * of the intel manual yourself. */
2607 unsigned u1DefBig : 1;
2608 /** Granularity of the limit. If set 4KB granularity is used, if
2609 * clear byte. - *IGNORED* */
2610 unsigned u1Granularity : 1;
2611 /** Base address - highest 8 bits. - *IGNORED* */
2612 unsigned u8BaseHigh2 : 8;
2613 /** Base address - bits 63-32. */
2614 unsigned u32BaseHigh3 : 32;
2615 unsigned u8Reserved : 8;
2616 unsigned u5Zeros : 5;
2617 unsigned u19Reserved : 19;
2618} X86DESC64GENERIC;
2619#pragma pack()
2620/** Pointer to a generic descriptor entry. */
2621typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2622/** Pointer to a const generic descriptor entry. */
2623typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2624
2625/**
2626 * System descriptor table entry (64 bits)
2627 *
2628 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2629 */
2630#pragma pack(1)
2631typedef struct X86DESC64SYSTEM
2632{
2633 /** Limit - Low word. */
2634 unsigned u16LimitLow : 16;
2635 /** Base address - lowe word.
2636 * Don't try set this to 24 because MSC is doing stupid things then. */
2637 unsigned u16BaseLow : 16;
2638 /** Base address - first 8 bits of high word. */
2639 unsigned u8BaseHigh1 : 8;
2640 /** Segment Type. */
2641 unsigned u4Type : 4;
2642 /** Descriptor Type. System(=0) or code/data selector */
2643 unsigned u1DescType : 1;
2644 /** Descriptor Privelege level. */
2645 unsigned u2Dpl : 2;
2646 /** Flags selector present(=1) or not. */
2647 unsigned u1Present : 1;
2648 /** Segment limit 16-19. */
2649 unsigned u4LimitHigh : 4;
2650 /** Available for system software. */
2651 unsigned u1Available : 1;
2652 /** Reserved - 0. */
2653 unsigned u1Reserved : 1;
2654 /** This flags meaning depends on the segment type. Try make sense out
2655 * of the intel manual yourself. */
2656 unsigned u1DefBig : 1;
2657 /** Granularity of the limit. If set 4KB granularity is used, if
2658 * clear byte. */
2659 unsigned u1Granularity : 1;
2660 /** Base address - bits 31-24. */
2661 unsigned u8BaseHigh2 : 8;
2662 /** Base address - bits 63-32. */
2663 unsigned u32BaseHigh3 : 32;
2664 unsigned u8Reserved : 8;
2665 unsigned u5Zeros : 5;
2666 unsigned u19Reserved : 19;
2667} X86DESC64SYSTEM;
2668#pragma pack()
2669/** Pointer to a system descriptor entry. */
2670typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2671/** Pointer to a const system descriptor entry. */
2672typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2673
2674/**
2675 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2676 */
2677typedef struct X86DESC64GATE
2678{
2679 /** Target code segment offset - Low word. */
2680 unsigned u16OffsetLow : 16;
2681 /** Target code segment selector. */
2682 unsigned u16Sel : 16;
2683 /** Interrupt stack table for interrupt- and trap-gates.
2684 * Ignored by call-gates. */
2685 unsigned u3IST : 3;
2686 /** Reserved / ignored. */
2687 unsigned u5Reserved : 5;
2688 /** Segment Type. */
2689 unsigned u4Type : 4;
2690 /** Descriptor Type (0 = system). */
2691 unsigned u1DescType : 1;
2692 /** Descriptor Privelege level. */
2693 unsigned u2Dpl : 2;
2694 /** Flags selector present(=1) or not. */
2695 unsigned u1Present : 1;
2696 /** Target code segment offset - High word.
2697 * Ignored if task-gate. */
2698 unsigned u16OffsetHigh : 16;
2699 /** Target code segment offset - Top dword.
2700 * Ignored if task-gate. */
2701 unsigned u32OffsetTop : 32;
2702 /** Reserved / ignored / must be zero.
2703 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2704 unsigned u32Reserved : 32;
2705} X86DESC64GATE;
2706AssertCompileSize(X86DESC64GATE, 16);
2707/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2708typedef X86DESC64GATE *PX86DESC64GATE;
2709/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2710typedef const X86DESC64GATE *PCX86DESC64GATE;
2711
2712#endif /* VBOX_FOR_DTRACE_LIB */
2713
2714/**
2715 * Descriptor table entry.
2716 */
2717#pragma pack(1)
2718typedef union X86DESC64
2719{
2720#ifndef VBOX_FOR_DTRACE_LIB
2721 /** Generic descriptor view. */
2722 X86DESC64GENERIC Gen;
2723 /** System descriptor view. */
2724 X86DESC64SYSTEM System;
2725 /** Gate descriptor view. */
2726 X86DESC64GATE Gate;
2727#endif
2728
2729 /** 8 bit unsigned integer view. */
2730 uint8_t au8[16];
2731 /** 16 bit unsigned integer view. */
2732 uint16_t au16[8];
2733 /** 32 bit unsigned integer view. */
2734 uint32_t au32[4];
2735 /** 64 bit unsigned integer view. */
2736 uint64_t au64[2];
2737} X86DESC64;
2738#ifndef VBOX_FOR_DTRACE_LIB
2739AssertCompileSize(X86DESC64, 16);
2740#endif
2741#pragma pack()
2742/** Pointer to descriptor table entry. */
2743typedef X86DESC64 *PX86DESC64;
2744/** Pointer to const descriptor table entry. */
2745typedef const X86DESC64 *PCX86DESC64;
2746
2747/** @def X86DESC64_BASE
2748 * Return the base of a 64-bit descriptor.
2749 */
2750#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
2751 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2752 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2753 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2754 | ( (a_pDesc)->Gen.u16BaseLow ) )
2755
2756
2757
2758/** @name Host system descriptor table entry - Use with care!
2759 * @{ */
2760/** Host system descriptor table entry. */
2761#if HC_ARCH_BITS == 64
2762typedef X86DESC64 X86DESCHC;
2763#else
2764typedef X86DESC X86DESCHC;
2765#endif
2766/** Pointer to a host system descriptor table entry. */
2767#if HC_ARCH_BITS == 64
2768typedef PX86DESC64 PX86DESCHC;
2769#else
2770typedef PX86DESC PX86DESCHC;
2771#endif
2772/** Pointer to a const host system descriptor table entry. */
2773#if HC_ARCH_BITS == 64
2774typedef PCX86DESC64 PCX86DESCHC;
2775#else
2776typedef PCX86DESC PCX86DESCHC;
2777#endif
2778/** @} */
2779
2780
2781/** @name Selector Descriptor Types.
2782 * @{
2783 */
2784
2785/** @name Non-System Selector Types.
2786 * @{ */
2787/** Code(=set)/Data(=clear) bit. */
2788#define X86_SEL_TYPE_CODE 8
2789/** Memory(=set)/System(=clear) bit. */
2790#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2791/** Accessed bit. */
2792#define X86_SEL_TYPE_ACCESSED 1
2793/** Expand down bit (for data selectors only). */
2794#define X86_SEL_TYPE_DOWN 4
2795/** Conforming bit (for code selectors only). */
2796#define X86_SEL_TYPE_CONF 4
2797/** Write bit (for data selectors only). */
2798#define X86_SEL_TYPE_WRITE 2
2799/** Read bit (for code selectors only). */
2800#define X86_SEL_TYPE_READ 2
2801/** The bit number of the code segment read bit (relative to u4Type). */
2802#define X86_SEL_TYPE_READ_BIT 1
2803
2804/** Read only selector type. */
2805#define X86_SEL_TYPE_RO 0
2806/** Accessed read only selector type. */
2807#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
2808/** Read write selector type. */
2809#define X86_SEL_TYPE_RW 2
2810/** Accessed read write selector type. */
2811#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
2812/** Expand down read only selector type. */
2813#define X86_SEL_TYPE_RO_DOWN 4
2814/** Accessed expand down read only selector type. */
2815#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
2816/** Expand down read write selector type. */
2817#define X86_SEL_TYPE_RW_DOWN 6
2818/** Accessed expand down read write selector type. */
2819#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
2820/** Execute only selector type. */
2821#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
2822/** Accessed execute only selector type. */
2823#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2824/** Execute and read selector type. */
2825#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
2826/** Accessed execute and read selector type. */
2827#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2828/** Conforming execute only selector type. */
2829#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
2830/** Accessed Conforming execute only selector type. */
2831#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2832/** Conforming execute and write selector type. */
2833#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
2834/** Accessed Conforming execute and write selector type. */
2835#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2836/** @} */
2837
2838
2839/** @name System Selector Types.
2840 * @{ */
2841/** The TSS busy bit mask. */
2842#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2843
2844/** Undefined system selector type. */
2845#define X86_SEL_TYPE_SYS_UNDEFINED 0
2846/** 286 TSS selector. */
2847#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2848/** LDT selector. */
2849#define X86_SEL_TYPE_SYS_LDT 2
2850/** 286 TSS selector - Busy. */
2851#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2852/** 286 Callgate selector. */
2853#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2854/** Taskgate selector. */
2855#define X86_SEL_TYPE_SYS_TASK_GATE 5
2856/** 286 Interrupt gate selector. */
2857#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2858/** 286 Trapgate selector. */
2859#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2860/** Undefined system selector. */
2861#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2862/** 386 TSS selector. */
2863#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2864/** Undefined system selector. */
2865#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2866/** 386 TSS selector - Busy. */
2867#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2868/** 386 Callgate selector. */
2869#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2870/** Undefined system selector. */
2871#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2872/** 386 Interruptgate selector. */
2873#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2874/** 386 Trapgate selector. */
2875#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2876/** @} */
2877
2878/** @name AMD64 System Selector Types.
2879 * @{ */
2880/** LDT selector. */
2881#define AMD64_SEL_TYPE_SYS_LDT 2
2882/** TSS selector - Busy. */
2883#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2884/** TSS selector - Busy. */
2885#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2886/** Callgate selector. */
2887#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2888/** Interruptgate selector. */
2889#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2890/** Trapgate selector. */
2891#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2892/** @} */
2893
2894/** @} */
2895
2896
2897/** @name Descriptor Table Entry Flag Masks.
2898 * These are for the 2nd 32-bit word of a descriptor.
2899 * @{ */
2900/** Bits 8-11 - TYPE - Descriptor type mask. */
2901#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
2902/** Bit 12 - S - System (=0) or Code/Data (=1). */
2903#define X86_DESC_S RT_BIT(12)
2904/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2905#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
2906/** Bit 15 - P - Present. */
2907#define X86_DESC_P RT_BIT(15)
2908/** Bit 20 - AVL - Available for system software. */
2909#define X86_DESC_AVL RT_BIT(20)
2910/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2911#define X86_DESC_DB RT_BIT(22)
2912/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2913 * used, if clear byte. */
2914#define X86_DESC_G RT_BIT(23)
2915/** @} */
2916
2917/** @} */
2918
2919
2920/** @name Task Segments.
2921 * @{
2922 */
2923
2924/**
2925 * 16-bit Task Segment (TSS).
2926 */
2927#pragma pack(1)
2928typedef struct X86TSS16
2929{
2930 /** Back link to previous task. (static) */
2931 RTSEL selPrev;
2932 /** Ring-0 stack pointer. (static) */
2933 uint16_t sp0;
2934 /** Ring-0 stack segment. (static) */
2935 RTSEL ss0;
2936 /** Ring-1 stack pointer. (static) */
2937 uint16_t sp1;
2938 /** Ring-1 stack segment. (static) */
2939 RTSEL ss1;
2940 /** Ring-2 stack pointer. (static) */
2941 uint16_t sp2;
2942 /** Ring-2 stack segment. (static) */
2943 RTSEL ss2;
2944 /** IP before task switch. */
2945 uint16_t ip;
2946 /** FLAGS before task switch. */
2947 uint16_t flags;
2948 /** AX before task switch. */
2949 uint16_t ax;
2950 /** CX before task switch. */
2951 uint16_t cx;
2952 /** DX before task switch. */
2953 uint16_t dx;
2954 /** BX before task switch. */
2955 uint16_t bx;
2956 /** SP before task switch. */
2957 uint16_t sp;
2958 /** BP before task switch. */
2959 uint16_t bp;
2960 /** SI before task switch. */
2961 uint16_t si;
2962 /** DI before task switch. */
2963 uint16_t di;
2964 /** ES before task switch. */
2965 RTSEL es;
2966 /** CS before task switch. */
2967 RTSEL cs;
2968 /** SS before task switch. */
2969 RTSEL ss;
2970 /** DS before task switch. */
2971 RTSEL ds;
2972 /** LDTR before task switch. */
2973 RTSEL selLdt;
2974} X86TSS16;
2975#ifndef VBOX_FOR_DTRACE_LIB
2976AssertCompileSize(X86TSS16, 44);
2977#endif
2978#pragma pack()
2979/** Pointer to a 16-bit task segment. */
2980typedef X86TSS16 *PX86TSS16;
2981/** Pointer to a const 16-bit task segment. */
2982typedef const X86TSS16 *PCX86TSS16;
2983
2984
2985/**
2986 * 32-bit Task Segment (TSS).
2987 */
2988#pragma pack(1)
2989typedef struct X86TSS32
2990{
2991 /** Back link to previous task. (static) */
2992 RTSEL selPrev;
2993 uint16_t padding1;
2994 /** Ring-0 stack pointer. (static) */
2995 uint32_t esp0;
2996 /** Ring-0 stack segment. (static) */
2997 RTSEL ss0;
2998 uint16_t padding_ss0;
2999 /** Ring-1 stack pointer. (static) */
3000 uint32_t esp1;
3001 /** Ring-1 stack segment. (static) */
3002 RTSEL ss1;
3003 uint16_t padding_ss1;
3004 /** Ring-2 stack pointer. (static) */
3005 uint32_t esp2;
3006 /** Ring-2 stack segment. (static) */
3007 RTSEL ss2;
3008 uint16_t padding_ss2;
3009 /** Page directory for the task. (static) */
3010 uint32_t cr3;
3011 /** EIP before task switch. */
3012 uint32_t eip;
3013 /** EFLAGS before task switch. */
3014 uint32_t eflags;
3015 /** EAX before task switch. */
3016 uint32_t eax;
3017 /** ECX before task switch. */
3018 uint32_t ecx;
3019 /** EDX before task switch. */
3020 uint32_t edx;
3021 /** EBX before task switch. */
3022 uint32_t ebx;
3023 /** ESP before task switch. */
3024 uint32_t esp;
3025 /** EBP before task switch. */
3026 uint32_t ebp;
3027 /** ESI before task switch. */
3028 uint32_t esi;
3029 /** EDI before task switch. */
3030 uint32_t edi;
3031 /** ES before task switch. */
3032 RTSEL es;
3033 uint16_t padding_es;
3034 /** CS before task switch. */
3035 RTSEL cs;
3036 uint16_t padding_cs;
3037 /** SS before task switch. */
3038 RTSEL ss;
3039 uint16_t padding_ss;
3040 /** DS before task switch. */
3041 RTSEL ds;
3042 uint16_t padding_ds;
3043 /** FS before task switch. */
3044 RTSEL fs;
3045 uint16_t padding_fs;
3046 /** GS before task switch. */
3047 RTSEL gs;
3048 uint16_t padding_gs;
3049 /** LDTR before task switch. */
3050 RTSEL selLdt;
3051 uint16_t padding_ldt;
3052 /** Debug trap flag */
3053 uint16_t fDebugTrap;
3054 /** Offset relative to the TSS of the start of the I/O Bitmap
3055 * and the end of the interrupt redirection bitmap. */
3056 uint16_t offIoBitmap;
3057 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3058 uint8_t IntRedirBitmap[32];
3059} X86TSS32;
3060#pragma pack()
3061/** Pointer to task segment. */
3062typedef X86TSS32 *PX86TSS32;
3063/** Pointer to const task segment. */
3064typedef const X86TSS32 *PCX86TSS32;
3065
3066
3067/**
3068 * 64-bit Task segment.
3069 */
3070#pragma pack(1)
3071typedef struct X86TSS64
3072{
3073 /** Reserved. */
3074 uint32_t u32Reserved;
3075 /** Ring-0 stack pointer. (static) */
3076 uint64_t rsp0;
3077 /** Ring-1 stack pointer. (static) */
3078 uint64_t rsp1;
3079 /** Ring-2 stack pointer. (static) */
3080 uint64_t rsp2;
3081 /** Reserved. */
3082 uint32_t u32Reserved2[2];
3083 /* IST */
3084 uint64_t ist1;
3085 uint64_t ist2;
3086 uint64_t ist3;
3087 uint64_t ist4;
3088 uint64_t ist5;
3089 uint64_t ist6;
3090 uint64_t ist7;
3091 /* Reserved. */
3092 uint16_t u16Reserved[5];
3093 /** Offset relative to the TSS of the start of the I/O Bitmap
3094 * and the end of the interrupt redirection bitmap. */
3095 uint16_t offIoBitmap;
3096 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3097 uint8_t IntRedirBitmap[32];
3098} X86TSS64;
3099#pragma pack()
3100/** Pointer to a 64-bit task segment. */
3101typedef X86TSS64 *PX86TSS64;
3102/** Pointer to a const 64-bit task segment. */
3103typedef const X86TSS64 *PCX86TSS64;
3104#ifndef VBOX_FOR_DTRACE_LIB
3105AssertCompileSize(X86TSS64, 136);
3106#endif
3107
3108/** @} */
3109
3110
3111/** @name Selectors.
3112 * @{
3113 */
3114
3115/**
3116 * The shift used to convert a selector from and to index an index (C).
3117 */
3118#define X86_SEL_SHIFT 3
3119
3120/**
3121 * The mask used to mask off the table indicator and RPL of an selector.
3122 */
3123#define X86_SEL_MASK 0xfff8U
3124
3125/**
3126 * The mask used to mask off the RPL of an selector.
3127 * This is suitable for checking for NULL selectors.
3128 */
3129#define X86_SEL_MASK_OFF_RPL 0xfffcU
3130
3131/**
3132 * The bit indicating that a selector is in the LDT and not in the GDT.
3133 */
3134#define X86_SEL_LDT 0x0004U
3135
3136/**
3137 * The bit mask for getting the RPL of a selector.
3138 */
3139#define X86_SEL_RPL 0x0003U
3140
3141/**
3142 * The mask covering both RPL and LDT.
3143 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3144 * checks.
3145 */
3146#define X86_SEL_RPL_LDT 0x0007U
3147
3148/** @} */
3149
3150
3151/**
3152 * x86 Exceptions/Faults/Traps.
3153 */
3154typedef enum X86XCPT
3155{
3156 /** \#DE - Divide error. */
3157 X86_XCPT_DE = 0x00,
3158 /** \#DB - Debug event (single step, DRx, ..) */
3159 X86_XCPT_DB = 0x01,
3160 /** NMI - Non-Maskable Interrupt */
3161 X86_XCPT_NMI = 0x02,
3162 /** \#BP - Breakpoint (INT3). */
3163 X86_XCPT_BP = 0x03,
3164 /** \#OF - Overflow (INTO). */
3165 X86_XCPT_OF = 0x04,
3166 /** \#BR - Bound range exceeded (BOUND). */
3167 X86_XCPT_BR = 0x05,
3168 /** \#UD - Undefined opcode. */
3169 X86_XCPT_UD = 0x06,
3170 /** \#NM - Device not available (math coprocessor device). */
3171 X86_XCPT_NM = 0x07,
3172 /** \#DF - Double fault. */
3173 X86_XCPT_DF = 0x08,
3174 /** ??? - Coprocessor segment overrun (obsolete). */
3175 X86_XCPT_CO_SEG_OVERRUN = 0x09,
3176 /** \#TS - Taskswitch (TSS). */
3177 X86_XCPT_TS = 0x0a,
3178 /** \#NP - Segment no present. */
3179 X86_XCPT_NP = 0x0b,
3180 /** \#SS - Stack segment fault. */
3181 X86_XCPT_SS = 0x0c,
3182 /** \#GP - General protection fault. */
3183 X86_XCPT_GP = 0x0d,
3184 /** \#PF - Page fault. */
3185 X86_XCPT_PF = 0x0e,
3186 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3187 /** \#MF - Math fault (FPU). */
3188 X86_XCPT_MF = 0x10,
3189 /** \#AC - Alignment check. */
3190 X86_XCPT_AC = 0x11,
3191 /** \#MC - Machine check. */
3192 X86_XCPT_MC = 0x12,
3193 /** \#XF - SIMD Floating-Pointer Exception. */
3194 X86_XCPT_XF = 0x13,
3195 /** \#VE - Virtualzation Exception. */
3196 X86_XCPT_VE = 0x14,
3197 /** \#SX - Security Exception. */
3198 X86_XCPT_SX = 0x1f
3199} X86XCPT;
3200/** Pointer to a x86 exception code. */
3201typedef X86XCPT *PX86XCPT;
3202/** Pointer to a const x86 exception code. */
3203typedef const X86XCPT *PCX86XCPT;
3204/** The maximum exception value. */
3205#define X86_XCPT_MAX (X86_XCPT_SX)
3206
3207
3208/** @name Trap Error Codes
3209 * @{
3210 */
3211/** External indicator. */
3212#define X86_TRAP_ERR_EXTERNAL 1
3213/** IDT indicator. */
3214#define X86_TRAP_ERR_IDT 2
3215/** Descriptor table indicator - If set LDT, if clear GDT. */
3216#define X86_TRAP_ERR_TI 4
3217/** Mask for getting the selector. */
3218#define X86_TRAP_ERR_SEL_MASK 0xfff8
3219/** Shift for getting the selector table index (C type index). */
3220#define X86_TRAP_ERR_SEL_SHIFT 3
3221/** @} */
3222
3223
3224/** @name \#PF Trap Error Codes
3225 * @{
3226 */
3227/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3228#define X86_TRAP_PF_P RT_BIT(0)
3229/** Bit 1 - R/W - Read (clear) or write (set) access. */
3230#define X86_TRAP_PF_RW RT_BIT(1)
3231/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3232#define X86_TRAP_PF_US RT_BIT(2)
3233/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3234#define X86_TRAP_PF_RSVD RT_BIT(3)
3235/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3236#define X86_TRAP_PF_ID RT_BIT(4)
3237/** @} */
3238
3239#pragma pack(1)
3240/**
3241 * 32-bit IDTR/GDTR.
3242 */
3243typedef struct X86XDTR32
3244{
3245 /** Size of the descriptor table. */
3246 uint16_t cb;
3247 /** Address of the descriptor table. */
3248#ifndef VBOX_FOR_DTRACE_LIB
3249 uint32_t uAddr;
3250#else
3251 uint16_t au16Addr[2];
3252#endif
3253} X86XDTR32, *PX86XDTR32;
3254#pragma pack()
3255
3256#pragma pack(1)
3257/**
3258 * 64-bit IDTR/GDTR.
3259 */
3260typedef struct X86XDTR64
3261{
3262 /** Size of the descriptor table. */
3263 uint16_t cb;
3264 /** Address of the descriptor table. */
3265#ifndef VBOX_FOR_DTRACE_LIB
3266 uint64_t uAddr;
3267#else
3268 uint16_t au16Addr[4];
3269#endif
3270} X86XDTR64, *PX86XDTR64;
3271#pragma pack()
3272
3273
3274/** @name ModR/M
3275 * @{ */
3276#define X86_MODRM_RM_MASK UINT8_C(0x07)
3277#define X86_MODRM_REG_MASK UINT8_C(0x38)
3278#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3279#define X86_MODRM_REG_SHIFT 3
3280#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3281#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3282#define X86_MODRM_MOD_SHIFT 6
3283#ifndef VBOX_FOR_DTRACE_LIB
3284AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
3285AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3286AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3287#endif
3288/** @} */
3289
3290/** @name SIB
3291 * @{ */
3292#define X86_SIB_BASE_MASK UINT8_C(0x07)
3293#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3294#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3295#define X86_SIB_INDEX_SHIFT 3
3296#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3297#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3298#define X86_SIB_SCALE_SHIFT 6
3299#ifndef VBOX_FOR_DTRACE_LIB
3300AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
3301AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3302AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3303#endif
3304/** @} */
3305
3306/** @name General register indexes
3307 * @{ */
3308#define X86_GREG_xAX 0
3309#define X86_GREG_xCX 1
3310#define X86_GREG_xDX 2
3311#define X86_GREG_xBX 3
3312#define X86_GREG_xSP 4
3313#define X86_GREG_xBP 5
3314#define X86_GREG_xSI 6
3315#define X86_GREG_xDI 7
3316#define X86_GREG_x8 8
3317#define X86_GREG_x9 9
3318#define X86_GREG_x10 10
3319#define X86_GREG_x11 11
3320#define X86_GREG_x12 12
3321#define X86_GREG_x13 13
3322#define X86_GREG_x14 14
3323#define X86_GREG_x15 15
3324/** @} */
3325
3326/** @name X86_SREG_XXX - Segment register indexes.
3327 * @{ */
3328#define X86_SREG_ES 0
3329#define X86_SREG_CS 1
3330#define X86_SREG_SS 2
3331#define X86_SREG_DS 3
3332#define X86_SREG_FS 4
3333#define X86_SREG_GS 5
3334/** @} */
3335/** Segment register count. */
3336#define X86_SREG_COUNT 6
3337
3338
3339/** @name X86_OP_XXX - Prefixes
3340 * @{ */
3341#define X86_OP_PRF_CS UINT8_C(0x2e)
3342#define X86_OP_PRF_SS UINT8_C(0x36)
3343#define X86_OP_PRF_DS UINT8_C(0x3e)
3344#define X86_OP_PRF_ES UINT8_C(0x26)
3345#define X86_OP_PRF_FS UINT8_C(0x64)
3346#define X86_OP_PRF_GS UINT8_C(0x65)
3347#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3348#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3349#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3350#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3351#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3352#define X86_OP_REX_B UINT8_C(0x41)
3353#define X86_OP_REX_X UINT8_C(0x42)
3354#define X86_OP_REX_R UINT8_C(0x44)
3355#define X86_OP_REX_W UINT8_C(0x48)
3356/** @} */
3357
3358
3359/** @} */
3360
3361#endif
3362
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