x86.h@ 48066

Last change on this file since 48066 was 48066, checked in by vboxsync, 11 years ago
CPUM: Fake MSR_IA32_MCG_STATUS reads. Corrected MSR names, IA32_MCP should be IA32_MCG according to latest intel docs.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 120.7 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	/** Bit 1 - Reserved, reads as 1. */
165	#define X86_EFL_1 RT_BIT(1)
166	/** Bit 2 - PF - Parity flag - Status flag. */
167	#define X86_EFL_PF RT_BIT(2)
168	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169	#define X86_EFL_AF RT_BIT(4)
170	/** Bit 6 - ZF - Zero flag - Status flag. */
171	#define X86_EFL_ZF RT_BIT(6)
172	/** Bit 7 - SF - Signed flag - Status flag. */
173	#define X86_EFL_SF RT_BIT(7)
174	/** Bit 8 - TF - Trap flag - System flag. */
175	#define X86_EFL_TF RT_BIT(8)
176	/** Bit 9 - IF - Interrupt flag - System flag. */
177	#define X86_EFL_IF RT_BIT(9)
178	/** Bit 10 - DF - Direction flag - Control flag. */
179	#define X86_EFL_DF RT_BIT(10)
180	/** Bit 11 - OF - Overflow flag - Status flag. */
181	#define X86_EFL_OF RT_BIT(11)
182	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
184	/** Bit 14 - NT - Nested task flag - System flag. */
185	#define X86_EFL_NT RT_BIT(14)
186	/** Bit 16 - RF - Resume flag - System flag. */
187	#define X86_EFL_RF RT_BIT(16)
188	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189	#define X86_EFL_VM RT_BIT(17)
190	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191	#define X86_EFL_AC RT_BIT(18)
192	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193	#define X86_EFL_VIF RT_BIT(19)
194	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195	#define X86_EFL_VIP RT_BIT(20)
196	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197	#define X86_EFL_ID RT_BIT(21)
198	/** All live bits. */
199	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
200	/** Read as 1 bits. */
201	#define X86_EFL_RA1_MASK RT_BIT_32(1)
202	/** IOPL shift. */
203	#define X86_EFL_IOPL_SHIFT 12
204	/** The the IOPL level from the flags. */
205	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
206	/** Bits restored by popf */
207	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
208	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
209	/** @} */
210
211
212	/** CPUID Feature information - ECX.
213	* CPUID query with EAX=1.
214	*/
215	#ifndef VBOX_FOR_DTRACE_LIB
216	typedef struct X86CPUIDFEATECX
217	{
218	/** Bit 0 - SSE3 - Supports SSE3 or not. */
219	unsigned u1SSE3 : 1;
220	/** Bit 1 - PCLMULQDQ. */
221	unsigned u1PCLMULQDQ : 1;
222	/** Bit 2 - DS Area 64-bit layout. */
223	unsigned u1DTE64 : 1;
224	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
225	unsigned u1Monitor : 1;
226	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
227	unsigned u1CPLDS : 1;
228	/** Bit 5 - VMX - Virtual Machine Technology. */
229	unsigned u1VMX : 1;
230	/** Bit 6 - SMX: Safer Mode Extensions. */
231	unsigned u1SMX : 1;
232	/** Bit 7 - EST - Enh. SpeedStep Tech. */
233	unsigned u1EST : 1;
234	/** Bit 8 - TM2 - Terminal Monitor 2. */
235	unsigned u1TM2 : 1;
236	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
237	unsigned u1SSSE3 : 1;
238	/** Bit 10 - CNTX-ID - L1 Context ID. */
239	unsigned u1CNTXID : 1;
240	/** Bit 11 - Reserved. */
241	unsigned u1Reserved1 : 1;
242	/** Bit 12 - FMA. */
243	unsigned u1FMA : 1;
244	/** Bit 13 - CX16 - CMPXCHG16B. */
245	unsigned u1CX16 : 1;
246	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
247	unsigned u1TPRUpdate : 1;
248	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
249	unsigned u1PDCM : 1;
250	/** Bit 16 - Reserved. */
251	unsigned u1Reserved2 : 1;
252	/** Bit 17 - PCID - Process-context identifiers. */
253	unsigned u1PCID : 1;
254	/** Bit 18 - Direct Cache Access. */
255	unsigned u1DCA : 1;
256	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
257	unsigned u1SSE4_1 : 1;
258	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
259	unsigned u1SSE4_2 : 1;
260	/** Bit 21 - x2APIC. */
261	unsigned u1x2APIC : 1;
262	/** Bit 22 - MOVBE - Supports MOVBE. */
263	unsigned u1MOVBE : 1;
264	/** Bit 23 - POPCNT - Supports POPCNT. */
265	unsigned u1POPCNT : 1;
266	/** Bit 24 - TSC-Deadline. */
267	unsigned u1TSCDEADLINE : 1;
268	/** Bit 25 - AES. */
269	unsigned u1AES : 1;
270	/** Bit 26 - XSAVE - Supports XSAVE. */
271	unsigned u1XSAVE : 1;
272	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
273	unsigned u1OSXSAVE : 1;
274	/** Bit 28 - AVX - Supports AVX instruction extensions. */
275	unsigned u1AVX : 1;
276	/** Bit 29 - 30 - Reserved */
277	unsigned u2Reserved3 : 2;
278	/** Bit 31 - Hypervisor present (we're a guest). */
279	unsigned u1HVP : 1;
280	} X86CPUIDFEATECX;
281	#else /* VBOX_FOR_DTRACE_LIB */
282	typedef uint32_t X86CPUIDFEATECX;
283	#endif /* VBOX_FOR_DTRACE_LIB */
284	/** Pointer to CPUID Feature Information - ECX. */
285	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
286	/** Pointer to const CPUID Feature Information - ECX. */
287	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
288
289
290	/** CPUID Feature Information - EDX.
291	* CPUID query with EAX=1.
292	*/
293	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
294	typedef struct X86CPUIDFEATEDX
295	{
296	/** Bit 0 - FPU - x87 FPU on Chip. */
297	unsigned u1FPU : 1;
298	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
299	unsigned u1VME : 1;
300	/** Bit 2 - DE - Debugging extensions. */
301	unsigned u1DE : 1;
302	/** Bit 3 - PSE - Page Size Extension. */
303	unsigned u1PSE : 1;
304	/** Bit 4 - TSC - Time Stamp Counter. */
305	unsigned u1TSC : 1;
306	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
307	unsigned u1MSR : 1;
308	/** Bit 6 - PAE - Physical Address Extension. */
309	unsigned u1PAE : 1;
310	/** Bit 7 - MCE - Machine Check Exception. */
311	unsigned u1MCE : 1;
312	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
313	unsigned u1CX8 : 1;
314	/** Bit 9 - APIC - APIC On-Chip. */
315	unsigned u1APIC : 1;
316	/** Bit 10 - Reserved. */
317	unsigned u1Reserved1 : 1;
318	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
319	unsigned u1SEP : 1;
320	/** Bit 12 - MTRR - Memory Type Range Registers. */
321	unsigned u1MTRR : 1;
322	/** Bit 13 - PGE - PTE Global Bit. */
323	unsigned u1PGE : 1;
324	/** Bit 14 - MCA - Machine Check Architecture. */
325	unsigned u1MCA : 1;
326	/** Bit 15 - CMOV - Conditional Move Instructions. */
327	unsigned u1CMOV : 1;
328	/** Bit 16 - PAT - Page Attribute Table. */
329	unsigned u1PAT : 1;
330	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
331	unsigned u1PSE36 : 1;
332	/** Bit 18 - PSN - Processor Serial Number. */
333	unsigned u1PSN : 1;
334	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
335	unsigned u1CLFSH : 1;
336	/** Bit 20 - Reserved. */
337	unsigned u1Reserved2 : 1;
338	/** Bit 21 - DS - Debug Store. */
339	unsigned u1DS : 1;
340	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
341	unsigned u1ACPI : 1;
342	/** Bit 23 - MMX - Intel MMX 'Technology'. */
343	unsigned u1MMX : 1;
344	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
345	unsigned u1FXSR : 1;
346	/** Bit 25 - SSE - SSE Support. */
347	unsigned u1SSE : 1;
348	/** Bit 26 - SSE2 - SSE2 Support. */
349	unsigned u1SSE2 : 1;
350	/** Bit 27 - SS - Self Snoop. */
351	unsigned u1SS : 1;
352	/** Bit 28 - HTT - Hyper-Threading Technology. */
353	unsigned u1HTT : 1;
354	/** Bit 29 - TM - Thermal Monitor. */
355	unsigned u1TM : 1;
356	/** Bit 30 - Reserved - . */
357	unsigned u1Reserved3 : 1;
358	/** Bit 31 - PBE - Pending Break Enabled. */
359	unsigned u1PBE : 1;
360	} X86CPUIDFEATEDX;
361	#else /* VBOX_FOR_DTRACE_LIB */
362	typedef uint32_t X86CPUIDFEATEDX;
363	#endif /* VBOX_FOR_DTRACE_LIB */
364	/** Pointer to CPUID Feature Information - EDX. */
365	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
366	/** Pointer to const CPUID Feature Information - EDX. */
367	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
368
369	/** @name CPUID Vendor information.
370	* CPUID query with EAX=0.
371	* @{
372	*/
373	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
374	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
375	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
376
377	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
378	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
379	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
380
381	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
382	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
383	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
384	/** @} */
385
386
387	/** @name CPUID Feature information.
388	* CPUID query with EAX=1.
389	* @{
390	*/
391	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
392	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
393	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
394	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
395	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
396	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
397	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
398	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
399	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
400	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
401	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
402	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
403	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
404	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
405	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
406	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
407	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
408	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
409	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
410	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
411	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
412	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
413	/** ECX Bit 12 - FMA. */
414	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
415	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
416	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
417	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
418	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
419	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
420	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
421	/** ECX Bit 17 - PCID - Process-context identifiers. */
422	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
423	/** ECX Bit 18 - DCA - Direct Cache Access. */
424	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
425	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
426	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
427	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
428	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
429	/** ECX Bit 21 - x2APIC support. */
430	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
431	/** ECX Bit 22 - MOVBE instruction. */
432	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
433	/** ECX Bit 23 - POPCNT instruction. */
434	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
435	/** ECX Bir 24 - TSC-Deadline. */
436	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
437	/** ECX Bit 25 - AES instructions. */
438	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
439	/** ECX Bit 26 - XSAVE instruction. */
440	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
441	/** ECX Bit 27 - OSXSAVE instruction. */
442	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
443	/** ECX Bit 28 - AVX. */
444	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
445	/** ECX Bit 31 - Hypervisor Present (software only). */
446	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
447
448
449	/** Bit 0 - FPU - x87 FPU on Chip. */
450	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
451	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
452	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
453	/** Bit 2 - DE - Debugging extensions. */
454	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
455	/** Bit 3 - PSE - Page Size Extension. */
456	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
457	/** Bit 4 - TSC - Time Stamp Counter. */
458	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
459	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
460	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
461	/** Bit 6 - PAE - Physical Address Extension. */
462	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
463	/** Bit 7 - MCE - Machine Check Exception. */
464	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
465	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
466	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
467	/** Bit 9 - APIC - APIC On-Chip. */
468	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
469	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
470	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
471	/** Bit 12 - MTRR - Memory Type Range Registers. */
472	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
473	/** Bit 13 - PGE - PTE Global Bit. */
474	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
475	/** Bit 14 - MCA - Machine Check Architecture. */
476	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
477	/** Bit 15 - CMOV - Conditional Move Instructions. */
478	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
479	/** Bit 16 - PAT - Page Attribute Table. */
480	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
481	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
482	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
483	/** Bit 18 - PSN - Processor Serial Number. */
484	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
485	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
486	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
487	/** Bit 21 - DS - Debug Store. */
488	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
489	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
490	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
491	/** Bit 23 - MMX - Intel MMX Technology. */
492	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
493	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
494	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
495	/** Bit 25 - SSE - SSE Support. */
496	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
497	/** Bit 26 - SSE2 - SSE2 Support. */
498	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
499	/** Bit 27 - SS - Self Snoop. */
500	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
501	/** Bit 28 - HTT - Hyper-Threading Technology. */
502	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
503	/** Bit 29 - TM - Therm. Monitor. */
504	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
505	/** Bit 31 - PBE - Pending Break Enabled. */
506	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
507	/** @} */
508
509	/** @name CPUID mwait/monitor information.
510	* CPUID query with EAX=5.
511	* @{
512	*/
513	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
514	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
515	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
516	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
517	/** @} */
518
519
520	/** @name CPUID Extended Feature information.
521	* CPUID query with EAX=0x80000001.
522	* @{
523	*/
524	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
525	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
526
527	/** EDX Bit 11 - SYSCALL/SYSRET. */
528	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
529	/** EDX Bit 20 - No-Execute/Execute-Disable. */
530	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
531	/** EDX Bit 26 - 1 GB large page. */
532	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
533	/** EDX Bit 27 - RDTSCP. */
534	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
535	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
536	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
537	/** @}*/
538
539	/** @name CPUID AMD Feature information.
540	* CPUID query with EAX=0x80000001.
541	* @{
542	*/
543	/** Bit 0 - FPU - x87 FPU on Chip. */
544	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
545	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
546	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
547	/** Bit 2 - DE - Debugging extensions. */
548	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
549	/** Bit 3 - PSE - Page Size Extension. */
550	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
551	/** Bit 4 - TSC - Time Stamp Counter. */
552	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
553	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
554	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
555	/** Bit 6 - PAE - Physical Address Extension. */
556	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
557	/** Bit 7 - MCE - Machine Check Exception. */
558	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
559	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
560	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
561	/** Bit 9 - APIC - APIC On-Chip. */
562	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
563	/** Bit 12 - MTRR - Memory Type Range Registers. */
564	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
565	/** Bit 13 - PGE - PTE Global Bit. */
566	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
567	/** Bit 14 - MCA - Machine Check Architecture. */
568	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
569	/** Bit 15 - CMOV - Conditional Move Instructions. */
570	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
571	/** Bit 16 - PAT - Page Attribute Table. */
572	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
573	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
574	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
575	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
576	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
577	/** Bit 23 - MMX - Intel MMX Technology. */
578	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
579	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
580	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
581	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
582	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
583	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
584	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
585	/** Bit 31 - 3DNOW - AMD 3DNow. */
586	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
587
588	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
589	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
590	/** Bit 2 - SVM - AMD VM extensions. */
591	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
592	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
593	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
594	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
595	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
596	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
597	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
598	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
599	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
600	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
601	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
602	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
603	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
604	/** Bit 9 - OSVW - AMD OS visible workaround. */
605	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
606	/** Bit 10 - IBS - Instruct based sampling. */
607	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
608	/** Bit 11 - SSE5 - SSE5 instruction support. */
609	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
610	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
611	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
612	/** Bit 13 - WDT - AMD Watchdog timer support. */
613	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
614
615	/** @} */
616
617
618	/** @name CPUID AMD Feature information.
619	* CPUID query with EAX=0x80000007.
620	* @{
621	*/
622	/** Bit 0 - TS - Temperature Sensor. */
623	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
624	/** Bit 1 - FID - Frequency ID Control. */
625	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
626	/** Bit 2 - VID - Voltage ID Control. */
627	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
628	/** Bit 3 - TTP - THERMTRIP. */
629	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
630	/** Bit 4 - TM - Hardware Thermal Control. */
631	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
632	/** Bit 5 - STC - Software Thermal Control. */
633	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
634	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
635	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
636	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
637	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
638	/** Bit 8 - TSCINVAR - TSC Invariant. */
639	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
640	/** @} */
641
642
643	/** @name CR0
644	* @{ */
645	/** Bit 0 - PE - Protection Enabled */
646	#define X86_CR0_PE RT_BIT(0)
647	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
648	/** Bit 1 - MP - Monitor Coprocessor */
649	#define X86_CR0_MP RT_BIT(1)
650	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
651	/** Bit 2 - EM - Emulation. */
652	#define X86_CR0_EM RT_BIT(2)
653	#define X86_CR0_EMULATE_FPU RT_BIT(2)
654	/** Bit 3 - TS - Task Switch. */
655	#define X86_CR0_TS RT_BIT(3)
656	#define X86_CR0_TASK_SWITCH RT_BIT(3)
657	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
658	#define X86_CR0_ET RT_BIT(4)
659	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
660	/** Bit 5 - NE - Numeric error. */
661	#define X86_CR0_NE RT_BIT(5)
662	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
663	/** Bit 16 - WP - Write Protect. */
664	#define X86_CR0_WP RT_BIT(16)
665	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
666	/** Bit 18 - AM - Alignment Mask. */
667	#define X86_CR0_AM RT_BIT(18)
668	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
669	/** Bit 29 - NW - Not Write-though. */
670	#define X86_CR0_NW RT_BIT(29)
671	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
672	/** Bit 30 - WP - Cache Disable. */
673	#define X86_CR0_CD RT_BIT(30)
674	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
675	/** Bit 31 - PG - Paging. */
676	#define X86_CR0_PG RT_BIT(31)
677	#define X86_CR0_PAGING RT_BIT(31)
678	/** @} */
679
680
681	/** @name CR3
682	* @{ */
683	/** Bit 3 - PWT - Page-level Writes Transparent. */
684	#define X86_CR3_PWT RT_BIT(3)
685	/** Bit 4 - PCD - Page-level Cache Disable. */
686	#define X86_CR3_PCD RT_BIT(4)
687	/** Bits 12-31 - - Page directory page number. */
688	#define X86_CR3_PAGE_MASK (0xfffff000)
689	/** Bits 5-31 - - PAE Page directory page number. */
690	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
691	/** Bits 12-51 - - AMD64 Page directory page number. */
692	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
693	/** @} */
694
695
696	/** @name CR4
697	* @{ */
698	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
699	#define X86_CR4_VME RT_BIT(0)
700	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
701	#define X86_CR4_PVI RT_BIT(1)
702	/** Bit 2 - TSD - Time Stamp Disable. */
703	#define X86_CR4_TSD RT_BIT(2)
704	/** Bit 3 - DE - Debugging Extensions. */
705	#define X86_CR4_DE RT_BIT(3)
706	/** Bit 4 - PSE - Page Size Extension. */
707	#define X86_CR4_PSE RT_BIT(4)
708	/** Bit 5 - PAE - Physical Address Extension. */
709	#define X86_CR4_PAE RT_BIT(5)
710	/** Bit 6 - MCE - Machine-Check Enable. */
711	#define X86_CR4_MCE RT_BIT(6)
712	/** Bit 7 - PGE - Page Global Enable. */
713	#define X86_CR4_PGE RT_BIT(7)
714	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
715	#define X86_CR4_PCE RT_BIT(8)
716	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
717	#define X86_CR4_OSFSXR RT_BIT(9)
718	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
719	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
720	/** Bit 13 - VMXE - VMX mode is enabled. */
721	#define X86_CR4_VMXE RT_BIT(13)
722	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
723	#define X86_CR4_SMXE RT_BIT(14)
724	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
725	#define X86_CR4_PCIDE RT_BIT(17)
726	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
727	* extended states. */
728	#define X86_CR4_OSXSAVE RT_BIT(18)
729	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
730	#define X86_CR4_SMEP RT_BIT(20)
731	/** @} */
732
733
734	/** @name DR6
735	* @{ */
736	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
737	#define X86_DR6_B0 RT_BIT(0)
738	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
739	#define X86_DR6_B1 RT_BIT(1)
740	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
741	#define X86_DR6_B2 RT_BIT(2)
742	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
743	#define X86_DR6_B3 RT_BIT(3)
744	/** Mask of all the Bx bits. */
745	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
746	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
747	#define X86_DR6_BD RT_BIT(13)
748	/** Bit 14 - BS - Single step */
749	#define X86_DR6_BS RT_BIT(14)
750	/** Bit 15 - BT - Task switch. (TSS T bit.) */
751	#define X86_DR6_BT RT_BIT(15)
752	/** Value of DR6 after powerup/reset. */
753	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
754	/** Bits which must be 1s in DR6. */
755	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
756	/** Bits which must be 0s in DR6. */
757	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
758	/** Bits which must be 0s on writes to DR6. */
759	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
760	/** @} */
761
762	/** Get the DR6.Bx bit for a the given breakpoint. */
763	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
764
765
766	/** @name DR7
767	* @{ */
768	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
769	#define X86_DR7_L0 RT_BIT(0)
770	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
771	#define X86_DR7_G0 RT_BIT(1)
772	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
773	#define X86_DR7_L1 RT_BIT(2)
774	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
775	#define X86_DR7_G1 RT_BIT(3)
776	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
777	#define X86_DR7_L2 RT_BIT(4)
778	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
779	#define X86_DR7_G2 RT_BIT(5)
780	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
781	#define X86_DR7_L3 RT_BIT(6)
782	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
783	#define X86_DR7_G3 RT_BIT(7)
784	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
785	#define X86_DR7_LE RT_BIT(8)
786	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
787	#define X86_DR7_GE RT_BIT(9)
788
789	/** L0, L1, L2, and L3. */
790	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
791	/** L0, L1, L2, and L3. */
792	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
793
794	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
795	* any DR register is accessed. */
796	#define X86_DR7_GD RT_BIT(13)
797	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
798	#define X86_DR7_RW0_MASK (3 << 16)
799	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
800	#define X86_DR7_LEN0_MASK (3 << 18)
801	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
802	#define X86_DR7_RW1_MASK (3 << 20)
803	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
804	#define X86_DR7_LEN1_MASK (3 << 22)
805	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
806	#define X86_DR7_RW2_MASK (3 << 24)
807	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
808	#define X86_DR7_LEN2_MASK (3 << 26)
809	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
810	#define X86_DR7_RW3_MASK (3 << 28)
811	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
812	#define X86_DR7_LEN3_MASK (3 << 30)
813
814	/** Bits which reads as 1s. */
815	#define X86_DR7_RA1_MASK (RT_BIT(10))
816	/** Bits which reads as zeros. */
817	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
818	/** Bits which must be 0s when writing to DR7. */
819	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
820
821	/** Calcs the L bit of Nth breakpoint.
822	* @param iBp The breakpoint number [0..3].
823	*/
824	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
825
826	/** Calcs the G bit of Nth breakpoint.
827	* @param iBp The breakpoint number [0..3].
828	*/
829	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
830
831	/** Calcs the L and G bits of Nth breakpoint.
832	* @param iBp The breakpoint number [0..3].
833	*/
834	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
835
836	/** @name Read/Write values.
837	* @{ */
838	/** Break on instruction fetch only. */
839	#define X86_DR7_RW_EO 0U
840	/** Break on write only. */
841	#define X86_DR7_RW_WO 1U
842	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
843	#define X86_DR7_RW_IO 2U
844	/** Break on read or write (but not instruction fetches). */
845	#define X86_DR7_RW_RW 3U
846	/** @} */
847
848	/** Shifts a X86_DR7_RW_* value to its right place.
849	* @param iBp The breakpoint number [0..3].
850	* @param fRw One of the X86_DR7_RW_* value.
851	*/
852	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
853
854	/** Fetch the the R/Wx bits for a given breakpoint (so it can be compared with
855	* one of the X86_DR7_RW_XXX constants).
856	*
857	* @returns X86_DR7_RW_XXX
858	* @param uDR7 DR7 value
859	* @param iBp The breakpoint number [0..3].
860	*/
861	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
862
863	/** R/W0, R/W1, R/W2, and R/W3. */
864	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
865
866	/** Checks if there are any I/O breakpoint types configured in the RW
867	* registers. Does NOT check if these are enabled, sorry. */
868	#define X86_DR7_ANY_RW_IO(uDR7) \
869	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
870	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
871	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
872	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
873	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
874	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
875	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
876	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
877	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
878	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
879	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
880
881	/** @name Length values.
882	* @{ */
883	#define X86_DR7_LEN_BYTE 0U
884	#define X86_DR7_LEN_WORD 1U
885	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
886	#define X86_DR7_LEN_DWORD 3U
887	/** @} */
888
889	/** Shifts a X86_DR7_LEN_* value to its right place.
890	* @param iBp The breakpoint number [0..3].
891	* @param cb One of the X86_DR7_LEN_* values.
892	*/
893	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
894
895	/** Fetch the breakpoint length bits from the DR7 value.
896	* @param uDR7 DR7 value
897	* @param iBp The breakpoint number [0..3].
898	*/
899	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
900
901	/** Mask used to check if any breakpoints are enabled. */
902	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
903
904	/** LEN0, LEN1, LEN2, and LEN3. */
905	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
906	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
907	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
908
909	/** Value of DR7 after powerup/reset. */
910	#define X86_DR7_INIT_VAL 0x400
911	/** @} */
912
913
914	/** @name Machine Specific Registers
915	* @{
916	*/
917
918	/** Time Stamp Counter. */
919	#define MSR_IA32_TSC 0x10
920
921	#define MSR_IA32_PLATFORM_ID 0x17
922
923	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
924	# define MSR_IA32_APICBASE 0x1b
925	/** Local APIC enabled. */
926	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
927	/** X2APIC enabled (requires the EN bit to be set). */
928	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
929	/** The processor is the boot strap processor (BSP). */
930	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
931	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
932	* width. */
933	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
934	#endif
935
936	/** CPU Feature control. */
937	#define MSR_IA32_FEATURE_CONTROL 0x3A
938	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
939	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
940
941	/** BIOS update trigger (microcode update). */
942	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
943
944	/** BIOS update signature (microcode). */
945	#define MSR_IA32_BIOS_SIGN_ID 0x8B
946
947	/** General performance counter no. 0. */
948	#define MSR_IA32_PMC0 0xC1
949	/** General performance counter no. 1. */
950	#define MSR_IA32_PMC1 0xC2
951	/** General performance counter no. 2. */
952	#define MSR_IA32_PMC2 0xC3
953	/** General performance counter no. 3. */
954	#define MSR_IA32_PMC3 0xC4
955
956	/** Nehalem power control. */
957	#define MSR_IA32_PLATFORM_INFO 0xCE
958
959	/** Get FSB clock status (Intel-specific). */
960	#define MSR_IA32_FSB_CLOCK_STS 0xCD
961
962	/** MTRR Capabilities. */
963	#define MSR_IA32_MTRR_CAP 0xFE
964
965
966	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
967	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
968	* R0 SS == CS + 8
969	* R3 CS == CS + 16
970	* R3 SS == CS + 24
971	*/
972	#define MSR_IA32_SYSENTER_CS 0x174
973	/** SYSENTER_ESP - the R0 ESP. */
974	#define MSR_IA32_SYSENTER_ESP 0x175
975	/** SYSENTER_EIP - the R0 EIP. */
976	#define MSR_IA32_SYSENTER_EIP 0x176
977	#endif
978
979	/** Machine Check Global Capabilities Register. */
980	#define MSR_IA32_MCG_CAP 0x179
981	/** Machine Check Global Status Register. */
982	#define MSR_IA32_MCG_STATUS 0x17A
983	/** Machine Check Global Control Register. */
984	#define MSR_IA32_MCG_CTRL 0x17B
985
986	/** Trace/Profile Resource Control (R/W) */
987	#define MSR_IA32_DEBUGCTL 0x1D9
988
989	/** Page Attribute Table. */
990	#define MSR_IA32_CR_PAT 0x277
991
992	/** Performance counter MSRs. (Intel only) */
993	#define MSR_IA32_PERFEVTSEL0 0x186
994	#define MSR_IA32_PERFEVTSEL1 0x187
995	#define MSR_IA32_FLEX_RATIO 0x194
996	#define MSR_IA32_PERF_STATUS 0x198
997	#define MSR_IA32_PERF_CTL 0x199
998	#define MSR_IA32_THERM_STATUS 0x19c
999
1000	/** Enable misc. processor features (R/W). */
1001	#define MSR_IA32_MISC_ENABLE 0x1A0
1002	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1003	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
1004	/** Automatic Thermal Control Circuit Enable (R/W). */
1005	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
1006	/** Performance Monitoring Available (R). */
1007	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
1008	/** Branch Trace Storage Unavailable (R/O). */
1009	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
1010	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1011	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
1012	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1013	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
1014	/** If MONITOR/MWAIT is supported (R/W). */
1015	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
1016	/** Limit CPUID Maxval to 3 leafs (R/W). */
1017	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
1018	/** When set to 1, xTPR messages are disabled (R/W). */
1019	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
1020	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1021	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
1022
1023	#define IA32_MTRR_PHYSBASE0 0x200
1024	#define IA32_MTRR_PHYSMASK0 0x201
1025	#define IA32_MTRR_PHYSBASE1 0x202
1026	#define IA32_MTRR_PHYSMASK1 0x203
1027	#define IA32_MTRR_PHYSBASE2 0x204
1028	#define IA32_MTRR_PHYSMASK2 0x205
1029	#define IA32_MTRR_PHYSBASE3 0x206
1030	#define IA32_MTRR_PHYSMASK3 0x207
1031	#define IA32_MTRR_PHYSBASE4 0x208
1032	#define IA32_MTRR_PHYSMASK4 0x209
1033	#define IA32_MTRR_PHYSBASE5 0x20a
1034	#define IA32_MTRR_PHYSMASK5 0x20b
1035	#define IA32_MTRR_PHYSBASE6 0x20c
1036	#define IA32_MTRR_PHYSMASK6 0x20d
1037	#define IA32_MTRR_PHYSBASE7 0x20e
1038	#define IA32_MTRR_PHYSMASK7 0x20f
1039	#define IA32_MTRR_PHYSBASE8 0x210
1040	#define IA32_MTRR_PHYSMASK8 0x211
1041	#define IA32_MTRR_PHYSBASE9 0x212
1042	#define IA32_MTRR_PHYSMASK9 0x213
1043
1044	/** Fixed range MTRRs.
1045	* @{ */
1046	#define IA32_MTRR_FIX64K_00000 0x250
1047	#define IA32_MTRR_FIX16K_80000 0x258
1048	#define IA32_MTRR_FIX16K_A0000 0x259
1049	#define IA32_MTRR_FIX4K_C0000 0x268
1050	#define IA32_MTRR_FIX4K_C8000 0x269
1051	#define IA32_MTRR_FIX4K_D0000 0x26a
1052	#define IA32_MTRR_FIX4K_D8000 0x26b
1053	#define IA32_MTRR_FIX4K_E0000 0x26c
1054	#define IA32_MTRR_FIX4K_E8000 0x26d
1055	#define IA32_MTRR_FIX4K_F0000 0x26e
1056	#define IA32_MTRR_FIX4K_F8000 0x26f
1057	/** @} */
1058
1059	/** MTRR Default Range. */
1060	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1061
1062	#define MSR_IA32_MC0_CTL 0x400
1063	#define MSR_IA32_MC0_STATUS 0x401
1064
1065	/** Basic VMX information. */
1066	#define MSR_IA32_VMX_BASIC_INFO 0x480
1067	/** Allowed settings for pin-based VM execution controls */
1068	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1069	/** Allowed settings for proc-based VM execution controls */
1070	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1071	/** Allowed settings for the VMX exit controls. */
1072	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1073	/** Allowed settings for the VMX entry controls. */
1074	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1075	/** Misc VMX info. */
1076	#define MSR_IA32_VMX_MISC 0x485
1077	/** Fixed cleared bits in CR0. */
1078	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1079	/** Fixed set bits in CR0. */
1080	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1081	/** Fixed cleared bits in CR4. */
1082	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1083	/** Fixed set bits in CR4. */
1084	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1085	/** Information for enumerating fields in the VMCS. */
1086	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1087	/** Allowed settings for the VM-functions controls. */
1088	#define MSR_IA32_VMX_VMFUNC 0x491
1089	/** Allowed settings for secondary proc-based VM execution controls */
1090	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1091	/** EPT capabilities. */
1092	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1093	/** DS Save Area (R/W). */
1094	#define MSR_IA32_DS_AREA 0x600
1095	/** Running Average Power Limit (RAPL) power units. */
1096	#define MSR_RAPL_POWER_UNIT 0x606
1097	/** X2APIC MSR ranges. */
1098	#define MSR_IA32_X2APIC_START 0x800
1099	#define MSR_IA32_X2APIC_TPR 0x808
1100	#define MSR_IA32_X2APIC_END 0xBFF
1101
1102	/** K6 EFER - Extended Feature Enable Register. */
1103	#define MSR_K6_EFER UINT32_C(0xc0000080)
1104	/** @todo document EFER */
1105	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1106	#define MSR_K6_EFER_SCE RT_BIT(0)
1107	/** Bit 8 - LME - Long mode enabled. (R/W) */
1108	#define MSR_K6_EFER_LME RT_BIT(8)
1109	/** Bit 10 - LMA - Long mode active. (R) */
1110	#define MSR_K6_EFER_LMA RT_BIT(10)
1111	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1112	#define MSR_K6_EFER_NXE RT_BIT(11)
1113	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1114	#define MSR_K6_EFER_SVME RT_BIT(12)
1115	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1116	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1117	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1118	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1119	/** K6 STAR - SYSCALL/RET targets. */
1120	#define MSR_K6_STAR UINT32_C(0xc0000081)
1121	/** Shift value for getting the SYSRET CS and SS value. */
1122	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1123	/** Shift value for getting the SYSCALL CS and SS value. */
1124	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1125	/** Selector mask for use after shifting. */
1126	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1127	/** The mask which give the SYSCALL EIP. */
1128	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1129	/** K6 WHCR - Write Handling Control Register. */
1130	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1131	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1132	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1133	/** K6 PSOR - Processor State Observability Register. */
1134	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1135	/** K6 PFIR - Page Flush/Invalidate Register. */
1136	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1137
1138	/** Performance counter MSRs. (AMD only) */
1139	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1140	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1141	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1142	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1143	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1144	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1145	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1146	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1147
1148	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1149	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1150	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1151	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1152	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1153	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1154	/** K8 FS.base - The 64-bit base FS register. */
1155	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1156	/** K8 GS.base - The 64-bit base GS register. */
1157	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1158	/** K8 KernelGSbase - Used with SWAPGS. */
1159	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1160	/** K8 TSC_AUX - Used with RDTSCP. */
1161	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1162	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1163	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1164	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1165	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1166	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1167	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1168	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1169	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1170	/** North bridge config? See BIOS & Kernel dev guides for
1171	* details. */
1172	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1173
1174	/** Hypertransport interrupt pending register.
1175	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1176	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1177	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1178	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1179
1180	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1181	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1182	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1183	* host state during world switch. */
1184	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1185
1186	/** @} */
1187
1188
1189	/** @name Page Table / Directory / Directory Pointers / L4.
1190	* @{
1191	*/
1192
1193	/** Page table/directory entry as an unsigned integer. */
1194	typedef uint32_t X86PGUINT;
1195	/** Pointer to a page table/directory table entry as an unsigned integer. */
1196	typedef X86PGUINT *PX86PGUINT;
1197	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1198	typedef X86PGUINT const *PCX86PGUINT;
1199
1200	/** Number of entries in a 32-bit PT/PD. */
1201	#define X86_PG_ENTRIES 1024
1202
1203
1204	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1205	typedef uint64_t X86PGPAEUINT;
1206	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1207	typedef X86PGPAEUINT *PX86PGPAEUINT;
1208	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1209	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1210
1211	/** Number of entries in a PAE PT/PD. */
1212	#define X86_PG_PAE_ENTRIES 512
1213	/** Number of entries in a PAE PDPT. */
1214	#define X86_PG_PAE_PDPE_ENTRIES 4
1215
1216	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1217	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1218	/** Number of entries in an AMD64 PDPT.
1219	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1220	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1221
1222	/** The size of a 4KB page. */
1223	#define X86_PAGE_4K_SIZE _4K
1224	/** The page shift of a 4KB page. */
1225	#define X86_PAGE_4K_SHIFT 12
1226	/** The 4KB page offset mask. */
1227	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1228	/** The 4KB page base mask for virtual addresses. */
1229	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1230	/** The 4KB page base mask for virtual addresses - 32bit version. */
1231	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1232
1233	/** The size of a 2MB page. */
1234	#define X86_PAGE_2M_SIZE _2M
1235	/** The page shift of a 2MB page. */
1236	#define X86_PAGE_2M_SHIFT 21
1237	/** The 2MB page offset mask. */
1238	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1239	/** The 2MB page base mask for virtual addresses. */
1240	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1241	/** The 2MB page base mask for virtual addresses - 32bit version. */
1242	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1243
1244	/** The size of a 4MB page. */
1245	#define X86_PAGE_4M_SIZE _4M
1246	/** The page shift of a 4MB page. */
1247	#define X86_PAGE_4M_SHIFT 22
1248	/** The 4MB page offset mask. */
1249	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1250	/** The 4MB page base mask for virtual addresses. */
1251	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1252	/** The 4MB page base mask for virtual addresses - 32bit version. */
1253	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1254
1255
1256
1257	/** @name Page Table Entry
1258	* @{
1259	*/
1260	/** Bit 0 - P - Present bit. */
1261	#define X86_PTE_BIT_P 0
1262	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1263	#define X86_PTE_BIT_RW 1
1264	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1265	#define X86_PTE_BIT_US 2
1266	/** Bit 3 - PWT - Page level write thru bit. */
1267	#define X86_PTE_BIT_PWT 3
1268	/** Bit 4 - PCD - Page level cache disable bit. */
1269	#define X86_PTE_BIT_PCD 4
1270	/** Bit 5 - A - Access bit. */
1271	#define X86_PTE_BIT_A 5
1272	/** Bit 6 - D - Dirty bit. */
1273	#define X86_PTE_BIT_D 6
1274	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1275	#define X86_PTE_BIT_PAT 7
1276	/** Bit 8 - G - Global flag. */
1277	#define X86_PTE_BIT_G 8
1278
1279	/** Bit 0 - P - Present bit mask. */
1280	#define X86_PTE_P RT_BIT(0)
1281	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1282	#define X86_PTE_RW RT_BIT(1)
1283	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1284	#define X86_PTE_US RT_BIT(2)
1285	/** Bit 3 - PWT - Page level write thru bit mask. */
1286	#define X86_PTE_PWT RT_BIT(3)
1287	/** Bit 4 - PCD - Page level cache disable bit mask. */
1288	#define X86_PTE_PCD RT_BIT(4)
1289	/** Bit 5 - A - Access bit mask. */
1290	#define X86_PTE_A RT_BIT(5)
1291	/** Bit 6 - D - Dirty bit mask. */
1292	#define X86_PTE_D RT_BIT(6)
1293	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1294	#define X86_PTE_PAT RT_BIT(7)
1295	/** Bit 8 - G - Global bit mask. */
1296	#define X86_PTE_G RT_BIT(8)
1297
1298	/** Bits 9-11 - - Available for use to system software. */
1299	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1300	/** Bits 12-31 - - Physical Page number of the next level. */
1301	#define X86_PTE_PG_MASK ( 0xfffff000 )
1302
1303	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1304	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1305	/** Bits 63 - NX - PAE/LM - No execution flag. */
1306	#define X86_PTE_PAE_NX RT_BIT_64(63)
1307	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1308	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1309	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1310	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1311	/** No bits - - LM - MBZ bits when NX is active. */
1312	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1313	/** Bits 63 - - LM - MBZ bits when no NX. */
1314	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1315
1316	/**
1317	* Page table entry.
1318	*/
1319	typedef struct X86PTEBITS
1320	{
1321	/** Flags whether(=1) or not the page is present. */
1322	unsigned u1Present : 1;
1323	/** Read(=0) / Write(=1) flag. */
1324	unsigned u1Write : 1;
1325	/** User(=1) / Supervisor (=0) flag. */
1326	unsigned u1User : 1;
1327	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1328	unsigned u1WriteThru : 1;
1329	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1330	unsigned u1CacheDisable : 1;
1331	/** Accessed flag.
1332	* Indicates that the page have been read or written to. */
1333	unsigned u1Accessed : 1;
1334	/** Dirty flag.
1335	* Indicates that the page has been written to. */
1336	unsigned u1Dirty : 1;
1337	/** Reserved / If PAT enabled, bit 2 of the index. */
1338	unsigned u1PAT : 1;
1339	/** Global flag. (Ignored in all but final level.) */
1340	unsigned u1Global : 1;
1341	/** Available for use to system software. */
1342	unsigned u3Available : 3;
1343	/** Physical Page number of the next level. */
1344	unsigned u20PageNo : 20;
1345	} X86PTEBITS;
1346	/** Pointer to a page table entry. */
1347	typedef X86PTEBITS *PX86PTEBITS;
1348	/** Pointer to a const page table entry. */
1349	typedef const X86PTEBITS *PCX86PTEBITS;
1350
1351	/**
1352	* Page table entry.
1353	*/
1354	typedef union X86PTE
1355	{
1356	/** Unsigned integer view */
1357	X86PGUINT u;
1358	/** Bit field view. */
1359	X86PTEBITS n;
1360	/** 32-bit view. */
1361	uint32_t au32[1];
1362	/** 16-bit view. */
1363	uint16_t au16[2];
1364	/** 8-bit view. */
1365	uint8_t au8[4];
1366	} X86PTE;
1367	/** Pointer to a page table entry. */
1368	typedef X86PTE *PX86PTE;
1369	/** Pointer to a const page table entry. */
1370	typedef const X86PTE *PCX86PTE;
1371
1372
1373	/**
1374	* PAE page table entry.
1375	*/
1376	typedef struct X86PTEPAEBITS
1377	{
1378	/** Flags whether(=1) or not the page is present. */
1379	uint32_t u1Present : 1;
1380	/** Read(=0) / Write(=1) flag. */
1381	uint32_t u1Write : 1;
1382	/** User(=1) / Supervisor(=0) flag. */
1383	uint32_t u1User : 1;
1384	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1385	uint32_t u1WriteThru : 1;
1386	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1387	uint32_t u1CacheDisable : 1;
1388	/** Accessed flag.
1389	* Indicates that the page have been read or written to. */
1390	uint32_t u1Accessed : 1;
1391	/** Dirty flag.
1392	* Indicates that the page has been written to. */
1393	uint32_t u1Dirty : 1;
1394	/** Reserved / If PAT enabled, bit 2 of the index. */
1395	uint32_t u1PAT : 1;
1396	/** Global flag. (Ignored in all but final level.) */
1397	uint32_t u1Global : 1;
1398	/** Available for use to system software. */
1399	uint32_t u3Available : 3;
1400	/** Physical Page number of the next level - Low Part. Don't use this. */
1401	uint32_t u20PageNoLow : 20;
1402	/** Physical Page number of the next level - High Part. Don't use this. */
1403	uint32_t u20PageNoHigh : 20;
1404	/** MBZ bits */
1405	uint32_t u11Reserved : 11;
1406	/** No Execute flag. */
1407	uint32_t u1NoExecute : 1;
1408	} X86PTEPAEBITS;
1409	/** Pointer to a page table entry. */
1410	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1411	/** Pointer to a page table entry. */
1412	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1413
1414	/**
1415	* PAE Page table entry.
1416	*/
1417	typedef union X86PTEPAE
1418	{
1419	/** Unsigned integer view */
1420	X86PGPAEUINT u;
1421	/** Bit field view. */
1422	X86PTEPAEBITS n;
1423	/** 32-bit view. */
1424	uint32_t au32[2];
1425	/** 16-bit view. */
1426	uint16_t au16[4];
1427	/** 8-bit view. */
1428	uint8_t au8[8];
1429	} X86PTEPAE;
1430	/** Pointer to a PAE page table entry. */
1431	typedef X86PTEPAE *PX86PTEPAE;
1432	/** Pointer to a const PAE page table entry. */
1433	typedef const X86PTEPAE *PCX86PTEPAE;
1434	/** @} */
1435
1436	/**
1437	* Page table.
1438	*/
1439	typedef struct X86PT
1440	{
1441	/** PTE Array. */
1442	X86PTE a[X86_PG_ENTRIES];
1443	} X86PT;
1444	/** Pointer to a page table. */
1445	typedef X86PT *PX86PT;
1446	/** Pointer to a const page table. */
1447	typedef const X86PT *PCX86PT;
1448
1449	/** The page shift to get the PT index. */
1450	#define X86_PT_SHIFT 12
1451	/** The PT index mask (apply to a shifted page address). */
1452	#define X86_PT_MASK 0x3ff
1453
1454
1455	/**
1456	* Page directory.
1457	*/
1458	typedef struct X86PTPAE
1459	{
1460	/** PTE Array. */
1461	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1462	} X86PTPAE;
1463	/** Pointer to a page table. */
1464	typedef X86PTPAE *PX86PTPAE;
1465	/** Pointer to a const page table. */
1466	typedef const X86PTPAE *PCX86PTPAE;
1467
1468	/** The page shift to get the PA PTE index. */
1469	#define X86_PT_PAE_SHIFT 12
1470	/** The PAE PT index mask (apply to a shifted page address). */
1471	#define X86_PT_PAE_MASK 0x1ff
1472
1473
1474	/** @name 4KB Page Directory Entry
1475	* @{
1476	*/
1477	/** Bit 0 - P - Present bit. */
1478	#define X86_PDE_P RT_BIT(0)
1479	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1480	#define X86_PDE_RW RT_BIT(1)
1481	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1482	#define X86_PDE_US RT_BIT(2)
1483	/** Bit 3 - PWT - Page level write thru bit. */
1484	#define X86_PDE_PWT RT_BIT(3)
1485	/** Bit 4 - PCD - Page level cache disable bit. */
1486	#define X86_PDE_PCD RT_BIT(4)
1487	/** Bit 5 - A - Access bit. */
1488	#define X86_PDE_A RT_BIT(5)
1489	/** Bit 7 - PS - Page size attribute.
1490	* Clear mean 4KB pages, set means large pages (2/4MB). */
1491	#define X86_PDE_PS RT_BIT(7)
1492	/** Bits 9-11 - - Available for use to system software. */
1493	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1494	/** Bits 12-31 - - Physical Page number of the next level. */
1495	#define X86_PDE_PG_MASK ( 0xfffff000 )
1496
1497	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1498	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1499	/** Bits 63 - NX - PAE/LM - No execution flag. */
1500	#define X86_PDE_PAE_NX RT_BIT_64(63)
1501	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1502	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1503	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1504	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1505	/** Bit 7 - - LM - MBZ bits when NX is active. */
1506	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1507	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1508	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1509
1510	/**
1511	* Page directory entry.
1512	*/
1513	typedef struct X86PDEBITS
1514	{
1515	/** Flags whether(=1) or not the page is present. */
1516	unsigned u1Present : 1;
1517	/** Read(=0) / Write(=1) flag. */
1518	unsigned u1Write : 1;
1519	/** User(=1) / Supervisor (=0) flag. */
1520	unsigned u1User : 1;
1521	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1522	unsigned u1WriteThru : 1;
1523	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1524	unsigned u1CacheDisable : 1;
1525	/** Accessed flag.
1526	* Indicates that the page has been read or written to. */
1527	unsigned u1Accessed : 1;
1528	/** Reserved / Ignored (dirty bit). */
1529	unsigned u1Reserved0 : 1;
1530	/** Size bit if PSE is enabled - in any event it's 0. */
1531	unsigned u1Size : 1;
1532	/** Reserved / Ignored (global bit). */
1533	unsigned u1Reserved1 : 1;
1534	/** Available for use to system software. */
1535	unsigned u3Available : 3;
1536	/** Physical Page number of the next level. */
1537	unsigned u20PageNo : 20;
1538	} X86PDEBITS;
1539	/** Pointer to a page directory entry. */
1540	typedef X86PDEBITS *PX86PDEBITS;
1541	/** Pointer to a const page directory entry. */
1542	typedef const X86PDEBITS *PCX86PDEBITS;
1543
1544
1545	/**
1546	* PAE page directory entry.
1547	*/
1548	typedef struct X86PDEPAEBITS
1549	{
1550	/** Flags whether(=1) or not the page is present. */
1551	uint32_t u1Present : 1;
1552	/** Read(=0) / Write(=1) flag. */
1553	uint32_t u1Write : 1;
1554	/** User(=1) / Supervisor (=0) flag. */
1555	uint32_t u1User : 1;
1556	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1557	uint32_t u1WriteThru : 1;
1558	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1559	uint32_t u1CacheDisable : 1;
1560	/** Accessed flag.
1561	* Indicates that the page has been read or written to. */
1562	uint32_t u1Accessed : 1;
1563	/** Reserved / Ignored (dirty bit). */
1564	uint32_t u1Reserved0 : 1;
1565	/** Size bit if PSE is enabled - in any event it's 0. */
1566	uint32_t u1Size : 1;
1567	/** Reserved / Ignored (global bit). / */
1568	uint32_t u1Reserved1 : 1;
1569	/** Available for use to system software. */
1570	uint32_t u3Available : 3;
1571	/** Physical Page number of the next level - Low Part. Don't use! */
1572	uint32_t u20PageNoLow : 20;
1573	/** Physical Page number of the next level - High Part. Don't use! */
1574	uint32_t u20PageNoHigh : 20;
1575	/** MBZ bits */
1576	uint32_t u11Reserved : 11;
1577	/** No Execute flag. */
1578	uint32_t u1NoExecute : 1;
1579	} X86PDEPAEBITS;
1580	/** Pointer to a page directory entry. */
1581	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1582	/** Pointer to a const page directory entry. */
1583	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1584
1585	/** @} */
1586
1587
1588	/** @name 2/4MB Page Directory Entry
1589	* @{
1590	*/
1591	/** Bit 0 - P - Present bit. */
1592	#define X86_PDE4M_P RT_BIT(0)
1593	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1594	#define X86_PDE4M_RW RT_BIT(1)
1595	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1596	#define X86_PDE4M_US RT_BIT(2)
1597	/** Bit 3 - PWT - Page level write thru bit. */
1598	#define X86_PDE4M_PWT RT_BIT(3)
1599	/** Bit 4 - PCD - Page level cache disable bit. */
1600	#define X86_PDE4M_PCD RT_BIT(4)
1601	/** Bit 5 - A - Access bit. */
1602	#define X86_PDE4M_A RT_BIT(5)
1603	/** Bit 6 - D - Dirty bit. */
1604	#define X86_PDE4M_D RT_BIT(6)
1605	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1606	#define X86_PDE4M_PS RT_BIT(7)
1607	/** Bit 8 - G - Global flag. */
1608	#define X86_PDE4M_G RT_BIT(8)
1609	/** Bits 9-11 - AVL - Available for use to system software. */
1610	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1611	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1612	#define X86_PDE4M_PAT RT_BIT(12)
1613	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1614	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1615	/** Bits 22-31 - - Physical Page number. */
1616	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1617	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1618	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1619	/** The number of bits to the high part of the page number. */
1620	#define X86_PDE4M_PG_HIGH_SHIFT 19
1621	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1622	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1623
1624	/** Bits 21-51 - - PAE/LM - Physical Page number.
1625	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1626	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1627	/** Bits 63 - NX - PAE/LM - No execution flag. */
1628	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1629	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1630	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1631	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1632	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1633	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1634	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1635	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1636	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1637
1638	/**
1639	* 4MB page directory entry.
1640	*/
1641	typedef struct X86PDE4MBITS
1642	{
1643	/** Flags whether(=1) or not the page is present. */
1644	unsigned u1Present : 1;
1645	/** Read(=0) / Write(=1) flag. */
1646	unsigned u1Write : 1;
1647	/** User(=1) / Supervisor (=0) flag. */
1648	unsigned u1User : 1;
1649	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1650	unsigned u1WriteThru : 1;
1651	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1652	unsigned u1CacheDisable : 1;
1653	/** Accessed flag.
1654	* Indicates that the page have been read or written to. */
1655	unsigned u1Accessed : 1;
1656	/** Dirty flag.
1657	* Indicates that the page has been written to. */
1658	unsigned u1Dirty : 1;
1659	/** Page size flag - always 1 for 4MB entries. */
1660	unsigned u1Size : 1;
1661	/** Global flag. */
1662	unsigned u1Global : 1;
1663	/** Available for use to system software. */
1664	unsigned u3Available : 3;
1665	/** Reserved / If PAT enabled, bit 2 of the index. */
1666	unsigned u1PAT : 1;
1667	/** Bits 32-39 of the page number on AMD64.
1668	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1669	unsigned u8PageNoHigh : 8;
1670	/** Reserved. */
1671	unsigned u1Reserved : 1;
1672	/** Physical Page number of the page. */
1673	unsigned u10PageNo : 10;
1674	} X86PDE4MBITS;
1675	/** Pointer to a page table entry. */
1676	typedef X86PDE4MBITS *PX86PDE4MBITS;
1677	/** Pointer to a const page table entry. */
1678	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1679
1680
1681	/**
1682	* 2MB PAE page directory entry.
1683	*/
1684	typedef struct X86PDE2MPAEBITS
1685	{
1686	/** Flags whether(=1) or not the page is present. */
1687	uint32_t u1Present : 1;
1688	/** Read(=0) / Write(=1) flag. */
1689	uint32_t u1Write : 1;
1690	/** User(=1) / Supervisor(=0) flag. */
1691	uint32_t u1User : 1;
1692	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1693	uint32_t u1WriteThru : 1;
1694	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1695	uint32_t u1CacheDisable : 1;
1696	/** Accessed flag.
1697	* Indicates that the page have been read or written to. */
1698	uint32_t u1Accessed : 1;
1699	/** Dirty flag.
1700	* Indicates that the page has been written to. */
1701	uint32_t u1Dirty : 1;
1702	/** Page size flag - always 1 for 2MB entries. */
1703	uint32_t u1Size : 1;
1704	/** Global flag. */
1705	uint32_t u1Global : 1;
1706	/** Available for use to system software. */
1707	uint32_t u3Available : 3;
1708	/** Reserved / If PAT enabled, bit 2 of the index. */
1709	uint32_t u1PAT : 1;
1710	/** Reserved. */
1711	uint32_t u9Reserved : 9;
1712	/** Physical Page number of the next level - Low part. Don't use! */
1713	uint32_t u10PageNoLow : 10;
1714	/** Physical Page number of the next level - High part. Don't use! */
1715	uint32_t u20PageNoHigh : 20;
1716	/** MBZ bits */
1717	uint32_t u11Reserved : 11;
1718	/** No Execute flag. */
1719	uint32_t u1NoExecute : 1;
1720	} X86PDE2MPAEBITS;
1721	/** Pointer to a 2MB PAE page table entry. */
1722	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1723	/** Pointer to a 2MB PAE page table entry. */
1724	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1725
1726	/** @} */
1727
1728	/**
1729	* Page directory entry.
1730	*/
1731	typedef union X86PDE
1732	{
1733	/** Unsigned integer view. */
1734	X86PGUINT u;
1735	/** Normal view. */
1736	X86PDEBITS n;
1737	/** 4MB view (big). */
1738	X86PDE4MBITS b;
1739	/** 8 bit unsigned integer view. */
1740	uint8_t au8[4];
1741	/** 16 bit unsigned integer view. */
1742	uint16_t au16[2];
1743	/** 32 bit unsigned integer view. */
1744	uint32_t au32[1];
1745	} X86PDE;
1746	/** Pointer to a page directory entry. */
1747	typedef X86PDE *PX86PDE;
1748	/** Pointer to a const page directory entry. */
1749	typedef const X86PDE *PCX86PDE;
1750
1751	/**
1752	* PAE page directory entry.
1753	*/
1754	typedef union X86PDEPAE
1755	{
1756	/** Unsigned integer view. */
1757	X86PGPAEUINT u;
1758	/** Normal view. */
1759	X86PDEPAEBITS n;
1760	/** 2MB page view (big). */
1761	X86PDE2MPAEBITS b;
1762	/** 8 bit unsigned integer view. */
1763	uint8_t au8[8];
1764	/** 16 bit unsigned integer view. */
1765	uint16_t au16[4];
1766	/** 32 bit unsigned integer view. */
1767	uint32_t au32[2];
1768	} X86PDEPAE;
1769	/** Pointer to a page directory entry. */
1770	typedef X86PDEPAE *PX86PDEPAE;
1771	/** Pointer to a const page directory entry. */
1772	typedef const X86PDEPAE *PCX86PDEPAE;
1773
1774	/**
1775	* Page directory.
1776	*/
1777	typedef struct X86PD
1778	{
1779	/** PDE Array. */
1780	X86PDE a[X86_PG_ENTRIES];
1781	} X86PD;
1782	/** Pointer to a page directory. */
1783	typedef X86PD *PX86PD;
1784	/** Pointer to a const page directory. */
1785	typedef const X86PD *PCX86PD;
1786
1787	/** The page shift to get the PD index. */
1788	#define X86_PD_SHIFT 22
1789	/** The PD index mask (apply to a shifted page address). */
1790	#define X86_PD_MASK 0x3ff
1791
1792
1793	/**
1794	* PAE page directory.
1795	*/
1796	typedef struct X86PDPAE
1797	{
1798	/** PDE Array. */
1799	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1800	} X86PDPAE;
1801	/** Pointer to a PAE page directory. */
1802	typedef X86PDPAE *PX86PDPAE;
1803	/** Pointer to a const PAE page directory. */
1804	typedef const X86PDPAE *PCX86PDPAE;
1805
1806	/** The page shift to get the PAE PD index. */
1807	#define X86_PD_PAE_SHIFT 21
1808	/** The PAE PD index mask (apply to a shifted page address). */
1809	#define X86_PD_PAE_MASK 0x1ff
1810
1811
1812	/** @name Page Directory Pointer Table Entry (PAE)
1813	* @{
1814	*/
1815	/** Bit 0 - P - Present bit. */
1816	#define X86_PDPE_P RT_BIT(0)
1817	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1818	#define X86_PDPE_RW RT_BIT(1)
1819	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1820	#define X86_PDPE_US RT_BIT(2)
1821	/** Bit 3 - PWT - Page level write thru bit. */
1822	#define X86_PDPE_PWT RT_BIT(3)
1823	/** Bit 4 - PCD - Page level cache disable bit. */
1824	#define X86_PDPE_PCD RT_BIT(4)
1825	/** Bit 5 - A - Access bit. Long Mode only. */
1826	#define X86_PDPE_A RT_BIT(5)
1827	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1828	#define X86_PDPE_LM_PS RT_BIT(7)
1829	/** Bits 9-11 - - Available for use to system software. */
1830	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1831	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1832	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1833	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1834	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1835	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1836	#define X86_PDPE_LM_NX RT_BIT_64(63)
1837	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1838	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1839	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1840	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1841	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1842	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1843	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1844	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1845
1846
1847	/**
1848	* Page directory pointer table entry.
1849	*/
1850	typedef struct X86PDPEBITS
1851	{
1852	/** Flags whether(=1) or not the page is present. */
1853	uint32_t u1Present : 1;
1854	/** Chunk of reserved bits. */
1855	uint32_t u2Reserved : 2;
1856	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1857	uint32_t u1WriteThru : 1;
1858	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1859	uint32_t u1CacheDisable : 1;
1860	/** Chunk of reserved bits. */
1861	uint32_t u4Reserved : 4;
1862	/** Available for use to system software. */
1863	uint32_t u3Available : 3;
1864	/** Physical Page number of the next level - Low Part. Don't use! */
1865	uint32_t u20PageNoLow : 20;
1866	/** Physical Page number of the next level - High Part. Don't use! */
1867	uint32_t u20PageNoHigh : 20;
1868	/** MBZ bits */
1869	uint32_t u12Reserved : 12;
1870	} X86PDPEBITS;
1871	/** Pointer to a page directory pointer table entry. */
1872	typedef X86PDPEBITS *PX86PTPEBITS;
1873	/** Pointer to a const page directory pointer table entry. */
1874	typedef const X86PDPEBITS *PCX86PTPEBITS;
1875
1876	/**
1877	* Page directory pointer table entry. AMD64 version
1878	*/
1879	typedef struct X86PDPEAMD64BITS
1880	{
1881	/** Flags whether(=1) or not the page is present. */
1882	uint32_t u1Present : 1;
1883	/** Read(=0) / Write(=1) flag. */
1884	uint32_t u1Write : 1;
1885	/** User(=1) / Supervisor (=0) flag. */
1886	uint32_t u1User : 1;
1887	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1888	uint32_t u1WriteThru : 1;
1889	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1890	uint32_t u1CacheDisable : 1;
1891	/** Accessed flag.
1892	* Indicates that the page have been read or written to. */
1893	uint32_t u1Accessed : 1;
1894	/** Chunk of reserved bits. */
1895	uint32_t u3Reserved : 3;
1896	/** Available for use to system software. */
1897	uint32_t u3Available : 3;
1898	/** Physical Page number of the next level - Low Part. Don't use! */
1899	uint32_t u20PageNoLow : 20;
1900	/** Physical Page number of the next level - High Part. Don't use! */
1901	uint32_t u20PageNoHigh : 20;
1902	/** MBZ bits */
1903	uint32_t u11Reserved : 11;
1904	/** No Execute flag. */
1905	uint32_t u1NoExecute : 1;
1906	} X86PDPEAMD64BITS;
1907	/** Pointer to a page directory pointer table entry. */
1908	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1909	/** Pointer to a const page directory pointer table entry. */
1910	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1911
1912	/**
1913	* Page directory pointer table entry.
1914	*/
1915	typedef union X86PDPE
1916	{
1917	/** Unsigned integer view. */
1918	X86PGPAEUINT u;
1919	/** Normal view. */
1920	X86PDPEBITS n;
1921	/** AMD64 view. */
1922	X86PDPEAMD64BITS lm;
1923	/** 8 bit unsigned integer view. */
1924	uint8_t au8[8];
1925	/** 16 bit unsigned integer view. */
1926	uint16_t au16[4];
1927	/** 32 bit unsigned integer view. */
1928	uint32_t au32[2];
1929	} X86PDPE;
1930	/** Pointer to a page directory pointer table entry. */
1931	typedef X86PDPE *PX86PDPE;
1932	/** Pointer to a const page directory pointer table entry. */
1933	typedef const X86PDPE *PCX86PDPE;
1934
1935
1936	/**
1937	* Page directory pointer table.
1938	*/
1939	typedef struct X86PDPT
1940	{
1941	/** PDE Array. */
1942	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1943	} X86PDPT;
1944	/** Pointer to a page directory pointer table. */
1945	typedef X86PDPT *PX86PDPT;
1946	/** Pointer to a const page directory pointer table. */
1947	typedef const X86PDPT *PCX86PDPT;
1948
1949	/** The page shift to get the PDPT index. */
1950	#define X86_PDPT_SHIFT 30
1951	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1952	#define X86_PDPT_MASK_PAE 0x3
1953	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1954	#define X86_PDPT_MASK_AMD64 0x1ff
1955
1956	/** @} */
1957
1958
1959	/** @name Page Map Level-4 Entry (Long Mode PAE)
1960	* @{
1961	*/
1962	/** Bit 0 - P - Present bit. */
1963	#define X86_PML4E_P RT_BIT(0)
1964	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1965	#define X86_PML4E_RW RT_BIT(1)
1966	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1967	#define X86_PML4E_US RT_BIT(2)
1968	/** Bit 3 - PWT - Page level write thru bit. */
1969	#define X86_PML4E_PWT RT_BIT(3)
1970	/** Bit 4 - PCD - Page level cache disable bit. */
1971	#define X86_PML4E_PCD RT_BIT(4)
1972	/** Bit 5 - A - Access bit. */
1973	#define X86_PML4E_A RT_BIT(5)
1974	/** Bits 9-11 - - Available for use to system software. */
1975	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1976	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1977	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1978	/** Bits 8, 7 - - MBZ bits when NX is active. */
1979	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1980	/** Bits 63, 7 - - MBZ bits when no NX. */
1981	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1982	/** Bits 63 - NX - PAE - No execution flag. */
1983	#define X86_PML4E_NX RT_BIT_64(63)
1984
1985	/**
1986	* Page Map Level-4 Entry
1987	*/
1988	typedef struct X86PML4EBITS
1989	{
1990	/** Flags whether(=1) or not the page is present. */
1991	uint32_t u1Present : 1;
1992	/** Read(=0) / Write(=1) flag. */
1993	uint32_t u1Write : 1;
1994	/** User(=1) / Supervisor (=0) flag. */
1995	uint32_t u1User : 1;
1996	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1997	uint32_t u1WriteThru : 1;
1998	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1999	uint32_t u1CacheDisable : 1;
2000	/** Accessed flag.
2001	* Indicates that the page have been read or written to. */
2002	uint32_t u1Accessed : 1;
2003	/** Chunk of reserved bits. */
2004	uint32_t u3Reserved : 3;
2005	/** Available for use to system software. */
2006	uint32_t u3Available : 3;
2007	/** Physical Page number of the next level - Low Part. Don't use! */
2008	uint32_t u20PageNoLow : 20;
2009	/** Physical Page number of the next level - High Part. Don't use! */
2010	uint32_t u20PageNoHigh : 20;
2011	/** MBZ bits */
2012	uint32_t u11Reserved : 11;
2013	/** No Execute flag. */
2014	uint32_t u1NoExecute : 1;
2015	} X86PML4EBITS;
2016	/** Pointer to a page map level-4 entry. */
2017	typedef X86PML4EBITS *PX86PML4EBITS;
2018	/** Pointer to a const page map level-4 entry. */
2019	typedef const X86PML4EBITS *PCX86PML4EBITS;
2020
2021	/**
2022	* Page Map Level-4 Entry.
2023	*/
2024	typedef union X86PML4E
2025	{
2026	/** Unsigned integer view. */
2027	X86PGPAEUINT u;
2028	/** Normal view. */
2029	X86PML4EBITS n;
2030	/** 8 bit unsigned integer view. */
2031	uint8_t au8[8];
2032	/** 16 bit unsigned integer view. */
2033	uint16_t au16[4];
2034	/** 32 bit unsigned integer view. */
2035	uint32_t au32[2];
2036	} X86PML4E;
2037	/** Pointer to a page map level-4 entry. */
2038	typedef X86PML4E *PX86PML4E;
2039	/** Pointer to a const page map level-4 entry. */
2040	typedef const X86PML4E *PCX86PML4E;
2041
2042
2043	/**
2044	* Page Map Level-4.
2045	*/
2046	typedef struct X86PML4
2047	{
2048	/** PDE Array. */
2049	X86PML4E a[X86_PG_PAE_ENTRIES];
2050	} X86PML4;
2051	/** Pointer to a page map level-4. */
2052	typedef X86PML4 *PX86PML4;
2053	/** Pointer to a const page map level-4. */
2054	typedef const X86PML4 *PCX86PML4;
2055
2056	/** The page shift to get the PML4 index. */
2057	#define X86_PML4_SHIFT 39
2058	/** The PML4 index mask (apply to a shifted page address). */
2059	#define X86_PML4_MASK 0x1ff
2060
2061	/** @} */
2062
2063	/** @} */
2064
2065
2066	/**
2067	* 80-bit MMX/FPU register type.
2068	*/
2069	typedef struct X86FPUMMX
2070	{
2071	uint8_t reg[10];
2072	} X86FPUMMX;
2073	/** Pointer to a 80-bit MMX/FPU register type. */
2074	typedef X86FPUMMX *PX86FPUMMX;
2075	/** Pointer to a const 80-bit MMX/FPU register type. */
2076	typedef const X86FPUMMX *PCX86FPUMMX;
2077
2078	/**
2079	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2080	* @todo verify this...
2081	*/
2082	#pragma pack(1)
2083	typedef struct X86FPUSTATE
2084	{
2085	/** 0x00 - Control word. */
2086	uint16_t FCW;
2087	/** 0x02 - Alignment word */
2088	uint16_t Dummy1;
2089	/** 0x04 - Status word. */
2090	uint16_t FSW;
2091	/** 0x06 - Alignment word */
2092	uint16_t Dummy2;
2093	/** 0x08 - Tag word */
2094	uint16_t FTW;
2095	/** 0x0a - Alignment word */
2096	uint16_t Dummy3;
2097
2098	/** 0x0c - Instruction pointer. */
2099	uint32_t FPUIP;
2100	/** 0x10 - Code selector. */
2101	uint16_t CS;
2102	/** 0x12 - Opcode. */
2103	uint16_t FOP;
2104	/** 0x14 - FOO. */
2105	uint32_t FPUOO;
2106	/** 0x18 - FOS. */
2107	uint32_t FPUOS;
2108	/** 0x1c */
2109	union
2110	{
2111	/** MMX view. */
2112	uint64_t mmx;
2113	/** FPU view - todo. */
2114	X86FPUMMX fpu;
2115	/** Extended precision floating point view. */
2116	RTFLOAT80U r80;
2117	/** Extended precision floating point view v2. */
2118	RTFLOAT80U2 r80Ex;
2119	/** 8-bit view. */
2120	uint8_t au8[16];
2121	/** 16-bit view. */
2122	uint16_t au16[8];
2123	/** 32-bit view. */
2124	uint32_t au32[4];
2125	/** 64-bit view. */
2126	uint64_t au64[2];
2127	/** 128-bit view. (yeah, very helpful) */
2128	uint128_t au128[1];
2129	} regs[8];
2130	} X86FPUSTATE;
2131	#pragma pack()
2132	/** Pointer to a FPU state. */
2133	typedef X86FPUSTATE *PX86FPUSTATE;
2134	/** Pointer to a const FPU state. */
2135	typedef const X86FPUSTATE *PCX86FPUSTATE;
2136
2137	/**
2138	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2139	*/
2140	#pragma pack(1)
2141	typedef struct X86FXSTATE
2142	{
2143	/** 0x00 - Control word. */
2144	uint16_t FCW;
2145	/** 0x02 - Status word. */
2146	uint16_t FSW;
2147	/** 0x04 - Tag word. (The upper byte is always zero.) */
2148	uint16_t FTW;
2149	/** 0x06 - Opcode. */
2150	uint16_t FOP;
2151	/** 0x08 - Instruction pointer. */
2152	uint32_t FPUIP;
2153	/** 0x0c - Code selector. */
2154	uint16_t CS;
2155	uint16_t Rsrvd1;
2156	/** 0x10 - Data pointer. */
2157	uint32_t FPUDP;
2158	/** 0x14 - Data segment */
2159	uint16_t DS;
2160	/** 0x16 */
2161	uint16_t Rsrvd2;
2162	/** 0x18 */
2163	uint32_t MXCSR;
2164	/** 0x1c */
2165	uint32_t MXCSR_MASK;
2166	/** 0x20 */
2167	union
2168	{
2169	/** MMX view. */
2170	uint64_t mmx;
2171	/** FPU view - todo. */
2172	X86FPUMMX fpu;
2173	/** Extended precision floating point view. */
2174	RTFLOAT80U r80;
2175	/** Extended precision floating point view v2 */
2176	RTFLOAT80U2 r80Ex;
2177	/** 8-bit view. */
2178	uint8_t au8[16];
2179	/** 16-bit view. */
2180	uint16_t au16[8];
2181	/** 32-bit view. */
2182	uint32_t au32[4];
2183	/** 64-bit view. */
2184	uint64_t au64[2];
2185	/** 128-bit view. (yeah, very helpful) */
2186	uint128_t au128[1];
2187	} aRegs[8];
2188	/* - offset 160 - */
2189	union
2190	{
2191	/** XMM Register view . /
2192	uint128_t xmm;
2193	/** 8-bit view. */
2194	uint8_t au8[16];
2195	/** 16-bit view. */
2196	uint16_t au16[8];
2197	/** 32-bit view. */
2198	uint32_t au32[4];
2199	/** 64-bit view. */
2200	uint64_t au64[2];
2201	/** 128-bit view. (yeah, very helpful) */
2202	uint128_t au128[1];
2203	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2204	/* - offset 416 - */
2205	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2206	} X86FXSTATE;
2207	#pragma pack()
2208	/** Pointer to a FPU Extended state. */
2209	typedef X86FXSTATE *PX86FXSTATE;
2210	/** Pointer to a const FPU Extended state. */
2211	typedef const X86FXSTATE *PCX86FXSTATE;
2212
2213	/** @name FPU status word flags.
2214	* @{ */
2215	/** Exception Flag: Invalid operation. */
2216	#define X86_FSW_IE RT_BIT(0)
2217	/** Exception Flag: Denormalized operand. */
2218	#define X86_FSW_DE RT_BIT(1)
2219	/** Exception Flag: Zero divide. */
2220	#define X86_FSW_ZE RT_BIT(2)
2221	/** Exception Flag: Overflow. */
2222	#define X86_FSW_OE RT_BIT(3)
2223	/** Exception Flag: Underflow. */
2224	#define X86_FSW_UE RT_BIT(4)
2225	/** Exception Flag: Precision. */
2226	#define X86_FSW_PE RT_BIT(5)
2227	/** Stack fault. */
2228	#define X86_FSW_SF RT_BIT(6)
2229	/** Error summary status. */
2230	#define X86_FSW_ES RT_BIT(7)
2231	/** Mask of exceptions flags, excluding the summary bit. */
2232	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2233	/** Mask of exceptions flags, including the summary bit. */
2234	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2235	/** Condition code 0. */
2236	#define X86_FSW_C0 RT_BIT(8)
2237	/** Condition code 1. */
2238	#define X86_FSW_C1 RT_BIT(9)
2239	/** Condition code 2. */
2240	#define X86_FSW_C2 RT_BIT(10)
2241	/** Top of the stack mask. */
2242	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2243	/** TOP shift value. */
2244	#define X86_FSW_TOP_SHIFT 11
2245	/** Mask for getting TOP value after shifting it right. */
2246	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2247	/** Get the TOP value. */
2248	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2249	/** Condition code 3. */
2250	#define X86_FSW_C3 RT_BIT(14)
2251	/** Mask of exceptions flags, including the summary bit. */
2252	#define X86_FSW_C_MASK UINT16_C(0x4700)
2253	/** FPU busy. */
2254	#define X86_FSW_B RT_BIT(15)
2255	/** @} */
2256
2257
2258	/** @name FPU control word flags.
2259	* @{ */
2260	/** Exception Mask: Invalid operation. */
2261	#define X86_FCW_IM RT_BIT(0)
2262	/** Exception Mask: Denormalized operand. */
2263	#define X86_FCW_DM RT_BIT(1)
2264	/** Exception Mask: Zero divide. */
2265	#define X86_FCW_ZM RT_BIT(2)
2266	/** Exception Mask: Overflow. */
2267	#define X86_FCW_OM RT_BIT(3)
2268	/** Exception Mask: Underflow. */
2269	#define X86_FCW_UM RT_BIT(4)
2270	/** Exception Mask: Precision. */
2271	#define X86_FCW_PM RT_BIT(5)
2272	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2273	* @remarks This includes reserved bit 6. */
2274	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2275	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2276	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2277	/** Precision control mask. */
2278	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2279	/** Precision control: 24-bit. */
2280	#define X86_FCW_PC_24 UINT16_C(0x0000)
2281	/** Precision control: Reserved. */
2282	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2283	/** Precision control: 53-bit. */
2284	#define X86_FCW_PC_53 UINT16_C(0x0200)
2285	/** Precision control: 64-bit. */
2286	#define X86_FCW_PC_64 UINT16_C(0x0300)
2287	/** Rounding control mask. */
2288	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2289	/** Rounding control: To nearest. */
2290	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2291	/** Rounding control: Down. */
2292	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2293	/** Rounding control: Up. */
2294	#define X86_FCW_RC_UP UINT16_C(0x0800)
2295	/** Rounding control: Towards zero. */
2296	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2297	/** Bits which should be zero, apparently. */
2298	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2299	/** @} */
2300
2301	/** @name SSE MXCSR
2302	* @{ */
2303	/** Exception Flag: Invalid operation. */
2304	#define X86_MSXCR_IE RT_BIT(0)
2305	/** Exception Flag: Denormalized operand. */
2306	#define X86_MSXCR_DE RT_BIT(1)
2307	/** Exception Flag: Zero divide. */
2308	#define X86_MSXCR_ZE RT_BIT(2)
2309	/** Exception Flag: Overflow. */
2310	#define X86_MSXCR_OE RT_BIT(3)
2311	/** Exception Flag: Underflow. */
2312	#define X86_MSXCR_UE RT_BIT(4)
2313	/** Exception Flag: Precision. */
2314	#define X86_MSXCR_PE RT_BIT(5)
2315
2316	/** Denormals are zero. */
2317	#define X86_MSXCR_DAZ RT_BIT(6)
2318
2319	/** Exception Mask: Invalid operation. */
2320	#define X86_MSXCR_IM RT_BIT(7)
2321	/** Exception Mask: Denormalized operand. */
2322	#define X86_MSXCR_DM RT_BIT(8)
2323	/** Exception Mask: Zero divide. */
2324	#define X86_MSXCR_ZM RT_BIT(9)
2325	/** Exception Mask: Overflow. */
2326	#define X86_MSXCR_OM RT_BIT(10)
2327	/** Exception Mask: Underflow. */
2328	#define X86_MSXCR_UM RT_BIT(11)
2329	/** Exception Mask: Precision. */
2330	#define X86_MSXCR_PM RT_BIT(12)
2331
2332	/** Rounding control mask. */
2333	#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2334	/** Rounding control: To nearest. */
2335	#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2336	/** Rounding control: Down. */
2337	#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2338	/** Rounding control: Up. */
2339	#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2340	/** Rounding control: Towards zero. */
2341	#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2342
2343	/** Flush-to-zero for masked underflow. */
2344	#define X86_MSXCR_FZ RT_BIT(15)
2345
2346	/** Misaligned Exception Mask. */
2347	#define X86_MSXCR_MM RT_BIT(16)
2348	/** @} */
2349
2350
2351	/** @name Selector Descriptor
2352	* @{
2353	*/
2354
2355	#ifndef VBOX_FOR_DTRACE_LIB
2356	/**
2357	* Descriptor attributes (as seen by VT-x).
2358	*/
2359	typedef struct X86DESCATTRBITS
2360	{
2361	/** 00 - Segment Type. */
2362	unsigned u4Type : 4;
2363	/** 04 - Descriptor Type. System(=0) or code/data selector */
2364	unsigned u1DescType : 1;
2365	/** 05 - Descriptor Privelege level. */
2366	unsigned u2Dpl : 2;
2367	/** 07 - Flags selector present(=1) or not. */
2368	unsigned u1Present : 1;
2369	/** 08 - Segment limit 16-19. */
2370	unsigned u4LimitHigh : 4;
2371	/** 0c - Available for system software. */
2372	unsigned u1Available : 1;
2373	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2374	unsigned u1Long : 1;
2375	/** 0e - This flags meaning depends on the segment type. Try make sense out
2376	* of the intel manual yourself. */
2377	unsigned u1DefBig : 1;
2378	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2379	* clear byte. */
2380	unsigned u1Granularity : 1;
2381	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2382	unsigned u1Unusable : 1;
2383	} X86DESCATTRBITS;
2384	#endif /* !VBOX_FOR_DTRACE_LIB */
2385
2386	/** @name X86DESCATTR masks
2387	* @{ */
2388	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2389	#define X86DESCATTR_DT UINT32_C(0x00000010)
2390	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2391	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2392	#define X86DESCATTR_P UINT32_C(0x00000080)
2393	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2394	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2395	#define X86DESCATTR_L UINT32_C(0x00002000)
2396	#define X86DESCATTR_D UINT32_C(0x00004000)
2397	#define X86DESCATTR_G UINT32_C(0x00008000)
2398	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2399	/** @} */
2400
2401	#pragma pack(1)
2402	typedef union X86DESCATTR
2403	{
2404	/** Unsigned integer view. */
2405	uint32_t u;
2406	#ifndef VBOX_FOR_DTRACE_LIB
2407	/** Normal view. */
2408	X86DESCATTRBITS n;
2409	#endif
2410	} X86DESCATTR;
2411	#pragma pack()
2412	/** Pointer to descriptor attributes. */
2413	typedef X86DESCATTR *PX86DESCATTR;
2414	/** Pointer to const descriptor attributes. */
2415	typedef const X86DESCATTR *PCX86DESCATTR;
2416
2417	#ifndef VBOX_FOR_DTRACE_LIB
2418
2419	/**
2420	* Generic descriptor table entry
2421	*/
2422	#pragma pack(1)
2423	typedef struct X86DESCGENERIC
2424	{
2425	/** 00 - Limit - Low word. */
2426	unsigned u16LimitLow : 16;
2427	/** 10 - Base address - lowe word.
2428	* Don't try set this to 24 because MSC is doing stupid things then. */
2429	unsigned u16BaseLow : 16;
2430	/** 20 - Base address - first 8 bits of high word. */
2431	unsigned u8BaseHigh1 : 8;
2432	/** 28 - Segment Type. */
2433	unsigned u4Type : 4;
2434	/** 2c - Descriptor Type. System(=0) or code/data selector */
2435	unsigned u1DescType : 1;
2436	/** 2d - Descriptor Privelege level. */
2437	unsigned u2Dpl : 2;
2438	/** 2f - Flags selector present(=1) or not. */
2439	unsigned u1Present : 1;
2440	/** 30 - Segment limit 16-19. */
2441	unsigned u4LimitHigh : 4;
2442	/** 34 - Available for system software. */
2443	unsigned u1Available : 1;
2444	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2445	unsigned u1Long : 1;
2446	/** 36 - This flags meaning depends on the segment type. Try make sense out
2447	* of the intel manual yourself. */
2448	unsigned u1DefBig : 1;
2449	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
2450	* clear byte. */
2451	unsigned u1Granularity : 1;
2452	/** 38 - Base address - highest 8 bits. */
2453	unsigned u8BaseHigh2 : 8;
2454	} X86DESCGENERIC;
2455	#pragma pack()
2456	/** Pointer to a generic descriptor entry. */
2457	typedef X86DESCGENERIC *PX86DESCGENERIC;
2458	/** Pointer to a const generic descriptor entry. */
2459	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2460
2461	/** @name Bit offsets of X86DESCGENERIC members.
2462	* @{*/
2463	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
2464	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
2465	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
2466	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
2467	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
2468	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
2469	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
2470	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
2471	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
2472	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
2473	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
2474	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
2475	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
2476	/** @} */
2477
2478	/**
2479	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2480	*/
2481	typedef struct X86DESCGATE
2482	{
2483	/** 00 - Target code segment offset - Low word.
2484	* Ignored if task-gate. */
2485	unsigned u16OffsetLow : 16;
2486	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2487	* TSS selector if task-gate. */
2488	unsigned u16Sel : 16;
2489	/** 20 - Number of parameters for a call-gate.
2490	* Ignored if interrupt-, trap- or task-gate. */
2491	unsigned u4ParmCount : 4;
2492	/** 24 - Reserved / ignored. */
2493	unsigned u4Reserved : 4;
2494	/** 28 - Segment Type. */
2495	unsigned u4Type : 4;
2496	/** 2c - Descriptor Type (0 = system). */
2497	unsigned u1DescType : 1;
2498	/** 2d - Descriptor Privelege level. */
2499	unsigned u2Dpl : 2;
2500	/** 2f - Flags selector present(=1) or not. */
2501	unsigned u1Present : 1;
2502	/** 30 - Target code segment offset - High word.
2503	* Ignored if task-gate. */
2504	unsigned u16OffsetHigh : 16;
2505	} X86DESCGATE;
2506	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2507	typedef X86DESCGATE *PX86DESCGATE;
2508	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2509	typedef const X86DESCGATE *PCX86DESCGATE;
2510
2511	#endif /* VBOX_FOR_DTRACE_LIB */
2512
2513	/**
2514	* Descriptor table entry.
2515	*/
2516	#pragma pack(1)
2517	typedef union X86DESC
2518	{
2519	#ifndef VBOX_FOR_DTRACE_LIB
2520	/** Generic descriptor view. */
2521	X86DESCGENERIC Gen;
2522	/** Gate descriptor view. */
2523	X86DESCGATE Gate;
2524	#endif
2525
2526	/** 8 bit unsigned integer view. */
2527	uint8_t au8[8];
2528	/** 16 bit unsigned integer view. */
2529	uint16_t au16[4];
2530	/** 32 bit unsigned integer view. */
2531	uint32_t au32[2];
2532	/** 64 bit unsigned integer view. */
2533	uint64_t au64[1];
2534	/** Unsigned integer view. */
2535	uint64_t u;
2536	} X86DESC;
2537	#ifndef VBOX_FOR_DTRACE_LIB
2538	AssertCompileSize(X86DESC, 8);
2539	#endif
2540	#pragma pack()
2541	/** Pointer to descriptor table entry. */
2542	typedef X86DESC *PX86DESC;
2543	/** Pointer to const descriptor table entry. */
2544	typedef const X86DESC *PCX86DESC;
2545
2546	/** @def X86DESC_BASE
2547	* Return the base address of a descriptor.
2548	*/
2549	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
2550	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2551	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2552	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2553
2554	/** @def X86DESC_LIMIT
2555	* Return the limit of a descriptor.
2556	*/
2557	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
2558	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2559	\| ( (a_pDesc)->Gen.u16LimitLow ) )
2560
2561	/** @def X86DESC_LIMIT_G
2562	* Return the limit of a descriptor with the granularity bit taken into account.
2563	* @returns Selector limit (uint32_t).
2564	* @param a_pDesc Pointer to the descriptor.
2565	*/
2566	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
2567	( (a_pDesc)->Gen.u1Granularity \
2568	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
2569	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
2570	)
2571
2572	/** @def X86DESC_GET_HID_ATTR
2573	* Get the descriptor attributes for the hidden register.
2574	*/
2575	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
2576	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2577
2578	#ifndef VBOX_FOR_DTRACE_LIB
2579
2580	/**
2581	* 64 bits generic descriptor table entry
2582	* Note: most of these bits have no meaning in long mode.
2583	*/
2584	#pragma pack(1)
2585	typedef struct X86DESC64GENERIC
2586	{
2587	/** Limit - Low word - IGNORED. */
2588	unsigned u16LimitLow : 16;
2589	/** Base address - low word. - IGNORED
2590	* Don't try set this to 24 because MSC is doing stupid things then. */
2591	unsigned u16BaseLow : 16;
2592	/** Base address - first 8 bits of high word. - IGNORED */
2593	unsigned u8BaseHigh1 : 8;
2594	/** Segment Type. */
2595	unsigned u4Type : 4;
2596	/** Descriptor Type. System(=0) or code/data selector */
2597	unsigned u1DescType : 1;
2598	/** Descriptor Privelege level. */
2599	unsigned u2Dpl : 2;
2600	/** Flags selector present(=1) or not. */
2601	unsigned u1Present : 1;
2602	/** Segment limit 16-19. - IGNORED */
2603	unsigned u4LimitHigh : 4;
2604	/** Available for system software. - IGNORED */
2605	unsigned u1Available : 1;
2606	/** Long mode flag. */
2607	unsigned u1Long : 1;
2608	/** This flags meaning depends on the segment type. Try make sense out
2609	* of the intel manual yourself. */
2610	unsigned u1DefBig : 1;
2611	/** Granularity of the limit. If set 4KB granularity is used, if
2612	* clear byte. - IGNORED */
2613	unsigned u1Granularity : 1;
2614	/** Base address - highest 8 bits. - IGNORED */
2615	unsigned u8BaseHigh2 : 8;
2616	/** Base address - bits 63-32. */
2617	unsigned u32BaseHigh3 : 32;
2618	unsigned u8Reserved : 8;
2619	unsigned u5Zeros : 5;
2620	unsigned u19Reserved : 19;
2621	} X86DESC64GENERIC;
2622	#pragma pack()
2623	/** Pointer to a generic descriptor entry. */
2624	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2625	/** Pointer to a const generic descriptor entry. */
2626	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2627
2628	/**
2629	* System descriptor table entry (64 bits)
2630	*
2631	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2632	*/
2633	#pragma pack(1)
2634	typedef struct X86DESC64SYSTEM
2635	{
2636	/** Limit - Low word. */
2637	unsigned u16LimitLow : 16;
2638	/** Base address - lowe word.
2639	* Don't try set this to 24 because MSC is doing stupid things then. */
2640	unsigned u16BaseLow : 16;
2641	/** Base address - first 8 bits of high word. */
2642	unsigned u8BaseHigh1 : 8;
2643	/** Segment Type. */
2644	unsigned u4Type : 4;
2645	/** Descriptor Type. System(=0) or code/data selector */
2646	unsigned u1DescType : 1;
2647	/** Descriptor Privelege level. */
2648	unsigned u2Dpl : 2;
2649	/** Flags selector present(=1) or not. */
2650	unsigned u1Present : 1;
2651	/** Segment limit 16-19. */
2652	unsigned u4LimitHigh : 4;
2653	/** Available for system software. */
2654	unsigned u1Available : 1;
2655	/** Reserved - 0. */
2656	unsigned u1Reserved : 1;
2657	/** This flags meaning depends on the segment type. Try make sense out
2658	* of the intel manual yourself. */
2659	unsigned u1DefBig : 1;
2660	/** Granularity of the limit. If set 4KB granularity is used, if
2661	* clear byte. */
2662	unsigned u1Granularity : 1;
2663	/** Base address - bits 31-24. */
2664	unsigned u8BaseHigh2 : 8;
2665	/** Base address - bits 63-32. */
2666	unsigned u32BaseHigh3 : 32;
2667	unsigned u8Reserved : 8;
2668	unsigned u5Zeros : 5;
2669	unsigned u19Reserved : 19;
2670	} X86DESC64SYSTEM;
2671	#pragma pack()
2672	/** Pointer to a system descriptor entry. */
2673	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2674	/** Pointer to a const system descriptor entry. */
2675	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2676
2677	/**
2678	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2679	*/
2680	typedef struct X86DESC64GATE
2681	{
2682	/** Target code segment offset - Low word. */
2683	unsigned u16OffsetLow : 16;
2684	/** Target code segment selector. */
2685	unsigned u16Sel : 16;
2686	/** Interrupt stack table for interrupt- and trap-gates.
2687	* Ignored by call-gates. */
2688	unsigned u3IST : 3;
2689	/** Reserved / ignored. */
2690	unsigned u5Reserved : 5;
2691	/** Segment Type. */
2692	unsigned u4Type : 4;
2693	/** Descriptor Type (0 = system). */
2694	unsigned u1DescType : 1;
2695	/** Descriptor Privelege level. */
2696	unsigned u2Dpl : 2;
2697	/** Flags selector present(=1) or not. */
2698	unsigned u1Present : 1;
2699	/** Target code segment offset - High word.
2700	* Ignored if task-gate. */
2701	unsigned u16OffsetHigh : 16;
2702	/** Target code segment offset - Top dword.
2703	* Ignored if task-gate. */
2704	unsigned u32OffsetTop : 32;
2705	/** Reserved / ignored / must be zero.
2706	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2707	unsigned u32Reserved : 32;
2708	} X86DESC64GATE;
2709	AssertCompileSize(X86DESC64GATE, 16);
2710	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2711	typedef X86DESC64GATE *PX86DESC64GATE;
2712	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2713	typedef const X86DESC64GATE *PCX86DESC64GATE;
2714
2715	#endif /* VBOX_FOR_DTRACE_LIB */
2716
2717	/**
2718	* Descriptor table entry.
2719	*/
2720	#pragma pack(1)
2721	typedef union X86DESC64
2722	{
2723	#ifndef VBOX_FOR_DTRACE_LIB
2724	/** Generic descriptor view. */
2725	X86DESC64GENERIC Gen;
2726	/** System descriptor view. */
2727	X86DESC64SYSTEM System;
2728	/** Gate descriptor view. */
2729	X86DESC64GATE Gate;
2730	#endif
2731
2732	/** 8 bit unsigned integer view. */
2733	uint8_t au8[16];
2734	/** 16 bit unsigned integer view. */
2735	uint16_t au16[8];
2736	/** 32 bit unsigned integer view. */
2737	uint32_t au32[4];
2738	/** 64 bit unsigned integer view. */
2739	uint64_t au64[2];
2740	} X86DESC64;
2741	#ifndef VBOX_FOR_DTRACE_LIB
2742	AssertCompileSize(X86DESC64, 16);
2743	#endif
2744	#pragma pack()
2745	/** Pointer to descriptor table entry. */
2746	typedef X86DESC64 *PX86DESC64;
2747	/** Pointer to const descriptor table entry. */
2748	typedef const X86DESC64 *PCX86DESC64;
2749
2750	/** @def X86DESC64_BASE
2751	* Return the base of a 64-bit descriptor.
2752	*/
2753	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
2754	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2755	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2756	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2757	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2758
2759
2760
2761	/** @name Host system descriptor table entry - Use with care!
2762	* @{ */
2763	/** Host system descriptor table entry. */
2764	#if HC_ARCH_BITS == 64
2765	typedef X86DESC64 X86DESCHC;
2766	#else
2767	typedef X86DESC X86DESCHC;
2768	#endif
2769	/** Pointer to a host system descriptor table entry. */
2770	#if HC_ARCH_BITS == 64
2771	typedef PX86DESC64 PX86DESCHC;
2772	#else
2773	typedef PX86DESC PX86DESCHC;
2774	#endif
2775	/** Pointer to a const host system descriptor table entry. */
2776	#if HC_ARCH_BITS == 64
2777	typedef PCX86DESC64 PCX86DESCHC;
2778	#else
2779	typedef PCX86DESC PCX86DESCHC;
2780	#endif
2781	/** @} */
2782
2783
2784	/** @name Selector Descriptor Types.
2785	* @{
2786	*/
2787
2788	/** @name Non-System Selector Types.
2789	* @{ */
2790	/** Code(=set)/Data(=clear) bit. */
2791	#define X86_SEL_TYPE_CODE 8
2792	/** Memory(=set)/System(=clear) bit. */
2793	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2794	/** Accessed bit. */
2795	#define X86_SEL_TYPE_ACCESSED 1
2796	/** Expand down bit (for data selectors only). */
2797	#define X86_SEL_TYPE_DOWN 4
2798	/** Conforming bit (for code selectors only). */
2799	#define X86_SEL_TYPE_CONF 4
2800	/** Write bit (for data selectors only). */
2801	#define X86_SEL_TYPE_WRITE 2
2802	/** Read bit (for code selectors only). */
2803	#define X86_SEL_TYPE_READ 2
2804	/** The bit number of the code segment read bit (relative to u4Type). */
2805	#define X86_SEL_TYPE_READ_BIT 1
2806
2807	/** Read only selector type. */
2808	#define X86_SEL_TYPE_RO 0
2809	/** Accessed read only selector type. */
2810	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2811	/** Read write selector type. */
2812	#define X86_SEL_TYPE_RW 2
2813	/** Accessed read write selector type. */
2814	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2815	/** Expand down read only selector type. */
2816	#define X86_SEL_TYPE_RO_DOWN 4
2817	/** Accessed expand down read only selector type. */
2818	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2819	/** Expand down read write selector type. */
2820	#define X86_SEL_TYPE_RW_DOWN 6
2821	/** Accessed expand down read write selector type. */
2822	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2823	/** Execute only selector type. */
2824	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2825	/** Accessed execute only selector type. */
2826	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2827	/** Execute and read selector type. */
2828	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2829	/** Accessed execute and read selector type. */
2830	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2831	/** Conforming execute only selector type. */
2832	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2833	/** Accessed Conforming execute only selector type. */
2834	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2835	/** Conforming execute and write selector type. */
2836	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2837	/** Accessed Conforming execute and write selector type. */
2838	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2839	/** @} */
2840
2841
2842	/** @name System Selector Types.
2843	* @{ */
2844	/** The TSS busy bit mask. */
2845	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2846
2847	/** Undefined system selector type. */
2848	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2849	/** 286 TSS selector. */
2850	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2851	/** LDT selector. */
2852	#define X86_SEL_TYPE_SYS_LDT 2
2853	/** 286 TSS selector - Busy. */
2854	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2855	/** 286 Callgate selector. */
2856	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2857	/** Taskgate selector. */
2858	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2859	/** 286 Interrupt gate selector. */
2860	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2861	/** 286 Trapgate selector. */
2862	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2863	/** Undefined system selector. */
2864	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2865	/** 386 TSS selector. */
2866	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2867	/** Undefined system selector. */
2868	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2869	/** 386 TSS selector - Busy. */
2870	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2871	/** 386 Callgate selector. */
2872	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2873	/** Undefined system selector. */
2874	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2875	/** 386 Interruptgate selector. */
2876	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2877	/** 386 Trapgate selector. */
2878	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2879	/** @} */
2880
2881	/** @name AMD64 System Selector Types.
2882	* @{ */
2883	/** LDT selector. */
2884	#define AMD64_SEL_TYPE_SYS_LDT 2
2885	/** TSS selector - Busy. */
2886	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2887	/** TSS selector - Busy. */
2888	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2889	/** Callgate selector. */
2890	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2891	/** Interruptgate selector. */
2892	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2893	/** Trapgate selector. */
2894	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2895	/** @} */
2896
2897	/** @} */
2898
2899
2900	/** @name Descriptor Table Entry Flag Masks.
2901	* These are for the 2nd 32-bit word of a descriptor.
2902	* @{ */
2903	/** Bits 8-11 - TYPE - Descriptor type mask. */
2904	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2905	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2906	#define X86_DESC_S RT_BIT(12)
2907	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2908	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2909	/** Bit 15 - P - Present. */
2910	#define X86_DESC_P RT_BIT(15)
2911	/** Bit 20 - AVL - Available for system software. */
2912	#define X86_DESC_AVL RT_BIT(20)
2913	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2914	#define X86_DESC_DB RT_BIT(22)
2915	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2916	* used, if clear byte. */
2917	#define X86_DESC_G RT_BIT(23)
2918	/** @} */
2919
2920	/** @} */
2921
2922
2923	/** @name Task Segments.
2924	* @{
2925	*/
2926
2927	/**
2928	* 16-bit Task Segment (TSS).
2929	*/
2930	#pragma pack(1)
2931	typedef struct X86TSS16
2932	{
2933	/** Back link to previous task. (static) */
2934	RTSEL selPrev;
2935	/** Ring-0 stack pointer. (static) */
2936	uint16_t sp0;
2937	/** Ring-0 stack segment. (static) */
2938	RTSEL ss0;
2939	/** Ring-1 stack pointer. (static) */
2940	uint16_t sp1;
2941	/** Ring-1 stack segment. (static) */
2942	RTSEL ss1;
2943	/** Ring-2 stack pointer. (static) */
2944	uint16_t sp2;
2945	/** Ring-2 stack segment. (static) */
2946	RTSEL ss2;
2947	/** IP before task switch. */
2948	uint16_t ip;
2949	/** FLAGS before task switch. */
2950	uint16_t flags;
2951	/** AX before task switch. */
2952	uint16_t ax;
2953	/** CX before task switch. */
2954	uint16_t cx;
2955	/** DX before task switch. */
2956	uint16_t dx;
2957	/** BX before task switch. */
2958	uint16_t bx;
2959	/** SP before task switch. */
2960	uint16_t sp;
2961	/** BP before task switch. */
2962	uint16_t bp;
2963	/** SI before task switch. */
2964	uint16_t si;
2965	/** DI before task switch. */
2966	uint16_t di;
2967	/** ES before task switch. */
2968	RTSEL es;
2969	/** CS before task switch. */
2970	RTSEL cs;
2971	/** SS before task switch. */
2972	RTSEL ss;
2973	/** DS before task switch. */
2974	RTSEL ds;
2975	/** LDTR before task switch. */
2976	RTSEL selLdt;
2977	} X86TSS16;
2978	#ifndef VBOX_FOR_DTRACE_LIB
2979	AssertCompileSize(X86TSS16, 44);
2980	#endif
2981	#pragma pack()
2982	/** Pointer to a 16-bit task segment. */
2983	typedef X86TSS16 *PX86TSS16;
2984	/** Pointer to a const 16-bit task segment. */
2985	typedef const X86TSS16 *PCX86TSS16;
2986
2987
2988	/**
2989	* 32-bit Task Segment (TSS).
2990	*/
2991	#pragma pack(1)
2992	typedef struct X86TSS32
2993	{
2994	/** Back link to previous task. (static) */
2995	RTSEL selPrev;
2996	uint16_t padding1;
2997	/** Ring-0 stack pointer. (static) */
2998	uint32_t esp0;
2999	/** Ring-0 stack segment. (static) */
3000	RTSEL ss0;
3001	uint16_t padding_ss0;
3002	/** Ring-1 stack pointer. (static) */
3003	uint32_t esp1;
3004	/** Ring-1 stack segment. (static) */
3005	RTSEL ss1;
3006	uint16_t padding_ss1;
3007	/** Ring-2 stack pointer. (static) */
3008	uint32_t esp2;
3009	/** Ring-2 stack segment. (static) */
3010	RTSEL ss2;
3011	uint16_t padding_ss2;
3012	/** Page directory for the task. (static) */
3013	uint32_t cr3;
3014	/** EIP before task switch. */
3015	uint32_t eip;
3016	/** EFLAGS before task switch. */
3017	uint32_t eflags;
3018	/** EAX before task switch. */
3019	uint32_t eax;
3020	/** ECX before task switch. */
3021	uint32_t ecx;
3022	/** EDX before task switch. */
3023	uint32_t edx;
3024	/** EBX before task switch. */
3025	uint32_t ebx;
3026	/** ESP before task switch. */
3027	uint32_t esp;
3028	/** EBP before task switch. */
3029	uint32_t ebp;
3030	/** ESI before task switch. */
3031	uint32_t esi;
3032	/** EDI before task switch. */
3033	uint32_t edi;
3034	/** ES before task switch. */
3035	RTSEL es;
3036	uint16_t padding_es;
3037	/** CS before task switch. */
3038	RTSEL cs;
3039	uint16_t padding_cs;
3040	/** SS before task switch. */
3041	RTSEL ss;
3042	uint16_t padding_ss;
3043	/** DS before task switch. */
3044	RTSEL ds;
3045	uint16_t padding_ds;
3046	/** FS before task switch. */
3047	RTSEL fs;
3048	uint16_t padding_fs;
3049	/** GS before task switch. */
3050	RTSEL gs;
3051	uint16_t padding_gs;
3052	/** LDTR before task switch. */
3053	RTSEL selLdt;
3054	uint16_t padding_ldt;
3055	/** Debug trap flag */
3056	uint16_t fDebugTrap;
3057	/** Offset relative to the TSS of the start of the I/O Bitmap
3058	* and the end of the interrupt redirection bitmap. */
3059	uint16_t offIoBitmap;
3060	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3061	uint8_t IntRedirBitmap[32];
3062	} X86TSS32;
3063	#pragma pack()
3064	/** Pointer to task segment. */
3065	typedef X86TSS32 *PX86TSS32;
3066	/** Pointer to const task segment. */
3067	typedef const X86TSS32 *PCX86TSS32;
3068
3069
3070	/**
3071	* 64-bit Task segment.
3072	*/
3073	#pragma pack(1)
3074	typedef struct X86TSS64
3075	{
3076	/** Reserved. */
3077	uint32_t u32Reserved;
3078	/** Ring-0 stack pointer. (static) */
3079	uint64_t rsp0;
3080	/** Ring-1 stack pointer. (static) */
3081	uint64_t rsp1;
3082	/** Ring-2 stack pointer. (static) */
3083	uint64_t rsp2;
3084	/** Reserved. */
3085	uint32_t u32Reserved2[2];
3086	/* IST */
3087	uint64_t ist1;
3088	uint64_t ist2;
3089	uint64_t ist3;
3090	uint64_t ist4;
3091	uint64_t ist5;
3092	uint64_t ist6;
3093	uint64_t ist7;
3094	/* Reserved. */
3095	uint16_t u16Reserved[5];
3096	/** Offset relative to the TSS of the start of the I/O Bitmap
3097	* and the end of the interrupt redirection bitmap. */
3098	uint16_t offIoBitmap;
3099	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3100	uint8_t IntRedirBitmap[32];
3101	} X86TSS64;
3102	#pragma pack()
3103	/** Pointer to a 64-bit task segment. */
3104	typedef X86TSS64 *PX86TSS64;
3105	/** Pointer to a const 64-bit task segment. */
3106	typedef const X86TSS64 *PCX86TSS64;
3107	#ifndef VBOX_FOR_DTRACE_LIB
3108	AssertCompileSize(X86TSS64, 136);
3109	#endif
3110
3111	/** @} */
3112
3113
3114	/** @name Selectors.
3115	* @{
3116	*/
3117
3118	/**
3119	* The shift used to convert a selector from and to index an index (C).
3120	*/
3121	#define X86_SEL_SHIFT 3
3122
3123	/**
3124	* The mask used to mask off the table indicator and RPL of an selector.
3125	*/
3126	#define X86_SEL_MASK 0xfff8U
3127
3128	/**
3129	* The mask used to mask off the RPL of an selector.
3130	* This is suitable for checking for NULL selectors.
3131	*/
3132	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3133
3134	/**
3135	* The bit indicating that a selector is in the LDT and not in the GDT.
3136	*/
3137	#define X86_SEL_LDT 0x0004U
3138
3139	/**
3140	* The bit mask for getting the RPL of a selector.
3141	*/
3142	#define X86_SEL_RPL 0x0003U
3143
3144	/**
3145	* The mask covering both RPL and LDT.
3146	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3147	* checks.
3148	*/
3149	#define X86_SEL_RPL_LDT 0x0007U
3150
3151	/** @} */
3152
3153
3154	/**
3155	* x86 Exceptions/Faults/Traps.
3156	*/
3157	typedef enum X86XCPT
3158	{
3159	/** \#DE - Divide error. */
3160	X86_XCPT_DE = 0x00,
3161	/** \#DB - Debug event (single step, DRx, ..) */
3162	X86_XCPT_DB = 0x01,
3163	/** NMI - Non-Maskable Interrupt */
3164	X86_XCPT_NMI = 0x02,
3165	/** \#BP - Breakpoint (INT3). */
3166	X86_XCPT_BP = 0x03,
3167	/** \#OF - Overflow (INTO). */
3168	X86_XCPT_OF = 0x04,
3169	/** \#BR - Bound range exceeded (BOUND). */
3170	X86_XCPT_BR = 0x05,
3171	/** \#UD - Undefined opcode. */
3172	X86_XCPT_UD = 0x06,
3173	/** \#NM - Device not available (math coprocessor device). */
3174	X86_XCPT_NM = 0x07,
3175	/** \#DF - Double fault. */
3176	X86_XCPT_DF = 0x08,
3177	/** ??? - Coprocessor segment overrun (obsolete). */
3178	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3179	/** \#TS - Taskswitch (TSS). */
3180	X86_XCPT_TS = 0x0a,
3181	/** \#NP - Segment no present. */
3182	X86_XCPT_NP = 0x0b,
3183	/** \#SS - Stack segment fault. */
3184	X86_XCPT_SS = 0x0c,
3185	/** \#GP - General protection fault. */
3186	X86_XCPT_GP = 0x0d,
3187	/** \#PF - Page fault. */
3188	X86_XCPT_PF = 0x0e,
3189	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3190	/** \#MF - Math fault (FPU). */
3191	X86_XCPT_MF = 0x10,
3192	/** \#AC - Alignment check. */
3193	X86_XCPT_AC = 0x11,
3194	/** \#MC - Machine check. */
3195	X86_XCPT_MC = 0x12,
3196	/** \#XF - SIMD Floating-Pointer Exception. */
3197	X86_XCPT_XF = 0x13,
3198	/** \#VE - Virtualzation Exception. */
3199	X86_XCPT_VE = 0x14,
3200	/** \#SX - Security Exception. */
3201	X86_XCPT_SX = 0x1f
3202	} X86XCPT;
3203	/** Pointer to a x86 exception code. */
3204	typedef X86XCPT *PX86XCPT;
3205	/** Pointer to a const x86 exception code. */
3206	typedef const X86XCPT *PCX86XCPT;
3207	/** The maximum exception value. */
3208	#define X86_XCPT_MAX (X86_XCPT_SX)
3209
3210
3211	/** @name Trap Error Codes
3212	* @{
3213	*/
3214	/** External indicator. */
3215	#define X86_TRAP_ERR_EXTERNAL 1
3216	/** IDT indicator. */
3217	#define X86_TRAP_ERR_IDT 2
3218	/** Descriptor table indicator - If set LDT, if clear GDT. */
3219	#define X86_TRAP_ERR_TI 4
3220	/** Mask for getting the selector. */
3221	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3222	/** Shift for getting the selector table index (C type index). */
3223	#define X86_TRAP_ERR_SEL_SHIFT 3
3224	/** @} */
3225
3226
3227	/** @name \#PF Trap Error Codes
3228	* @{
3229	*/
3230	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3231	#define X86_TRAP_PF_P RT_BIT(0)
3232	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3233	#define X86_TRAP_PF_RW RT_BIT(1)
3234	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3235	#define X86_TRAP_PF_US RT_BIT(2)
3236	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3237	#define X86_TRAP_PF_RSVD RT_BIT(3)
3238	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3239	#define X86_TRAP_PF_ID RT_BIT(4)
3240	/** @} */
3241
3242	#pragma pack(1)
3243	/**
3244	* 32-bit IDTR/GDTR.
3245	*/
3246	typedef struct X86XDTR32
3247	{
3248	/** Size of the descriptor table. */
3249	uint16_t cb;
3250	/** Address of the descriptor table. */
3251	#ifndef VBOX_FOR_DTRACE_LIB
3252	uint32_t uAddr;
3253	#else
3254	uint16_t au16Addr[2];
3255	#endif
3256	} X86XDTR32, *PX86XDTR32;
3257	#pragma pack()
3258
3259	#pragma pack(1)
3260	/**
3261	* 64-bit IDTR/GDTR.
3262	*/
3263	typedef struct X86XDTR64
3264	{
3265	/** Size of the descriptor table. */
3266	uint16_t cb;
3267	/** Address of the descriptor table. */
3268	#ifndef VBOX_FOR_DTRACE_LIB
3269	uint64_t uAddr;
3270	#else
3271	uint16_t au16Addr[4];
3272	#endif
3273	} X86XDTR64, *PX86XDTR64;
3274	#pragma pack()
3275
3276
3277	/** @name ModR/M
3278	* @{ */
3279	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3280	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3281	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3282	#define X86_MODRM_REG_SHIFT 3
3283	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3284	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3285	#define X86_MODRM_MOD_SHIFT 6
3286	#ifndef VBOX_FOR_DTRACE_LIB
3287	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3288	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3289	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3290	#endif
3291	/** @} */
3292
3293	/** @name SIB
3294	* @{ */
3295	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3296	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3297	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3298	#define X86_SIB_INDEX_SHIFT 3
3299	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3300	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3301	#define X86_SIB_SCALE_SHIFT 6
3302	#ifndef VBOX_FOR_DTRACE_LIB
3303	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3304	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3305	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3306	#endif
3307	/** @} */
3308
3309	/** @name General register indexes
3310	* @{ */
3311	#define X86_GREG_xAX 0
3312	#define X86_GREG_xCX 1
3313	#define X86_GREG_xDX 2
3314	#define X86_GREG_xBX 3
3315	#define X86_GREG_xSP 4
3316	#define X86_GREG_xBP 5
3317	#define X86_GREG_xSI 6
3318	#define X86_GREG_xDI 7
3319	#define X86_GREG_x8 8
3320	#define X86_GREG_x9 9
3321	#define X86_GREG_x10 10
3322	#define X86_GREG_x11 11
3323	#define X86_GREG_x12 12
3324	#define X86_GREG_x13 13
3325	#define X86_GREG_x14 14
3326	#define X86_GREG_x15 15
3327	/** @} */
3328
3329	/** @name X86_SREG_XXX - Segment register indexes.
3330	* @{ */
3331	#define X86_SREG_ES 0
3332	#define X86_SREG_CS 1
3333	#define X86_SREG_SS 2
3334	#define X86_SREG_DS 3
3335	#define X86_SREG_FS 4
3336	#define X86_SREG_GS 5
3337	/** @} */
3338	/** Segment register count. */
3339	#define X86_SREG_COUNT 6
3340
3341
3342	/** @name X86_OP_XXX - Prefixes
3343	* @{ */
3344	#define X86_OP_PRF_CS UINT8_C(0x2e)
3345	#define X86_OP_PRF_SS UINT8_C(0x36)
3346	#define X86_OP_PRF_DS UINT8_C(0x3e)
3347	#define X86_OP_PRF_ES UINT8_C(0x26)
3348	#define X86_OP_PRF_FS UINT8_C(0x64)
3349	#define X86_OP_PRF_GS UINT8_C(0x65)
3350	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3351	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3352	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3353	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3354	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3355	#define X86_OP_REX_B UINT8_C(0x41)
3356	#define X86_OP_REX_X UINT8_C(0x42)
3357	#define X86_OP_REX_R UINT8_C(0x44)
3358	#define X86_OP_REX_W UINT8_C(0x48)
3359	/** @} */
3360
3361
3362	/** @} */
3363
3364	#endif
3365

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source: vbox/trunk/include/iprt/x86.h@ 48066

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