x86.h@ 48267

Last change on this file since 48267 was 48267, checked in by vboxsync, 11 years ago
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The the IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** The status bits commonly updated by arithmetic instructions. */
215	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
216	/** @} */
217
218
219	/** CPUID Feature information - ECX.
220	* CPUID query with EAX=1.
221	*/
222	#ifndef VBOX_FOR_DTRACE_LIB
223	typedef struct X86CPUIDFEATECX
224	{
225	/** Bit 0 - SSE3 - Supports SSE3 or not. */
226	unsigned u1SSE3 : 1;
227	/** Bit 1 - PCLMULQDQ. */
228	unsigned u1PCLMULQDQ : 1;
229	/** Bit 2 - DS Area 64-bit layout. */
230	unsigned u1DTE64 : 1;
231	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
232	unsigned u1Monitor : 1;
233	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
234	unsigned u1CPLDS : 1;
235	/** Bit 5 - VMX - Virtual Machine Technology. */
236	unsigned u1VMX : 1;
237	/** Bit 6 - SMX: Safer Mode Extensions. */
238	unsigned u1SMX : 1;
239	/** Bit 7 - EST - Enh. SpeedStep Tech. */
240	unsigned u1EST : 1;
241	/** Bit 8 - TM2 - Terminal Monitor 2. */
242	unsigned u1TM2 : 1;
243	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
244	unsigned u1SSSE3 : 1;
245	/** Bit 10 - CNTX-ID - L1 Context ID. */
246	unsigned u1CNTXID : 1;
247	/** Bit 11 - Reserved. */
248	unsigned u1Reserved1 : 1;
249	/** Bit 12 - FMA. */
250	unsigned u1FMA : 1;
251	/** Bit 13 - CX16 - CMPXCHG16B. */
252	unsigned u1CX16 : 1;
253	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
254	unsigned u1TPRUpdate : 1;
255	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
256	unsigned u1PDCM : 1;
257	/** Bit 16 - Reserved. */
258	unsigned u1Reserved2 : 1;
259	/** Bit 17 - PCID - Process-context identifiers. */
260	unsigned u1PCID : 1;
261	/** Bit 18 - Direct Cache Access. */
262	unsigned u1DCA : 1;
263	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
264	unsigned u1SSE4_1 : 1;
265	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
266	unsigned u1SSE4_2 : 1;
267	/** Bit 21 - x2APIC. */
268	unsigned u1x2APIC : 1;
269	/** Bit 22 - MOVBE - Supports MOVBE. */
270	unsigned u1MOVBE : 1;
271	/** Bit 23 - POPCNT - Supports POPCNT. */
272	unsigned u1POPCNT : 1;
273	/** Bit 24 - TSC-Deadline. */
274	unsigned u1TSCDEADLINE : 1;
275	/** Bit 25 - AES. */
276	unsigned u1AES : 1;
277	/** Bit 26 - XSAVE - Supports XSAVE. */
278	unsigned u1XSAVE : 1;
279	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
280	unsigned u1OSXSAVE : 1;
281	/** Bit 28 - AVX - Supports AVX instruction extensions. */
282	unsigned u1AVX : 1;
283	/** Bit 29 - 30 - Reserved */
284	unsigned u2Reserved3 : 2;
285	/** Bit 31 - Hypervisor present (we're a guest). */
286	unsigned u1HVP : 1;
287	} X86CPUIDFEATECX;
288	#else /* VBOX_FOR_DTRACE_LIB */
289	typedef uint32_t X86CPUIDFEATECX;
290	#endif /* VBOX_FOR_DTRACE_LIB */
291	/** Pointer to CPUID Feature Information - ECX. */
292	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
293	/** Pointer to const CPUID Feature Information - ECX. */
294	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
295
296
297	/** CPUID Feature Information - EDX.
298	* CPUID query with EAX=1.
299	*/
300	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
301	typedef struct X86CPUIDFEATEDX
302	{
303	/** Bit 0 - FPU - x87 FPU on Chip. */
304	unsigned u1FPU : 1;
305	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
306	unsigned u1VME : 1;
307	/** Bit 2 - DE - Debugging extensions. */
308	unsigned u1DE : 1;
309	/** Bit 3 - PSE - Page Size Extension. */
310	unsigned u1PSE : 1;
311	/** Bit 4 - TSC - Time Stamp Counter. */
312	unsigned u1TSC : 1;
313	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
314	unsigned u1MSR : 1;
315	/** Bit 6 - PAE - Physical Address Extension. */
316	unsigned u1PAE : 1;
317	/** Bit 7 - MCE - Machine Check Exception. */
318	unsigned u1MCE : 1;
319	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
320	unsigned u1CX8 : 1;
321	/** Bit 9 - APIC - APIC On-Chip. */
322	unsigned u1APIC : 1;
323	/** Bit 10 - Reserved. */
324	unsigned u1Reserved1 : 1;
325	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
326	unsigned u1SEP : 1;
327	/** Bit 12 - MTRR - Memory Type Range Registers. */
328	unsigned u1MTRR : 1;
329	/** Bit 13 - PGE - PTE Global Bit. */
330	unsigned u1PGE : 1;
331	/** Bit 14 - MCA - Machine Check Architecture. */
332	unsigned u1MCA : 1;
333	/** Bit 15 - CMOV - Conditional Move Instructions. */
334	unsigned u1CMOV : 1;
335	/** Bit 16 - PAT - Page Attribute Table. */
336	unsigned u1PAT : 1;
337	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
338	unsigned u1PSE36 : 1;
339	/** Bit 18 - PSN - Processor Serial Number. */
340	unsigned u1PSN : 1;
341	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
342	unsigned u1CLFSH : 1;
343	/** Bit 20 - Reserved. */
344	unsigned u1Reserved2 : 1;
345	/** Bit 21 - DS - Debug Store. */
346	unsigned u1DS : 1;
347	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
348	unsigned u1ACPI : 1;
349	/** Bit 23 - MMX - Intel MMX 'Technology'. */
350	unsigned u1MMX : 1;
351	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
352	unsigned u1FXSR : 1;
353	/** Bit 25 - SSE - SSE Support. */
354	unsigned u1SSE : 1;
355	/** Bit 26 - SSE2 - SSE2 Support. */
356	unsigned u1SSE2 : 1;
357	/** Bit 27 - SS - Self Snoop. */
358	unsigned u1SS : 1;
359	/** Bit 28 - HTT - Hyper-Threading Technology. */
360	unsigned u1HTT : 1;
361	/** Bit 29 - TM - Thermal Monitor. */
362	unsigned u1TM : 1;
363	/** Bit 30 - Reserved - . */
364	unsigned u1Reserved3 : 1;
365	/** Bit 31 - PBE - Pending Break Enabled. */
366	unsigned u1PBE : 1;
367	} X86CPUIDFEATEDX;
368	#else /* VBOX_FOR_DTRACE_LIB */
369	typedef uint32_t X86CPUIDFEATEDX;
370	#endif /* VBOX_FOR_DTRACE_LIB */
371	/** Pointer to CPUID Feature Information - EDX. */
372	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
373	/** Pointer to const CPUID Feature Information - EDX. */
374	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
375
376	/** @name CPUID Vendor information.
377	* CPUID query with EAX=0.
378	* @{
379	*/
380	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
381	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
382	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
383
384	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
385	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
386	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
387
388	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
389	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
390	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
391	/** @} */
392
393
394	/** @name CPUID Feature information.
395	* CPUID query with EAX=1.
396	* @{
397	*/
398	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
399	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
400	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
401	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
402	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
403	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
404	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
405	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
406	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
407	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
408	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
409	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
410	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
411	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
412	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
413	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
414	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
415	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
416	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
417	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
418	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
419	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
420	/** ECX Bit 12 - FMA. */
421	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
422	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
423	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
424	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
425	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
426	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
427	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
428	/** ECX Bit 17 - PCID - Process-context identifiers. */
429	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
430	/** ECX Bit 18 - DCA - Direct Cache Access. */
431	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
432	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
433	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
434	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
435	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
436	/** ECX Bit 21 - x2APIC support. */
437	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
438	/** ECX Bit 22 - MOVBE instruction. */
439	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
440	/** ECX Bit 23 - POPCNT instruction. */
441	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
442	/** ECX Bir 24 - TSC-Deadline. */
443	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
444	/** ECX Bit 25 - AES instructions. */
445	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
446	/** ECX Bit 26 - XSAVE instruction. */
447	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
448	/** ECX Bit 27 - OSXSAVE instruction. */
449	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
450	/** ECX Bit 28 - AVX. */
451	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
452	/** ECX Bit 31 - Hypervisor Present (software only). */
453	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
454
455
456	/** Bit 0 - FPU - x87 FPU on Chip. */
457	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
458	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
459	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
460	/** Bit 2 - DE - Debugging extensions. */
461	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
462	/** Bit 3 - PSE - Page Size Extension. */
463	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
464	/** Bit 4 - TSC - Time Stamp Counter. */
465	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
466	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
467	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
468	/** Bit 6 - PAE - Physical Address Extension. */
469	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
470	/** Bit 7 - MCE - Machine Check Exception. */
471	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
472	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
473	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
474	/** Bit 9 - APIC - APIC On-Chip. */
475	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
476	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
477	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
478	/** Bit 12 - MTRR - Memory Type Range Registers. */
479	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
480	/** Bit 13 - PGE - PTE Global Bit. */
481	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
482	/** Bit 14 - MCA - Machine Check Architecture. */
483	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
484	/** Bit 15 - CMOV - Conditional Move Instructions. */
485	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
486	/** Bit 16 - PAT - Page Attribute Table. */
487	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
488	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
489	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
490	/** Bit 18 - PSN - Processor Serial Number. */
491	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
492	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
493	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
494	/** Bit 21 - DS - Debug Store. */
495	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
496	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
497	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
498	/** Bit 23 - MMX - Intel MMX Technology. */
499	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
500	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
501	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
502	/** Bit 25 - SSE - SSE Support. */
503	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
504	/** Bit 26 - SSE2 - SSE2 Support. */
505	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
506	/** Bit 27 - SS - Self Snoop. */
507	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
508	/** Bit 28 - HTT - Hyper-Threading Technology. */
509	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
510	/** Bit 29 - TM - Therm. Monitor. */
511	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
512	/** Bit 31 - PBE - Pending Break Enabled. */
513	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
514	/** @} */
515
516	/** @name CPUID mwait/monitor information.
517	* CPUID query with EAX=5.
518	* @{
519	*/
520	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
521	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
522	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
523	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
524	/** @} */
525
526
527	/** @name CPUID Extended Feature information.
528	* CPUID query with EAX=0x80000001.
529	* @{
530	*/
531	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
532	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
533
534	/** EDX Bit 11 - SYSCALL/SYSRET. */
535	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
536	/** EDX Bit 20 - No-Execute/Execute-Disable. */
537	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
538	/** EDX Bit 26 - 1 GB large page. */
539	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
540	/** EDX Bit 27 - RDTSCP. */
541	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
542	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
543	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
544	/** @}*/
545
546	/** @name CPUID AMD Feature information.
547	* CPUID query with EAX=0x80000001.
548	* @{
549	*/
550	/** Bit 0 - FPU - x87 FPU on Chip. */
551	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
552	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
553	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
554	/** Bit 2 - DE - Debugging extensions. */
555	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
556	/** Bit 3 - PSE - Page Size Extension. */
557	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
558	/** Bit 4 - TSC - Time Stamp Counter. */
559	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
560	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
561	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
562	/** Bit 6 - PAE - Physical Address Extension. */
563	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
564	/** Bit 7 - MCE - Machine Check Exception. */
565	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
566	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
567	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
568	/** Bit 9 - APIC - APIC On-Chip. */
569	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
570	/** Bit 12 - MTRR - Memory Type Range Registers. */
571	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
572	/** Bit 13 - PGE - PTE Global Bit. */
573	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
574	/** Bit 14 - MCA - Machine Check Architecture. */
575	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
576	/** Bit 15 - CMOV - Conditional Move Instructions. */
577	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
578	/** Bit 16 - PAT - Page Attribute Table. */
579	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
580	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
581	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
582	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
583	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
584	/** Bit 23 - MMX - Intel MMX Technology. */
585	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
586	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
587	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
588	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
589	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
590	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
591	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
592	/** Bit 31 - 3DNOW - AMD 3DNow. */
593	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
594
595	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
596	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
597	/** Bit 2 - SVM - AMD VM extensions. */
598	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
599	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
600	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
601	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
602	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
603	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
604	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
605	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
606	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
607	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
608	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
609	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
610	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
611	/** Bit 9 - OSVW - AMD OS visible workaround. */
612	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
613	/** Bit 10 - IBS - Instruct based sampling. */
614	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
615	/** Bit 11 - SSE5 - SSE5 instruction support. */
616	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
617	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
618	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
619	/** Bit 13 - WDT - AMD Watchdog timer support. */
620	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
621
622	/** @} */
623
624
625	/** @name CPUID AMD Feature information.
626	* CPUID query with EAX=0x80000007.
627	* @{
628	*/
629	/** Bit 0 - TS - Temperature Sensor. */
630	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
631	/** Bit 1 - FID - Frequency ID Control. */
632	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
633	/** Bit 2 - VID - Voltage ID Control. */
634	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
635	/** Bit 3 - TTP - THERMTRIP. */
636	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
637	/** Bit 4 - TM - Hardware Thermal Control. */
638	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
639	/** Bit 5 - STC - Software Thermal Control. */
640	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
641	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
642	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
643	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
644	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
645	/** Bit 8 - TSCINVAR - TSC Invariant. */
646	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
647	/** @} */
648
649
650	/** @name CR0
651	* @{ */
652	/** Bit 0 - PE - Protection Enabled */
653	#define X86_CR0_PE RT_BIT(0)
654	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
655	/** Bit 1 - MP - Monitor Coprocessor */
656	#define X86_CR0_MP RT_BIT(1)
657	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
658	/** Bit 2 - EM - Emulation. */
659	#define X86_CR0_EM RT_BIT(2)
660	#define X86_CR0_EMULATE_FPU RT_BIT(2)
661	/** Bit 3 - TS - Task Switch. */
662	#define X86_CR0_TS RT_BIT(3)
663	#define X86_CR0_TASK_SWITCH RT_BIT(3)
664	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
665	#define X86_CR0_ET RT_BIT(4)
666	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
667	/** Bit 5 - NE - Numeric error. */
668	#define X86_CR0_NE RT_BIT(5)
669	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
670	/** Bit 16 - WP - Write Protect. */
671	#define X86_CR0_WP RT_BIT(16)
672	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
673	/** Bit 18 - AM - Alignment Mask. */
674	#define X86_CR0_AM RT_BIT(18)
675	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
676	/** Bit 29 - NW - Not Write-though. */
677	#define X86_CR0_NW RT_BIT(29)
678	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
679	/** Bit 30 - WP - Cache Disable. */
680	#define X86_CR0_CD RT_BIT(30)
681	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
682	/** Bit 31 - PG - Paging. */
683	#define X86_CR0_PG RT_BIT(31)
684	#define X86_CR0_PAGING RT_BIT(31)
685	/** @} */
686
687
688	/** @name CR3
689	* @{ */
690	/** Bit 3 - PWT - Page-level Writes Transparent. */
691	#define X86_CR3_PWT RT_BIT(3)
692	/** Bit 4 - PCD - Page-level Cache Disable. */
693	#define X86_CR3_PCD RT_BIT(4)
694	/** Bits 12-31 - - Page directory page number. */
695	#define X86_CR3_PAGE_MASK (0xfffff000)
696	/** Bits 5-31 - - PAE Page directory page number. */
697	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
698	/** Bits 12-51 - - AMD64 Page directory page number. */
699	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
700	/** @} */
701
702
703	/** @name CR4
704	* @{ */
705	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
706	#define X86_CR4_VME RT_BIT(0)
707	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
708	#define X86_CR4_PVI RT_BIT(1)
709	/** Bit 2 - TSD - Time Stamp Disable. */
710	#define X86_CR4_TSD RT_BIT(2)
711	/** Bit 3 - DE - Debugging Extensions. */
712	#define X86_CR4_DE RT_BIT(3)
713	/** Bit 4 - PSE - Page Size Extension. */
714	#define X86_CR4_PSE RT_BIT(4)
715	/** Bit 5 - PAE - Physical Address Extension. */
716	#define X86_CR4_PAE RT_BIT(5)
717	/** Bit 6 - MCE - Machine-Check Enable. */
718	#define X86_CR4_MCE RT_BIT(6)
719	/** Bit 7 - PGE - Page Global Enable. */
720	#define X86_CR4_PGE RT_BIT(7)
721	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
722	#define X86_CR4_PCE RT_BIT(8)
723	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
724	#define X86_CR4_OSFSXR RT_BIT(9)
725	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
726	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
727	/** Bit 13 - VMXE - VMX mode is enabled. */
728	#define X86_CR4_VMXE RT_BIT(13)
729	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
730	#define X86_CR4_SMXE RT_BIT(14)
731	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
732	#define X86_CR4_PCIDE RT_BIT(17)
733	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
734	* extended states. */
735	#define X86_CR4_OSXSAVE RT_BIT(18)
736	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
737	#define X86_CR4_SMEP RT_BIT(20)
738	/** @} */
739
740
741	/** @name DR6
742	* @{ */
743	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
744	#define X86_DR6_B0 RT_BIT(0)
745	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
746	#define X86_DR6_B1 RT_BIT(1)
747	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
748	#define X86_DR6_B2 RT_BIT(2)
749	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
750	#define X86_DR6_B3 RT_BIT(3)
751	/** Mask of all the Bx bits. */
752	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
753	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
754	#define X86_DR6_BD RT_BIT(13)
755	/** Bit 14 - BS - Single step */
756	#define X86_DR6_BS RT_BIT(14)
757	/** Bit 15 - BT - Task switch. (TSS T bit.) */
758	#define X86_DR6_BT RT_BIT(15)
759	/** Value of DR6 after powerup/reset. */
760	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
761	/** Bits which must be 1s in DR6. */
762	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
763	/** Bits which must be 0s in DR6. */
764	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
765	/** Bits which must be 0s on writes to DR6. */
766	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
767	/** @} */
768
769	/** Get the DR6.Bx bit for a the given breakpoint. */
770	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
771
772
773	/** @name DR7
774	* @{ */
775	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
776	#define X86_DR7_L0 RT_BIT(0)
777	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
778	#define X86_DR7_G0 RT_BIT(1)
779	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
780	#define X86_DR7_L1 RT_BIT(2)
781	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
782	#define X86_DR7_G1 RT_BIT(3)
783	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
784	#define X86_DR7_L2 RT_BIT(4)
785	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
786	#define X86_DR7_G2 RT_BIT(5)
787	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
788	#define X86_DR7_L3 RT_BIT(6)
789	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
790	#define X86_DR7_G3 RT_BIT(7)
791	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
792	#define X86_DR7_LE RT_BIT(8)
793	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
794	#define X86_DR7_GE RT_BIT(9)
795
796	/** L0, L1, L2, and L3. */
797	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
798	/** L0, L1, L2, and L3. */
799	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
800
801	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
802	* any DR register is accessed. */
803	#define X86_DR7_GD RT_BIT(13)
804	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
805	#define X86_DR7_RW0_MASK (3 << 16)
806	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
807	#define X86_DR7_LEN0_MASK (3 << 18)
808	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
809	#define X86_DR7_RW1_MASK (3 << 20)
810	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
811	#define X86_DR7_LEN1_MASK (3 << 22)
812	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
813	#define X86_DR7_RW2_MASK (3 << 24)
814	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
815	#define X86_DR7_LEN2_MASK (3 << 26)
816	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
817	#define X86_DR7_RW3_MASK (3 << 28)
818	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
819	#define X86_DR7_LEN3_MASK (3 << 30)
820
821	/** Bits which reads as 1s. */
822	#define X86_DR7_RA1_MASK (RT_BIT(10))
823	/** Bits which reads as zeros. */
824	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
825	/** Bits which must be 0s when writing to DR7. */
826	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
827
828	/** Calcs the L bit of Nth breakpoint.
829	* @param iBp The breakpoint number [0..3].
830	*/
831	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
832
833	/** Calcs the G bit of Nth breakpoint.
834	* @param iBp The breakpoint number [0..3].
835	*/
836	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
837
838	/** Calcs the L and G bits of Nth breakpoint.
839	* @param iBp The breakpoint number [0..3].
840	*/
841	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
842
843	/** @name Read/Write values.
844	* @{ */
845	/** Break on instruction fetch only. */
846	#define X86_DR7_RW_EO 0U
847	/** Break on write only. */
848	#define X86_DR7_RW_WO 1U
849	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
850	#define X86_DR7_RW_IO 2U
851	/** Break on read or write (but not instruction fetches). */
852	#define X86_DR7_RW_RW 3U
853	/** @} */
854
855	/** Shifts a X86_DR7_RW_* value to its right place.
856	* @param iBp The breakpoint number [0..3].
857	* @param fRw One of the X86_DR7_RW_* value.
858	*/
859	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
860
861	/** Fetch the the R/Wx bits for a given breakpoint (so it can be compared with
862	* one of the X86_DR7_RW_XXX constants).
863	*
864	* @returns X86_DR7_RW_XXX
865	* @param uDR7 DR7 value
866	* @param iBp The breakpoint number [0..3].
867	*/
868	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
869
870	/** R/W0, R/W1, R/W2, and R/W3. */
871	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
872
873	/** Checks if there are any I/O breakpoint types configured in the RW
874	* registers. Does NOT check if these are enabled, sorry. */
875	#define X86_DR7_ANY_RW_IO(uDR7) \
876	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
877	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
878	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
879	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
880	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
881	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
882	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
883	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
884	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
885	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
886	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
887
888	/** @name Length values.
889	* @{ */
890	#define X86_DR7_LEN_BYTE 0U
891	#define X86_DR7_LEN_WORD 1U
892	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
893	#define X86_DR7_LEN_DWORD 3U
894	/** @} */
895
896	/** Shifts a X86_DR7_LEN_* value to its right place.
897	* @param iBp The breakpoint number [0..3].
898	* @param cb One of the X86_DR7_LEN_* values.
899	*/
900	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
901
902	/** Fetch the breakpoint length bits from the DR7 value.
903	* @param uDR7 DR7 value
904	* @param iBp The breakpoint number [0..3].
905	*/
906	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
907
908	/** Mask used to check if any breakpoints are enabled. */
909	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
910
911	/** LEN0, LEN1, LEN2, and LEN3. */
912	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
913	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
914	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
915
916	/** Value of DR7 after powerup/reset. */
917	#define X86_DR7_INIT_VAL 0x400
918	/** @} */
919
920
921	/** @name Machine Specific Registers
922	* @{
923	*/
924	/** Machine check address register (P5). */
925	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
926	/** Machine check type register (P5). */
927	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
928	/** Time Stamp Counter. */
929	#define MSR_IA32_TSC 0x10
930	#define MSR_IA32_CESR UINT32_C(0x00000011)
931	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
932	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
933
934	#define MSR_IA32_PLATFORM_ID 0x17
935
936	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
937	# define MSR_IA32_APICBASE 0x1b
938	/** Local APIC enabled. */
939	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
940	/** X2APIC enabled (requires the EN bit to be set). */
941	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
942	/** The processor is the boot strap processor (BSP). */
943	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
944	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
945	* width. */
946	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
947	#endif
948
949	/** CPU Feature control. */
950	#define MSR_IA32_FEATURE_CONTROL 0x3A
951	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
952	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
953	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
954
955	/** BIOS update trigger (microcode update). */
956	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
957
958	/** BIOS update signature (microcode). */
959	#define MSR_IA32_BIOS_SIGN_ID 0x8B
960
961	/** General performance counter no. 0. */
962	#define MSR_IA32_PMC0 0xC1
963	/** General performance counter no. 1. */
964	#define MSR_IA32_PMC1 0xC2
965	/** General performance counter no. 2. */
966	#define MSR_IA32_PMC2 0xC3
967	/** General performance counter no. 3. */
968	#define MSR_IA32_PMC3 0xC4
969
970	/** Nehalem power control. */
971	#define MSR_IA32_PLATFORM_INFO 0xCE
972
973	/** Get FSB clock status (Intel-specific). */
974	#define MSR_IA32_FSB_CLOCK_STS 0xCD
975
976	/** MTRR Capabilities. */
977	#define MSR_IA32_MTRR_CAP 0xFE
978
979	/** Cache control/info. */
980	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
981
982	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
983	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
984	* R0 SS == CS + 8
985	* R3 CS == CS + 16
986	* R3 SS == CS + 24
987	*/
988	#define MSR_IA32_SYSENTER_CS 0x174
989	/** SYSENTER_ESP - the R0 ESP. */
990	#define MSR_IA32_SYSENTER_ESP 0x175
991	/** SYSENTER_EIP - the R0 EIP. */
992	#define MSR_IA32_SYSENTER_EIP 0x176
993	#endif
994
995	/** Machine Check Global Capabilities Register. */
996	#define MSR_IA32_MCG_CAP 0x179
997	/** Machine Check Global Status Register. */
998	#define MSR_IA32_MCG_STATUS 0x17A
999	/** Machine Check Global Control Register. */
1000	#define MSR_IA32_MCG_CTRL 0x17B
1001
1002	/** Page Attribute Table. */
1003	#define MSR_IA32_CR_PAT 0x277
1004
1005	/** Performance counter MSRs. (Intel only) */
1006	#define MSR_IA32_PERFEVTSEL0 0x186
1007	#define MSR_IA32_PERFEVTSEL1 0x187
1008	#define MSR_IA32_FLEX_RATIO 0x194
1009	#define MSR_IA32_PERF_STATUS 0x198
1010	#define MSR_IA32_PERF_CTL 0x199
1011	#define MSR_IA32_THERM_STATUS 0x19c
1012
1013	/** Enable misc. processor features (R/W). */
1014	#define MSR_IA32_MISC_ENABLE 0x1A0
1015	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1016	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
1017	/** Automatic Thermal Control Circuit Enable (R/W). */
1018	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
1019	/** Performance Monitoring Available (R). */
1020	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
1021	/** Branch Trace Storage Unavailable (R/O). */
1022	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
1023	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1024	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
1025	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1026	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
1027	/** If MONITOR/MWAIT is supported (R/W). */
1028	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
1029	/** Limit CPUID Maxval to 3 leafs (R/W). */
1030	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
1031	/** When set to 1, xTPR messages are disabled (R/W). */
1032	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
1033	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1034	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
1035
1036	/** Trace/Profile Resource Control (R/W) */
1037	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1038	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1039	* related Xeons. */
1040	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1041	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1042	* @{ */
1043	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1044	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1045	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1046	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1047	/** @} */
1048
1049
1050	#define IA32_MTRR_PHYSBASE0 0x200
1051	#define IA32_MTRR_PHYSMASK0 0x201
1052	#define IA32_MTRR_PHYSBASE1 0x202
1053	#define IA32_MTRR_PHYSMASK1 0x203
1054	#define IA32_MTRR_PHYSBASE2 0x204
1055	#define IA32_MTRR_PHYSMASK2 0x205
1056	#define IA32_MTRR_PHYSBASE3 0x206
1057	#define IA32_MTRR_PHYSMASK3 0x207
1058	#define IA32_MTRR_PHYSBASE4 0x208
1059	#define IA32_MTRR_PHYSMASK4 0x209
1060	#define IA32_MTRR_PHYSBASE5 0x20a
1061	#define IA32_MTRR_PHYSMASK5 0x20b
1062	#define IA32_MTRR_PHYSBASE6 0x20c
1063	#define IA32_MTRR_PHYSMASK6 0x20d
1064	#define IA32_MTRR_PHYSBASE7 0x20e
1065	#define IA32_MTRR_PHYSMASK7 0x20f
1066	#define IA32_MTRR_PHYSBASE8 0x210
1067	#define IA32_MTRR_PHYSMASK8 0x211
1068	#define IA32_MTRR_PHYSBASE9 0x212
1069	#define IA32_MTRR_PHYSMASK9 0x213
1070
1071	/** Fixed range MTRRs.
1072	* @{ */
1073	#define IA32_MTRR_FIX64K_00000 0x250
1074	#define IA32_MTRR_FIX16K_80000 0x258
1075	#define IA32_MTRR_FIX16K_A0000 0x259
1076	#define IA32_MTRR_FIX4K_C0000 0x268
1077	#define IA32_MTRR_FIX4K_C8000 0x269
1078	#define IA32_MTRR_FIX4K_D0000 0x26a
1079	#define IA32_MTRR_FIX4K_D8000 0x26b
1080	#define IA32_MTRR_FIX4K_E0000 0x26c
1081	#define IA32_MTRR_FIX4K_E8000 0x26d
1082	#define IA32_MTRR_FIX4K_F0000 0x26e
1083	#define IA32_MTRR_FIX4K_F8000 0x26f
1084	/** @} */
1085
1086	/** MTRR Default Range. */
1087	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1088
1089	#define MSR_IA32_MC0_CTL 0x400
1090	#define MSR_IA32_MC0_STATUS 0x401
1091
1092	/** Basic VMX information. */
1093	#define MSR_IA32_VMX_BASIC_INFO 0x480
1094	/** Allowed settings for pin-based VM execution controls */
1095	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1096	/** Allowed settings for proc-based VM execution controls */
1097	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1098	/** Allowed settings for the VMX exit controls. */
1099	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1100	/** Allowed settings for the VMX entry controls. */
1101	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1102	/** Misc VMX info. */
1103	#define MSR_IA32_VMX_MISC 0x485
1104	/** Fixed cleared bits in CR0. */
1105	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1106	/** Fixed set bits in CR0. */
1107	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1108	/** Fixed cleared bits in CR4. */
1109	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1110	/** Fixed set bits in CR4. */
1111	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1112	/** Information for enumerating fields in the VMCS. */
1113	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1114	/** Allowed settings for the VM-functions controls. */
1115	#define MSR_IA32_VMX_VMFUNC 0x491
1116	/** Allowed settings for secondary proc-based VM execution controls */
1117	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1118	/** EPT capabilities. */
1119	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1120	/** DS Save Area (R/W). */
1121	#define MSR_IA32_DS_AREA 0x600
1122	/** Running Average Power Limit (RAPL) power units. */
1123	#define MSR_RAPL_POWER_UNIT 0x606
1124	/** X2APIC MSR ranges. */
1125	#define MSR_IA32_X2APIC_START 0x800
1126	#define MSR_IA32_X2APIC_TPR 0x808
1127	#define MSR_IA32_X2APIC_END 0xBFF
1128
1129	/** K6 EFER - Extended Feature Enable Register. */
1130	#define MSR_K6_EFER UINT32_C(0xc0000080)
1131	/** @todo document EFER */
1132	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1133	#define MSR_K6_EFER_SCE RT_BIT(0)
1134	/** Bit 8 - LME - Long mode enabled. (R/W) */
1135	#define MSR_K6_EFER_LME RT_BIT(8)
1136	/** Bit 10 - LMA - Long mode active. (R) */
1137	#define MSR_K6_EFER_LMA RT_BIT(10)
1138	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1139	#define MSR_K6_EFER_NXE RT_BIT(11)
1140	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1141	#define MSR_K6_EFER_SVME RT_BIT(12)
1142	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1143	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1144	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1145	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1146	/** K6 STAR - SYSCALL/RET targets. */
1147	#define MSR_K6_STAR UINT32_C(0xc0000081)
1148	/** Shift value for getting the SYSRET CS and SS value. */
1149	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1150	/** Shift value for getting the SYSCALL CS and SS value. */
1151	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1152	/** Selector mask for use after shifting. */
1153	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1154	/** The mask which give the SYSCALL EIP. */
1155	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1156	/** K6 WHCR - Write Handling Control Register. */
1157	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1158	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1159	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1160	/** K6 PSOR - Processor State Observability Register. */
1161	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1162	/** K6 PFIR - Page Flush/Invalidate Register. */
1163	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1164
1165	/** Performance counter MSRs. (AMD only) */
1166	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1167	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1168	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1169	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1170	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1171	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1172	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1173	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1174
1175	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1176	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1177	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1178	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1179	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1180	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1181	/** K8 FS.base - The 64-bit base FS register. */
1182	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1183	/** K8 GS.base - The 64-bit base GS register. */
1184	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1185	/** K8 KernelGSbase - Used with SWAPGS. */
1186	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1187	/** K8 TSC_AUX - Used with RDTSCP. */
1188	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1189	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1190	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1191	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1192	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1193	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1194	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1195	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1196	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1197	/** North bridge config? See BIOS & Kernel dev guides for
1198	* details. */
1199	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1200
1201	/** Hypertransport interrupt pending register.
1202	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1203	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1204	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1205	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1206
1207	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1208	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1209	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1210	* host state during world switch. */
1211	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1212
1213	/** @} */
1214
1215
1216	/** @name Page Table / Directory / Directory Pointers / L4.
1217	* @{
1218	*/
1219
1220	/** Page table/directory entry as an unsigned integer. */
1221	typedef uint32_t X86PGUINT;
1222	/** Pointer to a page table/directory table entry as an unsigned integer. */
1223	typedef X86PGUINT *PX86PGUINT;
1224	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1225	typedef X86PGUINT const *PCX86PGUINT;
1226
1227	/** Number of entries in a 32-bit PT/PD. */
1228	#define X86_PG_ENTRIES 1024
1229
1230
1231	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1232	typedef uint64_t X86PGPAEUINT;
1233	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1234	typedef X86PGPAEUINT *PX86PGPAEUINT;
1235	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1236	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1237
1238	/** Number of entries in a PAE PT/PD. */
1239	#define X86_PG_PAE_ENTRIES 512
1240	/** Number of entries in a PAE PDPT. */
1241	#define X86_PG_PAE_PDPE_ENTRIES 4
1242
1243	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1244	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1245	/** Number of entries in an AMD64 PDPT.
1246	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1247	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1248
1249	/** The size of a 4KB page. */
1250	#define X86_PAGE_4K_SIZE _4K
1251	/** The page shift of a 4KB page. */
1252	#define X86_PAGE_4K_SHIFT 12
1253	/** The 4KB page offset mask. */
1254	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1255	/** The 4KB page base mask for virtual addresses. */
1256	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1257	/** The 4KB page base mask for virtual addresses - 32bit version. */
1258	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1259
1260	/** The size of a 2MB page. */
1261	#define X86_PAGE_2M_SIZE _2M
1262	/** The page shift of a 2MB page. */
1263	#define X86_PAGE_2M_SHIFT 21
1264	/** The 2MB page offset mask. */
1265	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1266	/** The 2MB page base mask for virtual addresses. */
1267	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1268	/** The 2MB page base mask for virtual addresses - 32bit version. */
1269	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1270
1271	/** The size of a 4MB page. */
1272	#define X86_PAGE_4M_SIZE _4M
1273	/** The page shift of a 4MB page. */
1274	#define X86_PAGE_4M_SHIFT 22
1275	/** The 4MB page offset mask. */
1276	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1277	/** The 4MB page base mask for virtual addresses. */
1278	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1279	/** The 4MB page base mask for virtual addresses - 32bit version. */
1280	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1281
1282
1283
1284	/** @name Page Table Entry
1285	* @{
1286	*/
1287	/** Bit 0 - P - Present bit. */
1288	#define X86_PTE_BIT_P 0
1289	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1290	#define X86_PTE_BIT_RW 1
1291	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1292	#define X86_PTE_BIT_US 2
1293	/** Bit 3 - PWT - Page level write thru bit. */
1294	#define X86_PTE_BIT_PWT 3
1295	/** Bit 4 - PCD - Page level cache disable bit. */
1296	#define X86_PTE_BIT_PCD 4
1297	/** Bit 5 - A - Access bit. */
1298	#define X86_PTE_BIT_A 5
1299	/** Bit 6 - D - Dirty bit. */
1300	#define X86_PTE_BIT_D 6
1301	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1302	#define X86_PTE_BIT_PAT 7
1303	/** Bit 8 - G - Global flag. */
1304	#define X86_PTE_BIT_G 8
1305
1306	/** Bit 0 - P - Present bit mask. */
1307	#define X86_PTE_P RT_BIT(0)
1308	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1309	#define X86_PTE_RW RT_BIT(1)
1310	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1311	#define X86_PTE_US RT_BIT(2)
1312	/** Bit 3 - PWT - Page level write thru bit mask. */
1313	#define X86_PTE_PWT RT_BIT(3)
1314	/** Bit 4 - PCD - Page level cache disable bit mask. */
1315	#define X86_PTE_PCD RT_BIT(4)
1316	/** Bit 5 - A - Access bit mask. */
1317	#define X86_PTE_A RT_BIT(5)
1318	/** Bit 6 - D - Dirty bit mask. */
1319	#define X86_PTE_D RT_BIT(6)
1320	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1321	#define X86_PTE_PAT RT_BIT(7)
1322	/** Bit 8 - G - Global bit mask. */
1323	#define X86_PTE_G RT_BIT(8)
1324
1325	/** Bits 9-11 - - Available for use to system software. */
1326	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1327	/** Bits 12-31 - - Physical Page number of the next level. */
1328	#define X86_PTE_PG_MASK ( 0xfffff000 )
1329
1330	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1331	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1332	/** Bits 63 - NX - PAE/LM - No execution flag. */
1333	#define X86_PTE_PAE_NX RT_BIT_64(63)
1334	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1335	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1336	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1337	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1338	/** No bits - - LM - MBZ bits when NX is active. */
1339	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1340	/** Bits 63 - - LM - MBZ bits when no NX. */
1341	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1342
1343	/**
1344	* Page table entry.
1345	*/
1346	typedef struct X86PTEBITS
1347	{
1348	/** Flags whether(=1) or not the page is present. */
1349	unsigned u1Present : 1;
1350	/** Read(=0) / Write(=1) flag. */
1351	unsigned u1Write : 1;
1352	/** User(=1) / Supervisor (=0) flag. */
1353	unsigned u1User : 1;
1354	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1355	unsigned u1WriteThru : 1;
1356	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1357	unsigned u1CacheDisable : 1;
1358	/** Accessed flag.
1359	* Indicates that the page have been read or written to. */
1360	unsigned u1Accessed : 1;
1361	/** Dirty flag.
1362	* Indicates that the page has been written to. */
1363	unsigned u1Dirty : 1;
1364	/** Reserved / If PAT enabled, bit 2 of the index. */
1365	unsigned u1PAT : 1;
1366	/** Global flag. (Ignored in all but final level.) */
1367	unsigned u1Global : 1;
1368	/** Available for use to system software. */
1369	unsigned u3Available : 3;
1370	/** Physical Page number of the next level. */
1371	unsigned u20PageNo : 20;
1372	} X86PTEBITS;
1373	/** Pointer to a page table entry. */
1374	typedef X86PTEBITS *PX86PTEBITS;
1375	/** Pointer to a const page table entry. */
1376	typedef const X86PTEBITS *PCX86PTEBITS;
1377
1378	/**
1379	* Page table entry.
1380	*/
1381	typedef union X86PTE
1382	{
1383	/** Unsigned integer view */
1384	X86PGUINT u;
1385	/** Bit field view. */
1386	X86PTEBITS n;
1387	/** 32-bit view. */
1388	uint32_t au32[1];
1389	/** 16-bit view. */
1390	uint16_t au16[2];
1391	/** 8-bit view. */
1392	uint8_t au8[4];
1393	} X86PTE;
1394	/** Pointer to a page table entry. */
1395	typedef X86PTE *PX86PTE;
1396	/** Pointer to a const page table entry. */
1397	typedef const X86PTE *PCX86PTE;
1398
1399
1400	/**
1401	* PAE page table entry.
1402	*/
1403	typedef struct X86PTEPAEBITS
1404	{
1405	/** Flags whether(=1) or not the page is present. */
1406	uint32_t u1Present : 1;
1407	/** Read(=0) / Write(=1) flag. */
1408	uint32_t u1Write : 1;
1409	/** User(=1) / Supervisor(=0) flag. */
1410	uint32_t u1User : 1;
1411	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1412	uint32_t u1WriteThru : 1;
1413	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1414	uint32_t u1CacheDisable : 1;
1415	/** Accessed flag.
1416	* Indicates that the page have been read or written to. */
1417	uint32_t u1Accessed : 1;
1418	/** Dirty flag.
1419	* Indicates that the page has been written to. */
1420	uint32_t u1Dirty : 1;
1421	/** Reserved / If PAT enabled, bit 2 of the index. */
1422	uint32_t u1PAT : 1;
1423	/** Global flag. (Ignored in all but final level.) */
1424	uint32_t u1Global : 1;
1425	/** Available for use to system software. */
1426	uint32_t u3Available : 3;
1427	/** Physical Page number of the next level - Low Part. Don't use this. */
1428	uint32_t u20PageNoLow : 20;
1429	/** Physical Page number of the next level - High Part. Don't use this. */
1430	uint32_t u20PageNoHigh : 20;
1431	/** MBZ bits */
1432	uint32_t u11Reserved : 11;
1433	/** No Execute flag. */
1434	uint32_t u1NoExecute : 1;
1435	} X86PTEPAEBITS;
1436	/** Pointer to a page table entry. */
1437	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1438	/** Pointer to a page table entry. */
1439	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1440
1441	/**
1442	* PAE Page table entry.
1443	*/
1444	typedef union X86PTEPAE
1445	{
1446	/** Unsigned integer view */
1447	X86PGPAEUINT u;
1448	/** Bit field view. */
1449	X86PTEPAEBITS n;
1450	/** 32-bit view. */
1451	uint32_t au32[2];
1452	/** 16-bit view. */
1453	uint16_t au16[4];
1454	/** 8-bit view. */
1455	uint8_t au8[8];
1456	} X86PTEPAE;
1457	/** Pointer to a PAE page table entry. */
1458	typedef X86PTEPAE *PX86PTEPAE;
1459	/** Pointer to a const PAE page table entry. */
1460	typedef const X86PTEPAE *PCX86PTEPAE;
1461	/** @} */
1462
1463	/**
1464	* Page table.
1465	*/
1466	typedef struct X86PT
1467	{
1468	/** PTE Array. */
1469	X86PTE a[X86_PG_ENTRIES];
1470	} X86PT;
1471	/** Pointer to a page table. */
1472	typedef X86PT *PX86PT;
1473	/** Pointer to a const page table. */
1474	typedef const X86PT *PCX86PT;
1475
1476	/** The page shift to get the PT index. */
1477	#define X86_PT_SHIFT 12
1478	/** The PT index mask (apply to a shifted page address). */
1479	#define X86_PT_MASK 0x3ff
1480
1481
1482	/**
1483	* Page directory.
1484	*/
1485	typedef struct X86PTPAE
1486	{
1487	/** PTE Array. */
1488	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1489	} X86PTPAE;
1490	/** Pointer to a page table. */
1491	typedef X86PTPAE *PX86PTPAE;
1492	/** Pointer to a const page table. */
1493	typedef const X86PTPAE *PCX86PTPAE;
1494
1495	/** The page shift to get the PA PTE index. */
1496	#define X86_PT_PAE_SHIFT 12
1497	/** The PAE PT index mask (apply to a shifted page address). */
1498	#define X86_PT_PAE_MASK 0x1ff
1499
1500
1501	/** @name 4KB Page Directory Entry
1502	* @{
1503	*/
1504	/** Bit 0 - P - Present bit. */
1505	#define X86_PDE_P RT_BIT(0)
1506	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1507	#define X86_PDE_RW RT_BIT(1)
1508	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1509	#define X86_PDE_US RT_BIT(2)
1510	/** Bit 3 - PWT - Page level write thru bit. */
1511	#define X86_PDE_PWT RT_BIT(3)
1512	/** Bit 4 - PCD - Page level cache disable bit. */
1513	#define X86_PDE_PCD RT_BIT(4)
1514	/** Bit 5 - A - Access bit. */
1515	#define X86_PDE_A RT_BIT(5)
1516	/** Bit 7 - PS - Page size attribute.
1517	* Clear mean 4KB pages, set means large pages (2/4MB). */
1518	#define X86_PDE_PS RT_BIT(7)
1519	/** Bits 9-11 - - Available for use to system software. */
1520	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1521	/** Bits 12-31 - - Physical Page number of the next level. */
1522	#define X86_PDE_PG_MASK ( 0xfffff000 )
1523
1524	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1525	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1526	/** Bits 63 - NX - PAE/LM - No execution flag. */
1527	#define X86_PDE_PAE_NX RT_BIT_64(63)
1528	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1529	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1530	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1531	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1532	/** Bit 7 - - LM - MBZ bits when NX is active. */
1533	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1534	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1535	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1536
1537	/**
1538	* Page directory entry.
1539	*/
1540	typedef struct X86PDEBITS
1541	{
1542	/** Flags whether(=1) or not the page is present. */
1543	unsigned u1Present : 1;
1544	/** Read(=0) / Write(=1) flag. */
1545	unsigned u1Write : 1;
1546	/** User(=1) / Supervisor (=0) flag. */
1547	unsigned u1User : 1;
1548	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1549	unsigned u1WriteThru : 1;
1550	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1551	unsigned u1CacheDisable : 1;
1552	/** Accessed flag.
1553	* Indicates that the page has been read or written to. */
1554	unsigned u1Accessed : 1;
1555	/** Reserved / Ignored (dirty bit). */
1556	unsigned u1Reserved0 : 1;
1557	/** Size bit if PSE is enabled - in any event it's 0. */
1558	unsigned u1Size : 1;
1559	/** Reserved / Ignored (global bit). */
1560	unsigned u1Reserved1 : 1;
1561	/** Available for use to system software. */
1562	unsigned u3Available : 3;
1563	/** Physical Page number of the next level. */
1564	unsigned u20PageNo : 20;
1565	} X86PDEBITS;
1566	/** Pointer to a page directory entry. */
1567	typedef X86PDEBITS *PX86PDEBITS;
1568	/** Pointer to a const page directory entry. */
1569	typedef const X86PDEBITS *PCX86PDEBITS;
1570
1571
1572	/**
1573	* PAE page directory entry.
1574	*/
1575	typedef struct X86PDEPAEBITS
1576	{
1577	/** Flags whether(=1) or not the page is present. */
1578	uint32_t u1Present : 1;
1579	/** Read(=0) / Write(=1) flag. */
1580	uint32_t u1Write : 1;
1581	/** User(=1) / Supervisor (=0) flag. */
1582	uint32_t u1User : 1;
1583	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1584	uint32_t u1WriteThru : 1;
1585	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1586	uint32_t u1CacheDisable : 1;
1587	/** Accessed flag.
1588	* Indicates that the page has been read or written to. */
1589	uint32_t u1Accessed : 1;
1590	/** Reserved / Ignored (dirty bit). */
1591	uint32_t u1Reserved0 : 1;
1592	/** Size bit if PSE is enabled - in any event it's 0. */
1593	uint32_t u1Size : 1;
1594	/** Reserved / Ignored (global bit). / */
1595	uint32_t u1Reserved1 : 1;
1596	/** Available for use to system software. */
1597	uint32_t u3Available : 3;
1598	/** Physical Page number of the next level - Low Part. Don't use! */
1599	uint32_t u20PageNoLow : 20;
1600	/** Physical Page number of the next level - High Part. Don't use! */
1601	uint32_t u20PageNoHigh : 20;
1602	/** MBZ bits */
1603	uint32_t u11Reserved : 11;
1604	/** No Execute flag. */
1605	uint32_t u1NoExecute : 1;
1606	} X86PDEPAEBITS;
1607	/** Pointer to a page directory entry. */
1608	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1609	/** Pointer to a const page directory entry. */
1610	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1611
1612	/** @} */
1613
1614
1615	/** @name 2/4MB Page Directory Entry
1616	* @{
1617	*/
1618	/** Bit 0 - P - Present bit. */
1619	#define X86_PDE4M_P RT_BIT(0)
1620	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1621	#define X86_PDE4M_RW RT_BIT(1)
1622	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1623	#define X86_PDE4M_US RT_BIT(2)
1624	/** Bit 3 - PWT - Page level write thru bit. */
1625	#define X86_PDE4M_PWT RT_BIT(3)
1626	/** Bit 4 - PCD - Page level cache disable bit. */
1627	#define X86_PDE4M_PCD RT_BIT(4)
1628	/** Bit 5 - A - Access bit. */
1629	#define X86_PDE4M_A RT_BIT(5)
1630	/** Bit 6 - D - Dirty bit. */
1631	#define X86_PDE4M_D RT_BIT(6)
1632	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1633	#define X86_PDE4M_PS RT_BIT(7)
1634	/** Bit 8 - G - Global flag. */
1635	#define X86_PDE4M_G RT_BIT(8)
1636	/** Bits 9-11 - AVL - Available for use to system software. */
1637	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1638	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1639	#define X86_PDE4M_PAT RT_BIT(12)
1640	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1641	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1642	/** Bits 22-31 - - Physical Page number. */
1643	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1644	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1645	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1646	/** The number of bits to the high part of the page number. */
1647	#define X86_PDE4M_PG_HIGH_SHIFT 19
1648	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1649	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1650
1651	/** Bits 21-51 - - PAE/LM - Physical Page number.
1652	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1653	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1654	/** Bits 63 - NX - PAE/LM - No execution flag. */
1655	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1656	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1657	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1658	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1659	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1660	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1661	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1662	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1663	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1664
1665	/**
1666	* 4MB page directory entry.
1667	*/
1668	typedef struct X86PDE4MBITS
1669	{
1670	/** Flags whether(=1) or not the page is present. */
1671	unsigned u1Present : 1;
1672	/** Read(=0) / Write(=1) flag. */
1673	unsigned u1Write : 1;
1674	/** User(=1) / Supervisor (=0) flag. */
1675	unsigned u1User : 1;
1676	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1677	unsigned u1WriteThru : 1;
1678	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1679	unsigned u1CacheDisable : 1;
1680	/** Accessed flag.
1681	* Indicates that the page have been read or written to. */
1682	unsigned u1Accessed : 1;
1683	/** Dirty flag.
1684	* Indicates that the page has been written to. */
1685	unsigned u1Dirty : 1;
1686	/** Page size flag - always 1 for 4MB entries. */
1687	unsigned u1Size : 1;
1688	/** Global flag. */
1689	unsigned u1Global : 1;
1690	/** Available for use to system software. */
1691	unsigned u3Available : 3;
1692	/** Reserved / If PAT enabled, bit 2 of the index. */
1693	unsigned u1PAT : 1;
1694	/** Bits 32-39 of the page number on AMD64.
1695	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1696	unsigned u8PageNoHigh : 8;
1697	/** Reserved. */
1698	unsigned u1Reserved : 1;
1699	/** Physical Page number of the page. */
1700	unsigned u10PageNo : 10;
1701	} X86PDE4MBITS;
1702	/** Pointer to a page table entry. */
1703	typedef X86PDE4MBITS *PX86PDE4MBITS;
1704	/** Pointer to a const page table entry. */
1705	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1706
1707
1708	/**
1709	* 2MB PAE page directory entry.
1710	*/
1711	typedef struct X86PDE2MPAEBITS
1712	{
1713	/** Flags whether(=1) or not the page is present. */
1714	uint32_t u1Present : 1;
1715	/** Read(=0) / Write(=1) flag. */
1716	uint32_t u1Write : 1;
1717	/** User(=1) / Supervisor(=0) flag. */
1718	uint32_t u1User : 1;
1719	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1720	uint32_t u1WriteThru : 1;
1721	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1722	uint32_t u1CacheDisable : 1;
1723	/** Accessed flag.
1724	* Indicates that the page have been read or written to. */
1725	uint32_t u1Accessed : 1;
1726	/** Dirty flag.
1727	* Indicates that the page has been written to. */
1728	uint32_t u1Dirty : 1;
1729	/** Page size flag - always 1 for 2MB entries. */
1730	uint32_t u1Size : 1;
1731	/** Global flag. */
1732	uint32_t u1Global : 1;
1733	/** Available for use to system software. */
1734	uint32_t u3Available : 3;
1735	/** Reserved / If PAT enabled, bit 2 of the index. */
1736	uint32_t u1PAT : 1;
1737	/** Reserved. */
1738	uint32_t u9Reserved : 9;
1739	/** Physical Page number of the next level - Low part. Don't use! */
1740	uint32_t u10PageNoLow : 10;
1741	/** Physical Page number of the next level - High part. Don't use! */
1742	uint32_t u20PageNoHigh : 20;
1743	/** MBZ bits */
1744	uint32_t u11Reserved : 11;
1745	/** No Execute flag. */
1746	uint32_t u1NoExecute : 1;
1747	} X86PDE2MPAEBITS;
1748	/** Pointer to a 2MB PAE page table entry. */
1749	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1750	/** Pointer to a 2MB PAE page table entry. */
1751	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1752
1753	/** @} */
1754
1755	/**
1756	* Page directory entry.
1757	*/
1758	typedef union X86PDE
1759	{
1760	/** Unsigned integer view. */
1761	X86PGUINT u;
1762	/** Normal view. */
1763	X86PDEBITS n;
1764	/** 4MB view (big). */
1765	X86PDE4MBITS b;
1766	/** 8 bit unsigned integer view. */
1767	uint8_t au8[4];
1768	/** 16 bit unsigned integer view. */
1769	uint16_t au16[2];
1770	/** 32 bit unsigned integer view. */
1771	uint32_t au32[1];
1772	} X86PDE;
1773	/** Pointer to a page directory entry. */
1774	typedef X86PDE *PX86PDE;
1775	/** Pointer to a const page directory entry. */
1776	typedef const X86PDE *PCX86PDE;
1777
1778	/**
1779	* PAE page directory entry.
1780	*/
1781	typedef union X86PDEPAE
1782	{
1783	/** Unsigned integer view. */
1784	X86PGPAEUINT u;
1785	/** Normal view. */
1786	X86PDEPAEBITS n;
1787	/** 2MB page view (big). */
1788	X86PDE2MPAEBITS b;
1789	/** 8 bit unsigned integer view. */
1790	uint8_t au8[8];
1791	/** 16 bit unsigned integer view. */
1792	uint16_t au16[4];
1793	/** 32 bit unsigned integer view. */
1794	uint32_t au32[2];
1795	} X86PDEPAE;
1796	/** Pointer to a page directory entry. */
1797	typedef X86PDEPAE *PX86PDEPAE;
1798	/** Pointer to a const page directory entry. */
1799	typedef const X86PDEPAE *PCX86PDEPAE;
1800
1801	/**
1802	* Page directory.
1803	*/
1804	typedef struct X86PD
1805	{
1806	/** PDE Array. */
1807	X86PDE a[X86_PG_ENTRIES];
1808	} X86PD;
1809	/** Pointer to a page directory. */
1810	typedef X86PD *PX86PD;
1811	/** Pointer to a const page directory. */
1812	typedef const X86PD *PCX86PD;
1813
1814	/** The page shift to get the PD index. */
1815	#define X86_PD_SHIFT 22
1816	/** The PD index mask (apply to a shifted page address). */
1817	#define X86_PD_MASK 0x3ff
1818
1819
1820	/**
1821	* PAE page directory.
1822	*/
1823	typedef struct X86PDPAE
1824	{
1825	/** PDE Array. */
1826	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1827	} X86PDPAE;
1828	/** Pointer to a PAE page directory. */
1829	typedef X86PDPAE *PX86PDPAE;
1830	/** Pointer to a const PAE page directory. */
1831	typedef const X86PDPAE *PCX86PDPAE;
1832
1833	/** The page shift to get the PAE PD index. */
1834	#define X86_PD_PAE_SHIFT 21
1835	/** The PAE PD index mask (apply to a shifted page address). */
1836	#define X86_PD_PAE_MASK 0x1ff
1837
1838
1839	/** @name Page Directory Pointer Table Entry (PAE)
1840	* @{
1841	*/
1842	/** Bit 0 - P - Present bit. */
1843	#define X86_PDPE_P RT_BIT(0)
1844	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1845	#define X86_PDPE_RW RT_BIT(1)
1846	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1847	#define X86_PDPE_US RT_BIT(2)
1848	/** Bit 3 - PWT - Page level write thru bit. */
1849	#define X86_PDPE_PWT RT_BIT(3)
1850	/** Bit 4 - PCD - Page level cache disable bit. */
1851	#define X86_PDPE_PCD RT_BIT(4)
1852	/** Bit 5 - A - Access bit. Long Mode only. */
1853	#define X86_PDPE_A RT_BIT(5)
1854	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1855	#define X86_PDPE_LM_PS RT_BIT(7)
1856	/** Bits 9-11 - - Available for use to system software. */
1857	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1858	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1859	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1860	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1861	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1862	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1863	#define X86_PDPE_LM_NX RT_BIT_64(63)
1864	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1865	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1866	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1867	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1868	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1869	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1870	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1871	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1872
1873
1874	/**
1875	* Page directory pointer table entry.
1876	*/
1877	typedef struct X86PDPEBITS
1878	{
1879	/** Flags whether(=1) or not the page is present. */
1880	uint32_t u1Present : 1;
1881	/** Chunk of reserved bits. */
1882	uint32_t u2Reserved : 2;
1883	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1884	uint32_t u1WriteThru : 1;
1885	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1886	uint32_t u1CacheDisable : 1;
1887	/** Chunk of reserved bits. */
1888	uint32_t u4Reserved : 4;
1889	/** Available for use to system software. */
1890	uint32_t u3Available : 3;
1891	/** Physical Page number of the next level - Low Part. Don't use! */
1892	uint32_t u20PageNoLow : 20;
1893	/** Physical Page number of the next level - High Part. Don't use! */
1894	uint32_t u20PageNoHigh : 20;
1895	/** MBZ bits */
1896	uint32_t u12Reserved : 12;
1897	} X86PDPEBITS;
1898	/** Pointer to a page directory pointer table entry. */
1899	typedef X86PDPEBITS *PX86PTPEBITS;
1900	/** Pointer to a const page directory pointer table entry. */
1901	typedef const X86PDPEBITS *PCX86PTPEBITS;
1902
1903	/**
1904	* Page directory pointer table entry. AMD64 version
1905	*/
1906	typedef struct X86PDPEAMD64BITS
1907	{
1908	/** Flags whether(=1) or not the page is present. */
1909	uint32_t u1Present : 1;
1910	/** Read(=0) / Write(=1) flag. */
1911	uint32_t u1Write : 1;
1912	/** User(=1) / Supervisor (=0) flag. */
1913	uint32_t u1User : 1;
1914	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1915	uint32_t u1WriteThru : 1;
1916	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1917	uint32_t u1CacheDisable : 1;
1918	/** Accessed flag.
1919	* Indicates that the page have been read or written to. */
1920	uint32_t u1Accessed : 1;
1921	/** Chunk of reserved bits. */
1922	uint32_t u3Reserved : 3;
1923	/** Available for use to system software. */
1924	uint32_t u3Available : 3;
1925	/** Physical Page number of the next level - Low Part. Don't use! */
1926	uint32_t u20PageNoLow : 20;
1927	/** Physical Page number of the next level - High Part. Don't use! */
1928	uint32_t u20PageNoHigh : 20;
1929	/** MBZ bits */
1930	uint32_t u11Reserved : 11;
1931	/** No Execute flag. */
1932	uint32_t u1NoExecute : 1;
1933	} X86PDPEAMD64BITS;
1934	/** Pointer to a page directory pointer table entry. */
1935	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1936	/** Pointer to a const page directory pointer table entry. */
1937	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1938
1939	/**
1940	* Page directory pointer table entry.
1941	*/
1942	typedef union X86PDPE
1943	{
1944	/** Unsigned integer view. */
1945	X86PGPAEUINT u;
1946	/** Normal view. */
1947	X86PDPEBITS n;
1948	/** AMD64 view. */
1949	X86PDPEAMD64BITS lm;
1950	/** 8 bit unsigned integer view. */
1951	uint8_t au8[8];
1952	/** 16 bit unsigned integer view. */
1953	uint16_t au16[4];
1954	/** 32 bit unsigned integer view. */
1955	uint32_t au32[2];
1956	} X86PDPE;
1957	/** Pointer to a page directory pointer table entry. */
1958	typedef X86PDPE *PX86PDPE;
1959	/** Pointer to a const page directory pointer table entry. */
1960	typedef const X86PDPE *PCX86PDPE;
1961
1962
1963	/**
1964	* Page directory pointer table.
1965	*/
1966	typedef struct X86PDPT
1967	{
1968	/** PDE Array. */
1969	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1970	} X86PDPT;
1971	/** Pointer to a page directory pointer table. */
1972	typedef X86PDPT *PX86PDPT;
1973	/** Pointer to a const page directory pointer table. */
1974	typedef const X86PDPT *PCX86PDPT;
1975
1976	/** The page shift to get the PDPT index. */
1977	#define X86_PDPT_SHIFT 30
1978	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1979	#define X86_PDPT_MASK_PAE 0x3
1980	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1981	#define X86_PDPT_MASK_AMD64 0x1ff
1982
1983	/** @} */
1984
1985
1986	/** @name Page Map Level-4 Entry (Long Mode PAE)
1987	* @{
1988	*/
1989	/** Bit 0 - P - Present bit. */
1990	#define X86_PML4E_P RT_BIT(0)
1991	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1992	#define X86_PML4E_RW RT_BIT(1)
1993	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1994	#define X86_PML4E_US RT_BIT(2)
1995	/** Bit 3 - PWT - Page level write thru bit. */
1996	#define X86_PML4E_PWT RT_BIT(3)
1997	/** Bit 4 - PCD - Page level cache disable bit. */
1998	#define X86_PML4E_PCD RT_BIT(4)
1999	/** Bit 5 - A - Access bit. */
2000	#define X86_PML4E_A RT_BIT(5)
2001	/** Bits 9-11 - - Available for use to system software. */
2002	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2003	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2004	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2005	/** Bits 8, 7 - - MBZ bits when NX is active. */
2006	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2007	/** Bits 63, 7 - - MBZ bits when no NX. */
2008	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2009	/** Bits 63 - NX - PAE - No execution flag. */
2010	#define X86_PML4E_NX RT_BIT_64(63)
2011
2012	/**
2013	* Page Map Level-4 Entry
2014	*/
2015	typedef struct X86PML4EBITS
2016	{
2017	/** Flags whether(=1) or not the page is present. */
2018	uint32_t u1Present : 1;
2019	/** Read(=0) / Write(=1) flag. */
2020	uint32_t u1Write : 1;
2021	/** User(=1) / Supervisor (=0) flag. */
2022	uint32_t u1User : 1;
2023	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2024	uint32_t u1WriteThru : 1;
2025	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2026	uint32_t u1CacheDisable : 1;
2027	/** Accessed flag.
2028	* Indicates that the page have been read or written to. */
2029	uint32_t u1Accessed : 1;
2030	/** Chunk of reserved bits. */
2031	uint32_t u3Reserved : 3;
2032	/** Available for use to system software. */
2033	uint32_t u3Available : 3;
2034	/** Physical Page number of the next level - Low Part. Don't use! */
2035	uint32_t u20PageNoLow : 20;
2036	/** Physical Page number of the next level - High Part. Don't use! */
2037	uint32_t u20PageNoHigh : 20;
2038	/** MBZ bits */
2039	uint32_t u11Reserved : 11;
2040	/** No Execute flag. */
2041	uint32_t u1NoExecute : 1;
2042	} X86PML4EBITS;
2043	/** Pointer to a page map level-4 entry. */
2044	typedef X86PML4EBITS *PX86PML4EBITS;
2045	/** Pointer to a const page map level-4 entry. */
2046	typedef const X86PML4EBITS *PCX86PML4EBITS;
2047
2048	/**
2049	* Page Map Level-4 Entry.
2050	*/
2051	typedef union X86PML4E
2052	{
2053	/** Unsigned integer view. */
2054	X86PGPAEUINT u;
2055	/** Normal view. */
2056	X86PML4EBITS n;
2057	/** 8 bit unsigned integer view. */
2058	uint8_t au8[8];
2059	/** 16 bit unsigned integer view. */
2060	uint16_t au16[4];
2061	/** 32 bit unsigned integer view. */
2062	uint32_t au32[2];
2063	} X86PML4E;
2064	/** Pointer to a page map level-4 entry. */
2065	typedef X86PML4E *PX86PML4E;
2066	/** Pointer to a const page map level-4 entry. */
2067	typedef const X86PML4E *PCX86PML4E;
2068
2069
2070	/**
2071	* Page Map Level-4.
2072	*/
2073	typedef struct X86PML4
2074	{
2075	/** PDE Array. */
2076	X86PML4E a[X86_PG_PAE_ENTRIES];
2077	} X86PML4;
2078	/** Pointer to a page map level-4. */
2079	typedef X86PML4 *PX86PML4;
2080	/** Pointer to a const page map level-4. */
2081	typedef const X86PML4 *PCX86PML4;
2082
2083	/** The page shift to get the PML4 index. */
2084	#define X86_PML4_SHIFT 39
2085	/** The PML4 index mask (apply to a shifted page address). */
2086	#define X86_PML4_MASK 0x1ff
2087
2088	/** @} */
2089
2090	/** @} */
2091
2092
2093	/**
2094	* 80-bit MMX/FPU register type.
2095	*/
2096	typedef struct X86FPUMMX
2097	{
2098	uint8_t reg[10];
2099	} X86FPUMMX;
2100	/** Pointer to a 80-bit MMX/FPU register type. */
2101	typedef X86FPUMMX *PX86FPUMMX;
2102	/** Pointer to a const 80-bit MMX/FPU register type. */
2103	typedef const X86FPUMMX *PCX86FPUMMX;
2104
2105	/**
2106	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2107	* @todo verify this...
2108	*/
2109	#pragma pack(1)
2110	typedef struct X86FPUSTATE
2111	{
2112	/** 0x00 - Control word. */
2113	uint16_t FCW;
2114	/** 0x02 - Alignment word */
2115	uint16_t Dummy1;
2116	/** 0x04 - Status word. */
2117	uint16_t FSW;
2118	/** 0x06 - Alignment word */
2119	uint16_t Dummy2;
2120	/** 0x08 - Tag word */
2121	uint16_t FTW;
2122	/** 0x0a - Alignment word */
2123	uint16_t Dummy3;
2124
2125	/** 0x0c - Instruction pointer. */
2126	uint32_t FPUIP;
2127	/** 0x10 - Code selector. */
2128	uint16_t CS;
2129	/** 0x12 - Opcode. */
2130	uint16_t FOP;
2131	/** 0x14 - FOO. */
2132	uint32_t FPUOO;
2133	/** 0x18 - FOS. */
2134	uint32_t FPUOS;
2135	/** 0x1c */
2136	union
2137	{
2138	/** MMX view. */
2139	uint64_t mmx;
2140	/** FPU view - todo. */
2141	X86FPUMMX fpu;
2142	/** Extended precision floating point view. */
2143	RTFLOAT80U r80;
2144	/** Extended precision floating point view v2. */
2145	RTFLOAT80U2 r80Ex;
2146	/** 8-bit view. */
2147	uint8_t au8[16];
2148	/** 16-bit view. */
2149	uint16_t au16[8];
2150	/** 32-bit view. */
2151	uint32_t au32[4];
2152	/** 64-bit view. */
2153	uint64_t au64[2];
2154	/** 128-bit view. (yeah, very helpful) */
2155	uint128_t au128[1];
2156	} regs[8];
2157	} X86FPUSTATE;
2158	#pragma pack()
2159	/** Pointer to a FPU state. */
2160	typedef X86FPUSTATE *PX86FPUSTATE;
2161	/** Pointer to a const FPU state. */
2162	typedef const X86FPUSTATE *PCX86FPUSTATE;
2163
2164	/**
2165	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2166	*/
2167	#pragma pack(1)
2168	typedef struct X86FXSTATE
2169	{
2170	/** 0x00 - Control word. */
2171	uint16_t FCW;
2172	/** 0x02 - Status word. */
2173	uint16_t FSW;
2174	/** 0x04 - Tag word. (The upper byte is always zero.) */
2175	uint16_t FTW;
2176	/** 0x06 - Opcode. */
2177	uint16_t FOP;
2178	/** 0x08 - Instruction pointer. */
2179	uint32_t FPUIP;
2180	/** 0x0c - Code selector. */
2181	uint16_t CS;
2182	uint16_t Rsrvd1;
2183	/** 0x10 - Data pointer. */
2184	uint32_t FPUDP;
2185	/** 0x14 - Data segment */
2186	uint16_t DS;
2187	/** 0x16 */
2188	uint16_t Rsrvd2;
2189	/** 0x18 */
2190	uint32_t MXCSR;
2191	/** 0x1c */
2192	uint32_t MXCSR_MASK;
2193	/** 0x20 */
2194	union
2195	{
2196	/** MMX view. */
2197	uint64_t mmx;
2198	/** FPU view - todo. */
2199	X86FPUMMX fpu;
2200	/** Extended precision floating point view. */
2201	RTFLOAT80U r80;
2202	/** Extended precision floating point view v2 */
2203	RTFLOAT80U2 r80Ex;
2204	/** 8-bit view. */
2205	uint8_t au8[16];
2206	/** 16-bit view. */
2207	uint16_t au16[8];
2208	/** 32-bit view. */
2209	uint32_t au32[4];
2210	/** 64-bit view. */
2211	uint64_t au64[2];
2212	/** 128-bit view. (yeah, very helpful) */
2213	uint128_t au128[1];
2214	} aRegs[8];
2215	/* - offset 160 - */
2216	union
2217	{
2218	/** XMM Register view . /
2219	uint128_t xmm;
2220	/** 8-bit view. */
2221	uint8_t au8[16];
2222	/** 16-bit view. */
2223	uint16_t au16[8];
2224	/** 32-bit view. */
2225	uint32_t au32[4];
2226	/** 64-bit view. */
2227	uint64_t au64[2];
2228	/** 128-bit view. (yeah, very helpful) */
2229	uint128_t au128[1];
2230	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2231	/* - offset 416 - */
2232	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2233	} X86FXSTATE;
2234	#pragma pack()
2235	/** Pointer to a FPU Extended state. */
2236	typedef X86FXSTATE *PX86FXSTATE;
2237	/** Pointer to a const FPU Extended state. */
2238	typedef const X86FXSTATE *PCX86FXSTATE;
2239
2240	/** @name FPU status word flags.
2241	* @{ */
2242	/** Exception Flag: Invalid operation. */
2243	#define X86_FSW_IE RT_BIT(0)
2244	/** Exception Flag: Denormalized operand. */
2245	#define X86_FSW_DE RT_BIT(1)
2246	/** Exception Flag: Zero divide. */
2247	#define X86_FSW_ZE RT_BIT(2)
2248	/** Exception Flag: Overflow. */
2249	#define X86_FSW_OE RT_BIT(3)
2250	/** Exception Flag: Underflow. */
2251	#define X86_FSW_UE RT_BIT(4)
2252	/** Exception Flag: Precision. */
2253	#define X86_FSW_PE RT_BIT(5)
2254	/** Stack fault. */
2255	#define X86_FSW_SF RT_BIT(6)
2256	/** Error summary status. */
2257	#define X86_FSW_ES RT_BIT(7)
2258	/** Mask of exceptions flags, excluding the summary bit. */
2259	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2260	/** Mask of exceptions flags, including the summary bit. */
2261	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2262	/** Condition code 0. */
2263	#define X86_FSW_C0 RT_BIT(8)
2264	/** Condition code 1. */
2265	#define X86_FSW_C1 RT_BIT(9)
2266	/** Condition code 2. */
2267	#define X86_FSW_C2 RT_BIT(10)
2268	/** Top of the stack mask. */
2269	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2270	/** TOP shift value. */
2271	#define X86_FSW_TOP_SHIFT 11
2272	/** Mask for getting TOP value after shifting it right. */
2273	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2274	/** Get the TOP value. */
2275	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2276	/** Condition code 3. */
2277	#define X86_FSW_C3 RT_BIT(14)
2278	/** Mask of exceptions flags, including the summary bit. */
2279	#define X86_FSW_C_MASK UINT16_C(0x4700)
2280	/** FPU busy. */
2281	#define X86_FSW_B RT_BIT(15)
2282	/** @} */
2283
2284
2285	/** @name FPU control word flags.
2286	* @{ */
2287	/** Exception Mask: Invalid operation. */
2288	#define X86_FCW_IM RT_BIT(0)
2289	/** Exception Mask: Denormalized operand. */
2290	#define X86_FCW_DM RT_BIT(1)
2291	/** Exception Mask: Zero divide. */
2292	#define X86_FCW_ZM RT_BIT(2)
2293	/** Exception Mask: Overflow. */
2294	#define X86_FCW_OM RT_BIT(3)
2295	/** Exception Mask: Underflow. */
2296	#define X86_FCW_UM RT_BIT(4)
2297	/** Exception Mask: Precision. */
2298	#define X86_FCW_PM RT_BIT(5)
2299	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2300	* @remarks This includes reserved bit 6. */
2301	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2302	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2303	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2304	/** Precision control mask. */
2305	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2306	/** Precision control: 24-bit. */
2307	#define X86_FCW_PC_24 UINT16_C(0x0000)
2308	/** Precision control: Reserved. */
2309	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2310	/** Precision control: 53-bit. */
2311	#define X86_FCW_PC_53 UINT16_C(0x0200)
2312	/** Precision control: 64-bit. */
2313	#define X86_FCW_PC_64 UINT16_C(0x0300)
2314	/** Rounding control mask. */
2315	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2316	/** Rounding control: To nearest. */
2317	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2318	/** Rounding control: Down. */
2319	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2320	/** Rounding control: Up. */
2321	#define X86_FCW_RC_UP UINT16_C(0x0800)
2322	/** Rounding control: Towards zero. */
2323	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2324	/** Bits which should be zero, apparently. */
2325	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2326	/** @} */
2327
2328	/** @name SSE MXCSR
2329	* @{ */
2330	/** Exception Flag: Invalid operation. */
2331	#define X86_MSXCR_IE RT_BIT(0)
2332	/** Exception Flag: Denormalized operand. */
2333	#define X86_MSXCR_DE RT_BIT(1)
2334	/** Exception Flag: Zero divide. */
2335	#define X86_MSXCR_ZE RT_BIT(2)
2336	/** Exception Flag: Overflow. */
2337	#define X86_MSXCR_OE RT_BIT(3)
2338	/** Exception Flag: Underflow. */
2339	#define X86_MSXCR_UE RT_BIT(4)
2340	/** Exception Flag: Precision. */
2341	#define X86_MSXCR_PE RT_BIT(5)
2342
2343	/** Denormals are zero. */
2344	#define X86_MSXCR_DAZ RT_BIT(6)
2345
2346	/** Exception Mask: Invalid operation. */
2347	#define X86_MSXCR_IM RT_BIT(7)
2348	/** Exception Mask: Denormalized operand. */
2349	#define X86_MSXCR_DM RT_BIT(8)
2350	/** Exception Mask: Zero divide. */
2351	#define X86_MSXCR_ZM RT_BIT(9)
2352	/** Exception Mask: Overflow. */
2353	#define X86_MSXCR_OM RT_BIT(10)
2354	/** Exception Mask: Underflow. */
2355	#define X86_MSXCR_UM RT_BIT(11)
2356	/** Exception Mask: Precision. */
2357	#define X86_MSXCR_PM RT_BIT(12)
2358
2359	/** Rounding control mask. */
2360	#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2361	/** Rounding control: To nearest. */
2362	#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2363	/** Rounding control: Down. */
2364	#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2365	/** Rounding control: Up. */
2366	#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2367	/** Rounding control: Towards zero. */
2368	#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2369
2370	/** Flush-to-zero for masked underflow. */
2371	#define X86_MSXCR_FZ RT_BIT(15)
2372
2373	/** Misaligned Exception Mask. */
2374	#define X86_MSXCR_MM RT_BIT(16)
2375	/** @} */
2376
2377
2378	/** @name Selector Descriptor
2379	* @{
2380	*/
2381
2382	#ifndef VBOX_FOR_DTRACE_LIB
2383	/**
2384	* Descriptor attributes (as seen by VT-x).
2385	*/
2386	typedef struct X86DESCATTRBITS
2387	{
2388	/** 00 - Segment Type. */
2389	unsigned u4Type : 4;
2390	/** 04 - Descriptor Type. System(=0) or code/data selector */
2391	unsigned u1DescType : 1;
2392	/** 05 - Descriptor Privelege level. */
2393	unsigned u2Dpl : 2;
2394	/** 07 - Flags selector present(=1) or not. */
2395	unsigned u1Present : 1;
2396	/** 08 - Segment limit 16-19. */
2397	unsigned u4LimitHigh : 4;
2398	/** 0c - Available for system software. */
2399	unsigned u1Available : 1;
2400	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2401	unsigned u1Long : 1;
2402	/** 0e - This flags meaning depends on the segment type. Try make sense out
2403	* of the intel manual yourself. */
2404	unsigned u1DefBig : 1;
2405	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2406	* clear byte. */
2407	unsigned u1Granularity : 1;
2408	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2409	unsigned u1Unusable : 1;
2410	} X86DESCATTRBITS;
2411	#endif /* !VBOX_FOR_DTRACE_LIB */
2412
2413	/** @name X86DESCATTR masks
2414	* @{ */
2415	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2416	#define X86DESCATTR_DT UINT32_C(0x00000010)
2417	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2418	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2419	#define X86DESCATTR_P UINT32_C(0x00000080)
2420	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2421	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2422	#define X86DESCATTR_L UINT32_C(0x00002000)
2423	#define X86DESCATTR_D UINT32_C(0x00004000)
2424	#define X86DESCATTR_G UINT32_C(0x00008000)
2425	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2426	/** @} */
2427
2428	#pragma pack(1)
2429	typedef union X86DESCATTR
2430	{
2431	/** Unsigned integer view. */
2432	uint32_t u;
2433	#ifndef VBOX_FOR_DTRACE_LIB
2434	/** Normal view. */
2435	X86DESCATTRBITS n;
2436	#endif
2437	} X86DESCATTR;
2438	#pragma pack()
2439	/** Pointer to descriptor attributes. */
2440	typedef X86DESCATTR *PX86DESCATTR;
2441	/** Pointer to const descriptor attributes. */
2442	typedef const X86DESCATTR *PCX86DESCATTR;
2443
2444	#ifndef VBOX_FOR_DTRACE_LIB
2445
2446	/**
2447	* Generic descriptor table entry
2448	*/
2449	#pragma pack(1)
2450	typedef struct X86DESCGENERIC
2451	{
2452	/** 00 - Limit - Low word. */
2453	unsigned u16LimitLow : 16;
2454	/** 10 - Base address - lowe word.
2455	* Don't try set this to 24 because MSC is doing stupid things then. */
2456	unsigned u16BaseLow : 16;
2457	/** 20 - Base address - first 8 bits of high word. */
2458	unsigned u8BaseHigh1 : 8;
2459	/** 28 - Segment Type. */
2460	unsigned u4Type : 4;
2461	/** 2c - Descriptor Type. System(=0) or code/data selector */
2462	unsigned u1DescType : 1;
2463	/** 2d - Descriptor Privelege level. */
2464	unsigned u2Dpl : 2;
2465	/** 2f - Flags selector present(=1) or not. */
2466	unsigned u1Present : 1;
2467	/** 30 - Segment limit 16-19. */
2468	unsigned u4LimitHigh : 4;
2469	/** 34 - Available for system software. */
2470	unsigned u1Available : 1;
2471	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2472	unsigned u1Long : 1;
2473	/** 36 - This flags meaning depends on the segment type. Try make sense out
2474	* of the intel manual yourself. */
2475	unsigned u1DefBig : 1;
2476	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
2477	* clear byte. */
2478	unsigned u1Granularity : 1;
2479	/** 38 - Base address - highest 8 bits. */
2480	unsigned u8BaseHigh2 : 8;
2481	} X86DESCGENERIC;
2482	#pragma pack()
2483	/** Pointer to a generic descriptor entry. */
2484	typedef X86DESCGENERIC *PX86DESCGENERIC;
2485	/** Pointer to a const generic descriptor entry. */
2486	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2487
2488	/** @name Bit offsets of X86DESCGENERIC members.
2489	* @{*/
2490	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
2491	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
2492	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
2493	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
2494	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
2495	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
2496	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
2497	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
2498	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
2499	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
2500	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
2501	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
2502	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
2503	/** @} */
2504
2505	/**
2506	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2507	*/
2508	typedef struct X86DESCGATE
2509	{
2510	/** 00 - Target code segment offset - Low word.
2511	* Ignored if task-gate. */
2512	unsigned u16OffsetLow : 16;
2513	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2514	* TSS selector if task-gate. */
2515	unsigned u16Sel : 16;
2516	/** 20 - Number of parameters for a call-gate.
2517	* Ignored if interrupt-, trap- or task-gate. */
2518	unsigned u4ParmCount : 4;
2519	/** 24 - Reserved / ignored. */
2520	unsigned u4Reserved : 4;
2521	/** 28 - Segment Type. */
2522	unsigned u4Type : 4;
2523	/** 2c - Descriptor Type (0 = system). */
2524	unsigned u1DescType : 1;
2525	/** 2d - Descriptor Privelege level. */
2526	unsigned u2Dpl : 2;
2527	/** 2f - Flags selector present(=1) or not. */
2528	unsigned u1Present : 1;
2529	/** 30 - Target code segment offset - High word.
2530	* Ignored if task-gate. */
2531	unsigned u16OffsetHigh : 16;
2532	} X86DESCGATE;
2533	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2534	typedef X86DESCGATE *PX86DESCGATE;
2535	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2536	typedef const X86DESCGATE *PCX86DESCGATE;
2537
2538	#endif /* VBOX_FOR_DTRACE_LIB */
2539
2540	/**
2541	* Descriptor table entry.
2542	*/
2543	#pragma pack(1)
2544	typedef union X86DESC
2545	{
2546	#ifndef VBOX_FOR_DTRACE_LIB
2547	/** Generic descriptor view. */
2548	X86DESCGENERIC Gen;
2549	/** Gate descriptor view. */
2550	X86DESCGATE Gate;
2551	#endif
2552
2553	/** 8 bit unsigned integer view. */
2554	uint8_t au8[8];
2555	/** 16 bit unsigned integer view. */
2556	uint16_t au16[4];
2557	/** 32 bit unsigned integer view. */
2558	uint32_t au32[2];
2559	/** 64 bit unsigned integer view. */
2560	uint64_t au64[1];
2561	/** Unsigned integer view. */
2562	uint64_t u;
2563	} X86DESC;
2564	#ifndef VBOX_FOR_DTRACE_LIB
2565	AssertCompileSize(X86DESC, 8);
2566	#endif
2567	#pragma pack()
2568	/** Pointer to descriptor table entry. */
2569	typedef X86DESC *PX86DESC;
2570	/** Pointer to const descriptor table entry. */
2571	typedef const X86DESC *PCX86DESC;
2572
2573	/** @def X86DESC_BASE
2574	* Return the base address of a descriptor.
2575	*/
2576	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
2577	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2578	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2579	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2580
2581	/** @def X86DESC_LIMIT
2582	* Return the limit of a descriptor.
2583	*/
2584	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
2585	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2586	\| ( (a_pDesc)->Gen.u16LimitLow ) )
2587
2588	/** @def X86DESC_LIMIT_G
2589	* Return the limit of a descriptor with the granularity bit taken into account.
2590	* @returns Selector limit (uint32_t).
2591	* @param a_pDesc Pointer to the descriptor.
2592	*/
2593	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
2594	( (a_pDesc)->Gen.u1Granularity \
2595	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
2596	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
2597	)
2598
2599	/** @def X86DESC_GET_HID_ATTR
2600	* Get the descriptor attributes for the hidden register.
2601	*/
2602	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
2603	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2604
2605	#ifndef VBOX_FOR_DTRACE_LIB
2606
2607	/**
2608	* 64 bits generic descriptor table entry
2609	* Note: most of these bits have no meaning in long mode.
2610	*/
2611	#pragma pack(1)
2612	typedef struct X86DESC64GENERIC
2613	{
2614	/** Limit - Low word - IGNORED. */
2615	unsigned u16LimitLow : 16;
2616	/** Base address - low word. - IGNORED
2617	* Don't try set this to 24 because MSC is doing stupid things then. */
2618	unsigned u16BaseLow : 16;
2619	/** Base address - first 8 bits of high word. - IGNORED */
2620	unsigned u8BaseHigh1 : 8;
2621	/** Segment Type. */
2622	unsigned u4Type : 4;
2623	/** Descriptor Type. System(=0) or code/data selector */
2624	unsigned u1DescType : 1;
2625	/** Descriptor Privelege level. */
2626	unsigned u2Dpl : 2;
2627	/** Flags selector present(=1) or not. */
2628	unsigned u1Present : 1;
2629	/** Segment limit 16-19. - IGNORED */
2630	unsigned u4LimitHigh : 4;
2631	/** Available for system software. - IGNORED */
2632	unsigned u1Available : 1;
2633	/** Long mode flag. */
2634	unsigned u1Long : 1;
2635	/** This flags meaning depends on the segment type. Try make sense out
2636	* of the intel manual yourself. */
2637	unsigned u1DefBig : 1;
2638	/** Granularity of the limit. If set 4KB granularity is used, if
2639	* clear byte. - IGNORED */
2640	unsigned u1Granularity : 1;
2641	/** Base address - highest 8 bits. - IGNORED */
2642	unsigned u8BaseHigh2 : 8;
2643	/** Base address - bits 63-32. */
2644	unsigned u32BaseHigh3 : 32;
2645	unsigned u8Reserved : 8;
2646	unsigned u5Zeros : 5;
2647	unsigned u19Reserved : 19;
2648	} X86DESC64GENERIC;
2649	#pragma pack()
2650	/** Pointer to a generic descriptor entry. */
2651	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2652	/** Pointer to a const generic descriptor entry. */
2653	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2654
2655	/**
2656	* System descriptor table entry (64 bits)
2657	*
2658	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2659	*/
2660	#pragma pack(1)
2661	typedef struct X86DESC64SYSTEM
2662	{
2663	/** Limit - Low word. */
2664	unsigned u16LimitLow : 16;
2665	/** Base address - lowe word.
2666	* Don't try set this to 24 because MSC is doing stupid things then. */
2667	unsigned u16BaseLow : 16;
2668	/** Base address - first 8 bits of high word. */
2669	unsigned u8BaseHigh1 : 8;
2670	/** Segment Type. */
2671	unsigned u4Type : 4;
2672	/** Descriptor Type. System(=0) or code/data selector */
2673	unsigned u1DescType : 1;
2674	/** Descriptor Privelege level. */
2675	unsigned u2Dpl : 2;
2676	/** Flags selector present(=1) or not. */
2677	unsigned u1Present : 1;
2678	/** Segment limit 16-19. */
2679	unsigned u4LimitHigh : 4;
2680	/** Available for system software. */
2681	unsigned u1Available : 1;
2682	/** Reserved - 0. */
2683	unsigned u1Reserved : 1;
2684	/** This flags meaning depends on the segment type. Try make sense out
2685	* of the intel manual yourself. */
2686	unsigned u1DefBig : 1;
2687	/** Granularity of the limit. If set 4KB granularity is used, if
2688	* clear byte. */
2689	unsigned u1Granularity : 1;
2690	/** Base address - bits 31-24. */
2691	unsigned u8BaseHigh2 : 8;
2692	/** Base address - bits 63-32. */
2693	unsigned u32BaseHigh3 : 32;
2694	unsigned u8Reserved : 8;
2695	unsigned u5Zeros : 5;
2696	unsigned u19Reserved : 19;
2697	} X86DESC64SYSTEM;
2698	#pragma pack()
2699	/** Pointer to a system descriptor entry. */
2700	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2701	/** Pointer to a const system descriptor entry. */
2702	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2703
2704	/**
2705	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2706	*/
2707	typedef struct X86DESC64GATE
2708	{
2709	/** Target code segment offset - Low word. */
2710	unsigned u16OffsetLow : 16;
2711	/** Target code segment selector. */
2712	unsigned u16Sel : 16;
2713	/** Interrupt stack table for interrupt- and trap-gates.
2714	* Ignored by call-gates. */
2715	unsigned u3IST : 3;
2716	/** Reserved / ignored. */
2717	unsigned u5Reserved : 5;
2718	/** Segment Type. */
2719	unsigned u4Type : 4;
2720	/** Descriptor Type (0 = system). */
2721	unsigned u1DescType : 1;
2722	/** Descriptor Privelege level. */
2723	unsigned u2Dpl : 2;
2724	/** Flags selector present(=1) or not. */
2725	unsigned u1Present : 1;
2726	/** Target code segment offset - High word.
2727	* Ignored if task-gate. */
2728	unsigned u16OffsetHigh : 16;
2729	/** Target code segment offset - Top dword.
2730	* Ignored if task-gate. */
2731	unsigned u32OffsetTop : 32;
2732	/** Reserved / ignored / must be zero.
2733	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2734	unsigned u32Reserved : 32;
2735	} X86DESC64GATE;
2736	AssertCompileSize(X86DESC64GATE, 16);
2737	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2738	typedef X86DESC64GATE *PX86DESC64GATE;
2739	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2740	typedef const X86DESC64GATE *PCX86DESC64GATE;
2741
2742	#endif /* VBOX_FOR_DTRACE_LIB */
2743
2744	/**
2745	* Descriptor table entry.
2746	*/
2747	#pragma pack(1)
2748	typedef union X86DESC64
2749	{
2750	#ifndef VBOX_FOR_DTRACE_LIB
2751	/** Generic descriptor view. */
2752	X86DESC64GENERIC Gen;
2753	/** System descriptor view. */
2754	X86DESC64SYSTEM System;
2755	/** Gate descriptor view. */
2756	X86DESC64GATE Gate;
2757	#endif
2758
2759	/** 8 bit unsigned integer view. */
2760	uint8_t au8[16];
2761	/** 16 bit unsigned integer view. */
2762	uint16_t au16[8];
2763	/** 32 bit unsigned integer view. */
2764	uint32_t au32[4];
2765	/** 64 bit unsigned integer view. */
2766	uint64_t au64[2];
2767	} X86DESC64;
2768	#ifndef VBOX_FOR_DTRACE_LIB
2769	AssertCompileSize(X86DESC64, 16);
2770	#endif
2771	#pragma pack()
2772	/** Pointer to descriptor table entry. */
2773	typedef X86DESC64 *PX86DESC64;
2774	/** Pointer to const descriptor table entry. */
2775	typedef const X86DESC64 *PCX86DESC64;
2776
2777	/** @def X86DESC64_BASE
2778	* Return the base of a 64-bit descriptor.
2779	*/
2780	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
2781	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2782	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2783	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2784	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2785
2786
2787
2788	/** @name Host system descriptor table entry - Use with care!
2789	* @{ */
2790	/** Host system descriptor table entry. */
2791	#if HC_ARCH_BITS == 64
2792	typedef X86DESC64 X86DESCHC;
2793	#else
2794	typedef X86DESC X86DESCHC;
2795	#endif
2796	/** Pointer to a host system descriptor table entry. */
2797	#if HC_ARCH_BITS == 64
2798	typedef PX86DESC64 PX86DESCHC;
2799	#else
2800	typedef PX86DESC PX86DESCHC;
2801	#endif
2802	/** Pointer to a const host system descriptor table entry. */
2803	#if HC_ARCH_BITS == 64
2804	typedef PCX86DESC64 PCX86DESCHC;
2805	#else
2806	typedef PCX86DESC PCX86DESCHC;
2807	#endif
2808	/** @} */
2809
2810
2811	/** @name Selector Descriptor Types.
2812	* @{
2813	*/
2814
2815	/** @name Non-System Selector Types.
2816	* @{ */
2817	/** Code(=set)/Data(=clear) bit. */
2818	#define X86_SEL_TYPE_CODE 8
2819	/** Memory(=set)/System(=clear) bit. */
2820	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2821	/** Accessed bit. */
2822	#define X86_SEL_TYPE_ACCESSED 1
2823	/** Expand down bit (for data selectors only). */
2824	#define X86_SEL_TYPE_DOWN 4
2825	/** Conforming bit (for code selectors only). */
2826	#define X86_SEL_TYPE_CONF 4
2827	/** Write bit (for data selectors only). */
2828	#define X86_SEL_TYPE_WRITE 2
2829	/** Read bit (for code selectors only). */
2830	#define X86_SEL_TYPE_READ 2
2831	/** The bit number of the code segment read bit (relative to u4Type). */
2832	#define X86_SEL_TYPE_READ_BIT 1
2833
2834	/** Read only selector type. */
2835	#define X86_SEL_TYPE_RO 0
2836	/** Accessed read only selector type. */
2837	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2838	/** Read write selector type. */
2839	#define X86_SEL_TYPE_RW 2
2840	/** Accessed read write selector type. */
2841	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2842	/** Expand down read only selector type. */
2843	#define X86_SEL_TYPE_RO_DOWN 4
2844	/** Accessed expand down read only selector type. */
2845	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2846	/** Expand down read write selector type. */
2847	#define X86_SEL_TYPE_RW_DOWN 6
2848	/** Accessed expand down read write selector type. */
2849	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2850	/** Execute only selector type. */
2851	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2852	/** Accessed execute only selector type. */
2853	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2854	/** Execute and read selector type. */
2855	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2856	/** Accessed execute and read selector type. */
2857	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2858	/** Conforming execute only selector type. */
2859	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2860	/** Accessed Conforming execute only selector type. */
2861	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2862	/** Conforming execute and write selector type. */
2863	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2864	/** Accessed Conforming execute and write selector type. */
2865	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2866	/** @} */
2867
2868
2869	/** @name System Selector Types.
2870	* @{ */
2871	/** The TSS busy bit mask. */
2872	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2873
2874	/** Undefined system selector type. */
2875	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2876	/** 286 TSS selector. */
2877	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2878	/** LDT selector. */
2879	#define X86_SEL_TYPE_SYS_LDT 2
2880	/** 286 TSS selector - Busy. */
2881	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2882	/** 286 Callgate selector. */
2883	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2884	/** Taskgate selector. */
2885	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2886	/** 286 Interrupt gate selector. */
2887	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2888	/** 286 Trapgate selector. */
2889	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2890	/** Undefined system selector. */
2891	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2892	/** 386 TSS selector. */
2893	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2894	/** Undefined system selector. */
2895	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2896	/** 386 TSS selector - Busy. */
2897	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2898	/** 386 Callgate selector. */
2899	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2900	/** Undefined system selector. */
2901	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2902	/** 386 Interruptgate selector. */
2903	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2904	/** 386 Trapgate selector. */
2905	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2906	/** @} */
2907
2908	/** @name AMD64 System Selector Types.
2909	* @{ */
2910	/** LDT selector. */
2911	#define AMD64_SEL_TYPE_SYS_LDT 2
2912	/** TSS selector - Busy. */
2913	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2914	/** TSS selector - Busy. */
2915	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2916	/** Callgate selector. */
2917	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2918	/** Interruptgate selector. */
2919	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2920	/** Trapgate selector. */
2921	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2922	/** @} */
2923
2924	/** @} */
2925
2926
2927	/** @name Descriptor Table Entry Flag Masks.
2928	* These are for the 2nd 32-bit word of a descriptor.
2929	* @{ */
2930	/** Bits 8-11 - TYPE - Descriptor type mask. */
2931	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2932	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2933	#define X86_DESC_S RT_BIT(12)
2934	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2935	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2936	/** Bit 15 - P - Present. */
2937	#define X86_DESC_P RT_BIT(15)
2938	/** Bit 20 - AVL - Available for system software. */
2939	#define X86_DESC_AVL RT_BIT(20)
2940	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2941	#define X86_DESC_DB RT_BIT(22)
2942	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2943	* used, if clear byte. */
2944	#define X86_DESC_G RT_BIT(23)
2945	/** @} */
2946
2947	/** @} */
2948
2949
2950	/** @name Task Segments.
2951	* @{
2952	*/
2953
2954	/**
2955	* 16-bit Task Segment (TSS).
2956	*/
2957	#pragma pack(1)
2958	typedef struct X86TSS16
2959	{
2960	/** Back link to previous task. (static) */
2961	RTSEL selPrev;
2962	/** Ring-0 stack pointer. (static) */
2963	uint16_t sp0;
2964	/** Ring-0 stack segment. (static) */
2965	RTSEL ss0;
2966	/** Ring-1 stack pointer. (static) */
2967	uint16_t sp1;
2968	/** Ring-1 stack segment. (static) */
2969	RTSEL ss1;
2970	/** Ring-2 stack pointer. (static) */
2971	uint16_t sp2;
2972	/** Ring-2 stack segment. (static) */
2973	RTSEL ss2;
2974	/** IP before task switch. */
2975	uint16_t ip;
2976	/** FLAGS before task switch. */
2977	uint16_t flags;
2978	/** AX before task switch. */
2979	uint16_t ax;
2980	/** CX before task switch. */
2981	uint16_t cx;
2982	/** DX before task switch. */
2983	uint16_t dx;
2984	/** BX before task switch. */
2985	uint16_t bx;
2986	/** SP before task switch. */
2987	uint16_t sp;
2988	/** BP before task switch. */
2989	uint16_t bp;
2990	/** SI before task switch. */
2991	uint16_t si;
2992	/** DI before task switch. */
2993	uint16_t di;
2994	/** ES before task switch. */
2995	RTSEL es;
2996	/** CS before task switch. */
2997	RTSEL cs;
2998	/** SS before task switch. */
2999	RTSEL ss;
3000	/** DS before task switch. */
3001	RTSEL ds;
3002	/** LDTR before task switch. */
3003	RTSEL selLdt;
3004	} X86TSS16;
3005	#ifndef VBOX_FOR_DTRACE_LIB
3006	AssertCompileSize(X86TSS16, 44);
3007	#endif
3008	#pragma pack()
3009	/** Pointer to a 16-bit task segment. */
3010	typedef X86TSS16 *PX86TSS16;
3011	/** Pointer to a const 16-bit task segment. */
3012	typedef const X86TSS16 *PCX86TSS16;
3013
3014
3015	/**
3016	* 32-bit Task Segment (TSS).
3017	*/
3018	#pragma pack(1)
3019	typedef struct X86TSS32
3020	{
3021	/** Back link to previous task. (static) */
3022	RTSEL selPrev;
3023	uint16_t padding1;
3024	/** Ring-0 stack pointer. (static) */
3025	uint32_t esp0;
3026	/** Ring-0 stack segment. (static) */
3027	RTSEL ss0;
3028	uint16_t padding_ss0;
3029	/** Ring-1 stack pointer. (static) */
3030	uint32_t esp1;
3031	/** Ring-1 stack segment. (static) */
3032	RTSEL ss1;
3033	uint16_t padding_ss1;
3034	/** Ring-2 stack pointer. (static) */
3035	uint32_t esp2;
3036	/** Ring-2 stack segment. (static) */
3037	RTSEL ss2;
3038	uint16_t padding_ss2;
3039	/** Page directory for the task. (static) */
3040	uint32_t cr3;
3041	/** EIP before task switch. */
3042	uint32_t eip;
3043	/** EFLAGS before task switch. */
3044	uint32_t eflags;
3045	/** EAX before task switch. */
3046	uint32_t eax;
3047	/** ECX before task switch. */
3048	uint32_t ecx;
3049	/** EDX before task switch. */
3050	uint32_t edx;
3051	/** EBX before task switch. */
3052	uint32_t ebx;
3053	/** ESP before task switch. */
3054	uint32_t esp;
3055	/** EBP before task switch. */
3056	uint32_t ebp;
3057	/** ESI before task switch. */
3058	uint32_t esi;
3059	/** EDI before task switch. */
3060	uint32_t edi;
3061	/** ES before task switch. */
3062	RTSEL es;
3063	uint16_t padding_es;
3064	/** CS before task switch. */
3065	RTSEL cs;
3066	uint16_t padding_cs;
3067	/** SS before task switch. */
3068	RTSEL ss;
3069	uint16_t padding_ss;
3070	/** DS before task switch. */
3071	RTSEL ds;
3072	uint16_t padding_ds;
3073	/** FS before task switch. */
3074	RTSEL fs;
3075	uint16_t padding_fs;
3076	/** GS before task switch. */
3077	RTSEL gs;
3078	uint16_t padding_gs;
3079	/** LDTR before task switch. */
3080	RTSEL selLdt;
3081	uint16_t padding_ldt;
3082	/** Debug trap flag */
3083	uint16_t fDebugTrap;
3084	/** Offset relative to the TSS of the start of the I/O Bitmap
3085	* and the end of the interrupt redirection bitmap. */
3086	uint16_t offIoBitmap;
3087	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3088	uint8_t IntRedirBitmap[32];
3089	} X86TSS32;
3090	#pragma pack()
3091	/** Pointer to task segment. */
3092	typedef X86TSS32 *PX86TSS32;
3093	/** Pointer to const task segment. */
3094	typedef const X86TSS32 *PCX86TSS32;
3095
3096
3097	/**
3098	* 64-bit Task segment.
3099	*/
3100	#pragma pack(1)
3101	typedef struct X86TSS64
3102	{
3103	/** Reserved. */
3104	uint32_t u32Reserved;
3105	/** Ring-0 stack pointer. (static) */
3106	uint64_t rsp0;
3107	/** Ring-1 stack pointer. (static) */
3108	uint64_t rsp1;
3109	/** Ring-2 stack pointer. (static) */
3110	uint64_t rsp2;
3111	/** Reserved. */
3112	uint32_t u32Reserved2[2];
3113	/* IST */
3114	uint64_t ist1;
3115	uint64_t ist2;
3116	uint64_t ist3;
3117	uint64_t ist4;
3118	uint64_t ist5;
3119	uint64_t ist6;
3120	uint64_t ist7;
3121	/* Reserved. */
3122	uint16_t u16Reserved[5];
3123	/** Offset relative to the TSS of the start of the I/O Bitmap
3124	* and the end of the interrupt redirection bitmap. */
3125	uint16_t offIoBitmap;
3126	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3127	uint8_t IntRedirBitmap[32];
3128	} X86TSS64;
3129	#pragma pack()
3130	/** Pointer to a 64-bit task segment. */
3131	typedef X86TSS64 *PX86TSS64;
3132	/** Pointer to a const 64-bit task segment. */
3133	typedef const X86TSS64 *PCX86TSS64;
3134	#ifndef VBOX_FOR_DTRACE_LIB
3135	AssertCompileSize(X86TSS64, 136);
3136	#endif
3137
3138	/** @} */
3139
3140
3141	/** @name Selectors.
3142	* @{
3143	*/
3144
3145	/**
3146	* The shift used to convert a selector from and to index an index (C).
3147	*/
3148	#define X86_SEL_SHIFT 3
3149
3150	/**
3151	* The mask used to mask off the table indicator and RPL of an selector.
3152	*/
3153	#define X86_SEL_MASK 0xfff8U
3154
3155	/**
3156	* The mask used to mask off the RPL of an selector.
3157	* This is suitable for checking for NULL selectors.
3158	*/
3159	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3160
3161	/**
3162	* The bit indicating that a selector is in the LDT and not in the GDT.
3163	*/
3164	#define X86_SEL_LDT 0x0004U
3165
3166	/**
3167	* The bit mask for getting the RPL of a selector.
3168	*/
3169	#define X86_SEL_RPL 0x0003U
3170
3171	/**
3172	* The mask covering both RPL and LDT.
3173	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3174	* checks.
3175	*/
3176	#define X86_SEL_RPL_LDT 0x0007U
3177
3178	/** @} */
3179
3180
3181	/**
3182	* x86 Exceptions/Faults/Traps.
3183	*/
3184	typedef enum X86XCPT
3185	{
3186	/** \#DE - Divide error. */
3187	X86_XCPT_DE = 0x00,
3188	/** \#DB - Debug event (single step, DRx, ..) */
3189	X86_XCPT_DB = 0x01,
3190	/** NMI - Non-Maskable Interrupt */
3191	X86_XCPT_NMI = 0x02,
3192	/** \#BP - Breakpoint (INT3). */
3193	X86_XCPT_BP = 0x03,
3194	/** \#OF - Overflow (INTO). */
3195	X86_XCPT_OF = 0x04,
3196	/** \#BR - Bound range exceeded (BOUND). */
3197	X86_XCPT_BR = 0x05,
3198	/** \#UD - Undefined opcode. */
3199	X86_XCPT_UD = 0x06,
3200	/** \#NM - Device not available (math coprocessor device). */
3201	X86_XCPT_NM = 0x07,
3202	/** \#DF - Double fault. */
3203	X86_XCPT_DF = 0x08,
3204	/** ??? - Coprocessor segment overrun (obsolete). */
3205	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3206	/** \#TS - Taskswitch (TSS). */
3207	X86_XCPT_TS = 0x0a,
3208	/** \#NP - Segment no present. */
3209	X86_XCPT_NP = 0x0b,
3210	/** \#SS - Stack segment fault. */
3211	X86_XCPT_SS = 0x0c,
3212	/** \#GP - General protection fault. */
3213	X86_XCPT_GP = 0x0d,
3214	/** \#PF - Page fault. */
3215	X86_XCPT_PF = 0x0e,
3216	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3217	/** \#MF - Math fault (FPU). */
3218	X86_XCPT_MF = 0x10,
3219	/** \#AC - Alignment check. */
3220	X86_XCPT_AC = 0x11,
3221	/** \#MC - Machine check. */
3222	X86_XCPT_MC = 0x12,
3223	/** \#XF - SIMD Floating-Pointer Exception. */
3224	X86_XCPT_XF = 0x13,
3225	/** \#VE - Virtualzation Exception. */
3226	X86_XCPT_VE = 0x14,
3227	/** \#SX - Security Exception. */
3228	X86_XCPT_SX = 0x1f
3229	} X86XCPT;
3230	/** Pointer to a x86 exception code. */
3231	typedef X86XCPT *PX86XCPT;
3232	/** Pointer to a const x86 exception code. */
3233	typedef const X86XCPT *PCX86XCPT;
3234	/** The maximum exception value. */
3235	#define X86_XCPT_MAX (X86_XCPT_SX)
3236
3237
3238	/** @name Trap Error Codes
3239	* @{
3240	*/
3241	/** External indicator. */
3242	#define X86_TRAP_ERR_EXTERNAL 1
3243	/** IDT indicator. */
3244	#define X86_TRAP_ERR_IDT 2
3245	/** Descriptor table indicator - If set LDT, if clear GDT. */
3246	#define X86_TRAP_ERR_TI 4
3247	/** Mask for getting the selector. */
3248	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3249	/** Shift for getting the selector table index (C type index). */
3250	#define X86_TRAP_ERR_SEL_SHIFT 3
3251	/** @} */
3252
3253
3254	/** @name \#PF Trap Error Codes
3255	* @{
3256	*/
3257	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3258	#define X86_TRAP_PF_P RT_BIT(0)
3259	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3260	#define X86_TRAP_PF_RW RT_BIT(1)
3261	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3262	#define X86_TRAP_PF_US RT_BIT(2)
3263	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3264	#define X86_TRAP_PF_RSVD RT_BIT(3)
3265	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3266	#define X86_TRAP_PF_ID RT_BIT(4)
3267	/** @} */
3268
3269	#pragma pack(1)
3270	/**
3271	* 32-bit IDTR/GDTR.
3272	*/
3273	typedef struct X86XDTR32
3274	{
3275	/** Size of the descriptor table. */
3276	uint16_t cb;
3277	/** Address of the descriptor table. */
3278	#ifndef VBOX_FOR_DTRACE_LIB
3279	uint32_t uAddr;
3280	#else
3281	uint16_t au16Addr[2];
3282	#endif
3283	} X86XDTR32, *PX86XDTR32;
3284	#pragma pack()
3285
3286	#pragma pack(1)
3287	/**
3288	* 64-bit IDTR/GDTR.
3289	*/
3290	typedef struct X86XDTR64
3291	{
3292	/** Size of the descriptor table. */
3293	uint16_t cb;
3294	/** Address of the descriptor table. */
3295	#ifndef VBOX_FOR_DTRACE_LIB
3296	uint64_t uAddr;
3297	#else
3298	uint16_t au16Addr[4];
3299	#endif
3300	} X86XDTR64, *PX86XDTR64;
3301	#pragma pack()
3302
3303
3304	/** @name ModR/M
3305	* @{ */
3306	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3307	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3308	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3309	#define X86_MODRM_REG_SHIFT 3
3310	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3311	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3312	#define X86_MODRM_MOD_SHIFT 6
3313	#ifndef VBOX_FOR_DTRACE_LIB
3314	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3315	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3316	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3317	#endif
3318	/** @} */
3319
3320	/** @name SIB
3321	* @{ */
3322	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3323	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3324	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3325	#define X86_SIB_INDEX_SHIFT 3
3326	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3327	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3328	#define X86_SIB_SCALE_SHIFT 6
3329	#ifndef VBOX_FOR_DTRACE_LIB
3330	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3331	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3332	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3333	#endif
3334	/** @} */
3335
3336	/** @name General register indexes
3337	* @{ */
3338	#define X86_GREG_xAX 0
3339	#define X86_GREG_xCX 1
3340	#define X86_GREG_xDX 2
3341	#define X86_GREG_xBX 3
3342	#define X86_GREG_xSP 4
3343	#define X86_GREG_xBP 5
3344	#define X86_GREG_xSI 6
3345	#define X86_GREG_xDI 7
3346	#define X86_GREG_x8 8
3347	#define X86_GREG_x9 9
3348	#define X86_GREG_x10 10
3349	#define X86_GREG_x11 11
3350	#define X86_GREG_x12 12
3351	#define X86_GREG_x13 13
3352	#define X86_GREG_x14 14
3353	#define X86_GREG_x15 15
3354	/** @} */
3355
3356	/** @name X86_SREG_XXX - Segment register indexes.
3357	* @{ */
3358	#define X86_SREG_ES 0
3359	#define X86_SREG_CS 1
3360	#define X86_SREG_SS 2
3361	#define X86_SREG_DS 3
3362	#define X86_SREG_FS 4
3363	#define X86_SREG_GS 5
3364	/** @} */
3365	/** Segment register count. */
3366	#define X86_SREG_COUNT 6
3367
3368
3369	/** @name X86_OP_XXX - Prefixes
3370	* @{ */
3371	#define X86_OP_PRF_CS UINT8_C(0x2e)
3372	#define X86_OP_PRF_SS UINT8_C(0x36)
3373	#define X86_OP_PRF_DS UINT8_C(0x3e)
3374	#define X86_OP_PRF_ES UINT8_C(0x26)
3375	#define X86_OP_PRF_FS UINT8_C(0x64)
3376	#define X86_OP_PRF_GS UINT8_C(0x65)
3377	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3378	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3379	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3380	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3381	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3382	#define X86_OP_REX_B UINT8_C(0x41)
3383	#define X86_OP_REX_X UINT8_C(0x42)
3384	#define X86_OP_REX_R UINT8_C(0x44)
3385	#define X86_OP_REX_W UINT8_C(0x48)
3386	/** @} */
3387
3388
3389	/** @} */
3390
3391	#endif
3392

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source: vbox/trunk/include/iprt/x86.h@ 48267

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