x86.h@ 50255

Last change on this file since 50255 was 50255, checked in by vboxsync, 11 years ago
VMM: two undocumented CPUID bits
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The the IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** The status bits commonly updated by arithmetic instructions. */
215	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
216	/** @} */
217
218
219	/** CPUID Feature information - ECX.
220	* CPUID query with EAX=1.
221	*/
222	#ifndef VBOX_FOR_DTRACE_LIB
223	typedef struct X86CPUIDFEATECX
224	{
225	/** Bit 0 - SSE3 - Supports SSE3 or not. */
226	unsigned u1SSE3 : 1;
227	/** Bit 1 - PCLMULQDQ. */
228	unsigned u1PCLMULQDQ : 1;
229	/** Bit 2 - DS Area 64-bit layout. */
230	unsigned u1DTE64 : 1;
231	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
232	unsigned u1Monitor : 1;
233	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
234	unsigned u1CPLDS : 1;
235	/** Bit 5 - VMX - Virtual Machine Technology. */
236	unsigned u1VMX : 1;
237	/** Bit 6 - SMX: Safer Mode Extensions. */
238	unsigned u1SMX : 1;
239	/** Bit 7 - EST - Enh. SpeedStep Tech. */
240	unsigned u1EST : 1;
241	/** Bit 8 - TM2 - Terminal Monitor 2. */
242	unsigned u1TM2 : 1;
243	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
244	unsigned u1SSSE3 : 1;
245	/** Bit 10 - CNTX-ID - L1 Context ID. */
246	unsigned u1CNTXID : 1;
247	/** Bit 11 - Reserved. */
248	unsigned u1Reserved1 : 1;
249	/** Bit 12 - FMA. */
250	unsigned u1FMA : 1;
251	/** Bit 13 - CX16 - CMPXCHG16B. */
252	unsigned u1CX16 : 1;
253	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
254	unsigned u1TPRUpdate : 1;
255	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
256	unsigned u1PDCM : 1;
257	/** Bit 16 - Reserved. */
258	unsigned u1Reserved2 : 1;
259	/** Bit 17 - PCID - Process-context identifiers. */
260	unsigned u1PCID : 1;
261	/** Bit 18 - Direct Cache Access. */
262	unsigned u1DCA : 1;
263	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
264	unsigned u1SSE4_1 : 1;
265	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
266	unsigned u1SSE4_2 : 1;
267	/** Bit 21 - x2APIC. */
268	unsigned u1x2APIC : 1;
269	/** Bit 22 - MOVBE - Supports MOVBE. */
270	unsigned u1MOVBE : 1;
271	/** Bit 23 - POPCNT - Supports POPCNT. */
272	unsigned u1POPCNT : 1;
273	/** Bit 24 - TSC-Deadline. */
274	unsigned u1TSCDEADLINE : 1;
275	/** Bit 25 - AES. */
276	unsigned u1AES : 1;
277	/** Bit 26 - XSAVE - Supports XSAVE. */
278	unsigned u1XSAVE : 1;
279	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
280	unsigned u1OSXSAVE : 1;
281	/** Bit 28 - AVX - Supports AVX instruction extensions. */
282	unsigned u1AVX : 1;
283	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
284	unsigned u1F16C : 1;
285	/** Bit 30 - RDRAND - Supports RDRAND. */
286	unsigned u1RDRAND : 1;
287	/** Bit 31 - Hypervisor present (we're a guest). */
288	unsigned u1HVP : 1;
289	} X86CPUIDFEATECX;
290	#else /* VBOX_FOR_DTRACE_LIB */
291	typedef uint32_t X86CPUIDFEATECX;
292	#endif /* VBOX_FOR_DTRACE_LIB */
293	/** Pointer to CPUID Feature Information - ECX. */
294	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
295	/** Pointer to const CPUID Feature Information - ECX. */
296	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
297
298
299	/** CPUID Feature Information - EDX.
300	* CPUID query with EAX=1.
301	*/
302	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
303	typedef struct X86CPUIDFEATEDX
304	{
305	/** Bit 0 - FPU - x87 FPU on Chip. */
306	unsigned u1FPU : 1;
307	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
308	unsigned u1VME : 1;
309	/** Bit 2 - DE - Debugging extensions. */
310	unsigned u1DE : 1;
311	/** Bit 3 - PSE - Page Size Extension. */
312	unsigned u1PSE : 1;
313	/** Bit 4 - TSC - Time Stamp Counter. */
314	unsigned u1TSC : 1;
315	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
316	unsigned u1MSR : 1;
317	/** Bit 6 - PAE - Physical Address Extension. */
318	unsigned u1PAE : 1;
319	/** Bit 7 - MCE - Machine Check Exception. */
320	unsigned u1MCE : 1;
321	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
322	unsigned u1CX8 : 1;
323	/** Bit 9 - APIC - APIC On-Chip. */
324	unsigned u1APIC : 1;
325	/** Bit 10 - Reserved. */
326	unsigned u1Reserved1 : 1;
327	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
328	unsigned u1SEP : 1;
329	/** Bit 12 - MTRR - Memory Type Range Registers. */
330	unsigned u1MTRR : 1;
331	/** Bit 13 - PGE - PTE Global Bit. */
332	unsigned u1PGE : 1;
333	/** Bit 14 - MCA - Machine Check Architecture. */
334	unsigned u1MCA : 1;
335	/** Bit 15 - CMOV - Conditional Move Instructions. */
336	unsigned u1CMOV : 1;
337	/** Bit 16 - PAT - Page Attribute Table. */
338	unsigned u1PAT : 1;
339	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
340	unsigned u1PSE36 : 1;
341	/** Bit 18 - PSN - Processor Serial Number. */
342	unsigned u1PSN : 1;
343	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
344	unsigned u1CLFSH : 1;
345	/** Bit 20 - Reserved. */
346	unsigned u1Reserved2 : 1;
347	/** Bit 21 - DS - Debug Store. */
348	unsigned u1DS : 1;
349	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
350	unsigned u1ACPI : 1;
351	/** Bit 23 - MMX - Intel MMX 'Technology'. */
352	unsigned u1MMX : 1;
353	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
354	unsigned u1FXSR : 1;
355	/** Bit 25 - SSE - SSE Support. */
356	unsigned u1SSE : 1;
357	/** Bit 26 - SSE2 - SSE2 Support. */
358	unsigned u1SSE2 : 1;
359	/** Bit 27 - SS - Self Snoop. */
360	unsigned u1SS : 1;
361	/** Bit 28 - HTT - Hyper-Threading Technology. */
362	unsigned u1HTT : 1;
363	/** Bit 29 - TM - Thermal Monitor. */
364	unsigned u1TM : 1;
365	/** Bit 30 - Reserved - . */
366	unsigned u1Reserved3 : 1;
367	/** Bit 31 - PBE - Pending Break Enabled. */
368	unsigned u1PBE : 1;
369	} X86CPUIDFEATEDX;
370	#else /* VBOX_FOR_DTRACE_LIB */
371	typedef uint32_t X86CPUIDFEATEDX;
372	#endif /* VBOX_FOR_DTRACE_LIB */
373	/** Pointer to CPUID Feature Information - EDX. */
374	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
375	/** Pointer to const CPUID Feature Information - EDX. */
376	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
377
378	/** @name CPUID Vendor information.
379	* CPUID query with EAX=0.
380	* @{
381	*/
382	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
383	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
384	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
385
386	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
387	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
388	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
389
390	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
391	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
392	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
393	/** @} */
394
395
396	/** @name CPUID Feature information.
397	* CPUID query with EAX=1.
398	* @{
399	*/
400	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
401	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
402	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
403	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
404	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
405	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
406	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
407	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
408	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
409	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
410	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
411	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
412	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
413	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
414	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
415	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
416	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
417	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
418	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
419	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
420	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
421	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
422	/** ECX Bit 12 - FMA. */
423	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
424	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
425	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
426	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
427	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
428	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
429	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
430	/** ECX Bit 17 - PCID - Process-context identifiers. */
431	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
432	/** ECX Bit 18 - DCA - Direct Cache Access. */
433	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
434	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
435	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
436	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
437	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
438	/** ECX Bit 21 - x2APIC support. */
439	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
440	/** ECX Bit 22 - MOVBE instruction. */
441	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
442	/** ECX Bit 23 - POPCNT instruction. */
443	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
444	/** ECX Bir 24 - TSC-Deadline. */
445	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
446	/** ECX Bit 25 - AES instructions. */
447	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
448	/** ECX Bit 26 - XSAVE instruction. */
449	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
450	/** ECX Bit 27 - OSXSAVE instruction. */
451	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
452	/** ECX Bit 28 - AVX. */
453	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
454	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
455	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29)
456	/** ECX Bit 30 - RDRAND instruction. */
457	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT(30)
458	/** ECX Bit 31 - Hypervisor Present (software only). */
459	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
460
461
462	/** Bit 0 - FPU - x87 FPU on Chip. */
463	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
464	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
465	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
466	/** Bit 2 - DE - Debugging extensions. */
467	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
468	/** Bit 3 - PSE - Page Size Extension. */
469	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
470	/** Bit 4 - TSC - Time Stamp Counter. */
471	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
472	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
473	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
474	/** Bit 6 - PAE - Physical Address Extension. */
475	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
476	/** Bit 7 - MCE - Machine Check Exception. */
477	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
478	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
479	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
480	/** Bit 9 - APIC - APIC On-Chip. */
481	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
482	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
483	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
484	/** Bit 12 - MTRR - Memory Type Range Registers. */
485	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
486	/** Bit 13 - PGE - PTE Global Bit. */
487	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
488	/** Bit 14 - MCA - Machine Check Architecture. */
489	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
490	/** Bit 15 - CMOV - Conditional Move Instructions. */
491	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
492	/** Bit 16 - PAT - Page Attribute Table. */
493	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
494	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
495	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
496	/** Bit 18 - PSN - Processor Serial Number. */
497	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
498	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
499	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
500	/** Bit 21 - DS - Debug Store. */
501	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
502	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
503	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
504	/** Bit 23 - MMX - Intel MMX Technology. */
505	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
506	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
507	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
508	/** Bit 25 - SSE - SSE Support. */
509	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
510	/** Bit 26 - SSE2 - SSE2 Support. */
511	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
512	/** Bit 27 - SS - Self Snoop. */
513	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
514	/** Bit 28 - HTT - Hyper-Threading Technology. */
515	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
516	/** Bit 29 - TM - Therm. Monitor. */
517	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
518	/** Bit 31 - PBE - Pending Break Enabled. */
519	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
520	/** @} */
521
522	/** @name CPUID mwait/monitor information.
523	* CPUID query with EAX=5.
524	* @{
525	*/
526	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
527	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
528	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
529	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
530	/** @} */
531
532
533	/** @name CPUID Extended Feature information.
534	* CPUID query with EAX=0x80000001.
535	* @{
536	*/
537	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
538	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
539
540	/** EDX Bit 11 - SYSCALL/SYSRET. */
541	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
542	/** EDX Bit 20 - No-Execute/Execute-Disable. */
543	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
544	/** EDX Bit 26 - 1 GB large page. */
545	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
546	/** EDX Bit 27 - RDTSCP. */
547	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
548	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
549	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
550	/** @}*/
551
552	/** @name CPUID AMD Feature information.
553	* CPUID query with EAX=0x80000001.
554	* @{
555	*/
556	/** Bit 0 - FPU - x87 FPU on Chip. */
557	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
558	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
559	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
560	/** Bit 2 - DE - Debugging extensions. */
561	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
562	/** Bit 3 - PSE - Page Size Extension. */
563	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
564	/** Bit 4 - TSC - Time Stamp Counter. */
565	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
566	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
567	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
568	/** Bit 6 - PAE - Physical Address Extension. */
569	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
570	/** Bit 7 - MCE - Machine Check Exception. */
571	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
572	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
573	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
574	/** Bit 9 - APIC - APIC On-Chip. */
575	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
576	/** Bit 12 - MTRR - Memory Type Range Registers. */
577	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
578	/** Bit 13 - PGE - PTE Global Bit. */
579	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
580	/** Bit 14 - MCA - Machine Check Architecture. */
581	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
582	/** Bit 15 - CMOV - Conditional Move Instructions. */
583	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
584	/** Bit 16 - PAT - Page Attribute Table. */
585	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
586	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
587	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
588	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
589	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
590	/** Bit 23 - MMX - Intel MMX Technology. */
591	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
592	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
593	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
594	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
595	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
596	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
597	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
598	/** Bit 31 - 3DNOW - AMD 3DNow. */
599	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
600
601	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
602	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
603	/** Bit 2 - SVM - AMD VM extensions. */
604	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
605	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
606	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
607	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
608	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
609	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
610	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
611	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
612	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
613	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
614	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
615	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
616	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
617	/** Bit 9 - OSVW - AMD OS visible workaround. */
618	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
619	/** Bit 10 - IBS - Instruct based sampling. */
620	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
621	/** Bit 11 - SSE5 - SSE5 instruction support. */
622	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
623	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
624	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
625	/** Bit 13 - WDT - AMD Watchdog timer support. */
626	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
627
628	/** @} */
629
630
631	/** @name CPUID AMD Feature information.
632	* CPUID query with EAX=0x80000007.
633	* @{
634	*/
635	/** Bit 0 - TS - Temperature Sensor. */
636	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
637	/** Bit 1 - FID - Frequency ID Control. */
638	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
639	/** Bit 2 - VID - Voltage ID Control. */
640	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
641	/** Bit 3 - TTP - THERMTRIP. */
642	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
643	/** Bit 4 - TM - Hardware Thermal Control. */
644	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
645	/** Bit 5 - STC - Software Thermal Control. */
646	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
647	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
648	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
649	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
650	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
651	/** Bit 8 - TSCINVAR - TSC Invariant. */
652	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
653	/** @} */
654
655
656	/** @name CR0
657	* @{ */
658	/** Bit 0 - PE - Protection Enabled */
659	#define X86_CR0_PE RT_BIT(0)
660	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
661	/** Bit 1 - MP - Monitor Coprocessor */
662	#define X86_CR0_MP RT_BIT(1)
663	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
664	/** Bit 2 - EM - Emulation. */
665	#define X86_CR0_EM RT_BIT(2)
666	#define X86_CR0_EMULATE_FPU RT_BIT(2)
667	/** Bit 3 - TS - Task Switch. */
668	#define X86_CR0_TS RT_BIT(3)
669	#define X86_CR0_TASK_SWITCH RT_BIT(3)
670	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
671	#define X86_CR0_ET RT_BIT(4)
672	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
673	/** Bit 5 - NE - Numeric error. */
674	#define X86_CR0_NE RT_BIT(5)
675	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
676	/** Bit 16 - WP - Write Protect. */
677	#define X86_CR0_WP RT_BIT(16)
678	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
679	/** Bit 18 - AM - Alignment Mask. */
680	#define X86_CR0_AM RT_BIT(18)
681	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
682	/** Bit 29 - NW - Not Write-though. */
683	#define X86_CR0_NW RT_BIT(29)
684	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
685	/** Bit 30 - WP - Cache Disable. */
686	#define X86_CR0_CD RT_BIT(30)
687	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
688	/** Bit 31 - PG - Paging. */
689	#define X86_CR0_PG RT_BIT(31)
690	#define X86_CR0_PAGING RT_BIT(31)
691	/** @} */
692
693
694	/** @name CR3
695	* @{ */
696	/** Bit 3 - PWT - Page-level Writes Transparent. */
697	#define X86_CR3_PWT RT_BIT(3)
698	/** Bit 4 - PCD - Page-level Cache Disable. */
699	#define X86_CR3_PCD RT_BIT(4)
700	/** Bits 12-31 - - Page directory page number. */
701	#define X86_CR3_PAGE_MASK (0xfffff000)
702	/** Bits 5-31 - - PAE Page directory page number. */
703	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
704	/** Bits 12-51 - - AMD64 Page directory page number. */
705	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
706	/** @} */
707
708
709	/** @name CR4
710	* @{ */
711	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
712	#define X86_CR4_VME RT_BIT(0)
713	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
714	#define X86_CR4_PVI RT_BIT(1)
715	/** Bit 2 - TSD - Time Stamp Disable. */
716	#define X86_CR4_TSD RT_BIT(2)
717	/** Bit 3 - DE - Debugging Extensions. */
718	#define X86_CR4_DE RT_BIT(3)
719	/** Bit 4 - PSE - Page Size Extension. */
720	#define X86_CR4_PSE RT_BIT(4)
721	/** Bit 5 - PAE - Physical Address Extension. */
722	#define X86_CR4_PAE RT_BIT(5)
723	/** Bit 6 - MCE - Machine-Check Enable. */
724	#define X86_CR4_MCE RT_BIT(6)
725	/** Bit 7 - PGE - Page Global Enable. */
726	#define X86_CR4_PGE RT_BIT(7)
727	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
728	#define X86_CR4_PCE RT_BIT(8)
729	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
730	#define X86_CR4_OSFSXR RT_BIT(9)
731	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
732	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
733	/** Bit 13 - VMXE - VMX mode is enabled. */
734	#define X86_CR4_VMXE RT_BIT(13)
735	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
736	#define X86_CR4_SMXE RT_BIT(14)
737	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
738	#define X86_CR4_PCIDE RT_BIT(17)
739	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
740	* extended states. */
741	#define X86_CR4_OSXSAVE RT_BIT(18)
742	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
743	#define X86_CR4_SMEP RT_BIT(20)
744	/** @} */
745
746
747	/** @name DR6
748	* @{ */
749	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
750	#define X86_DR6_B0 RT_BIT(0)
751	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
752	#define X86_DR6_B1 RT_BIT(1)
753	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
754	#define X86_DR6_B2 RT_BIT(2)
755	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
756	#define X86_DR6_B3 RT_BIT(3)
757	/** Mask of all the Bx bits. */
758	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
759	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
760	#define X86_DR6_BD RT_BIT(13)
761	/** Bit 14 - BS - Single step */
762	#define X86_DR6_BS RT_BIT(14)
763	/** Bit 15 - BT - Task switch. (TSS T bit.) */
764	#define X86_DR6_BT RT_BIT(15)
765	/** Value of DR6 after powerup/reset. */
766	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
767	/** Bits which must be 1s in DR6. */
768	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
769	/** Bits which must be 0s in DR6. */
770	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
771	/** Bits which must be 0s on writes to DR6. */
772	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
773	/** @} */
774
775	/** Get the DR6.Bx bit for a the given breakpoint. */
776	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
777
778
779	/** @name DR7
780	* @{ */
781	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
782	#define X86_DR7_L0 RT_BIT(0)
783	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
784	#define X86_DR7_G0 RT_BIT(1)
785	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
786	#define X86_DR7_L1 RT_BIT(2)
787	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
788	#define X86_DR7_G1 RT_BIT(3)
789	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
790	#define X86_DR7_L2 RT_BIT(4)
791	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
792	#define X86_DR7_G2 RT_BIT(5)
793	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
794	#define X86_DR7_L3 RT_BIT(6)
795	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
796	#define X86_DR7_G3 RT_BIT(7)
797	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
798	#define X86_DR7_LE RT_BIT(8)
799	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
800	#define X86_DR7_GE RT_BIT(9)
801
802	/** L0, L1, L2, and L3. */
803	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
804	/** L0, L1, L2, and L3. */
805	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
806
807	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
808	* any DR register is accessed. */
809	#define X86_DR7_GD RT_BIT(13)
810	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
811	#define X86_DR7_RW0_MASK (3 << 16)
812	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
813	#define X86_DR7_LEN0_MASK (3 << 18)
814	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
815	#define X86_DR7_RW1_MASK (3 << 20)
816	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
817	#define X86_DR7_LEN1_MASK (3 << 22)
818	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
819	#define X86_DR7_RW2_MASK (3 << 24)
820	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
821	#define X86_DR7_LEN2_MASK (3 << 26)
822	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
823	#define X86_DR7_RW3_MASK (3 << 28)
824	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
825	#define X86_DR7_LEN3_MASK (3 << 30)
826
827	/** Bits which reads as 1s. */
828	#define X86_DR7_RA1_MASK (RT_BIT(10))
829	/** Bits which reads as zeros. */
830	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
831	/** Bits which must be 0s when writing to DR7. */
832	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
833
834	/** Calcs the L bit of Nth breakpoint.
835	* @param iBp The breakpoint number [0..3].
836	*/
837	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
838
839	/** Calcs the G bit of Nth breakpoint.
840	* @param iBp The breakpoint number [0..3].
841	*/
842	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
843
844	/** Calcs the L and G bits of Nth breakpoint.
845	* @param iBp The breakpoint number [0..3].
846	*/
847	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
848
849	/** @name Read/Write values.
850	* @{ */
851	/** Break on instruction fetch only. */
852	#define X86_DR7_RW_EO 0U
853	/** Break on write only. */
854	#define X86_DR7_RW_WO 1U
855	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
856	#define X86_DR7_RW_IO 2U
857	/** Break on read or write (but not instruction fetches). */
858	#define X86_DR7_RW_RW 3U
859	/** @} */
860
861	/** Shifts a X86_DR7_RW_* value to its right place.
862	* @param iBp The breakpoint number [0..3].
863	* @param fRw One of the X86_DR7_RW_* value.
864	*/
865	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
866
867	/** Fetch the the R/Wx bits for a given breakpoint (so it can be compared with
868	* one of the X86_DR7_RW_XXX constants).
869	*
870	* @returns X86_DR7_RW_XXX
871	* @param uDR7 DR7 value
872	* @param iBp The breakpoint number [0..3].
873	*/
874	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
875
876	/** R/W0, R/W1, R/W2, and R/W3. */
877	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
878
879	/** Checks if there are any I/O breakpoint types configured in the RW
880	* registers. Does NOT check if these are enabled, sorry. */
881	#define X86_DR7_ANY_RW_IO(uDR7) \
882	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
883	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
884	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
885	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
886	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
887	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
888	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
889	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
890	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
891	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
892	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
893
894	/** @name Length values.
895	* @{ */
896	#define X86_DR7_LEN_BYTE 0U
897	#define X86_DR7_LEN_WORD 1U
898	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
899	#define X86_DR7_LEN_DWORD 3U
900	/** @} */
901
902	/** Shifts a X86_DR7_LEN_* value to its right place.
903	* @param iBp The breakpoint number [0..3].
904	* @param cb One of the X86_DR7_LEN_* values.
905	*/
906	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
907
908	/** Fetch the breakpoint length bits from the DR7 value.
909	* @param uDR7 DR7 value
910	* @param iBp The breakpoint number [0..3].
911	*/
912	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
913
914	/** Mask used to check if any breakpoints are enabled. */
915	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
916
917	/** LEN0, LEN1, LEN2, and LEN3. */
918	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
919	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
920	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
921
922	/** Value of DR7 after powerup/reset. */
923	#define X86_DR7_INIT_VAL 0x400
924	/** @} */
925
926
927	/** @name Machine Specific Registers
928	* @{
929	*/
930	/** Machine check address register (P5). */
931	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
932	/** Machine check type register (P5). */
933	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
934	/** Time Stamp Counter. */
935	#define MSR_IA32_TSC 0x10
936	#define MSR_IA32_CESR UINT32_C(0x00000011)
937	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
938	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
939
940	#define MSR_IA32_PLATFORM_ID 0x17
941
942	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
943	# define MSR_IA32_APICBASE 0x1b
944	/** Local APIC enabled. */
945	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
946	/** X2APIC enabled (requires the EN bit to be set). */
947	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
948	/** The processor is the boot strap processor (BSP). */
949	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
950	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
951	* width. */
952	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
953	#endif
954
955	/** Undocumented intel MSR for reporting thread and core counts.
956	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
957	* first 16 bits is the thread count. The next 16 bits the core count, except
958	* on Westmere where it seems it's only the next 4 bits for some reason. */
959	#define MSR_CORE_THREAD_COUNT 0x35
960
961	/** CPU Feature control. */
962	#define MSR_IA32_FEATURE_CONTROL 0x3A
963	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
964	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
965	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
966
967	/** BIOS update trigger (microcode update). */
968	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
969
970	/** BIOS update signature (microcode). */
971	#define MSR_IA32_BIOS_SIGN_ID 0x8B
972
973	/** General performance counter no. 0. */
974	#define MSR_IA32_PMC0 0xC1
975	/** General performance counter no. 1. */
976	#define MSR_IA32_PMC1 0xC2
977	/** General performance counter no. 2. */
978	#define MSR_IA32_PMC2 0xC3
979	/** General performance counter no. 3. */
980	#define MSR_IA32_PMC3 0xC4
981
982	/** Nehalem power control. */
983	#define MSR_IA32_PLATFORM_INFO 0xCE
984
985	/** Get FSB clock status (Intel-specific). */
986	#define MSR_IA32_FSB_CLOCK_STS 0xCD
987
988	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
989	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
990
991	/** C0 Maximum Frequency Clock Count */
992	#define MSR_IA32_MPERF 0xE7
993	/** C0 Actual Frequency Clock Count */
994	#define MSR_IA32_APERF 0xE8
995
996	/** MTRR Capabilities. */
997	#define MSR_IA32_MTRR_CAP 0xFE
998
999	/** Cache control/info. */
1000	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1001
1002	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1003	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1004	* R0 SS == CS + 8
1005	* R3 CS == CS + 16
1006	* R3 SS == CS + 24
1007	*/
1008	#define MSR_IA32_SYSENTER_CS 0x174
1009	/** SYSENTER_ESP - the R0 ESP. */
1010	#define MSR_IA32_SYSENTER_ESP 0x175
1011	/** SYSENTER_EIP - the R0 EIP. */
1012	#define MSR_IA32_SYSENTER_EIP 0x176
1013	#endif
1014
1015	/** Machine Check Global Capabilities Register. */
1016	#define MSR_IA32_MCG_CAP 0x179
1017	/** Machine Check Global Status Register. */
1018	#define MSR_IA32_MCG_STATUS 0x17A
1019	/** Machine Check Global Control Register. */
1020	#define MSR_IA32_MCG_CTRL 0x17B
1021
1022	/** Page Attribute Table. */
1023	#define MSR_IA32_CR_PAT 0x277
1024
1025	/** Performance counter MSRs. (Intel only) */
1026	#define MSR_IA32_PERFEVTSEL0 0x186
1027	#define MSR_IA32_PERFEVTSEL1 0x187
1028	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1029	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1030	* holds a ratio that Apple takes for TSC granularity.
1031	*
1032	* @note This MSR conflics the P4 MSR_MCG_R12 register. */
1033	#define MSR_FLEX_RATIO 0x194
1034	/** Performance state value and starting with Intel core more.
1035	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1036	#define MSR_IA32_PERF_STATUS 0x198
1037	#define MSR_IA32_PERF_CTL 0x199
1038	#define MSR_IA32_THERM_STATUS 0x19c
1039
1040	/** Enable misc. processor features (R/W). */
1041	#define MSR_IA32_MISC_ENABLE 0x1A0
1042	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1043	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1044	/** Automatic Thermal Control Circuit Enable (R/W). */
1045	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1046	/** Performance Monitoring Available (R). */
1047	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1048	/** Branch Trace Storage Unavailable (R/O). */
1049	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1050	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1051	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1052	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1053	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1054	/** If MONITOR/MWAIT is supported (R/W). */
1055	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1056	/** Limit CPUID Maxval to 3 leafs (R/W). */
1057	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1058	/** When set to 1, xTPR messages are disabled (R/W). */
1059	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1060	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1061	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1062
1063	/** Trace/Profile Resource Control (R/W) */
1064	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1065	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1066	* related Xeons. */
1067	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1068	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1069	* @{ */
1070	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1071	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1072	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1073	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1074	/** @} */
1075
1076
1077	#define IA32_MTRR_PHYSBASE0 0x200
1078	#define IA32_MTRR_PHYSMASK0 0x201
1079	#define IA32_MTRR_PHYSBASE1 0x202
1080	#define IA32_MTRR_PHYSMASK1 0x203
1081	#define IA32_MTRR_PHYSBASE2 0x204
1082	#define IA32_MTRR_PHYSMASK2 0x205
1083	#define IA32_MTRR_PHYSBASE3 0x206
1084	#define IA32_MTRR_PHYSMASK3 0x207
1085	#define IA32_MTRR_PHYSBASE4 0x208
1086	#define IA32_MTRR_PHYSMASK4 0x209
1087	#define IA32_MTRR_PHYSBASE5 0x20a
1088	#define IA32_MTRR_PHYSMASK5 0x20b
1089	#define IA32_MTRR_PHYSBASE6 0x20c
1090	#define IA32_MTRR_PHYSMASK6 0x20d
1091	#define IA32_MTRR_PHYSBASE7 0x20e
1092	#define IA32_MTRR_PHYSMASK7 0x20f
1093	#define IA32_MTRR_PHYSBASE8 0x210
1094	#define IA32_MTRR_PHYSMASK8 0x211
1095	#define IA32_MTRR_PHYSBASE9 0x212
1096	#define IA32_MTRR_PHYSMASK9 0x213
1097
1098	/** Fixed range MTRRs.
1099	* @{ */
1100	#define IA32_MTRR_FIX64K_00000 0x250
1101	#define IA32_MTRR_FIX16K_80000 0x258
1102	#define IA32_MTRR_FIX16K_A0000 0x259
1103	#define IA32_MTRR_FIX4K_C0000 0x268
1104	#define IA32_MTRR_FIX4K_C8000 0x269
1105	#define IA32_MTRR_FIX4K_D0000 0x26a
1106	#define IA32_MTRR_FIX4K_D8000 0x26b
1107	#define IA32_MTRR_FIX4K_E0000 0x26c
1108	#define IA32_MTRR_FIX4K_E8000 0x26d
1109	#define IA32_MTRR_FIX4K_F0000 0x26e
1110	#define IA32_MTRR_FIX4K_F8000 0x26f
1111	/** @} */
1112
1113	/** MTRR Default Range. */
1114	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1115
1116	#define MSR_IA32_MC0_CTL 0x400
1117	#define MSR_IA32_MC0_STATUS 0x401
1118
1119	/** Basic VMX information. */
1120	#define MSR_IA32_VMX_BASIC_INFO 0x480
1121	/** Allowed settings for pin-based VM execution controls */
1122	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1123	/** Allowed settings for proc-based VM execution controls */
1124	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1125	/** Allowed settings for the VMX exit controls. */
1126	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1127	/** Allowed settings for the VMX entry controls. */
1128	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1129	/** Misc VMX info. */
1130	#define MSR_IA32_VMX_MISC 0x485
1131	/** Fixed cleared bits in CR0. */
1132	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1133	/** Fixed set bits in CR0. */
1134	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1135	/** Fixed cleared bits in CR4. */
1136	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1137	/** Fixed set bits in CR4. */
1138	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1139	/** Information for enumerating fields in the VMCS. */
1140	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1141	/** Allowed settings for the VM-functions controls. */
1142	#define MSR_IA32_VMX_VMFUNC 0x491
1143	/** Allowed settings for secondary proc-based VM execution controls */
1144	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1145	/** EPT capabilities. */
1146	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1147	/** DS Save Area (R/W). */
1148	#define MSR_IA32_DS_AREA 0x600
1149	/** Running Average Power Limit (RAPL) power units. */
1150	#define MSR_RAPL_POWER_UNIT 0x606
1151	/** X2APIC MSR ranges. */
1152	#define MSR_IA32_X2APIC_START 0x800
1153	#define MSR_IA32_X2APIC_TPR 0x808
1154	#define MSR_IA32_X2APIC_END 0xBFF
1155
1156	/** K6 EFER - Extended Feature Enable Register. */
1157	#define MSR_K6_EFER UINT32_C(0xc0000080)
1158	/** @todo document EFER */
1159	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1160	#define MSR_K6_EFER_SCE RT_BIT(0)
1161	/** Bit 8 - LME - Long mode enabled. (R/W) */
1162	#define MSR_K6_EFER_LME RT_BIT(8)
1163	/** Bit 10 - LMA - Long mode active. (R) */
1164	#define MSR_K6_EFER_LMA RT_BIT(10)
1165	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1166	#define MSR_K6_EFER_NXE RT_BIT(11)
1167	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1168	#define MSR_K6_EFER_SVME RT_BIT(12)
1169	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1170	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1171	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1172	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1173	/** K6 STAR - SYSCALL/RET targets. */
1174	#define MSR_K6_STAR UINT32_C(0xc0000081)
1175	/** Shift value for getting the SYSRET CS and SS value. */
1176	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1177	/** Shift value for getting the SYSCALL CS and SS value. */
1178	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1179	/** Selector mask for use after shifting. */
1180	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1181	/** The mask which give the SYSCALL EIP. */
1182	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1183	/** K6 WHCR - Write Handling Control Register. */
1184	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1185	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1186	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1187	/** K6 PSOR - Processor State Observability Register. */
1188	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1189	/** K6 PFIR - Page Flush/Invalidate Register. */
1190	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1191
1192	/** Performance counter MSRs. (AMD only) */
1193	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1194	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1195	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1196	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1197	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1198	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1199	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1200	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1201
1202	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1203	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1204	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1205	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1206	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1207	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1208	/** K8 FS.base - The 64-bit base FS register. */
1209	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1210	/** K8 GS.base - The 64-bit base GS register. */
1211	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1212	/** K8 KernelGSbase - Used with SWAPGS. */
1213	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1214	/** K8 TSC_AUX - Used with RDTSCP. */
1215	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1216	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1217	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1218	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1219	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1220	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1221	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1222	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1223	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1224	/** North bridge config? See BIOS & Kernel dev guides for
1225	* details. */
1226	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1227
1228	/** Hypertransport interrupt pending register.
1229	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1230	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1231	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1232	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1233
1234	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1235	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1236	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1237	* host state during world switch. */
1238	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1239
1240	/** @} */
1241
1242
1243	/** @name Page Table / Directory / Directory Pointers / L4.
1244	* @{
1245	*/
1246
1247	/** Page table/directory entry as an unsigned integer. */
1248	typedef uint32_t X86PGUINT;
1249	/** Pointer to a page table/directory table entry as an unsigned integer. */
1250	typedef X86PGUINT *PX86PGUINT;
1251	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1252	typedef X86PGUINT const *PCX86PGUINT;
1253
1254	/** Number of entries in a 32-bit PT/PD. */
1255	#define X86_PG_ENTRIES 1024
1256
1257
1258	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1259	typedef uint64_t X86PGPAEUINT;
1260	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1261	typedef X86PGPAEUINT *PX86PGPAEUINT;
1262	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1263	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1264
1265	/** Number of entries in a PAE PT/PD. */
1266	#define X86_PG_PAE_ENTRIES 512
1267	/** Number of entries in a PAE PDPT. */
1268	#define X86_PG_PAE_PDPE_ENTRIES 4
1269
1270	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1271	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1272	/** Number of entries in an AMD64 PDPT.
1273	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1274	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1275
1276	/** The size of a 4KB page. */
1277	#define X86_PAGE_4K_SIZE _4K
1278	/** The page shift of a 4KB page. */
1279	#define X86_PAGE_4K_SHIFT 12
1280	/** The 4KB page offset mask. */
1281	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1282	/** The 4KB page base mask for virtual addresses. */
1283	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1284	/** The 4KB page base mask for virtual addresses - 32bit version. */
1285	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1286
1287	/** The size of a 2MB page. */
1288	#define X86_PAGE_2M_SIZE _2M
1289	/** The page shift of a 2MB page. */
1290	#define X86_PAGE_2M_SHIFT 21
1291	/** The 2MB page offset mask. */
1292	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1293	/** The 2MB page base mask for virtual addresses. */
1294	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1295	/** The 2MB page base mask for virtual addresses - 32bit version. */
1296	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1297
1298	/** The size of a 4MB page. */
1299	#define X86_PAGE_4M_SIZE _4M
1300	/** The page shift of a 4MB page. */
1301	#define X86_PAGE_4M_SHIFT 22
1302	/** The 4MB page offset mask. */
1303	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1304	/** The 4MB page base mask for virtual addresses. */
1305	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1306	/** The 4MB page base mask for virtual addresses - 32bit version. */
1307	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1308
1309	/**
1310	* Check if the given address is canonical.
1311	*/
1312	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1313
1314
1315	/** @name Page Table Entry
1316	* @{
1317	*/
1318	/** Bit 0 - P - Present bit. */
1319	#define X86_PTE_BIT_P 0
1320	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1321	#define X86_PTE_BIT_RW 1
1322	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1323	#define X86_PTE_BIT_US 2
1324	/** Bit 3 - PWT - Page level write thru bit. */
1325	#define X86_PTE_BIT_PWT 3
1326	/** Bit 4 - PCD - Page level cache disable bit. */
1327	#define X86_PTE_BIT_PCD 4
1328	/** Bit 5 - A - Access bit. */
1329	#define X86_PTE_BIT_A 5
1330	/** Bit 6 - D - Dirty bit. */
1331	#define X86_PTE_BIT_D 6
1332	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1333	#define X86_PTE_BIT_PAT 7
1334	/** Bit 8 - G - Global flag. */
1335	#define X86_PTE_BIT_G 8
1336
1337	/** Bit 0 - P - Present bit mask. */
1338	#define X86_PTE_P RT_BIT(0)
1339	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1340	#define X86_PTE_RW RT_BIT(1)
1341	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1342	#define X86_PTE_US RT_BIT(2)
1343	/** Bit 3 - PWT - Page level write thru bit mask. */
1344	#define X86_PTE_PWT RT_BIT(3)
1345	/** Bit 4 - PCD - Page level cache disable bit mask. */
1346	#define X86_PTE_PCD RT_BIT(4)
1347	/** Bit 5 - A - Access bit mask. */
1348	#define X86_PTE_A RT_BIT(5)
1349	/** Bit 6 - D - Dirty bit mask. */
1350	#define X86_PTE_D RT_BIT(6)
1351	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1352	#define X86_PTE_PAT RT_BIT(7)
1353	/** Bit 8 - G - Global bit mask. */
1354	#define X86_PTE_G RT_BIT(8)
1355
1356	/** Bits 9-11 - - Available for use to system software. */
1357	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1358	/** Bits 12-31 - - Physical Page number of the next level. */
1359	#define X86_PTE_PG_MASK ( 0xfffff000 )
1360
1361	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1362	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1363	/** Bits 63 - NX - PAE/LM - No execution flag. */
1364	#define X86_PTE_PAE_NX RT_BIT_64(63)
1365	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1366	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1367	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1368	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1369	/** No bits - - LM - MBZ bits when NX is active. */
1370	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1371	/** Bits 63 - - LM - MBZ bits when no NX. */
1372	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1373
1374	/**
1375	* Page table entry.
1376	*/
1377	typedef struct X86PTEBITS
1378	{
1379	/** Flags whether(=1) or not the page is present. */
1380	unsigned u1Present : 1;
1381	/** Read(=0) / Write(=1) flag. */
1382	unsigned u1Write : 1;
1383	/** User(=1) / Supervisor (=0) flag. */
1384	unsigned u1User : 1;
1385	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1386	unsigned u1WriteThru : 1;
1387	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1388	unsigned u1CacheDisable : 1;
1389	/** Accessed flag.
1390	* Indicates that the page have been read or written to. */
1391	unsigned u1Accessed : 1;
1392	/** Dirty flag.
1393	* Indicates that the page has been written to. */
1394	unsigned u1Dirty : 1;
1395	/** Reserved / If PAT enabled, bit 2 of the index. */
1396	unsigned u1PAT : 1;
1397	/** Global flag. (Ignored in all but final level.) */
1398	unsigned u1Global : 1;
1399	/** Available for use to system software. */
1400	unsigned u3Available : 3;
1401	/** Physical Page number of the next level. */
1402	unsigned u20PageNo : 20;
1403	} X86PTEBITS;
1404	/** Pointer to a page table entry. */
1405	typedef X86PTEBITS *PX86PTEBITS;
1406	/** Pointer to a const page table entry. */
1407	typedef const X86PTEBITS *PCX86PTEBITS;
1408
1409	/**
1410	* Page table entry.
1411	*/
1412	typedef union X86PTE
1413	{
1414	/** Unsigned integer view */
1415	X86PGUINT u;
1416	/** Bit field view. */
1417	X86PTEBITS n;
1418	/** 32-bit view. */
1419	uint32_t au32[1];
1420	/** 16-bit view. */
1421	uint16_t au16[2];
1422	/** 8-bit view. */
1423	uint8_t au8[4];
1424	} X86PTE;
1425	/** Pointer to a page table entry. */
1426	typedef X86PTE *PX86PTE;
1427	/** Pointer to a const page table entry. */
1428	typedef const X86PTE *PCX86PTE;
1429
1430
1431	/**
1432	* PAE page table entry.
1433	*/
1434	typedef struct X86PTEPAEBITS
1435	{
1436	/** Flags whether(=1) or not the page is present. */
1437	uint32_t u1Present : 1;
1438	/** Read(=0) / Write(=1) flag. */
1439	uint32_t u1Write : 1;
1440	/** User(=1) / Supervisor(=0) flag. */
1441	uint32_t u1User : 1;
1442	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1443	uint32_t u1WriteThru : 1;
1444	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1445	uint32_t u1CacheDisable : 1;
1446	/** Accessed flag.
1447	* Indicates that the page have been read or written to. */
1448	uint32_t u1Accessed : 1;
1449	/** Dirty flag.
1450	* Indicates that the page has been written to. */
1451	uint32_t u1Dirty : 1;
1452	/** Reserved / If PAT enabled, bit 2 of the index. */
1453	uint32_t u1PAT : 1;
1454	/** Global flag. (Ignored in all but final level.) */
1455	uint32_t u1Global : 1;
1456	/** Available for use to system software. */
1457	uint32_t u3Available : 3;
1458	/** Physical Page number of the next level - Low Part. Don't use this. */
1459	uint32_t u20PageNoLow : 20;
1460	/** Physical Page number of the next level - High Part. Don't use this. */
1461	uint32_t u20PageNoHigh : 20;
1462	/** MBZ bits */
1463	uint32_t u11Reserved : 11;
1464	/** No Execute flag. */
1465	uint32_t u1NoExecute : 1;
1466	} X86PTEPAEBITS;
1467	/** Pointer to a page table entry. */
1468	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1469	/** Pointer to a page table entry. */
1470	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1471
1472	/**
1473	* PAE Page table entry.
1474	*/
1475	typedef union X86PTEPAE
1476	{
1477	/** Unsigned integer view */
1478	X86PGPAEUINT u;
1479	/** Bit field view. */
1480	X86PTEPAEBITS n;
1481	/** 32-bit view. */
1482	uint32_t au32[2];
1483	/** 16-bit view. */
1484	uint16_t au16[4];
1485	/** 8-bit view. */
1486	uint8_t au8[8];
1487	} X86PTEPAE;
1488	/** Pointer to a PAE page table entry. */
1489	typedef X86PTEPAE *PX86PTEPAE;
1490	/** Pointer to a const PAE page table entry. */
1491	typedef const X86PTEPAE *PCX86PTEPAE;
1492	/** @} */
1493
1494	/**
1495	* Page table.
1496	*/
1497	typedef struct X86PT
1498	{
1499	/** PTE Array. */
1500	X86PTE a[X86_PG_ENTRIES];
1501	} X86PT;
1502	/** Pointer to a page table. */
1503	typedef X86PT *PX86PT;
1504	/** Pointer to a const page table. */
1505	typedef const X86PT *PCX86PT;
1506
1507	/** The page shift to get the PT index. */
1508	#define X86_PT_SHIFT 12
1509	/** The PT index mask (apply to a shifted page address). */
1510	#define X86_PT_MASK 0x3ff
1511
1512
1513	/**
1514	* Page directory.
1515	*/
1516	typedef struct X86PTPAE
1517	{
1518	/** PTE Array. */
1519	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1520	} X86PTPAE;
1521	/** Pointer to a page table. */
1522	typedef X86PTPAE *PX86PTPAE;
1523	/** Pointer to a const page table. */
1524	typedef const X86PTPAE *PCX86PTPAE;
1525
1526	/** The page shift to get the PA PTE index. */
1527	#define X86_PT_PAE_SHIFT 12
1528	/** The PAE PT index mask (apply to a shifted page address). */
1529	#define X86_PT_PAE_MASK 0x1ff
1530
1531
1532	/** @name 4KB Page Directory Entry
1533	* @{
1534	*/
1535	/** Bit 0 - P - Present bit. */
1536	#define X86_PDE_P RT_BIT(0)
1537	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1538	#define X86_PDE_RW RT_BIT(1)
1539	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1540	#define X86_PDE_US RT_BIT(2)
1541	/** Bit 3 - PWT - Page level write thru bit. */
1542	#define X86_PDE_PWT RT_BIT(3)
1543	/** Bit 4 - PCD - Page level cache disable bit. */
1544	#define X86_PDE_PCD RT_BIT(4)
1545	/** Bit 5 - A - Access bit. */
1546	#define X86_PDE_A RT_BIT(5)
1547	/** Bit 7 - PS - Page size attribute.
1548	* Clear mean 4KB pages, set means large pages (2/4MB). */
1549	#define X86_PDE_PS RT_BIT(7)
1550	/** Bits 9-11 - - Available for use to system software. */
1551	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1552	/** Bits 12-31 - - Physical Page number of the next level. */
1553	#define X86_PDE_PG_MASK ( 0xfffff000 )
1554
1555	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1556	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1557	/** Bits 63 - NX - PAE/LM - No execution flag. */
1558	#define X86_PDE_PAE_NX RT_BIT_64(63)
1559	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1560	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1561	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1562	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1563	/** Bit 7 - - LM - MBZ bits when NX is active. */
1564	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1565	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1566	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1567
1568	/**
1569	* Page directory entry.
1570	*/
1571	typedef struct X86PDEBITS
1572	{
1573	/** Flags whether(=1) or not the page is present. */
1574	unsigned u1Present : 1;
1575	/** Read(=0) / Write(=1) flag. */
1576	unsigned u1Write : 1;
1577	/** User(=1) / Supervisor (=0) flag. */
1578	unsigned u1User : 1;
1579	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1580	unsigned u1WriteThru : 1;
1581	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1582	unsigned u1CacheDisable : 1;
1583	/** Accessed flag.
1584	* Indicates that the page has been read or written to. */
1585	unsigned u1Accessed : 1;
1586	/** Reserved / Ignored (dirty bit). */
1587	unsigned u1Reserved0 : 1;
1588	/** Size bit if PSE is enabled - in any event it's 0. */
1589	unsigned u1Size : 1;
1590	/** Reserved / Ignored (global bit). */
1591	unsigned u1Reserved1 : 1;
1592	/** Available for use to system software. */
1593	unsigned u3Available : 3;
1594	/** Physical Page number of the next level. */
1595	unsigned u20PageNo : 20;
1596	} X86PDEBITS;
1597	/** Pointer to a page directory entry. */
1598	typedef X86PDEBITS *PX86PDEBITS;
1599	/** Pointer to a const page directory entry. */
1600	typedef const X86PDEBITS *PCX86PDEBITS;
1601
1602
1603	/**
1604	* PAE page directory entry.
1605	*/
1606	typedef struct X86PDEPAEBITS
1607	{
1608	/** Flags whether(=1) or not the page is present. */
1609	uint32_t u1Present : 1;
1610	/** Read(=0) / Write(=1) flag. */
1611	uint32_t u1Write : 1;
1612	/** User(=1) / Supervisor (=0) flag. */
1613	uint32_t u1User : 1;
1614	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1615	uint32_t u1WriteThru : 1;
1616	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1617	uint32_t u1CacheDisable : 1;
1618	/** Accessed flag.
1619	* Indicates that the page has been read or written to. */
1620	uint32_t u1Accessed : 1;
1621	/** Reserved / Ignored (dirty bit). */
1622	uint32_t u1Reserved0 : 1;
1623	/** Size bit if PSE is enabled - in any event it's 0. */
1624	uint32_t u1Size : 1;
1625	/** Reserved / Ignored (global bit). / */
1626	uint32_t u1Reserved1 : 1;
1627	/** Available for use to system software. */
1628	uint32_t u3Available : 3;
1629	/** Physical Page number of the next level - Low Part. Don't use! */
1630	uint32_t u20PageNoLow : 20;
1631	/** Physical Page number of the next level - High Part. Don't use! */
1632	uint32_t u20PageNoHigh : 20;
1633	/** MBZ bits */
1634	uint32_t u11Reserved : 11;
1635	/** No Execute flag. */
1636	uint32_t u1NoExecute : 1;
1637	} X86PDEPAEBITS;
1638	/** Pointer to a page directory entry. */
1639	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1640	/** Pointer to a const page directory entry. */
1641	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1642
1643	/** @} */
1644
1645
1646	/** @name 2/4MB Page Directory Entry
1647	* @{
1648	*/
1649	/** Bit 0 - P - Present bit. */
1650	#define X86_PDE4M_P RT_BIT(0)
1651	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1652	#define X86_PDE4M_RW RT_BIT(1)
1653	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1654	#define X86_PDE4M_US RT_BIT(2)
1655	/** Bit 3 - PWT - Page level write thru bit. */
1656	#define X86_PDE4M_PWT RT_BIT(3)
1657	/** Bit 4 - PCD - Page level cache disable bit. */
1658	#define X86_PDE4M_PCD RT_BIT(4)
1659	/** Bit 5 - A - Access bit. */
1660	#define X86_PDE4M_A RT_BIT(5)
1661	/** Bit 6 - D - Dirty bit. */
1662	#define X86_PDE4M_D RT_BIT(6)
1663	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1664	#define X86_PDE4M_PS RT_BIT(7)
1665	/** Bit 8 - G - Global flag. */
1666	#define X86_PDE4M_G RT_BIT(8)
1667	/** Bits 9-11 - AVL - Available for use to system software. */
1668	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1669	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1670	#define X86_PDE4M_PAT RT_BIT(12)
1671	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1672	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1673	/** Bits 22-31 - - Physical Page number. */
1674	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1675	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1676	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1677	/** The number of bits to the high part of the page number. */
1678	#define X86_PDE4M_PG_HIGH_SHIFT 19
1679	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1680	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1681
1682	/** Bits 21-51 - - PAE/LM - Physical Page number.
1683	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1684	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1685	/** Bits 63 - NX - PAE/LM - No execution flag. */
1686	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1687	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1688	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1689	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1690	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1691	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1692	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1693	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1694	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1695
1696	/**
1697	* 4MB page directory entry.
1698	*/
1699	typedef struct X86PDE4MBITS
1700	{
1701	/** Flags whether(=1) or not the page is present. */
1702	unsigned u1Present : 1;
1703	/** Read(=0) / Write(=1) flag. */
1704	unsigned u1Write : 1;
1705	/** User(=1) / Supervisor (=0) flag. */
1706	unsigned u1User : 1;
1707	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1708	unsigned u1WriteThru : 1;
1709	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1710	unsigned u1CacheDisable : 1;
1711	/** Accessed flag.
1712	* Indicates that the page have been read or written to. */
1713	unsigned u1Accessed : 1;
1714	/** Dirty flag.
1715	* Indicates that the page has been written to. */
1716	unsigned u1Dirty : 1;
1717	/** Page size flag - always 1 for 4MB entries. */
1718	unsigned u1Size : 1;
1719	/** Global flag. */
1720	unsigned u1Global : 1;
1721	/** Available for use to system software. */
1722	unsigned u3Available : 3;
1723	/** Reserved / If PAT enabled, bit 2 of the index. */
1724	unsigned u1PAT : 1;
1725	/** Bits 32-39 of the page number on AMD64.
1726	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1727	unsigned u8PageNoHigh : 8;
1728	/** Reserved. */
1729	unsigned u1Reserved : 1;
1730	/** Physical Page number of the page. */
1731	unsigned u10PageNo : 10;
1732	} X86PDE4MBITS;
1733	/** Pointer to a page table entry. */
1734	typedef X86PDE4MBITS *PX86PDE4MBITS;
1735	/** Pointer to a const page table entry. */
1736	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1737
1738
1739	/**
1740	* 2MB PAE page directory entry.
1741	*/
1742	typedef struct X86PDE2MPAEBITS
1743	{
1744	/** Flags whether(=1) or not the page is present. */
1745	uint32_t u1Present : 1;
1746	/** Read(=0) / Write(=1) flag. */
1747	uint32_t u1Write : 1;
1748	/** User(=1) / Supervisor(=0) flag. */
1749	uint32_t u1User : 1;
1750	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1751	uint32_t u1WriteThru : 1;
1752	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1753	uint32_t u1CacheDisable : 1;
1754	/** Accessed flag.
1755	* Indicates that the page have been read or written to. */
1756	uint32_t u1Accessed : 1;
1757	/** Dirty flag.
1758	* Indicates that the page has been written to. */
1759	uint32_t u1Dirty : 1;
1760	/** Page size flag - always 1 for 2MB entries. */
1761	uint32_t u1Size : 1;
1762	/** Global flag. */
1763	uint32_t u1Global : 1;
1764	/** Available for use to system software. */
1765	uint32_t u3Available : 3;
1766	/** Reserved / If PAT enabled, bit 2 of the index. */
1767	uint32_t u1PAT : 1;
1768	/** Reserved. */
1769	uint32_t u9Reserved : 9;
1770	/** Physical Page number of the next level - Low part. Don't use! */
1771	uint32_t u10PageNoLow : 10;
1772	/** Physical Page number of the next level - High part. Don't use! */
1773	uint32_t u20PageNoHigh : 20;
1774	/** MBZ bits */
1775	uint32_t u11Reserved : 11;
1776	/** No Execute flag. */
1777	uint32_t u1NoExecute : 1;
1778	} X86PDE2MPAEBITS;
1779	/** Pointer to a 2MB PAE page table entry. */
1780	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1781	/** Pointer to a 2MB PAE page table entry. */
1782	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1783
1784	/** @} */
1785
1786	/**
1787	* Page directory entry.
1788	*/
1789	typedef union X86PDE
1790	{
1791	/** Unsigned integer view. */
1792	X86PGUINT u;
1793	/** Normal view. */
1794	X86PDEBITS n;
1795	/** 4MB view (big). */
1796	X86PDE4MBITS b;
1797	/** 8 bit unsigned integer view. */
1798	uint8_t au8[4];
1799	/** 16 bit unsigned integer view. */
1800	uint16_t au16[2];
1801	/** 32 bit unsigned integer view. */
1802	uint32_t au32[1];
1803	} X86PDE;
1804	/** Pointer to a page directory entry. */
1805	typedef X86PDE *PX86PDE;
1806	/** Pointer to a const page directory entry. */
1807	typedef const X86PDE *PCX86PDE;
1808
1809	/**
1810	* PAE page directory entry.
1811	*/
1812	typedef union X86PDEPAE
1813	{
1814	/** Unsigned integer view. */
1815	X86PGPAEUINT u;
1816	/** Normal view. */
1817	X86PDEPAEBITS n;
1818	/** 2MB page view (big). */
1819	X86PDE2MPAEBITS b;
1820	/** 8 bit unsigned integer view. */
1821	uint8_t au8[8];
1822	/** 16 bit unsigned integer view. */
1823	uint16_t au16[4];
1824	/** 32 bit unsigned integer view. */
1825	uint32_t au32[2];
1826	} X86PDEPAE;
1827	/** Pointer to a page directory entry. */
1828	typedef X86PDEPAE *PX86PDEPAE;
1829	/** Pointer to a const page directory entry. */
1830	typedef const X86PDEPAE *PCX86PDEPAE;
1831
1832	/**
1833	* Page directory.
1834	*/
1835	typedef struct X86PD
1836	{
1837	/** PDE Array. */
1838	X86PDE a[X86_PG_ENTRIES];
1839	} X86PD;
1840	/** Pointer to a page directory. */
1841	typedef X86PD *PX86PD;
1842	/** Pointer to a const page directory. */
1843	typedef const X86PD *PCX86PD;
1844
1845	/** The page shift to get the PD index. */
1846	#define X86_PD_SHIFT 22
1847	/** The PD index mask (apply to a shifted page address). */
1848	#define X86_PD_MASK 0x3ff
1849
1850
1851	/**
1852	* PAE page directory.
1853	*/
1854	typedef struct X86PDPAE
1855	{
1856	/** PDE Array. */
1857	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1858	} X86PDPAE;
1859	/** Pointer to a PAE page directory. */
1860	typedef X86PDPAE *PX86PDPAE;
1861	/** Pointer to a const PAE page directory. */
1862	typedef const X86PDPAE *PCX86PDPAE;
1863
1864	/** The page shift to get the PAE PD index. */
1865	#define X86_PD_PAE_SHIFT 21
1866	/** The PAE PD index mask (apply to a shifted page address). */
1867	#define X86_PD_PAE_MASK 0x1ff
1868
1869
1870	/** @name Page Directory Pointer Table Entry (PAE)
1871	* @{
1872	*/
1873	/** Bit 0 - P - Present bit. */
1874	#define X86_PDPE_P RT_BIT(0)
1875	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1876	#define X86_PDPE_RW RT_BIT(1)
1877	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1878	#define X86_PDPE_US RT_BIT(2)
1879	/** Bit 3 - PWT - Page level write thru bit. */
1880	#define X86_PDPE_PWT RT_BIT(3)
1881	/** Bit 4 - PCD - Page level cache disable bit. */
1882	#define X86_PDPE_PCD RT_BIT(4)
1883	/** Bit 5 - A - Access bit. Long Mode only. */
1884	#define X86_PDPE_A RT_BIT(5)
1885	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1886	#define X86_PDPE_LM_PS RT_BIT(7)
1887	/** Bits 9-11 - - Available for use to system software. */
1888	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1889	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1890	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1891	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1892	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1893	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1894	#define X86_PDPE_LM_NX RT_BIT_64(63)
1895	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1896	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1897	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1898	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1899	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1900	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1901	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1902	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1903
1904
1905	/**
1906	* Page directory pointer table entry.
1907	*/
1908	typedef struct X86PDPEBITS
1909	{
1910	/** Flags whether(=1) or not the page is present. */
1911	uint32_t u1Present : 1;
1912	/** Chunk of reserved bits. */
1913	uint32_t u2Reserved : 2;
1914	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1915	uint32_t u1WriteThru : 1;
1916	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1917	uint32_t u1CacheDisable : 1;
1918	/** Chunk of reserved bits. */
1919	uint32_t u4Reserved : 4;
1920	/** Available for use to system software. */
1921	uint32_t u3Available : 3;
1922	/** Physical Page number of the next level - Low Part. Don't use! */
1923	uint32_t u20PageNoLow : 20;
1924	/** Physical Page number of the next level - High Part. Don't use! */
1925	uint32_t u20PageNoHigh : 20;
1926	/** MBZ bits */
1927	uint32_t u12Reserved : 12;
1928	} X86PDPEBITS;
1929	/** Pointer to a page directory pointer table entry. */
1930	typedef X86PDPEBITS *PX86PTPEBITS;
1931	/** Pointer to a const page directory pointer table entry. */
1932	typedef const X86PDPEBITS *PCX86PTPEBITS;
1933
1934	/**
1935	* Page directory pointer table entry. AMD64 version
1936	*/
1937	typedef struct X86PDPEAMD64BITS
1938	{
1939	/** Flags whether(=1) or not the page is present. */
1940	uint32_t u1Present : 1;
1941	/** Read(=0) / Write(=1) flag. */
1942	uint32_t u1Write : 1;
1943	/** User(=1) / Supervisor (=0) flag. */
1944	uint32_t u1User : 1;
1945	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1946	uint32_t u1WriteThru : 1;
1947	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1948	uint32_t u1CacheDisable : 1;
1949	/** Accessed flag.
1950	* Indicates that the page have been read or written to. */
1951	uint32_t u1Accessed : 1;
1952	/** Chunk of reserved bits. */
1953	uint32_t u3Reserved : 3;
1954	/** Available for use to system software. */
1955	uint32_t u3Available : 3;
1956	/** Physical Page number of the next level - Low Part. Don't use! */
1957	uint32_t u20PageNoLow : 20;
1958	/** Physical Page number of the next level - High Part. Don't use! */
1959	uint32_t u20PageNoHigh : 20;
1960	/** MBZ bits */
1961	uint32_t u11Reserved : 11;
1962	/** No Execute flag. */
1963	uint32_t u1NoExecute : 1;
1964	} X86PDPEAMD64BITS;
1965	/** Pointer to a page directory pointer table entry. */
1966	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1967	/** Pointer to a const page directory pointer table entry. */
1968	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1969
1970	/**
1971	* Page directory pointer table entry.
1972	*/
1973	typedef union X86PDPE
1974	{
1975	/** Unsigned integer view. */
1976	X86PGPAEUINT u;
1977	/** Normal view. */
1978	X86PDPEBITS n;
1979	/** AMD64 view. */
1980	X86PDPEAMD64BITS lm;
1981	/** 8 bit unsigned integer view. */
1982	uint8_t au8[8];
1983	/** 16 bit unsigned integer view. */
1984	uint16_t au16[4];
1985	/** 32 bit unsigned integer view. */
1986	uint32_t au32[2];
1987	} X86PDPE;
1988	/** Pointer to a page directory pointer table entry. */
1989	typedef X86PDPE *PX86PDPE;
1990	/** Pointer to a const page directory pointer table entry. */
1991	typedef const X86PDPE *PCX86PDPE;
1992
1993
1994	/**
1995	* Page directory pointer table.
1996	*/
1997	typedef struct X86PDPT
1998	{
1999	/** PDE Array. */
2000	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2001	} X86PDPT;
2002	/** Pointer to a page directory pointer table. */
2003	typedef X86PDPT *PX86PDPT;
2004	/** Pointer to a const page directory pointer table. */
2005	typedef const X86PDPT *PCX86PDPT;
2006
2007	/** The page shift to get the PDPT index. */
2008	#define X86_PDPT_SHIFT 30
2009	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2010	#define X86_PDPT_MASK_PAE 0x3
2011	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2012	#define X86_PDPT_MASK_AMD64 0x1ff
2013
2014	/** @} */
2015
2016
2017	/** @name Page Map Level-4 Entry (Long Mode PAE)
2018	* @{
2019	*/
2020	/** Bit 0 - P - Present bit. */
2021	#define X86_PML4E_P RT_BIT(0)
2022	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2023	#define X86_PML4E_RW RT_BIT(1)
2024	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2025	#define X86_PML4E_US RT_BIT(2)
2026	/** Bit 3 - PWT - Page level write thru bit. */
2027	#define X86_PML4E_PWT RT_BIT(3)
2028	/** Bit 4 - PCD - Page level cache disable bit. */
2029	#define X86_PML4E_PCD RT_BIT(4)
2030	/** Bit 5 - A - Access bit. */
2031	#define X86_PML4E_A RT_BIT(5)
2032	/** Bits 9-11 - - Available for use to system software. */
2033	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2034	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2035	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2036	/** Bits 8, 7 - - MBZ bits when NX is active. */
2037	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2038	/** Bits 63, 7 - - MBZ bits when no NX. */
2039	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2040	/** Bits 63 - NX - PAE - No execution flag. */
2041	#define X86_PML4E_NX RT_BIT_64(63)
2042
2043	/**
2044	* Page Map Level-4 Entry
2045	*/
2046	typedef struct X86PML4EBITS
2047	{
2048	/** Flags whether(=1) or not the page is present. */
2049	uint32_t u1Present : 1;
2050	/** Read(=0) / Write(=1) flag. */
2051	uint32_t u1Write : 1;
2052	/** User(=1) / Supervisor (=0) flag. */
2053	uint32_t u1User : 1;
2054	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2055	uint32_t u1WriteThru : 1;
2056	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2057	uint32_t u1CacheDisable : 1;
2058	/** Accessed flag.
2059	* Indicates that the page have been read or written to. */
2060	uint32_t u1Accessed : 1;
2061	/** Chunk of reserved bits. */
2062	uint32_t u3Reserved : 3;
2063	/** Available for use to system software. */
2064	uint32_t u3Available : 3;
2065	/** Physical Page number of the next level - Low Part. Don't use! */
2066	uint32_t u20PageNoLow : 20;
2067	/** Physical Page number of the next level - High Part. Don't use! */
2068	uint32_t u20PageNoHigh : 20;
2069	/** MBZ bits */
2070	uint32_t u11Reserved : 11;
2071	/** No Execute flag. */
2072	uint32_t u1NoExecute : 1;
2073	} X86PML4EBITS;
2074	/** Pointer to a page map level-4 entry. */
2075	typedef X86PML4EBITS *PX86PML4EBITS;
2076	/** Pointer to a const page map level-4 entry. */
2077	typedef const X86PML4EBITS *PCX86PML4EBITS;
2078
2079	/**
2080	* Page Map Level-4 Entry.
2081	*/
2082	typedef union X86PML4E
2083	{
2084	/** Unsigned integer view. */
2085	X86PGPAEUINT u;
2086	/** Normal view. */
2087	X86PML4EBITS n;
2088	/** 8 bit unsigned integer view. */
2089	uint8_t au8[8];
2090	/** 16 bit unsigned integer view. */
2091	uint16_t au16[4];
2092	/** 32 bit unsigned integer view. */
2093	uint32_t au32[2];
2094	} X86PML4E;
2095	/** Pointer to a page map level-4 entry. */
2096	typedef X86PML4E *PX86PML4E;
2097	/** Pointer to a const page map level-4 entry. */
2098	typedef const X86PML4E *PCX86PML4E;
2099
2100
2101	/**
2102	* Page Map Level-4.
2103	*/
2104	typedef struct X86PML4
2105	{
2106	/** PDE Array. */
2107	X86PML4E a[X86_PG_PAE_ENTRIES];
2108	} X86PML4;
2109	/** Pointer to a page map level-4. */
2110	typedef X86PML4 *PX86PML4;
2111	/** Pointer to a const page map level-4. */
2112	typedef const X86PML4 *PCX86PML4;
2113
2114	/** The page shift to get the PML4 index. */
2115	#define X86_PML4_SHIFT 39
2116	/** The PML4 index mask (apply to a shifted page address). */
2117	#define X86_PML4_MASK 0x1ff
2118
2119	/** @} */
2120
2121	/** @} */
2122
2123	/**
2124	* 32-bit protected mode FSTENV image.
2125	*/
2126	typedef struct X86FSTENV32P
2127	{
2128	uint16_t FCW;
2129	uint16_t padding1;
2130	uint16_t FSW;
2131	uint16_t padding2;
2132	uint16_t FTW;
2133	uint16_t padding3;
2134	uint32_t FPUIP;
2135	uint16_t FPUCS;
2136	uint16_t FOP;
2137	uint32_t FPUDP;
2138	uint16_t FPUDS;
2139	uint16_t padding4;
2140	} X86FSTENV32P;
2141	/** Pointer to a 32-bit protected mode FSTENV image. */
2142	typedef X86FSTENV32P *PX86FSTENV32P;
2143	/** Pointer to a const 32-bit protected mode FSTENV image. */
2144	typedef X86FSTENV32P const *PCX86FSTENV32P;
2145
2146
2147	/**
2148	* 80-bit MMX/FPU register type.
2149	*/
2150	typedef struct X86FPUMMX
2151	{
2152	uint8_t reg[10];
2153	} X86FPUMMX;
2154	/** Pointer to a 80-bit MMX/FPU register type. */
2155	typedef X86FPUMMX *PX86FPUMMX;
2156	/** Pointer to a const 80-bit MMX/FPU register type. */
2157	typedef const X86FPUMMX *PCX86FPUMMX;
2158
2159	/**
2160	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2161	* @todo verify this...
2162	*/
2163	#pragma pack(1)
2164	typedef struct X86FPUSTATE
2165	{
2166	/** 0x00 - Control word. */
2167	uint16_t FCW;
2168	/** 0x02 - Alignment word */
2169	uint16_t Dummy1;
2170	/** 0x04 - Status word. */
2171	uint16_t FSW;
2172	/** 0x06 - Alignment word */
2173	uint16_t Dummy2;
2174	/** 0x08 - Tag word */
2175	uint16_t FTW;
2176	/** 0x0a - Alignment word */
2177	uint16_t Dummy3;
2178
2179	/** 0x0c - Instruction pointer. */
2180	uint32_t FPUIP;
2181	/** 0x10 - Code selector. */
2182	uint16_t CS;
2183	/** 0x12 - Opcode. */
2184	uint16_t FOP;
2185	/** 0x14 - FOO. */
2186	uint32_t FPUOO;
2187	/** 0x18 - FOS. */
2188	uint32_t FPUOS;
2189	/** 0x1c */
2190	union
2191	{
2192	/** MMX view. */
2193	uint64_t mmx;
2194	/** FPU view - todo. */
2195	X86FPUMMX fpu;
2196	/** Extended precision floating point view. */
2197	RTFLOAT80U r80;
2198	/** Extended precision floating point view v2. */
2199	RTFLOAT80U2 r80Ex;
2200	/** 8-bit view. */
2201	uint8_t au8[16];
2202	/** 16-bit view. */
2203	uint16_t au16[8];
2204	/** 32-bit view. */
2205	uint32_t au32[4];
2206	/** 64-bit view. */
2207	uint64_t au64[2];
2208	/** 128-bit view. (yeah, very helpful) */
2209	uint128_t au128[1];
2210	} regs[8];
2211	} X86FPUSTATE;
2212	#pragma pack()
2213	/** Pointer to a FPU state. */
2214	typedef X86FPUSTATE *PX86FPUSTATE;
2215	/** Pointer to a const FPU state. */
2216	typedef const X86FPUSTATE *PCX86FPUSTATE;
2217
2218	/**
2219	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2220	*/
2221	#pragma pack(1)
2222	typedef struct X86FXSTATE
2223	{
2224	/** 0x00 - Control word. */
2225	uint16_t FCW;
2226	/** 0x02 - Status word. */
2227	uint16_t FSW;
2228	/** 0x04 - Tag word. (The upper byte is always zero.) */
2229	uint16_t FTW;
2230	/** 0x06 - Opcode. */
2231	uint16_t FOP;
2232	/** 0x08 - Instruction pointer. */
2233	uint32_t FPUIP;
2234	/** 0x0c - Code selector. */
2235	uint16_t CS;
2236	uint16_t Rsrvd1;
2237	/** 0x10 - Data pointer. */
2238	uint32_t FPUDP;
2239	/** 0x14 - Data segment */
2240	uint16_t DS;
2241	/** 0x16 */
2242	uint16_t Rsrvd2;
2243	/** 0x18 */
2244	uint32_t MXCSR;
2245	/** 0x1c */
2246	uint32_t MXCSR_MASK;
2247	/** 0x20 */
2248	union
2249	{
2250	/** MMX view. */
2251	uint64_t mmx;
2252	/** FPU view - todo. */
2253	X86FPUMMX fpu;
2254	/** Extended precision floating point view. */
2255	RTFLOAT80U r80;
2256	/** Extended precision floating point view v2 */
2257	RTFLOAT80U2 r80Ex;
2258	/** 8-bit view. */
2259	uint8_t au8[16];
2260	/** 16-bit view. */
2261	uint16_t au16[8];
2262	/** 32-bit view. */
2263	uint32_t au32[4];
2264	/** 64-bit view. */
2265	uint64_t au64[2];
2266	/** 128-bit view. (yeah, very helpful) */
2267	uint128_t au128[1];
2268	} aRegs[8];
2269	/* - offset 160 - */
2270	union
2271	{
2272	/** XMM Register view . /
2273	uint128_t xmm;
2274	/** 8-bit view. */
2275	uint8_t au8[16];
2276	/** 16-bit view. */
2277	uint16_t au16[8];
2278	/** 32-bit view. */
2279	uint32_t au32[4];
2280	/** 64-bit view. */
2281	uint64_t au64[2];
2282	/** 128-bit view. (yeah, very helpful) */
2283	uint128_t au128[1];
2284	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2285	/* - offset 416 - */
2286	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2287	} X86FXSTATE;
2288	#pragma pack()
2289	/** Pointer to a FPU Extended state. */
2290	typedef X86FXSTATE *PX86FXSTATE;
2291	/** Pointer to a const FPU Extended state. */
2292	typedef const X86FXSTATE *PCX86FXSTATE;
2293
2294	/** @name FPU status word flags.
2295	* @{ */
2296	/** Exception Flag: Invalid operation. */
2297	#define X86_FSW_IE RT_BIT(0)
2298	/** Exception Flag: Denormalized operand. */
2299	#define X86_FSW_DE RT_BIT(1)
2300	/** Exception Flag: Zero divide. */
2301	#define X86_FSW_ZE RT_BIT(2)
2302	/** Exception Flag: Overflow. */
2303	#define X86_FSW_OE RT_BIT(3)
2304	/** Exception Flag: Underflow. */
2305	#define X86_FSW_UE RT_BIT(4)
2306	/** Exception Flag: Precision. */
2307	#define X86_FSW_PE RT_BIT(5)
2308	/** Stack fault. */
2309	#define X86_FSW_SF RT_BIT(6)
2310	/** Error summary status. */
2311	#define X86_FSW_ES RT_BIT(7)
2312	/** Mask of exceptions flags, excluding the summary bit. */
2313	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2314	/** Mask of exceptions flags, including the summary bit. */
2315	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2316	/** Condition code 0. */
2317	#define X86_FSW_C0 RT_BIT(8)
2318	/** Condition code 1. */
2319	#define X86_FSW_C1 RT_BIT(9)
2320	/** Condition code 2. */
2321	#define X86_FSW_C2 RT_BIT(10)
2322	/** Top of the stack mask. */
2323	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2324	/** TOP shift value. */
2325	#define X86_FSW_TOP_SHIFT 11
2326	/** Mask for getting TOP value after shifting it right. */
2327	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2328	/** Get the TOP value. */
2329	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2330	/** Condition code 3. */
2331	#define X86_FSW_C3 RT_BIT(14)
2332	/** Mask of exceptions flags, including the summary bit. */
2333	#define X86_FSW_C_MASK UINT16_C(0x4700)
2334	/** FPU busy. */
2335	#define X86_FSW_B RT_BIT(15)
2336	/** @} */
2337
2338
2339	/** @name FPU control word flags.
2340	* @{ */
2341	/** Exception Mask: Invalid operation. */
2342	#define X86_FCW_IM RT_BIT(0)
2343	/** Exception Mask: Denormalized operand. */
2344	#define X86_FCW_DM RT_BIT(1)
2345	/** Exception Mask: Zero divide. */
2346	#define X86_FCW_ZM RT_BIT(2)
2347	/** Exception Mask: Overflow. */
2348	#define X86_FCW_OM RT_BIT(3)
2349	/** Exception Mask: Underflow. */
2350	#define X86_FCW_UM RT_BIT(4)
2351	/** Exception Mask: Precision. */
2352	#define X86_FCW_PM RT_BIT(5)
2353	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2354	* @remarks This includes reserved bit 6. */
2355	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2356	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2357	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2358	/** Precision control mask. */
2359	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2360	/** Precision control: 24-bit. */
2361	#define X86_FCW_PC_24 UINT16_C(0x0000)
2362	/** Precision control: Reserved. */
2363	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2364	/** Precision control: 53-bit. */
2365	#define X86_FCW_PC_53 UINT16_C(0x0200)
2366	/** Precision control: 64-bit. */
2367	#define X86_FCW_PC_64 UINT16_C(0x0300)
2368	/** Rounding control mask. */
2369	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2370	/** Rounding control: To nearest. */
2371	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2372	/** Rounding control: Down. */
2373	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2374	/** Rounding control: Up. */
2375	#define X86_FCW_RC_UP UINT16_C(0x0800)
2376	/** Rounding control: Towards zero. */
2377	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2378	/** Bits which should be zero, apparently. */
2379	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2380	/** @} */
2381
2382	/** @name SSE MXCSR
2383	* @{ */
2384	/** Exception Flag: Invalid operation. */
2385	#define X86_MSXCR_IE RT_BIT(0)
2386	/** Exception Flag: Denormalized operand. */
2387	#define X86_MSXCR_DE RT_BIT(1)
2388	/** Exception Flag: Zero divide. */
2389	#define X86_MSXCR_ZE RT_BIT(2)
2390	/** Exception Flag: Overflow. */
2391	#define X86_MSXCR_OE RT_BIT(3)
2392	/** Exception Flag: Underflow. */
2393	#define X86_MSXCR_UE RT_BIT(4)
2394	/** Exception Flag: Precision. */
2395	#define X86_MSXCR_PE RT_BIT(5)
2396
2397	/** Denormals are zero. */
2398	#define X86_MSXCR_DAZ RT_BIT(6)
2399
2400	/** Exception Mask: Invalid operation. */
2401	#define X86_MSXCR_IM RT_BIT(7)
2402	/** Exception Mask: Denormalized operand. */
2403	#define X86_MSXCR_DM RT_BIT(8)
2404	/** Exception Mask: Zero divide. */
2405	#define X86_MSXCR_ZM RT_BIT(9)
2406	/** Exception Mask: Overflow. */
2407	#define X86_MSXCR_OM RT_BIT(10)
2408	/** Exception Mask: Underflow. */
2409	#define X86_MSXCR_UM RT_BIT(11)
2410	/** Exception Mask: Precision. */
2411	#define X86_MSXCR_PM RT_BIT(12)
2412
2413	/** Rounding control mask. */
2414	#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2415	/** Rounding control: To nearest. */
2416	#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2417	/** Rounding control: Down. */
2418	#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2419	/** Rounding control: Up. */
2420	#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2421	/** Rounding control: Towards zero. */
2422	#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2423
2424	/** Flush-to-zero for masked underflow. */
2425	#define X86_MSXCR_FZ RT_BIT(15)
2426
2427	/** Misaligned Exception Mask. */
2428	#define X86_MSXCR_MM RT_BIT(16)
2429	/** @} */
2430
2431
2432	/** @name Selector Descriptor
2433	* @{
2434	*/
2435
2436	#ifndef VBOX_FOR_DTRACE_LIB
2437	/**
2438	* Descriptor attributes (as seen by VT-x).
2439	*/
2440	typedef struct X86DESCATTRBITS
2441	{
2442	/** 00 - Segment Type. */
2443	unsigned u4Type : 4;
2444	/** 04 - Descriptor Type. System(=0) or code/data selector */
2445	unsigned u1DescType : 1;
2446	/** 05 - Descriptor Privelege level. */
2447	unsigned u2Dpl : 2;
2448	/** 07 - Flags selector present(=1) or not. */
2449	unsigned u1Present : 1;
2450	/** 08 - Segment limit 16-19. */
2451	unsigned u4LimitHigh : 4;
2452	/** 0c - Available for system software. */
2453	unsigned u1Available : 1;
2454	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2455	unsigned u1Long : 1;
2456	/** 0e - This flags meaning depends on the segment type. Try make sense out
2457	* of the intel manual yourself. */
2458	unsigned u1DefBig : 1;
2459	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2460	* clear byte. */
2461	unsigned u1Granularity : 1;
2462	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2463	unsigned u1Unusable : 1;
2464	} X86DESCATTRBITS;
2465	#endif /* !VBOX_FOR_DTRACE_LIB */
2466
2467	/** @name X86DESCATTR masks
2468	* @{ */
2469	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2470	#define X86DESCATTR_DT UINT32_C(0x00000010)
2471	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2472	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2473	#define X86DESCATTR_P UINT32_C(0x00000080)
2474	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2475	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2476	#define X86DESCATTR_L UINT32_C(0x00002000)
2477	#define X86DESCATTR_D UINT32_C(0x00004000)
2478	#define X86DESCATTR_G UINT32_C(0x00008000)
2479	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2480	/** @} */
2481
2482	#pragma pack(1)
2483	typedef union X86DESCATTR
2484	{
2485	/** Unsigned integer view. */
2486	uint32_t u;
2487	#ifndef VBOX_FOR_DTRACE_LIB
2488	/** Normal view. */
2489	X86DESCATTRBITS n;
2490	#endif
2491	} X86DESCATTR;
2492	#pragma pack()
2493	/** Pointer to descriptor attributes. */
2494	typedef X86DESCATTR *PX86DESCATTR;
2495	/** Pointer to const descriptor attributes. */
2496	typedef const X86DESCATTR *PCX86DESCATTR;
2497
2498	#ifndef VBOX_FOR_DTRACE_LIB
2499
2500	/**
2501	* Generic descriptor table entry
2502	*/
2503	#pragma pack(1)
2504	typedef struct X86DESCGENERIC
2505	{
2506	/** 00 - Limit - Low word. */
2507	unsigned u16LimitLow : 16;
2508	/** 10 - Base address - lowe word.
2509	* Don't try set this to 24 because MSC is doing stupid things then. */
2510	unsigned u16BaseLow : 16;
2511	/** 20 - Base address - first 8 bits of high word. */
2512	unsigned u8BaseHigh1 : 8;
2513	/** 28 - Segment Type. */
2514	unsigned u4Type : 4;
2515	/** 2c - Descriptor Type. System(=0) or code/data selector */
2516	unsigned u1DescType : 1;
2517	/** 2d - Descriptor Privelege level. */
2518	unsigned u2Dpl : 2;
2519	/** 2f - Flags selector present(=1) or not. */
2520	unsigned u1Present : 1;
2521	/** 30 - Segment limit 16-19. */
2522	unsigned u4LimitHigh : 4;
2523	/** 34 - Available for system software. */
2524	unsigned u1Available : 1;
2525	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2526	unsigned u1Long : 1;
2527	/** 36 - This flags meaning depends on the segment type. Try make sense out
2528	* of the intel manual yourself. */
2529	unsigned u1DefBig : 1;
2530	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
2531	* clear byte. */
2532	unsigned u1Granularity : 1;
2533	/** 38 - Base address - highest 8 bits. */
2534	unsigned u8BaseHigh2 : 8;
2535	} X86DESCGENERIC;
2536	#pragma pack()
2537	/** Pointer to a generic descriptor entry. */
2538	typedef X86DESCGENERIC *PX86DESCGENERIC;
2539	/** Pointer to a const generic descriptor entry. */
2540	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2541
2542	/** @name Bit offsets of X86DESCGENERIC members.
2543	* @{*/
2544	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
2545	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
2546	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
2547	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
2548	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
2549	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
2550	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
2551	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
2552	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
2553	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
2554	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
2555	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
2556	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
2557	/** @} */
2558
2559	/**
2560	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2561	*/
2562	typedef struct X86DESCGATE
2563	{
2564	/** 00 - Target code segment offset - Low word.
2565	* Ignored if task-gate. */
2566	unsigned u16OffsetLow : 16;
2567	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2568	* TSS selector if task-gate. */
2569	unsigned u16Sel : 16;
2570	/** 20 - Number of parameters for a call-gate.
2571	* Ignored if interrupt-, trap- or task-gate. */
2572	unsigned u4ParmCount : 4;
2573	/** 24 - Reserved / ignored. */
2574	unsigned u4Reserved : 4;
2575	/** 28 - Segment Type. */
2576	unsigned u4Type : 4;
2577	/** 2c - Descriptor Type (0 = system). */
2578	unsigned u1DescType : 1;
2579	/** 2d - Descriptor Privelege level. */
2580	unsigned u2Dpl : 2;
2581	/** 2f - Flags selector present(=1) or not. */
2582	unsigned u1Present : 1;
2583	/** 30 - Target code segment offset - High word.
2584	* Ignored if task-gate. */
2585	unsigned u16OffsetHigh : 16;
2586	} X86DESCGATE;
2587	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2588	typedef X86DESCGATE *PX86DESCGATE;
2589	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2590	typedef const X86DESCGATE *PCX86DESCGATE;
2591
2592	#endif /* VBOX_FOR_DTRACE_LIB */
2593
2594	/**
2595	* Descriptor table entry.
2596	*/
2597	#pragma pack(1)
2598	typedef union X86DESC
2599	{
2600	#ifndef VBOX_FOR_DTRACE_LIB
2601	/** Generic descriptor view. */
2602	X86DESCGENERIC Gen;
2603	/** Gate descriptor view. */
2604	X86DESCGATE Gate;
2605	#endif
2606
2607	/** 8 bit unsigned integer view. */
2608	uint8_t au8[8];
2609	/** 16 bit unsigned integer view. */
2610	uint16_t au16[4];
2611	/** 32 bit unsigned integer view. */
2612	uint32_t au32[2];
2613	/** 64 bit unsigned integer view. */
2614	uint64_t au64[1];
2615	/** Unsigned integer view. */
2616	uint64_t u;
2617	} X86DESC;
2618	#ifndef VBOX_FOR_DTRACE_LIB
2619	AssertCompileSize(X86DESC, 8);
2620	#endif
2621	#pragma pack()
2622	/** Pointer to descriptor table entry. */
2623	typedef X86DESC *PX86DESC;
2624	/** Pointer to const descriptor table entry. */
2625	typedef const X86DESC *PCX86DESC;
2626
2627	/** @def X86DESC_BASE
2628	* Return the base address of a descriptor.
2629	*/
2630	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
2631	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2632	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2633	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2634
2635	/** @def X86DESC_LIMIT
2636	* Return the limit of a descriptor.
2637	*/
2638	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
2639	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2640	\| ( (a_pDesc)->Gen.u16LimitLow ) )
2641
2642	/** @def X86DESC_LIMIT_G
2643	* Return the limit of a descriptor with the granularity bit taken into account.
2644	* @returns Selector limit (uint32_t).
2645	* @param a_pDesc Pointer to the descriptor.
2646	*/
2647	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
2648	( (a_pDesc)->Gen.u1Granularity \
2649	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
2650	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
2651	)
2652
2653	/** @def X86DESC_GET_HID_ATTR
2654	* Get the descriptor attributes for the hidden register.
2655	*/
2656	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
2657	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2658
2659	#ifndef VBOX_FOR_DTRACE_LIB
2660
2661	/**
2662	* 64 bits generic descriptor table entry
2663	* Note: most of these bits have no meaning in long mode.
2664	*/
2665	#pragma pack(1)
2666	typedef struct X86DESC64GENERIC
2667	{
2668	/** Limit - Low word - IGNORED. */
2669	unsigned u16LimitLow : 16;
2670	/** Base address - low word. - IGNORED
2671	* Don't try set this to 24 because MSC is doing stupid things then. */
2672	unsigned u16BaseLow : 16;
2673	/** Base address - first 8 bits of high word. - IGNORED */
2674	unsigned u8BaseHigh1 : 8;
2675	/** Segment Type. */
2676	unsigned u4Type : 4;
2677	/** Descriptor Type. System(=0) or code/data selector */
2678	unsigned u1DescType : 1;
2679	/** Descriptor Privelege level. */
2680	unsigned u2Dpl : 2;
2681	/** Flags selector present(=1) or not. */
2682	unsigned u1Present : 1;
2683	/** Segment limit 16-19. - IGNORED */
2684	unsigned u4LimitHigh : 4;
2685	/** Available for system software. - IGNORED */
2686	unsigned u1Available : 1;
2687	/** Long mode flag. */
2688	unsigned u1Long : 1;
2689	/** This flags meaning depends on the segment type. Try make sense out
2690	* of the intel manual yourself. */
2691	unsigned u1DefBig : 1;
2692	/** Granularity of the limit. If set 4KB granularity is used, if
2693	* clear byte. - IGNORED */
2694	unsigned u1Granularity : 1;
2695	/** Base address - highest 8 bits. - IGNORED */
2696	unsigned u8BaseHigh2 : 8;
2697	/** Base address - bits 63-32. */
2698	unsigned u32BaseHigh3 : 32;
2699	unsigned u8Reserved : 8;
2700	unsigned u5Zeros : 5;
2701	unsigned u19Reserved : 19;
2702	} X86DESC64GENERIC;
2703	#pragma pack()
2704	/** Pointer to a generic descriptor entry. */
2705	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2706	/** Pointer to a const generic descriptor entry. */
2707	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2708
2709	/**
2710	* System descriptor table entry (64 bits)
2711	*
2712	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2713	*/
2714	#pragma pack(1)
2715	typedef struct X86DESC64SYSTEM
2716	{
2717	/** Limit - Low word. */
2718	unsigned u16LimitLow : 16;
2719	/** Base address - lowe word.
2720	* Don't try set this to 24 because MSC is doing stupid things then. */
2721	unsigned u16BaseLow : 16;
2722	/** Base address - first 8 bits of high word. */
2723	unsigned u8BaseHigh1 : 8;
2724	/** Segment Type. */
2725	unsigned u4Type : 4;
2726	/** Descriptor Type. System(=0) or code/data selector */
2727	unsigned u1DescType : 1;
2728	/** Descriptor Privelege level. */
2729	unsigned u2Dpl : 2;
2730	/** Flags selector present(=1) or not. */
2731	unsigned u1Present : 1;
2732	/** Segment limit 16-19. */
2733	unsigned u4LimitHigh : 4;
2734	/** Available for system software. */
2735	unsigned u1Available : 1;
2736	/** Reserved - 0. */
2737	unsigned u1Reserved : 1;
2738	/** This flags meaning depends on the segment type. Try make sense out
2739	* of the intel manual yourself. */
2740	unsigned u1DefBig : 1;
2741	/** Granularity of the limit. If set 4KB granularity is used, if
2742	* clear byte. */
2743	unsigned u1Granularity : 1;
2744	/** Base address - bits 31-24. */
2745	unsigned u8BaseHigh2 : 8;
2746	/** Base address - bits 63-32. */
2747	unsigned u32BaseHigh3 : 32;
2748	unsigned u8Reserved : 8;
2749	unsigned u5Zeros : 5;
2750	unsigned u19Reserved : 19;
2751	} X86DESC64SYSTEM;
2752	#pragma pack()
2753	/** Pointer to a system descriptor entry. */
2754	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2755	/** Pointer to a const system descriptor entry. */
2756	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2757
2758	/**
2759	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2760	*/
2761	typedef struct X86DESC64GATE
2762	{
2763	/** Target code segment offset - Low word. */
2764	unsigned u16OffsetLow : 16;
2765	/** Target code segment selector. */
2766	unsigned u16Sel : 16;
2767	/** Interrupt stack table for interrupt- and trap-gates.
2768	* Ignored by call-gates. */
2769	unsigned u3IST : 3;
2770	/** Reserved / ignored. */
2771	unsigned u5Reserved : 5;
2772	/** Segment Type. */
2773	unsigned u4Type : 4;
2774	/** Descriptor Type (0 = system). */
2775	unsigned u1DescType : 1;
2776	/** Descriptor Privelege level. */
2777	unsigned u2Dpl : 2;
2778	/** Flags selector present(=1) or not. */
2779	unsigned u1Present : 1;
2780	/** Target code segment offset - High word.
2781	* Ignored if task-gate. */
2782	unsigned u16OffsetHigh : 16;
2783	/** Target code segment offset - Top dword.
2784	* Ignored if task-gate. */
2785	unsigned u32OffsetTop : 32;
2786	/** Reserved / ignored / must be zero.
2787	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2788	unsigned u32Reserved : 32;
2789	} X86DESC64GATE;
2790	AssertCompileSize(X86DESC64GATE, 16);
2791	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2792	typedef X86DESC64GATE *PX86DESC64GATE;
2793	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2794	typedef const X86DESC64GATE *PCX86DESC64GATE;
2795
2796	#endif /* VBOX_FOR_DTRACE_LIB */
2797
2798	/**
2799	* Descriptor table entry.
2800	*/
2801	#pragma pack(1)
2802	typedef union X86DESC64
2803	{
2804	#ifndef VBOX_FOR_DTRACE_LIB
2805	/** Generic descriptor view. */
2806	X86DESC64GENERIC Gen;
2807	/** System descriptor view. */
2808	X86DESC64SYSTEM System;
2809	/** Gate descriptor view. */
2810	X86DESC64GATE Gate;
2811	#endif
2812
2813	/** 8 bit unsigned integer view. */
2814	uint8_t au8[16];
2815	/** 16 bit unsigned integer view. */
2816	uint16_t au16[8];
2817	/** 32 bit unsigned integer view. */
2818	uint32_t au32[4];
2819	/** 64 bit unsigned integer view. */
2820	uint64_t au64[2];
2821	} X86DESC64;
2822	#ifndef VBOX_FOR_DTRACE_LIB
2823	AssertCompileSize(X86DESC64, 16);
2824	#endif
2825	#pragma pack()
2826	/** Pointer to descriptor table entry. */
2827	typedef X86DESC64 *PX86DESC64;
2828	/** Pointer to const descriptor table entry. */
2829	typedef const X86DESC64 *PCX86DESC64;
2830
2831	/** @def X86DESC64_BASE
2832	* Return the base of a 64-bit descriptor.
2833	*/
2834	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
2835	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2836	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2837	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2838	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2839
2840
2841
2842	/** @name Host system descriptor table entry - Use with care!
2843	* @{ */
2844	/** Host system descriptor table entry. */
2845	#if HC_ARCH_BITS == 64
2846	typedef X86DESC64 X86DESCHC;
2847	#else
2848	typedef X86DESC X86DESCHC;
2849	#endif
2850	/** Pointer to a host system descriptor table entry. */
2851	#if HC_ARCH_BITS == 64
2852	typedef PX86DESC64 PX86DESCHC;
2853	#else
2854	typedef PX86DESC PX86DESCHC;
2855	#endif
2856	/** Pointer to a const host system descriptor table entry. */
2857	#if HC_ARCH_BITS == 64
2858	typedef PCX86DESC64 PCX86DESCHC;
2859	#else
2860	typedef PCX86DESC PCX86DESCHC;
2861	#endif
2862	/** @} */
2863
2864
2865	/** @name Selector Descriptor Types.
2866	* @{
2867	*/
2868
2869	/** @name Non-System Selector Types.
2870	* @{ */
2871	/** Code(=set)/Data(=clear) bit. */
2872	#define X86_SEL_TYPE_CODE 8
2873	/** Memory(=set)/System(=clear) bit. */
2874	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2875	/** Accessed bit. */
2876	#define X86_SEL_TYPE_ACCESSED 1
2877	/** Expand down bit (for data selectors only). */
2878	#define X86_SEL_TYPE_DOWN 4
2879	/** Conforming bit (for code selectors only). */
2880	#define X86_SEL_TYPE_CONF 4
2881	/** Write bit (for data selectors only). */
2882	#define X86_SEL_TYPE_WRITE 2
2883	/** Read bit (for code selectors only). */
2884	#define X86_SEL_TYPE_READ 2
2885	/** The bit number of the code segment read bit (relative to u4Type). */
2886	#define X86_SEL_TYPE_READ_BIT 1
2887
2888	/** Read only selector type. */
2889	#define X86_SEL_TYPE_RO 0
2890	/** Accessed read only selector type. */
2891	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2892	/** Read write selector type. */
2893	#define X86_SEL_TYPE_RW 2
2894	/** Accessed read write selector type. */
2895	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2896	/** Expand down read only selector type. */
2897	#define X86_SEL_TYPE_RO_DOWN 4
2898	/** Accessed expand down read only selector type. */
2899	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2900	/** Expand down read write selector type. */
2901	#define X86_SEL_TYPE_RW_DOWN 6
2902	/** Accessed expand down read write selector type. */
2903	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2904	/** Execute only selector type. */
2905	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2906	/** Accessed execute only selector type. */
2907	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2908	/** Execute and read selector type. */
2909	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2910	/** Accessed execute and read selector type. */
2911	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2912	/** Conforming execute only selector type. */
2913	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2914	/** Accessed Conforming execute only selector type. */
2915	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2916	/** Conforming execute and write selector type. */
2917	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2918	/** Accessed Conforming execute and write selector type. */
2919	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2920	/** @} */
2921
2922
2923	/** @name System Selector Types.
2924	* @{ */
2925	/** The TSS busy bit mask. */
2926	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2927
2928	/** Undefined system selector type. */
2929	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2930	/** 286 TSS selector. */
2931	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2932	/** LDT selector. */
2933	#define X86_SEL_TYPE_SYS_LDT 2
2934	/** 286 TSS selector - Busy. */
2935	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2936	/** 286 Callgate selector. */
2937	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2938	/** Taskgate selector. */
2939	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2940	/** 286 Interrupt gate selector. */
2941	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2942	/** 286 Trapgate selector. */
2943	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2944	/** Undefined system selector. */
2945	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2946	/** 386 TSS selector. */
2947	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2948	/** Undefined system selector. */
2949	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2950	/** 386 TSS selector - Busy. */
2951	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2952	/** 386 Callgate selector. */
2953	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2954	/** Undefined system selector. */
2955	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2956	/** 386 Interruptgate selector. */
2957	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2958	/** 386 Trapgate selector. */
2959	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2960	/** @} */
2961
2962	/** @name AMD64 System Selector Types.
2963	* @{ */
2964	/** LDT selector. */
2965	#define AMD64_SEL_TYPE_SYS_LDT 2
2966	/** TSS selector - Busy. */
2967	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2968	/** TSS selector - Busy. */
2969	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2970	/** Callgate selector. */
2971	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2972	/** Interruptgate selector. */
2973	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2974	/** Trapgate selector. */
2975	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2976	/** @} */
2977
2978	/** @} */
2979
2980
2981	/** @name Descriptor Table Entry Flag Masks.
2982	* These are for the 2nd 32-bit word of a descriptor.
2983	* @{ */
2984	/** Bits 8-11 - TYPE - Descriptor type mask. */
2985	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2986	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2987	#define X86_DESC_S RT_BIT(12)
2988	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2989	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2990	/** Bit 15 - P - Present. */
2991	#define X86_DESC_P RT_BIT(15)
2992	/** Bit 20 - AVL - Available for system software. */
2993	#define X86_DESC_AVL RT_BIT(20)
2994	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2995	#define X86_DESC_DB RT_BIT(22)
2996	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2997	* used, if clear byte. */
2998	#define X86_DESC_G RT_BIT(23)
2999	/** @} */
3000
3001	/** @} */
3002
3003
3004	/** @name Task Segments.
3005	* @{
3006	*/
3007
3008	/**
3009	* 16-bit Task Segment (TSS).
3010	*/
3011	#pragma pack(1)
3012	typedef struct X86TSS16
3013	{
3014	/** Back link to previous task. (static) */
3015	RTSEL selPrev;
3016	/** Ring-0 stack pointer. (static) */
3017	uint16_t sp0;
3018	/** Ring-0 stack segment. (static) */
3019	RTSEL ss0;
3020	/** Ring-1 stack pointer. (static) */
3021	uint16_t sp1;
3022	/** Ring-1 stack segment. (static) */
3023	RTSEL ss1;
3024	/** Ring-2 stack pointer. (static) */
3025	uint16_t sp2;
3026	/** Ring-2 stack segment. (static) */
3027	RTSEL ss2;
3028	/** IP before task switch. */
3029	uint16_t ip;
3030	/** FLAGS before task switch. */
3031	uint16_t flags;
3032	/** AX before task switch. */
3033	uint16_t ax;
3034	/** CX before task switch. */
3035	uint16_t cx;
3036	/** DX before task switch. */
3037	uint16_t dx;
3038	/** BX before task switch. */
3039	uint16_t bx;
3040	/** SP before task switch. */
3041	uint16_t sp;
3042	/** BP before task switch. */
3043	uint16_t bp;
3044	/** SI before task switch. */
3045	uint16_t si;
3046	/** DI before task switch. */
3047	uint16_t di;
3048	/** ES before task switch. */
3049	RTSEL es;
3050	/** CS before task switch. */
3051	RTSEL cs;
3052	/** SS before task switch. */
3053	RTSEL ss;
3054	/** DS before task switch. */
3055	RTSEL ds;
3056	/** LDTR before task switch. */
3057	RTSEL selLdt;
3058	} X86TSS16;
3059	#ifndef VBOX_FOR_DTRACE_LIB
3060	AssertCompileSize(X86TSS16, 44);
3061	#endif
3062	#pragma pack()
3063	/** Pointer to a 16-bit task segment. */
3064	typedef X86TSS16 *PX86TSS16;
3065	/** Pointer to a const 16-bit task segment. */
3066	typedef const X86TSS16 *PCX86TSS16;
3067
3068
3069	/**
3070	* 32-bit Task Segment (TSS).
3071	*/
3072	#pragma pack(1)
3073	typedef struct X86TSS32
3074	{
3075	/** Back link to previous task. (static) */
3076	RTSEL selPrev;
3077	uint16_t padding1;
3078	/** Ring-0 stack pointer. (static) */
3079	uint32_t esp0;
3080	/** Ring-0 stack segment. (static) */
3081	RTSEL ss0;
3082	uint16_t padding_ss0;
3083	/** Ring-1 stack pointer. (static) */
3084	uint32_t esp1;
3085	/** Ring-1 stack segment. (static) */
3086	RTSEL ss1;
3087	uint16_t padding_ss1;
3088	/** Ring-2 stack pointer. (static) */
3089	uint32_t esp2;
3090	/** Ring-2 stack segment. (static) */
3091	RTSEL ss2;
3092	uint16_t padding_ss2;
3093	/** Page directory for the task. (static) */
3094	uint32_t cr3;
3095	/** EIP before task switch. */
3096	uint32_t eip;
3097	/** EFLAGS before task switch. */
3098	uint32_t eflags;
3099	/** EAX before task switch. */
3100	uint32_t eax;
3101	/** ECX before task switch. */
3102	uint32_t ecx;
3103	/** EDX before task switch. */
3104	uint32_t edx;
3105	/** EBX before task switch. */
3106	uint32_t ebx;
3107	/** ESP before task switch. */
3108	uint32_t esp;
3109	/** EBP before task switch. */
3110	uint32_t ebp;
3111	/** ESI before task switch. */
3112	uint32_t esi;
3113	/** EDI before task switch. */
3114	uint32_t edi;
3115	/** ES before task switch. */
3116	RTSEL es;
3117	uint16_t padding_es;
3118	/** CS before task switch. */
3119	RTSEL cs;
3120	uint16_t padding_cs;
3121	/** SS before task switch. */
3122	RTSEL ss;
3123	uint16_t padding_ss;
3124	/** DS before task switch. */
3125	RTSEL ds;
3126	uint16_t padding_ds;
3127	/** FS before task switch. */
3128	RTSEL fs;
3129	uint16_t padding_fs;
3130	/** GS before task switch. */
3131	RTSEL gs;
3132	uint16_t padding_gs;
3133	/** LDTR before task switch. */
3134	RTSEL selLdt;
3135	uint16_t padding_ldt;
3136	/** Debug trap flag */
3137	uint16_t fDebugTrap;
3138	/** Offset relative to the TSS of the start of the I/O Bitmap
3139	* and the end of the interrupt redirection bitmap. */
3140	uint16_t offIoBitmap;
3141	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3142	uint8_t IntRedirBitmap[32];
3143	} X86TSS32;
3144	#pragma pack()
3145	/** Pointer to task segment. */
3146	typedef X86TSS32 *PX86TSS32;
3147	/** Pointer to const task segment. */
3148	typedef const X86TSS32 *PCX86TSS32;
3149
3150
3151	/**
3152	* 64-bit Task segment.
3153	*/
3154	#pragma pack(1)
3155	typedef struct X86TSS64
3156	{
3157	/** Reserved. */
3158	uint32_t u32Reserved;
3159	/** Ring-0 stack pointer. (static) */
3160	uint64_t rsp0;
3161	/** Ring-1 stack pointer. (static) */
3162	uint64_t rsp1;
3163	/** Ring-2 stack pointer. (static) */
3164	uint64_t rsp2;
3165	/** Reserved. */
3166	uint32_t u32Reserved2[2];
3167	/* IST */
3168	uint64_t ist1;
3169	uint64_t ist2;
3170	uint64_t ist3;
3171	uint64_t ist4;
3172	uint64_t ist5;
3173	uint64_t ist6;
3174	uint64_t ist7;
3175	/* Reserved. */
3176	uint16_t u16Reserved[5];
3177	/** Offset relative to the TSS of the start of the I/O Bitmap
3178	* and the end of the interrupt redirection bitmap. */
3179	uint16_t offIoBitmap;
3180	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3181	uint8_t IntRedirBitmap[32];
3182	} X86TSS64;
3183	#pragma pack()
3184	/** Pointer to a 64-bit task segment. */
3185	typedef X86TSS64 *PX86TSS64;
3186	/** Pointer to a const 64-bit task segment. */
3187	typedef const X86TSS64 *PCX86TSS64;
3188	#ifndef VBOX_FOR_DTRACE_LIB
3189	AssertCompileSize(X86TSS64, 136);
3190	#endif
3191
3192	/** @} */
3193
3194
3195	/** @name Selectors.
3196	* @{
3197	*/
3198
3199	/**
3200	* The shift used to convert a selector from and to index an index (C).
3201	*/
3202	#define X86_SEL_SHIFT 3
3203
3204	/**
3205	* The mask used to mask off the table indicator and RPL of an selector.
3206	*/
3207	#define X86_SEL_MASK 0xfff8U
3208
3209	/**
3210	* The mask used to mask off the RPL of an selector.
3211	* This is suitable for checking for NULL selectors.
3212	*/
3213	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3214
3215	/**
3216	* The bit indicating that a selector is in the LDT and not in the GDT.
3217	*/
3218	#define X86_SEL_LDT 0x0004U
3219
3220	/**
3221	* The bit mask for getting the RPL of a selector.
3222	*/
3223	#define X86_SEL_RPL 0x0003U
3224
3225	/**
3226	* The mask covering both RPL and LDT.
3227	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3228	* checks.
3229	*/
3230	#define X86_SEL_RPL_LDT 0x0007U
3231
3232	/** @} */
3233
3234
3235	/**
3236	* x86 Exceptions/Faults/Traps.
3237	*/
3238	typedef enum X86XCPT
3239	{
3240	/** \#DE - Divide error. */
3241	X86_XCPT_DE = 0x00,
3242	/** \#DB - Debug event (single step, DRx, ..) */
3243	X86_XCPT_DB = 0x01,
3244	/** NMI - Non-Maskable Interrupt */
3245	X86_XCPT_NMI = 0x02,
3246	/** \#BP - Breakpoint (INT3). */
3247	X86_XCPT_BP = 0x03,
3248	/** \#OF - Overflow (INTO). */
3249	X86_XCPT_OF = 0x04,
3250	/** \#BR - Bound range exceeded (BOUND). */
3251	X86_XCPT_BR = 0x05,
3252	/** \#UD - Undefined opcode. */
3253	X86_XCPT_UD = 0x06,
3254	/** \#NM - Device not available (math coprocessor device). */
3255	X86_XCPT_NM = 0x07,
3256	/** \#DF - Double fault. */
3257	X86_XCPT_DF = 0x08,
3258	/** ??? - Coprocessor segment overrun (obsolete). */
3259	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3260	/** \#TS - Taskswitch (TSS). */
3261	X86_XCPT_TS = 0x0a,
3262	/** \#NP - Segment no present. */
3263	X86_XCPT_NP = 0x0b,
3264	/** \#SS - Stack segment fault. */
3265	X86_XCPT_SS = 0x0c,
3266	/** \#GP - General protection fault. */
3267	X86_XCPT_GP = 0x0d,
3268	/** \#PF - Page fault. */
3269	X86_XCPT_PF = 0x0e,
3270	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3271	/** \#MF - Math fault (FPU). */
3272	X86_XCPT_MF = 0x10,
3273	/** \#AC - Alignment check. */
3274	X86_XCPT_AC = 0x11,
3275	/** \#MC - Machine check. */
3276	X86_XCPT_MC = 0x12,
3277	/** \#XF - SIMD Floating-Pointer Exception. */
3278	X86_XCPT_XF = 0x13,
3279	/** \#VE - Virtualzation Exception. */
3280	X86_XCPT_VE = 0x14,
3281	/** \#SX - Security Exception. */
3282	X86_XCPT_SX = 0x1f
3283	} X86XCPT;
3284	/** Pointer to a x86 exception code. */
3285	typedef X86XCPT *PX86XCPT;
3286	/** Pointer to a const x86 exception code. */
3287	typedef const X86XCPT *PCX86XCPT;
3288	/** The maximum exception value. */
3289	#define X86_XCPT_MAX (X86_XCPT_SX)
3290
3291
3292	/** @name Trap Error Codes
3293	* @{
3294	*/
3295	/** External indicator. */
3296	#define X86_TRAP_ERR_EXTERNAL 1
3297	/** IDT indicator. */
3298	#define X86_TRAP_ERR_IDT 2
3299	/** Descriptor table indicator - If set LDT, if clear GDT. */
3300	#define X86_TRAP_ERR_TI 4
3301	/** Mask for getting the selector. */
3302	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3303	/** Shift for getting the selector table index (C type index). */
3304	#define X86_TRAP_ERR_SEL_SHIFT 3
3305	/** @} */
3306
3307
3308	/** @name \#PF Trap Error Codes
3309	* @{
3310	*/
3311	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3312	#define X86_TRAP_PF_P RT_BIT(0)
3313	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3314	#define X86_TRAP_PF_RW RT_BIT(1)
3315	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3316	#define X86_TRAP_PF_US RT_BIT(2)
3317	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3318	#define X86_TRAP_PF_RSVD RT_BIT(3)
3319	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3320	#define X86_TRAP_PF_ID RT_BIT(4)
3321	/** @} */
3322
3323	#pragma pack(1)
3324	/**
3325	* 16-bit IDTR.
3326	*/
3327	typedef struct X86IDTR16
3328	{
3329	/** Offset. */
3330	uint16_t offSel;
3331	/** Selector. */
3332	uint16_t uSel;
3333	} X86IDTR16, *PX86IDTR16;
3334	#pragma pack()
3335
3336	#pragma pack(1)
3337	/**
3338	* 32-bit IDTR/GDTR.
3339	*/
3340	typedef struct X86XDTR32
3341	{
3342	/** Size of the descriptor table. */
3343	uint16_t cb;
3344	/** Address of the descriptor table. */
3345	#ifndef VBOX_FOR_DTRACE_LIB
3346	uint32_t uAddr;
3347	#else
3348	uint16_t au16Addr[2];
3349	#endif
3350	} X86XDTR32, *PX86XDTR32;
3351	#pragma pack()
3352
3353	#pragma pack(1)
3354	/**
3355	* 64-bit IDTR/GDTR.
3356	*/
3357	typedef struct X86XDTR64
3358	{
3359	/** Size of the descriptor table. */
3360	uint16_t cb;
3361	/** Address of the descriptor table. */
3362	#ifndef VBOX_FOR_DTRACE_LIB
3363	uint64_t uAddr;
3364	#else
3365	uint16_t au16Addr[4];
3366	#endif
3367	} X86XDTR64, *PX86XDTR64;
3368	#pragma pack()
3369
3370
3371	/** @name ModR/M
3372	* @{ */
3373	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3374	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3375	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3376	#define X86_MODRM_REG_SHIFT 3
3377	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3378	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3379	#define X86_MODRM_MOD_SHIFT 6
3380	#ifndef VBOX_FOR_DTRACE_LIB
3381	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3382	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3383	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3384	#endif
3385	/** @} */
3386
3387	/** @name SIB
3388	* @{ */
3389	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3390	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3391	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3392	#define X86_SIB_INDEX_SHIFT 3
3393	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3394	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3395	#define X86_SIB_SCALE_SHIFT 6
3396	#ifndef VBOX_FOR_DTRACE_LIB
3397	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3398	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3399	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3400	#endif
3401	/** @} */
3402
3403	/** @name General register indexes
3404	* @{ */
3405	#define X86_GREG_xAX 0
3406	#define X86_GREG_xCX 1
3407	#define X86_GREG_xDX 2
3408	#define X86_GREG_xBX 3
3409	#define X86_GREG_xSP 4
3410	#define X86_GREG_xBP 5
3411	#define X86_GREG_xSI 6
3412	#define X86_GREG_xDI 7
3413	#define X86_GREG_x8 8
3414	#define X86_GREG_x9 9
3415	#define X86_GREG_x10 10
3416	#define X86_GREG_x11 11
3417	#define X86_GREG_x12 12
3418	#define X86_GREG_x13 13
3419	#define X86_GREG_x14 14
3420	#define X86_GREG_x15 15
3421	/** @} */
3422
3423	/** @name X86_SREG_XXX - Segment register indexes.
3424	* @{ */
3425	#define X86_SREG_ES 0
3426	#define X86_SREG_CS 1
3427	#define X86_SREG_SS 2
3428	#define X86_SREG_DS 3
3429	#define X86_SREG_FS 4
3430	#define X86_SREG_GS 5
3431	/** @} */
3432	/** Segment register count. */
3433	#define X86_SREG_COUNT 6
3434
3435
3436	/** @name X86_OP_XXX - Prefixes
3437	* @{ */
3438	#define X86_OP_PRF_CS UINT8_C(0x2e)
3439	#define X86_OP_PRF_SS UINT8_C(0x36)
3440	#define X86_OP_PRF_DS UINT8_C(0x3e)
3441	#define X86_OP_PRF_ES UINT8_C(0x26)
3442	#define X86_OP_PRF_FS UINT8_C(0x64)
3443	#define X86_OP_PRF_GS UINT8_C(0x65)
3444	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3445	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3446	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3447	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3448	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3449	#define X86_OP_REX_B UINT8_C(0x41)
3450	#define X86_OP_REX_X UINT8_C(0x42)
3451	#define X86_OP_REX_R UINT8_C(0x44)
3452	#define X86_OP_REX_W UINT8_C(0x48)
3453	/** @} */
3454
3455
3456	/** @} */
3457
3458	#endif
3459

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source: vbox/trunk/include/iprt/x86.h@ 50255

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