x86.h@ 54403

Last change on this file since 54403 was 53630, checked in by vboxsync, 10 years ago
dtrace library fixes/hacks.
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File size: 129.4 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2014 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** The status bits commonly updated by arithmetic instructions. */
215	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
216	/** @} */
217
218
219	/** CPUID Feature information - ECX.
220	* CPUID query with EAX=1.
221	*/
222	#ifndef VBOX_FOR_DTRACE_LIB
223	typedef struct X86CPUIDFEATECX
224	{
225	/** Bit 0 - SSE3 - Supports SSE3 or not. */
226	unsigned u1SSE3 : 1;
227	/** Bit 1 - PCLMULQDQ. */
228	unsigned u1PCLMULQDQ : 1;
229	/** Bit 2 - DS Area 64-bit layout. */
230	unsigned u1DTE64 : 1;
231	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
232	unsigned u1Monitor : 1;
233	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
234	unsigned u1CPLDS : 1;
235	/** Bit 5 - VMX - Virtual Machine Technology. */
236	unsigned u1VMX : 1;
237	/** Bit 6 - SMX: Safer Mode Extensions. */
238	unsigned u1SMX : 1;
239	/** Bit 7 - EST - Enh. SpeedStep Tech. */
240	unsigned u1EST : 1;
241	/** Bit 8 - TM2 - Terminal Monitor 2. */
242	unsigned u1TM2 : 1;
243	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
244	unsigned u1SSSE3 : 1;
245	/** Bit 10 - CNTX-ID - L1 Context ID. */
246	unsigned u1CNTXID : 1;
247	/** Bit 11 - Reserved. */
248	unsigned u1Reserved1 : 1;
249	/** Bit 12 - FMA. */
250	unsigned u1FMA : 1;
251	/** Bit 13 - CX16 - CMPXCHG16B. */
252	unsigned u1CX16 : 1;
253	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
254	unsigned u1TPRUpdate : 1;
255	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
256	unsigned u1PDCM : 1;
257	/** Bit 16 - Reserved. */
258	unsigned u1Reserved2 : 1;
259	/** Bit 17 - PCID - Process-context identifiers. */
260	unsigned u1PCID : 1;
261	/** Bit 18 - Direct Cache Access. */
262	unsigned u1DCA : 1;
263	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
264	unsigned u1SSE4_1 : 1;
265	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
266	unsigned u1SSE4_2 : 1;
267	/** Bit 21 - x2APIC. */
268	unsigned u1x2APIC : 1;
269	/** Bit 22 - MOVBE - Supports MOVBE. */
270	unsigned u1MOVBE : 1;
271	/** Bit 23 - POPCNT - Supports POPCNT. */
272	unsigned u1POPCNT : 1;
273	/** Bit 24 - TSC-Deadline. */
274	unsigned u1TSCDEADLINE : 1;
275	/** Bit 25 - AES. */
276	unsigned u1AES : 1;
277	/** Bit 26 - XSAVE - Supports XSAVE. */
278	unsigned u1XSAVE : 1;
279	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
280	unsigned u1OSXSAVE : 1;
281	/** Bit 28 - AVX - Supports AVX instruction extensions. */
282	unsigned u1AVX : 1;
283	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
284	unsigned u1F16C : 1;
285	/** Bit 30 - RDRAND - Supports RDRAND. */
286	unsigned u1RDRAND : 1;
287	/** Bit 31 - Hypervisor present (we're a guest). */
288	unsigned u1HVP : 1;
289	} X86CPUIDFEATECX;
290	#else /* VBOX_FOR_DTRACE_LIB */
291	typedef uint32_t X86CPUIDFEATECX;
292	#endif /* VBOX_FOR_DTRACE_LIB */
293	/** Pointer to CPUID Feature Information - ECX. */
294	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
295	/** Pointer to const CPUID Feature Information - ECX. */
296	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
297
298
299	/** CPUID Feature Information - EDX.
300	* CPUID query with EAX=1.
301	*/
302	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
303	typedef struct X86CPUIDFEATEDX
304	{
305	/** Bit 0 - FPU - x87 FPU on Chip. */
306	unsigned u1FPU : 1;
307	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
308	unsigned u1VME : 1;
309	/** Bit 2 - DE - Debugging extensions. */
310	unsigned u1DE : 1;
311	/** Bit 3 - PSE - Page Size Extension. */
312	unsigned u1PSE : 1;
313	/** Bit 4 - TSC - Time Stamp Counter. */
314	unsigned u1TSC : 1;
315	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
316	unsigned u1MSR : 1;
317	/** Bit 6 - PAE - Physical Address Extension. */
318	unsigned u1PAE : 1;
319	/** Bit 7 - MCE - Machine Check Exception. */
320	unsigned u1MCE : 1;
321	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
322	unsigned u1CX8 : 1;
323	/** Bit 9 - APIC - APIC On-Chip. */
324	unsigned u1APIC : 1;
325	/** Bit 10 - Reserved. */
326	unsigned u1Reserved1 : 1;
327	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
328	unsigned u1SEP : 1;
329	/** Bit 12 - MTRR - Memory Type Range Registers. */
330	unsigned u1MTRR : 1;
331	/** Bit 13 - PGE - PTE Global Bit. */
332	unsigned u1PGE : 1;
333	/** Bit 14 - MCA - Machine Check Architecture. */
334	unsigned u1MCA : 1;
335	/** Bit 15 - CMOV - Conditional Move Instructions. */
336	unsigned u1CMOV : 1;
337	/** Bit 16 - PAT - Page Attribute Table. */
338	unsigned u1PAT : 1;
339	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
340	unsigned u1PSE36 : 1;
341	/** Bit 18 - PSN - Processor Serial Number. */
342	unsigned u1PSN : 1;
343	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
344	unsigned u1CLFSH : 1;
345	/** Bit 20 - Reserved. */
346	unsigned u1Reserved2 : 1;
347	/** Bit 21 - DS - Debug Store. */
348	unsigned u1DS : 1;
349	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
350	unsigned u1ACPI : 1;
351	/** Bit 23 - MMX - Intel MMX 'Technology'. */
352	unsigned u1MMX : 1;
353	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
354	unsigned u1FXSR : 1;
355	/** Bit 25 - SSE - SSE Support. */
356	unsigned u1SSE : 1;
357	/** Bit 26 - SSE2 - SSE2 Support. */
358	unsigned u1SSE2 : 1;
359	/** Bit 27 - SS - Self Snoop. */
360	unsigned u1SS : 1;
361	/** Bit 28 - HTT - Hyper-Threading Technology. */
362	unsigned u1HTT : 1;
363	/** Bit 29 - TM - Thermal Monitor. */
364	unsigned u1TM : 1;
365	/** Bit 30 - Reserved - . */
366	unsigned u1Reserved3 : 1;
367	/** Bit 31 - PBE - Pending Break Enabled. */
368	unsigned u1PBE : 1;
369	} X86CPUIDFEATEDX;
370	#else /* VBOX_FOR_DTRACE_LIB */
371	typedef uint32_t X86CPUIDFEATEDX;
372	#endif /* VBOX_FOR_DTRACE_LIB */
373	/** Pointer to CPUID Feature Information - EDX. */
374	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
375	/** Pointer to const CPUID Feature Information - EDX. */
376	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
377
378	/** @name CPUID Vendor information.
379	* CPUID query with EAX=0.
380	* @{
381	*/
382	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
383	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
384	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
385
386	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
387	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
388	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
389
390	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
391	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
392	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
393	/** @} */
394
395
396	/** @name CPUID Feature information.
397	* CPUID query with EAX=1.
398	* @{
399	*/
400	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
401	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
402	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
403	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
404	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
405	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
406	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
407	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
408	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
409	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
410	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
411	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
412	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
413	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
414	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
415	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
416	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
417	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
418	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
419	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
420	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
421	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
422	/** ECX Bit 12 - FMA. */
423	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
424	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
425	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
426	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
427	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
428	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
429	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
430	/** ECX Bit 17 - PCID - Process-context identifiers. */
431	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
432	/** ECX Bit 18 - DCA - Direct Cache Access. */
433	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
434	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
435	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
436	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
437	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
438	/** ECX Bit 21 - x2APIC support. */
439	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
440	/** ECX Bit 22 - MOVBE instruction. */
441	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
442	/** ECX Bit 23 - POPCNT instruction. */
443	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
444	/** ECX Bir 24 - TSC-Deadline. */
445	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
446	/** ECX Bit 25 - AES instructions. */
447	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
448	/** ECX Bit 26 - XSAVE instruction. */
449	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
450	/** ECX Bit 27 - OSXSAVE instruction. */
451	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
452	/** ECX Bit 28 - AVX. */
453	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
454	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
455	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29)
456	/** ECX Bit 30 - RDRAND instruction. */
457	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT(30)
458	/** ECX Bit 31 - Hypervisor Present (software only). */
459	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
460
461
462	/** Bit 0 - FPU - x87 FPU on Chip. */
463	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
464	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
465	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
466	/** Bit 2 - DE - Debugging extensions. */
467	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
468	/** Bit 3 - PSE - Page Size Extension. */
469	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
470	/** Bit 4 - TSC - Time Stamp Counter. */
471	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
472	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
473	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
474	/** Bit 6 - PAE - Physical Address Extension. */
475	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
476	/** Bit 7 - MCE - Machine Check Exception. */
477	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
478	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
479	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
480	/** Bit 9 - APIC - APIC On-Chip. */
481	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
482	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
483	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
484	/** Bit 12 - MTRR - Memory Type Range Registers. */
485	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
486	/** Bit 13 - PGE - PTE Global Bit. */
487	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
488	/** Bit 14 - MCA - Machine Check Architecture. */
489	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
490	/** Bit 15 - CMOV - Conditional Move Instructions. */
491	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
492	/** Bit 16 - PAT - Page Attribute Table. */
493	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
494	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
495	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
496	/** Bit 18 - PSN - Processor Serial Number. */
497	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
498	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
499	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
500	/** Bit 21 - DS - Debug Store. */
501	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
502	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
503	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
504	/** Bit 23 - MMX - Intel MMX Technology. */
505	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
506	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
507	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
508	/** Bit 25 - SSE - SSE Support. */
509	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
510	/** Bit 26 - SSE2 - SSE2 Support. */
511	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
512	/** Bit 27 - SS - Self Snoop. */
513	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
514	/** Bit 28 - HTT - Hyper-Threading Technology. */
515	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
516	/** Bit 29 - TM - Therm. Monitor. */
517	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
518	/** Bit 31 - PBE - Pending Break Enabled. */
519	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
520	/** @} */
521
522	/** @name CPUID mwait/monitor information.
523	* CPUID query with EAX=5.
524	* @{
525	*/
526	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
527	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
528	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
529	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
530	/** @} */
531
532
533	/** @name CPUID Structured Extended Feature information.
534	* CPUID query with EAX=7.
535	* @{
536	*/
537	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
538	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
539	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
540	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
541	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
542	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
543	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
544	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
545	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
546	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
547	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
548	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
549	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
550	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
551	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
552	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
553	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
554	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
555	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
556	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
557	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
558	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
559	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
560	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT(13)
561	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
562	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
563	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
564	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
565	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
566	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
567	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
568	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)
569	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
570	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
571	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
572	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
573	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
574	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT(23)
575	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
576	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
577	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
578	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
579	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
580	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
581	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
582	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
583	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
584	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
585	/** @} */
586
587
588	/** @name CPUID Extended Feature information.
589	* CPUID query with EAX=0x80000001.
590	* @{
591	*/
592	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
593	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
594
595	/** EDX Bit 11 - SYSCALL/SYSRET. */
596	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
597	/** EDX Bit 20 - No-Execute/Execute-Disable. */
598	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
599	/** EDX Bit 26 - 1 GB large page. */
600	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
601	/** EDX Bit 27 - RDTSCP. */
602	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
603	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
604	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
605	/** @}*/
606
607	/** @name CPUID AMD Feature information.
608	* CPUID query with EAX=0x80000001.
609	* @{
610	*/
611	/** Bit 0 - FPU - x87 FPU on Chip. */
612	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
613	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
614	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
615	/** Bit 2 - DE - Debugging extensions. */
616	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
617	/** Bit 3 - PSE - Page Size Extension. */
618	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
619	/** Bit 4 - TSC - Time Stamp Counter. */
620	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
621	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
622	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
623	/** Bit 6 - PAE - Physical Address Extension. */
624	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
625	/** Bit 7 - MCE - Machine Check Exception. */
626	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
627	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
628	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
629	/** Bit 9 - APIC - APIC On-Chip. */
630	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
631	/** Bit 12 - MTRR - Memory Type Range Registers. */
632	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
633	/** Bit 13 - PGE - PTE Global Bit. */
634	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
635	/** Bit 14 - MCA - Machine Check Architecture. */
636	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
637	/** Bit 15 - CMOV - Conditional Move Instructions. */
638	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
639	/** Bit 16 - PAT - Page Attribute Table. */
640	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
641	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
642	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
643	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
644	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
645	/** Bit 23 - MMX - Intel MMX Technology. */
646	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
647	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
648	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
649	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
650	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
651	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
652	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
653	/** Bit 31 - 3DNOW - AMD 3DNow. */
654	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
655
656	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
657	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
658	/** Bit 2 - SVM - AMD VM extensions. */
659	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
660	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
661	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
662	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
663	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
664	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
665	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
666	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
667	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
668	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
669	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
670	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
671	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
672	/** Bit 9 - OSVW - AMD OS visible workaround. */
673	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
674	/** Bit 10 - IBS - Instruct based sampling. */
675	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
676	/** Bit 11 - SSE5 - SSE5 instruction support. */
677	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
678	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
679	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
680	/** Bit 13 - WDT - AMD Watchdog timer support. */
681	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
682
683	/** @} */
684
685
686	/** @name CPUID AMD Feature information.
687	* CPUID query with EAX=0x80000007.
688	* @{
689	*/
690	/** Bit 0 - TS - Temperature Sensor. */
691	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
692	/** Bit 1 - FID - Frequency ID Control. */
693	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
694	/** Bit 2 - VID - Voltage ID Control. */
695	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
696	/** Bit 3 - TTP - THERMTRIP. */
697	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
698	/** Bit 4 - TM - Hardware Thermal Control. */
699	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
700	/** Bit 5 - STC - Software Thermal Control. */
701	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
702	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
703	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
704	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
705	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
706	/** Bit 8 - TSCINVAR - TSC Invariant. */
707	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
708	/** @} */
709
710
711	/** @name CR0
712	* @{ */
713	/** Bit 0 - PE - Protection Enabled */
714	#define X86_CR0_PE RT_BIT(0)
715	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
716	/** Bit 1 - MP - Monitor Coprocessor */
717	#define X86_CR0_MP RT_BIT(1)
718	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
719	/** Bit 2 - EM - Emulation. */
720	#define X86_CR0_EM RT_BIT(2)
721	#define X86_CR0_EMULATE_FPU RT_BIT(2)
722	/** Bit 3 - TS - Task Switch. */
723	#define X86_CR0_TS RT_BIT(3)
724	#define X86_CR0_TASK_SWITCH RT_BIT(3)
725	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
726	#define X86_CR0_ET RT_BIT(4)
727	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
728	/** Bit 5 - NE - Numeric error. */
729	#define X86_CR0_NE RT_BIT(5)
730	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
731	/** Bit 16 - WP - Write Protect. */
732	#define X86_CR0_WP RT_BIT(16)
733	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
734	/** Bit 18 - AM - Alignment Mask. */
735	#define X86_CR0_AM RT_BIT(18)
736	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
737	/** Bit 29 - NW - Not Write-though. */
738	#define X86_CR0_NW RT_BIT(29)
739	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
740	/** Bit 30 - WP - Cache Disable. */
741	#define X86_CR0_CD RT_BIT(30)
742	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
743	/** Bit 31 - PG - Paging. */
744	#define X86_CR0_PG RT_BIT(31)
745	#define X86_CR0_PAGING RT_BIT(31)
746	/** @} */
747
748
749	/** @name CR3
750	* @{ */
751	/** Bit 3 - PWT - Page-level Writes Transparent. */
752	#define X86_CR3_PWT RT_BIT(3)
753	/** Bit 4 - PCD - Page-level Cache Disable. */
754	#define X86_CR3_PCD RT_BIT(4)
755	/** Bits 12-31 - - Page directory page number. */
756	#define X86_CR3_PAGE_MASK (0xfffff000)
757	/** Bits 5-31 - - PAE Page directory page number. */
758	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
759	/** Bits 12-51 - - AMD64 Page directory page number. */
760	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
761	/** @} */
762
763
764	/** @name CR4
765	* @{ */
766	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
767	#define X86_CR4_VME RT_BIT(0)
768	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
769	#define X86_CR4_PVI RT_BIT(1)
770	/** Bit 2 - TSD - Time Stamp Disable. */
771	#define X86_CR4_TSD RT_BIT(2)
772	/** Bit 3 - DE - Debugging Extensions. */
773	#define X86_CR4_DE RT_BIT(3)
774	/** Bit 4 - PSE - Page Size Extension. */
775	#define X86_CR4_PSE RT_BIT(4)
776	/** Bit 5 - PAE - Physical Address Extension. */
777	#define X86_CR4_PAE RT_BIT(5)
778	/** Bit 6 - MCE - Machine-Check Enable. */
779	#define X86_CR4_MCE RT_BIT(6)
780	/** Bit 7 - PGE - Page Global Enable. */
781	#define X86_CR4_PGE RT_BIT(7)
782	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
783	#define X86_CR4_PCE RT_BIT(8)
784	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
785	#define X86_CR4_OSFSXR RT_BIT(9)
786	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
787	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
788	/** Bit 13 - VMXE - VMX mode is enabled. */
789	#define X86_CR4_VMXE RT_BIT(13)
790	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
791	#define X86_CR4_SMXE RT_BIT(14)
792	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
793	#define X86_CR4_PCIDE RT_BIT(17)
794	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
795	* extended states. */
796	#define X86_CR4_OSXSAVE RT_BIT(18)
797	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
798	#define X86_CR4_SMEP RT_BIT(20)
799	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
800	#define X86_CR4_SMAP RT_BIT(21)
801	/** @} */
802
803
804	/** @name DR6
805	* @{ */
806	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
807	#define X86_DR6_B0 RT_BIT(0)
808	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
809	#define X86_DR6_B1 RT_BIT(1)
810	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
811	#define X86_DR6_B2 RT_BIT(2)
812	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
813	#define X86_DR6_B3 RT_BIT(3)
814	/** Mask of all the Bx bits. */
815	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
816	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
817	#define X86_DR6_BD RT_BIT(13)
818	/** Bit 14 - BS - Single step */
819	#define X86_DR6_BS RT_BIT(14)
820	/** Bit 15 - BT - Task switch. (TSS T bit.) */
821	#define X86_DR6_BT RT_BIT(15)
822	/** Value of DR6 after powerup/reset. */
823	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
824	/** Bits which must be 1s in DR6. */
825	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
826	/** Bits which must be 0s in DR6. */
827	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
828	/** Bits which must be 0s on writes to DR6. */
829	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
830	/** @} */
831
832	/** Get the DR6.Bx bit for a the given breakpoint. */
833	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
834
835
836	/** @name DR7
837	* @{ */
838	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
839	#define X86_DR7_L0 RT_BIT(0)
840	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
841	#define X86_DR7_G0 RT_BIT(1)
842	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
843	#define X86_DR7_L1 RT_BIT(2)
844	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
845	#define X86_DR7_G1 RT_BIT(3)
846	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
847	#define X86_DR7_L2 RT_BIT(4)
848	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
849	#define X86_DR7_G2 RT_BIT(5)
850	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
851	#define X86_DR7_L3 RT_BIT(6)
852	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
853	#define X86_DR7_G3 RT_BIT(7)
854	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
855	#define X86_DR7_LE RT_BIT(8)
856	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
857	#define X86_DR7_GE RT_BIT(9)
858
859	/** L0, L1, L2, and L3. */
860	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
861	/** L0, L1, L2, and L3. */
862	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
863
864	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
865	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
866	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
867	* instruction is executed.
868	* @see http://www.rcollins.org/secrets/DR7.html */
869	#define X86_DR7_ICE_IR RT_BIT(12)
870	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
871	* any DR register is accessed. */
872	#define X86_DR7_GD RT_BIT(13)
873	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
874	* Pentium. */
875	#define X86_DR7_ICE_TR1 RT_BIT(14)
876	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
877	#define X86_DR7_ICE_TR2 RT_BIT(15)
878	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
879	#define X86_DR7_RW0_MASK (3 << 16)
880	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
881	#define X86_DR7_LEN0_MASK (3 << 18)
882	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
883	#define X86_DR7_RW1_MASK (3 << 20)
884	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
885	#define X86_DR7_LEN1_MASK (3 << 22)
886	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
887	#define X86_DR7_RW2_MASK (3 << 24)
888	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
889	#define X86_DR7_LEN2_MASK (3 << 26)
890	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
891	#define X86_DR7_RW3_MASK (3 << 28)
892	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
893	#define X86_DR7_LEN3_MASK (3 << 30)
894
895	/** Bits which reads as 1s. */
896	#define X86_DR7_RA1_MASK (RT_BIT(10))
897	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
898	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
899	/** Bits which must be 0s when writing to DR7. */
900	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
901
902	/** Calcs the L bit of Nth breakpoint.
903	* @param iBp The breakpoint number [0..3].
904	*/
905	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
906
907	/** Calcs the G bit of Nth breakpoint.
908	* @param iBp The breakpoint number [0..3].
909	*/
910	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
911
912	/** Calcs the L and G bits of Nth breakpoint.
913	* @param iBp The breakpoint number [0..3].
914	*/
915	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
916
917	/** @name Read/Write values.
918	* @{ */
919	/** Break on instruction fetch only. */
920	#define X86_DR7_RW_EO 0U
921	/** Break on write only. */
922	#define X86_DR7_RW_WO 1U
923	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
924	#define X86_DR7_RW_IO 2U
925	/** Break on read or write (but not instruction fetches). */
926	#define X86_DR7_RW_RW 3U
927	/** @} */
928
929	/** Shifts a X86_DR7_RW_* value to its right place.
930	* @param iBp The breakpoint number [0..3].
931	* @param fRw One of the X86_DR7_RW_* value.
932	*/
933	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
934
935	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
936	* one of the X86_DR7_RW_XXX constants).
937	*
938	* @returns X86_DR7_RW_XXX
939	* @param uDR7 DR7 value
940	* @param iBp The breakpoint number [0..3].
941	*/
942	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
943
944	/** R/W0, R/W1, R/W2, and R/W3. */
945	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
946
947	#ifndef VBOX_FOR_DTRACE_LIB
948	/** Checks if there are any I/O breakpoint types configured in the RW
949	* registers. Does NOT check if these are enabled, sorry. */
950	# define X86_DR7_ANY_RW_IO(uDR7) \
951	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
952	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
953	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
954	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
955	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
956	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
957	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
958	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
959	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
960	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
961	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
962	#endif /* !VBOX_FOR_DTRACE_LIB */
963
964	/** @name Length values.
965	* @{ */
966	#define X86_DR7_LEN_BYTE 0U
967	#define X86_DR7_LEN_WORD 1U
968	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
969	#define X86_DR7_LEN_DWORD 3U
970	/** @} */
971
972	/** Shifts a X86_DR7_LEN_* value to its right place.
973	* @param iBp The breakpoint number [0..3].
974	* @param cb One of the X86_DR7_LEN_* values.
975	*/
976	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
977
978	/** Fetch the breakpoint length bits from the DR7 value.
979	* @param uDR7 DR7 value
980	* @param iBp The breakpoint number [0..3].
981	*/
982	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
983
984	/** Mask used to check if any breakpoints are enabled. */
985	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
986
987	/** LEN0, LEN1, LEN2, and LEN3. */
988	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
989	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
990	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
991
992	/** Value of DR7 after powerup/reset. */
993	#define X86_DR7_INIT_VAL 0x400
994	/** @} */
995
996
997	/** @name Machine Specific Registers
998	* @{
999	*/
1000	/** Machine check address register (P5). */
1001	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1002	/** Machine check type register (P5). */
1003	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1004	/** Time Stamp Counter. */
1005	#define MSR_IA32_TSC 0x10
1006	#define MSR_IA32_CESR UINT32_C(0x00000011)
1007	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1008	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1009
1010	#define MSR_IA32_PLATFORM_ID 0x17
1011
1012	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1013	# define MSR_IA32_APICBASE 0x1b
1014	/** Local APIC enabled. */
1015	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1016	/** X2APIC enabled (requires the EN bit to be set). */
1017	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1018	/** The processor is the boot strap processor (BSP). */
1019	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1020	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1021	* width. */
1022	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1023	#endif
1024
1025	/** Undocumented intel MSR for reporting thread and core counts.
1026	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1027	* first 16 bits is the thread count. The next 16 bits the core count, except
1028	* on Westmere where it seems it's only the next 4 bits for some reason. */
1029	#define MSR_CORE_THREAD_COUNT 0x35
1030
1031	/** CPU Feature control. */
1032	#define MSR_IA32_FEATURE_CONTROL 0x3A
1033	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
1034	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
1035	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
1036
1037	/** Per-processor TSC adjust MSR. */
1038	#define MSR_IA32_TSC_ADJUST 0x3B
1039
1040	/** BIOS update trigger (microcode update). */
1041	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1042
1043	/** BIOS update signature (microcode). */
1044	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1045
1046	/** General performance counter no. 0. */
1047	#define MSR_IA32_PMC0 0xC1
1048	/** General performance counter no. 1. */
1049	#define MSR_IA32_PMC1 0xC2
1050	/** General performance counter no. 2. */
1051	#define MSR_IA32_PMC2 0xC3
1052	/** General performance counter no. 3. */
1053	#define MSR_IA32_PMC3 0xC4
1054
1055	/** Nehalem power control. */
1056	#define MSR_IA32_PLATFORM_INFO 0xCE
1057
1058	/** Get FSB clock status (Intel-specific). */
1059	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1060
1061	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1062	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1063
1064	/** C0 Maximum Frequency Clock Count */
1065	#define MSR_IA32_MPERF 0xE7
1066	/** C0 Actual Frequency Clock Count */
1067	#define MSR_IA32_APERF 0xE8
1068
1069	/** MTRR Capabilities. */
1070	#define MSR_IA32_MTRR_CAP 0xFE
1071
1072	/** Cache control/info. */
1073	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1074
1075	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1076	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1077	* R0 SS == CS + 8
1078	* R3 CS == CS + 16
1079	* R3 SS == CS + 24
1080	*/
1081	#define MSR_IA32_SYSENTER_CS 0x174
1082	/** SYSENTER_ESP - the R0 ESP. */
1083	#define MSR_IA32_SYSENTER_ESP 0x175
1084	/** SYSENTER_EIP - the R0 EIP. */
1085	#define MSR_IA32_SYSENTER_EIP 0x176
1086	#endif
1087
1088	/** Machine Check Global Capabilities Register. */
1089	#define MSR_IA32_MCG_CAP 0x179
1090	/** Machine Check Global Status Register. */
1091	#define MSR_IA32_MCG_STATUS 0x17A
1092	/** Machine Check Global Control Register. */
1093	#define MSR_IA32_MCG_CTRL 0x17B
1094
1095	/** Page Attribute Table. */
1096	#define MSR_IA32_CR_PAT 0x277
1097
1098	/** Performance counter MSRs. (Intel only) */
1099	#define MSR_IA32_PERFEVTSEL0 0x186
1100	#define MSR_IA32_PERFEVTSEL1 0x187
1101	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1102	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1103	* holds a ratio that Apple takes for TSC granularity.
1104	*
1105	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1106	#define MSR_FLEX_RATIO 0x194
1107	/** Performance state value and starting with Intel core more.
1108	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1109	#define MSR_IA32_PERF_STATUS 0x198
1110	#define MSR_IA32_PERF_CTL 0x199
1111	#define MSR_IA32_THERM_STATUS 0x19c
1112
1113	/** Enable misc. processor features (R/W). */
1114	#define MSR_IA32_MISC_ENABLE 0x1A0
1115	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1116	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1117	/** Automatic Thermal Control Circuit Enable (R/W). */
1118	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1119	/** Performance Monitoring Available (R). */
1120	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1121	/** Branch Trace Storage Unavailable (R/O). */
1122	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1123	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1124	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1125	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1126	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1127	/** If MONITOR/MWAIT is supported (R/W). */
1128	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1129	/** Limit CPUID Maxval to 3 leafs (R/W). */
1130	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1131	/** When set to 1, xTPR messages are disabled (R/W). */
1132	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1133	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1134	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1135
1136	/** Trace/Profile Resource Control (R/W) */
1137	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1138	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1139	* related Xeons. */
1140	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1141	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1142	* @{ */
1143	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1144	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1145	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1146	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1147	/** @} */
1148
1149
1150	#define IA32_MTRR_PHYSBASE0 0x200
1151	#define IA32_MTRR_PHYSMASK0 0x201
1152	#define IA32_MTRR_PHYSBASE1 0x202
1153	#define IA32_MTRR_PHYSMASK1 0x203
1154	#define IA32_MTRR_PHYSBASE2 0x204
1155	#define IA32_MTRR_PHYSMASK2 0x205
1156	#define IA32_MTRR_PHYSBASE3 0x206
1157	#define IA32_MTRR_PHYSMASK3 0x207
1158	#define IA32_MTRR_PHYSBASE4 0x208
1159	#define IA32_MTRR_PHYSMASK4 0x209
1160	#define IA32_MTRR_PHYSBASE5 0x20a
1161	#define IA32_MTRR_PHYSMASK5 0x20b
1162	#define IA32_MTRR_PHYSBASE6 0x20c
1163	#define IA32_MTRR_PHYSMASK6 0x20d
1164	#define IA32_MTRR_PHYSBASE7 0x20e
1165	#define IA32_MTRR_PHYSMASK7 0x20f
1166	#define IA32_MTRR_PHYSBASE8 0x210
1167	#define IA32_MTRR_PHYSMASK8 0x211
1168	#define IA32_MTRR_PHYSBASE9 0x212
1169	#define IA32_MTRR_PHYSMASK9 0x213
1170
1171	/** Fixed range MTRRs.
1172	* @{ */
1173	#define IA32_MTRR_FIX64K_00000 0x250
1174	#define IA32_MTRR_FIX16K_80000 0x258
1175	#define IA32_MTRR_FIX16K_A0000 0x259
1176	#define IA32_MTRR_FIX4K_C0000 0x268
1177	#define IA32_MTRR_FIX4K_C8000 0x269
1178	#define IA32_MTRR_FIX4K_D0000 0x26a
1179	#define IA32_MTRR_FIX4K_D8000 0x26b
1180	#define IA32_MTRR_FIX4K_E0000 0x26c
1181	#define IA32_MTRR_FIX4K_E8000 0x26d
1182	#define IA32_MTRR_FIX4K_F0000 0x26e
1183	#define IA32_MTRR_FIX4K_F8000 0x26f
1184	/** @} */
1185
1186	/** MTRR Default Range. */
1187	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1188
1189	#define MSR_IA32_MC0_CTL 0x400
1190	#define MSR_IA32_MC0_STATUS 0x401
1191
1192	/** Basic VMX information. */
1193	#define MSR_IA32_VMX_BASIC_INFO 0x480
1194	/** Allowed settings for pin-based VM execution controls */
1195	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1196	/** Allowed settings for proc-based VM execution controls */
1197	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1198	/** Allowed settings for the VMX exit controls. */
1199	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1200	/** Allowed settings for the VMX entry controls. */
1201	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1202	/** Misc VMX info. */
1203	#define MSR_IA32_VMX_MISC 0x485
1204	/** Fixed cleared bits in CR0. */
1205	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1206	/** Fixed set bits in CR0. */
1207	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1208	/** Fixed cleared bits in CR4. */
1209	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1210	/** Fixed set bits in CR4. */
1211	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1212	/** Information for enumerating fields in the VMCS. */
1213	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1214	/** Allowed settings for the VM-functions controls. */
1215	#define MSR_IA32_VMX_VMFUNC 0x491
1216	/** Allowed settings for secondary proc-based VM execution controls */
1217	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1218	/** EPT capabilities. */
1219	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1220	/** DS Save Area (R/W). */
1221	#define MSR_IA32_DS_AREA 0x600
1222	/** Running Average Power Limit (RAPL) power units. */
1223	#define MSR_RAPL_POWER_UNIT 0x606
1224	/** X2APIC MSR ranges. */
1225	#define MSR_IA32_X2APIC_START 0x800
1226	#define MSR_IA32_X2APIC_TPR 0x808
1227	#define MSR_IA32_X2APIC_END 0xBFF
1228
1229	/** K6 EFER - Extended Feature Enable Register. */
1230	#define MSR_K6_EFER UINT32_C(0xc0000080)
1231	/** @todo document EFER */
1232	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1233	#define MSR_K6_EFER_SCE RT_BIT(0)
1234	/** Bit 8 - LME - Long mode enabled. (R/W) */
1235	#define MSR_K6_EFER_LME RT_BIT(8)
1236	/** Bit 10 - LMA - Long mode active. (R) */
1237	#define MSR_K6_EFER_LMA RT_BIT(10)
1238	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1239	#define MSR_K6_EFER_NXE RT_BIT(11)
1240	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1241	#define MSR_K6_EFER_SVME RT_BIT(12)
1242	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1243	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1244	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1245	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1246	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1247	#define MSR_K6_EFER_TCE RT_BIT(15)
1248	/** K6 STAR - SYSCALL/RET targets. */
1249	#define MSR_K6_STAR UINT32_C(0xc0000081)
1250	/** Shift value for getting the SYSRET CS and SS value. */
1251	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1252	/** Shift value for getting the SYSCALL CS and SS value. */
1253	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1254	/** Selector mask for use after shifting. */
1255	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1256	/** The mask which give the SYSCALL EIP. */
1257	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1258	/** K6 WHCR - Write Handling Control Register. */
1259	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1260	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1261	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1262	/** K6 PSOR - Processor State Observability Register. */
1263	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1264	/** K6 PFIR - Page Flush/Invalidate Register. */
1265	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1266
1267	/** Performance counter MSRs. (AMD only) */
1268	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1269	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1270	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1271	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1272	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1273	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1274	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1275	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1276
1277	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1278	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1279	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1280	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1281	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1282	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1283	/** K8 FS.base - The 64-bit base FS register. */
1284	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1285	/** K8 GS.base - The 64-bit base GS register. */
1286	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1287	/** K8 KernelGSbase - Used with SWAPGS. */
1288	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1289	/** K8 TSC_AUX - Used with RDTSCP. */
1290	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1291	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1292	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1293	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1294	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1295	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1296	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1297	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1298	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1299	/** North bridge config? See BIOS & Kernel dev guides for
1300	* details. */
1301	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1302
1303	/** Hypertransport interrupt pending register.
1304	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1305	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1306	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1307	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1308
1309	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1310	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1311	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1312	* host state during world switch. */
1313	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1314
1315	/** @} */
1316
1317
1318	/** @name Page Table / Directory / Directory Pointers / L4.
1319	* @{
1320	*/
1321
1322	/** Page table/directory entry as an unsigned integer. */
1323	typedef uint32_t X86PGUINT;
1324	/** Pointer to a page table/directory table entry as an unsigned integer. */
1325	typedef X86PGUINT *PX86PGUINT;
1326	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1327	typedef X86PGUINT const *PCX86PGUINT;
1328
1329	/** Number of entries in a 32-bit PT/PD. */
1330	#define X86_PG_ENTRIES 1024
1331
1332
1333	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1334	typedef uint64_t X86PGPAEUINT;
1335	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1336	typedef X86PGPAEUINT *PX86PGPAEUINT;
1337	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1338	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1339
1340	/** Number of entries in a PAE PT/PD. */
1341	#define X86_PG_PAE_ENTRIES 512
1342	/** Number of entries in a PAE PDPT. */
1343	#define X86_PG_PAE_PDPE_ENTRIES 4
1344
1345	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1346	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1347	/** Number of entries in an AMD64 PDPT.
1348	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1349	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1350
1351	/** The size of a 4KB page. */
1352	#define X86_PAGE_4K_SIZE _4K
1353	/** The page shift of a 4KB page. */
1354	#define X86_PAGE_4K_SHIFT 12
1355	/** The 4KB page offset mask. */
1356	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1357	/** The 4KB page base mask for virtual addresses. */
1358	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1359	/** The 4KB page base mask for virtual addresses - 32bit version. */
1360	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1361
1362	/** The size of a 2MB page. */
1363	#define X86_PAGE_2M_SIZE _2M
1364	/** The page shift of a 2MB page. */
1365	#define X86_PAGE_2M_SHIFT 21
1366	/** The 2MB page offset mask. */
1367	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1368	/** The 2MB page base mask for virtual addresses. */
1369	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1370	/** The 2MB page base mask for virtual addresses - 32bit version. */
1371	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1372
1373	/** The size of a 4MB page. */
1374	#define X86_PAGE_4M_SIZE _4M
1375	/** The page shift of a 4MB page. */
1376	#define X86_PAGE_4M_SHIFT 22
1377	/** The 4MB page offset mask. */
1378	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1379	/** The 4MB page base mask for virtual addresses. */
1380	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1381	/** The 4MB page base mask for virtual addresses - 32bit version. */
1382	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1383
1384	/**
1385	* Check if the given address is canonical.
1386	*/
1387	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1388
1389
1390	/** @name Page Table Entry
1391	* @{
1392	*/
1393	/** Bit 0 - P - Present bit. */
1394	#define X86_PTE_BIT_P 0
1395	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1396	#define X86_PTE_BIT_RW 1
1397	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1398	#define X86_PTE_BIT_US 2
1399	/** Bit 3 - PWT - Page level write thru bit. */
1400	#define X86_PTE_BIT_PWT 3
1401	/** Bit 4 - PCD - Page level cache disable bit. */
1402	#define X86_PTE_BIT_PCD 4
1403	/** Bit 5 - A - Access bit. */
1404	#define X86_PTE_BIT_A 5
1405	/** Bit 6 - D - Dirty bit. */
1406	#define X86_PTE_BIT_D 6
1407	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1408	#define X86_PTE_BIT_PAT 7
1409	/** Bit 8 - G - Global flag. */
1410	#define X86_PTE_BIT_G 8
1411
1412	/** Bit 0 - P - Present bit mask. */
1413	#define X86_PTE_P RT_BIT(0)
1414	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1415	#define X86_PTE_RW RT_BIT(1)
1416	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1417	#define X86_PTE_US RT_BIT(2)
1418	/** Bit 3 - PWT - Page level write thru bit mask. */
1419	#define X86_PTE_PWT RT_BIT(3)
1420	/** Bit 4 - PCD - Page level cache disable bit mask. */
1421	#define X86_PTE_PCD RT_BIT(4)
1422	/** Bit 5 - A - Access bit mask. */
1423	#define X86_PTE_A RT_BIT(5)
1424	/** Bit 6 - D - Dirty bit mask. */
1425	#define X86_PTE_D RT_BIT(6)
1426	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1427	#define X86_PTE_PAT RT_BIT(7)
1428	/** Bit 8 - G - Global bit mask. */
1429	#define X86_PTE_G RT_BIT(8)
1430
1431	/** Bits 9-11 - - Available for use to system software. */
1432	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1433	/** Bits 12-31 - - Physical Page number of the next level. */
1434	#define X86_PTE_PG_MASK ( 0xfffff000 )
1435
1436	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1437	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1438	/** Bits 63 - NX - PAE/LM - No execution flag. */
1439	#define X86_PTE_PAE_NX RT_BIT_64(63)
1440	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1441	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1442	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1443	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1444	/** No bits - - LM - MBZ bits when NX is active. */
1445	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1446	/** Bits 63 - - LM - MBZ bits when no NX. */
1447	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1448
1449	/**
1450	* Page table entry.
1451	*/
1452	typedef struct X86PTEBITS
1453	{
1454	/** Flags whether(=1) or not the page is present. */
1455	unsigned u1Present : 1;
1456	/** Read(=0) / Write(=1) flag. */
1457	unsigned u1Write : 1;
1458	/** User(=1) / Supervisor (=0) flag. */
1459	unsigned u1User : 1;
1460	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1461	unsigned u1WriteThru : 1;
1462	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1463	unsigned u1CacheDisable : 1;
1464	/** Accessed flag.
1465	* Indicates that the page have been read or written to. */
1466	unsigned u1Accessed : 1;
1467	/** Dirty flag.
1468	* Indicates that the page has been written to. */
1469	unsigned u1Dirty : 1;
1470	/** Reserved / If PAT enabled, bit 2 of the index. */
1471	unsigned u1PAT : 1;
1472	/** Global flag. (Ignored in all but final level.) */
1473	unsigned u1Global : 1;
1474	/** Available for use to system software. */
1475	unsigned u3Available : 3;
1476	/** Physical Page number of the next level. */
1477	unsigned u20PageNo : 20;
1478	} X86PTEBITS;
1479	/** Pointer to a page table entry. */
1480	typedef X86PTEBITS *PX86PTEBITS;
1481	/** Pointer to a const page table entry. */
1482	typedef const X86PTEBITS *PCX86PTEBITS;
1483
1484	/**
1485	* Page table entry.
1486	*/
1487	typedef union X86PTE
1488	{
1489	/** Unsigned integer view */
1490	X86PGUINT u;
1491	/** Bit field view. */
1492	X86PTEBITS n;
1493	/** 32-bit view. */
1494	uint32_t au32[1];
1495	/** 16-bit view. */
1496	uint16_t au16[2];
1497	/** 8-bit view. */
1498	uint8_t au8[4];
1499	} X86PTE;
1500	/** Pointer to a page table entry. */
1501	typedef X86PTE *PX86PTE;
1502	/** Pointer to a const page table entry. */
1503	typedef const X86PTE *PCX86PTE;
1504
1505
1506	/**
1507	* PAE page table entry.
1508	*/
1509	typedef struct X86PTEPAEBITS
1510	{
1511	/** Flags whether(=1) or not the page is present. */
1512	uint32_t u1Present : 1;
1513	/** Read(=0) / Write(=1) flag. */
1514	uint32_t u1Write : 1;
1515	/** User(=1) / Supervisor(=0) flag. */
1516	uint32_t u1User : 1;
1517	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1518	uint32_t u1WriteThru : 1;
1519	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1520	uint32_t u1CacheDisable : 1;
1521	/** Accessed flag.
1522	* Indicates that the page have been read or written to. */
1523	uint32_t u1Accessed : 1;
1524	/** Dirty flag.
1525	* Indicates that the page has been written to. */
1526	uint32_t u1Dirty : 1;
1527	/** Reserved / If PAT enabled, bit 2 of the index. */
1528	uint32_t u1PAT : 1;
1529	/** Global flag. (Ignored in all but final level.) */
1530	uint32_t u1Global : 1;
1531	/** Available for use to system software. */
1532	uint32_t u3Available : 3;
1533	/** Physical Page number of the next level - Low Part. Don't use this. */
1534	uint32_t u20PageNoLow : 20;
1535	/** Physical Page number of the next level - High Part. Don't use this. */
1536	uint32_t u20PageNoHigh : 20;
1537	/** MBZ bits */
1538	uint32_t u11Reserved : 11;
1539	/** No Execute flag. */
1540	uint32_t u1NoExecute : 1;
1541	} X86PTEPAEBITS;
1542	/** Pointer to a page table entry. */
1543	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1544	/** Pointer to a page table entry. */
1545	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1546
1547	/**
1548	* PAE Page table entry.
1549	*/
1550	typedef union X86PTEPAE
1551	{
1552	/** Unsigned integer view */
1553	X86PGPAEUINT u;
1554	/** Bit field view. */
1555	X86PTEPAEBITS n;
1556	/** 32-bit view. */
1557	uint32_t au32[2];
1558	/** 16-bit view. */
1559	uint16_t au16[4];
1560	/** 8-bit view. */
1561	uint8_t au8[8];
1562	} X86PTEPAE;
1563	/** Pointer to a PAE page table entry. */
1564	typedef X86PTEPAE *PX86PTEPAE;
1565	/** Pointer to a const PAE page table entry. */
1566	typedef const X86PTEPAE *PCX86PTEPAE;
1567	/** @} */
1568
1569	/**
1570	* Page table.
1571	*/
1572	typedef struct X86PT
1573	{
1574	/** PTE Array. */
1575	X86PTE a[X86_PG_ENTRIES];
1576	} X86PT;
1577	/** Pointer to a page table. */
1578	typedef X86PT *PX86PT;
1579	/** Pointer to a const page table. */
1580	typedef const X86PT *PCX86PT;
1581
1582	/** The page shift to get the PT index. */
1583	#define X86_PT_SHIFT 12
1584	/** The PT index mask (apply to a shifted page address). */
1585	#define X86_PT_MASK 0x3ff
1586
1587
1588	/**
1589	* Page directory.
1590	*/
1591	typedef struct X86PTPAE
1592	{
1593	/** PTE Array. */
1594	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1595	} X86PTPAE;
1596	/** Pointer to a page table. */
1597	typedef X86PTPAE *PX86PTPAE;
1598	/** Pointer to a const page table. */
1599	typedef const X86PTPAE *PCX86PTPAE;
1600
1601	/** The page shift to get the PA PTE index. */
1602	#define X86_PT_PAE_SHIFT 12
1603	/** The PAE PT index mask (apply to a shifted page address). */
1604	#define X86_PT_PAE_MASK 0x1ff
1605
1606
1607	/** @name 4KB Page Directory Entry
1608	* @{
1609	*/
1610	/** Bit 0 - P - Present bit. */
1611	#define X86_PDE_P RT_BIT(0)
1612	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1613	#define X86_PDE_RW RT_BIT(1)
1614	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1615	#define X86_PDE_US RT_BIT(2)
1616	/** Bit 3 - PWT - Page level write thru bit. */
1617	#define X86_PDE_PWT RT_BIT(3)
1618	/** Bit 4 - PCD - Page level cache disable bit. */
1619	#define X86_PDE_PCD RT_BIT(4)
1620	/** Bit 5 - A - Access bit. */
1621	#define X86_PDE_A RT_BIT(5)
1622	/** Bit 7 - PS - Page size attribute.
1623	* Clear mean 4KB pages, set means large pages (2/4MB). */
1624	#define X86_PDE_PS RT_BIT(7)
1625	/** Bits 9-11 - - Available for use to system software. */
1626	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1627	/** Bits 12-31 - - Physical Page number of the next level. */
1628	#define X86_PDE_PG_MASK ( 0xfffff000 )
1629
1630	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1631	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1632	/** Bits 63 - NX - PAE/LM - No execution flag. */
1633	#define X86_PDE_PAE_NX RT_BIT_64(63)
1634	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1635	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1636	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1637	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1638	/** Bit 7 - - LM - MBZ bits when NX is active. */
1639	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1640	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1641	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1642
1643	/**
1644	* Page directory entry.
1645	*/
1646	typedef struct X86PDEBITS
1647	{
1648	/** Flags whether(=1) or not the page is present. */
1649	unsigned u1Present : 1;
1650	/** Read(=0) / Write(=1) flag. */
1651	unsigned u1Write : 1;
1652	/** User(=1) / Supervisor (=0) flag. */
1653	unsigned u1User : 1;
1654	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1655	unsigned u1WriteThru : 1;
1656	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1657	unsigned u1CacheDisable : 1;
1658	/** Accessed flag.
1659	* Indicates that the page has been read or written to. */
1660	unsigned u1Accessed : 1;
1661	/** Reserved / Ignored (dirty bit). */
1662	unsigned u1Reserved0 : 1;
1663	/** Size bit if PSE is enabled - in any event it's 0. */
1664	unsigned u1Size : 1;
1665	/** Reserved / Ignored (global bit). */
1666	unsigned u1Reserved1 : 1;
1667	/** Available for use to system software. */
1668	unsigned u3Available : 3;
1669	/** Physical Page number of the next level. */
1670	unsigned u20PageNo : 20;
1671	} X86PDEBITS;
1672	/** Pointer to a page directory entry. */
1673	typedef X86PDEBITS *PX86PDEBITS;
1674	/** Pointer to a const page directory entry. */
1675	typedef const X86PDEBITS *PCX86PDEBITS;
1676
1677
1678	/**
1679	* PAE page directory entry.
1680	*/
1681	typedef struct X86PDEPAEBITS
1682	{
1683	/** Flags whether(=1) or not the page is present. */
1684	uint32_t u1Present : 1;
1685	/** Read(=0) / Write(=1) flag. */
1686	uint32_t u1Write : 1;
1687	/** User(=1) / Supervisor (=0) flag. */
1688	uint32_t u1User : 1;
1689	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1690	uint32_t u1WriteThru : 1;
1691	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1692	uint32_t u1CacheDisable : 1;
1693	/** Accessed flag.
1694	* Indicates that the page has been read or written to. */
1695	uint32_t u1Accessed : 1;
1696	/** Reserved / Ignored (dirty bit). */
1697	uint32_t u1Reserved0 : 1;
1698	/** Size bit if PSE is enabled - in any event it's 0. */
1699	uint32_t u1Size : 1;
1700	/** Reserved / Ignored (global bit). / */
1701	uint32_t u1Reserved1 : 1;
1702	/** Available for use to system software. */
1703	uint32_t u3Available : 3;
1704	/** Physical Page number of the next level - Low Part. Don't use! */
1705	uint32_t u20PageNoLow : 20;
1706	/** Physical Page number of the next level - High Part. Don't use! */
1707	uint32_t u20PageNoHigh : 20;
1708	/** MBZ bits */
1709	uint32_t u11Reserved : 11;
1710	/** No Execute flag. */
1711	uint32_t u1NoExecute : 1;
1712	} X86PDEPAEBITS;
1713	/** Pointer to a page directory entry. */
1714	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1715	/** Pointer to a const page directory entry. */
1716	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1717
1718	/** @} */
1719
1720
1721	/** @name 2/4MB Page Directory Entry
1722	* @{
1723	*/
1724	/** Bit 0 - P - Present bit. */
1725	#define X86_PDE4M_P RT_BIT(0)
1726	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1727	#define X86_PDE4M_RW RT_BIT(1)
1728	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1729	#define X86_PDE4M_US RT_BIT(2)
1730	/** Bit 3 - PWT - Page level write thru bit. */
1731	#define X86_PDE4M_PWT RT_BIT(3)
1732	/** Bit 4 - PCD - Page level cache disable bit. */
1733	#define X86_PDE4M_PCD RT_BIT(4)
1734	/** Bit 5 - A - Access bit. */
1735	#define X86_PDE4M_A RT_BIT(5)
1736	/** Bit 6 - D - Dirty bit. */
1737	#define X86_PDE4M_D RT_BIT(6)
1738	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1739	#define X86_PDE4M_PS RT_BIT(7)
1740	/** Bit 8 - G - Global flag. */
1741	#define X86_PDE4M_G RT_BIT(8)
1742	/** Bits 9-11 - AVL - Available for use to system software. */
1743	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1744	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1745	#define X86_PDE4M_PAT RT_BIT(12)
1746	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1747	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1748	/** Bits 22-31 - - Physical Page number. */
1749	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1750	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1751	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1752	/** The number of bits to the high part of the page number. */
1753	#define X86_PDE4M_PG_HIGH_SHIFT 19
1754	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1755	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1756
1757	/** Bits 21-51 - - PAE/LM - Physical Page number.
1758	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1759	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1760	/** Bits 63 - NX - PAE/LM - No execution flag. */
1761	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1762	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1763	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1764	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1765	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1766	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1767	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1768	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1769	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1770
1771	/**
1772	* 4MB page directory entry.
1773	*/
1774	typedef struct X86PDE4MBITS
1775	{
1776	/** Flags whether(=1) or not the page is present. */
1777	unsigned u1Present : 1;
1778	/** Read(=0) / Write(=1) flag. */
1779	unsigned u1Write : 1;
1780	/** User(=1) / Supervisor (=0) flag. */
1781	unsigned u1User : 1;
1782	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1783	unsigned u1WriteThru : 1;
1784	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1785	unsigned u1CacheDisable : 1;
1786	/** Accessed flag.
1787	* Indicates that the page have been read or written to. */
1788	unsigned u1Accessed : 1;
1789	/** Dirty flag.
1790	* Indicates that the page has been written to. */
1791	unsigned u1Dirty : 1;
1792	/** Page size flag - always 1 for 4MB entries. */
1793	unsigned u1Size : 1;
1794	/** Global flag. */
1795	unsigned u1Global : 1;
1796	/** Available for use to system software. */
1797	unsigned u3Available : 3;
1798	/** Reserved / If PAT enabled, bit 2 of the index. */
1799	unsigned u1PAT : 1;
1800	/** Bits 32-39 of the page number on AMD64.
1801	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1802	unsigned u8PageNoHigh : 8;
1803	/** Reserved. */
1804	unsigned u1Reserved : 1;
1805	/** Physical Page number of the page. */
1806	unsigned u10PageNo : 10;
1807	} X86PDE4MBITS;
1808	/** Pointer to a page table entry. */
1809	typedef X86PDE4MBITS *PX86PDE4MBITS;
1810	/** Pointer to a const page table entry. */
1811	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1812
1813
1814	/**
1815	* 2MB PAE page directory entry.
1816	*/
1817	typedef struct X86PDE2MPAEBITS
1818	{
1819	/** Flags whether(=1) or not the page is present. */
1820	uint32_t u1Present : 1;
1821	/** Read(=0) / Write(=1) flag. */
1822	uint32_t u1Write : 1;
1823	/** User(=1) / Supervisor(=0) flag. */
1824	uint32_t u1User : 1;
1825	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1826	uint32_t u1WriteThru : 1;
1827	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1828	uint32_t u1CacheDisable : 1;
1829	/** Accessed flag.
1830	* Indicates that the page have been read or written to. */
1831	uint32_t u1Accessed : 1;
1832	/** Dirty flag.
1833	* Indicates that the page has been written to. */
1834	uint32_t u1Dirty : 1;
1835	/** Page size flag - always 1 for 2MB entries. */
1836	uint32_t u1Size : 1;
1837	/** Global flag. */
1838	uint32_t u1Global : 1;
1839	/** Available for use to system software. */
1840	uint32_t u3Available : 3;
1841	/** Reserved / If PAT enabled, bit 2 of the index. */
1842	uint32_t u1PAT : 1;
1843	/** Reserved. */
1844	uint32_t u9Reserved : 9;
1845	/** Physical Page number of the next level - Low part. Don't use! */
1846	uint32_t u10PageNoLow : 10;
1847	/** Physical Page number of the next level - High part. Don't use! */
1848	uint32_t u20PageNoHigh : 20;
1849	/** MBZ bits */
1850	uint32_t u11Reserved : 11;
1851	/** No Execute flag. */
1852	uint32_t u1NoExecute : 1;
1853	} X86PDE2MPAEBITS;
1854	/** Pointer to a 2MB PAE page table entry. */
1855	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1856	/** Pointer to a 2MB PAE page table entry. */
1857	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1858
1859	/** @} */
1860
1861	/**
1862	* Page directory entry.
1863	*/
1864	typedef union X86PDE
1865	{
1866	/** Unsigned integer view. */
1867	X86PGUINT u;
1868	/** Normal view. */
1869	X86PDEBITS n;
1870	/** 4MB view (big). */
1871	X86PDE4MBITS b;
1872	/** 8 bit unsigned integer view. */
1873	uint8_t au8[4];
1874	/** 16 bit unsigned integer view. */
1875	uint16_t au16[2];
1876	/** 32 bit unsigned integer view. */
1877	uint32_t au32[1];
1878	} X86PDE;
1879	/** Pointer to a page directory entry. */
1880	typedef X86PDE *PX86PDE;
1881	/** Pointer to a const page directory entry. */
1882	typedef const X86PDE *PCX86PDE;
1883
1884	/**
1885	* PAE page directory entry.
1886	*/
1887	typedef union X86PDEPAE
1888	{
1889	/** Unsigned integer view. */
1890	X86PGPAEUINT u;
1891	/** Normal view. */
1892	X86PDEPAEBITS n;
1893	/** 2MB page view (big). */
1894	X86PDE2MPAEBITS b;
1895	/** 8 bit unsigned integer view. */
1896	uint8_t au8[8];
1897	/** 16 bit unsigned integer view. */
1898	uint16_t au16[4];
1899	/** 32 bit unsigned integer view. */
1900	uint32_t au32[2];
1901	} X86PDEPAE;
1902	/** Pointer to a page directory entry. */
1903	typedef X86PDEPAE *PX86PDEPAE;
1904	/** Pointer to a const page directory entry. */
1905	typedef const X86PDEPAE *PCX86PDEPAE;
1906
1907	/**
1908	* Page directory.
1909	*/
1910	typedef struct X86PD
1911	{
1912	/** PDE Array. */
1913	X86PDE a[X86_PG_ENTRIES];
1914	} X86PD;
1915	/** Pointer to a page directory. */
1916	typedef X86PD *PX86PD;
1917	/** Pointer to a const page directory. */
1918	typedef const X86PD *PCX86PD;
1919
1920	/** The page shift to get the PD index. */
1921	#define X86_PD_SHIFT 22
1922	/** The PD index mask (apply to a shifted page address). */
1923	#define X86_PD_MASK 0x3ff
1924
1925
1926	/**
1927	* PAE page directory.
1928	*/
1929	typedef struct X86PDPAE
1930	{
1931	/** PDE Array. */
1932	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1933	} X86PDPAE;
1934	/** Pointer to a PAE page directory. */
1935	typedef X86PDPAE *PX86PDPAE;
1936	/** Pointer to a const PAE page directory. */
1937	typedef const X86PDPAE *PCX86PDPAE;
1938
1939	/** The page shift to get the PAE PD index. */
1940	#define X86_PD_PAE_SHIFT 21
1941	/** The PAE PD index mask (apply to a shifted page address). */
1942	#define X86_PD_PAE_MASK 0x1ff
1943
1944
1945	/** @name Page Directory Pointer Table Entry (PAE)
1946	* @{
1947	*/
1948	/** Bit 0 - P - Present bit. */
1949	#define X86_PDPE_P RT_BIT(0)
1950	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1951	#define X86_PDPE_RW RT_BIT(1)
1952	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1953	#define X86_PDPE_US RT_BIT(2)
1954	/** Bit 3 - PWT - Page level write thru bit. */
1955	#define X86_PDPE_PWT RT_BIT(3)
1956	/** Bit 4 - PCD - Page level cache disable bit. */
1957	#define X86_PDPE_PCD RT_BIT(4)
1958	/** Bit 5 - A - Access bit. Long Mode only. */
1959	#define X86_PDPE_A RT_BIT(5)
1960	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1961	#define X86_PDPE_LM_PS RT_BIT(7)
1962	/** Bits 9-11 - - Available for use to system software. */
1963	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1964	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1965	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1966	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1967	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1968	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1969	#define X86_PDPE_LM_NX RT_BIT_64(63)
1970	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1971	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1972	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1973	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1974	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1975	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1976	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1977	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1978
1979
1980	/**
1981	* Page directory pointer table entry.
1982	*/
1983	typedef struct X86PDPEBITS
1984	{
1985	/** Flags whether(=1) or not the page is present. */
1986	uint32_t u1Present : 1;
1987	/** Chunk of reserved bits. */
1988	uint32_t u2Reserved : 2;
1989	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1990	uint32_t u1WriteThru : 1;
1991	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1992	uint32_t u1CacheDisable : 1;
1993	/** Chunk of reserved bits. */
1994	uint32_t u4Reserved : 4;
1995	/** Available for use to system software. */
1996	uint32_t u3Available : 3;
1997	/** Physical Page number of the next level - Low Part. Don't use! */
1998	uint32_t u20PageNoLow : 20;
1999	/** Physical Page number of the next level - High Part. Don't use! */
2000	uint32_t u20PageNoHigh : 20;
2001	/** MBZ bits */
2002	uint32_t u12Reserved : 12;
2003	} X86PDPEBITS;
2004	/** Pointer to a page directory pointer table entry. */
2005	typedef X86PDPEBITS *PX86PTPEBITS;
2006	/** Pointer to a const page directory pointer table entry. */
2007	typedef const X86PDPEBITS *PCX86PTPEBITS;
2008
2009	/**
2010	* Page directory pointer table entry. AMD64 version
2011	*/
2012	typedef struct X86PDPEAMD64BITS
2013	{
2014	/** Flags whether(=1) or not the page is present. */
2015	uint32_t u1Present : 1;
2016	/** Read(=0) / Write(=1) flag. */
2017	uint32_t u1Write : 1;
2018	/** User(=1) / Supervisor (=0) flag. */
2019	uint32_t u1User : 1;
2020	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2021	uint32_t u1WriteThru : 1;
2022	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2023	uint32_t u1CacheDisable : 1;
2024	/** Accessed flag.
2025	* Indicates that the page have been read or written to. */
2026	uint32_t u1Accessed : 1;
2027	/** Chunk of reserved bits. */
2028	uint32_t u3Reserved : 3;
2029	/** Available for use to system software. */
2030	uint32_t u3Available : 3;
2031	/** Physical Page number of the next level - Low Part. Don't use! */
2032	uint32_t u20PageNoLow : 20;
2033	/** Physical Page number of the next level - High Part. Don't use! */
2034	uint32_t u20PageNoHigh : 20;
2035	/** MBZ bits */
2036	uint32_t u11Reserved : 11;
2037	/** No Execute flag. */
2038	uint32_t u1NoExecute : 1;
2039	} X86PDPEAMD64BITS;
2040	/** Pointer to a page directory pointer table entry. */
2041	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2042	/** Pointer to a const page directory pointer table entry. */
2043	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2044
2045	/**
2046	* Page directory pointer table entry.
2047	*/
2048	typedef union X86PDPE
2049	{
2050	/** Unsigned integer view. */
2051	X86PGPAEUINT u;
2052	/** Normal view. */
2053	X86PDPEBITS n;
2054	/** AMD64 view. */
2055	X86PDPEAMD64BITS lm;
2056	/** 8 bit unsigned integer view. */
2057	uint8_t au8[8];
2058	/** 16 bit unsigned integer view. */
2059	uint16_t au16[4];
2060	/** 32 bit unsigned integer view. */
2061	uint32_t au32[2];
2062	} X86PDPE;
2063	/** Pointer to a page directory pointer table entry. */
2064	typedef X86PDPE *PX86PDPE;
2065	/** Pointer to a const page directory pointer table entry. */
2066	typedef const X86PDPE *PCX86PDPE;
2067
2068
2069	/**
2070	* Page directory pointer table.
2071	*/
2072	typedef struct X86PDPT
2073	{
2074	/** PDE Array. */
2075	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2076	} X86PDPT;
2077	/** Pointer to a page directory pointer table. */
2078	typedef X86PDPT *PX86PDPT;
2079	/** Pointer to a const page directory pointer table. */
2080	typedef const X86PDPT *PCX86PDPT;
2081
2082	/** The page shift to get the PDPT index. */
2083	#define X86_PDPT_SHIFT 30
2084	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2085	#define X86_PDPT_MASK_PAE 0x3
2086	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2087	#define X86_PDPT_MASK_AMD64 0x1ff
2088
2089	/** @} */
2090
2091
2092	/** @name Page Map Level-4 Entry (Long Mode PAE)
2093	* @{
2094	*/
2095	/** Bit 0 - P - Present bit. */
2096	#define X86_PML4E_P RT_BIT(0)
2097	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2098	#define X86_PML4E_RW RT_BIT(1)
2099	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2100	#define X86_PML4E_US RT_BIT(2)
2101	/** Bit 3 - PWT - Page level write thru bit. */
2102	#define X86_PML4E_PWT RT_BIT(3)
2103	/** Bit 4 - PCD - Page level cache disable bit. */
2104	#define X86_PML4E_PCD RT_BIT(4)
2105	/** Bit 5 - A - Access bit. */
2106	#define X86_PML4E_A RT_BIT(5)
2107	/** Bits 9-11 - - Available for use to system software. */
2108	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2109	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2110	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2111	/** Bits 8, 7 - - MBZ bits when NX is active. */
2112	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2113	/** Bits 63, 7 - - MBZ bits when no NX. */
2114	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2115	/** Bits 63 - NX - PAE - No execution flag. */
2116	#define X86_PML4E_NX RT_BIT_64(63)
2117
2118	/**
2119	* Page Map Level-4 Entry
2120	*/
2121	typedef struct X86PML4EBITS
2122	{
2123	/** Flags whether(=1) or not the page is present. */
2124	uint32_t u1Present : 1;
2125	/** Read(=0) / Write(=1) flag. */
2126	uint32_t u1Write : 1;
2127	/** User(=1) / Supervisor (=0) flag. */
2128	uint32_t u1User : 1;
2129	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2130	uint32_t u1WriteThru : 1;
2131	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2132	uint32_t u1CacheDisable : 1;
2133	/** Accessed flag.
2134	* Indicates that the page have been read or written to. */
2135	uint32_t u1Accessed : 1;
2136	/** Chunk of reserved bits. */
2137	uint32_t u3Reserved : 3;
2138	/** Available for use to system software. */
2139	uint32_t u3Available : 3;
2140	/** Physical Page number of the next level - Low Part. Don't use! */
2141	uint32_t u20PageNoLow : 20;
2142	/** Physical Page number of the next level - High Part. Don't use! */
2143	uint32_t u20PageNoHigh : 20;
2144	/** MBZ bits */
2145	uint32_t u11Reserved : 11;
2146	/** No Execute flag. */
2147	uint32_t u1NoExecute : 1;
2148	} X86PML4EBITS;
2149	/** Pointer to a page map level-4 entry. */
2150	typedef X86PML4EBITS *PX86PML4EBITS;
2151	/** Pointer to a const page map level-4 entry. */
2152	typedef const X86PML4EBITS *PCX86PML4EBITS;
2153
2154	/**
2155	* Page Map Level-4 Entry.
2156	*/
2157	typedef union X86PML4E
2158	{
2159	/** Unsigned integer view. */
2160	X86PGPAEUINT u;
2161	/** Normal view. */
2162	X86PML4EBITS n;
2163	/** 8 bit unsigned integer view. */
2164	uint8_t au8[8];
2165	/** 16 bit unsigned integer view. */
2166	uint16_t au16[4];
2167	/** 32 bit unsigned integer view. */
2168	uint32_t au32[2];
2169	} X86PML4E;
2170	/** Pointer to a page map level-4 entry. */
2171	typedef X86PML4E *PX86PML4E;
2172	/** Pointer to a const page map level-4 entry. */
2173	typedef const X86PML4E *PCX86PML4E;
2174
2175
2176	/**
2177	* Page Map Level-4.
2178	*/
2179	typedef struct X86PML4
2180	{
2181	/** PDE Array. */
2182	X86PML4E a[X86_PG_PAE_ENTRIES];
2183	} X86PML4;
2184	/** Pointer to a page map level-4. */
2185	typedef X86PML4 *PX86PML4;
2186	/** Pointer to a const page map level-4. */
2187	typedef const X86PML4 *PCX86PML4;
2188
2189	/** The page shift to get the PML4 index. */
2190	#define X86_PML4_SHIFT 39
2191	/** The PML4 index mask (apply to a shifted page address). */
2192	#define X86_PML4_MASK 0x1ff
2193
2194	/** @} */
2195
2196	/** @} */
2197
2198	/**
2199	* 32-bit protected mode FSTENV image.
2200	*/
2201	typedef struct X86FSTENV32P
2202	{
2203	uint16_t FCW;
2204	uint16_t padding1;
2205	uint16_t FSW;
2206	uint16_t padding2;
2207	uint16_t FTW;
2208	uint16_t padding3;
2209	uint32_t FPUIP;
2210	uint16_t FPUCS;
2211	uint16_t FOP;
2212	uint32_t FPUDP;
2213	uint16_t FPUDS;
2214	uint16_t padding4;
2215	} X86FSTENV32P;
2216	/** Pointer to a 32-bit protected mode FSTENV image. */
2217	typedef X86FSTENV32P *PX86FSTENV32P;
2218	/** Pointer to a const 32-bit protected mode FSTENV image. */
2219	typedef X86FSTENV32P const *PCX86FSTENV32P;
2220
2221
2222	/**
2223	* 80-bit MMX/FPU register type.
2224	*/
2225	typedef struct X86FPUMMX
2226	{
2227	uint8_t reg[10];
2228	} X86FPUMMX;
2229	/** Pointer to a 80-bit MMX/FPU register type. */
2230	typedef X86FPUMMX *PX86FPUMMX;
2231	/** Pointer to a const 80-bit MMX/FPU register type. */
2232	typedef const X86FPUMMX *PCX86FPUMMX;
2233
2234	/**
2235	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2236	* @todo verify this...
2237	*/
2238	#pragma pack(1)
2239	typedef struct X86FPUSTATE
2240	{
2241	/** 0x00 - Control word. */
2242	uint16_t FCW;
2243	/** 0x02 - Alignment word */
2244	uint16_t Dummy1;
2245	/** 0x04 - Status word. */
2246	uint16_t FSW;
2247	/** 0x06 - Alignment word */
2248	uint16_t Dummy2;
2249	/** 0x08 - Tag word */
2250	uint16_t FTW;
2251	/** 0x0a - Alignment word */
2252	uint16_t Dummy3;
2253
2254	/** 0x0c - Instruction pointer. */
2255	uint32_t FPUIP;
2256	/** 0x10 - Code selector. */
2257	uint16_t CS;
2258	/** 0x12 - Opcode. */
2259	uint16_t FOP;
2260	/** 0x14 - FOO. */
2261	uint32_t FPUOO;
2262	/** 0x18 - FOS. */
2263	uint32_t FPUOS;
2264	/** 0x1c */
2265	union
2266	{
2267	/** MMX view. */
2268	uint64_t mmx;
2269	/** FPU view - todo. */
2270	X86FPUMMX fpu;
2271	/** Extended precision floating point view. */
2272	RTFLOAT80U r80;
2273	/** Extended precision floating point view v2. */
2274	RTFLOAT80U2 r80Ex;
2275	/** 8-bit view. */
2276	uint8_t au8[16];
2277	/** 16-bit view. */
2278	uint16_t au16[8];
2279	/** 32-bit view. */
2280	uint32_t au32[4];
2281	/** 64-bit view. */
2282	uint64_t au64[2];
2283	/** 128-bit view. (yeah, very helpful) */
2284	uint128_t au128[1];
2285	} regs[8];
2286	} X86FPUSTATE;
2287	#pragma pack()
2288	/** Pointer to a FPU state. */
2289	typedef X86FPUSTATE *PX86FPUSTATE;
2290	/** Pointer to a const FPU state. */
2291	typedef const X86FPUSTATE *PCX86FPUSTATE;
2292
2293	/**
2294	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2295	*/
2296	#pragma pack(1)
2297	typedef struct X86FXSTATE
2298	{
2299	/** 0x00 - Control word. */
2300	uint16_t FCW;
2301	/** 0x02 - Status word. */
2302	uint16_t FSW;
2303	/** 0x04 - Tag word. (The upper byte is always zero.) */
2304	uint16_t FTW;
2305	/** 0x06 - Opcode. */
2306	uint16_t FOP;
2307	/** 0x08 - Instruction pointer. */
2308	uint32_t FPUIP;
2309	/** 0x0c - Code selector. */
2310	uint16_t CS;
2311	uint16_t Rsrvd1;
2312	/** 0x10 - Data pointer. */
2313	uint32_t FPUDP;
2314	/** 0x14 - Data segment */
2315	uint16_t DS;
2316	/** 0x16 */
2317	uint16_t Rsrvd2;
2318	/** 0x18 */
2319	uint32_t MXCSR;
2320	/** 0x1c */
2321	uint32_t MXCSR_MASK;
2322	/** 0x20 */
2323	union
2324	{
2325	/** MMX view. */
2326	uint64_t mmx;
2327	/** FPU view - todo. */
2328	X86FPUMMX fpu;
2329	/** Extended precision floating point view. */
2330	RTFLOAT80U r80;
2331	/** Extended precision floating point view v2 */
2332	RTFLOAT80U2 r80Ex;
2333	/** 8-bit view. */
2334	uint8_t au8[16];
2335	/** 16-bit view. */
2336	uint16_t au16[8];
2337	/** 32-bit view. */
2338	uint32_t au32[4];
2339	/** 64-bit view. */
2340	uint64_t au64[2];
2341	/** 128-bit view. (yeah, very helpful) */
2342	uint128_t au128[1];
2343	} aRegs[8];
2344	/* - offset 160 - */
2345	union
2346	{
2347	/** XMM Register view . /
2348	uint128_t xmm;
2349	/** 8-bit view. */
2350	uint8_t au8[16];
2351	/** 16-bit view. */
2352	uint16_t au16[8];
2353	/** 32-bit view. */
2354	uint32_t au32[4];
2355	/** 64-bit view. */
2356	uint64_t au64[2];
2357	/** 128-bit view. (yeah, very helpful) */
2358	uint128_t au128[1];
2359	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2360	/* - offset 416 - */
2361	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2362	/* - offset 464 - Software usable reserved bits. */
2363	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2364	} X86FXSTATE;
2365	#pragma pack()
2366	/** Pointer to a FPU Extended state. */
2367	typedef X86FXSTATE *PX86FXSTATE;
2368	/** Pointer to a const FPU Extended state. */
2369	typedef const X86FXSTATE *PCX86FXSTATE;
2370
2371	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2372	* magic. Don't forget to update x86.mac if you change this! */
2373	#define X86_OFF_FXSTATE_RSVD 0x1d0
2374	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2375	* forget to update x86.mac if you change this! */
2376	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2377	#ifndef VBOX_FOR_DTRACE_LIB
2378	AssertCompileSize(X86FXSTATE, 512);
2379	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2380	#endif
2381
2382	/** @name FPU status word flags.
2383	* @{ */
2384	/** Exception Flag: Invalid operation. */
2385	#define X86_FSW_IE RT_BIT(0)
2386	/** Exception Flag: Denormalized operand. */
2387	#define X86_FSW_DE RT_BIT(1)
2388	/** Exception Flag: Zero divide. */
2389	#define X86_FSW_ZE RT_BIT(2)
2390	/** Exception Flag: Overflow. */
2391	#define X86_FSW_OE RT_BIT(3)
2392	/** Exception Flag: Underflow. */
2393	#define X86_FSW_UE RT_BIT(4)
2394	/** Exception Flag: Precision. */
2395	#define X86_FSW_PE RT_BIT(5)
2396	/** Stack fault. */
2397	#define X86_FSW_SF RT_BIT(6)
2398	/** Error summary status. */
2399	#define X86_FSW_ES RT_BIT(7)
2400	/** Mask of exceptions flags, excluding the summary bit. */
2401	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2402	/** Mask of exceptions flags, including the summary bit. */
2403	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2404	/** Condition code 0. */
2405	#define X86_FSW_C0 RT_BIT(8)
2406	/** Condition code 1. */
2407	#define X86_FSW_C1 RT_BIT(9)
2408	/** Condition code 2. */
2409	#define X86_FSW_C2 RT_BIT(10)
2410	/** Top of the stack mask. */
2411	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2412	/** TOP shift value. */
2413	#define X86_FSW_TOP_SHIFT 11
2414	/** Mask for getting TOP value after shifting it right. */
2415	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2416	/** Get the TOP value. */
2417	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2418	/** Condition code 3. */
2419	#define X86_FSW_C3 RT_BIT(14)
2420	/** Mask of exceptions flags, including the summary bit. */
2421	#define X86_FSW_C_MASK UINT16_C(0x4700)
2422	/** FPU busy. */
2423	#define X86_FSW_B RT_BIT(15)
2424	/** @} */
2425
2426
2427	/** @name FPU control word flags.
2428	* @{ */
2429	/** Exception Mask: Invalid operation. */
2430	#define X86_FCW_IM RT_BIT(0)
2431	/** Exception Mask: Denormalized operand. */
2432	#define X86_FCW_DM RT_BIT(1)
2433	/** Exception Mask: Zero divide. */
2434	#define X86_FCW_ZM RT_BIT(2)
2435	/** Exception Mask: Overflow. */
2436	#define X86_FCW_OM RT_BIT(3)
2437	/** Exception Mask: Underflow. */
2438	#define X86_FCW_UM RT_BIT(4)
2439	/** Exception Mask: Precision. */
2440	#define X86_FCW_PM RT_BIT(5)
2441	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2442	* @remarks This includes reserved bit 6. */
2443	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2444	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2445	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2446	/** Precision control mask. */
2447	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2448	/** Precision control: 24-bit. */
2449	#define X86_FCW_PC_24 UINT16_C(0x0000)
2450	/** Precision control: Reserved. */
2451	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2452	/** Precision control: 53-bit. */
2453	#define X86_FCW_PC_53 UINT16_C(0x0200)
2454	/** Precision control: 64-bit. */
2455	#define X86_FCW_PC_64 UINT16_C(0x0300)
2456	/** Rounding control mask. */
2457	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2458	/** Rounding control: To nearest. */
2459	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2460	/** Rounding control: Down. */
2461	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2462	/** Rounding control: Up. */
2463	#define X86_FCW_RC_UP UINT16_C(0x0800)
2464	/** Rounding control: Towards zero. */
2465	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2466	/** Bits which should be zero, apparently. */
2467	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2468	/** @} */
2469
2470	/** @name SSE MXCSR
2471	* @{ */
2472	/** Exception Flag: Invalid operation. */
2473	#define X86_MSXCR_IE RT_BIT(0)
2474	/** Exception Flag: Denormalized operand. */
2475	#define X86_MSXCR_DE RT_BIT(1)
2476	/** Exception Flag: Zero divide. */
2477	#define X86_MSXCR_ZE RT_BIT(2)
2478	/** Exception Flag: Overflow. */
2479	#define X86_MSXCR_OE RT_BIT(3)
2480	/** Exception Flag: Underflow. */
2481	#define X86_MSXCR_UE RT_BIT(4)
2482	/** Exception Flag: Precision. */
2483	#define X86_MSXCR_PE RT_BIT(5)
2484
2485	/** Denormals are zero. */
2486	#define X86_MSXCR_DAZ RT_BIT(6)
2487
2488	/** Exception Mask: Invalid operation. */
2489	#define X86_MSXCR_IM RT_BIT(7)
2490	/** Exception Mask: Denormalized operand. */
2491	#define X86_MSXCR_DM RT_BIT(8)
2492	/** Exception Mask: Zero divide. */
2493	#define X86_MSXCR_ZM RT_BIT(9)
2494	/** Exception Mask: Overflow. */
2495	#define X86_MSXCR_OM RT_BIT(10)
2496	/** Exception Mask: Underflow. */
2497	#define X86_MSXCR_UM RT_BIT(11)
2498	/** Exception Mask: Precision. */
2499	#define X86_MSXCR_PM RT_BIT(12)
2500
2501	/** Rounding control mask. */
2502	#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2503	/** Rounding control: To nearest. */
2504	#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2505	/** Rounding control: Down. */
2506	#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2507	/** Rounding control: Up. */
2508	#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2509	/** Rounding control: Towards zero. */
2510	#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2511
2512	/** Flush-to-zero for masked underflow. */
2513	#define X86_MSXCR_FZ RT_BIT(15)
2514
2515	/** Misaligned Exception Mask. */
2516	#define X86_MSXCR_MM RT_BIT(16)
2517	/** @} */
2518
2519
2520	/** @name Selector Descriptor
2521	* @{
2522	*/
2523
2524	#ifndef VBOX_FOR_DTRACE_LIB
2525	/**
2526	* Descriptor attributes (as seen by VT-x).
2527	*/
2528	typedef struct X86DESCATTRBITS
2529	{
2530	/** 00 - Segment Type. */
2531	unsigned u4Type : 4;
2532	/** 04 - Descriptor Type. System(=0) or code/data selector */
2533	unsigned u1DescType : 1;
2534	/** 05 - Descriptor Privilege level. */
2535	unsigned u2Dpl : 2;
2536	/** 07 - Flags selector present(=1) or not. */
2537	unsigned u1Present : 1;
2538	/** 08 - Segment limit 16-19. */
2539	unsigned u4LimitHigh : 4;
2540	/** 0c - Available for system software. */
2541	unsigned u1Available : 1;
2542	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2543	unsigned u1Long : 1;
2544	/** 0e - This flags meaning depends on the segment type. Try make sense out
2545	* of the intel manual yourself. */
2546	unsigned u1DefBig : 1;
2547	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2548	* clear byte. */
2549	unsigned u1Granularity : 1;
2550	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2551	unsigned u1Unusable : 1;
2552	} X86DESCATTRBITS;
2553	#endif /* !VBOX_FOR_DTRACE_LIB */
2554
2555	/** @name X86DESCATTR masks
2556	* @{ */
2557	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2558	#define X86DESCATTR_DT UINT32_C(0x00000010)
2559	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2560	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2561	#define X86DESCATTR_P UINT32_C(0x00000080)
2562	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2563	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2564	#define X86DESCATTR_L UINT32_C(0x00002000)
2565	#define X86DESCATTR_D UINT32_C(0x00004000)
2566	#define X86DESCATTR_G UINT32_C(0x00008000)
2567	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2568	/** @} */
2569
2570	#pragma pack(1)
2571	typedef union X86DESCATTR
2572	{
2573	/** Unsigned integer view. */
2574	uint32_t u;
2575	#ifndef VBOX_FOR_DTRACE_LIB
2576	/** Normal view. */
2577	X86DESCATTRBITS n;
2578	#endif
2579	} X86DESCATTR;
2580	#pragma pack()
2581	/** Pointer to descriptor attributes. */
2582	typedef X86DESCATTR *PX86DESCATTR;
2583	/** Pointer to const descriptor attributes. */
2584	typedef const X86DESCATTR *PCX86DESCATTR;
2585
2586	#ifndef VBOX_FOR_DTRACE_LIB
2587
2588	/**
2589	* Generic descriptor table entry
2590	*/
2591	#pragma pack(1)
2592	typedef struct X86DESCGENERIC
2593	{
2594	/** 00 - Limit - Low word. */
2595	unsigned u16LimitLow : 16;
2596	/** 10 - Base address - lowe word.
2597	* Don't try set this to 24 because MSC is doing stupid things then. */
2598	unsigned u16BaseLow : 16;
2599	/** 20 - Base address - first 8 bits of high word. */
2600	unsigned u8BaseHigh1 : 8;
2601	/** 28 - Segment Type. */
2602	unsigned u4Type : 4;
2603	/** 2c - Descriptor Type. System(=0) or code/data selector */
2604	unsigned u1DescType : 1;
2605	/** 2d - Descriptor Privilege level. */
2606	unsigned u2Dpl : 2;
2607	/** 2f - Flags selector present(=1) or not. */
2608	unsigned u1Present : 1;
2609	/** 30 - Segment limit 16-19. */
2610	unsigned u4LimitHigh : 4;
2611	/** 34 - Available for system software. */
2612	unsigned u1Available : 1;
2613	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2614	unsigned u1Long : 1;
2615	/** 36 - This flags meaning depends on the segment type. Try make sense out
2616	* of the intel manual yourself. */
2617	unsigned u1DefBig : 1;
2618	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
2619	* clear byte. */
2620	unsigned u1Granularity : 1;
2621	/** 38 - Base address - highest 8 bits. */
2622	unsigned u8BaseHigh2 : 8;
2623	} X86DESCGENERIC;
2624	#pragma pack()
2625	/** Pointer to a generic descriptor entry. */
2626	typedef X86DESCGENERIC *PX86DESCGENERIC;
2627	/** Pointer to a const generic descriptor entry. */
2628	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2629
2630	/** @name Bit offsets of X86DESCGENERIC members.
2631	* @{*/
2632	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
2633	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
2634	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
2635	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
2636	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
2637	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
2638	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
2639	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
2640	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
2641	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
2642	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
2643	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
2644	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
2645	/** @} */
2646
2647	/**
2648	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2649	*/
2650	typedef struct X86DESCGATE
2651	{
2652	/** 00 - Target code segment offset - Low word.
2653	* Ignored if task-gate. */
2654	unsigned u16OffsetLow : 16;
2655	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2656	* TSS selector if task-gate. */
2657	unsigned u16Sel : 16;
2658	/** 20 - Number of parameters for a call-gate.
2659	* Ignored if interrupt-, trap- or task-gate. */
2660	unsigned u4ParmCount : 4;
2661	/** 24 - Reserved / ignored. */
2662	unsigned u4Reserved : 4;
2663	/** 28 - Segment Type. */
2664	unsigned u4Type : 4;
2665	/** 2c - Descriptor Type (0 = system). */
2666	unsigned u1DescType : 1;
2667	/** 2d - Descriptor Privilege level. */
2668	unsigned u2Dpl : 2;
2669	/** 2f - Flags selector present(=1) or not. */
2670	unsigned u1Present : 1;
2671	/** 30 - Target code segment offset - High word.
2672	* Ignored if task-gate. */
2673	unsigned u16OffsetHigh : 16;
2674	} X86DESCGATE;
2675	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2676	typedef X86DESCGATE *PX86DESCGATE;
2677	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2678	typedef const X86DESCGATE *PCX86DESCGATE;
2679
2680	#endif /* VBOX_FOR_DTRACE_LIB */
2681
2682	/**
2683	* Descriptor table entry.
2684	*/
2685	#pragma pack(1)
2686	typedef union X86DESC
2687	{
2688	#ifndef VBOX_FOR_DTRACE_LIB
2689	/** Generic descriptor view. */
2690	X86DESCGENERIC Gen;
2691	/** Gate descriptor view. */
2692	X86DESCGATE Gate;
2693	#endif
2694
2695	/** 8 bit unsigned integer view. */
2696	uint8_t au8[8];
2697	/** 16 bit unsigned integer view. */
2698	uint16_t au16[4];
2699	/** 32 bit unsigned integer view. */
2700	uint32_t au32[2];
2701	/** 64 bit unsigned integer view. */
2702	uint64_t au64[1];
2703	/** Unsigned integer view. */
2704	uint64_t u;
2705	} X86DESC;
2706	#ifndef VBOX_FOR_DTRACE_LIB
2707	AssertCompileSize(X86DESC, 8);
2708	#endif
2709	#pragma pack()
2710	/** Pointer to descriptor table entry. */
2711	typedef X86DESC *PX86DESC;
2712	/** Pointer to const descriptor table entry. */
2713	typedef const X86DESC *PCX86DESC;
2714
2715	/** @def X86DESC_BASE
2716	* Return the base address of a descriptor.
2717	*/
2718	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
2719	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2720	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2721	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2722
2723	/** @def X86DESC_LIMIT
2724	* Return the limit of a descriptor.
2725	*/
2726	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
2727	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2728	\| ( (a_pDesc)->Gen.u16LimitLow ) )
2729
2730	/** @def X86DESC_LIMIT_G
2731	* Return the limit of a descriptor with the granularity bit taken into account.
2732	* @returns Selector limit (uint32_t).
2733	* @param a_pDesc Pointer to the descriptor.
2734	*/
2735	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
2736	( (a_pDesc)->Gen.u1Granularity \
2737	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
2738	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
2739	)
2740
2741	/** @def X86DESC_GET_HID_ATTR
2742	* Get the descriptor attributes for the hidden register.
2743	*/
2744	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
2745	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2746
2747	#ifndef VBOX_FOR_DTRACE_LIB
2748
2749	/**
2750	* 64 bits generic descriptor table entry
2751	* Note: most of these bits have no meaning in long mode.
2752	*/
2753	#pragma pack(1)
2754	typedef struct X86DESC64GENERIC
2755	{
2756	/** Limit - Low word - IGNORED. */
2757	unsigned u16LimitLow : 16;
2758	/** Base address - low word. - IGNORED
2759	* Don't try set this to 24 because MSC is doing stupid things then. */
2760	unsigned u16BaseLow : 16;
2761	/** Base address - first 8 bits of high word. - IGNORED */
2762	unsigned u8BaseHigh1 : 8;
2763	/** Segment Type. */
2764	unsigned u4Type : 4;
2765	/** Descriptor Type. System(=0) or code/data selector */
2766	unsigned u1DescType : 1;
2767	/** Descriptor Privilege level. */
2768	unsigned u2Dpl : 2;
2769	/** Flags selector present(=1) or not. */
2770	unsigned u1Present : 1;
2771	/** Segment limit 16-19. - IGNORED */
2772	unsigned u4LimitHigh : 4;
2773	/** Available for system software. - IGNORED */
2774	unsigned u1Available : 1;
2775	/** Long mode flag. */
2776	unsigned u1Long : 1;
2777	/** This flags meaning depends on the segment type. Try make sense out
2778	* of the intel manual yourself. */
2779	unsigned u1DefBig : 1;
2780	/** Granularity of the limit. If set 4KB granularity is used, if
2781	* clear byte. - IGNORED */
2782	unsigned u1Granularity : 1;
2783	/** Base address - highest 8 bits. - IGNORED */
2784	unsigned u8BaseHigh2 : 8;
2785	/** Base address - bits 63-32. */
2786	unsigned u32BaseHigh3 : 32;
2787	unsigned u8Reserved : 8;
2788	unsigned u5Zeros : 5;
2789	unsigned u19Reserved : 19;
2790	} X86DESC64GENERIC;
2791	#pragma pack()
2792	/** Pointer to a generic descriptor entry. */
2793	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2794	/** Pointer to a const generic descriptor entry. */
2795	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2796
2797	/**
2798	* System descriptor table entry (64 bits)
2799	*
2800	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2801	*/
2802	#pragma pack(1)
2803	typedef struct X86DESC64SYSTEM
2804	{
2805	/** Limit - Low word. */
2806	unsigned u16LimitLow : 16;
2807	/** Base address - lowe word.
2808	* Don't try set this to 24 because MSC is doing stupid things then. */
2809	unsigned u16BaseLow : 16;
2810	/** Base address - first 8 bits of high word. */
2811	unsigned u8BaseHigh1 : 8;
2812	/** Segment Type. */
2813	unsigned u4Type : 4;
2814	/** Descriptor Type. System(=0) or code/data selector */
2815	unsigned u1DescType : 1;
2816	/** Descriptor Privilege level. */
2817	unsigned u2Dpl : 2;
2818	/** Flags selector present(=1) or not. */
2819	unsigned u1Present : 1;
2820	/** Segment limit 16-19. */
2821	unsigned u4LimitHigh : 4;
2822	/** Available for system software. */
2823	unsigned u1Available : 1;
2824	/** Reserved - 0. */
2825	unsigned u1Reserved : 1;
2826	/** This flags meaning depends on the segment type. Try make sense out
2827	* of the intel manual yourself. */
2828	unsigned u1DefBig : 1;
2829	/** Granularity of the limit. If set 4KB granularity is used, if
2830	* clear byte. */
2831	unsigned u1Granularity : 1;
2832	/** Base address - bits 31-24. */
2833	unsigned u8BaseHigh2 : 8;
2834	/** Base address - bits 63-32. */
2835	unsigned u32BaseHigh3 : 32;
2836	unsigned u8Reserved : 8;
2837	unsigned u5Zeros : 5;
2838	unsigned u19Reserved : 19;
2839	} X86DESC64SYSTEM;
2840	#pragma pack()
2841	/** Pointer to a system descriptor entry. */
2842	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2843	/** Pointer to a const system descriptor entry. */
2844	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2845
2846	/**
2847	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2848	*/
2849	typedef struct X86DESC64GATE
2850	{
2851	/** Target code segment offset - Low word. */
2852	unsigned u16OffsetLow : 16;
2853	/** Target code segment selector. */
2854	unsigned u16Sel : 16;
2855	/** Interrupt stack table for interrupt- and trap-gates.
2856	* Ignored by call-gates. */
2857	unsigned u3IST : 3;
2858	/** Reserved / ignored. */
2859	unsigned u5Reserved : 5;
2860	/** Segment Type. */
2861	unsigned u4Type : 4;
2862	/** Descriptor Type (0 = system). */
2863	unsigned u1DescType : 1;
2864	/** Descriptor Privilege level. */
2865	unsigned u2Dpl : 2;
2866	/** Flags selector present(=1) or not. */
2867	unsigned u1Present : 1;
2868	/** Target code segment offset - High word.
2869	* Ignored if task-gate. */
2870	unsigned u16OffsetHigh : 16;
2871	/** Target code segment offset - Top dword.
2872	* Ignored if task-gate. */
2873	unsigned u32OffsetTop : 32;
2874	/** Reserved / ignored / must be zero.
2875	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2876	unsigned u32Reserved : 32;
2877	} X86DESC64GATE;
2878	AssertCompileSize(X86DESC64GATE, 16);
2879	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2880	typedef X86DESC64GATE *PX86DESC64GATE;
2881	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2882	typedef const X86DESC64GATE *PCX86DESC64GATE;
2883
2884	#endif /* VBOX_FOR_DTRACE_LIB */
2885
2886	/**
2887	* Descriptor table entry.
2888	*/
2889	#pragma pack(1)
2890	typedef union X86DESC64
2891	{
2892	#ifndef VBOX_FOR_DTRACE_LIB
2893	/** Generic descriptor view. */
2894	X86DESC64GENERIC Gen;
2895	/** System descriptor view. */
2896	X86DESC64SYSTEM System;
2897	/** Gate descriptor view. */
2898	X86DESC64GATE Gate;
2899	#endif
2900
2901	/** 8 bit unsigned integer view. */
2902	uint8_t au8[16];
2903	/** 16 bit unsigned integer view. */
2904	uint16_t au16[8];
2905	/** 32 bit unsigned integer view. */
2906	uint32_t au32[4];
2907	/** 64 bit unsigned integer view. */
2908	uint64_t au64[2];
2909	} X86DESC64;
2910	#ifndef VBOX_FOR_DTRACE_LIB
2911	AssertCompileSize(X86DESC64, 16);
2912	#endif
2913	#pragma pack()
2914	/** Pointer to descriptor table entry. */
2915	typedef X86DESC64 *PX86DESC64;
2916	/** Pointer to const descriptor table entry. */
2917	typedef const X86DESC64 *PCX86DESC64;
2918
2919	/** @def X86DESC64_BASE
2920	* Return the base of a 64-bit descriptor.
2921	*/
2922	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
2923	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2924	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2925	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2926	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2927
2928
2929
2930	/** @name Host system descriptor table entry - Use with care!
2931	* @{ */
2932	/** Host system descriptor table entry. */
2933	#if HC_ARCH_BITS == 64
2934	typedef X86DESC64 X86DESCHC;
2935	#else
2936	typedef X86DESC X86DESCHC;
2937	#endif
2938	/** Pointer to a host system descriptor table entry. */
2939	#if HC_ARCH_BITS == 64
2940	typedef PX86DESC64 PX86DESCHC;
2941	#else
2942	typedef PX86DESC PX86DESCHC;
2943	#endif
2944	/** Pointer to a const host system descriptor table entry. */
2945	#if HC_ARCH_BITS == 64
2946	typedef PCX86DESC64 PCX86DESCHC;
2947	#else
2948	typedef PCX86DESC PCX86DESCHC;
2949	#endif
2950	/** @} */
2951
2952
2953	/** @name Selector Descriptor Types.
2954	* @{
2955	*/
2956
2957	/** @name Non-System Selector Types.
2958	* @{ */
2959	/** Code(=set)/Data(=clear) bit. */
2960	#define X86_SEL_TYPE_CODE 8
2961	/** Memory(=set)/System(=clear) bit. */
2962	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2963	/** Accessed bit. */
2964	#define X86_SEL_TYPE_ACCESSED 1
2965	/** Expand down bit (for data selectors only). */
2966	#define X86_SEL_TYPE_DOWN 4
2967	/** Conforming bit (for code selectors only). */
2968	#define X86_SEL_TYPE_CONF 4
2969	/** Write bit (for data selectors only). */
2970	#define X86_SEL_TYPE_WRITE 2
2971	/** Read bit (for code selectors only). */
2972	#define X86_SEL_TYPE_READ 2
2973	/** The bit number of the code segment read bit (relative to u4Type). */
2974	#define X86_SEL_TYPE_READ_BIT 1
2975
2976	/** Read only selector type. */
2977	#define X86_SEL_TYPE_RO 0
2978	/** Accessed read only selector type. */
2979	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2980	/** Read write selector type. */
2981	#define X86_SEL_TYPE_RW 2
2982	/** Accessed read write selector type. */
2983	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2984	/** Expand down read only selector type. */
2985	#define X86_SEL_TYPE_RO_DOWN 4
2986	/** Accessed expand down read only selector type. */
2987	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2988	/** Expand down read write selector type. */
2989	#define X86_SEL_TYPE_RW_DOWN 6
2990	/** Accessed expand down read write selector type. */
2991	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2992	/** Execute only selector type. */
2993	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2994	/** Accessed execute only selector type. */
2995	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2996	/** Execute and read selector type. */
2997	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2998	/** Accessed execute and read selector type. */
2999	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3000	/** Conforming execute only selector type. */
3001	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3002	/** Accessed Conforming execute only selector type. */
3003	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3004	/** Conforming execute and write selector type. */
3005	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3006	/** Accessed Conforming execute and write selector type. */
3007	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3008	/** @} */
3009
3010
3011	/** @name System Selector Types.
3012	* @{ */
3013	/** The TSS busy bit mask. */
3014	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3015
3016	/** Undefined system selector type. */
3017	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3018	/** 286 TSS selector. */
3019	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3020	/** LDT selector. */
3021	#define X86_SEL_TYPE_SYS_LDT 2
3022	/** 286 TSS selector - Busy. */
3023	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3024	/** 286 Callgate selector. */
3025	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3026	/** Taskgate selector. */
3027	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3028	/** 286 Interrupt gate selector. */
3029	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3030	/** 286 Trapgate selector. */
3031	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3032	/** Undefined system selector. */
3033	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3034	/** 386 TSS selector. */
3035	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3036	/** Undefined system selector. */
3037	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3038	/** 386 TSS selector - Busy. */
3039	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3040	/** 386 Callgate selector. */
3041	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3042	/** Undefined system selector. */
3043	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3044	/** 386 Interruptgate selector. */
3045	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3046	/** 386 Trapgate selector. */
3047	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3048	/** @} */
3049
3050	/** @name AMD64 System Selector Types.
3051	* @{ */
3052	/** LDT selector. */
3053	#define AMD64_SEL_TYPE_SYS_LDT 2
3054	/** TSS selector - Busy. */
3055	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3056	/** TSS selector - Busy. */
3057	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3058	/** Callgate selector. */
3059	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3060	/** Interruptgate selector. */
3061	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3062	/** Trapgate selector. */
3063	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3064	/** @} */
3065
3066	/** @} */
3067
3068
3069	/** @name Descriptor Table Entry Flag Masks.
3070	* These are for the 2nd 32-bit word of a descriptor.
3071	* @{ */
3072	/** Bits 8-11 - TYPE - Descriptor type mask. */
3073	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
3074	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3075	#define X86_DESC_S RT_BIT(12)
3076	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3077	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
3078	/** Bit 15 - P - Present. */
3079	#define X86_DESC_P RT_BIT(15)
3080	/** Bit 20 - AVL - Available for system software. */
3081	#define X86_DESC_AVL RT_BIT(20)
3082	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3083	#define X86_DESC_DB RT_BIT(22)
3084	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3085	* used, if clear byte. */
3086	#define X86_DESC_G RT_BIT(23)
3087	/** @} */
3088
3089	/** @} */
3090
3091
3092	/** @name Task Segments.
3093	* @{
3094	*/
3095
3096	/**
3097	* The minimum TSS descriptor limit for 286 tasks.
3098	*/
3099	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3100
3101	/**
3102	* The minimum TSS descriptor segment limit for 386 tasks.
3103	*/
3104	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3105
3106	/**
3107	* 16-bit Task Segment (TSS).
3108	*/
3109	#pragma pack(1)
3110	typedef struct X86TSS16
3111	{
3112	/** Back link to previous task. (static) */
3113	RTSEL selPrev;
3114	/** Ring-0 stack pointer. (static) */
3115	uint16_t sp0;
3116	/** Ring-0 stack segment. (static) */
3117	RTSEL ss0;
3118	/** Ring-1 stack pointer. (static) */
3119	uint16_t sp1;
3120	/** Ring-1 stack segment. (static) */
3121	RTSEL ss1;
3122	/** Ring-2 stack pointer. (static) */
3123	uint16_t sp2;
3124	/** Ring-2 stack segment. (static) */
3125	RTSEL ss2;
3126	/** IP before task switch. */
3127	uint16_t ip;
3128	/** FLAGS before task switch. */
3129	uint16_t flags;
3130	/** AX before task switch. */
3131	uint16_t ax;
3132	/** CX before task switch. */
3133	uint16_t cx;
3134	/** DX before task switch. */
3135	uint16_t dx;
3136	/** BX before task switch. */
3137	uint16_t bx;
3138	/** SP before task switch. */
3139	uint16_t sp;
3140	/** BP before task switch. */
3141	uint16_t bp;
3142	/** SI before task switch. */
3143	uint16_t si;
3144	/** DI before task switch. */
3145	uint16_t di;
3146	/** ES before task switch. */
3147	RTSEL es;
3148	/** CS before task switch. */
3149	RTSEL cs;
3150	/** SS before task switch. */
3151	RTSEL ss;
3152	/** DS before task switch. */
3153	RTSEL ds;
3154	/** LDTR before task switch. */
3155	RTSEL selLdt;
3156	} X86TSS16;
3157	#ifndef VBOX_FOR_DTRACE_LIB
3158	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3159	#endif
3160	#pragma pack()
3161	/** Pointer to a 16-bit task segment. */
3162	typedef X86TSS16 *PX86TSS16;
3163	/** Pointer to a const 16-bit task segment. */
3164	typedef const X86TSS16 *PCX86TSS16;
3165
3166
3167	/**
3168	* 32-bit Task Segment (TSS).
3169	*/
3170	#pragma pack(1)
3171	typedef struct X86TSS32
3172	{
3173	/** Back link to previous task. (static) */
3174	RTSEL selPrev;
3175	uint16_t padding1;
3176	/** Ring-0 stack pointer. (static) */
3177	uint32_t esp0;
3178	/** Ring-0 stack segment. (static) */
3179	RTSEL ss0;
3180	uint16_t padding_ss0;
3181	/** Ring-1 stack pointer. (static) */
3182	uint32_t esp1;
3183	/** Ring-1 stack segment. (static) */
3184	RTSEL ss1;
3185	uint16_t padding_ss1;
3186	/** Ring-2 stack pointer. (static) */
3187	uint32_t esp2;
3188	/** Ring-2 stack segment. (static) */
3189	RTSEL ss2;
3190	uint16_t padding_ss2;
3191	/** Page directory for the task. (static) */
3192	uint32_t cr3;
3193	/** EIP before task switch. */
3194	uint32_t eip;
3195	/** EFLAGS before task switch. */
3196	uint32_t eflags;
3197	/** EAX before task switch. */
3198	uint32_t eax;
3199	/** ECX before task switch. */
3200	uint32_t ecx;
3201	/** EDX before task switch. */
3202	uint32_t edx;
3203	/** EBX before task switch. */
3204	uint32_t ebx;
3205	/** ESP before task switch. */
3206	uint32_t esp;
3207	/** EBP before task switch. */
3208	uint32_t ebp;
3209	/** ESI before task switch. */
3210	uint32_t esi;
3211	/** EDI before task switch. */
3212	uint32_t edi;
3213	/** ES before task switch. */
3214	RTSEL es;
3215	uint16_t padding_es;
3216	/** CS before task switch. */
3217	RTSEL cs;
3218	uint16_t padding_cs;
3219	/** SS before task switch. */
3220	RTSEL ss;
3221	uint16_t padding_ss;
3222	/** DS before task switch. */
3223	RTSEL ds;
3224	uint16_t padding_ds;
3225	/** FS before task switch. */
3226	RTSEL fs;
3227	uint16_t padding_fs;
3228	/** GS before task switch. */
3229	RTSEL gs;
3230	uint16_t padding_gs;
3231	/** LDTR before task switch. */
3232	RTSEL selLdt;
3233	uint16_t padding_ldt;
3234	/** Debug trap flag */
3235	uint16_t fDebugTrap;
3236	/** Offset relative to the TSS of the start of the I/O Bitmap
3237	* and the end of the interrupt redirection bitmap. */
3238	uint16_t offIoBitmap;
3239	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3240	uint8_t IntRedirBitmap[32];
3241	} X86TSS32;
3242	#pragma pack()
3243	/** Pointer to task segment. */
3244	typedef X86TSS32 *PX86TSS32;
3245	/** Pointer to const task segment. */
3246	typedef const X86TSS32 *PCX86TSS32;
3247
3248	/**
3249	* 64-bit Task segment.
3250	*/
3251	#pragma pack(1)
3252	typedef struct X86TSS64
3253	{
3254	/** Reserved. */
3255	uint32_t u32Reserved;
3256	/** Ring-0 stack pointer. (static) */
3257	uint64_t rsp0;
3258	/** Ring-1 stack pointer. (static) */
3259	uint64_t rsp1;
3260	/** Ring-2 stack pointer. (static) */
3261	uint64_t rsp2;
3262	/** Reserved. */
3263	uint32_t u32Reserved2[2];
3264	/* IST */
3265	uint64_t ist1;
3266	uint64_t ist2;
3267	uint64_t ist3;
3268	uint64_t ist4;
3269	uint64_t ist5;
3270	uint64_t ist6;
3271	uint64_t ist7;
3272	/* Reserved. */
3273	uint16_t u16Reserved[5];
3274	/** Offset relative to the TSS of the start of the I/O Bitmap
3275	* and the end of the interrupt redirection bitmap. */
3276	uint16_t offIoBitmap;
3277	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3278	uint8_t IntRedirBitmap[32];
3279	} X86TSS64;
3280	#pragma pack()
3281	/** Pointer to a 64-bit task segment. */
3282	typedef X86TSS64 *PX86TSS64;
3283	/** Pointer to a const 64-bit task segment. */
3284	typedef const X86TSS64 *PCX86TSS64;
3285	#ifndef VBOX_FOR_DTRACE_LIB
3286	AssertCompileSize(X86TSS64, 136);
3287	#endif
3288
3289	/** @} */
3290
3291
3292	/** @name Selectors.
3293	* @{
3294	*/
3295
3296	/**
3297	* The shift used to convert a selector from and to index an index (C).
3298	*/
3299	#define X86_SEL_SHIFT 3
3300
3301	/**
3302	* The mask used to mask off the table indicator and RPL of an selector.
3303	*/
3304	#define X86_SEL_MASK 0xfff8U
3305
3306	/**
3307	* The mask used to mask off the RPL of an selector.
3308	* This is suitable for checking for NULL selectors.
3309	*/
3310	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3311
3312	/**
3313	* The bit indicating that a selector is in the LDT and not in the GDT.
3314	*/
3315	#define X86_SEL_LDT 0x0004U
3316
3317	/**
3318	* The bit mask for getting the RPL of a selector.
3319	*/
3320	#define X86_SEL_RPL 0x0003U
3321
3322	/**
3323	* The mask covering both RPL and LDT.
3324	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3325	* checks.
3326	*/
3327	#define X86_SEL_RPL_LDT 0x0007U
3328
3329	/** @} */
3330
3331
3332	/**
3333	* x86 Exceptions/Faults/Traps.
3334	*/
3335	typedef enum X86XCPT
3336	{
3337	/** \#DE - Divide error. */
3338	X86_XCPT_DE = 0x00,
3339	/** \#DB - Debug event (single step, DRx, ..) */
3340	X86_XCPT_DB = 0x01,
3341	/** NMI - Non-Maskable Interrupt */
3342	X86_XCPT_NMI = 0x02,
3343	/** \#BP - Breakpoint (INT3). */
3344	X86_XCPT_BP = 0x03,
3345	/** \#OF - Overflow (INTO). */
3346	X86_XCPT_OF = 0x04,
3347	/** \#BR - Bound range exceeded (BOUND). */
3348	X86_XCPT_BR = 0x05,
3349	/** \#UD - Undefined opcode. */
3350	X86_XCPT_UD = 0x06,
3351	/** \#NM - Device not available (math coprocessor device). */
3352	X86_XCPT_NM = 0x07,
3353	/** \#DF - Double fault. */
3354	X86_XCPT_DF = 0x08,
3355	/** ??? - Coprocessor segment overrun (obsolete). */
3356	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3357	/** \#TS - Taskswitch (TSS). */
3358	X86_XCPT_TS = 0x0a,
3359	/** \#NP - Segment no present. */
3360	X86_XCPT_NP = 0x0b,
3361	/** \#SS - Stack segment fault. */
3362	X86_XCPT_SS = 0x0c,
3363	/** \#GP - General protection fault. */
3364	X86_XCPT_GP = 0x0d,
3365	/** \#PF - Page fault. */
3366	X86_XCPT_PF = 0x0e,
3367	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3368	/** \#MF - Math fault (FPU). */
3369	X86_XCPT_MF = 0x10,
3370	/** \#AC - Alignment check. */
3371	X86_XCPT_AC = 0x11,
3372	/** \#MC - Machine check. */
3373	X86_XCPT_MC = 0x12,
3374	/** \#XF - SIMD Floating-Pointer Exception. */
3375	X86_XCPT_XF = 0x13,
3376	/** \#VE - Virtualization Exception. */
3377	X86_XCPT_VE = 0x14,
3378	/** \#SX - Security Exception. */
3379	X86_XCPT_SX = 0x1f
3380	} X86XCPT;
3381	/** Pointer to a x86 exception code. */
3382	typedef X86XCPT *PX86XCPT;
3383	/** Pointer to a const x86 exception code. */
3384	typedef const X86XCPT *PCX86XCPT;
3385	/** The maximum exception value. */
3386	#define X86_XCPT_MAX (X86_XCPT_SX)
3387
3388
3389	/** @name Trap Error Codes
3390	* @{
3391	*/
3392	/** External indicator. */
3393	#define X86_TRAP_ERR_EXTERNAL 1
3394	/** IDT indicator. */
3395	#define X86_TRAP_ERR_IDT 2
3396	/** Descriptor table indicator - If set LDT, if clear GDT. */
3397	#define X86_TRAP_ERR_TI 4
3398	/** Mask for getting the selector. */
3399	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3400	/** Shift for getting the selector table index (C type index). */
3401	#define X86_TRAP_ERR_SEL_SHIFT 3
3402	/** @} */
3403
3404
3405	/** @name \#PF Trap Error Codes
3406	* @{
3407	*/
3408	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3409	#define X86_TRAP_PF_P RT_BIT(0)
3410	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3411	#define X86_TRAP_PF_RW RT_BIT(1)
3412	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3413	#define X86_TRAP_PF_US RT_BIT(2)
3414	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3415	#define X86_TRAP_PF_RSVD RT_BIT(3)
3416	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3417	#define X86_TRAP_PF_ID RT_BIT(4)
3418	/** @} */
3419
3420	#pragma pack(1)
3421	/**
3422	* 16-bit IDTR.
3423	*/
3424	typedef struct X86IDTR16
3425	{
3426	/** Offset. */
3427	uint16_t offSel;
3428	/** Selector. */
3429	uint16_t uSel;
3430	} X86IDTR16, *PX86IDTR16;
3431	#pragma pack()
3432
3433	#pragma pack(1)
3434	/**
3435	* 32-bit IDTR/GDTR.
3436	*/
3437	typedef struct X86XDTR32
3438	{
3439	/** Size of the descriptor table. */
3440	uint16_t cb;
3441	/** Address of the descriptor table. */
3442	#ifndef VBOX_FOR_DTRACE_LIB
3443	uint32_t uAddr;
3444	#else
3445	uint16_t au16Addr[2];
3446	#endif
3447	} X86XDTR32, *PX86XDTR32;
3448	#pragma pack()
3449
3450	#pragma pack(1)
3451	/**
3452	* 64-bit IDTR/GDTR.
3453	*/
3454	typedef struct X86XDTR64
3455	{
3456	/** Size of the descriptor table. */
3457	uint16_t cb;
3458	/** Address of the descriptor table. */
3459	#ifndef VBOX_FOR_DTRACE_LIB
3460	uint64_t uAddr;
3461	#else
3462	uint16_t au16Addr[4];
3463	#endif
3464	} X86XDTR64, *PX86XDTR64;
3465	#pragma pack()
3466
3467
3468	/** @name ModR/M
3469	* @{ */
3470	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3471	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3472	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3473	#define X86_MODRM_REG_SHIFT 3
3474	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3475	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3476	#define X86_MODRM_MOD_SHIFT 6
3477	#ifndef VBOX_FOR_DTRACE_LIB
3478	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3479	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3480	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3481	#endif
3482	/** @} */
3483
3484	/** @name SIB
3485	* @{ */
3486	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3487	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3488	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3489	#define X86_SIB_INDEX_SHIFT 3
3490	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3491	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3492	#define X86_SIB_SCALE_SHIFT 6
3493	#ifndef VBOX_FOR_DTRACE_LIB
3494	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3495	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3496	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3497	#endif
3498	/** @} */
3499
3500	/** @name General register indexes
3501	* @{ */
3502	#define X86_GREG_xAX 0
3503	#define X86_GREG_xCX 1
3504	#define X86_GREG_xDX 2
3505	#define X86_GREG_xBX 3
3506	#define X86_GREG_xSP 4
3507	#define X86_GREG_xBP 5
3508	#define X86_GREG_xSI 6
3509	#define X86_GREG_xDI 7
3510	#define X86_GREG_x8 8
3511	#define X86_GREG_x9 9
3512	#define X86_GREG_x10 10
3513	#define X86_GREG_x11 11
3514	#define X86_GREG_x12 12
3515	#define X86_GREG_x13 13
3516	#define X86_GREG_x14 14
3517	#define X86_GREG_x15 15
3518	/** @} */
3519
3520	/** @name X86_SREG_XXX - Segment register indexes.
3521	* @{ */
3522	#define X86_SREG_ES 0
3523	#define X86_SREG_CS 1
3524	#define X86_SREG_SS 2
3525	#define X86_SREG_DS 3
3526	#define X86_SREG_FS 4
3527	#define X86_SREG_GS 5
3528	/** @} */
3529	/** Segment register count. */
3530	#define X86_SREG_COUNT 6
3531
3532
3533	/** @name X86_OP_XXX - Prefixes
3534	* @{ */
3535	#define X86_OP_PRF_CS UINT8_C(0x2e)
3536	#define X86_OP_PRF_SS UINT8_C(0x36)
3537	#define X86_OP_PRF_DS UINT8_C(0x3e)
3538	#define X86_OP_PRF_ES UINT8_C(0x26)
3539	#define X86_OP_PRF_FS UINT8_C(0x64)
3540	#define X86_OP_PRF_GS UINT8_C(0x65)
3541	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3542	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3543	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3544	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3545	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3546	#define X86_OP_REX_B UINT8_C(0x41)
3547	#define X86_OP_REX_X UINT8_C(0x42)
3548	#define X86_OP_REX_R UINT8_C(0x44)
3549	#define X86_OP_REX_W UINT8_C(0x48)
3550	/** @} */
3551
3552
3553	/** @} */
3554
3555	#endif
3556

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source: vbox/trunk/include/iprt/x86.h@ 54403

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