x86.h@ 66601

Last change on this file since 66601 was 66599, checked in by vboxsync, 8 years ago
x86.h,bs2: X86_XCPT_MAX -> X86_XCPT_LAST; Corrected X86_XCPT_SX value.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 155.5 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2016 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT_32(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT_32(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT_32(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT_32(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT_32(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT_32(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT_32(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT_32(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT_32(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT_32(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT_32(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT_32(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT_32(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT_32(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT_32(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT_32(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT_32(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** Bits restored by popf */
215	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
216	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
217	/** The status bits commonly updated by arithmetic instructions. */
218	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
219	/** @} */
220
221
222	/** CPUID Feature information - ECX.
223	* CPUID query with EAX=1.
224	*/
225	#ifndef VBOX_FOR_DTRACE_LIB
226	typedef struct X86CPUIDFEATECX
227	{
228	/** Bit 0 - SSE3 - Supports SSE3 or not. */
229	unsigned u1SSE3 : 1;
230	/** Bit 1 - PCLMULQDQ. */
231	unsigned u1PCLMULQDQ : 1;
232	/** Bit 2 - DS Area 64-bit layout. */
233	unsigned u1DTE64 : 1;
234	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235	unsigned u1Monitor : 1;
236	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237	unsigned u1CPLDS : 1;
238	/** Bit 5 - VMX - Virtual Machine Technology. */
239	unsigned u1VMX : 1;
240	/** Bit 6 - SMX: Safer Mode Extensions. */
241	unsigned u1SMX : 1;
242	/** Bit 7 - EST - Enh. SpeedStep Tech. */
243	unsigned u1EST : 1;
244	/** Bit 8 - TM2 - Terminal Monitor 2. */
245	unsigned u1TM2 : 1;
246	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247	unsigned u1SSSE3 : 1;
248	/** Bit 10 - CNTX-ID - L1 Context ID. */
249	unsigned u1CNTXID : 1;
250	/** Bit 11 - Reserved. */
251	unsigned u1Reserved1 : 1;
252	/** Bit 12 - FMA. */
253	unsigned u1FMA : 1;
254	/** Bit 13 - CX16 - CMPXCHG16B. */
255	unsigned u1CX16 : 1;
256	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257	unsigned u1TPRUpdate : 1;
258	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259	unsigned u1PDCM : 1;
260	/** Bit 16 - Reserved. */
261	unsigned u1Reserved2 : 1;
262	/** Bit 17 - PCID - Process-context identifiers. */
263	unsigned u1PCID : 1;
264	/** Bit 18 - Direct Cache Access. */
265	unsigned u1DCA : 1;
266	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267	unsigned u1SSE4_1 : 1;
268	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269	unsigned u1SSE4_2 : 1;
270	/** Bit 21 - x2APIC. */
271	unsigned u1x2APIC : 1;
272	/** Bit 22 - MOVBE - Supports MOVBE. */
273	unsigned u1MOVBE : 1;
274	/** Bit 23 - POPCNT - Supports POPCNT. */
275	unsigned u1POPCNT : 1;
276	/** Bit 24 - TSC-Deadline. */
277	unsigned u1TSCDEADLINE : 1;
278	/** Bit 25 - AES. */
279	unsigned u1AES : 1;
280	/** Bit 26 - XSAVE - Supports XSAVE. */
281	unsigned u1XSAVE : 1;
282	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283	unsigned u1OSXSAVE : 1;
284	/** Bit 28 - AVX - Supports AVX instruction extensions. */
285	unsigned u1AVX : 1;
286	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287	unsigned u1F16C : 1;
288	/** Bit 30 - RDRAND - Supports RDRAND. */
289	unsigned u1RDRAND : 1;
290	/** Bit 31 - Hypervisor present (we're a guest). */
291	unsigned u1HVP : 1;
292	} X86CPUIDFEATECX;
293	#else /* VBOX_FOR_DTRACE_LIB */
294	typedef uint32_t X86CPUIDFEATECX;
295	#endif /* VBOX_FOR_DTRACE_LIB */
296	/** Pointer to CPUID Feature Information - ECX. */
297	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298	/** Pointer to const CPUID Feature Information - ECX. */
299	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302	/** CPUID Feature Information - EDX.
303	* CPUID query with EAX=1.
304	*/
305	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306	typedef struct X86CPUIDFEATEDX
307	{
308	/** Bit 0 - FPU - x87 FPU on Chip. */
309	unsigned u1FPU : 1;
310	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311	unsigned u1VME : 1;
312	/** Bit 2 - DE - Debugging extensions. */
313	unsigned u1DE : 1;
314	/** Bit 3 - PSE - Page Size Extension. */
315	unsigned u1PSE : 1;
316	/** Bit 4 - TSC - Time Stamp Counter. */
317	unsigned u1TSC : 1;
318	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319	unsigned u1MSR : 1;
320	/** Bit 6 - PAE - Physical Address Extension. */
321	unsigned u1PAE : 1;
322	/** Bit 7 - MCE - Machine Check Exception. */
323	unsigned u1MCE : 1;
324	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
325	unsigned u1CX8 : 1;
326	/** Bit 9 - APIC - APIC On-Chip. */
327	unsigned u1APIC : 1;
328	/** Bit 10 - Reserved. */
329	unsigned u1Reserved1 : 1;
330	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331	unsigned u1SEP : 1;
332	/** Bit 12 - MTRR - Memory Type Range Registers. */
333	unsigned u1MTRR : 1;
334	/** Bit 13 - PGE - PTE Global Bit. */
335	unsigned u1PGE : 1;
336	/** Bit 14 - MCA - Machine Check Architecture. */
337	unsigned u1MCA : 1;
338	/** Bit 15 - CMOV - Conditional Move Instructions. */
339	unsigned u1CMOV : 1;
340	/** Bit 16 - PAT - Page Attribute Table. */
341	unsigned u1PAT : 1;
342	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343	unsigned u1PSE36 : 1;
344	/** Bit 18 - PSN - Processor Serial Number. */
345	unsigned u1PSN : 1;
346	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
347	unsigned u1CLFSH : 1;
348	/** Bit 20 - Reserved. */
349	unsigned u1Reserved2 : 1;
350	/** Bit 21 - DS - Debug Store. */
351	unsigned u1DS : 1;
352	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353	unsigned u1ACPI : 1;
354	/** Bit 23 - MMX - Intel MMX 'Technology'. */
355	unsigned u1MMX : 1;
356	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357	unsigned u1FXSR : 1;
358	/** Bit 25 - SSE - SSE Support. */
359	unsigned u1SSE : 1;
360	/** Bit 26 - SSE2 - SSE2 Support. */
361	unsigned u1SSE2 : 1;
362	/** Bit 27 - SS - Self Snoop. */
363	unsigned u1SS : 1;
364	/** Bit 28 - HTT - Hyper-Threading Technology. */
365	unsigned u1HTT : 1;
366	/** Bit 29 - TM - Thermal Monitor. */
367	unsigned u1TM : 1;
368	/** Bit 30 - Reserved - . */
369	unsigned u1Reserved3 : 1;
370	/** Bit 31 - PBE - Pending Break Enabled. */
371	unsigned u1PBE : 1;
372	} X86CPUIDFEATEDX;
373	#else /* VBOX_FOR_DTRACE_LIB */
374	typedef uint32_t X86CPUIDFEATEDX;
375	#endif /* VBOX_FOR_DTRACE_LIB */
376	/** Pointer to CPUID Feature Information - EDX. */
377	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378	/** Pointer to const CPUID Feature Information - EDX. */
379	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381	/** @name CPUID Vendor information.
382	* CPUID query with EAX=0.
383	* @{
384	*/
385	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396	/** @} */
397
398
399	/** @name CPUID Feature information.
400	* CPUID query with EAX=1.
401	* @{
402	*/
403	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428	/** ECX Bit 12 - FMA. */
429	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436	/** ECX Bit 17 - PCID - Process-context identifiers. */
437	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438	/** ECX Bit 18 - DCA - Direct Cache Access. */
439	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444	/** ECX Bit 21 - x2APIC support. */
445	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446	/** ECX Bit 22 - MOVBE instruction. */
447	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448	/** ECX Bit 23 - POPCNT instruction. */
449	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450	/** ECX Bir 24 - TSC-Deadline. */
451	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452	/** ECX Bit 25 - AES instructions. */
453	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454	/** ECX Bit 26 - XSAVE instruction. */
455	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458	/** ECX Bit 28 - AVX. */
459	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462	/** ECX Bit 30 - RDRAND instruction. */
463	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464	/** ECX Bit 31 - Hypervisor Present (software only). */
465	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468	/** Bit 0 - FPU - x87 FPU on Chip. */
469	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472	/** Bit 2 - DE - Debugging extensions. */
473	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474	/** Bit 3 - PSE - Page Size Extension. */
475	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
477	/** Bit 4 - TSC - Time Stamp Counter. */
478	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481	/** Bit 6 - PAE - Physical Address Extension. */
482	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
484	/** Bit 7 - MCE - Machine Check Exception. */
485	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488	/** Bit 9 - APIC - APIC On-Chip. */
489	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492	/** Bit 12 - MTRR - Memory Type Range Registers. */
493	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494	/** Bit 13 - PGE - PTE Global Bit. */
495	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496	/** Bit 14 - MCA - Machine Check Architecture. */
497	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498	/** Bit 15 - CMOV - Conditional Move Instructions. */
499	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500	/** Bit 16 - PAT - Page Attribute Table. */
501	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504	/** Bit 18 - PSN - Processor Serial Number. */
505	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508	/** Bit 21 - DS - Debug Store. */
509	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512	/** Bit 23 - MMX - Intel MMX Technology. */
513	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516	/** Bit 25 - SSE - SSE Support. */
517	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518	/** Bit 26 - SSE2 - SSE2 Support. */
519	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520	/** Bit 27 - SS - Self Snoop. */
521	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522	/** Bit 28 - HTT - Hyper-Threading Technology. */
523	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524	/** Bit 29 - TM - Therm. Monitor. */
525	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526	/** Bit 31 - PBE - Pending Break Enabled. */
527	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528	/** @} */
529
530	/** @name CPUID mwait/monitor information.
531	* CPUID query with EAX=5.
532	* @{
533	*/
534	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538	/** @} */
539
540
541	/** @name CPUID Structured Extended Feature information.
542	* CPUID query with EAX=7.
543	* @{
544	*/
545	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600	/** @} */
601
602
603	/** @name CPUID Extended Feature information.
604	* CPUID query with EAX=0x80000001.
605	* @{
606	*/
607	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
608	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
609
610	/** EDX Bit 11 - SYSCALL/SYSRET. */
611	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
612	/** EDX Bit 20 - No-Execute/Execute-Disable. */
613	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
614	/** EDX Bit 26 - 1 GB large page. */
615	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
616	/** EDX Bit 27 - RDTSCP. */
617	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
618	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
619	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
620	/** @}*/
621
622	/** @name CPUID AMD Feature information.
623	* CPUID query with EAX=0x80000001.
624	* @{
625	*/
626	/** Bit 0 - FPU - x87 FPU on Chip. */
627	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
628	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
629	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
630	/** Bit 2 - DE - Debugging extensions. */
631	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
632	/** Bit 3 - PSE - Page Size Extension. */
633	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
634	/** Bit 4 - TSC - Time Stamp Counter. */
635	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
636	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
637	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
638	/** Bit 6 - PAE - Physical Address Extension. */
639	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
640	/** Bit 7 - MCE - Machine Check Exception. */
641	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
642	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
643	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
644	/** Bit 9 - APIC - APIC On-Chip. */
645	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
646	/** Bit 12 - MTRR - Memory Type Range Registers. */
647	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
648	/** Bit 13 - PGE - PTE Global Bit. */
649	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
650	/** Bit 14 - MCA - Machine Check Architecture. */
651	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
652	/** Bit 15 - CMOV - Conditional Move Instructions. */
653	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
654	/** Bit 16 - PAT - Page Attribute Table. */
655	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
656	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
657	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
658	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
659	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
660	/** Bit 23 - MMX - Intel MMX Technology. */
661	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
662	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
663	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
664	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
665	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
666	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
667	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
668	/** Bit 31 - 3DNOW - AMD 3DNow. */
669	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
670
671	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
672	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
673	/** Bit 2 - SVM - AMD VM extensions. */
674	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
675	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
676	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
677	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
678	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
679	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
680	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
681	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
682	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
683	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
684	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
685	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
686	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
687	/** Bit 9 - OSVW - AMD OS visible workaround. */
688	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
689	/** Bit 10 - IBS - Instruct based sampling. */
690	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
691	/** Bit 11 - XOP - Extended operation support (see APM6). */
692	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
693	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
694	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
695	/** Bit 13 - WDT - AMD Watchdog timer support. */
696	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
697	/** Bit 15 - LWP - Lightweight profiling support. */
698	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
699	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
700	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
701	/** Bit 19 - NodeId - Indicates support for
702	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
703	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
704	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
705	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
706	/** Bit 22 - TopologyExtensions - . */
707	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
708	/** @} */
709
710
711	/** @name CPUID AMD Feature information.
712	* CPUID query with EAX=0x80000007.
713	* @{
714	*/
715	/** Bit 0 - TS - Temperature Sensor. */
716	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
717	/** Bit 1 - FID - Frequency ID Control. */
718	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
719	/** Bit 2 - VID - Voltage ID Control. */
720	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
721	/** Bit 3 - TTP - THERMTRIP. */
722	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
723	/** Bit 4 - TM - Hardware Thermal Control. */
724	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
725	/** Bit 5 - STC - Software Thermal Control. */
726	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
727	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
728	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
729	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
730	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
731	/** Bit 8 - TSCINVAR - TSC Invariant. */
732	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
733	/** Bit 9 - CPB - TSC Invariant. */
734	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
735	/** Bit 10 - EffFreqRO - MPERF/APERF. */
736	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
737	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
738	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
739	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
740	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
741	/** @} */
742
743
744	/** @name CPUID AMD SVM Feature information.
745	* CPUID query with EAX=0x8000000a.
746	* @{
747	*/
748	/** Bit 0 - NP - Nested Paging supported. */
749	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
750	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
751	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
752	/** Bit 2 - SVML - SVM locking bit supported. */
753	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
754	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
755	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
756	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
757	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
758	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
759	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
760	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
761	* VMCB.TLB_Control is supported. */
762	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
763	/** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
764	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
765	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
766	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
767	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
768	* intercept filter cycle count threshold. */
769	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
770	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
771	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
772	/** @} */
773
774
775	/** @name CR0
776	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
777	* reserved flags.
778	* @{ */
779	/** Bit 0 - PE - Protection Enabled */
780	#define X86_CR0_PE RT_BIT_32(0)
781	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
782	/** Bit 1 - MP - Monitor Coprocessor */
783	#define X86_CR0_MP RT_BIT_32(1)
784	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
785	/** Bit 2 - EM - Emulation. */
786	#define X86_CR0_EM RT_BIT_32(2)
787	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
788	/** Bit 3 - TS - Task Switch. */
789	#define X86_CR0_TS RT_BIT_32(3)
790	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
791	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
792	#define X86_CR0_ET RT_BIT_32(4)
793	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
794	/** Bit 5 - NE - Numeric error (486+). */
795	#define X86_CR0_NE RT_BIT_32(5)
796	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
797	/** Bit 16 - WP - Write Protect (486+). */
798	#define X86_CR0_WP RT_BIT_32(16)
799	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
800	/** Bit 18 - AM - Alignment Mask (486+). */
801	#define X86_CR0_AM RT_BIT_32(18)
802	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
803	/** Bit 29 - NW - Not Write-though (486+). */
804	#define X86_CR0_NW RT_BIT_32(29)
805	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
806	/** Bit 30 - WP - Cache Disable (486+). */
807	#define X86_CR0_CD RT_BIT_32(30)
808	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
809	/** Bit 31 - PG - Paging. */
810	#define X86_CR0_PG RT_BIT_32(31)
811	#define X86_CR0_PAGING RT_BIT_32(31)
812	/** @} */
813
814
815	/** @name CR3
816	* @{ */
817	/** Bit 3 - PWT - Page-level Writes Transparent. */
818	#define X86_CR3_PWT RT_BIT_32(3)
819	/** Bit 4 - PCD - Page-level Cache Disable. */
820	#define X86_CR3_PCD RT_BIT_32(4)
821	/** Bits 12-31 - - Page directory page number. */
822	#define X86_CR3_PAGE_MASK (0xfffff000)
823	/** Bits 5-31 - - PAE Page directory page number. */
824	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
825	/** Bits 12-51 - - AMD64 Page directory page number. */
826	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
827	/** @} */
828
829
830	/** @name CR4
831	* @{ */
832	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
833	#define X86_CR4_VME RT_BIT_32(0)
834	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
835	#define X86_CR4_PVI RT_BIT_32(1)
836	/** Bit 2 - TSD - Time Stamp Disable. */
837	#define X86_CR4_TSD RT_BIT_32(2)
838	/** Bit 3 - DE - Debugging Extensions. */
839	#define X86_CR4_DE RT_BIT_32(3)
840	/** Bit 4 - PSE - Page Size Extension. */
841	#define X86_CR4_PSE RT_BIT_32(4)
842	/** Bit 5 - PAE - Physical Address Extension. */
843	#define X86_CR4_PAE RT_BIT_32(5)
844	/** Bit 6 - MCE - Machine-Check Enable. */
845	#define X86_CR4_MCE RT_BIT_32(6)
846	/** Bit 7 - PGE - Page Global Enable. */
847	#define X86_CR4_PGE RT_BIT_32(7)
848	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
849	#define X86_CR4_PCE RT_BIT_32(8)
850	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
851	#define X86_CR4_OSFXSR RT_BIT_32(9)
852	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
853	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
854	/** Bit 13 - VMXE - VMX mode is enabled. */
855	#define X86_CR4_VMXE RT_BIT_32(13)
856	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
857	#define X86_CR4_SMXE RT_BIT_32(14)
858	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
859	#define X86_CR4_PCIDE RT_BIT_32(17)
860	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
861	* extended states. */
862	#define X86_CR4_OSXSAVE RT_BIT_32(18)
863	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
864	#define X86_CR4_SMEP RT_BIT_32(20)
865	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
866	#define X86_CR4_SMAP RT_BIT_32(21)
867	/** Bit 22 - PKE - Protection Key Enable. */
868	#define X86_CR4_PKE RT_BIT_32(22)
869	/** @} */
870
871
872	/** @name DR6
873	* @{ */
874	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
875	#define X86_DR6_B0 RT_BIT_32(0)
876	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
877	#define X86_DR6_B1 RT_BIT_32(1)
878	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
879	#define X86_DR6_B2 RT_BIT_32(2)
880	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
881	#define X86_DR6_B3 RT_BIT_32(3)
882	/** Mask of all the Bx bits. */
883	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
884	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
885	#define X86_DR6_BD RT_BIT_32(13)
886	/** Bit 14 - BS - Single step */
887	#define X86_DR6_BS RT_BIT_32(14)
888	/** Bit 15 - BT - Task switch. (TSS T bit.) */
889	#define X86_DR6_BT RT_BIT_32(15)
890	/** Value of DR6 after powerup/reset. */
891	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
892	/** Bits which must be 1s in DR6. */
893	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
894	/** Bits which must be 0s in DR6. */
895	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
896	/** Bits which must be 0s on writes to DR6. */
897	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
898	/** @} */
899
900	/** Get the DR6.Bx bit for a the given breakpoint. */
901	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
902
903
904	/** @name DR7
905	* @{ */
906	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
907	#define X86_DR7_L0 RT_BIT_32(0)
908	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
909	#define X86_DR7_G0 RT_BIT_32(1)
910	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
911	#define X86_DR7_L1 RT_BIT_32(2)
912	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
913	#define X86_DR7_G1 RT_BIT_32(3)
914	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
915	#define X86_DR7_L2 RT_BIT_32(4)
916	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
917	#define X86_DR7_G2 RT_BIT_32(5)
918	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
919	#define X86_DR7_L3 RT_BIT_32(6)
920	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
921	#define X86_DR7_G3 RT_BIT_32(7)
922	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
923	#define X86_DR7_LE RT_BIT_32(8)
924	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
925	#define X86_DR7_GE RT_BIT_32(9)
926
927	/** L0, L1, L2, and L3. */
928	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
929	/** L0, L1, L2, and L3. */
930	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
931
932	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
933	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
934	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
935	* instruction is executed.
936	* @see http://www.rcollins.org/secrets/DR7.html */
937	#define X86_DR7_ICE_IR RT_BIT_32(12)
938	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
939	* any DR register is accessed. */
940	#define X86_DR7_GD RT_BIT_32(13)
941	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
942	* Pentium. */
943	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
944	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
945	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
946	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
947	#define X86_DR7_RW0_MASK (3 << 16)
948	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
949	#define X86_DR7_LEN0_MASK (3 << 18)
950	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
951	#define X86_DR7_RW1_MASK (3 << 20)
952	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
953	#define X86_DR7_LEN1_MASK (3 << 22)
954	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
955	#define X86_DR7_RW2_MASK (3 << 24)
956	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
957	#define X86_DR7_LEN2_MASK (3 << 26)
958	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
959	#define X86_DR7_RW3_MASK (3 << 28)
960	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
961	#define X86_DR7_LEN3_MASK (3 << 30)
962
963	/** Bits which reads as 1s. */
964	#define X86_DR7_RA1_MASK RT_BIT_32(10)
965	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
966	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
967	/** Bits which must be 0s when writing to DR7. */
968	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
969
970	/** Calcs the L bit of Nth breakpoint.
971	* @param iBp The breakpoint number [0..3].
972	*/
973	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
974
975	/** Calcs the G bit of Nth breakpoint.
976	* @param iBp The breakpoint number [0..3].
977	*/
978	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
979
980	/** Calcs the L and G bits of Nth breakpoint.
981	* @param iBp The breakpoint number [0..3].
982	*/
983	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
984
985	/** @name Read/Write values.
986	* @{ */
987	/** Break on instruction fetch only. */
988	#define X86_DR7_RW_EO 0U
989	/** Break on write only. */
990	#define X86_DR7_RW_WO 1U
991	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
992	#define X86_DR7_RW_IO 2U
993	/** Break on read or write (but not instruction fetches). */
994	#define X86_DR7_RW_RW 3U
995	/** @} */
996
997	/** Shifts a X86_DR7_RW_* value to its right place.
998	* @param iBp The breakpoint number [0..3].
999	* @param fRw One of the X86_DR7_RW_* value.
1000	*/
1001	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1002
1003	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1004	* one of the X86_DR7_RW_XXX constants).
1005	*
1006	* @returns X86_DR7_RW_XXX
1007	* @param uDR7 DR7 value
1008	* @param iBp The breakpoint number [0..3].
1009	*/
1010	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1011
1012	/** R/W0, R/W1, R/W2, and R/W3. */
1013	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1014
1015	#ifndef VBOX_FOR_DTRACE_LIB
1016	/** Checks if there are any I/O breakpoint types configured in the RW
1017	* registers. Does NOT check if these are enabled, sorry. */
1018	# define X86_DR7_ANY_RW_IO(uDR7) \
1019	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1020	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1021	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1022	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1023	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1024	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1025	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1026	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1027	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1028	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1029	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1030	#endif /* !VBOX_FOR_DTRACE_LIB */
1031
1032	/** @name Length values.
1033	* @{ */
1034	#define X86_DR7_LEN_BYTE 0U
1035	#define X86_DR7_LEN_WORD 1U
1036	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
1037	#define X86_DR7_LEN_DWORD 3U
1038	/** @} */
1039
1040	/** Shifts a X86_DR7_LEN_* value to its right place.
1041	* @param iBp The breakpoint number [0..3].
1042	* @param cb One of the X86_DR7_LEN_* values.
1043	*/
1044	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1045
1046	/** Fetch the breakpoint length bits from the DR7 value.
1047	* @param uDR7 DR7 value
1048	* @param iBp The breakpoint number [0..3].
1049	*/
1050	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1051
1052	/** Mask used to check if any breakpoints are enabled. */
1053	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1054
1055	/** LEN0, LEN1, LEN2, and LEN3. */
1056	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1057	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1058	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1059
1060	/** Value of DR7 after powerup/reset. */
1061	#define X86_DR7_INIT_VAL 0x400
1062	/** @} */
1063
1064
1065	/** @name Machine Specific Registers
1066	* @{
1067	*/
1068	/** Machine check address register (P5). */
1069	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1070	/** Machine check type register (P5). */
1071	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1072	/** Time Stamp Counter. */
1073	#define MSR_IA32_TSC 0x10
1074	#define MSR_IA32_CESR UINT32_C(0x00000011)
1075	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1076	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1077
1078	#define MSR_IA32_PLATFORM_ID 0x17
1079
1080	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1081	# define MSR_IA32_APICBASE 0x1b
1082	/** Local APIC enabled. */
1083	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1084	/** X2APIC enabled (requires the EN bit to be set). */
1085	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1086	/** The processor is the boot strap processor (BSP). */
1087	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1088	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1089	* width. */
1090	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1091	/** The default physical base address of the APIC. */
1092	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1093	/** Gets the physical base address from the MSR. */
1094	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1095	#endif
1096
1097	/** Undocumented intel MSR for reporting thread and core counts.
1098	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1099	* first 16 bits is the thread count. The next 16 bits the core count, except
1100	* on Westmere where it seems it's only the next 4 bits for some reason. */
1101	#define MSR_CORE_THREAD_COUNT 0x35
1102
1103	/** CPU Feature control. */
1104	#define MSR_IA32_FEATURE_CONTROL 0x3A
1105	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
1106	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
1107	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
1108
1109	/** Per-processor TSC adjust MSR. */
1110	#define MSR_IA32_TSC_ADJUST 0x3B
1111
1112	/** BIOS update trigger (microcode update). */
1113	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1114
1115	/** BIOS update signature (microcode). */
1116	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1117
1118	/** SMM monitor control. */
1119	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1120
1121	/** General performance counter no. 0. */
1122	#define MSR_IA32_PMC0 0xC1
1123	/** General performance counter no. 1. */
1124	#define MSR_IA32_PMC1 0xC2
1125	/** General performance counter no. 2. */
1126	#define MSR_IA32_PMC2 0xC3
1127	/** General performance counter no. 3. */
1128	#define MSR_IA32_PMC3 0xC4
1129
1130	/** Nehalem power control. */
1131	#define MSR_IA32_PLATFORM_INFO 0xCE
1132
1133	/** Get FSB clock status (Intel-specific). */
1134	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1135
1136	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1137	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1138
1139	/** C0 Maximum Frequency Clock Count */
1140	#define MSR_IA32_MPERF 0xE7
1141	/** C0 Actual Frequency Clock Count */
1142	#define MSR_IA32_APERF 0xE8
1143
1144	/** MTRR Capabilities. */
1145	#define MSR_IA32_MTRR_CAP 0xFE
1146
1147	/** Cache control/info. */
1148	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1149
1150	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1151	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1152	* R0 SS == CS + 8
1153	* R3 CS == CS + 16
1154	* R3 SS == CS + 24
1155	*/
1156	#define MSR_IA32_SYSENTER_CS 0x174
1157	/** SYSENTER_ESP - the R0 ESP. */
1158	#define MSR_IA32_SYSENTER_ESP 0x175
1159	/** SYSENTER_EIP - the R0 EIP. */
1160	#define MSR_IA32_SYSENTER_EIP 0x176
1161	#endif
1162
1163	/** Machine Check Global Capabilities Register. */
1164	#define MSR_IA32_MCG_CAP 0x179
1165	/** Machine Check Global Status Register. */
1166	#define MSR_IA32_MCG_STATUS 0x17A
1167	/** Machine Check Global Control Register. */
1168	#define MSR_IA32_MCG_CTRL 0x17B
1169
1170	/** Page Attribute Table. */
1171	#define MSR_IA32_CR_PAT 0x277
1172
1173	/** Performance counter MSRs. (Intel only) */
1174	#define MSR_IA32_PERFEVTSEL0 0x186
1175	#define MSR_IA32_PERFEVTSEL1 0x187
1176	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1177	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1178	* holds a ratio that Apple takes for TSC granularity.
1179	*
1180	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1181	#define MSR_FLEX_RATIO 0x194
1182	/** Performance state value and starting with Intel core more.
1183	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1184	#define MSR_IA32_PERF_STATUS 0x198
1185	#define MSR_IA32_PERF_CTL 0x199
1186	#define MSR_IA32_THERM_STATUS 0x19c
1187
1188	/** Enable misc. processor features (R/W). */
1189	#define MSR_IA32_MISC_ENABLE 0x1A0
1190	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1191	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1192	/** Automatic Thermal Control Circuit Enable (R/W). */
1193	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1194	/** Performance Monitoring Available (R). */
1195	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1196	/** Branch Trace Storage Unavailable (R/O). */
1197	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1198	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1199	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1200	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1201	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1202	/** If MONITOR/MWAIT is supported (R/W). */
1203	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1204	/** Limit CPUID Maxval to 3 leafs (R/W). */
1205	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1206	/** When set to 1, xTPR messages are disabled (R/W). */
1207	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1208	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1209	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1210
1211	/** Trace/Profile Resource Control (R/W) */
1212	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1213	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1214	* related Xeons. */
1215	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1216	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1217	* @{ */
1218	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1219	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1220	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1221	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1222	/** @} */
1223
1224
1225	#define IA32_MTRR_PHYSBASE0 0x200
1226	#define IA32_MTRR_PHYSMASK0 0x201
1227	#define IA32_MTRR_PHYSBASE1 0x202
1228	#define IA32_MTRR_PHYSMASK1 0x203
1229	#define IA32_MTRR_PHYSBASE2 0x204
1230	#define IA32_MTRR_PHYSMASK2 0x205
1231	#define IA32_MTRR_PHYSBASE3 0x206
1232	#define IA32_MTRR_PHYSMASK3 0x207
1233	#define IA32_MTRR_PHYSBASE4 0x208
1234	#define IA32_MTRR_PHYSMASK4 0x209
1235	#define IA32_MTRR_PHYSBASE5 0x20a
1236	#define IA32_MTRR_PHYSMASK5 0x20b
1237	#define IA32_MTRR_PHYSBASE6 0x20c
1238	#define IA32_MTRR_PHYSMASK6 0x20d
1239	#define IA32_MTRR_PHYSBASE7 0x20e
1240	#define IA32_MTRR_PHYSMASK7 0x20f
1241	#define IA32_MTRR_PHYSBASE8 0x210
1242	#define IA32_MTRR_PHYSMASK8 0x211
1243	#define IA32_MTRR_PHYSBASE9 0x212
1244	#define IA32_MTRR_PHYSMASK9 0x213
1245
1246	/** Fixed range MTRRs.
1247	* @{ */
1248	#define IA32_MTRR_FIX64K_00000 0x250
1249	#define IA32_MTRR_FIX16K_80000 0x258
1250	#define IA32_MTRR_FIX16K_A0000 0x259
1251	#define IA32_MTRR_FIX4K_C0000 0x268
1252	#define IA32_MTRR_FIX4K_C8000 0x269
1253	#define IA32_MTRR_FIX4K_D0000 0x26a
1254	#define IA32_MTRR_FIX4K_D8000 0x26b
1255	#define IA32_MTRR_FIX4K_E0000 0x26c
1256	#define IA32_MTRR_FIX4K_E8000 0x26d
1257	#define IA32_MTRR_FIX4K_F0000 0x26e
1258	#define IA32_MTRR_FIX4K_F8000 0x26f
1259	/** @} */
1260
1261	/** MTRR Default Range. */
1262	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1263
1264	/** Global performance counter control facilities (Intel only). */
1265	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1266	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1267	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1268
1269	/** Precise Event Based sampling (Intel only). */
1270	#define MSR_IA32_PEBS_ENABLE 0x3F1
1271
1272	#define MSR_IA32_MC0_CTL 0x400
1273	#define MSR_IA32_MC0_STATUS 0x401
1274
1275	/** Basic VMX information. */
1276	#define MSR_IA32_VMX_BASIC_INFO 0x480
1277	/** Allowed settings for pin-based VM execution controls */
1278	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1279	/** Allowed settings for proc-based VM execution controls */
1280	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1281	/** Allowed settings for the VMX exit controls. */
1282	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1283	/** Allowed settings for the VMX entry controls. */
1284	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1285	/** Misc VMX info. */
1286	#define MSR_IA32_VMX_MISC 0x485
1287	/** Fixed cleared bits in CR0. */
1288	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1289	/** Fixed set bits in CR0. */
1290	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1291	/** Fixed cleared bits in CR4. */
1292	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1293	/** Fixed set bits in CR4. */
1294	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1295	/** Information for enumerating fields in the VMCS. */
1296	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1297	/** Allowed settings for the VM-functions controls. */
1298	#define MSR_IA32_VMX_VMFUNC 0x491
1299	/** Allowed settings for secondary proc-based VM execution controls */
1300	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1301	/** EPT capabilities. */
1302	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1303	/** Allowed settings of all pin-based VM execution controls. */
1304	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1305	/** Allowed settings of all proc-based VM execution controls. */
1306	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1307	/** Allowed settings of all VMX exit controls. */
1308	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1309	/** Allowed settings of all VMX entry controls. */
1310	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1311
1312	/** DS Save Area (R/W). */
1313	#define MSR_IA32_DS_AREA 0x600
1314	/** Running Average Power Limit (RAPL) power units. */
1315	#define MSR_RAPL_POWER_UNIT 0x606
1316
1317	/** X2APIC MSR range start. */
1318	#define MSR_IA32_X2APIC_START 0x800
1319	/** X2APIC MSR - APIC ID Register. */
1320	#define MSR_IA32_X2APIC_ID 0x802
1321	/** X2APIC MSR - APIC Version Register. */
1322	#define MSR_IA32_X2APIC_VERSION 0x803
1323	/** X2APIC MSR - Task Priority Register. */
1324	#define MSR_IA32_X2APIC_TPR 0x808
1325	/** X2APIC MSR - Processor Priority register. */
1326	#define MSR_IA32_X2APIC_PPR 0x80A
1327	/** X2APIC MSR - End Of Interrupt register. */
1328	#define MSR_IA32_X2APIC_EOI 0x80B
1329	/** X2APIC MSR - Logical Destination Register. */
1330	#define MSR_IA32_X2APIC_LDR 0x80D
1331	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1332	#define MSR_IA32_X2APIC_SVR 0x80F
1333	/** X2APIC MSR - In-service Register (bits 31:0). */
1334	#define MSR_IA32_X2APIC_ISR0 0x810
1335	/** X2APIC MSR - In-service Register (bits 63:32). */
1336	#define MSR_IA32_X2APIC_ISR1 0x811
1337	/** X2APIC MSR - In-service Register (bits 95:64). */
1338	#define MSR_IA32_X2APIC_ISR2 0x812
1339	/** X2APIC MSR - In-service Register (bits 127:96). */
1340	#define MSR_IA32_X2APIC_ISR3 0x813
1341	/** X2APIC MSR - In-service Register (bits 159:128). */
1342	#define MSR_IA32_X2APIC_ISR4 0x814
1343	/** X2APIC MSR - In-service Register (bits 191:160). */
1344	#define MSR_IA32_X2APIC_ISR5 0x815
1345	/** X2APIC MSR - In-service Register (bits 223:192). */
1346	#define MSR_IA32_X2APIC_ISR6 0x816
1347	/** X2APIC MSR - In-service Register (bits 255:224). */
1348	#define MSR_IA32_X2APIC_ISR7 0x817
1349	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1350	#define MSR_IA32_X2APIC_TMR0 0x818
1351	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1352	#define MSR_IA32_X2APIC_TMR1 0x819
1353	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1354	#define MSR_IA32_X2APIC_TMR2 0x81A
1355	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1356	#define MSR_IA32_X2APIC_TMR3 0x81B
1357	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1358	#define MSR_IA32_X2APIC_TMR4 0x81C
1359	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1360	#define MSR_IA32_X2APIC_TMR5 0x81D
1361	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1362	#define MSR_IA32_X2APIC_TMR6 0x81E
1363	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1364	#define MSR_IA32_X2APIC_TMR7 0x81F
1365	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1366	#define MSR_IA32_X2APIC_IRR0 0x820
1367	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1368	#define MSR_IA32_X2APIC_IRR1 0x821
1369	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1370	#define MSR_IA32_X2APIC_IRR2 0x822
1371	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1372	#define MSR_IA32_X2APIC_IRR3 0x823
1373	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1374	#define MSR_IA32_X2APIC_IRR4 0x824
1375	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1376	#define MSR_IA32_X2APIC_IRR5 0x825
1377	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1378	#define MSR_IA32_X2APIC_IRR6 0x826
1379	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1380	#define MSR_IA32_X2APIC_IRR7 0x827
1381	/** X2APIC MSR - Error Status Register. */
1382	#define MSR_IA32_X2APIC_ESR 0x828
1383	/** X2APIC MSR - LVT CMCI Register. */
1384	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1385	/** X2APIC MSR - Interrupt Command Register. */
1386	#define MSR_IA32_X2APIC_ICR 0x830
1387	/** X2APIC MSR - LVT Timer Register. */
1388	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1389	/** X2APIC MSR - LVT Thermal Sensor Register. */
1390	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1391	/** X2APIC MSR - LVT Performance Counter Register. */
1392	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1393	/** X2APIC MSR - LVT LINT0 Register. */
1394	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1395	/** X2APIC MSR - LVT LINT1 Register. */
1396	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1397	/** X2APIC MSR - LVT Error Register . */
1398	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1399	/** X2APIC MSR - Timer Initial Count Register. */
1400	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1401	/** X2APIC MSR - Timer Current Count Register. */
1402	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1403	/** X2APIC MSR - Timer Divide Configuration Register. */
1404	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1405	/** X2APIC MSR - Self IPI. */
1406	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1407	/** X2APIC MSR range end. */
1408	#define MSR_IA32_X2APIC_END 0xBFF
1409	/** X2APIC MSR - LVT start range. */
1410	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1411	/** X2APIC MSR - LVT end range (inclusive). */
1412	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1413
1414	/** K6 EFER - Extended Feature Enable Register. */
1415	#define MSR_K6_EFER UINT32_C(0xc0000080)
1416	/** @todo document EFER */
1417	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1418	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1419	/** Bit 8 - LME - Long mode enabled. (R/W) */
1420	#define MSR_K6_EFER_LME RT_BIT_32(8)
1421	/** Bit 10 - LMA - Long mode active. (R) */
1422	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1423	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1424	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1425	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1426	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1427	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1428	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1429	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1430	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1431	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1432	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1433	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1434	/** K6 STAR - SYSCALL/RET targets. */
1435	#define MSR_K6_STAR UINT32_C(0xc0000081)
1436	/** Shift value for getting the SYSRET CS and SS value. */
1437	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1438	/** Shift value for getting the SYSCALL CS and SS value. */
1439	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1440	/** Selector mask for use after shifting. */
1441	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1442	/** The mask which give the SYSCALL EIP. */
1443	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1444	/** K6 WHCR - Write Handling Control Register. */
1445	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1446	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1447	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1448	/** K6 PSOR - Processor State Observability Register. */
1449	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1450	/** K6 PFIR - Page Flush/Invalidate Register. */
1451	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1452
1453	/** Performance counter MSRs. (AMD only) */
1454	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1455	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1456	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1457	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1458	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1459	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1460	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1461	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1462
1463	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1464	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1465	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1466	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1467	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1468	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1469	/** K8 FS.base - The 64-bit base FS register. */
1470	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1471	/** K8 GS.base - The 64-bit base GS register. */
1472	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1473	/** K8 KernelGSbase - Used with SWAPGS. */
1474	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1475	/** K8 TSC_AUX - Used with RDTSCP. */
1476	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1477	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1478	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1479	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1480	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1481	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1482	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1483	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1484	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1485	/** North bridge config? See BIOS & Kernel dev guides for
1486	* details. */
1487	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1488
1489	/** Hypertransport interrupt pending register.
1490	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1491	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1492
1493	/** SVM Control. */
1494	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1495	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1496	* features. */
1497	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1498	/** If set, non-intercepted INIT signals are converted to \#SX
1499	* exceptions. */
1500	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1501	/** Disables A20 masking. */
1502	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1503	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1504	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1505	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1506	* clear, EFER.SVME can be written normally. */
1507	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1508
1509	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1510	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1511	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1512	* host state during world switch. */
1513	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1514
1515	/** @} */
1516
1517
1518	/** @name Page Table / Directory / Directory Pointers / L4.
1519	* @{
1520	*/
1521
1522	/** Page table/directory entry as an unsigned integer. */
1523	typedef uint32_t X86PGUINT;
1524	/** Pointer to a page table/directory table entry as an unsigned integer. */
1525	typedef X86PGUINT *PX86PGUINT;
1526	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1527	typedef X86PGUINT const *PCX86PGUINT;
1528
1529	/** Number of entries in a 32-bit PT/PD. */
1530	#define X86_PG_ENTRIES 1024
1531
1532
1533	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1534	typedef uint64_t X86PGPAEUINT;
1535	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1536	typedef X86PGPAEUINT *PX86PGPAEUINT;
1537	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1538	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1539
1540	/** Number of entries in a PAE PT/PD. */
1541	#define X86_PG_PAE_ENTRIES 512
1542	/** Number of entries in a PAE PDPT. */
1543	#define X86_PG_PAE_PDPE_ENTRIES 4
1544
1545	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1546	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1547	/** Number of entries in an AMD64 PDPT.
1548	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1549	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1550
1551	/** The size of a default page. */
1552	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1553	/** The page shift of a default page. */
1554	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1555	/** The default page offset mask. */
1556	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1557	/** The default page base mask for virtual addresses. */
1558	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1559	/** The default page base mask for virtual addresses - 32bit version. */
1560	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1561
1562	/** The size of a 4KB page. */
1563	#define X86_PAGE_4K_SIZE _4K
1564	/** The page shift of a 4KB page. */
1565	#define X86_PAGE_4K_SHIFT 12
1566	/** The 4KB page offset mask. */
1567	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1568	/** The 4KB page base mask for virtual addresses. */
1569	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1570	/** The 4KB page base mask for virtual addresses - 32bit version. */
1571	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1572
1573	/** The size of a 2MB page. */
1574	#define X86_PAGE_2M_SIZE _2M
1575	/** The page shift of a 2MB page. */
1576	#define X86_PAGE_2M_SHIFT 21
1577	/** The 2MB page offset mask. */
1578	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1579	/** The 2MB page base mask for virtual addresses. */
1580	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1581	/** The 2MB page base mask for virtual addresses - 32bit version. */
1582	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1583
1584	/** The size of a 4MB page. */
1585	#define X86_PAGE_4M_SIZE _4M
1586	/** The page shift of a 4MB page. */
1587	#define X86_PAGE_4M_SHIFT 22
1588	/** The 4MB page offset mask. */
1589	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1590	/** The 4MB page base mask for virtual addresses. */
1591	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1592	/** The 4MB page base mask for virtual addresses - 32bit version. */
1593	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1594
1595	/**
1596	* Check if the given address is canonical.
1597	*/
1598	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1599
1600
1601	/** @name Page Table Entry
1602	* @{
1603	*/
1604	/** Bit 0 - P - Present bit. */
1605	#define X86_PTE_BIT_P 0
1606	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1607	#define X86_PTE_BIT_RW 1
1608	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1609	#define X86_PTE_BIT_US 2
1610	/** Bit 3 - PWT - Page level write thru bit. */
1611	#define X86_PTE_BIT_PWT 3
1612	/** Bit 4 - PCD - Page level cache disable bit. */
1613	#define X86_PTE_BIT_PCD 4
1614	/** Bit 5 - A - Access bit. */
1615	#define X86_PTE_BIT_A 5
1616	/** Bit 6 - D - Dirty bit. */
1617	#define X86_PTE_BIT_D 6
1618	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1619	#define X86_PTE_BIT_PAT 7
1620	/** Bit 8 - G - Global flag. */
1621	#define X86_PTE_BIT_G 8
1622	/** Bits 63 - NX - PAE/LM - No execution flag. */
1623	#define X86_PTE_PAE_BIT_NX 63
1624
1625	/** Bit 0 - P - Present bit mask. */
1626	#define X86_PTE_P RT_BIT_32(0)
1627	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1628	#define X86_PTE_RW RT_BIT_32(1)
1629	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1630	#define X86_PTE_US RT_BIT_32(2)
1631	/** Bit 3 - PWT - Page level write thru bit mask. */
1632	#define X86_PTE_PWT RT_BIT_32(3)
1633	/** Bit 4 - PCD - Page level cache disable bit mask. */
1634	#define X86_PTE_PCD RT_BIT_32(4)
1635	/** Bit 5 - A - Access bit mask. */
1636	#define X86_PTE_A RT_BIT_32(5)
1637	/** Bit 6 - D - Dirty bit mask. */
1638	#define X86_PTE_D RT_BIT_32(6)
1639	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1640	#define X86_PTE_PAT RT_BIT_32(7)
1641	/** Bit 8 - G - Global bit mask. */
1642	#define X86_PTE_G RT_BIT_32(8)
1643
1644	/** Bits 9-11 - - Available for use to system software. */
1645	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1646	/** Bits 12-31 - - Physical Page number of the next level. */
1647	#define X86_PTE_PG_MASK ( 0xfffff000 )
1648
1649	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1650	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1651	/** Bits 63 - NX - PAE/LM - No execution flag. */
1652	#define X86_PTE_PAE_NX RT_BIT_64(63)
1653	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1654	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1655	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1656	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1657	/** No bits - - LM - MBZ bits when NX is active. */
1658	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1659	/** Bits 63 - - LM - MBZ bits when no NX. */
1660	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1661
1662	/**
1663	* Page table entry.
1664	*/
1665	typedef struct X86PTEBITS
1666	{
1667	/** Flags whether(=1) or not the page is present. */
1668	uint32_t u1Present : 1;
1669	/** Read(=0) / Write(=1) flag. */
1670	uint32_t u1Write : 1;
1671	/** User(=1) / Supervisor (=0) flag. */
1672	uint32_t u1User : 1;
1673	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1674	uint32_t u1WriteThru : 1;
1675	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1676	uint32_t u1CacheDisable : 1;
1677	/** Accessed flag.
1678	* Indicates that the page have been read or written to. */
1679	uint32_t u1Accessed : 1;
1680	/** Dirty flag.
1681	* Indicates that the page has been written to. */
1682	uint32_t u1Dirty : 1;
1683	/** Reserved / If PAT enabled, bit 2 of the index. */
1684	uint32_t u1PAT : 1;
1685	/** Global flag. (Ignored in all but final level.) */
1686	uint32_t u1Global : 1;
1687	/** Available for use to system software. */
1688	uint32_t u3Available : 3;
1689	/** Physical Page number of the next level. */
1690	uint32_t u20PageNo : 20;
1691	} X86PTEBITS;
1692	#ifndef VBOX_FOR_DTRACE_LIB
1693	AssertCompileSize(X86PTEBITS, 4);
1694	#endif
1695	/** Pointer to a page table entry. */
1696	typedef X86PTEBITS *PX86PTEBITS;
1697	/** Pointer to a const page table entry. */
1698	typedef const X86PTEBITS *PCX86PTEBITS;
1699
1700	/**
1701	* Page table entry.
1702	*/
1703	typedef union X86PTE
1704	{
1705	/** Unsigned integer view */
1706	X86PGUINT u;
1707	/** Bit field view. */
1708	X86PTEBITS n;
1709	/** 32-bit view. */
1710	uint32_t au32[1];
1711	/** 16-bit view. */
1712	uint16_t au16[2];
1713	/** 8-bit view. */
1714	uint8_t au8[4];
1715	} X86PTE;
1716	#ifndef VBOX_FOR_DTRACE_LIB
1717	AssertCompileSize(X86PTE, 4);
1718	#endif
1719	/** Pointer to a page table entry. */
1720	typedef X86PTE *PX86PTE;
1721	/** Pointer to a const page table entry. */
1722	typedef const X86PTE *PCX86PTE;
1723
1724
1725	/**
1726	* PAE page table entry.
1727	*/
1728	typedef struct X86PTEPAEBITS
1729	{
1730	/** Flags whether(=1) or not the page is present. */
1731	uint32_t u1Present : 1;
1732	/** Read(=0) / Write(=1) flag. */
1733	uint32_t u1Write : 1;
1734	/** User(=1) / Supervisor(=0) flag. */
1735	uint32_t u1User : 1;
1736	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1737	uint32_t u1WriteThru : 1;
1738	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1739	uint32_t u1CacheDisable : 1;
1740	/** Accessed flag.
1741	* Indicates that the page have been read or written to. */
1742	uint32_t u1Accessed : 1;
1743	/** Dirty flag.
1744	* Indicates that the page has been written to. */
1745	uint32_t u1Dirty : 1;
1746	/** Reserved / If PAT enabled, bit 2 of the index. */
1747	uint32_t u1PAT : 1;
1748	/** Global flag. (Ignored in all but final level.) */
1749	uint32_t u1Global : 1;
1750	/** Available for use to system software. */
1751	uint32_t u3Available : 3;
1752	/** Physical Page number of the next level - Low Part. Don't use this. */
1753	uint32_t u20PageNoLow : 20;
1754	/** Physical Page number of the next level - High Part. Don't use this. */
1755	uint32_t u20PageNoHigh : 20;
1756	/** MBZ bits */
1757	uint32_t u11Reserved : 11;
1758	/** No Execute flag. */
1759	uint32_t u1NoExecute : 1;
1760	} X86PTEPAEBITS;
1761	#ifndef VBOX_FOR_DTRACE_LIB
1762	AssertCompileSize(X86PTEPAEBITS, 8);
1763	#endif
1764	/** Pointer to a page table entry. */
1765	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1766	/** Pointer to a page table entry. */
1767	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1768
1769	/**
1770	* PAE Page table entry.
1771	*/
1772	typedef union X86PTEPAE
1773	{
1774	/** Unsigned integer view */
1775	X86PGPAEUINT u;
1776	/** Bit field view. */
1777	X86PTEPAEBITS n;
1778	/** 32-bit view. */
1779	uint32_t au32[2];
1780	/** 16-bit view. */
1781	uint16_t au16[4];
1782	/** 8-bit view. */
1783	uint8_t au8[8];
1784	} X86PTEPAE;
1785	#ifndef VBOX_FOR_DTRACE_LIB
1786	AssertCompileSize(X86PTEPAE, 8);
1787	#endif
1788	/** Pointer to a PAE page table entry. */
1789	typedef X86PTEPAE *PX86PTEPAE;
1790	/** Pointer to a const PAE page table entry. */
1791	typedef const X86PTEPAE *PCX86PTEPAE;
1792	/** @} */
1793
1794	/**
1795	* Page table.
1796	*/
1797	typedef struct X86PT
1798	{
1799	/** PTE Array. */
1800	X86PTE a[X86_PG_ENTRIES];
1801	} X86PT;
1802	#ifndef VBOX_FOR_DTRACE_LIB
1803	AssertCompileSize(X86PT, 4096);
1804	#endif
1805	/** Pointer to a page table. */
1806	typedef X86PT *PX86PT;
1807	/** Pointer to a const page table. */
1808	typedef const X86PT *PCX86PT;
1809
1810	/** The page shift to get the PT index. */
1811	#define X86_PT_SHIFT 12
1812	/** The PT index mask (apply to a shifted page address). */
1813	#define X86_PT_MASK 0x3ff
1814
1815
1816	/**
1817	* Page directory.
1818	*/
1819	typedef struct X86PTPAE
1820	{
1821	/** PTE Array. */
1822	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1823	} X86PTPAE;
1824	#ifndef VBOX_FOR_DTRACE_LIB
1825	AssertCompileSize(X86PTPAE, 4096);
1826	#endif
1827	/** Pointer to a page table. */
1828	typedef X86PTPAE *PX86PTPAE;
1829	/** Pointer to a const page table. */
1830	typedef const X86PTPAE *PCX86PTPAE;
1831
1832	/** The page shift to get the PA PTE index. */
1833	#define X86_PT_PAE_SHIFT 12
1834	/** The PAE PT index mask (apply to a shifted page address). */
1835	#define X86_PT_PAE_MASK 0x1ff
1836
1837
1838	/** @name 4KB Page Directory Entry
1839	* @{
1840	*/
1841	/** Bit 0 - P - Present bit. */
1842	#define X86_PDE_P RT_BIT_32(0)
1843	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1844	#define X86_PDE_RW RT_BIT_32(1)
1845	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1846	#define X86_PDE_US RT_BIT_32(2)
1847	/** Bit 3 - PWT - Page level write thru bit. */
1848	#define X86_PDE_PWT RT_BIT_32(3)
1849	/** Bit 4 - PCD - Page level cache disable bit. */
1850	#define X86_PDE_PCD RT_BIT_32(4)
1851	/** Bit 5 - A - Access bit. */
1852	#define X86_PDE_A RT_BIT_32(5)
1853	/** Bit 7 - PS - Page size attribute.
1854	* Clear mean 4KB pages, set means large pages (2/4MB). */
1855	#define X86_PDE_PS RT_BIT_32(7)
1856	/** Bits 9-11 - - Available for use to system software. */
1857	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1858	/** Bits 12-31 - - Physical Page number of the next level. */
1859	#define X86_PDE_PG_MASK ( 0xfffff000 )
1860
1861	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1862	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1863	/** Bits 63 - NX - PAE/LM - No execution flag. */
1864	#define X86_PDE_PAE_NX RT_BIT_64(63)
1865	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1866	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1867	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1868	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1869	/** Bit 7 - - LM - MBZ bits when NX is active. */
1870	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1871	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1872	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1873
1874	/**
1875	* Page directory entry.
1876	*/
1877	typedef struct X86PDEBITS
1878	{
1879	/** Flags whether(=1) or not the page is present. */
1880	uint32_t u1Present : 1;
1881	/** Read(=0) / Write(=1) flag. */
1882	uint32_t u1Write : 1;
1883	/** User(=1) / Supervisor (=0) flag. */
1884	uint32_t u1User : 1;
1885	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1886	uint32_t u1WriteThru : 1;
1887	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1888	uint32_t u1CacheDisable : 1;
1889	/** Accessed flag.
1890	* Indicates that the page has been read or written to. */
1891	uint32_t u1Accessed : 1;
1892	/** Reserved / Ignored (dirty bit). */
1893	uint32_t u1Reserved0 : 1;
1894	/** Size bit if PSE is enabled - in any event it's 0. */
1895	uint32_t u1Size : 1;
1896	/** Reserved / Ignored (global bit). */
1897	uint32_t u1Reserved1 : 1;
1898	/** Available for use to system software. */
1899	uint32_t u3Available : 3;
1900	/** Physical Page number of the next level. */
1901	uint32_t u20PageNo : 20;
1902	} X86PDEBITS;
1903	#ifndef VBOX_FOR_DTRACE_LIB
1904	AssertCompileSize(X86PDEBITS, 4);
1905	#endif
1906	/** Pointer to a page directory entry. */
1907	typedef X86PDEBITS *PX86PDEBITS;
1908	/** Pointer to a const page directory entry. */
1909	typedef const X86PDEBITS *PCX86PDEBITS;
1910
1911
1912	/**
1913	* PAE page directory entry.
1914	*/
1915	typedef struct X86PDEPAEBITS
1916	{
1917	/** Flags whether(=1) or not the page is present. */
1918	uint32_t u1Present : 1;
1919	/** Read(=0) / Write(=1) flag. */
1920	uint32_t u1Write : 1;
1921	/** User(=1) / Supervisor (=0) flag. */
1922	uint32_t u1User : 1;
1923	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1924	uint32_t u1WriteThru : 1;
1925	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1926	uint32_t u1CacheDisable : 1;
1927	/** Accessed flag.
1928	* Indicates that the page has been read or written to. */
1929	uint32_t u1Accessed : 1;
1930	/** Reserved / Ignored (dirty bit). */
1931	uint32_t u1Reserved0 : 1;
1932	/** Size bit if PSE is enabled - in any event it's 0. */
1933	uint32_t u1Size : 1;
1934	/** Reserved / Ignored (global bit). / */
1935	uint32_t u1Reserved1 : 1;
1936	/** Available for use to system software. */
1937	uint32_t u3Available : 3;
1938	/** Physical Page number of the next level - Low Part. Don't use! */
1939	uint32_t u20PageNoLow : 20;
1940	/** Physical Page number of the next level - High Part. Don't use! */
1941	uint32_t u20PageNoHigh : 20;
1942	/** MBZ bits */
1943	uint32_t u11Reserved : 11;
1944	/** No Execute flag. */
1945	uint32_t u1NoExecute : 1;
1946	} X86PDEPAEBITS;
1947	#ifndef VBOX_FOR_DTRACE_LIB
1948	AssertCompileSize(X86PDEPAEBITS, 8);
1949	#endif
1950	/** Pointer to a page directory entry. */
1951	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1952	/** Pointer to a const page directory entry. */
1953	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1954
1955	/** @} */
1956
1957
1958	/** @name 2/4MB Page Directory Entry
1959	* @{
1960	*/
1961	/** Bit 0 - P - Present bit. */
1962	#define X86_PDE4M_P RT_BIT_32(0)
1963	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1964	#define X86_PDE4M_RW RT_BIT_32(1)
1965	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1966	#define X86_PDE4M_US RT_BIT_32(2)
1967	/** Bit 3 - PWT - Page level write thru bit. */
1968	#define X86_PDE4M_PWT RT_BIT_32(3)
1969	/** Bit 4 - PCD - Page level cache disable bit. */
1970	#define X86_PDE4M_PCD RT_BIT_32(4)
1971	/** Bit 5 - A - Access bit. */
1972	#define X86_PDE4M_A RT_BIT_32(5)
1973	/** Bit 6 - D - Dirty bit. */
1974	#define X86_PDE4M_D RT_BIT_32(6)
1975	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1976	#define X86_PDE4M_PS RT_BIT_32(7)
1977	/** Bit 8 - G - Global flag. */
1978	#define X86_PDE4M_G RT_BIT_32(8)
1979	/** Bits 9-11 - AVL - Available for use to system software. */
1980	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1981	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1982	#define X86_PDE4M_PAT RT_BIT_32(12)
1983	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1984	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1985	/** Bits 22-31 - - Physical Page number. */
1986	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1987	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1988	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1989	/** The number of bits to the high part of the page number. */
1990	#define X86_PDE4M_PG_HIGH_SHIFT 19
1991	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1992	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1993
1994	/** Bits 21-51 - - PAE/LM - Physical Page number.
1995	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1996	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1997	/** Bits 63 - NX - PAE/LM - No execution flag. */
1998	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1999	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2000	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2001	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2002	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2003	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2004	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2005	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2006	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2007
2008	/**
2009	* 4MB page directory entry.
2010	*/
2011	typedef struct X86PDE4MBITS
2012	{
2013	/** Flags whether(=1) or not the page is present. */
2014	uint32_t u1Present : 1;
2015	/** Read(=0) / Write(=1) flag. */
2016	uint32_t u1Write : 1;
2017	/** User(=1) / Supervisor (=0) flag. */
2018	uint32_t u1User : 1;
2019	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2020	uint32_t u1WriteThru : 1;
2021	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2022	uint32_t u1CacheDisable : 1;
2023	/** Accessed flag.
2024	* Indicates that the page have been read or written to. */
2025	uint32_t u1Accessed : 1;
2026	/** Dirty flag.
2027	* Indicates that the page has been written to. */
2028	uint32_t u1Dirty : 1;
2029	/** Page size flag - always 1 for 4MB entries. */
2030	uint32_t u1Size : 1;
2031	/** Global flag. */
2032	uint32_t u1Global : 1;
2033	/** Available for use to system software. */
2034	uint32_t u3Available : 3;
2035	/** Reserved / If PAT enabled, bit 2 of the index. */
2036	uint32_t u1PAT : 1;
2037	/** Bits 32-39 of the page number on AMD64.
2038	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2039	uint32_t u8PageNoHigh : 8;
2040	/** Reserved. */
2041	uint32_t u1Reserved : 1;
2042	/** Physical Page number of the page. */
2043	uint32_t u10PageNo : 10;
2044	} X86PDE4MBITS;
2045	#ifndef VBOX_FOR_DTRACE_LIB
2046	AssertCompileSize(X86PDE4MBITS, 4);
2047	#endif
2048	/** Pointer to a page table entry. */
2049	typedef X86PDE4MBITS *PX86PDE4MBITS;
2050	/** Pointer to a const page table entry. */
2051	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2052
2053
2054	/**
2055	* 2MB PAE page directory entry.
2056	*/
2057	typedef struct X86PDE2MPAEBITS
2058	{
2059	/** Flags whether(=1) or not the page is present. */
2060	uint32_t u1Present : 1;
2061	/** Read(=0) / Write(=1) flag. */
2062	uint32_t u1Write : 1;
2063	/** User(=1) / Supervisor(=0) flag. */
2064	uint32_t u1User : 1;
2065	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2066	uint32_t u1WriteThru : 1;
2067	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2068	uint32_t u1CacheDisable : 1;
2069	/** Accessed flag.
2070	* Indicates that the page have been read or written to. */
2071	uint32_t u1Accessed : 1;
2072	/** Dirty flag.
2073	* Indicates that the page has been written to. */
2074	uint32_t u1Dirty : 1;
2075	/** Page size flag - always 1 for 2MB entries. */
2076	uint32_t u1Size : 1;
2077	/** Global flag. */
2078	uint32_t u1Global : 1;
2079	/** Available for use to system software. */
2080	uint32_t u3Available : 3;
2081	/** Reserved / If PAT enabled, bit 2 of the index. */
2082	uint32_t u1PAT : 1;
2083	/** Reserved. */
2084	uint32_t u9Reserved : 9;
2085	/** Physical Page number of the next level - Low part. Don't use! */
2086	uint32_t u10PageNoLow : 10;
2087	/** Physical Page number of the next level - High part. Don't use! */
2088	uint32_t u20PageNoHigh : 20;
2089	/** MBZ bits */
2090	uint32_t u11Reserved : 11;
2091	/** No Execute flag. */
2092	uint32_t u1NoExecute : 1;
2093	} X86PDE2MPAEBITS;
2094	#ifndef VBOX_FOR_DTRACE_LIB
2095	AssertCompileSize(X86PDE2MPAEBITS, 8);
2096	#endif
2097	/** Pointer to a 2MB PAE page table entry. */
2098	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2099	/** Pointer to a 2MB PAE page table entry. */
2100	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2101
2102	/** @} */
2103
2104	/**
2105	* Page directory entry.
2106	*/
2107	typedef union X86PDE
2108	{
2109	/** Unsigned integer view. */
2110	X86PGUINT u;
2111	/** Normal view. */
2112	X86PDEBITS n;
2113	/** 4MB view (big). */
2114	X86PDE4MBITS b;
2115	/** 8 bit unsigned integer view. */
2116	uint8_t au8[4];
2117	/** 16 bit unsigned integer view. */
2118	uint16_t au16[2];
2119	/** 32 bit unsigned integer view. */
2120	uint32_t au32[1];
2121	} X86PDE;
2122	#ifndef VBOX_FOR_DTRACE_LIB
2123	AssertCompileSize(X86PDE, 4);
2124	#endif
2125	/** Pointer to a page directory entry. */
2126	typedef X86PDE *PX86PDE;
2127	/** Pointer to a const page directory entry. */
2128	typedef const X86PDE *PCX86PDE;
2129
2130	/**
2131	* PAE page directory entry.
2132	*/
2133	typedef union X86PDEPAE
2134	{
2135	/** Unsigned integer view. */
2136	X86PGPAEUINT u;
2137	/** Normal view. */
2138	X86PDEPAEBITS n;
2139	/** 2MB page view (big). */
2140	X86PDE2MPAEBITS b;
2141	/** 8 bit unsigned integer view. */
2142	uint8_t au8[8];
2143	/** 16 bit unsigned integer view. */
2144	uint16_t au16[4];
2145	/** 32 bit unsigned integer view. */
2146	uint32_t au32[2];
2147	} X86PDEPAE;
2148	#ifndef VBOX_FOR_DTRACE_LIB
2149	AssertCompileSize(X86PDEPAE, 8);
2150	#endif
2151	/** Pointer to a page directory entry. */
2152	typedef X86PDEPAE *PX86PDEPAE;
2153	/** Pointer to a const page directory entry. */
2154	typedef const X86PDEPAE *PCX86PDEPAE;
2155
2156	/**
2157	* Page directory.
2158	*/
2159	typedef struct X86PD
2160	{
2161	/** PDE Array. */
2162	X86PDE a[X86_PG_ENTRIES];
2163	} X86PD;
2164	#ifndef VBOX_FOR_DTRACE_LIB
2165	AssertCompileSize(X86PD, 4096);
2166	#endif
2167	/** Pointer to a page directory. */
2168	typedef X86PD *PX86PD;
2169	/** Pointer to a const page directory. */
2170	typedef const X86PD *PCX86PD;
2171
2172	/** The page shift to get the PD index. */
2173	#define X86_PD_SHIFT 22
2174	/** The PD index mask (apply to a shifted page address). */
2175	#define X86_PD_MASK 0x3ff
2176
2177
2178	/**
2179	* PAE page directory.
2180	*/
2181	typedef struct X86PDPAE
2182	{
2183	/** PDE Array. */
2184	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2185	} X86PDPAE;
2186	#ifndef VBOX_FOR_DTRACE_LIB
2187	AssertCompileSize(X86PDPAE, 4096);
2188	#endif
2189	/** Pointer to a PAE page directory. */
2190	typedef X86PDPAE *PX86PDPAE;
2191	/** Pointer to a const PAE page directory. */
2192	typedef const X86PDPAE *PCX86PDPAE;
2193
2194	/** The page shift to get the PAE PD index. */
2195	#define X86_PD_PAE_SHIFT 21
2196	/** The PAE PD index mask (apply to a shifted page address). */
2197	#define X86_PD_PAE_MASK 0x1ff
2198
2199
2200	/** @name Page Directory Pointer Table Entry (PAE)
2201	* @{
2202	*/
2203	/** Bit 0 - P - Present bit. */
2204	#define X86_PDPE_P RT_BIT_32(0)
2205	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2206	#define X86_PDPE_RW RT_BIT_32(1)
2207	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2208	#define X86_PDPE_US RT_BIT_32(2)
2209	/** Bit 3 - PWT - Page level write thru bit. */
2210	#define X86_PDPE_PWT RT_BIT_32(3)
2211	/** Bit 4 - PCD - Page level cache disable bit. */
2212	#define X86_PDPE_PCD RT_BIT_32(4)
2213	/** Bit 5 - A - Access bit. Long Mode only. */
2214	#define X86_PDPE_A RT_BIT_32(5)
2215	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2216	#define X86_PDPE_LM_PS RT_BIT_32(7)
2217	/** Bits 9-11 - - Available for use to system software. */
2218	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2219	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2220	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2221	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2222	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2223	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2224	#define X86_PDPE_LM_NX RT_BIT_64(63)
2225	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2226	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2227	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2228	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2229	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2230	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2231	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2232	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2233
2234
2235	/**
2236	* Page directory pointer table entry.
2237	*/
2238	typedef struct X86PDPEBITS
2239	{
2240	/** Flags whether(=1) or not the page is present. */
2241	uint32_t u1Present : 1;
2242	/** Chunk of reserved bits. */
2243	uint32_t u2Reserved : 2;
2244	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2245	uint32_t u1WriteThru : 1;
2246	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2247	uint32_t u1CacheDisable : 1;
2248	/** Chunk of reserved bits. */
2249	uint32_t u4Reserved : 4;
2250	/** Available for use to system software. */
2251	uint32_t u3Available : 3;
2252	/** Physical Page number of the next level - Low Part. Don't use! */
2253	uint32_t u20PageNoLow : 20;
2254	/** Physical Page number of the next level - High Part. Don't use! */
2255	uint32_t u20PageNoHigh : 20;
2256	/** MBZ bits */
2257	uint32_t u12Reserved : 12;
2258	} X86PDPEBITS;
2259	#ifndef VBOX_FOR_DTRACE_LIB
2260	AssertCompileSize(X86PDPEBITS, 8);
2261	#endif
2262	/** Pointer to a page directory pointer table entry. */
2263	typedef X86PDPEBITS *PX86PTPEBITS;
2264	/** Pointer to a const page directory pointer table entry. */
2265	typedef const X86PDPEBITS *PCX86PTPEBITS;
2266
2267	/**
2268	* Page directory pointer table entry. AMD64 version
2269	*/
2270	typedef struct X86PDPEAMD64BITS
2271	{
2272	/** Flags whether(=1) or not the page is present. */
2273	uint32_t u1Present : 1;
2274	/** Read(=0) / Write(=1) flag. */
2275	uint32_t u1Write : 1;
2276	/** User(=1) / Supervisor (=0) flag. */
2277	uint32_t u1User : 1;
2278	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2279	uint32_t u1WriteThru : 1;
2280	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2281	uint32_t u1CacheDisable : 1;
2282	/** Accessed flag.
2283	* Indicates that the page have been read or written to. */
2284	uint32_t u1Accessed : 1;
2285	/** Chunk of reserved bits. */
2286	uint32_t u3Reserved : 3;
2287	/** Available for use to system software. */
2288	uint32_t u3Available : 3;
2289	/** Physical Page number of the next level - Low Part. Don't use! */
2290	uint32_t u20PageNoLow : 20;
2291	/** Physical Page number of the next level - High Part. Don't use! */
2292	uint32_t u20PageNoHigh : 20;
2293	/** MBZ bits */
2294	uint32_t u11Reserved : 11;
2295	/** No Execute flag. */
2296	uint32_t u1NoExecute : 1;
2297	} X86PDPEAMD64BITS;
2298	#ifndef VBOX_FOR_DTRACE_LIB
2299	AssertCompileSize(X86PDPEAMD64BITS, 8);
2300	#endif
2301	/** Pointer to a page directory pointer table entry. */
2302	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2303	/** Pointer to a const page directory pointer table entry. */
2304	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2305
2306	/**
2307	* Page directory pointer table entry for 1GB page. (AMD64 only)
2308	*/
2309	typedef struct X86PDPE1GB
2310	{
2311	/** 0: Flags whether(=1) or not the page is present. */
2312	uint32_t u1Present : 1;
2313	/** 1: Read(=0) / Write(=1) flag. */
2314	uint32_t u1Write : 1;
2315	/** 2: User(=1) / Supervisor (=0) flag. */
2316	uint32_t u1User : 1;
2317	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2318	uint32_t u1WriteThru : 1;
2319	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2320	uint32_t u1CacheDisable : 1;
2321	/** 5: Accessed flag.
2322	* Indicates that the page have been read or written to. */
2323	uint32_t u1Accessed : 1;
2324	/** 6: Dirty flag for 1GB pages. */
2325	uint32_t u1Dirty : 1;
2326	/** 7: Indicates 1GB page if set. */
2327	uint32_t u1Size : 1;
2328	/** 8: Global 1GB page. */
2329	uint32_t u1Global: 1;
2330	/** 9-11: Available for use to system software. */
2331	uint32_t u3Available : 3;
2332	/** 12: PAT bit for 1GB page. */
2333	uint32_t u1PAT : 1;
2334	/** 13-29: MBZ bits. */
2335	uint32_t u17Reserved : 17;
2336	/** 30-31: Physical page number - Low Part. Don't use! */
2337	uint32_t u2PageNoLow : 2;
2338	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2339	uint32_t u20PageNoHigh : 20;
2340	/** 52-62: MBZ bits */
2341	uint32_t u11Reserved : 11;
2342	/** 63: No Execute flag. */
2343	uint32_t u1NoExecute : 1;
2344	} X86PDPE1GB;
2345	#ifndef VBOX_FOR_DTRACE_LIB
2346	AssertCompileSize(X86PDPE1GB, 8);
2347	#endif
2348	/** Pointer to a page directory pointer table entry for a 1GB page. */
2349	typedef X86PDPE1GB *PX86PDPE1GB;
2350	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2351	typedef const X86PDPE1GB *PCX86PDPE1GB;
2352
2353	/**
2354	* Page directory pointer table entry.
2355	*/
2356	typedef union X86PDPE
2357	{
2358	/** Unsigned integer view. */
2359	X86PGPAEUINT u;
2360	/** Normal view. */
2361	X86PDPEBITS n;
2362	/** AMD64 view. */
2363	X86PDPEAMD64BITS lm;
2364	/** AMD64 big view. */
2365	X86PDPE1GB b;
2366	/** 8 bit unsigned integer view. */
2367	uint8_t au8[8];
2368	/** 16 bit unsigned integer view. */
2369	uint16_t au16[4];
2370	/** 32 bit unsigned integer view. */
2371	uint32_t au32[2];
2372	} X86PDPE;
2373	#ifndef VBOX_FOR_DTRACE_LIB
2374	AssertCompileSize(X86PDPE, 8);
2375	#endif
2376	/** Pointer to a page directory pointer table entry. */
2377	typedef X86PDPE *PX86PDPE;
2378	/** Pointer to a const page directory pointer table entry. */
2379	typedef const X86PDPE *PCX86PDPE;
2380
2381
2382	/**
2383	* Page directory pointer table.
2384	*/
2385	typedef struct X86PDPT
2386	{
2387	/** PDE Array. */
2388	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2389	} X86PDPT;
2390	#ifndef VBOX_FOR_DTRACE_LIB
2391	AssertCompileSize(X86PDPT, 4096);
2392	#endif
2393	/** Pointer to a page directory pointer table. */
2394	typedef X86PDPT *PX86PDPT;
2395	/** Pointer to a const page directory pointer table. */
2396	typedef const X86PDPT *PCX86PDPT;
2397
2398	/** The page shift to get the PDPT index. */
2399	#define X86_PDPT_SHIFT 30
2400	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2401	#define X86_PDPT_MASK_PAE 0x3
2402	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2403	#define X86_PDPT_MASK_AMD64 0x1ff
2404
2405	/** @} */
2406
2407
2408	/** @name Page Map Level-4 Entry (Long Mode PAE)
2409	* @{
2410	*/
2411	/** Bit 0 - P - Present bit. */
2412	#define X86_PML4E_P RT_BIT_32(0)
2413	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2414	#define X86_PML4E_RW RT_BIT_32(1)
2415	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2416	#define X86_PML4E_US RT_BIT_32(2)
2417	/** Bit 3 - PWT - Page level write thru bit. */
2418	#define X86_PML4E_PWT RT_BIT_32(3)
2419	/** Bit 4 - PCD - Page level cache disable bit. */
2420	#define X86_PML4E_PCD RT_BIT_32(4)
2421	/** Bit 5 - A - Access bit. */
2422	#define X86_PML4E_A RT_BIT_32(5)
2423	/** Bits 9-11 - - Available for use to system software. */
2424	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2425	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2426	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2427	/** Bits 8, 7 - - MBZ bits when NX is active. */
2428	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2429	/** Bits 63, 7 - - MBZ bits when no NX. */
2430	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2431	/** Bits 63 - NX - PAE - No execution flag. */
2432	#define X86_PML4E_NX RT_BIT_64(63)
2433
2434	/**
2435	* Page Map Level-4 Entry
2436	*/
2437	typedef struct X86PML4EBITS
2438	{
2439	/** Flags whether(=1) or not the page is present. */
2440	uint32_t u1Present : 1;
2441	/** Read(=0) / Write(=1) flag. */
2442	uint32_t u1Write : 1;
2443	/** User(=1) / Supervisor (=0) flag. */
2444	uint32_t u1User : 1;
2445	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2446	uint32_t u1WriteThru : 1;
2447	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2448	uint32_t u1CacheDisable : 1;
2449	/** Accessed flag.
2450	* Indicates that the page have been read or written to. */
2451	uint32_t u1Accessed : 1;
2452	/** Chunk of reserved bits. */
2453	uint32_t u3Reserved : 3;
2454	/** Available for use to system software. */
2455	uint32_t u3Available : 3;
2456	/** Physical Page number of the next level - Low Part. Don't use! */
2457	uint32_t u20PageNoLow : 20;
2458	/** Physical Page number of the next level - High Part. Don't use! */
2459	uint32_t u20PageNoHigh : 20;
2460	/** MBZ bits */
2461	uint32_t u11Reserved : 11;
2462	/** No Execute flag. */
2463	uint32_t u1NoExecute : 1;
2464	} X86PML4EBITS;
2465	#ifndef VBOX_FOR_DTRACE_LIB
2466	AssertCompileSize(X86PML4EBITS, 8);
2467	#endif
2468	/** Pointer to a page map level-4 entry. */
2469	typedef X86PML4EBITS *PX86PML4EBITS;
2470	/** Pointer to a const page map level-4 entry. */
2471	typedef const X86PML4EBITS *PCX86PML4EBITS;
2472
2473	/**
2474	* Page Map Level-4 Entry.
2475	*/
2476	typedef union X86PML4E
2477	{
2478	/** Unsigned integer view. */
2479	X86PGPAEUINT u;
2480	/** Normal view. */
2481	X86PML4EBITS n;
2482	/** 8 bit unsigned integer view. */
2483	uint8_t au8[8];
2484	/** 16 bit unsigned integer view. */
2485	uint16_t au16[4];
2486	/** 32 bit unsigned integer view. */
2487	uint32_t au32[2];
2488	} X86PML4E;
2489	#ifndef VBOX_FOR_DTRACE_LIB
2490	AssertCompileSize(X86PML4E, 8);
2491	#endif
2492	/** Pointer to a page map level-4 entry. */
2493	typedef X86PML4E *PX86PML4E;
2494	/** Pointer to a const page map level-4 entry. */
2495	typedef const X86PML4E *PCX86PML4E;
2496
2497
2498	/**
2499	* Page Map Level-4.
2500	*/
2501	typedef struct X86PML4
2502	{
2503	/** PDE Array. */
2504	X86PML4E a[X86_PG_PAE_ENTRIES];
2505	} X86PML4;
2506	#ifndef VBOX_FOR_DTRACE_LIB
2507	AssertCompileSize(X86PML4, 4096);
2508	#endif
2509	/** Pointer to a page map level-4. */
2510	typedef X86PML4 *PX86PML4;
2511	/** Pointer to a const page map level-4. */
2512	typedef const X86PML4 *PCX86PML4;
2513
2514	/** The page shift to get the PML4 index. */
2515	#define X86_PML4_SHIFT 39
2516	/** The PML4 index mask (apply to a shifted page address). */
2517	#define X86_PML4_MASK 0x1ff
2518
2519	/** @} */
2520
2521	/** @} */
2522
2523	/**
2524	* 32-bit protected mode FSTENV image.
2525	*/
2526	typedef struct X86FSTENV32P
2527	{
2528	uint16_t FCW;
2529	uint16_t padding1;
2530	uint16_t FSW;
2531	uint16_t padding2;
2532	uint16_t FTW;
2533	uint16_t padding3;
2534	uint32_t FPUIP;
2535	uint16_t FPUCS;
2536	uint16_t FOP;
2537	uint32_t FPUDP;
2538	uint16_t FPUDS;
2539	uint16_t padding4;
2540	} X86FSTENV32P;
2541	/** Pointer to a 32-bit protected mode FSTENV image. */
2542	typedef X86FSTENV32P *PX86FSTENV32P;
2543	/** Pointer to a const 32-bit protected mode FSTENV image. */
2544	typedef X86FSTENV32P const *PCX86FSTENV32P;
2545
2546
2547	/**
2548	* 80-bit MMX/FPU register type.
2549	*/
2550	typedef struct X86FPUMMX
2551	{
2552	uint8_t reg[10];
2553	} X86FPUMMX;
2554	#ifndef VBOX_FOR_DTRACE_LIB
2555	AssertCompileSize(X86FPUMMX, 10);
2556	#endif
2557	/** Pointer to a 80-bit MMX/FPU register type. */
2558	typedef X86FPUMMX *PX86FPUMMX;
2559	/** Pointer to a const 80-bit MMX/FPU register type. */
2560	typedef const X86FPUMMX *PCX86FPUMMX;
2561
2562	/** FPU (x87) register. */
2563	typedef union X86FPUREG
2564	{
2565	/** MMX view. */
2566	uint64_t mmx;
2567	/** FPU view - todo. */
2568	X86FPUMMX fpu;
2569	/** Extended precision floating point view. */
2570	RTFLOAT80U r80;
2571	/** Extended precision floating point view v2 */
2572	RTFLOAT80U2 r80Ex;
2573	/** 8-bit view. */
2574	uint8_t au8[16];
2575	/** 16-bit view. */
2576	uint16_t au16[8];
2577	/** 32-bit view. */
2578	uint32_t au32[4];
2579	/** 64-bit view. */
2580	uint64_t au64[2];
2581	/** 128-bit view. (yeah, very helpful) */
2582	uint128_t au128[1];
2583	} X86FPUREG;
2584	#ifndef VBOX_FOR_DTRACE_LIB
2585	AssertCompileSize(X86FPUREG, 16);
2586	#endif
2587	/** Pointer to a FPU register. */
2588	typedef X86FPUREG *PX86FPUREG;
2589	/** Pointer to a const FPU register. */
2590	typedef X86FPUREG const *PCX86FPUREG;
2591
2592	/**
2593	* XMM register union.
2594	*/
2595	typedef union X86XMMREG
2596	{
2597	/** XMM Register view. */
2598	uint128_t xmm;
2599	/** 8-bit view. */
2600	uint8_t au8[16];
2601	/** 16-bit view. */
2602	uint16_t au16[8];
2603	/** 32-bit view. */
2604	uint32_t au32[4];
2605	/** 64-bit view. */
2606	uint64_t au64[2];
2607	/** 128-bit view. (yeah, very helpful) */
2608	uint128_t au128[1];
2609	/** Confusing nested 128-bit union view (this is what xmm should've been). */
2610	RTUINT128U uXmm;
2611	} X86XMMREG;
2612	#ifndef VBOX_FOR_DTRACE_LIB
2613	AssertCompileSize(X86XMMREG, 16);
2614	#endif
2615	/** Pointer to an XMM register state. */
2616	typedef X86XMMREG *PX86XMMREG;
2617	/** Pointer to a const XMM register state. */
2618	typedef X86XMMREG const *PCX86XMMREG;
2619
2620	/**
2621	* YMM register union.
2622	*/
2623	typedef union X86YMMREG
2624	{
2625	/** 8-bit view. */
2626	uint8_t au8[32];
2627	/** 16-bit view. */
2628	uint16_t au16[16];
2629	/** 32-bit view. */
2630	uint32_t au32[8];
2631	/** 64-bit view. */
2632	uint64_t au64[4];
2633	/** 128-bit view. (yeah, very helpful) */
2634	uint128_t au128[2];
2635	/** XMM sub register view. */
2636	X86XMMREG aXmm[2];
2637	} X86YMMREG;
2638	#ifndef VBOX_FOR_DTRACE_LIB
2639	AssertCompileSize(X86YMMREG, 32);
2640	#endif
2641	/** Pointer to an YMM register state. */
2642	typedef X86YMMREG *PX86YMMREG;
2643	/** Pointer to a const YMM register state. */
2644	typedef X86YMMREG const *PCX86YMMREG;
2645
2646	/**
2647	* ZMM register union.
2648	*/
2649	typedef union X86ZMMREG
2650	{
2651	/** 8-bit view. */
2652	uint8_t au8[64];
2653	/** 16-bit view. */
2654	uint16_t au16[32];
2655	/** 32-bit view. */
2656	uint32_t au32[16];
2657	/** 64-bit view. */
2658	uint64_t au64[8];
2659	/** 128-bit view. (yeah, very helpful) */
2660	uint128_t au128[4];
2661	/** XMM sub register view. */
2662	X86XMMREG aXmm[4];
2663	/** YMM sub register view. */
2664	X86YMMREG aYmm[2];
2665	} X86ZMMREG;
2666	#ifndef VBOX_FOR_DTRACE_LIB
2667	AssertCompileSize(X86ZMMREG, 64);
2668	#endif
2669	/** Pointer to an ZMM register state. */
2670	typedef X86ZMMREG *PX86ZMMREG;
2671	/** Pointer to a const ZMM register state. */
2672	typedef X86ZMMREG const *PCX86ZMMREG;
2673
2674
2675	/**
2676	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2677	* @todo verify this...
2678	*/
2679	#pragma pack(1)
2680	typedef struct X86FPUSTATE
2681	{
2682	/** 0x00 - Control word. */
2683	uint16_t FCW;
2684	/** 0x02 - Alignment word */
2685	uint16_t Dummy1;
2686	/** 0x04 - Status word. */
2687	uint16_t FSW;
2688	/** 0x06 - Alignment word */
2689	uint16_t Dummy2;
2690	/** 0x08 - Tag word */
2691	uint16_t FTW;
2692	/** 0x0a - Alignment word */
2693	uint16_t Dummy3;
2694
2695	/** 0x0c - Instruction pointer. */
2696	uint32_t FPUIP;
2697	/** 0x10 - Code selector. */
2698	uint16_t CS;
2699	/** 0x12 - Opcode. */
2700	uint16_t FOP;
2701	/** 0x14 - FOO. */
2702	uint32_t FPUOO;
2703	/** 0x18 - FOS. */
2704	uint32_t FPUOS;
2705	/** 0x1c - FPU register. */
2706	X86FPUREG regs[8];
2707	} X86FPUSTATE;
2708	#pragma pack()
2709	/** Pointer to a FPU state. */
2710	typedef X86FPUSTATE *PX86FPUSTATE;
2711	/** Pointer to a const FPU state. */
2712	typedef const X86FPUSTATE *PCX86FPUSTATE;
2713
2714	/**
2715	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2716	*/
2717	#pragma pack(1)
2718	typedef struct X86FXSTATE
2719	{
2720	/** 0x00 - Control word. */
2721	uint16_t FCW;
2722	/** 0x02 - Status word. */
2723	uint16_t FSW;
2724	/** 0x04 - Tag word. (The upper byte is always zero.) */
2725	uint16_t FTW;
2726	/** 0x06 - Opcode. */
2727	uint16_t FOP;
2728	/** 0x08 - Instruction pointer. */
2729	uint32_t FPUIP;
2730	/** 0x0c - Code selector. */
2731	uint16_t CS;
2732	uint16_t Rsrvd1;
2733	/** 0x10 - Data pointer. */
2734	uint32_t FPUDP;
2735	/** 0x14 - Data segment */
2736	uint16_t DS;
2737	/** 0x16 */
2738	uint16_t Rsrvd2;
2739	/** 0x18 */
2740	uint32_t MXCSR;
2741	/** 0x1c */
2742	uint32_t MXCSR_MASK;
2743	/** 0x20 - FPU registers. */
2744	X86FPUREG aRegs[8];
2745	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2746	X86XMMREG aXMM[16];
2747	/* - offset 416 - */
2748	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2749	/* - offset 464 - Software usable reserved bits. */
2750	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2751	} X86FXSTATE;
2752	#pragma pack()
2753	/** Pointer to a FPU Extended state. */
2754	typedef X86FXSTATE *PX86FXSTATE;
2755	/** Pointer to a const FPU Extended state. */
2756	typedef const X86FXSTATE *PCX86FXSTATE;
2757
2758	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2759	* magic. Don't forget to update x86.mac if you change this! */
2760	#define X86_OFF_FXSTATE_RSVD 0x1d0
2761	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2762	* forget to update x86.mac if you change this!
2763	* @todo r=bird: This has nothing what-so-ever to do here.... */
2764	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2765	#ifndef VBOX_FOR_DTRACE_LIB
2766	AssertCompileSize(X86FXSTATE, 512);
2767	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2768	#endif
2769
2770	/** @name FPU status word flags.
2771	* @{ */
2772	/** Exception Flag: Invalid operation. */
2773	#define X86_FSW_IE RT_BIT_32(0)
2774	/** Exception Flag: Denormalized operand. */
2775	#define X86_FSW_DE RT_BIT_32(1)
2776	/** Exception Flag: Zero divide. */
2777	#define X86_FSW_ZE RT_BIT_32(2)
2778	/** Exception Flag: Overflow. */
2779	#define X86_FSW_OE RT_BIT_32(3)
2780	/** Exception Flag: Underflow. */
2781	#define X86_FSW_UE RT_BIT_32(4)
2782	/** Exception Flag: Precision. */
2783	#define X86_FSW_PE RT_BIT_32(5)
2784	/** Stack fault. */
2785	#define X86_FSW_SF RT_BIT_32(6)
2786	/** Error summary status. */
2787	#define X86_FSW_ES RT_BIT_32(7)
2788	/** Mask of exceptions flags, excluding the summary bit. */
2789	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2790	/** Mask of exceptions flags, including the summary bit. */
2791	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2792	/** Condition code 0. */
2793	#define X86_FSW_C0 RT_BIT_32(8)
2794	/** Condition code 1. */
2795	#define X86_FSW_C1 RT_BIT_32(9)
2796	/** Condition code 2. */
2797	#define X86_FSW_C2 RT_BIT_32(10)
2798	/** Top of the stack mask. */
2799	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2800	/** TOP shift value. */
2801	#define X86_FSW_TOP_SHIFT 11
2802	/** Mask for getting TOP value after shifting it right. */
2803	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2804	/** Get the TOP value. */
2805	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2806	/** Condition code 3. */
2807	#define X86_FSW_C3 RT_BIT_32(14)
2808	/** Mask of exceptions flags, including the summary bit. */
2809	#define X86_FSW_C_MASK UINT16_C(0x4700)
2810	/** FPU busy. */
2811	#define X86_FSW_B RT_BIT_32(15)
2812	/** @} */
2813
2814
2815	/** @name FPU control word flags.
2816	* @{ */
2817	/** Exception Mask: Invalid operation. */
2818	#define X86_FCW_IM RT_BIT_32(0)
2819	/** Exception Mask: Denormalized operand. */
2820	#define X86_FCW_DM RT_BIT_32(1)
2821	/** Exception Mask: Zero divide. */
2822	#define X86_FCW_ZM RT_BIT_32(2)
2823	/** Exception Mask: Overflow. */
2824	#define X86_FCW_OM RT_BIT_32(3)
2825	/** Exception Mask: Underflow. */
2826	#define X86_FCW_UM RT_BIT_32(4)
2827	/** Exception Mask: Precision. */
2828	#define X86_FCW_PM RT_BIT_32(5)
2829	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2830	* @remarks This includes reserved bit 6. */
2831	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2832	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2833	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2834	/** Precision control mask. */
2835	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2836	/** Precision control: 24-bit. */
2837	#define X86_FCW_PC_24 UINT16_C(0x0000)
2838	/** Precision control: Reserved. */
2839	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2840	/** Precision control: 53-bit. */
2841	#define X86_FCW_PC_53 UINT16_C(0x0200)
2842	/** Precision control: 64-bit. */
2843	#define X86_FCW_PC_64 UINT16_C(0x0300)
2844	/** Rounding control mask. */
2845	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2846	/** Rounding control: To nearest. */
2847	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2848	/** Rounding control: Down. */
2849	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2850	/** Rounding control: Up. */
2851	#define X86_FCW_RC_UP UINT16_C(0x0800)
2852	/** Rounding control: Towards zero. */
2853	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2854	/** Bits which should be zero, apparently. */
2855	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2856	/** @} */
2857
2858	/** @name SSE MXCSR
2859	* @{ */
2860	/** Exception Flag: Invalid operation. */
2861	#define X86_MXCSR_IE RT_BIT_32(0)
2862	/** Exception Flag: Denormalized operand. */
2863	#define X86_MXCSR_DE RT_BIT_32(1)
2864	/** Exception Flag: Zero divide. */
2865	#define X86_MXCSR_ZE RT_BIT_32(2)
2866	/** Exception Flag: Overflow. */
2867	#define X86_MXCSR_OE RT_BIT_32(3)
2868	/** Exception Flag: Underflow. */
2869	#define X86_MXCSR_UE RT_BIT_32(4)
2870	/** Exception Flag: Precision. */
2871	#define X86_MXCSR_PE RT_BIT_32(5)
2872
2873	/** Denormals are zero. */
2874	#define X86_MXCSR_DAZ RT_BIT_32(6)
2875
2876	/** Exception Mask: Invalid operation. */
2877	#define X86_MXCSR_IM RT_BIT_32(7)
2878	/** Exception Mask: Denormalized operand. */
2879	#define X86_MXCSR_DM RT_BIT_32(8)
2880	/** Exception Mask: Zero divide. */
2881	#define X86_MXCSR_ZM RT_BIT_32(9)
2882	/** Exception Mask: Overflow. */
2883	#define X86_MXCSR_OM RT_BIT_32(10)
2884	/** Exception Mask: Underflow. */
2885	#define X86_MXCSR_UM RT_BIT_32(11)
2886	/** Exception Mask: Precision. */
2887	#define X86_MXCSR_PM RT_BIT_32(12)
2888
2889	/** Rounding control mask. */
2890	#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
2891	/** Rounding control: To nearest. */
2892	#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
2893	/** Rounding control: Down. */
2894	#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
2895	/** Rounding control: Up. */
2896	#define X86_MXCSR_RC_UP UINT16_C(0x4000)
2897	/** Rounding control: Towards zero. */
2898	#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
2899
2900	/** Flush-to-zero for masked underflow. */
2901	#define X86_MXCSR_FZ RT_BIT_32(15)
2902
2903	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
2904	#define X86_MXCSR_MM RT_BIT_32(17)
2905	/** @} */
2906
2907	/**
2908	* XSAVE header.
2909	*/
2910	typedef struct X86XSAVEHDR
2911	{
2912	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
2913	uint64_t bmXState;
2914	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
2915	uint64_t bmXComp;
2916	/** Reserved for furture extensions, probably MBZ. */
2917	uint64_t au64Reserved[6];
2918	} X86XSAVEHDR;
2919	#ifndef VBOX_FOR_DTRACE_LIB
2920	AssertCompileSize(X86XSAVEHDR, 64);
2921	#endif
2922	/** Pointer to an XSAVE header. */
2923	typedef X86XSAVEHDR *PX86XSAVEHDR;
2924	/** Pointer to a const XSAVE header. */
2925	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
2926
2927
2928	/**
2929	* The high 128-bit YMM register state (XSAVE_C_YMM).
2930	* (The lower 128-bits being in X86FXSTATE.)
2931	*/
2932	typedef struct X86XSAVEYMMHI
2933	{
2934	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
2935	X86XMMREG aYmmHi[16];
2936	} X86XSAVEYMMHI;
2937	#ifndef VBOX_FOR_DTRACE_LIB
2938	AssertCompileSize(X86XSAVEYMMHI, 256);
2939	#endif
2940	/** Pointer to a high 128-bit YMM register state. */
2941	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
2942	/** Pointer to a const high 128-bit YMM register state. */
2943	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
2944
2945	/**
2946	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
2947	*/
2948	typedef struct X86XSAVEBNDREGS
2949	{
2950	/** Array of registers (BND0...BND3). */
2951	struct
2952	{
2953	/** Lower bound. */
2954	uint64_t uLowerBound;
2955	/** Upper bound. */
2956	uint64_t uUpperBound;
2957	} aRegs[4];
2958	} X86XSAVEBNDREGS;
2959	#ifndef VBOX_FOR_DTRACE_LIB
2960	AssertCompileSize(X86XSAVEBNDREGS, 64);
2961	#endif
2962	/** Pointer to a MPX bound register state. */
2963	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
2964	/** Pointer to a const MPX bound register state. */
2965	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
2966
2967	/**
2968	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
2969	*/
2970	typedef struct X86XSAVEBNDCFG
2971	{
2972	uint64_t fConfig;
2973	uint64_t fStatus;
2974	} X86XSAVEBNDCFG;
2975	#ifndef VBOX_FOR_DTRACE_LIB
2976	AssertCompileSize(X86XSAVEBNDCFG, 16);
2977	#endif
2978	/** Pointer to a MPX bound config and status register state. */
2979	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
2980	/** Pointer to a const MPX bound config and status register state. */
2981	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
2982
2983	/**
2984	* AVX-512 opmask state (XSAVE_C_OPMASK).
2985	*/
2986	typedef struct X86XSAVEOPMASK
2987	{
2988	/** The K0..K7 values. */
2989	uint64_t aKRegs[8];
2990	} X86XSAVEOPMASK;
2991	#ifndef VBOX_FOR_DTRACE_LIB
2992	AssertCompileSize(X86XSAVEOPMASK, 64);
2993	#endif
2994	/** Pointer to a AVX-512 opmask state. */
2995	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
2996	/** Pointer to a const AVX-512 opmask state. */
2997	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
2998
2999	/**
3000	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3001	*/
3002	typedef struct X86XSAVEZMMHI256
3003	{
3004	/** Upper 256-bits of ZMM0-15. */
3005	X86YMMREG aHi256Regs[16];
3006	} X86XSAVEZMMHI256;
3007	#ifndef VBOX_FOR_DTRACE_LIB
3008	AssertCompileSize(X86XSAVEZMMHI256, 512);
3009	#endif
3010	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3011	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3012	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3013	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3014
3015	/**
3016	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3017	*/
3018	typedef struct X86XSAVEZMM16HI
3019	{
3020	/** ZMM16 thru ZMM31. */
3021	X86ZMMREG aRegs[16];
3022	} X86XSAVEZMM16HI;
3023	#ifndef VBOX_FOR_DTRACE_LIB
3024	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3025	#endif
3026	/** Pointer to a state comprising ZMM16-32. */
3027	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3028	/** Pointer to a const state comprising ZMM16-32. */
3029	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3030
3031	/**
3032	* AMD Light weight profiling state (XSAVE_C_LWP).
3033	*
3034	* We probably won't play with this as AMD seems to be dropping from their "zen"
3035	* processor micro architecture.
3036	*/
3037	typedef struct X86XSAVELWP
3038	{
3039	/** Details when needed. */
3040	uint64_t auLater[128/8];
3041	} X86XSAVELWP;
3042	#ifndef VBOX_FOR_DTRACE_LIB
3043	AssertCompileSize(X86XSAVELWP, 128);
3044	#endif
3045
3046
3047	/**
3048	* x86 FPU/SSE/AVX/XXXX state.
3049	*
3050	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3051	* changes to this structure.
3052	*/
3053	typedef struct X86XSAVEAREA
3054	{
3055	/** The x87 and SSE region (or legacy region if you like). */
3056	X86FXSTATE x87;
3057	/** The XSAVE header. */
3058	X86XSAVEHDR Hdr;
3059	/** Beyond the header, there isn't really a fixed layout, but we can
3060	generally assume the YMM (AVX) register extensions are present and
3061	follows immediately. */
3062	union
3063	{
3064	/** This is a typical layout on intel CPUs (good for debuggers). */
3065	struct
3066	{
3067	X86XSAVEYMMHI YmmHi;
3068	X86XSAVEBNDREGS BndRegs;
3069	X86XSAVEBNDCFG BndCfg;
3070	uint8_t abFudgeToMatchDocs[0xB0];
3071	X86XSAVEOPMASK Opmask;
3072	X86XSAVEZMMHI256 ZmmHi256;
3073	X86XSAVEZMM16HI Zmm16Hi;
3074	} Intel;
3075
3076	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3077	struct
3078	{
3079	X86XSAVEYMMHI YmmHi;
3080	X86XSAVELWP Lwp;
3081	} AmdBd;
3082
3083	/** To enbling static deployments that have a reasonable chance of working for
3084	* the next 3-6 CPU generations without running short on space, we allocate a
3085	* lot of extra space here, making the structure a round 8KB in size. This
3086	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3087	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3088	uint8_t ab[8192 - 512 - 64];
3089	} u;
3090	} X86XSAVEAREA;
3091	#ifndef VBOX_FOR_DTRACE_LIB
3092	AssertCompileSize(X86XSAVEAREA, 8192);
3093	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3094	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3095	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3096	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3097	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3098	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3099	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3100	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3101	#endif
3102	/** Pointer to a XSAVE area. */
3103	typedef X86XSAVEAREA *PX86XSAVEAREA;
3104	/** Pointer to a const XSAVE area. */
3105	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3106
3107
3108	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3109	* @{ */
3110	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3111	#define XSAVE_C_X87_BIT 0
3112	/** Bit 0 - x87 - Legacy FPU state. */
3113	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3114	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3115	#define XSAVE_C_SSE_BIT 1
3116	/** Bit 1 - SSE - 128-bit SSE state. */
3117	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3118	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3119	#define XSAVE_C_YMM_BIT 2
3120	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3121	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3122	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3123	#define XSAVE_C_BNDREGS_BIT 3
3124	/** Bit 3 - BNDREGS - MPX bound register state. */
3125	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3126	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3127	#define XSAVE_C_BNDCSR_BIT 4
3128	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3129	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3130	/** Bit 5 - Opmask - opmask state (bit number). */
3131	#define XSAVE_C_OPMASK_BIT 5
3132	/** Bit 5 - Opmask - opmask state. */
3133	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3134	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3135	#define XSAVE_C_ZMM_HI256_BIT 6
3136	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3137	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3138	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3139	#define XSAVE_C_ZMM_16HI_BIT 7
3140	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3141	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3142	/** Bit 9 - PKRU - Protection-key state (bit number). */
3143	#define XSAVE_C_PKRU_BIT 9
3144	/** Bit 9 - PKRU - Protection-key state. */
3145	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3146	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3147	#define XSAVE_C_LWP_BIT 62
3148	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3149	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3150	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3151	#define XSAVE_C_X_BIT 63
3152	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3153	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3154	/** @} */
3155
3156
3157
3158	/** @name Selector Descriptor
3159	* @{
3160	*/
3161
3162	#ifndef VBOX_FOR_DTRACE_LIB
3163	/**
3164	* Descriptor attributes (as seen by VT-x).
3165	*/
3166	typedef struct X86DESCATTRBITS
3167	{
3168	/** 00 - Segment Type. */
3169	unsigned u4Type : 4;
3170	/** 04 - Descriptor Type. System(=0) or code/data selector */
3171	unsigned u1DescType : 1;
3172	/** 05 - Descriptor Privilege level. */
3173	unsigned u2Dpl : 2;
3174	/** 07 - Flags selector present(=1) or not. */
3175	unsigned u1Present : 1;
3176	/** 08 - Segment limit 16-19. */
3177	unsigned u4LimitHigh : 4;
3178	/** 0c - Available for system software. */
3179	unsigned u1Available : 1;
3180	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3181	unsigned u1Long : 1;
3182	/** 0e - This flags meaning depends on the segment type. Try make sense out
3183	* of the intel manual yourself. */
3184	unsigned u1DefBig : 1;
3185	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3186	* clear byte. */
3187	unsigned u1Granularity : 1;
3188	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3189	unsigned u1Unusable : 1;
3190	} X86DESCATTRBITS;
3191	#endif /* !VBOX_FOR_DTRACE_LIB */
3192
3193	/** @name X86DESCATTR masks
3194	* @{ */
3195	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3196	#define X86DESCATTR_DT UINT32_C(0x00000010)
3197	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3198	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3199	#define X86DESCATTR_P UINT32_C(0x00000080)
3200	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3201	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3202	#define X86DESCATTR_L UINT32_C(0x00002000)
3203	#define X86DESCATTR_D UINT32_C(0x00004000)
3204	#define X86DESCATTR_G UINT32_C(0x00008000)
3205	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3206	/** @} */
3207
3208	#pragma pack(1)
3209	typedef union X86DESCATTR
3210	{
3211	/** Unsigned integer view. */
3212	uint32_t u;
3213	#ifndef VBOX_FOR_DTRACE_LIB
3214	/** Normal view. */
3215	X86DESCATTRBITS n;
3216	#endif
3217	} X86DESCATTR;
3218	#pragma pack()
3219	/** Pointer to descriptor attributes. */
3220	typedef X86DESCATTR *PX86DESCATTR;
3221	/** Pointer to const descriptor attributes. */
3222	typedef const X86DESCATTR *PCX86DESCATTR;
3223
3224	#ifndef VBOX_FOR_DTRACE_LIB
3225
3226	/**
3227	* Generic descriptor table entry
3228	*/
3229	#pragma pack(1)
3230	typedef struct X86DESCGENERIC
3231	{
3232	/** 00 - Limit - Low word. */
3233	unsigned u16LimitLow : 16;
3234	/** 10 - Base address - low word.
3235	* Don't try set this to 24 because MSC is doing stupid things then. */
3236	unsigned u16BaseLow : 16;
3237	/** 20 - Base address - first 8 bits of high word. */
3238	unsigned u8BaseHigh1 : 8;
3239	/** 28 - Segment Type. */
3240	unsigned u4Type : 4;
3241	/** 2c - Descriptor Type. System(=0) or code/data selector */
3242	unsigned u1DescType : 1;
3243	/** 2d - Descriptor Privilege level. */
3244	unsigned u2Dpl : 2;
3245	/** 2f - Flags selector present(=1) or not. */
3246	unsigned u1Present : 1;
3247	/** 30 - Segment limit 16-19. */
3248	unsigned u4LimitHigh : 4;
3249	/** 34 - Available for system software. */
3250	unsigned u1Available : 1;
3251	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3252	unsigned u1Long : 1;
3253	/** 36 - This flags meaning depends on the segment type. Try make sense out
3254	* of the intel manual yourself. */
3255	unsigned u1DefBig : 1;
3256	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3257	* clear byte. */
3258	unsigned u1Granularity : 1;
3259	/** 38 - Base address - highest 8 bits. */
3260	unsigned u8BaseHigh2 : 8;
3261	} X86DESCGENERIC;
3262	#pragma pack()
3263	/** Pointer to a generic descriptor entry. */
3264	typedef X86DESCGENERIC *PX86DESCGENERIC;
3265	/** Pointer to a const generic descriptor entry. */
3266	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3267
3268	/** @name Bit offsets of X86DESCGENERIC members.
3269	* @{*/
3270	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3271	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3272	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3273	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3274	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3275	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3276	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3277	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3278	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3279	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3280	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3281	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3282	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3283	/** @} */
3284
3285
3286	/** @name LAR mask
3287	* @{ */
3288	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3289	#define X86LAR_F_DT UINT16_C( 0x1000)
3290	#define X86LAR_F_DPL UINT16_C( 0x6000)
3291	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3292	#define X86LAR_F_P UINT16_C( 0x8000)
3293	#define X86LAR_F_AVL UINT32_C(0x00100000)
3294	#define X86LAR_F_L UINT32_C(0x00200000)
3295	#define X86LAR_F_D UINT32_C(0x00400000)
3296	#define X86LAR_F_G UINT32_C(0x00800000)
3297	/** @} */
3298
3299
3300	/**
3301	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3302	*/
3303	typedef struct X86DESCGATE
3304	{
3305	/** 00 - Target code segment offset - Low word.
3306	* Ignored if task-gate. */
3307	unsigned u16OffsetLow : 16;
3308	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3309	* TSS selector if task-gate. */
3310	unsigned u16Sel : 16;
3311	/** 20 - Number of parameters for a call-gate.
3312	* Ignored if interrupt-, trap- or task-gate. */
3313	unsigned u5ParmCount : 5;
3314	/** 25 - Reserved / ignored. */
3315	unsigned u3Reserved : 3;
3316	/** 28 - Segment Type. */
3317	unsigned u4Type : 4;
3318	/** 2c - Descriptor Type (0 = system). */
3319	unsigned u1DescType : 1;
3320	/** 2d - Descriptor Privilege level. */
3321	unsigned u2Dpl : 2;
3322	/** 2f - Flags selector present(=1) or not. */
3323	unsigned u1Present : 1;
3324	/** 30 - Target code segment offset - High word.
3325	* Ignored if task-gate. */
3326	unsigned u16OffsetHigh : 16;
3327	} X86DESCGATE;
3328	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3329	typedef X86DESCGATE *PX86DESCGATE;
3330	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3331	typedef const X86DESCGATE *PCX86DESCGATE;
3332
3333	#endif /* VBOX_FOR_DTRACE_LIB */
3334
3335	/**
3336	* Descriptor table entry.
3337	*/
3338	#pragma pack(1)
3339	typedef union X86DESC
3340	{
3341	#ifndef VBOX_FOR_DTRACE_LIB
3342	/** Generic descriptor view. */
3343	X86DESCGENERIC Gen;
3344	/** Gate descriptor view. */
3345	X86DESCGATE Gate;
3346	#endif
3347
3348	/** 8 bit unsigned integer view. */
3349	uint8_t au8[8];
3350	/** 16 bit unsigned integer view. */
3351	uint16_t au16[4];
3352	/** 32 bit unsigned integer view. */
3353	uint32_t au32[2];
3354	/** 64 bit unsigned integer view. */
3355	uint64_t au64[1];
3356	/** Unsigned integer view. */
3357	uint64_t u;
3358	} X86DESC;
3359	#ifndef VBOX_FOR_DTRACE_LIB
3360	AssertCompileSize(X86DESC, 8);
3361	#endif
3362	#pragma pack()
3363	/** Pointer to descriptor table entry. */
3364	typedef X86DESC *PX86DESC;
3365	/** Pointer to const descriptor table entry. */
3366	typedef const X86DESC *PCX86DESC;
3367
3368	/** @def X86DESC_BASE
3369	* Return the base address of a descriptor.
3370	*/
3371	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3372	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3373	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3374	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3375
3376	/** @def X86DESC_LIMIT
3377	* Return the limit of a descriptor.
3378	*/
3379	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3380	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3381	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3382
3383	/** @def X86DESC_LIMIT_G
3384	* Return the limit of a descriptor with the granularity bit taken into account.
3385	* @returns Selector limit (uint32_t).
3386	* @param a_pDesc Pointer to the descriptor.
3387	*/
3388	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3389	( (a_pDesc)->Gen.u1Granularity \
3390	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3391	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3392	)
3393
3394	/** @def X86DESC_GET_HID_ATTR
3395	* Get the descriptor attributes for the hidden register.
3396	*/
3397	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3398	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3399
3400	#ifndef VBOX_FOR_DTRACE_LIB
3401
3402	/**
3403	* 64 bits generic descriptor table entry
3404	* Note: most of these bits have no meaning in long mode.
3405	*/
3406	#pragma pack(1)
3407	typedef struct X86DESC64GENERIC
3408	{
3409	/** Limit - Low word - IGNORED. */
3410	uint32_t u16LimitLow : 16;
3411	/** Base address - low word. - IGNORED
3412	* Don't try set this to 24 because MSC is doing stupid things then. */
3413	uint32_t u16BaseLow : 16;
3414	/** Base address - first 8 bits of high word. - IGNORED */
3415	uint32_t u8BaseHigh1 : 8;
3416	/** Segment Type. */
3417	uint32_t u4Type : 4;
3418	/** Descriptor Type. System(=0) or code/data selector */
3419	uint32_t u1DescType : 1;
3420	/** Descriptor Privilege level. */
3421	uint32_t u2Dpl : 2;
3422	/** Flags selector present(=1) or not. */
3423	uint32_t u1Present : 1;
3424	/** Segment limit 16-19. - IGNORED */
3425	uint32_t u4LimitHigh : 4;
3426	/** Available for system software. - IGNORED */
3427	uint32_t u1Available : 1;
3428	/** Long mode flag. */
3429	uint32_t u1Long : 1;
3430	/** This flags meaning depends on the segment type. Try make sense out
3431	* of the intel manual yourself. */
3432	uint32_t u1DefBig : 1;
3433	/** Granularity of the limit. If set 4KB granularity is used, if
3434	* clear byte. - IGNORED */
3435	uint32_t u1Granularity : 1;
3436	/** Base address - highest 8 bits. - IGNORED */
3437	uint32_t u8BaseHigh2 : 8;
3438	/** Base address - bits 63-32. */
3439	uint32_t u32BaseHigh3 : 32;
3440	uint32_t u8Reserved : 8;
3441	uint32_t u5Zeros : 5;
3442	uint32_t u19Reserved : 19;
3443	} X86DESC64GENERIC;
3444	#pragma pack()
3445	/** Pointer to a generic descriptor entry. */
3446	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3447	/** Pointer to a const generic descriptor entry. */
3448	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3449
3450	/**
3451	* System descriptor table entry (64 bits)
3452	*
3453	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3454	*/
3455	#pragma pack(1)
3456	typedef struct X86DESC64SYSTEM
3457	{
3458	/** Limit - Low word. */
3459	uint32_t u16LimitLow : 16;
3460	/** Base address - low word.
3461	* Don't try set this to 24 because MSC is doing stupid things then. */
3462	uint32_t u16BaseLow : 16;
3463	/** Base address - first 8 bits of high word. */
3464	uint32_t u8BaseHigh1 : 8;
3465	/** Segment Type. */
3466	uint32_t u4Type : 4;
3467	/** Descriptor Type. System(=0) or code/data selector */
3468	uint32_t u1DescType : 1;
3469	/** Descriptor Privilege level. */
3470	uint32_t u2Dpl : 2;
3471	/** Flags selector present(=1) or not. */
3472	uint32_t u1Present : 1;
3473	/** Segment limit 16-19. */
3474	uint32_t u4LimitHigh : 4;
3475	/** Available for system software. */
3476	uint32_t u1Available : 1;
3477	/** Reserved - 0. */
3478	uint32_t u1Reserved : 1;
3479	/** This flags meaning depends on the segment type. Try make sense out
3480	* of the intel manual yourself. */
3481	uint32_t u1DefBig : 1;
3482	/** Granularity of the limit. If set 4KB granularity is used, if
3483	* clear byte. */
3484	uint32_t u1Granularity : 1;
3485	/** Base address - bits 31-24. */
3486	uint32_t u8BaseHigh2 : 8;
3487	/** Base address - bits 63-32. */
3488	uint32_t u32BaseHigh3 : 32;
3489	uint32_t u8Reserved : 8;
3490	uint32_t u5Zeros : 5;
3491	uint32_t u19Reserved : 19;
3492	} X86DESC64SYSTEM;
3493	#pragma pack()
3494	/** Pointer to a system descriptor entry. */
3495	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3496	/** Pointer to a const system descriptor entry. */
3497	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3498
3499	/**
3500	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3501	*/
3502	typedef struct X86DESC64GATE
3503	{
3504	/** Target code segment offset - Low word. */
3505	uint32_t u16OffsetLow : 16;
3506	/** Target code segment selector. */
3507	uint32_t u16Sel : 16;
3508	/** Interrupt stack table for interrupt- and trap-gates.
3509	* Ignored by call-gates. */
3510	uint32_t u3IST : 3;
3511	/** Reserved / ignored. */
3512	uint32_t u5Reserved : 5;
3513	/** Segment Type. */
3514	uint32_t u4Type : 4;
3515	/** Descriptor Type (0 = system). */
3516	uint32_t u1DescType : 1;
3517	/** Descriptor Privilege level. */
3518	uint32_t u2Dpl : 2;
3519	/** Flags selector present(=1) or not. */
3520	uint32_t u1Present : 1;
3521	/** Target code segment offset - High word.
3522	* Ignored if task-gate. */
3523	uint32_t u16OffsetHigh : 16;
3524	/** Target code segment offset - Top dword.
3525	* Ignored if task-gate. */
3526	uint32_t u32OffsetTop : 32;
3527	/** Reserved / ignored / must be zero.
3528	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3529	uint32_t u32Reserved : 32;
3530	} X86DESC64GATE;
3531	AssertCompileSize(X86DESC64GATE, 16);
3532	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3533	typedef X86DESC64GATE *PX86DESC64GATE;
3534	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3535	typedef const X86DESC64GATE *PCX86DESC64GATE;
3536
3537	#endif /* VBOX_FOR_DTRACE_LIB */
3538
3539	/**
3540	* Descriptor table entry.
3541	*/
3542	#pragma pack(1)
3543	typedef union X86DESC64
3544	{
3545	#ifndef VBOX_FOR_DTRACE_LIB
3546	/** Generic descriptor view. */
3547	X86DESC64GENERIC Gen;
3548	/** System descriptor view. */
3549	X86DESC64SYSTEM System;
3550	/** Gate descriptor view. */
3551	X86DESC64GATE Gate;
3552	#endif
3553
3554	/** 8 bit unsigned integer view. */
3555	uint8_t au8[16];
3556	/** 16 bit unsigned integer view. */
3557	uint16_t au16[8];
3558	/** 32 bit unsigned integer view. */
3559	uint32_t au32[4];
3560	/** 64 bit unsigned integer view. */
3561	uint64_t au64[2];
3562	} X86DESC64;
3563	#ifndef VBOX_FOR_DTRACE_LIB
3564	AssertCompileSize(X86DESC64, 16);
3565	#endif
3566	#pragma pack()
3567	/** Pointer to descriptor table entry. */
3568	typedef X86DESC64 *PX86DESC64;
3569	/** Pointer to const descriptor table entry. */
3570	typedef const X86DESC64 *PCX86DESC64;
3571
3572	/** @def X86DESC64_BASE
3573	* Return the base of a 64-bit descriptor.
3574	*/
3575	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3576	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3577	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3578	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3579	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3580
3581
3582
3583	/** @name Host system descriptor table entry - Use with care!
3584	* @{ */
3585	/** Host system descriptor table entry. */
3586	#if HC_ARCH_BITS == 64
3587	typedef X86DESC64 X86DESCHC;
3588	#else
3589	typedef X86DESC X86DESCHC;
3590	#endif
3591	/** Pointer to a host system descriptor table entry. */
3592	#if HC_ARCH_BITS == 64
3593	typedef PX86DESC64 PX86DESCHC;
3594	#else
3595	typedef PX86DESC PX86DESCHC;
3596	#endif
3597	/** Pointer to a const host system descriptor table entry. */
3598	#if HC_ARCH_BITS == 64
3599	typedef PCX86DESC64 PCX86DESCHC;
3600	#else
3601	typedef PCX86DESC PCX86DESCHC;
3602	#endif
3603	/** @} */
3604
3605
3606	/** @name Selector Descriptor Types.
3607	* @{
3608	*/
3609
3610	/** @name Non-System Selector Types.
3611	* @{ */
3612	/** Code(=set)/Data(=clear) bit. */
3613	#define X86_SEL_TYPE_CODE 8
3614	/** Memory(=set)/System(=clear) bit. */
3615	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3616	/** Accessed bit. */
3617	#define X86_SEL_TYPE_ACCESSED 1
3618	/** Expand down bit (for data selectors only). */
3619	#define X86_SEL_TYPE_DOWN 4
3620	/** Conforming bit (for code selectors only). */
3621	#define X86_SEL_TYPE_CONF 4
3622	/** Write bit (for data selectors only). */
3623	#define X86_SEL_TYPE_WRITE 2
3624	/** Read bit (for code selectors only). */
3625	#define X86_SEL_TYPE_READ 2
3626	/** The bit number of the code segment read bit (relative to u4Type). */
3627	#define X86_SEL_TYPE_READ_BIT 1
3628
3629	/** Read only selector type. */
3630	#define X86_SEL_TYPE_RO 0
3631	/** Accessed read only selector type. */
3632	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3633	/** Read write selector type. */
3634	#define X86_SEL_TYPE_RW 2
3635	/** Accessed read write selector type. */
3636	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3637	/** Expand down read only selector type. */
3638	#define X86_SEL_TYPE_RO_DOWN 4
3639	/** Accessed expand down read only selector type. */
3640	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3641	/** Expand down read write selector type. */
3642	#define X86_SEL_TYPE_RW_DOWN 6
3643	/** Accessed expand down read write selector type. */
3644	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3645	/** Execute only selector type. */
3646	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3647	/** Accessed execute only selector type. */
3648	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3649	/** Execute and read selector type. */
3650	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3651	/** Accessed execute and read selector type. */
3652	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3653	/** Conforming execute only selector type. */
3654	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3655	/** Accessed Conforming execute only selector type. */
3656	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3657	/** Conforming execute and write selector type. */
3658	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3659	/** Accessed Conforming execute and write selector type. */
3660	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3661	/** @} */
3662
3663
3664	/** @name System Selector Types.
3665	* @{ */
3666	/** The TSS busy bit mask. */
3667	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3668
3669	/** Undefined system selector type. */
3670	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3671	/** 286 TSS selector. */
3672	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3673	/** LDT selector. */
3674	#define X86_SEL_TYPE_SYS_LDT 2
3675	/** 286 TSS selector - Busy. */
3676	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3677	/** 286 Callgate selector. */
3678	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3679	/** Taskgate selector. */
3680	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3681	/** 286 Interrupt gate selector. */
3682	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3683	/** 286 Trapgate selector. */
3684	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3685	/** Undefined system selector. */
3686	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3687	/** 386 TSS selector. */
3688	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3689	/** Undefined system selector. */
3690	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3691	/** 386 TSS selector - Busy. */
3692	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3693	/** 386 Callgate selector. */
3694	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3695	/** Undefined system selector. */
3696	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3697	/** 386 Interruptgate selector. */
3698	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3699	/** 386 Trapgate selector. */
3700	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3701	/** @} */
3702
3703	/** @name AMD64 System Selector Types.
3704	* @{ */
3705	/** LDT selector. */
3706	#define AMD64_SEL_TYPE_SYS_LDT 2
3707	/** TSS selector - Busy. */
3708	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3709	/** TSS selector - Busy. */
3710	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3711	/** Callgate selector. */
3712	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3713	/** Interruptgate selector. */
3714	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3715	/** Trapgate selector. */
3716	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3717	/** @} */
3718
3719	/** @} */
3720
3721
3722	/** @name Descriptor Table Entry Flag Masks.
3723	* These are for the 2nd 32-bit word of a descriptor.
3724	* @{ */
3725	/** Bits 8-11 - TYPE - Descriptor type mask. */
3726	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3727	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3728	#define X86_DESC_S RT_BIT_32(12)
3729	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3730	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
3731	/** Bit 15 - P - Present. */
3732	#define X86_DESC_P RT_BIT_32(15)
3733	/** Bit 20 - AVL - Available for system software. */
3734	#define X86_DESC_AVL RT_BIT_32(20)
3735	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3736	#define X86_DESC_DB RT_BIT_32(22)
3737	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3738	* used, if clear byte. */
3739	#define X86_DESC_G RT_BIT_32(23)
3740	/** @} */
3741
3742	/** @} */
3743
3744
3745	/** @name Task Segments.
3746	* @{
3747	*/
3748
3749	/**
3750	* The minimum TSS descriptor limit for 286 tasks.
3751	*/
3752	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3753
3754	/**
3755	* The minimum TSS descriptor segment limit for 386 tasks.
3756	*/
3757	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3758
3759	/**
3760	* 16-bit Task Segment (TSS).
3761	*/
3762	#pragma pack(1)
3763	typedef struct X86TSS16
3764	{
3765	/** Back link to previous task. (static) */
3766	RTSEL selPrev;
3767	/** Ring-0 stack pointer. (static) */
3768	uint16_t sp0;
3769	/** Ring-0 stack segment. (static) */
3770	RTSEL ss0;
3771	/** Ring-1 stack pointer. (static) */
3772	uint16_t sp1;
3773	/** Ring-1 stack segment. (static) */
3774	RTSEL ss1;
3775	/** Ring-2 stack pointer. (static) */
3776	uint16_t sp2;
3777	/** Ring-2 stack segment. (static) */
3778	RTSEL ss2;
3779	/** IP before task switch. */
3780	uint16_t ip;
3781	/** FLAGS before task switch. */
3782	uint16_t flags;
3783	/** AX before task switch. */
3784	uint16_t ax;
3785	/** CX before task switch. */
3786	uint16_t cx;
3787	/** DX before task switch. */
3788	uint16_t dx;
3789	/** BX before task switch. */
3790	uint16_t bx;
3791	/** SP before task switch. */
3792	uint16_t sp;
3793	/** BP before task switch. */
3794	uint16_t bp;
3795	/** SI before task switch. */
3796	uint16_t si;
3797	/** DI before task switch. */
3798	uint16_t di;
3799	/** ES before task switch. */
3800	RTSEL es;
3801	/** CS before task switch. */
3802	RTSEL cs;
3803	/** SS before task switch. */
3804	RTSEL ss;
3805	/** DS before task switch. */
3806	RTSEL ds;
3807	/** LDTR before task switch. */
3808	RTSEL selLdt;
3809	} X86TSS16;
3810	#ifndef VBOX_FOR_DTRACE_LIB
3811	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3812	#endif
3813	#pragma pack()
3814	/** Pointer to a 16-bit task segment. */
3815	typedef X86TSS16 *PX86TSS16;
3816	/** Pointer to a const 16-bit task segment. */
3817	typedef const X86TSS16 *PCX86TSS16;
3818
3819
3820	/**
3821	* 32-bit Task Segment (TSS).
3822	*/
3823	#pragma pack(1)
3824	typedef struct X86TSS32
3825	{
3826	/** Back link to previous task. (static) */
3827	RTSEL selPrev;
3828	uint16_t padding1;
3829	/** Ring-0 stack pointer. (static) */
3830	uint32_t esp0;
3831	/** Ring-0 stack segment. (static) */
3832	RTSEL ss0;
3833	uint16_t padding_ss0;
3834	/** Ring-1 stack pointer. (static) */
3835	uint32_t esp1;
3836	/** Ring-1 stack segment. (static) */
3837	RTSEL ss1;
3838	uint16_t padding_ss1;
3839	/** Ring-2 stack pointer. (static) */
3840	uint32_t esp2;
3841	/** Ring-2 stack segment. (static) */
3842	RTSEL ss2;
3843	uint16_t padding_ss2;
3844	/** Page directory for the task. (static) */
3845	uint32_t cr3;
3846	/** EIP before task switch. */
3847	uint32_t eip;
3848	/** EFLAGS before task switch. */
3849	uint32_t eflags;
3850	/** EAX before task switch. */
3851	uint32_t eax;
3852	/** ECX before task switch. */
3853	uint32_t ecx;
3854	/** EDX before task switch. */
3855	uint32_t edx;
3856	/** EBX before task switch. */
3857	uint32_t ebx;
3858	/** ESP before task switch. */
3859	uint32_t esp;
3860	/** EBP before task switch. */
3861	uint32_t ebp;
3862	/** ESI before task switch. */
3863	uint32_t esi;
3864	/** EDI before task switch. */
3865	uint32_t edi;
3866	/** ES before task switch. */
3867	RTSEL es;
3868	uint16_t padding_es;
3869	/** CS before task switch. */
3870	RTSEL cs;
3871	uint16_t padding_cs;
3872	/** SS before task switch. */
3873	RTSEL ss;
3874	uint16_t padding_ss;
3875	/** DS before task switch. */
3876	RTSEL ds;
3877	uint16_t padding_ds;
3878	/** FS before task switch. */
3879	RTSEL fs;
3880	uint16_t padding_fs;
3881	/** GS before task switch. */
3882	RTSEL gs;
3883	uint16_t padding_gs;
3884	/** LDTR before task switch. */
3885	RTSEL selLdt;
3886	uint16_t padding_ldt;
3887	/** Debug trap flag */
3888	uint16_t fDebugTrap;
3889	/** Offset relative to the TSS of the start of the I/O Bitmap
3890	* and the end of the interrupt redirection bitmap. */
3891	uint16_t offIoBitmap;
3892	} X86TSS32;
3893	#pragma pack()
3894	/** Pointer to task segment. */
3895	typedef X86TSS32 *PX86TSS32;
3896	/** Pointer to const task segment. */
3897	typedef const X86TSS32 *PCX86TSS32;
3898	#ifndef VBOX_FOR_DTRACE_LIB
3899	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3900	AssertCompileMemberOffset(X86TSS32, cr3, 28);
3901	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
3902	#endif
3903
3904	/**
3905	* 64-bit Task segment.
3906	*/
3907	#pragma pack(1)
3908	typedef struct X86TSS64
3909	{
3910	/** Reserved. */
3911	uint32_t u32Reserved;
3912	/** Ring-0 stack pointer. (static) */
3913	uint64_t rsp0;
3914	/** Ring-1 stack pointer. (static) */
3915	uint64_t rsp1;
3916	/** Ring-2 stack pointer. (static) */
3917	uint64_t rsp2;
3918	/** Reserved. */
3919	uint32_t u32Reserved2[2];
3920	/* IST */
3921	uint64_t ist1;
3922	uint64_t ist2;
3923	uint64_t ist3;
3924	uint64_t ist4;
3925	uint64_t ist5;
3926	uint64_t ist6;
3927	uint64_t ist7;
3928	/* Reserved. */
3929	uint16_t u16Reserved[5];
3930	/** Offset relative to the TSS of the start of the I/O Bitmap
3931	* and the end of the interrupt redirection bitmap. */
3932	uint16_t offIoBitmap;
3933	} X86TSS64;
3934	#pragma pack()
3935	/** Pointer to a 64-bit task segment. */
3936	typedef X86TSS64 *PX86TSS64;
3937	/** Pointer to a const 64-bit task segment. */
3938	typedef const X86TSS64 *PCX86TSS64;
3939	#ifndef VBOX_FOR_DTRACE_LIB
3940	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3941	#endif
3942
3943	/** @} */
3944
3945
3946	/** @name Selectors.
3947	* @{
3948	*/
3949
3950	/**
3951	* The shift used to convert a selector from and to index an index (C).
3952	*/
3953	#define X86_SEL_SHIFT 3
3954
3955	/**
3956	* The mask used to mask off the table indicator and RPL of an selector.
3957	*/
3958	#define X86_SEL_MASK 0xfff8U
3959
3960	/**
3961	* The mask used to mask off the RPL of an selector.
3962	* This is suitable for checking for NULL selectors.
3963	*/
3964	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3965
3966	/**
3967	* The bit indicating that a selector is in the LDT and not in the GDT.
3968	*/
3969	#define X86_SEL_LDT 0x0004U
3970
3971	/**
3972	* The bit mask for getting the RPL of a selector.
3973	*/
3974	#define X86_SEL_RPL 0x0003U
3975
3976	/**
3977	* The mask covering both RPL and LDT.
3978	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3979	* checks.
3980	*/
3981	#define X86_SEL_RPL_LDT 0x0007U
3982
3983	/** @} */
3984
3985
3986	/**
3987	* x86 Exceptions/Faults/Traps.
3988	*/
3989	typedef enum X86XCPT
3990	{
3991	/** \#DE - Divide error. */
3992	X86_XCPT_DE = 0x00,
3993	/** \#DB - Debug event (single step, DRx, ..) */
3994	X86_XCPT_DB = 0x01,
3995	/** NMI - Non-Maskable Interrupt */
3996	X86_XCPT_NMI = 0x02,
3997	/** \#BP - Breakpoint (INT3). */
3998	X86_XCPT_BP = 0x03,
3999	/** \#OF - Overflow (INTO). */
4000	X86_XCPT_OF = 0x04,
4001	/** \#BR - Bound range exceeded (BOUND). */
4002	X86_XCPT_BR = 0x05,
4003	/** \#UD - Undefined opcode. */
4004	X86_XCPT_UD = 0x06,
4005	/** \#NM - Device not available (math coprocessor device). */
4006	X86_XCPT_NM = 0x07,
4007	/** \#DF - Double fault. */
4008	X86_XCPT_DF = 0x08,
4009	/** ??? - Coprocessor segment overrun (obsolete). */
4010	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4011	/** \#TS - Taskswitch (TSS). */
4012	X86_XCPT_TS = 0x0a,
4013	/** \#NP - Segment no present. */
4014	X86_XCPT_NP = 0x0b,
4015	/** \#SS - Stack segment fault. */
4016	X86_XCPT_SS = 0x0c,
4017	/** \#GP - General protection fault. */
4018	X86_XCPT_GP = 0x0d,
4019	/** \#PF - Page fault. */
4020	X86_XCPT_PF = 0x0e,
4021	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4022	/** \#MF - Math fault (FPU). */
4023	X86_XCPT_MF = 0x10,
4024	/** \#AC - Alignment check. */
4025	X86_XCPT_AC = 0x11,
4026	/** \#MC - Machine check. */
4027	X86_XCPT_MC = 0x12,
4028	/** \#XF - SIMD Floating-Pointer Exception. */
4029	X86_XCPT_XF = 0x13,
4030	/** \#VE - Virtualization Exception. */
4031	X86_XCPT_VE = 0x14,
4032	/** \#SX - Security Exception. */
4033	X86_XCPT_SX = 0x1e
4034	} X86XCPT;
4035	/** Pointer to a x86 exception code. */
4036	typedef X86XCPT *PX86XCPT;
4037	/** Pointer to a const x86 exception code. */
4038	typedef const X86XCPT *PCX86XCPT;
4039	/** The last valid (currently reserved) exception value. */
4040	#define X86_XCPT_LAST 0x1f
4041
4042
4043	/** @name Trap Error Codes
4044	* @{
4045	*/
4046	/** External indicator. */
4047	#define X86_TRAP_ERR_EXTERNAL 1
4048	/** IDT indicator. */
4049	#define X86_TRAP_ERR_IDT 2
4050	/** Descriptor table indicator - If set LDT, if clear GDT. */
4051	#define X86_TRAP_ERR_TI 4
4052	/** Mask for getting the selector. */
4053	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4054	/** Shift for getting the selector table index (C type index). */
4055	#define X86_TRAP_ERR_SEL_SHIFT 3
4056	/** @} */
4057
4058
4059	/** @name \#PF Trap Error Codes
4060	* @{
4061	*/
4062	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4063	#define X86_TRAP_PF_P RT_BIT_32(0)
4064	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4065	#define X86_TRAP_PF_RW RT_BIT_32(1)
4066	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4067	#define X86_TRAP_PF_US RT_BIT_32(2)
4068	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4069	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4070	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4071	#define X86_TRAP_PF_ID RT_BIT_32(4)
4072	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4073	#define X86_TRAP_PF_PK RT_BIT_32(5)
4074	/** @} */
4075
4076	#pragma pack(1)
4077	/**
4078	* 16-bit IDTR.
4079	*/
4080	typedef struct X86IDTR16
4081	{
4082	/** Offset. */
4083	uint16_t offSel;
4084	/** Selector. */
4085	uint16_t uSel;
4086	} X86IDTR16, *PX86IDTR16;
4087	#pragma pack()
4088
4089	#pragma pack(1)
4090	/**
4091	* 32-bit IDTR/GDTR.
4092	*/
4093	typedef struct X86XDTR32
4094	{
4095	/** Size of the descriptor table. */
4096	uint16_t cb;
4097	/** Address of the descriptor table. */
4098	#ifndef VBOX_FOR_DTRACE_LIB
4099	uint32_t uAddr;
4100	#else
4101	uint16_t au16Addr[2];
4102	#endif
4103	} X86XDTR32, *PX86XDTR32;
4104	#pragma pack()
4105
4106	#pragma pack(1)
4107	/**
4108	* 64-bit IDTR/GDTR.
4109	*/
4110	typedef struct X86XDTR64
4111	{
4112	/** Size of the descriptor table. */
4113	uint16_t cb;
4114	/** Address of the descriptor table. */
4115	#ifndef VBOX_FOR_DTRACE_LIB
4116	uint64_t uAddr;
4117	#else
4118	uint16_t au16Addr[4];
4119	#endif
4120	} X86XDTR64, *PX86XDTR64;
4121	#pragma pack()
4122
4123
4124	/** @name ModR/M
4125	* @{ */
4126	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4127	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4128	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4129	#define X86_MODRM_REG_SHIFT 3
4130	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4131	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4132	#define X86_MODRM_MOD_SHIFT 6
4133	#ifndef VBOX_FOR_DTRACE_LIB
4134	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4135	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4136	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4137	/** @def X86_MODRM_MAKE
4138	* @param a_Mod The mod value (0..3).
4139	* @param a_Reg The register value (0..7).
4140	* @param a_RegMem The register or memory value (0..7). */
4141	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4142	#endif
4143	/** @} */
4144
4145	/** @name SIB
4146	* @{ */
4147	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4148	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4149	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4150	#define X86_SIB_INDEX_SHIFT 3
4151	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4152	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4153	#define X86_SIB_SCALE_SHIFT 6
4154	#ifndef VBOX_FOR_DTRACE_LIB
4155	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4156	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4157	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4158	#endif
4159	/** @} */
4160
4161	/** @name General register indexes
4162	* @{ */
4163	#define X86_GREG_xAX 0
4164	#define X86_GREG_xCX 1
4165	#define X86_GREG_xDX 2
4166	#define X86_GREG_xBX 3
4167	#define X86_GREG_xSP 4
4168	#define X86_GREG_xBP 5
4169	#define X86_GREG_xSI 6
4170	#define X86_GREG_xDI 7
4171	#define X86_GREG_x8 8
4172	#define X86_GREG_x9 9
4173	#define X86_GREG_x10 10
4174	#define X86_GREG_x11 11
4175	#define X86_GREG_x12 12
4176	#define X86_GREG_x13 13
4177	#define X86_GREG_x14 14
4178	#define X86_GREG_x15 15
4179	/** @} */
4180
4181	/** @name X86_SREG_XXX - Segment register indexes.
4182	* @{ */
4183	#define X86_SREG_ES 0
4184	#define X86_SREG_CS 1
4185	#define X86_SREG_SS 2
4186	#define X86_SREG_DS 3
4187	#define X86_SREG_FS 4
4188	#define X86_SREG_GS 5
4189	/** @} */
4190	/** Segment register count. */
4191	#define X86_SREG_COUNT 6
4192
4193
4194	/** @name X86_OP_XXX - Prefixes
4195	* @{ */
4196	#define X86_OP_PRF_CS UINT8_C(0x2e)
4197	#define X86_OP_PRF_SS UINT8_C(0x36)
4198	#define X86_OP_PRF_DS UINT8_C(0x3e)
4199	#define X86_OP_PRF_ES UINT8_C(0x26)
4200	#define X86_OP_PRF_FS UINT8_C(0x64)
4201	#define X86_OP_PRF_GS UINT8_C(0x65)
4202	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4203	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4204	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4205	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4206	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4207	#define X86_OP_REX_B UINT8_C(0x41)
4208	#define X86_OP_REX_X UINT8_C(0x42)
4209	#define X86_OP_REX_R UINT8_C(0x44)
4210	#define X86_OP_REX_W UINT8_C(0x48)
4211	/** @} */
4212
4213
4214	/** @} */
4215
4216	#endif
4217

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/iprt/x86.h@ 66601

Download in other formats: