x86.h@ 69692

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2017 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT_32(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT_32(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT_32(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT_32(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT_32(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT_32(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT_32(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT_32(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT_32(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT_32(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT_32(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT_32(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT_32(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT_32(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT_32(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT_32(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT_32(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** Bits restored by popf */
215	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
216	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
217	/** The status bits commonly updated by arithmetic instructions. */
218	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
219	/** @} */
220
221
222	/** CPUID Feature information - ECX.
223	* CPUID query with EAX=1.
224	*/
225	#ifndef VBOX_FOR_DTRACE_LIB
226	typedef struct X86CPUIDFEATECX
227	{
228	/** Bit 0 - SSE3 - Supports SSE3 or not. */
229	unsigned u1SSE3 : 1;
230	/** Bit 1 - PCLMULQDQ. */
231	unsigned u1PCLMULQDQ : 1;
232	/** Bit 2 - DS Area 64-bit layout. */
233	unsigned u1DTE64 : 1;
234	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235	unsigned u1Monitor : 1;
236	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237	unsigned u1CPLDS : 1;
238	/** Bit 5 - VMX - Virtual Machine Technology. */
239	unsigned u1VMX : 1;
240	/** Bit 6 - SMX: Safer Mode Extensions. */
241	unsigned u1SMX : 1;
242	/** Bit 7 - EST - Enh. SpeedStep Tech. */
243	unsigned u1EST : 1;
244	/** Bit 8 - TM2 - Terminal Monitor 2. */
245	unsigned u1TM2 : 1;
246	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247	unsigned u1SSSE3 : 1;
248	/** Bit 10 - CNTX-ID - L1 Context ID. */
249	unsigned u1CNTXID : 1;
250	/** Bit 11 - Reserved. */
251	unsigned u1Reserved1 : 1;
252	/** Bit 12 - FMA. */
253	unsigned u1FMA : 1;
254	/** Bit 13 - CX16 - CMPXCHG16B. */
255	unsigned u1CX16 : 1;
256	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257	unsigned u1TPRUpdate : 1;
258	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259	unsigned u1PDCM : 1;
260	/** Bit 16 - Reserved. */
261	unsigned u1Reserved2 : 1;
262	/** Bit 17 - PCID - Process-context identifiers. */
263	unsigned u1PCID : 1;
264	/** Bit 18 - Direct Cache Access. */
265	unsigned u1DCA : 1;
266	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267	unsigned u1SSE4_1 : 1;
268	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269	unsigned u1SSE4_2 : 1;
270	/** Bit 21 - x2APIC. */
271	unsigned u1x2APIC : 1;
272	/** Bit 22 - MOVBE - Supports MOVBE. */
273	unsigned u1MOVBE : 1;
274	/** Bit 23 - POPCNT - Supports POPCNT. */
275	unsigned u1POPCNT : 1;
276	/** Bit 24 - TSC-Deadline. */
277	unsigned u1TSCDEADLINE : 1;
278	/** Bit 25 - AES. */
279	unsigned u1AES : 1;
280	/** Bit 26 - XSAVE - Supports XSAVE. */
281	unsigned u1XSAVE : 1;
282	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283	unsigned u1OSXSAVE : 1;
284	/** Bit 28 - AVX - Supports AVX instruction extensions. */
285	unsigned u1AVX : 1;
286	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287	unsigned u1F16C : 1;
288	/** Bit 30 - RDRAND - Supports RDRAND. */
289	unsigned u1RDRAND : 1;
290	/** Bit 31 - Hypervisor present (we're a guest). */
291	unsigned u1HVP : 1;
292	} X86CPUIDFEATECX;
293	#else /* VBOX_FOR_DTRACE_LIB */
294	typedef uint32_t X86CPUIDFEATECX;
295	#endif /* VBOX_FOR_DTRACE_LIB */
296	/** Pointer to CPUID Feature Information - ECX. */
297	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298	/** Pointer to const CPUID Feature Information - ECX. */
299	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302	/** CPUID Feature Information - EDX.
303	* CPUID query with EAX=1.
304	*/
305	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306	typedef struct X86CPUIDFEATEDX
307	{
308	/** Bit 0 - FPU - x87 FPU on Chip. */
309	unsigned u1FPU : 1;
310	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311	unsigned u1VME : 1;
312	/** Bit 2 - DE - Debugging extensions. */
313	unsigned u1DE : 1;
314	/** Bit 3 - PSE - Page Size Extension. */
315	unsigned u1PSE : 1;
316	/** Bit 4 - TSC - Time Stamp Counter. */
317	unsigned u1TSC : 1;
318	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319	unsigned u1MSR : 1;
320	/** Bit 6 - PAE - Physical Address Extension. */
321	unsigned u1PAE : 1;
322	/** Bit 7 - MCE - Machine Check Exception. */
323	unsigned u1MCE : 1;
324	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
325	unsigned u1CX8 : 1;
326	/** Bit 9 - APIC - APIC On-Chip. */
327	unsigned u1APIC : 1;
328	/** Bit 10 - Reserved. */
329	unsigned u1Reserved1 : 1;
330	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331	unsigned u1SEP : 1;
332	/** Bit 12 - MTRR - Memory Type Range Registers. */
333	unsigned u1MTRR : 1;
334	/** Bit 13 - PGE - PTE Global Bit. */
335	unsigned u1PGE : 1;
336	/** Bit 14 - MCA - Machine Check Architecture. */
337	unsigned u1MCA : 1;
338	/** Bit 15 - CMOV - Conditional Move Instructions. */
339	unsigned u1CMOV : 1;
340	/** Bit 16 - PAT - Page Attribute Table. */
341	unsigned u1PAT : 1;
342	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343	unsigned u1PSE36 : 1;
344	/** Bit 18 - PSN - Processor Serial Number. */
345	unsigned u1PSN : 1;
346	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
347	unsigned u1CLFSH : 1;
348	/** Bit 20 - Reserved. */
349	unsigned u1Reserved2 : 1;
350	/** Bit 21 - DS - Debug Store. */
351	unsigned u1DS : 1;
352	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353	unsigned u1ACPI : 1;
354	/** Bit 23 - MMX - Intel MMX 'Technology'. */
355	unsigned u1MMX : 1;
356	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357	unsigned u1FXSR : 1;
358	/** Bit 25 - SSE - SSE Support. */
359	unsigned u1SSE : 1;
360	/** Bit 26 - SSE2 - SSE2 Support. */
361	unsigned u1SSE2 : 1;
362	/** Bit 27 - SS - Self Snoop. */
363	unsigned u1SS : 1;
364	/** Bit 28 - HTT - Hyper-Threading Technology. */
365	unsigned u1HTT : 1;
366	/** Bit 29 - TM - Thermal Monitor. */
367	unsigned u1TM : 1;
368	/** Bit 30 - Reserved - . */
369	unsigned u1Reserved3 : 1;
370	/** Bit 31 - PBE - Pending Break Enabled. */
371	unsigned u1PBE : 1;
372	} X86CPUIDFEATEDX;
373	#else /* VBOX_FOR_DTRACE_LIB */
374	typedef uint32_t X86CPUIDFEATEDX;
375	#endif /* VBOX_FOR_DTRACE_LIB */
376	/** Pointer to CPUID Feature Information - EDX. */
377	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378	/** Pointer to const CPUID Feature Information - EDX. */
379	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381	/** @name CPUID Vendor information.
382	* CPUID query with EAX=0.
383	* @{
384	*/
385	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396	/** @} */
397
398
399	/** @name CPUID Feature information.
400	* CPUID query with EAX=1.
401	* @{
402	*/
403	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428	/** ECX Bit 12 - FMA. */
429	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436	/** ECX Bit 17 - PCID - Process-context identifiers. */
437	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438	/** ECX Bit 18 - DCA - Direct Cache Access. */
439	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444	/** ECX Bit 21 - x2APIC support. */
445	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446	/** ECX Bit 22 - MOVBE instruction. */
447	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448	/** ECX Bit 23 - POPCNT instruction. */
449	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450	/** ECX Bir 24 - TSC-Deadline. */
451	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452	/** ECX Bit 25 - AES instructions. */
453	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454	/** ECX Bit 26 - XSAVE instruction. */
455	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458	/** ECX Bit 28 - AVX. */
459	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462	/** ECX Bit 30 - RDRAND instruction. */
463	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464	/** ECX Bit 31 - Hypervisor Present (software only). */
465	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468	/** Bit 0 - FPU - x87 FPU on Chip. */
469	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472	/** Bit 2 - DE - Debugging extensions. */
473	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474	/** Bit 3 - PSE - Page Size Extension. */
475	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
477	/** Bit 4 - TSC - Time Stamp Counter. */
478	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481	/** Bit 6 - PAE - Physical Address Extension. */
482	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
484	/** Bit 7 - MCE - Machine Check Exception. */
485	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488	/** Bit 9 - APIC - APIC On-Chip. */
489	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492	/** Bit 12 - MTRR - Memory Type Range Registers. */
493	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494	/** Bit 13 - PGE - PTE Global Bit. */
495	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496	/** Bit 14 - MCA - Machine Check Architecture. */
497	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498	/** Bit 15 - CMOV - Conditional Move Instructions. */
499	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500	/** Bit 16 - PAT - Page Attribute Table. */
501	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504	/** Bit 18 - PSN - Processor Serial Number. */
505	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508	/** Bit 21 - DS - Debug Store. */
509	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512	/** Bit 23 - MMX - Intel MMX Technology. */
513	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516	/** Bit 25 - SSE - SSE Support. */
517	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518	/** Bit 26 - SSE2 - SSE2 Support. */
519	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520	/** Bit 27 - SS - Self Snoop. */
521	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522	/** Bit 28 - HTT - Hyper-Threading Technology. */
523	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524	/** Bit 29 - TM - Therm. Monitor. */
525	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526	/** Bit 31 - PBE - Pending Break Enabled. */
527	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528	/** @} */
529
530	/** @name CPUID mwait/monitor information.
531	* CPUID query with EAX=5.
532	* @{
533	*/
534	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538	/** @} */
539
540
541	/** @name CPUID Structured Extended Feature information.
542	* CPUID query with EAX=7.
543	* @{
544	*/
545	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600	/** @} */
601
602
603	/** @name CPUID Extended Feature information.
604	* CPUID query with EAX=0x80000001.
605	* @{
606	*/
607	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
608	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
609
610	/** EDX Bit 11 - SYSCALL/SYSRET. */
611	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
612	/** EDX Bit 20 - No-Execute/Execute-Disable. */
613	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
614	/** EDX Bit 26 - 1 GB large page. */
615	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
616	/** EDX Bit 27 - RDTSCP. */
617	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
618	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
619	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
620	/** @}*/
621
622	/** @name CPUID AMD Feature information.
623	* CPUID query with EAX=0x80000001.
624	* @{
625	*/
626	/** Bit 0 - FPU - x87 FPU on Chip. */
627	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
628	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
629	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
630	/** Bit 2 - DE - Debugging extensions. */
631	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
632	/** Bit 3 - PSE - Page Size Extension. */
633	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
634	/** Bit 4 - TSC - Time Stamp Counter. */
635	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
636	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
637	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
638	/** Bit 6 - PAE - Physical Address Extension. */
639	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
640	/** Bit 7 - MCE - Machine Check Exception. */
641	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
642	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
643	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
644	/** Bit 9 - APIC - APIC On-Chip. */
645	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
646	/** Bit 12 - MTRR - Memory Type Range Registers. */
647	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
648	/** Bit 13 - PGE - PTE Global Bit. */
649	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
650	/** Bit 14 - MCA - Machine Check Architecture. */
651	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
652	/** Bit 15 - CMOV - Conditional Move Instructions. */
653	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
654	/** Bit 16 - PAT - Page Attribute Table. */
655	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
656	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
657	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
658	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
659	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
660	/** Bit 23 - MMX - Intel MMX Technology. */
661	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
662	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
663	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
664	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
665	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
666	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
667	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
668	/** Bit 31 - 3DNOW - AMD 3DNow. */
669	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
670
671	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
672	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
673	/** Bit 2 - SVM - AMD VM extensions. */
674	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
675	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
676	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
677	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
678	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
679	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
680	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
681	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
682	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
683	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
684	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
685	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
686	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
687	/** Bit 9 - OSVW - AMD OS visible workaround. */
688	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
689	/** Bit 10 - IBS - Instruct based sampling. */
690	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
691	/** Bit 11 - XOP - Extended operation support (see APM6). */
692	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
693	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
694	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
695	/** Bit 13 - WDT - AMD Watchdog timer support. */
696	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
697	/** Bit 15 - LWP - Lightweight profiling support. */
698	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
699	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
700	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
701	/** Bit 19 - NodeId - Indicates support for
702	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
703	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
704	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
705	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
706	/** Bit 22 - TopologyExtensions - . */
707	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
708	/** @} */
709
710
711	/** @name CPUID AMD Feature information.
712	* CPUID query with EAX=0x80000007.
713	* @{
714	*/
715	/** Bit 0 - TS - Temperature Sensor. */
716	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
717	/** Bit 1 - FID - Frequency ID Control. */
718	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
719	/** Bit 2 - VID - Voltage ID Control. */
720	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
721	/** Bit 3 - TTP - THERMTRIP. */
722	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
723	/** Bit 4 - TM - Hardware Thermal Control. */
724	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
725	/** Bit 5 - STC - Software Thermal Control. */
726	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
727	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
728	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
729	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
730	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
731	/** Bit 8 - TSCINVAR - TSC Invariant. */
732	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
733	/** Bit 9 - CPB - TSC Invariant. */
734	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
735	/** Bit 10 - EffFreqRO - MPERF/APERF. */
736	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
737	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
738	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
739	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
740	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
741	/** @} */
742
743
744	/** @name CPUID AMD SVM Feature information.
745	* CPUID query with EAX=0x8000000a.
746	* @{
747	*/
748	/** Bit 0 - NP - Nested Paging supported. */
749	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
750	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
751	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
752	/** Bit 2 - SVML - SVM locking bit supported. */
753	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
754	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
755	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
756	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
757	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
758	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
759	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
760	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
761	* VMCB.TLB_Control is supported. */
762	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
763	/** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
764	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
765	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
766	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
767	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
768	* intercept filter cycle count threshold. */
769	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
770	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
771	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
772	/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
773	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
774	/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
775	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
776	/** @} */
777
778
779	/** @name CR0
780	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
781	* reserved flags.
782	* @{ */
783	/** Bit 0 - PE - Protection Enabled */
784	#define X86_CR0_PE RT_BIT_32(0)
785	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
786	/** Bit 1 - MP - Monitor Coprocessor */
787	#define X86_CR0_MP RT_BIT_32(1)
788	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
789	/** Bit 2 - EM - Emulation. */
790	#define X86_CR0_EM RT_BIT_32(2)
791	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
792	/** Bit 3 - TS - Task Switch. */
793	#define X86_CR0_TS RT_BIT_32(3)
794	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
795	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
796	#define X86_CR0_ET RT_BIT_32(4)
797	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
798	/** Bit 5 - NE - Numeric error (486+). */
799	#define X86_CR0_NE RT_BIT_32(5)
800	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
801	/** Bit 16 - WP - Write Protect (486+). */
802	#define X86_CR0_WP RT_BIT_32(16)
803	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
804	/** Bit 18 - AM - Alignment Mask (486+). */
805	#define X86_CR0_AM RT_BIT_32(18)
806	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
807	/** Bit 29 - NW - Not Write-though (486+). */
808	#define X86_CR0_NW RT_BIT_32(29)
809	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
810	/** Bit 30 - WP - Cache Disable (486+). */
811	#define X86_CR0_CD RT_BIT_32(30)
812	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
813	/** Bit 31 - PG - Paging. */
814	#define X86_CR0_PG RT_BIT_32(31)
815	#define X86_CR0_PAGING RT_BIT_32(31)
816	/** @} */
817
818
819	/** @name CR3
820	* @{ */
821	/** Bit 3 - PWT - Page-level Writes Transparent. */
822	#define X86_CR3_PWT RT_BIT_32(3)
823	/** Bit 4 - PCD - Page-level Cache Disable. */
824	#define X86_CR3_PCD RT_BIT_32(4)
825	/** Bits 12-31 - - Page directory page number. */
826	#define X86_CR3_PAGE_MASK (0xfffff000)
827	/** Bits 5-31 - - PAE Page directory page number. */
828	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
829	/** Bits 12-51 - - AMD64 Page directory page number. */
830	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
831	/** @} */
832
833
834	/** @name CR4
835	* @{ */
836	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
837	#define X86_CR4_VME RT_BIT_32(0)
838	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
839	#define X86_CR4_PVI RT_BIT_32(1)
840	/** Bit 2 - TSD - Time Stamp Disable. */
841	#define X86_CR4_TSD RT_BIT_32(2)
842	/** Bit 3 - DE - Debugging Extensions. */
843	#define X86_CR4_DE RT_BIT_32(3)
844	/** Bit 4 - PSE - Page Size Extension. */
845	#define X86_CR4_PSE RT_BIT_32(4)
846	/** Bit 5 - PAE - Physical Address Extension. */
847	#define X86_CR4_PAE RT_BIT_32(5)
848	/** Bit 6 - MCE - Machine-Check Enable. */
849	#define X86_CR4_MCE RT_BIT_32(6)
850	/** Bit 7 - PGE - Page Global Enable. */
851	#define X86_CR4_PGE RT_BIT_32(7)
852	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
853	#define X86_CR4_PCE RT_BIT_32(8)
854	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
855	#define X86_CR4_OSFXSR RT_BIT_32(9)
856	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
857	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
858	/** Bit 13 - VMXE - VMX mode is enabled. */
859	#define X86_CR4_VMXE RT_BIT_32(13)
860	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
861	#define X86_CR4_SMXE RT_BIT_32(14)
862	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
863	#define X86_CR4_PCIDE RT_BIT_32(17)
864	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
865	* extended states. */
866	#define X86_CR4_OSXSAVE RT_BIT_32(18)
867	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
868	#define X86_CR4_SMEP RT_BIT_32(20)
869	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
870	#define X86_CR4_SMAP RT_BIT_32(21)
871	/** Bit 22 - PKE - Protection Key Enable. */
872	#define X86_CR4_PKE RT_BIT_32(22)
873	/** @} */
874
875
876	/** @name DR6
877	* @{ */
878	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
879	#define X86_DR6_B0 RT_BIT_32(0)
880	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
881	#define X86_DR6_B1 RT_BIT_32(1)
882	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
883	#define X86_DR6_B2 RT_BIT_32(2)
884	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
885	#define X86_DR6_B3 RT_BIT_32(3)
886	/** Mask of all the Bx bits. */
887	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
888	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
889	#define X86_DR6_BD RT_BIT_32(13)
890	/** Bit 14 - BS - Single step */
891	#define X86_DR6_BS RT_BIT_32(14)
892	/** Bit 15 - BT - Task switch. (TSS T bit.) */
893	#define X86_DR6_BT RT_BIT_32(15)
894	/** Value of DR6 after powerup/reset. */
895	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
896	/** Bits which must be 1s in DR6. */
897	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
898	/** Bits which must be 0s in DR6. */
899	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
900	/** Bits which must be 0s on writes to DR6. */
901	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
902	/** @} */
903
904	/** Get the DR6.Bx bit for a the given breakpoint. */
905	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
906
907
908	/** @name DR7
909	* @{ */
910	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
911	#define X86_DR7_L0 RT_BIT_32(0)
912	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
913	#define X86_DR7_G0 RT_BIT_32(1)
914	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
915	#define X86_DR7_L1 RT_BIT_32(2)
916	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
917	#define X86_DR7_G1 RT_BIT_32(3)
918	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
919	#define X86_DR7_L2 RT_BIT_32(4)
920	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
921	#define X86_DR7_G2 RT_BIT_32(5)
922	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
923	#define X86_DR7_L3 RT_BIT_32(6)
924	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
925	#define X86_DR7_G3 RT_BIT_32(7)
926	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
927	#define X86_DR7_LE RT_BIT_32(8)
928	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
929	#define X86_DR7_GE RT_BIT_32(9)
930
931	/** L0, L1, L2, and L3. */
932	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
933	/** L0, L1, L2, and L3. */
934	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
935
936	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
937	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
938	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
939	* instruction is executed.
940	* @see http://www.rcollins.org/secrets/DR7.html */
941	#define X86_DR7_ICE_IR RT_BIT_32(12)
942	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
943	* any DR register is accessed. */
944	#define X86_DR7_GD RT_BIT_32(13)
945	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
946	* Pentium. */
947	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
948	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
949	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
950	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
951	#define X86_DR7_RW0_MASK (3 << 16)
952	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
953	#define X86_DR7_LEN0_MASK (3 << 18)
954	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
955	#define X86_DR7_RW1_MASK (3 << 20)
956	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
957	#define X86_DR7_LEN1_MASK (3 << 22)
958	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
959	#define X86_DR7_RW2_MASK (3 << 24)
960	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
961	#define X86_DR7_LEN2_MASK (3 << 26)
962	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
963	#define X86_DR7_RW3_MASK (3 << 28)
964	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
965	#define X86_DR7_LEN3_MASK (3 << 30)
966
967	/** Bits which reads as 1s. */
968	#define X86_DR7_RA1_MASK RT_BIT_32(10)
969	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
970	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
971	/** Bits which must be 0s when writing to DR7. */
972	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
973
974	/** Calcs the L bit of Nth breakpoint.
975	* @param iBp The breakpoint number [0..3].
976	*/
977	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
978
979	/** Calcs the G bit of Nth breakpoint.
980	* @param iBp The breakpoint number [0..3].
981	*/
982	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
983
984	/** Calcs the L and G bits of Nth breakpoint.
985	* @param iBp The breakpoint number [0..3].
986	*/
987	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
988
989	/** @name Read/Write values.
990	* @{ */
991	/** Break on instruction fetch only. */
992	#define X86_DR7_RW_EO 0U
993	/** Break on write only. */
994	#define X86_DR7_RW_WO 1U
995	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
996	#define X86_DR7_RW_IO 2U
997	/** Break on read or write (but not instruction fetches). */
998	#define X86_DR7_RW_RW 3U
999	/** @} */
1000
1001	/** Shifts a X86_DR7_RW_* value to its right place.
1002	* @param iBp The breakpoint number [0..3].
1003	* @param fRw One of the X86_DR7_RW_* value.
1004	*/
1005	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1006
1007	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1008	* one of the X86_DR7_RW_XXX constants).
1009	*
1010	* @returns X86_DR7_RW_XXX
1011	* @param uDR7 DR7 value
1012	* @param iBp The breakpoint number [0..3].
1013	*/
1014	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1015
1016	/** R/W0, R/W1, R/W2, and R/W3. */
1017	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1018
1019	#ifndef VBOX_FOR_DTRACE_LIB
1020	/** Checks if there are any I/O breakpoint types configured in the RW
1021	* registers. Does NOT check if these are enabled, sorry. */
1022	# define X86_DR7_ANY_RW_IO(uDR7) \
1023	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1024	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1025	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1026	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1027	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1028	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1029	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1030	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1031	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1032	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1033	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1034	#endif /* !VBOX_FOR_DTRACE_LIB */
1035
1036	/** @name Length values.
1037	* @{ */
1038	#define X86_DR7_LEN_BYTE 0U
1039	#define X86_DR7_LEN_WORD 1U
1040	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
1041	#define X86_DR7_LEN_DWORD 3U
1042	/** @} */
1043
1044	/** Shifts a X86_DR7_LEN_* value to its right place.
1045	* @param iBp The breakpoint number [0..3].
1046	* @param cb One of the X86_DR7_LEN_* values.
1047	*/
1048	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1049
1050	/** Fetch the breakpoint length bits from the DR7 value.
1051	* @param uDR7 DR7 value
1052	* @param iBp The breakpoint number [0..3].
1053	*/
1054	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1055
1056	/** Mask used to check if any breakpoints are enabled. */
1057	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1058
1059	/** LEN0, LEN1, LEN2, and LEN3. */
1060	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1061	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1062	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1063
1064	/** Value of DR7 after powerup/reset. */
1065	#define X86_DR7_INIT_VAL 0x400
1066	/** @} */
1067
1068
1069	/** @name Machine Specific Registers
1070	* @{
1071	*/
1072	/** Machine check address register (P5). */
1073	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1074	/** Machine check type register (P5). */
1075	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1076	/** Time Stamp Counter. */
1077	#define MSR_IA32_TSC 0x10
1078	#define MSR_IA32_CESR UINT32_C(0x00000011)
1079	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1080	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1081
1082	#define MSR_IA32_PLATFORM_ID 0x17
1083
1084	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1085	# define MSR_IA32_APICBASE 0x1b
1086	/** Local APIC enabled. */
1087	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1088	/** X2APIC enabled (requires the EN bit to be set). */
1089	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1090	/** The processor is the boot strap processor (BSP). */
1091	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1092	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1093	* width. */
1094	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1095	/** The default physical base address of the APIC. */
1096	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1097	/** Gets the physical base address from the MSR. */
1098	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1099	#endif
1100
1101	/** Undocumented intel MSR for reporting thread and core counts.
1102	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1103	* first 16 bits is the thread count. The next 16 bits the core count, except
1104	* on Westmere where it seems it's only the next 4 bits for some reason. */
1105	#define MSR_CORE_THREAD_COUNT 0x35
1106
1107	/** CPU Feature control. */
1108	#define MSR_IA32_FEATURE_CONTROL 0x3A
1109	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
1110	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
1111	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
1112
1113	/** Per-processor TSC adjust MSR. */
1114	#define MSR_IA32_TSC_ADJUST 0x3B
1115
1116	/** BIOS update trigger (microcode update). */
1117	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1118
1119	/** BIOS update signature (microcode). */
1120	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1121
1122	/** SMM monitor control. */
1123	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1124
1125	/** General performance counter no. 0. */
1126	#define MSR_IA32_PMC0 0xC1
1127	/** General performance counter no. 1. */
1128	#define MSR_IA32_PMC1 0xC2
1129	/** General performance counter no. 2. */
1130	#define MSR_IA32_PMC2 0xC3
1131	/** General performance counter no. 3. */
1132	#define MSR_IA32_PMC3 0xC4
1133
1134	/** Nehalem power control. */
1135	#define MSR_IA32_PLATFORM_INFO 0xCE
1136
1137	/** Get FSB clock status (Intel-specific). */
1138	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1139
1140	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1141	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1142
1143	/** C0 Maximum Frequency Clock Count */
1144	#define MSR_IA32_MPERF 0xE7
1145	/** C0 Actual Frequency Clock Count */
1146	#define MSR_IA32_APERF 0xE8
1147
1148	/** MTRR Capabilities. */
1149	#define MSR_IA32_MTRR_CAP 0xFE
1150
1151	/** Cache control/info. */
1152	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1153
1154	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1155	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1156	* R0 SS == CS + 8
1157	* R3 CS == CS + 16
1158	* R3 SS == CS + 24
1159	*/
1160	#define MSR_IA32_SYSENTER_CS 0x174
1161	/** SYSENTER_ESP - the R0 ESP. */
1162	#define MSR_IA32_SYSENTER_ESP 0x175
1163	/** SYSENTER_EIP - the R0 EIP. */
1164	#define MSR_IA32_SYSENTER_EIP 0x176
1165	#endif
1166
1167	/** Machine Check Global Capabilities Register. */
1168	#define MSR_IA32_MCG_CAP 0x179
1169	/** Machine Check Global Status Register. */
1170	#define MSR_IA32_MCG_STATUS 0x17A
1171	/** Machine Check Global Control Register. */
1172	#define MSR_IA32_MCG_CTRL 0x17B
1173
1174	/** Page Attribute Table. */
1175	#define MSR_IA32_CR_PAT 0x277
1176
1177	/** Performance counter MSRs. (Intel only) */
1178	#define MSR_IA32_PERFEVTSEL0 0x186
1179	#define MSR_IA32_PERFEVTSEL1 0x187
1180	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1181	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1182	* holds a ratio that Apple takes for TSC granularity.
1183	*
1184	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1185	#define MSR_FLEX_RATIO 0x194
1186	/** Performance state value and starting with Intel core more.
1187	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1188	#define MSR_IA32_PERF_STATUS 0x198
1189	#define MSR_IA32_PERF_CTL 0x199
1190	#define MSR_IA32_THERM_STATUS 0x19c
1191
1192	/** Enable misc. processor features (R/W). */
1193	#define MSR_IA32_MISC_ENABLE 0x1A0
1194	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1195	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1196	/** Automatic Thermal Control Circuit Enable (R/W). */
1197	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1198	/** Performance Monitoring Available (R). */
1199	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1200	/** Branch Trace Storage Unavailable (R/O). */
1201	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1202	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1203	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1204	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1205	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1206	/** If MONITOR/MWAIT is supported (R/W). */
1207	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1208	/** Limit CPUID Maxval to 3 leafs (R/W). */
1209	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1210	/** When set to 1, xTPR messages are disabled (R/W). */
1211	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1212	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1213	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1214
1215	/** Trace/Profile Resource Control (R/W) */
1216	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1217	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1218	* related Xeons. */
1219	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1220	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1221	* @{ */
1222	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1223	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1224	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1225	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1226	/** @} */
1227
1228
1229	#define IA32_MTRR_PHYSBASE0 0x200
1230	#define IA32_MTRR_PHYSMASK0 0x201
1231	#define IA32_MTRR_PHYSBASE1 0x202
1232	#define IA32_MTRR_PHYSMASK1 0x203
1233	#define IA32_MTRR_PHYSBASE2 0x204
1234	#define IA32_MTRR_PHYSMASK2 0x205
1235	#define IA32_MTRR_PHYSBASE3 0x206
1236	#define IA32_MTRR_PHYSMASK3 0x207
1237	#define IA32_MTRR_PHYSBASE4 0x208
1238	#define IA32_MTRR_PHYSMASK4 0x209
1239	#define IA32_MTRR_PHYSBASE5 0x20a
1240	#define IA32_MTRR_PHYSMASK5 0x20b
1241	#define IA32_MTRR_PHYSBASE6 0x20c
1242	#define IA32_MTRR_PHYSMASK6 0x20d
1243	#define IA32_MTRR_PHYSBASE7 0x20e
1244	#define IA32_MTRR_PHYSMASK7 0x20f
1245	#define IA32_MTRR_PHYSBASE8 0x210
1246	#define IA32_MTRR_PHYSMASK8 0x211
1247	#define IA32_MTRR_PHYSBASE9 0x212
1248	#define IA32_MTRR_PHYSMASK9 0x213
1249
1250	/** Fixed range MTRRs.
1251	* @{ */
1252	#define IA32_MTRR_FIX64K_00000 0x250
1253	#define IA32_MTRR_FIX16K_80000 0x258
1254	#define IA32_MTRR_FIX16K_A0000 0x259
1255	#define IA32_MTRR_FIX4K_C0000 0x268
1256	#define IA32_MTRR_FIX4K_C8000 0x269
1257	#define IA32_MTRR_FIX4K_D0000 0x26a
1258	#define IA32_MTRR_FIX4K_D8000 0x26b
1259	#define IA32_MTRR_FIX4K_E0000 0x26c
1260	#define IA32_MTRR_FIX4K_E8000 0x26d
1261	#define IA32_MTRR_FIX4K_F0000 0x26e
1262	#define IA32_MTRR_FIX4K_F8000 0x26f
1263	/** @} */
1264
1265	/** MTRR Default Range. */
1266	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1267
1268	/** Global performance counter control facilities (Intel only). */
1269	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1270	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1271	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1272
1273	/** Precise Event Based sampling (Intel only). */
1274	#define MSR_IA32_PEBS_ENABLE 0x3F1
1275
1276	#define MSR_IA32_MC0_CTL 0x400
1277	#define MSR_IA32_MC0_STATUS 0x401
1278
1279	/** Basic VMX information. */
1280	#define MSR_IA32_VMX_BASIC_INFO 0x480
1281	/** Allowed settings for pin-based VM execution controls */
1282	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1283	/** Allowed settings for proc-based VM execution controls */
1284	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1285	/** Allowed settings for the VMX exit controls. */
1286	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1287	/** Allowed settings for the VMX entry controls. */
1288	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1289	/** Misc VMX info. */
1290	#define MSR_IA32_VMX_MISC 0x485
1291	/** Fixed cleared bits in CR0. */
1292	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1293	/** Fixed set bits in CR0. */
1294	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1295	/** Fixed cleared bits in CR4. */
1296	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1297	/** Fixed set bits in CR4. */
1298	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1299	/** Information for enumerating fields in the VMCS. */
1300	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1301	/** Allowed settings for the VM-functions controls. */
1302	#define MSR_IA32_VMX_VMFUNC 0x491
1303	/** Allowed settings for secondary proc-based VM execution controls */
1304	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1305	/** EPT capabilities. */
1306	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1307	/** Allowed settings of all pin-based VM execution controls. */
1308	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1309	/** Allowed settings of all proc-based VM execution controls. */
1310	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1311	/** Allowed settings of all VMX exit controls. */
1312	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1313	/** Allowed settings of all VMX entry controls. */
1314	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1315
1316	/** DS Save Area (R/W). */
1317	#define MSR_IA32_DS_AREA 0x600
1318	/** Running Average Power Limit (RAPL) power units. */
1319	#define MSR_RAPL_POWER_UNIT 0x606
1320
1321	/** X2APIC MSR range start. */
1322	#define MSR_IA32_X2APIC_START 0x800
1323	/** X2APIC MSR - APIC ID Register. */
1324	#define MSR_IA32_X2APIC_ID 0x802
1325	/** X2APIC MSR - APIC Version Register. */
1326	#define MSR_IA32_X2APIC_VERSION 0x803
1327	/** X2APIC MSR - Task Priority Register. */
1328	#define MSR_IA32_X2APIC_TPR 0x808
1329	/** X2APIC MSR - Processor Priority register. */
1330	#define MSR_IA32_X2APIC_PPR 0x80A
1331	/** X2APIC MSR - End Of Interrupt register. */
1332	#define MSR_IA32_X2APIC_EOI 0x80B
1333	/** X2APIC MSR - Logical Destination Register. */
1334	#define MSR_IA32_X2APIC_LDR 0x80D
1335	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1336	#define MSR_IA32_X2APIC_SVR 0x80F
1337	/** X2APIC MSR - In-service Register (bits 31:0). */
1338	#define MSR_IA32_X2APIC_ISR0 0x810
1339	/** X2APIC MSR - In-service Register (bits 63:32). */
1340	#define MSR_IA32_X2APIC_ISR1 0x811
1341	/** X2APIC MSR - In-service Register (bits 95:64). */
1342	#define MSR_IA32_X2APIC_ISR2 0x812
1343	/** X2APIC MSR - In-service Register (bits 127:96). */
1344	#define MSR_IA32_X2APIC_ISR3 0x813
1345	/** X2APIC MSR - In-service Register (bits 159:128). */
1346	#define MSR_IA32_X2APIC_ISR4 0x814
1347	/** X2APIC MSR - In-service Register (bits 191:160). */
1348	#define MSR_IA32_X2APIC_ISR5 0x815
1349	/** X2APIC MSR - In-service Register (bits 223:192). */
1350	#define MSR_IA32_X2APIC_ISR6 0x816
1351	/** X2APIC MSR - In-service Register (bits 255:224). */
1352	#define MSR_IA32_X2APIC_ISR7 0x817
1353	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1354	#define MSR_IA32_X2APIC_TMR0 0x818
1355	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1356	#define MSR_IA32_X2APIC_TMR1 0x819
1357	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1358	#define MSR_IA32_X2APIC_TMR2 0x81A
1359	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1360	#define MSR_IA32_X2APIC_TMR3 0x81B
1361	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1362	#define MSR_IA32_X2APIC_TMR4 0x81C
1363	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1364	#define MSR_IA32_X2APIC_TMR5 0x81D
1365	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1366	#define MSR_IA32_X2APIC_TMR6 0x81E
1367	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1368	#define MSR_IA32_X2APIC_TMR7 0x81F
1369	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1370	#define MSR_IA32_X2APIC_IRR0 0x820
1371	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1372	#define MSR_IA32_X2APIC_IRR1 0x821
1373	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1374	#define MSR_IA32_X2APIC_IRR2 0x822
1375	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1376	#define MSR_IA32_X2APIC_IRR3 0x823
1377	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1378	#define MSR_IA32_X2APIC_IRR4 0x824
1379	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1380	#define MSR_IA32_X2APIC_IRR5 0x825
1381	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1382	#define MSR_IA32_X2APIC_IRR6 0x826
1383	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1384	#define MSR_IA32_X2APIC_IRR7 0x827
1385	/** X2APIC MSR - Error Status Register. */
1386	#define MSR_IA32_X2APIC_ESR 0x828
1387	/** X2APIC MSR - LVT CMCI Register. */
1388	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1389	/** X2APIC MSR - Interrupt Command Register. */
1390	#define MSR_IA32_X2APIC_ICR 0x830
1391	/** X2APIC MSR - LVT Timer Register. */
1392	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1393	/** X2APIC MSR - LVT Thermal Sensor Register. */
1394	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1395	/** X2APIC MSR - LVT Performance Counter Register. */
1396	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1397	/** X2APIC MSR - LVT LINT0 Register. */
1398	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1399	/** X2APIC MSR - LVT LINT1 Register. */
1400	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1401	/** X2APIC MSR - LVT Error Register . */
1402	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1403	/** X2APIC MSR - Timer Initial Count Register. */
1404	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1405	/** X2APIC MSR - Timer Current Count Register. */
1406	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1407	/** X2APIC MSR - Timer Divide Configuration Register. */
1408	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1409	/** X2APIC MSR - Self IPI. */
1410	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1411	/** X2APIC MSR range end. */
1412	#define MSR_IA32_X2APIC_END 0xBFF
1413	/** X2APIC MSR - LVT start range. */
1414	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1415	/** X2APIC MSR - LVT end range (inclusive). */
1416	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1417
1418	/** K6 EFER - Extended Feature Enable Register. */
1419	#define MSR_K6_EFER UINT32_C(0xc0000080)
1420	/** @todo document EFER */
1421	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1422	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1423	/** Bit 8 - LME - Long mode enabled. (R/W) */
1424	#define MSR_K6_EFER_LME RT_BIT_32(8)
1425	/** Bit 10 - LMA - Long mode active. (R) */
1426	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1427	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1428	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1429	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1430	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1431	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1432	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1433	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1434	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1435	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1436	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1437	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1438	/** K6 STAR - SYSCALL/RET targets. */
1439	#define MSR_K6_STAR UINT32_C(0xc0000081)
1440	/** Shift value for getting the SYSRET CS and SS value. */
1441	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1442	/** Shift value for getting the SYSCALL CS and SS value. */
1443	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1444	/** Selector mask for use after shifting. */
1445	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1446	/** The mask which give the SYSCALL EIP. */
1447	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1448	/** K6 WHCR - Write Handling Control Register. */
1449	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1450	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1451	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1452	/** K6 PSOR - Processor State Observability Register. */
1453	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1454	/** K6 PFIR - Page Flush/Invalidate Register. */
1455	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1456
1457	/** Performance counter MSRs. (AMD only) */
1458	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1459	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1460	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1461	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1462	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1463	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1464	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1465	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1466
1467	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1468	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1469	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1470	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1471	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1472	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1473	/** K8 FS.base - The 64-bit base FS register. */
1474	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1475	/** K8 GS.base - The 64-bit base GS register. */
1476	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1477	/** K8 KernelGSbase - Used with SWAPGS. */
1478	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1479	/** K8 TSC_AUX - Used with RDTSCP. */
1480	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1481	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1482	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1483	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1484	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1485	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1486	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1487	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1488	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1489	/** North bridge config? See BIOS & Kernel dev guides for
1490	* details. */
1491	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1492
1493	/** Hypertransport interrupt pending register.
1494	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1495	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1496
1497	/** SVM Control. */
1498	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1499	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1500	* features. */
1501	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1502	/** If set, non-intercepted INIT signals are converted to \#SX
1503	* exceptions. */
1504	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1505	/** Disables A20 masking. */
1506	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1507	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1508	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1509	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1510	* clear, EFER.SVME can be written normally. */
1511	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1512
1513	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1514	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1515	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1516	* host state during world switch. */
1517	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1518
1519	/** @} */
1520
1521
1522	/** @name Page Table / Directory / Directory Pointers / L4.
1523	* @{
1524	*/
1525
1526	/** Page table/directory entry as an unsigned integer. */
1527	typedef uint32_t X86PGUINT;
1528	/** Pointer to a page table/directory table entry as an unsigned integer. */
1529	typedef X86PGUINT *PX86PGUINT;
1530	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1531	typedef X86PGUINT const *PCX86PGUINT;
1532
1533	/** Number of entries in a 32-bit PT/PD. */
1534	#define X86_PG_ENTRIES 1024
1535
1536
1537	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1538	typedef uint64_t X86PGPAEUINT;
1539	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1540	typedef X86PGPAEUINT *PX86PGPAEUINT;
1541	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1542	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1543
1544	/** Number of entries in a PAE PT/PD. */
1545	#define X86_PG_PAE_ENTRIES 512
1546	/** Number of entries in a PAE PDPT. */
1547	#define X86_PG_PAE_PDPE_ENTRIES 4
1548
1549	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1550	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1551	/** Number of entries in an AMD64 PDPT.
1552	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1553	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1554
1555	/** The size of a default page. */
1556	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1557	/** The page shift of a default page. */
1558	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1559	/** The default page offset mask. */
1560	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1561	/** The default page base mask for virtual addresses. */
1562	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1563	/** The default page base mask for virtual addresses - 32bit version. */
1564	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1565
1566	/** The size of a 4KB page. */
1567	#define X86_PAGE_4K_SIZE _4K
1568	/** The page shift of a 4KB page. */
1569	#define X86_PAGE_4K_SHIFT 12
1570	/** The 4KB page offset mask. */
1571	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1572	/** The 4KB page base mask for virtual addresses. */
1573	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1574	/** The 4KB page base mask for virtual addresses - 32bit version. */
1575	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1576
1577	/** The size of a 2MB page. */
1578	#define X86_PAGE_2M_SIZE _2M
1579	/** The page shift of a 2MB page. */
1580	#define X86_PAGE_2M_SHIFT 21
1581	/** The 2MB page offset mask. */
1582	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1583	/** The 2MB page base mask for virtual addresses. */
1584	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1585	/** The 2MB page base mask for virtual addresses - 32bit version. */
1586	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1587
1588	/** The size of a 4MB page. */
1589	#define X86_PAGE_4M_SIZE _4M
1590	/** The page shift of a 4MB page. */
1591	#define X86_PAGE_4M_SHIFT 22
1592	/** The 4MB page offset mask. */
1593	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1594	/** The 4MB page base mask for virtual addresses. */
1595	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1596	/** The 4MB page base mask for virtual addresses - 32bit version. */
1597	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1598
1599	/**
1600	* Check if the given address is canonical.
1601	*/
1602	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1603
1604
1605	/** @name Page Table Entry
1606	* @{
1607	*/
1608	/** Bit 0 - P - Present bit. */
1609	#define X86_PTE_BIT_P 0
1610	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1611	#define X86_PTE_BIT_RW 1
1612	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1613	#define X86_PTE_BIT_US 2
1614	/** Bit 3 - PWT - Page level write thru bit. */
1615	#define X86_PTE_BIT_PWT 3
1616	/** Bit 4 - PCD - Page level cache disable bit. */
1617	#define X86_PTE_BIT_PCD 4
1618	/** Bit 5 - A - Access bit. */
1619	#define X86_PTE_BIT_A 5
1620	/** Bit 6 - D - Dirty bit. */
1621	#define X86_PTE_BIT_D 6
1622	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1623	#define X86_PTE_BIT_PAT 7
1624	/** Bit 8 - G - Global flag. */
1625	#define X86_PTE_BIT_G 8
1626	/** Bits 63 - NX - PAE/LM - No execution flag. */
1627	#define X86_PTE_PAE_BIT_NX 63
1628
1629	/** Bit 0 - P - Present bit mask. */
1630	#define X86_PTE_P RT_BIT_32(0)
1631	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1632	#define X86_PTE_RW RT_BIT_32(1)
1633	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1634	#define X86_PTE_US RT_BIT_32(2)
1635	/** Bit 3 - PWT - Page level write thru bit mask. */
1636	#define X86_PTE_PWT RT_BIT_32(3)
1637	/** Bit 4 - PCD - Page level cache disable bit mask. */
1638	#define X86_PTE_PCD RT_BIT_32(4)
1639	/** Bit 5 - A - Access bit mask. */
1640	#define X86_PTE_A RT_BIT_32(5)
1641	/** Bit 6 - D - Dirty bit mask. */
1642	#define X86_PTE_D RT_BIT_32(6)
1643	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1644	#define X86_PTE_PAT RT_BIT_32(7)
1645	/** Bit 8 - G - Global bit mask. */
1646	#define X86_PTE_G RT_BIT_32(8)
1647
1648	/** Bits 9-11 - - Available for use to system software. */
1649	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1650	/** Bits 12-31 - - Physical Page number of the next level. */
1651	#define X86_PTE_PG_MASK ( 0xfffff000 )
1652
1653	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1654	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1655	/** Bits 63 - NX - PAE/LM - No execution flag. */
1656	#define X86_PTE_PAE_NX RT_BIT_64(63)
1657	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1658	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1659	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1660	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1661	/** No bits - - LM - MBZ bits when NX is active. */
1662	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1663	/** Bits 63 - - LM - MBZ bits when no NX. */
1664	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1665
1666	/**
1667	* Page table entry.
1668	*/
1669	typedef struct X86PTEBITS
1670	{
1671	/** Flags whether(=1) or not the page is present. */
1672	uint32_t u1Present : 1;
1673	/** Read(=0) / Write(=1) flag. */
1674	uint32_t u1Write : 1;
1675	/** User(=1) / Supervisor (=0) flag. */
1676	uint32_t u1User : 1;
1677	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1678	uint32_t u1WriteThru : 1;
1679	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1680	uint32_t u1CacheDisable : 1;
1681	/** Accessed flag.
1682	* Indicates that the page have been read or written to. */
1683	uint32_t u1Accessed : 1;
1684	/** Dirty flag.
1685	* Indicates that the page has been written to. */
1686	uint32_t u1Dirty : 1;
1687	/** Reserved / If PAT enabled, bit 2 of the index. */
1688	uint32_t u1PAT : 1;
1689	/** Global flag. (Ignored in all but final level.) */
1690	uint32_t u1Global : 1;
1691	/** Available for use to system software. */
1692	uint32_t u3Available : 3;
1693	/** Physical Page number of the next level. */
1694	uint32_t u20PageNo : 20;
1695	} X86PTEBITS;
1696	#ifndef VBOX_FOR_DTRACE_LIB
1697	AssertCompileSize(X86PTEBITS, 4);
1698	#endif
1699	/** Pointer to a page table entry. */
1700	typedef X86PTEBITS *PX86PTEBITS;
1701	/** Pointer to a const page table entry. */
1702	typedef const X86PTEBITS *PCX86PTEBITS;
1703
1704	/**
1705	* Page table entry.
1706	*/
1707	typedef union X86PTE
1708	{
1709	/** Unsigned integer view */
1710	X86PGUINT u;
1711	/** Bit field view. */
1712	X86PTEBITS n;
1713	/** 32-bit view. */
1714	uint32_t au32[1];
1715	/** 16-bit view. */
1716	uint16_t au16[2];
1717	/** 8-bit view. */
1718	uint8_t au8[4];
1719	} X86PTE;
1720	#ifndef VBOX_FOR_DTRACE_LIB
1721	AssertCompileSize(X86PTE, 4);
1722	#endif
1723	/** Pointer to a page table entry. */
1724	typedef X86PTE *PX86PTE;
1725	/** Pointer to a const page table entry. */
1726	typedef const X86PTE *PCX86PTE;
1727
1728
1729	/**
1730	* PAE page table entry.
1731	*/
1732	typedef struct X86PTEPAEBITS
1733	{
1734	/** Flags whether(=1) or not the page is present. */
1735	uint32_t u1Present : 1;
1736	/** Read(=0) / Write(=1) flag. */
1737	uint32_t u1Write : 1;
1738	/** User(=1) / Supervisor(=0) flag. */
1739	uint32_t u1User : 1;
1740	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1741	uint32_t u1WriteThru : 1;
1742	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1743	uint32_t u1CacheDisable : 1;
1744	/** Accessed flag.
1745	* Indicates that the page have been read or written to. */
1746	uint32_t u1Accessed : 1;
1747	/** Dirty flag.
1748	* Indicates that the page has been written to. */
1749	uint32_t u1Dirty : 1;
1750	/** Reserved / If PAT enabled, bit 2 of the index. */
1751	uint32_t u1PAT : 1;
1752	/** Global flag. (Ignored in all but final level.) */
1753	uint32_t u1Global : 1;
1754	/** Available for use to system software. */
1755	uint32_t u3Available : 3;
1756	/** Physical Page number of the next level - Low Part. Don't use this. */
1757	uint32_t u20PageNoLow : 20;
1758	/** Physical Page number of the next level - High Part. Don't use this. */
1759	uint32_t u20PageNoHigh : 20;
1760	/** MBZ bits */
1761	uint32_t u11Reserved : 11;
1762	/** No Execute flag. */
1763	uint32_t u1NoExecute : 1;
1764	} X86PTEPAEBITS;
1765	#ifndef VBOX_FOR_DTRACE_LIB
1766	AssertCompileSize(X86PTEPAEBITS, 8);
1767	#endif
1768	/** Pointer to a page table entry. */
1769	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1770	/** Pointer to a page table entry. */
1771	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1772
1773	/**
1774	* PAE Page table entry.
1775	*/
1776	typedef union X86PTEPAE
1777	{
1778	/** Unsigned integer view */
1779	X86PGPAEUINT u;
1780	/** Bit field view. */
1781	X86PTEPAEBITS n;
1782	/** 32-bit view. */
1783	uint32_t au32[2];
1784	/** 16-bit view. */
1785	uint16_t au16[4];
1786	/** 8-bit view. */
1787	uint8_t au8[8];
1788	} X86PTEPAE;
1789	#ifndef VBOX_FOR_DTRACE_LIB
1790	AssertCompileSize(X86PTEPAE, 8);
1791	#endif
1792	/** Pointer to a PAE page table entry. */
1793	typedef X86PTEPAE *PX86PTEPAE;
1794	/** Pointer to a const PAE page table entry. */
1795	typedef const X86PTEPAE *PCX86PTEPAE;
1796	/** @} */
1797
1798	/**
1799	* Page table.
1800	*/
1801	typedef struct X86PT
1802	{
1803	/** PTE Array. */
1804	X86PTE a[X86_PG_ENTRIES];
1805	} X86PT;
1806	#ifndef VBOX_FOR_DTRACE_LIB
1807	AssertCompileSize(X86PT, 4096);
1808	#endif
1809	/** Pointer to a page table. */
1810	typedef X86PT *PX86PT;
1811	/** Pointer to a const page table. */
1812	typedef const X86PT *PCX86PT;
1813
1814	/** The page shift to get the PT index. */
1815	#define X86_PT_SHIFT 12
1816	/** The PT index mask (apply to a shifted page address). */
1817	#define X86_PT_MASK 0x3ff
1818
1819
1820	/**
1821	* Page directory.
1822	*/
1823	typedef struct X86PTPAE
1824	{
1825	/** PTE Array. */
1826	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1827	} X86PTPAE;
1828	#ifndef VBOX_FOR_DTRACE_LIB
1829	AssertCompileSize(X86PTPAE, 4096);
1830	#endif
1831	/** Pointer to a page table. */
1832	typedef X86PTPAE *PX86PTPAE;
1833	/** Pointer to a const page table. */
1834	typedef const X86PTPAE *PCX86PTPAE;
1835
1836	/** The page shift to get the PA PTE index. */
1837	#define X86_PT_PAE_SHIFT 12
1838	/** The PAE PT index mask (apply to a shifted page address). */
1839	#define X86_PT_PAE_MASK 0x1ff
1840
1841
1842	/** @name 4KB Page Directory Entry
1843	* @{
1844	*/
1845	/** Bit 0 - P - Present bit. */
1846	#define X86_PDE_P RT_BIT_32(0)
1847	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1848	#define X86_PDE_RW RT_BIT_32(1)
1849	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1850	#define X86_PDE_US RT_BIT_32(2)
1851	/** Bit 3 - PWT - Page level write thru bit. */
1852	#define X86_PDE_PWT RT_BIT_32(3)
1853	/** Bit 4 - PCD - Page level cache disable bit. */
1854	#define X86_PDE_PCD RT_BIT_32(4)
1855	/** Bit 5 - A - Access bit. */
1856	#define X86_PDE_A RT_BIT_32(5)
1857	/** Bit 7 - PS - Page size attribute.
1858	* Clear mean 4KB pages, set means large pages (2/4MB). */
1859	#define X86_PDE_PS RT_BIT_32(7)
1860	/** Bits 9-11 - - Available for use to system software. */
1861	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1862	/** Bits 12-31 - - Physical Page number of the next level. */
1863	#define X86_PDE_PG_MASK ( 0xfffff000 )
1864
1865	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1866	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1867	/** Bits 63 - NX - PAE/LM - No execution flag. */
1868	#define X86_PDE_PAE_NX RT_BIT_64(63)
1869	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1870	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1871	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1872	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1873	/** Bit 7 - - LM - MBZ bits when NX is active. */
1874	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1875	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1876	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1877
1878	/**
1879	* Page directory entry.
1880	*/
1881	typedef struct X86PDEBITS
1882	{
1883	/** Flags whether(=1) or not the page is present. */
1884	uint32_t u1Present : 1;
1885	/** Read(=0) / Write(=1) flag. */
1886	uint32_t u1Write : 1;
1887	/** User(=1) / Supervisor (=0) flag. */
1888	uint32_t u1User : 1;
1889	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1890	uint32_t u1WriteThru : 1;
1891	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1892	uint32_t u1CacheDisable : 1;
1893	/** Accessed flag.
1894	* Indicates that the page has been read or written to. */
1895	uint32_t u1Accessed : 1;
1896	/** Reserved / Ignored (dirty bit). */
1897	uint32_t u1Reserved0 : 1;
1898	/** Size bit if PSE is enabled - in any event it's 0. */
1899	uint32_t u1Size : 1;
1900	/** Reserved / Ignored (global bit). */
1901	uint32_t u1Reserved1 : 1;
1902	/** Available for use to system software. */
1903	uint32_t u3Available : 3;
1904	/** Physical Page number of the next level. */
1905	uint32_t u20PageNo : 20;
1906	} X86PDEBITS;
1907	#ifndef VBOX_FOR_DTRACE_LIB
1908	AssertCompileSize(X86PDEBITS, 4);
1909	#endif
1910	/** Pointer to a page directory entry. */
1911	typedef X86PDEBITS *PX86PDEBITS;
1912	/** Pointer to a const page directory entry. */
1913	typedef const X86PDEBITS *PCX86PDEBITS;
1914
1915
1916	/**
1917	* PAE page directory entry.
1918	*/
1919	typedef struct X86PDEPAEBITS
1920	{
1921	/** Flags whether(=1) or not the page is present. */
1922	uint32_t u1Present : 1;
1923	/** Read(=0) / Write(=1) flag. */
1924	uint32_t u1Write : 1;
1925	/** User(=1) / Supervisor (=0) flag. */
1926	uint32_t u1User : 1;
1927	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1928	uint32_t u1WriteThru : 1;
1929	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1930	uint32_t u1CacheDisable : 1;
1931	/** Accessed flag.
1932	* Indicates that the page has been read or written to. */
1933	uint32_t u1Accessed : 1;
1934	/** Reserved / Ignored (dirty bit). */
1935	uint32_t u1Reserved0 : 1;
1936	/** Size bit if PSE is enabled - in any event it's 0. */
1937	uint32_t u1Size : 1;
1938	/** Reserved / Ignored (global bit). / */
1939	uint32_t u1Reserved1 : 1;
1940	/** Available for use to system software. */
1941	uint32_t u3Available : 3;
1942	/** Physical Page number of the next level - Low Part. Don't use! */
1943	uint32_t u20PageNoLow : 20;
1944	/** Physical Page number of the next level - High Part. Don't use! */
1945	uint32_t u20PageNoHigh : 20;
1946	/** MBZ bits */
1947	uint32_t u11Reserved : 11;
1948	/** No Execute flag. */
1949	uint32_t u1NoExecute : 1;
1950	} X86PDEPAEBITS;
1951	#ifndef VBOX_FOR_DTRACE_LIB
1952	AssertCompileSize(X86PDEPAEBITS, 8);
1953	#endif
1954	/** Pointer to a page directory entry. */
1955	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1956	/** Pointer to a const page directory entry. */
1957	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1958
1959	/** @} */
1960
1961
1962	/** @name 2/4MB Page Directory Entry
1963	* @{
1964	*/
1965	/** Bit 0 - P - Present bit. */
1966	#define X86_PDE4M_P RT_BIT_32(0)
1967	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1968	#define X86_PDE4M_RW RT_BIT_32(1)
1969	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1970	#define X86_PDE4M_US RT_BIT_32(2)
1971	/** Bit 3 - PWT - Page level write thru bit. */
1972	#define X86_PDE4M_PWT RT_BIT_32(3)
1973	/** Bit 4 - PCD - Page level cache disable bit. */
1974	#define X86_PDE4M_PCD RT_BIT_32(4)
1975	/** Bit 5 - A - Access bit. */
1976	#define X86_PDE4M_A RT_BIT_32(5)
1977	/** Bit 6 - D - Dirty bit. */
1978	#define X86_PDE4M_D RT_BIT_32(6)
1979	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1980	#define X86_PDE4M_PS RT_BIT_32(7)
1981	/** Bit 8 - G - Global flag. */
1982	#define X86_PDE4M_G RT_BIT_32(8)
1983	/** Bits 9-11 - AVL - Available for use to system software. */
1984	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1985	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1986	#define X86_PDE4M_PAT RT_BIT_32(12)
1987	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1988	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1989	/** Bits 22-31 - - Physical Page number. */
1990	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1991	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1992	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1993	/** The number of bits to the high part of the page number. */
1994	#define X86_PDE4M_PG_HIGH_SHIFT 19
1995	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1996	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1997
1998	/** Bits 21-51 - - PAE/LM - Physical Page number.
1999	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2000	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2001	/** Bits 63 - NX - PAE/LM - No execution flag. */
2002	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2003	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2004	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2005	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2006	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2007	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2008	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2009	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2010	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2011
2012	/**
2013	* 4MB page directory entry.
2014	*/
2015	typedef struct X86PDE4MBITS
2016	{
2017	/** Flags whether(=1) or not the page is present. */
2018	uint32_t u1Present : 1;
2019	/** Read(=0) / Write(=1) flag. */
2020	uint32_t u1Write : 1;
2021	/** User(=1) / Supervisor (=0) flag. */
2022	uint32_t u1User : 1;
2023	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2024	uint32_t u1WriteThru : 1;
2025	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2026	uint32_t u1CacheDisable : 1;
2027	/** Accessed flag.
2028	* Indicates that the page have been read or written to. */
2029	uint32_t u1Accessed : 1;
2030	/** Dirty flag.
2031	* Indicates that the page has been written to. */
2032	uint32_t u1Dirty : 1;
2033	/** Page size flag - always 1 for 4MB entries. */
2034	uint32_t u1Size : 1;
2035	/** Global flag. */
2036	uint32_t u1Global : 1;
2037	/** Available for use to system software. */
2038	uint32_t u3Available : 3;
2039	/** Reserved / If PAT enabled, bit 2 of the index. */
2040	uint32_t u1PAT : 1;
2041	/** Bits 32-39 of the page number on AMD64.
2042	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2043	uint32_t u8PageNoHigh : 8;
2044	/** Reserved. */
2045	uint32_t u1Reserved : 1;
2046	/** Physical Page number of the page. */
2047	uint32_t u10PageNo : 10;
2048	} X86PDE4MBITS;
2049	#ifndef VBOX_FOR_DTRACE_LIB
2050	AssertCompileSize(X86PDE4MBITS, 4);
2051	#endif
2052	/** Pointer to a page table entry. */
2053	typedef X86PDE4MBITS *PX86PDE4MBITS;
2054	/** Pointer to a const page table entry. */
2055	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2056
2057
2058	/**
2059	* 2MB PAE page directory entry.
2060	*/
2061	typedef struct X86PDE2MPAEBITS
2062	{
2063	/** Flags whether(=1) or not the page is present. */
2064	uint32_t u1Present : 1;
2065	/** Read(=0) / Write(=1) flag. */
2066	uint32_t u1Write : 1;
2067	/** User(=1) / Supervisor(=0) flag. */
2068	uint32_t u1User : 1;
2069	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2070	uint32_t u1WriteThru : 1;
2071	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2072	uint32_t u1CacheDisable : 1;
2073	/** Accessed flag.
2074	* Indicates that the page have been read or written to. */
2075	uint32_t u1Accessed : 1;
2076	/** Dirty flag.
2077	* Indicates that the page has been written to. */
2078	uint32_t u1Dirty : 1;
2079	/** Page size flag - always 1 for 2MB entries. */
2080	uint32_t u1Size : 1;
2081	/** Global flag. */
2082	uint32_t u1Global : 1;
2083	/** Available for use to system software. */
2084	uint32_t u3Available : 3;
2085	/** Reserved / If PAT enabled, bit 2 of the index. */
2086	uint32_t u1PAT : 1;
2087	/** Reserved. */
2088	uint32_t u9Reserved : 9;
2089	/** Physical Page number of the next level - Low part. Don't use! */
2090	uint32_t u10PageNoLow : 10;
2091	/** Physical Page number of the next level - High part. Don't use! */
2092	uint32_t u20PageNoHigh : 20;
2093	/** MBZ bits */
2094	uint32_t u11Reserved : 11;
2095	/** No Execute flag. */
2096	uint32_t u1NoExecute : 1;
2097	} X86PDE2MPAEBITS;
2098	#ifndef VBOX_FOR_DTRACE_LIB
2099	AssertCompileSize(X86PDE2MPAEBITS, 8);
2100	#endif
2101	/** Pointer to a 2MB PAE page table entry. */
2102	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2103	/** Pointer to a 2MB PAE page table entry. */
2104	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2105
2106	/** @} */
2107
2108	/**
2109	* Page directory entry.
2110	*/
2111	typedef union X86PDE
2112	{
2113	/** Unsigned integer view. */
2114	X86PGUINT u;
2115	/** Normal view. */
2116	X86PDEBITS n;
2117	/** 4MB view (big). */
2118	X86PDE4MBITS b;
2119	/** 8 bit unsigned integer view. */
2120	uint8_t au8[4];
2121	/** 16 bit unsigned integer view. */
2122	uint16_t au16[2];
2123	/** 32 bit unsigned integer view. */
2124	uint32_t au32[1];
2125	} X86PDE;
2126	#ifndef VBOX_FOR_DTRACE_LIB
2127	AssertCompileSize(X86PDE, 4);
2128	#endif
2129	/** Pointer to a page directory entry. */
2130	typedef X86PDE *PX86PDE;
2131	/** Pointer to a const page directory entry. */
2132	typedef const X86PDE *PCX86PDE;
2133
2134	/**
2135	* PAE page directory entry.
2136	*/
2137	typedef union X86PDEPAE
2138	{
2139	/** Unsigned integer view. */
2140	X86PGPAEUINT u;
2141	/** Normal view. */
2142	X86PDEPAEBITS n;
2143	/** 2MB page view (big). */
2144	X86PDE2MPAEBITS b;
2145	/** 8 bit unsigned integer view. */
2146	uint8_t au8[8];
2147	/** 16 bit unsigned integer view. */
2148	uint16_t au16[4];
2149	/** 32 bit unsigned integer view. */
2150	uint32_t au32[2];
2151	} X86PDEPAE;
2152	#ifndef VBOX_FOR_DTRACE_LIB
2153	AssertCompileSize(X86PDEPAE, 8);
2154	#endif
2155	/** Pointer to a page directory entry. */
2156	typedef X86PDEPAE *PX86PDEPAE;
2157	/** Pointer to a const page directory entry. */
2158	typedef const X86PDEPAE *PCX86PDEPAE;
2159
2160	/**
2161	* Page directory.
2162	*/
2163	typedef struct X86PD
2164	{
2165	/** PDE Array. */
2166	X86PDE a[X86_PG_ENTRIES];
2167	} X86PD;
2168	#ifndef VBOX_FOR_DTRACE_LIB
2169	AssertCompileSize(X86PD, 4096);
2170	#endif
2171	/** Pointer to a page directory. */
2172	typedef X86PD *PX86PD;
2173	/** Pointer to a const page directory. */
2174	typedef const X86PD *PCX86PD;
2175
2176	/** The page shift to get the PD index. */
2177	#define X86_PD_SHIFT 22
2178	/** The PD index mask (apply to a shifted page address). */
2179	#define X86_PD_MASK 0x3ff
2180
2181
2182	/**
2183	* PAE page directory.
2184	*/
2185	typedef struct X86PDPAE
2186	{
2187	/** PDE Array. */
2188	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2189	} X86PDPAE;
2190	#ifndef VBOX_FOR_DTRACE_LIB
2191	AssertCompileSize(X86PDPAE, 4096);
2192	#endif
2193	/** Pointer to a PAE page directory. */
2194	typedef X86PDPAE *PX86PDPAE;
2195	/** Pointer to a const PAE page directory. */
2196	typedef const X86PDPAE *PCX86PDPAE;
2197
2198	/** The page shift to get the PAE PD index. */
2199	#define X86_PD_PAE_SHIFT 21
2200	/** The PAE PD index mask (apply to a shifted page address). */
2201	#define X86_PD_PAE_MASK 0x1ff
2202
2203
2204	/** @name Page Directory Pointer Table Entry (PAE)
2205	* @{
2206	*/
2207	/** Bit 0 - P - Present bit. */
2208	#define X86_PDPE_P RT_BIT_32(0)
2209	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2210	#define X86_PDPE_RW RT_BIT_32(1)
2211	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2212	#define X86_PDPE_US RT_BIT_32(2)
2213	/** Bit 3 - PWT - Page level write thru bit. */
2214	#define X86_PDPE_PWT RT_BIT_32(3)
2215	/** Bit 4 - PCD - Page level cache disable bit. */
2216	#define X86_PDPE_PCD RT_BIT_32(4)
2217	/** Bit 5 - A - Access bit. Long Mode only. */
2218	#define X86_PDPE_A RT_BIT_32(5)
2219	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2220	#define X86_PDPE_LM_PS RT_BIT_32(7)
2221	/** Bits 9-11 - - Available for use to system software. */
2222	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2223	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2224	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2225	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2226	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2227	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2228	#define X86_PDPE_LM_NX RT_BIT_64(63)
2229	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2230	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2231	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2232	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2233	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2234	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2235	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2236	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2237
2238
2239	/**
2240	* Page directory pointer table entry.
2241	*/
2242	typedef struct X86PDPEBITS
2243	{
2244	/** Flags whether(=1) or not the page is present. */
2245	uint32_t u1Present : 1;
2246	/** Chunk of reserved bits. */
2247	uint32_t u2Reserved : 2;
2248	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2249	uint32_t u1WriteThru : 1;
2250	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2251	uint32_t u1CacheDisable : 1;
2252	/** Chunk of reserved bits. */
2253	uint32_t u4Reserved : 4;
2254	/** Available for use to system software. */
2255	uint32_t u3Available : 3;
2256	/** Physical Page number of the next level - Low Part. Don't use! */
2257	uint32_t u20PageNoLow : 20;
2258	/** Physical Page number of the next level - High Part. Don't use! */
2259	uint32_t u20PageNoHigh : 20;
2260	/** MBZ bits */
2261	uint32_t u12Reserved : 12;
2262	} X86PDPEBITS;
2263	#ifndef VBOX_FOR_DTRACE_LIB
2264	AssertCompileSize(X86PDPEBITS, 8);
2265	#endif
2266	/** Pointer to a page directory pointer table entry. */
2267	typedef X86PDPEBITS *PX86PTPEBITS;
2268	/** Pointer to a const page directory pointer table entry. */
2269	typedef const X86PDPEBITS *PCX86PTPEBITS;
2270
2271	/**
2272	* Page directory pointer table entry. AMD64 version
2273	*/
2274	typedef struct X86PDPEAMD64BITS
2275	{
2276	/** Flags whether(=1) or not the page is present. */
2277	uint32_t u1Present : 1;
2278	/** Read(=0) / Write(=1) flag. */
2279	uint32_t u1Write : 1;
2280	/** User(=1) / Supervisor (=0) flag. */
2281	uint32_t u1User : 1;
2282	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2283	uint32_t u1WriteThru : 1;
2284	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2285	uint32_t u1CacheDisable : 1;
2286	/** Accessed flag.
2287	* Indicates that the page have been read or written to. */
2288	uint32_t u1Accessed : 1;
2289	/** Chunk of reserved bits. */
2290	uint32_t u3Reserved : 3;
2291	/** Available for use to system software. */
2292	uint32_t u3Available : 3;
2293	/** Physical Page number of the next level - Low Part. Don't use! */
2294	uint32_t u20PageNoLow : 20;
2295	/** Physical Page number of the next level - High Part. Don't use! */
2296	uint32_t u20PageNoHigh : 20;
2297	/** MBZ bits */
2298	uint32_t u11Reserved : 11;
2299	/** No Execute flag. */
2300	uint32_t u1NoExecute : 1;
2301	} X86PDPEAMD64BITS;
2302	#ifndef VBOX_FOR_DTRACE_LIB
2303	AssertCompileSize(X86PDPEAMD64BITS, 8);
2304	#endif
2305	/** Pointer to a page directory pointer table entry. */
2306	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2307	/** Pointer to a const page directory pointer table entry. */
2308	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2309
2310	/**
2311	* Page directory pointer table entry for 1GB page. (AMD64 only)
2312	*/
2313	typedef struct X86PDPE1GB
2314	{
2315	/** 0: Flags whether(=1) or not the page is present. */
2316	uint32_t u1Present : 1;
2317	/** 1: Read(=0) / Write(=1) flag. */
2318	uint32_t u1Write : 1;
2319	/** 2: User(=1) / Supervisor (=0) flag. */
2320	uint32_t u1User : 1;
2321	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2322	uint32_t u1WriteThru : 1;
2323	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2324	uint32_t u1CacheDisable : 1;
2325	/** 5: Accessed flag.
2326	* Indicates that the page have been read or written to. */
2327	uint32_t u1Accessed : 1;
2328	/** 6: Dirty flag for 1GB pages. */
2329	uint32_t u1Dirty : 1;
2330	/** 7: Indicates 1GB page if set. */
2331	uint32_t u1Size : 1;
2332	/** 8: Global 1GB page. */
2333	uint32_t u1Global: 1;
2334	/** 9-11: Available for use to system software. */
2335	uint32_t u3Available : 3;
2336	/** 12: PAT bit for 1GB page. */
2337	uint32_t u1PAT : 1;
2338	/** 13-29: MBZ bits. */
2339	uint32_t u17Reserved : 17;
2340	/** 30-31: Physical page number - Low Part. Don't use! */
2341	uint32_t u2PageNoLow : 2;
2342	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2343	uint32_t u20PageNoHigh : 20;
2344	/** 52-62: MBZ bits */
2345	uint32_t u11Reserved : 11;
2346	/** 63: No Execute flag. */
2347	uint32_t u1NoExecute : 1;
2348	} X86PDPE1GB;
2349	#ifndef VBOX_FOR_DTRACE_LIB
2350	AssertCompileSize(X86PDPE1GB, 8);
2351	#endif
2352	/** Pointer to a page directory pointer table entry for a 1GB page. */
2353	typedef X86PDPE1GB *PX86PDPE1GB;
2354	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2355	typedef const X86PDPE1GB *PCX86PDPE1GB;
2356
2357	/**
2358	* Page directory pointer table entry.
2359	*/
2360	typedef union X86PDPE
2361	{
2362	/** Unsigned integer view. */
2363	X86PGPAEUINT u;
2364	/** Normal view. */
2365	X86PDPEBITS n;
2366	/** AMD64 view. */
2367	X86PDPEAMD64BITS lm;
2368	/** AMD64 big view. */
2369	X86PDPE1GB b;
2370	/** 8 bit unsigned integer view. */
2371	uint8_t au8[8];
2372	/** 16 bit unsigned integer view. */
2373	uint16_t au16[4];
2374	/** 32 bit unsigned integer view. */
2375	uint32_t au32[2];
2376	} X86PDPE;
2377	#ifndef VBOX_FOR_DTRACE_LIB
2378	AssertCompileSize(X86PDPE, 8);
2379	#endif
2380	/** Pointer to a page directory pointer table entry. */
2381	typedef X86PDPE *PX86PDPE;
2382	/** Pointer to a const page directory pointer table entry. */
2383	typedef const X86PDPE *PCX86PDPE;
2384
2385
2386	/**
2387	* Page directory pointer table.
2388	*/
2389	typedef struct X86PDPT
2390	{
2391	/** PDE Array. */
2392	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2393	} X86PDPT;
2394	#ifndef VBOX_FOR_DTRACE_LIB
2395	AssertCompileSize(X86PDPT, 4096);
2396	#endif
2397	/** Pointer to a page directory pointer table. */
2398	typedef X86PDPT *PX86PDPT;
2399	/** Pointer to a const page directory pointer table. */
2400	typedef const X86PDPT *PCX86PDPT;
2401
2402	/** The page shift to get the PDPT index. */
2403	#define X86_PDPT_SHIFT 30
2404	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2405	#define X86_PDPT_MASK_PAE 0x3
2406	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2407	#define X86_PDPT_MASK_AMD64 0x1ff
2408
2409	/** @} */
2410
2411
2412	/** @name Page Map Level-4 Entry (Long Mode PAE)
2413	* @{
2414	*/
2415	/** Bit 0 - P - Present bit. */
2416	#define X86_PML4E_P RT_BIT_32(0)
2417	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2418	#define X86_PML4E_RW RT_BIT_32(1)
2419	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2420	#define X86_PML4E_US RT_BIT_32(2)
2421	/** Bit 3 - PWT - Page level write thru bit. */
2422	#define X86_PML4E_PWT RT_BIT_32(3)
2423	/** Bit 4 - PCD - Page level cache disable bit. */
2424	#define X86_PML4E_PCD RT_BIT_32(4)
2425	/** Bit 5 - A - Access bit. */
2426	#define X86_PML4E_A RT_BIT_32(5)
2427	/** Bits 9-11 - - Available for use to system software. */
2428	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2429	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2430	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2431	/** Bits 8, 7 - - MBZ bits when NX is active. */
2432	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2433	/** Bits 63, 7 - - MBZ bits when no NX. */
2434	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2435	/** Bits 63 - NX - PAE - No execution flag. */
2436	#define X86_PML4E_NX RT_BIT_64(63)
2437
2438	/**
2439	* Page Map Level-4 Entry
2440	*/
2441	typedef struct X86PML4EBITS
2442	{
2443	/** Flags whether(=1) or not the page is present. */
2444	uint32_t u1Present : 1;
2445	/** Read(=0) / Write(=1) flag. */
2446	uint32_t u1Write : 1;
2447	/** User(=1) / Supervisor (=0) flag. */
2448	uint32_t u1User : 1;
2449	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2450	uint32_t u1WriteThru : 1;
2451	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2452	uint32_t u1CacheDisable : 1;
2453	/** Accessed flag.
2454	* Indicates that the page have been read or written to. */
2455	uint32_t u1Accessed : 1;
2456	/** Chunk of reserved bits. */
2457	uint32_t u3Reserved : 3;
2458	/** Available for use to system software. */
2459	uint32_t u3Available : 3;
2460	/** Physical Page number of the next level - Low Part. Don't use! */
2461	uint32_t u20PageNoLow : 20;
2462	/** Physical Page number of the next level - High Part. Don't use! */
2463	uint32_t u20PageNoHigh : 20;
2464	/** MBZ bits */
2465	uint32_t u11Reserved : 11;
2466	/** No Execute flag. */
2467	uint32_t u1NoExecute : 1;
2468	} X86PML4EBITS;
2469	#ifndef VBOX_FOR_DTRACE_LIB
2470	AssertCompileSize(X86PML4EBITS, 8);
2471	#endif
2472	/** Pointer to a page map level-4 entry. */
2473	typedef X86PML4EBITS *PX86PML4EBITS;
2474	/** Pointer to a const page map level-4 entry. */
2475	typedef const X86PML4EBITS *PCX86PML4EBITS;
2476
2477	/**
2478	* Page Map Level-4 Entry.
2479	*/
2480	typedef union X86PML4E
2481	{
2482	/** Unsigned integer view. */
2483	X86PGPAEUINT u;
2484	/** Normal view. */
2485	X86PML4EBITS n;
2486	/** 8 bit unsigned integer view. */
2487	uint8_t au8[8];
2488	/** 16 bit unsigned integer view. */
2489	uint16_t au16[4];
2490	/** 32 bit unsigned integer view. */
2491	uint32_t au32[2];
2492	} X86PML4E;
2493	#ifndef VBOX_FOR_DTRACE_LIB
2494	AssertCompileSize(X86PML4E, 8);
2495	#endif
2496	/** Pointer to a page map level-4 entry. */
2497	typedef X86PML4E *PX86PML4E;
2498	/** Pointer to a const page map level-4 entry. */
2499	typedef const X86PML4E *PCX86PML4E;
2500
2501
2502	/**
2503	* Page Map Level-4.
2504	*/
2505	typedef struct X86PML4
2506	{
2507	/** PDE Array. */
2508	X86PML4E a[X86_PG_PAE_ENTRIES];
2509	} X86PML4;
2510	#ifndef VBOX_FOR_DTRACE_LIB
2511	AssertCompileSize(X86PML4, 4096);
2512	#endif
2513	/** Pointer to a page map level-4. */
2514	typedef X86PML4 *PX86PML4;
2515	/** Pointer to a const page map level-4. */
2516	typedef const X86PML4 *PCX86PML4;
2517
2518	/** The page shift to get the PML4 index. */
2519	#define X86_PML4_SHIFT 39
2520	/** The PML4 index mask (apply to a shifted page address). */
2521	#define X86_PML4_MASK 0x1ff
2522
2523	/** @} */
2524
2525	/** @} */
2526
2527	/**
2528	* 32-bit protected mode FSTENV image.
2529	*/
2530	typedef struct X86FSTENV32P
2531	{
2532	uint16_t FCW;
2533	uint16_t padding1;
2534	uint16_t FSW;
2535	uint16_t padding2;
2536	uint16_t FTW;
2537	uint16_t padding3;
2538	uint32_t FPUIP;
2539	uint16_t FPUCS;
2540	uint16_t FOP;
2541	uint32_t FPUDP;
2542	uint16_t FPUDS;
2543	uint16_t padding4;
2544	} X86FSTENV32P;
2545	/** Pointer to a 32-bit protected mode FSTENV image. */
2546	typedef X86FSTENV32P *PX86FSTENV32P;
2547	/** Pointer to a const 32-bit protected mode FSTENV image. */
2548	typedef X86FSTENV32P const *PCX86FSTENV32P;
2549
2550
2551	/**
2552	* 80-bit MMX/FPU register type.
2553	*/
2554	typedef struct X86FPUMMX
2555	{
2556	uint8_t reg[10];
2557	} X86FPUMMX;
2558	#ifndef VBOX_FOR_DTRACE_LIB
2559	AssertCompileSize(X86FPUMMX, 10);
2560	#endif
2561	/** Pointer to a 80-bit MMX/FPU register type. */
2562	typedef X86FPUMMX *PX86FPUMMX;
2563	/** Pointer to a const 80-bit MMX/FPU register type. */
2564	typedef const X86FPUMMX *PCX86FPUMMX;
2565
2566	/** FPU (x87) register. */
2567	typedef union X86FPUREG
2568	{
2569	/** MMX view. */
2570	uint64_t mmx;
2571	/** FPU view - todo. */
2572	X86FPUMMX fpu;
2573	/** Extended precision floating point view. */
2574	RTFLOAT80U r80;
2575	/** Extended precision floating point view v2 */
2576	RTFLOAT80U2 r80Ex;
2577	/** 8-bit view. */
2578	uint8_t au8[16];
2579	/** 16-bit view. */
2580	uint16_t au16[8];
2581	/** 32-bit view. */
2582	uint32_t au32[4];
2583	/** 64-bit view. */
2584	uint64_t au64[2];
2585	/** 128-bit view. (yeah, very helpful) */
2586	uint128_t au128[1];
2587	} X86FPUREG;
2588	#ifndef VBOX_FOR_DTRACE_LIB
2589	AssertCompileSize(X86FPUREG, 16);
2590	#endif
2591	/** Pointer to a FPU register. */
2592	typedef X86FPUREG *PX86FPUREG;
2593	/** Pointer to a const FPU register. */
2594	typedef X86FPUREG const *PCX86FPUREG;
2595
2596	/**
2597	* XMM register union.
2598	*/
2599	typedef union X86XMMREG
2600	{
2601	/** XMM Register view. */
2602	uint128_t xmm;
2603	/** 8-bit view. */
2604	uint8_t au8[16];
2605	/** 16-bit view. */
2606	uint16_t au16[8];
2607	/** 32-bit view. */
2608	uint32_t au32[4];
2609	/** 64-bit view. */
2610	uint64_t au64[2];
2611	/** 128-bit view. (yeah, very helpful) */
2612	uint128_t au128[1];
2613	/** Confusing nested 128-bit union view (this is what xmm should've been). */
2614	RTUINT128U uXmm;
2615	} X86XMMREG;
2616	#ifndef VBOX_FOR_DTRACE_LIB
2617	AssertCompileSize(X86XMMREG, 16);
2618	#endif
2619	/** Pointer to an XMM register state. */
2620	typedef X86XMMREG *PX86XMMREG;
2621	/** Pointer to a const XMM register state. */
2622	typedef X86XMMREG const *PCX86XMMREG;
2623
2624	/**
2625	* YMM register union.
2626	*/
2627	typedef union X86YMMREG
2628	{
2629	/** 8-bit view. */
2630	uint8_t au8[32];
2631	/** 16-bit view. */
2632	uint16_t au16[16];
2633	/** 32-bit view. */
2634	uint32_t au32[8];
2635	/** 64-bit view. */
2636	uint64_t au64[4];
2637	/** 128-bit view. (yeah, very helpful) */
2638	uint128_t au128[2];
2639	/** XMM sub register view. */
2640	X86XMMREG aXmm[2];
2641	} X86YMMREG;
2642	#ifndef VBOX_FOR_DTRACE_LIB
2643	AssertCompileSize(X86YMMREG, 32);
2644	#endif
2645	/** Pointer to an YMM register state. */
2646	typedef X86YMMREG *PX86YMMREG;
2647	/** Pointer to a const YMM register state. */
2648	typedef X86YMMREG const *PCX86YMMREG;
2649
2650	/**
2651	* ZMM register union.
2652	*/
2653	typedef union X86ZMMREG
2654	{
2655	/** 8-bit view. */
2656	uint8_t au8[64];
2657	/** 16-bit view. */
2658	uint16_t au16[32];
2659	/** 32-bit view. */
2660	uint32_t au32[16];
2661	/** 64-bit view. */
2662	uint64_t au64[8];
2663	/** 128-bit view. (yeah, very helpful) */
2664	uint128_t au128[4];
2665	/** XMM sub register view. */
2666	X86XMMREG aXmm[4];
2667	/** YMM sub register view. */
2668	X86YMMREG aYmm[2];
2669	} X86ZMMREG;
2670	#ifndef VBOX_FOR_DTRACE_LIB
2671	AssertCompileSize(X86ZMMREG, 64);
2672	#endif
2673	/** Pointer to an ZMM register state. */
2674	typedef X86ZMMREG *PX86ZMMREG;
2675	/** Pointer to a const ZMM register state. */
2676	typedef X86ZMMREG const *PCX86ZMMREG;
2677
2678
2679	/**
2680	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2681	* @todo verify this...
2682	*/
2683	#pragma pack(1)
2684	typedef struct X86FPUSTATE
2685	{
2686	/** 0x00 - Control word. */
2687	uint16_t FCW;
2688	/** 0x02 - Alignment word */
2689	uint16_t Dummy1;
2690	/** 0x04 - Status word. */
2691	uint16_t FSW;
2692	/** 0x06 - Alignment word */
2693	uint16_t Dummy2;
2694	/** 0x08 - Tag word */
2695	uint16_t FTW;
2696	/** 0x0a - Alignment word */
2697	uint16_t Dummy3;
2698
2699	/** 0x0c - Instruction pointer. */
2700	uint32_t FPUIP;
2701	/** 0x10 - Code selector. */
2702	uint16_t CS;
2703	/** 0x12 - Opcode. */
2704	uint16_t FOP;
2705	/** 0x14 - FOO. */
2706	uint32_t FPUOO;
2707	/** 0x18 - FOS. */
2708	uint32_t FPUOS;
2709	/** 0x1c - FPU register. */
2710	X86FPUREG regs[8];
2711	} X86FPUSTATE;
2712	#pragma pack()
2713	/** Pointer to a FPU state. */
2714	typedef X86FPUSTATE *PX86FPUSTATE;
2715	/** Pointer to a const FPU state. */
2716	typedef const X86FPUSTATE *PCX86FPUSTATE;
2717
2718	/**
2719	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2720	*/
2721	#pragma pack(1)
2722	typedef struct X86FXSTATE
2723	{
2724	/** 0x00 - Control word. */
2725	uint16_t FCW;
2726	/** 0x02 - Status word. */
2727	uint16_t FSW;
2728	/** 0x04 - Tag word. (The upper byte is always zero.) */
2729	uint16_t FTW;
2730	/** 0x06 - Opcode. */
2731	uint16_t FOP;
2732	/** 0x08 - Instruction pointer. */
2733	uint32_t FPUIP;
2734	/** 0x0c - Code selector. */
2735	uint16_t CS;
2736	uint16_t Rsrvd1;
2737	/** 0x10 - Data pointer. */
2738	uint32_t FPUDP;
2739	/** 0x14 - Data segment */
2740	uint16_t DS;
2741	/** 0x16 */
2742	uint16_t Rsrvd2;
2743	/** 0x18 */
2744	uint32_t MXCSR;
2745	/** 0x1c */
2746	uint32_t MXCSR_MASK;
2747	/** 0x20 - FPU registers. */
2748	X86FPUREG aRegs[8];
2749	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2750	X86XMMREG aXMM[16];
2751	/* - offset 416 - */
2752	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2753	/* - offset 464 - Software usable reserved bits. */
2754	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2755	} X86FXSTATE;
2756	#pragma pack()
2757	/** Pointer to a FPU Extended state. */
2758	typedef X86FXSTATE *PX86FXSTATE;
2759	/** Pointer to a const FPU Extended state. */
2760	typedef const X86FXSTATE *PCX86FXSTATE;
2761
2762	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2763	* magic. Don't forget to update x86.mac if you change this! */
2764	#define X86_OFF_FXSTATE_RSVD 0x1d0
2765	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2766	* forget to update x86.mac if you change this!
2767	* @todo r=bird: This has nothing what-so-ever to do here.... */
2768	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2769	#ifndef VBOX_FOR_DTRACE_LIB
2770	AssertCompileSize(X86FXSTATE, 512);
2771	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2772	#endif
2773
2774	/** @name FPU status word flags.
2775	* @{ */
2776	/** Exception Flag: Invalid operation. */
2777	#define X86_FSW_IE RT_BIT_32(0)
2778	/** Exception Flag: Denormalized operand. */
2779	#define X86_FSW_DE RT_BIT_32(1)
2780	/** Exception Flag: Zero divide. */
2781	#define X86_FSW_ZE RT_BIT_32(2)
2782	/** Exception Flag: Overflow. */
2783	#define X86_FSW_OE RT_BIT_32(3)
2784	/** Exception Flag: Underflow. */
2785	#define X86_FSW_UE RT_BIT_32(4)
2786	/** Exception Flag: Precision. */
2787	#define X86_FSW_PE RT_BIT_32(5)
2788	/** Stack fault. */
2789	#define X86_FSW_SF RT_BIT_32(6)
2790	/** Error summary status. */
2791	#define X86_FSW_ES RT_BIT_32(7)
2792	/** Mask of exceptions flags, excluding the summary bit. */
2793	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2794	/** Mask of exceptions flags, including the summary bit. */
2795	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2796	/** Condition code 0. */
2797	#define X86_FSW_C0 RT_BIT_32(8)
2798	/** Condition code 1. */
2799	#define X86_FSW_C1 RT_BIT_32(9)
2800	/** Condition code 2. */
2801	#define X86_FSW_C2 RT_BIT_32(10)
2802	/** Top of the stack mask. */
2803	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2804	/** TOP shift value. */
2805	#define X86_FSW_TOP_SHIFT 11
2806	/** Mask for getting TOP value after shifting it right. */
2807	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2808	/** Get the TOP value. */
2809	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2810	/** Condition code 3. */
2811	#define X86_FSW_C3 RT_BIT_32(14)
2812	/** Mask of exceptions flags, including the summary bit. */
2813	#define X86_FSW_C_MASK UINT16_C(0x4700)
2814	/** FPU busy. */
2815	#define X86_FSW_B RT_BIT_32(15)
2816	/** @} */
2817
2818
2819	/** @name FPU control word flags.
2820	* @{ */
2821	/** Exception Mask: Invalid operation. */
2822	#define X86_FCW_IM RT_BIT_32(0)
2823	/** Exception Mask: Denormalized operand. */
2824	#define X86_FCW_DM RT_BIT_32(1)
2825	/** Exception Mask: Zero divide. */
2826	#define X86_FCW_ZM RT_BIT_32(2)
2827	/** Exception Mask: Overflow. */
2828	#define X86_FCW_OM RT_BIT_32(3)
2829	/** Exception Mask: Underflow. */
2830	#define X86_FCW_UM RT_BIT_32(4)
2831	/** Exception Mask: Precision. */
2832	#define X86_FCW_PM RT_BIT_32(5)
2833	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2834	* @remarks This includes reserved bit 6. */
2835	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2836	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2837	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2838	/** Precision control mask. */
2839	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2840	/** Precision control: 24-bit. */
2841	#define X86_FCW_PC_24 UINT16_C(0x0000)
2842	/** Precision control: Reserved. */
2843	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2844	/** Precision control: 53-bit. */
2845	#define X86_FCW_PC_53 UINT16_C(0x0200)
2846	/** Precision control: 64-bit. */
2847	#define X86_FCW_PC_64 UINT16_C(0x0300)
2848	/** Rounding control mask. */
2849	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2850	/** Rounding control: To nearest. */
2851	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2852	/** Rounding control: Down. */
2853	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2854	/** Rounding control: Up. */
2855	#define X86_FCW_RC_UP UINT16_C(0x0800)
2856	/** Rounding control: Towards zero. */
2857	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2858	/** Bits which should be zero, apparently. */
2859	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2860	/** @} */
2861
2862	/** @name SSE MXCSR
2863	* @{ */
2864	/** Exception Flag: Invalid operation. */
2865	#define X86_MXCSR_IE RT_BIT_32(0)
2866	/** Exception Flag: Denormalized operand. */
2867	#define X86_MXCSR_DE RT_BIT_32(1)
2868	/** Exception Flag: Zero divide. */
2869	#define X86_MXCSR_ZE RT_BIT_32(2)
2870	/** Exception Flag: Overflow. */
2871	#define X86_MXCSR_OE RT_BIT_32(3)
2872	/** Exception Flag: Underflow. */
2873	#define X86_MXCSR_UE RT_BIT_32(4)
2874	/** Exception Flag: Precision. */
2875	#define X86_MXCSR_PE RT_BIT_32(5)
2876
2877	/** Denormals are zero. */
2878	#define X86_MXCSR_DAZ RT_BIT_32(6)
2879
2880	/** Exception Mask: Invalid operation. */
2881	#define X86_MXCSR_IM RT_BIT_32(7)
2882	/** Exception Mask: Denormalized operand. */
2883	#define X86_MXCSR_DM RT_BIT_32(8)
2884	/** Exception Mask: Zero divide. */
2885	#define X86_MXCSR_ZM RT_BIT_32(9)
2886	/** Exception Mask: Overflow. */
2887	#define X86_MXCSR_OM RT_BIT_32(10)
2888	/** Exception Mask: Underflow. */
2889	#define X86_MXCSR_UM RT_BIT_32(11)
2890	/** Exception Mask: Precision. */
2891	#define X86_MXCSR_PM RT_BIT_32(12)
2892
2893	/** Rounding control mask. */
2894	#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
2895	/** Rounding control: To nearest. */
2896	#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
2897	/** Rounding control: Down. */
2898	#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
2899	/** Rounding control: Up. */
2900	#define X86_MXCSR_RC_UP UINT16_C(0x4000)
2901	/** Rounding control: Towards zero. */
2902	#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
2903
2904	/** Flush-to-zero for masked underflow. */
2905	#define X86_MXCSR_FZ RT_BIT_32(15)
2906
2907	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
2908	#define X86_MXCSR_MM RT_BIT_32(17)
2909	/** @} */
2910
2911	/**
2912	* XSAVE header.
2913	*/
2914	typedef struct X86XSAVEHDR
2915	{
2916	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
2917	uint64_t bmXState;
2918	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
2919	uint64_t bmXComp;
2920	/** Reserved for furture extensions, probably MBZ. */
2921	uint64_t au64Reserved[6];
2922	} X86XSAVEHDR;
2923	#ifndef VBOX_FOR_DTRACE_LIB
2924	AssertCompileSize(X86XSAVEHDR, 64);
2925	#endif
2926	/** Pointer to an XSAVE header. */
2927	typedef X86XSAVEHDR *PX86XSAVEHDR;
2928	/** Pointer to a const XSAVE header. */
2929	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
2930
2931
2932	/**
2933	* The high 128-bit YMM register state (XSAVE_C_YMM).
2934	* (The lower 128-bits being in X86FXSTATE.)
2935	*/
2936	typedef struct X86XSAVEYMMHI
2937	{
2938	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
2939	X86XMMREG aYmmHi[16];
2940	} X86XSAVEYMMHI;
2941	#ifndef VBOX_FOR_DTRACE_LIB
2942	AssertCompileSize(X86XSAVEYMMHI, 256);
2943	#endif
2944	/** Pointer to a high 128-bit YMM register state. */
2945	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
2946	/** Pointer to a const high 128-bit YMM register state. */
2947	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
2948
2949	/**
2950	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
2951	*/
2952	typedef struct X86XSAVEBNDREGS
2953	{
2954	/** Array of registers (BND0...BND3). */
2955	struct
2956	{
2957	/** Lower bound. */
2958	uint64_t uLowerBound;
2959	/** Upper bound. */
2960	uint64_t uUpperBound;
2961	} aRegs[4];
2962	} X86XSAVEBNDREGS;
2963	#ifndef VBOX_FOR_DTRACE_LIB
2964	AssertCompileSize(X86XSAVEBNDREGS, 64);
2965	#endif
2966	/** Pointer to a MPX bound register state. */
2967	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
2968	/** Pointer to a const MPX bound register state. */
2969	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
2970
2971	/**
2972	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
2973	*/
2974	typedef struct X86XSAVEBNDCFG
2975	{
2976	uint64_t fConfig;
2977	uint64_t fStatus;
2978	} X86XSAVEBNDCFG;
2979	#ifndef VBOX_FOR_DTRACE_LIB
2980	AssertCompileSize(X86XSAVEBNDCFG, 16);
2981	#endif
2982	/** Pointer to a MPX bound config and status register state. */
2983	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
2984	/** Pointer to a const MPX bound config and status register state. */
2985	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
2986
2987	/**
2988	* AVX-512 opmask state (XSAVE_C_OPMASK).
2989	*/
2990	typedef struct X86XSAVEOPMASK
2991	{
2992	/** The K0..K7 values. */
2993	uint64_t aKRegs[8];
2994	} X86XSAVEOPMASK;
2995	#ifndef VBOX_FOR_DTRACE_LIB
2996	AssertCompileSize(X86XSAVEOPMASK, 64);
2997	#endif
2998	/** Pointer to a AVX-512 opmask state. */
2999	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3000	/** Pointer to a const AVX-512 opmask state. */
3001	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3002
3003	/**
3004	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3005	*/
3006	typedef struct X86XSAVEZMMHI256
3007	{
3008	/** Upper 256-bits of ZMM0-15. */
3009	X86YMMREG aHi256Regs[16];
3010	} X86XSAVEZMMHI256;
3011	#ifndef VBOX_FOR_DTRACE_LIB
3012	AssertCompileSize(X86XSAVEZMMHI256, 512);
3013	#endif
3014	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3015	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3016	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3017	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3018
3019	/**
3020	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3021	*/
3022	typedef struct X86XSAVEZMM16HI
3023	{
3024	/** ZMM16 thru ZMM31. */
3025	X86ZMMREG aRegs[16];
3026	} X86XSAVEZMM16HI;
3027	#ifndef VBOX_FOR_DTRACE_LIB
3028	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3029	#endif
3030	/** Pointer to a state comprising ZMM16-32. */
3031	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3032	/** Pointer to a const state comprising ZMM16-32. */
3033	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3034
3035	/**
3036	* AMD Light weight profiling state (XSAVE_C_LWP).
3037	*
3038	* We probably won't play with this as AMD seems to be dropping from their "zen"
3039	* processor micro architecture.
3040	*/
3041	typedef struct X86XSAVELWP
3042	{
3043	/** Details when needed. */
3044	uint64_t auLater[128/8];
3045	} X86XSAVELWP;
3046	#ifndef VBOX_FOR_DTRACE_LIB
3047	AssertCompileSize(X86XSAVELWP, 128);
3048	#endif
3049
3050
3051	/**
3052	* x86 FPU/SSE/AVX/XXXX state.
3053	*
3054	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3055	* changes to this structure.
3056	*/
3057	typedef struct X86XSAVEAREA
3058	{
3059	/** The x87 and SSE region (or legacy region if you like). */
3060	X86FXSTATE x87;
3061	/** The XSAVE header. */
3062	X86XSAVEHDR Hdr;
3063	/** Beyond the header, there isn't really a fixed layout, but we can
3064	generally assume the YMM (AVX) register extensions are present and
3065	follows immediately. */
3066	union
3067	{
3068	/** The high 128-bit AVX registers for easy access by IEM.
3069	* @note This ASSUMES they will always be here... */
3070	X86XSAVEYMMHI YmmHi;
3071
3072	/** This is a typical layout on intel CPUs (good for debuggers). */
3073	struct
3074	{
3075	X86XSAVEYMMHI YmmHi;
3076	X86XSAVEBNDREGS BndRegs;
3077	X86XSAVEBNDCFG BndCfg;
3078	uint8_t abFudgeToMatchDocs[0xB0];
3079	X86XSAVEOPMASK Opmask;
3080	X86XSAVEZMMHI256 ZmmHi256;
3081	X86XSAVEZMM16HI Zmm16Hi;
3082	} Intel;
3083
3084	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3085	struct
3086	{
3087	X86XSAVEYMMHI YmmHi;
3088	X86XSAVELWP Lwp;
3089	} AmdBd;
3090
3091	/** To enbling static deployments that have a reasonable chance of working for
3092	* the next 3-6 CPU generations without running short on space, we allocate a
3093	* lot of extra space here, making the structure a round 8KB in size. This
3094	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3095	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3096	uint8_t ab[8192 - 512 - 64];
3097	} u;
3098	} X86XSAVEAREA;
3099	#ifndef VBOX_FOR_DTRACE_LIB
3100	AssertCompileSize(X86XSAVEAREA, 8192);
3101	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3102	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3103	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3104	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3105	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3106	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3107	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3108	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3109	#endif
3110	/** Pointer to a XSAVE area. */
3111	typedef X86XSAVEAREA *PX86XSAVEAREA;
3112	/** Pointer to a const XSAVE area. */
3113	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3114
3115
3116	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3117	* @{ */
3118	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3119	#define XSAVE_C_X87_BIT 0
3120	/** Bit 0 - x87 - Legacy FPU state. */
3121	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3122	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3123	#define XSAVE_C_SSE_BIT 1
3124	/** Bit 1 - SSE - 128-bit SSE state. */
3125	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3126	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3127	#define XSAVE_C_YMM_BIT 2
3128	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3129	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3130	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3131	#define XSAVE_C_BNDREGS_BIT 3
3132	/** Bit 3 - BNDREGS - MPX bound register state. */
3133	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3134	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3135	#define XSAVE_C_BNDCSR_BIT 4
3136	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3137	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3138	/** Bit 5 - Opmask - opmask state (bit number). */
3139	#define XSAVE_C_OPMASK_BIT 5
3140	/** Bit 5 - Opmask - opmask state. */
3141	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3142	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3143	#define XSAVE_C_ZMM_HI256_BIT 6
3144	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3145	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3146	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3147	#define XSAVE_C_ZMM_16HI_BIT 7
3148	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3149	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3150	/** Bit 9 - PKRU - Protection-key state (bit number). */
3151	#define XSAVE_C_PKRU_BIT 9
3152	/** Bit 9 - PKRU - Protection-key state. */
3153	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3154	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3155	#define XSAVE_C_LWP_BIT 62
3156	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3157	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3158	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3159	#define XSAVE_C_X_BIT 63
3160	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3161	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3162	/** @} */
3163
3164
3165
3166	/** @name Selector Descriptor
3167	* @{
3168	*/
3169
3170	#ifndef VBOX_FOR_DTRACE_LIB
3171	/**
3172	* Descriptor attributes (as seen by VT-x).
3173	*/
3174	typedef struct X86DESCATTRBITS
3175	{
3176	/** 00 - Segment Type. */
3177	unsigned u4Type : 4;
3178	/** 04 - Descriptor Type. System(=0) or code/data selector */
3179	unsigned u1DescType : 1;
3180	/** 05 - Descriptor Privilege level. */
3181	unsigned u2Dpl : 2;
3182	/** 07 - Flags selector present(=1) or not. */
3183	unsigned u1Present : 1;
3184	/** 08 - Segment limit 16-19. */
3185	unsigned u4LimitHigh : 4;
3186	/** 0c - Available for system software. */
3187	unsigned u1Available : 1;
3188	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3189	unsigned u1Long : 1;
3190	/** 0e - This flags meaning depends on the segment type. Try make sense out
3191	* of the intel manual yourself. */
3192	unsigned u1DefBig : 1;
3193	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3194	* clear byte. */
3195	unsigned u1Granularity : 1;
3196	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3197	unsigned u1Unusable : 1;
3198	} X86DESCATTRBITS;
3199	#endif /* !VBOX_FOR_DTRACE_LIB */
3200
3201	/** @name X86DESCATTR masks
3202	* @{ */
3203	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3204	#define X86DESCATTR_DT UINT32_C(0x00000010)
3205	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3206	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3207	#define X86DESCATTR_P UINT32_C(0x00000080)
3208	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3209	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3210	#define X86DESCATTR_L UINT32_C(0x00002000)
3211	#define X86DESCATTR_D UINT32_C(0x00004000)
3212	#define X86DESCATTR_G UINT32_C(0x00008000)
3213	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3214	/** @} */
3215
3216	#pragma pack(1)
3217	typedef union X86DESCATTR
3218	{
3219	/** Unsigned integer view. */
3220	uint32_t u;
3221	#ifndef VBOX_FOR_DTRACE_LIB
3222	/** Normal view. */
3223	X86DESCATTRBITS n;
3224	#endif
3225	} X86DESCATTR;
3226	#pragma pack()
3227	/** Pointer to descriptor attributes. */
3228	typedef X86DESCATTR *PX86DESCATTR;
3229	/** Pointer to const descriptor attributes. */
3230	typedef const X86DESCATTR *PCX86DESCATTR;
3231
3232	#ifndef VBOX_FOR_DTRACE_LIB
3233
3234	/**
3235	* Generic descriptor table entry
3236	*/
3237	#pragma pack(1)
3238	typedef struct X86DESCGENERIC
3239	{
3240	/** 00 - Limit - Low word. */
3241	unsigned u16LimitLow : 16;
3242	/** 10 - Base address - low word.
3243	* Don't try set this to 24 because MSC is doing stupid things then. */
3244	unsigned u16BaseLow : 16;
3245	/** 20 - Base address - first 8 bits of high word. */
3246	unsigned u8BaseHigh1 : 8;
3247	/** 28 - Segment Type. */
3248	unsigned u4Type : 4;
3249	/** 2c - Descriptor Type. System(=0) or code/data selector */
3250	unsigned u1DescType : 1;
3251	/** 2d - Descriptor Privilege level. */
3252	unsigned u2Dpl : 2;
3253	/** 2f - Flags selector present(=1) or not. */
3254	unsigned u1Present : 1;
3255	/** 30 - Segment limit 16-19. */
3256	unsigned u4LimitHigh : 4;
3257	/** 34 - Available for system software. */
3258	unsigned u1Available : 1;
3259	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3260	unsigned u1Long : 1;
3261	/** 36 - This flags meaning depends on the segment type. Try make sense out
3262	* of the intel manual yourself. */
3263	unsigned u1DefBig : 1;
3264	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3265	* clear byte. */
3266	unsigned u1Granularity : 1;
3267	/** 38 - Base address - highest 8 bits. */
3268	unsigned u8BaseHigh2 : 8;
3269	} X86DESCGENERIC;
3270	#pragma pack()
3271	/** Pointer to a generic descriptor entry. */
3272	typedef X86DESCGENERIC *PX86DESCGENERIC;
3273	/** Pointer to a const generic descriptor entry. */
3274	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3275
3276	/** @name Bit offsets of X86DESCGENERIC members.
3277	* @{*/
3278	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3279	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3280	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3281	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3282	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3283	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3284	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3285	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3286	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3287	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3288	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3289	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3290	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3291	/** @} */
3292
3293
3294	/** @name LAR mask
3295	* @{ */
3296	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3297	#define X86LAR_F_DT UINT16_C( 0x1000)
3298	#define X86LAR_F_DPL UINT16_C( 0x6000)
3299	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3300	#define X86LAR_F_P UINT16_C( 0x8000)
3301	#define X86LAR_F_AVL UINT32_C(0x00100000)
3302	#define X86LAR_F_L UINT32_C(0x00200000)
3303	#define X86LAR_F_D UINT32_C(0x00400000)
3304	#define X86LAR_F_G UINT32_C(0x00800000)
3305	/** @} */
3306
3307
3308	/**
3309	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3310	*/
3311	typedef struct X86DESCGATE
3312	{
3313	/** 00 - Target code segment offset - Low word.
3314	* Ignored if task-gate. */
3315	unsigned u16OffsetLow : 16;
3316	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3317	* TSS selector if task-gate. */
3318	unsigned u16Sel : 16;
3319	/** 20 - Number of parameters for a call-gate.
3320	* Ignored if interrupt-, trap- or task-gate. */
3321	unsigned u5ParmCount : 5;
3322	/** 25 - Reserved / ignored. */
3323	unsigned u3Reserved : 3;
3324	/** 28 - Segment Type. */
3325	unsigned u4Type : 4;
3326	/** 2c - Descriptor Type (0 = system). */
3327	unsigned u1DescType : 1;
3328	/** 2d - Descriptor Privilege level. */
3329	unsigned u2Dpl : 2;
3330	/** 2f - Flags selector present(=1) or not. */
3331	unsigned u1Present : 1;
3332	/** 30 - Target code segment offset - High word.
3333	* Ignored if task-gate. */
3334	unsigned u16OffsetHigh : 16;
3335	} X86DESCGATE;
3336	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3337	typedef X86DESCGATE *PX86DESCGATE;
3338	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3339	typedef const X86DESCGATE *PCX86DESCGATE;
3340
3341	#endif /* VBOX_FOR_DTRACE_LIB */
3342
3343	/**
3344	* Descriptor table entry.
3345	*/
3346	#pragma pack(1)
3347	typedef union X86DESC
3348	{
3349	#ifndef VBOX_FOR_DTRACE_LIB
3350	/** Generic descriptor view. */
3351	X86DESCGENERIC Gen;
3352	/** Gate descriptor view. */
3353	X86DESCGATE Gate;
3354	#endif
3355
3356	/** 8 bit unsigned integer view. */
3357	uint8_t au8[8];
3358	/** 16 bit unsigned integer view. */
3359	uint16_t au16[4];
3360	/** 32 bit unsigned integer view. */
3361	uint32_t au32[2];
3362	/** 64 bit unsigned integer view. */
3363	uint64_t au64[1];
3364	/** Unsigned integer view. */
3365	uint64_t u;
3366	} X86DESC;
3367	#ifndef VBOX_FOR_DTRACE_LIB
3368	AssertCompileSize(X86DESC, 8);
3369	#endif
3370	#pragma pack()
3371	/** Pointer to descriptor table entry. */
3372	typedef X86DESC *PX86DESC;
3373	/** Pointer to const descriptor table entry. */
3374	typedef const X86DESC *PCX86DESC;
3375
3376	/** @def X86DESC_BASE
3377	* Return the base address of a descriptor.
3378	*/
3379	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3380	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3381	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3382	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3383
3384	/** @def X86DESC_LIMIT
3385	* Return the limit of a descriptor.
3386	*/
3387	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3388	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3389	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3390
3391	/** @def X86DESC_LIMIT_G
3392	* Return the limit of a descriptor with the granularity bit taken into account.
3393	* @returns Selector limit (uint32_t).
3394	* @param a_pDesc Pointer to the descriptor.
3395	*/
3396	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3397	( (a_pDesc)->Gen.u1Granularity \
3398	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3399	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3400	)
3401
3402	/** @def X86DESC_GET_HID_ATTR
3403	* Get the descriptor attributes for the hidden register.
3404	*/
3405	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3406	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3407
3408	#ifndef VBOX_FOR_DTRACE_LIB
3409
3410	/**
3411	* 64 bits generic descriptor table entry
3412	* Note: most of these bits have no meaning in long mode.
3413	*/
3414	#pragma pack(1)
3415	typedef struct X86DESC64GENERIC
3416	{
3417	/** Limit - Low word - IGNORED. */
3418	uint32_t u16LimitLow : 16;
3419	/** Base address - low word. - IGNORED
3420	* Don't try set this to 24 because MSC is doing stupid things then. */
3421	uint32_t u16BaseLow : 16;
3422	/** Base address - first 8 bits of high word. - IGNORED */
3423	uint32_t u8BaseHigh1 : 8;
3424	/** Segment Type. */
3425	uint32_t u4Type : 4;
3426	/** Descriptor Type. System(=0) or code/data selector */
3427	uint32_t u1DescType : 1;
3428	/** Descriptor Privilege level. */
3429	uint32_t u2Dpl : 2;
3430	/** Flags selector present(=1) or not. */
3431	uint32_t u1Present : 1;
3432	/** Segment limit 16-19. - IGNORED */
3433	uint32_t u4LimitHigh : 4;
3434	/** Available for system software. - IGNORED */
3435	uint32_t u1Available : 1;
3436	/** Long mode flag. */
3437	uint32_t u1Long : 1;
3438	/** This flags meaning depends on the segment type. Try make sense out
3439	* of the intel manual yourself. */
3440	uint32_t u1DefBig : 1;
3441	/** Granularity of the limit. If set 4KB granularity is used, if
3442	* clear byte. - IGNORED */
3443	uint32_t u1Granularity : 1;
3444	/** Base address - highest 8 bits. - IGNORED */
3445	uint32_t u8BaseHigh2 : 8;
3446	/** Base address - bits 63-32. */
3447	uint32_t u32BaseHigh3 : 32;
3448	uint32_t u8Reserved : 8;
3449	uint32_t u5Zeros : 5;
3450	uint32_t u19Reserved : 19;
3451	} X86DESC64GENERIC;
3452	#pragma pack()
3453	/** Pointer to a generic descriptor entry. */
3454	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3455	/** Pointer to a const generic descriptor entry. */
3456	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3457
3458	/**
3459	* System descriptor table entry (64 bits)
3460	*
3461	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3462	*/
3463	#pragma pack(1)
3464	typedef struct X86DESC64SYSTEM
3465	{
3466	/** Limit - Low word. */
3467	uint32_t u16LimitLow : 16;
3468	/** Base address - low word.
3469	* Don't try set this to 24 because MSC is doing stupid things then. */
3470	uint32_t u16BaseLow : 16;
3471	/** Base address - first 8 bits of high word. */
3472	uint32_t u8BaseHigh1 : 8;
3473	/** Segment Type. */
3474	uint32_t u4Type : 4;
3475	/** Descriptor Type. System(=0) or code/data selector */
3476	uint32_t u1DescType : 1;
3477	/** Descriptor Privilege level. */
3478	uint32_t u2Dpl : 2;
3479	/** Flags selector present(=1) or not. */
3480	uint32_t u1Present : 1;
3481	/** Segment limit 16-19. */
3482	uint32_t u4LimitHigh : 4;
3483	/** Available for system software. */
3484	uint32_t u1Available : 1;
3485	/** Reserved - 0. */
3486	uint32_t u1Reserved : 1;
3487	/** This flags meaning depends on the segment type. Try make sense out
3488	* of the intel manual yourself. */
3489	uint32_t u1DefBig : 1;
3490	/** Granularity of the limit. If set 4KB granularity is used, if
3491	* clear byte. */
3492	uint32_t u1Granularity : 1;
3493	/** Base address - bits 31-24. */
3494	uint32_t u8BaseHigh2 : 8;
3495	/** Base address - bits 63-32. */
3496	uint32_t u32BaseHigh3 : 32;
3497	uint32_t u8Reserved : 8;
3498	uint32_t u5Zeros : 5;
3499	uint32_t u19Reserved : 19;
3500	} X86DESC64SYSTEM;
3501	#pragma pack()
3502	/** Pointer to a system descriptor entry. */
3503	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3504	/** Pointer to a const system descriptor entry. */
3505	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3506
3507	/**
3508	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3509	*/
3510	typedef struct X86DESC64GATE
3511	{
3512	/** Target code segment offset - Low word. */
3513	uint32_t u16OffsetLow : 16;
3514	/** Target code segment selector. */
3515	uint32_t u16Sel : 16;
3516	/** Interrupt stack table for interrupt- and trap-gates.
3517	* Ignored by call-gates. */
3518	uint32_t u3IST : 3;
3519	/** Reserved / ignored. */
3520	uint32_t u5Reserved : 5;
3521	/** Segment Type. */
3522	uint32_t u4Type : 4;
3523	/** Descriptor Type (0 = system). */
3524	uint32_t u1DescType : 1;
3525	/** Descriptor Privilege level. */
3526	uint32_t u2Dpl : 2;
3527	/** Flags selector present(=1) or not. */
3528	uint32_t u1Present : 1;
3529	/** Target code segment offset - High word.
3530	* Ignored if task-gate. */
3531	uint32_t u16OffsetHigh : 16;
3532	/** Target code segment offset - Top dword.
3533	* Ignored if task-gate. */
3534	uint32_t u32OffsetTop : 32;
3535	/** Reserved / ignored / must be zero.
3536	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3537	uint32_t u32Reserved : 32;
3538	} X86DESC64GATE;
3539	AssertCompileSize(X86DESC64GATE, 16);
3540	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3541	typedef X86DESC64GATE *PX86DESC64GATE;
3542	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3543	typedef const X86DESC64GATE *PCX86DESC64GATE;
3544
3545	#endif /* VBOX_FOR_DTRACE_LIB */
3546
3547	/**
3548	* Descriptor table entry.
3549	*/
3550	#pragma pack(1)
3551	typedef union X86DESC64
3552	{
3553	#ifndef VBOX_FOR_DTRACE_LIB
3554	/** Generic descriptor view. */
3555	X86DESC64GENERIC Gen;
3556	/** System descriptor view. */
3557	X86DESC64SYSTEM System;
3558	/** Gate descriptor view. */
3559	X86DESC64GATE Gate;
3560	#endif
3561
3562	/** 8 bit unsigned integer view. */
3563	uint8_t au8[16];
3564	/** 16 bit unsigned integer view. */
3565	uint16_t au16[8];
3566	/** 32 bit unsigned integer view. */
3567	uint32_t au32[4];
3568	/** 64 bit unsigned integer view. */
3569	uint64_t au64[2];
3570	} X86DESC64;
3571	#ifndef VBOX_FOR_DTRACE_LIB
3572	AssertCompileSize(X86DESC64, 16);
3573	#endif
3574	#pragma pack()
3575	/** Pointer to descriptor table entry. */
3576	typedef X86DESC64 *PX86DESC64;
3577	/** Pointer to const descriptor table entry. */
3578	typedef const X86DESC64 *PCX86DESC64;
3579
3580	/** @def X86DESC64_BASE
3581	* Return the base of a 64-bit descriptor.
3582	*/
3583	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3584	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3585	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3586	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3587	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3588
3589
3590
3591	/** @name Host system descriptor table entry - Use with care!
3592	* @{ */
3593	/** Host system descriptor table entry. */
3594	#if HC_ARCH_BITS == 64
3595	typedef X86DESC64 X86DESCHC;
3596	#else
3597	typedef X86DESC X86DESCHC;
3598	#endif
3599	/** Pointer to a host system descriptor table entry. */
3600	#if HC_ARCH_BITS == 64
3601	typedef PX86DESC64 PX86DESCHC;
3602	#else
3603	typedef PX86DESC PX86DESCHC;
3604	#endif
3605	/** Pointer to a const host system descriptor table entry. */
3606	#if HC_ARCH_BITS == 64
3607	typedef PCX86DESC64 PCX86DESCHC;
3608	#else
3609	typedef PCX86DESC PCX86DESCHC;
3610	#endif
3611	/** @} */
3612
3613
3614	/** @name Selector Descriptor Types.
3615	* @{
3616	*/
3617
3618	/** @name Non-System Selector Types.
3619	* @{ */
3620	/** Code(=set)/Data(=clear) bit. */
3621	#define X86_SEL_TYPE_CODE 8
3622	/** Memory(=set)/System(=clear) bit. */
3623	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3624	/** Accessed bit. */
3625	#define X86_SEL_TYPE_ACCESSED 1
3626	/** Expand down bit (for data selectors only). */
3627	#define X86_SEL_TYPE_DOWN 4
3628	/** Conforming bit (for code selectors only). */
3629	#define X86_SEL_TYPE_CONF 4
3630	/** Write bit (for data selectors only). */
3631	#define X86_SEL_TYPE_WRITE 2
3632	/** Read bit (for code selectors only). */
3633	#define X86_SEL_TYPE_READ 2
3634	/** The bit number of the code segment read bit (relative to u4Type). */
3635	#define X86_SEL_TYPE_READ_BIT 1
3636
3637	/** Read only selector type. */
3638	#define X86_SEL_TYPE_RO 0
3639	/** Accessed read only selector type. */
3640	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3641	/** Read write selector type. */
3642	#define X86_SEL_TYPE_RW 2
3643	/** Accessed read write selector type. */
3644	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3645	/** Expand down read only selector type. */
3646	#define X86_SEL_TYPE_RO_DOWN 4
3647	/** Accessed expand down read only selector type. */
3648	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3649	/** Expand down read write selector type. */
3650	#define X86_SEL_TYPE_RW_DOWN 6
3651	/** Accessed expand down read write selector type. */
3652	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3653	/** Execute only selector type. */
3654	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3655	/** Accessed execute only selector type. */
3656	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3657	/** Execute and read selector type. */
3658	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3659	/** Accessed execute and read selector type. */
3660	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3661	/** Conforming execute only selector type. */
3662	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3663	/** Accessed Conforming execute only selector type. */
3664	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3665	/** Conforming execute and write selector type. */
3666	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3667	/** Accessed Conforming execute and write selector type. */
3668	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3669	/** @} */
3670
3671
3672	/** @name System Selector Types.
3673	* @{ */
3674	/** The TSS busy bit mask. */
3675	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3676
3677	/** Undefined system selector type. */
3678	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3679	/** 286 TSS selector. */
3680	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3681	/** LDT selector. */
3682	#define X86_SEL_TYPE_SYS_LDT 2
3683	/** 286 TSS selector - Busy. */
3684	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3685	/** 286 Callgate selector. */
3686	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3687	/** Taskgate selector. */
3688	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3689	/** 286 Interrupt gate selector. */
3690	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3691	/** 286 Trapgate selector. */
3692	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3693	/** Undefined system selector. */
3694	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3695	/** 386 TSS selector. */
3696	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3697	/** Undefined system selector. */
3698	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3699	/** 386 TSS selector - Busy. */
3700	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3701	/** 386 Callgate selector. */
3702	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3703	/** Undefined system selector. */
3704	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3705	/** 386 Interruptgate selector. */
3706	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3707	/** 386 Trapgate selector. */
3708	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3709	/** @} */
3710
3711	/** @name AMD64 System Selector Types.
3712	* @{ */
3713	/** LDT selector. */
3714	#define AMD64_SEL_TYPE_SYS_LDT 2
3715	/** TSS selector - Busy. */
3716	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3717	/** TSS selector - Busy. */
3718	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3719	/** Callgate selector. */
3720	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3721	/** Interruptgate selector. */
3722	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3723	/** Trapgate selector. */
3724	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3725	/** @} */
3726
3727	/** @} */
3728
3729
3730	/** @name Descriptor Table Entry Flag Masks.
3731	* These are for the 2nd 32-bit word of a descriptor.
3732	* @{ */
3733	/** Bits 8-11 - TYPE - Descriptor type mask. */
3734	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3735	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3736	#define X86_DESC_S RT_BIT_32(12)
3737	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3738	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
3739	/** Bit 15 - P - Present. */
3740	#define X86_DESC_P RT_BIT_32(15)
3741	/** Bit 20 - AVL - Available for system software. */
3742	#define X86_DESC_AVL RT_BIT_32(20)
3743	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3744	#define X86_DESC_DB RT_BIT_32(22)
3745	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3746	* used, if clear byte. */
3747	#define X86_DESC_G RT_BIT_32(23)
3748	/** @} */
3749
3750	/** @} */
3751
3752
3753	/** @name Task Segments.
3754	* @{
3755	*/
3756
3757	/**
3758	* The minimum TSS descriptor limit for 286 tasks.
3759	*/
3760	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3761
3762	/**
3763	* The minimum TSS descriptor segment limit for 386 tasks.
3764	*/
3765	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3766
3767	/**
3768	* 16-bit Task Segment (TSS).
3769	*/
3770	#pragma pack(1)
3771	typedef struct X86TSS16
3772	{
3773	/** Back link to previous task. (static) */
3774	RTSEL selPrev;
3775	/** Ring-0 stack pointer. (static) */
3776	uint16_t sp0;
3777	/** Ring-0 stack segment. (static) */
3778	RTSEL ss0;
3779	/** Ring-1 stack pointer. (static) */
3780	uint16_t sp1;
3781	/** Ring-1 stack segment. (static) */
3782	RTSEL ss1;
3783	/** Ring-2 stack pointer. (static) */
3784	uint16_t sp2;
3785	/** Ring-2 stack segment. (static) */
3786	RTSEL ss2;
3787	/** IP before task switch. */
3788	uint16_t ip;
3789	/** FLAGS before task switch. */
3790	uint16_t flags;
3791	/** AX before task switch. */
3792	uint16_t ax;
3793	/** CX before task switch. */
3794	uint16_t cx;
3795	/** DX before task switch. */
3796	uint16_t dx;
3797	/** BX before task switch. */
3798	uint16_t bx;
3799	/** SP before task switch. */
3800	uint16_t sp;
3801	/** BP before task switch. */
3802	uint16_t bp;
3803	/** SI before task switch. */
3804	uint16_t si;
3805	/** DI before task switch. */
3806	uint16_t di;
3807	/** ES before task switch. */
3808	RTSEL es;
3809	/** CS before task switch. */
3810	RTSEL cs;
3811	/** SS before task switch. */
3812	RTSEL ss;
3813	/** DS before task switch. */
3814	RTSEL ds;
3815	/** LDTR before task switch. */
3816	RTSEL selLdt;
3817	} X86TSS16;
3818	#ifndef VBOX_FOR_DTRACE_LIB
3819	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3820	#endif
3821	#pragma pack()
3822	/** Pointer to a 16-bit task segment. */
3823	typedef X86TSS16 *PX86TSS16;
3824	/** Pointer to a const 16-bit task segment. */
3825	typedef const X86TSS16 *PCX86TSS16;
3826
3827
3828	/**
3829	* 32-bit Task Segment (TSS).
3830	*/
3831	#pragma pack(1)
3832	typedef struct X86TSS32
3833	{
3834	/** Back link to previous task. (static) */
3835	RTSEL selPrev;
3836	uint16_t padding1;
3837	/** Ring-0 stack pointer. (static) */
3838	uint32_t esp0;
3839	/** Ring-0 stack segment. (static) */
3840	RTSEL ss0;
3841	uint16_t padding_ss0;
3842	/** Ring-1 stack pointer. (static) */
3843	uint32_t esp1;
3844	/** Ring-1 stack segment. (static) */
3845	RTSEL ss1;
3846	uint16_t padding_ss1;
3847	/** Ring-2 stack pointer. (static) */
3848	uint32_t esp2;
3849	/** Ring-2 stack segment. (static) */
3850	RTSEL ss2;
3851	uint16_t padding_ss2;
3852	/** Page directory for the task. (static) */
3853	uint32_t cr3;
3854	/** EIP before task switch. */
3855	uint32_t eip;
3856	/** EFLAGS before task switch. */
3857	uint32_t eflags;
3858	/** EAX before task switch. */
3859	uint32_t eax;
3860	/** ECX before task switch. */
3861	uint32_t ecx;
3862	/** EDX before task switch. */
3863	uint32_t edx;
3864	/** EBX before task switch. */
3865	uint32_t ebx;
3866	/** ESP before task switch. */
3867	uint32_t esp;
3868	/** EBP before task switch. */
3869	uint32_t ebp;
3870	/** ESI before task switch. */
3871	uint32_t esi;
3872	/** EDI before task switch. */
3873	uint32_t edi;
3874	/** ES before task switch. */
3875	RTSEL es;
3876	uint16_t padding_es;
3877	/** CS before task switch. */
3878	RTSEL cs;
3879	uint16_t padding_cs;
3880	/** SS before task switch. */
3881	RTSEL ss;
3882	uint16_t padding_ss;
3883	/** DS before task switch. */
3884	RTSEL ds;
3885	uint16_t padding_ds;
3886	/** FS before task switch. */
3887	RTSEL fs;
3888	uint16_t padding_fs;
3889	/** GS before task switch. */
3890	RTSEL gs;
3891	uint16_t padding_gs;
3892	/** LDTR before task switch. */
3893	RTSEL selLdt;
3894	uint16_t padding_ldt;
3895	/** Debug trap flag */
3896	uint16_t fDebugTrap;
3897	/** Offset relative to the TSS of the start of the I/O Bitmap
3898	* and the end of the interrupt redirection bitmap. */
3899	uint16_t offIoBitmap;
3900	} X86TSS32;
3901	#pragma pack()
3902	/** Pointer to task segment. */
3903	typedef X86TSS32 *PX86TSS32;
3904	/** Pointer to const task segment. */
3905	typedef const X86TSS32 *PCX86TSS32;
3906	#ifndef VBOX_FOR_DTRACE_LIB
3907	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3908	AssertCompileMemberOffset(X86TSS32, cr3, 28);
3909	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
3910	#endif
3911
3912	/**
3913	* 64-bit Task segment.
3914	*/
3915	#pragma pack(1)
3916	typedef struct X86TSS64
3917	{
3918	/** Reserved. */
3919	uint32_t u32Reserved;
3920	/** Ring-0 stack pointer. (static) */
3921	uint64_t rsp0;
3922	/** Ring-1 stack pointer. (static) */
3923	uint64_t rsp1;
3924	/** Ring-2 stack pointer. (static) */
3925	uint64_t rsp2;
3926	/** Reserved. */
3927	uint32_t u32Reserved2[2];
3928	/* IST */
3929	uint64_t ist1;
3930	uint64_t ist2;
3931	uint64_t ist3;
3932	uint64_t ist4;
3933	uint64_t ist5;
3934	uint64_t ist6;
3935	uint64_t ist7;
3936	/* Reserved. */
3937	uint16_t u16Reserved[5];
3938	/** Offset relative to the TSS of the start of the I/O Bitmap
3939	* and the end of the interrupt redirection bitmap. */
3940	uint16_t offIoBitmap;
3941	} X86TSS64;
3942	#pragma pack()
3943	/** Pointer to a 64-bit task segment. */
3944	typedef X86TSS64 *PX86TSS64;
3945	/** Pointer to a const 64-bit task segment. */
3946	typedef const X86TSS64 *PCX86TSS64;
3947	#ifndef VBOX_FOR_DTRACE_LIB
3948	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3949	#endif
3950
3951	/** @} */
3952
3953
3954	/** @name Selectors.
3955	* @{
3956	*/
3957
3958	/**
3959	* The shift used to convert a selector from and to index an index (C).
3960	*/
3961	#define X86_SEL_SHIFT 3
3962
3963	/**
3964	* The mask used to mask off the table indicator and RPL of an selector.
3965	*/
3966	#define X86_SEL_MASK 0xfff8U
3967
3968	/**
3969	* The mask used to mask off the RPL of an selector.
3970	* This is suitable for checking for NULL selectors.
3971	*/
3972	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3973
3974	/**
3975	* The bit indicating that a selector is in the LDT and not in the GDT.
3976	*/
3977	#define X86_SEL_LDT 0x0004U
3978
3979	/**
3980	* The bit mask for getting the RPL of a selector.
3981	*/
3982	#define X86_SEL_RPL 0x0003U
3983
3984	/**
3985	* The mask covering both RPL and LDT.
3986	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3987	* checks.
3988	*/
3989	#define X86_SEL_RPL_LDT 0x0007U
3990
3991	/** @} */
3992
3993
3994	/**
3995	* x86 Exceptions/Faults/Traps.
3996	*/
3997	typedef enum X86XCPT
3998	{
3999	/** \#DE - Divide error. */
4000	X86_XCPT_DE = 0x00,
4001	/** \#DB - Debug event (single step, DRx, ..) */
4002	X86_XCPT_DB = 0x01,
4003	/** NMI - Non-Maskable Interrupt */
4004	X86_XCPT_NMI = 0x02,
4005	/** \#BP - Breakpoint (INT3). */
4006	X86_XCPT_BP = 0x03,
4007	/** \#OF - Overflow (INTO). */
4008	X86_XCPT_OF = 0x04,
4009	/** \#BR - Bound range exceeded (BOUND). */
4010	X86_XCPT_BR = 0x05,
4011	/** \#UD - Undefined opcode. */
4012	X86_XCPT_UD = 0x06,
4013	/** \#NM - Device not available (math coprocessor device). */
4014	X86_XCPT_NM = 0x07,
4015	/** \#DF - Double fault. */
4016	X86_XCPT_DF = 0x08,
4017	/** ??? - Coprocessor segment overrun (obsolete). */
4018	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4019	/** \#TS - Taskswitch (TSS). */
4020	X86_XCPT_TS = 0x0a,
4021	/** \#NP - Segment no present. */
4022	X86_XCPT_NP = 0x0b,
4023	/** \#SS - Stack segment fault. */
4024	X86_XCPT_SS = 0x0c,
4025	/** \#GP - General protection fault. */
4026	X86_XCPT_GP = 0x0d,
4027	/** \#PF - Page fault. */
4028	X86_XCPT_PF = 0x0e,
4029	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4030	/** \#MF - Math fault (FPU). */
4031	X86_XCPT_MF = 0x10,
4032	/** \#AC - Alignment check. */
4033	X86_XCPT_AC = 0x11,
4034	/** \#MC - Machine check. */
4035	X86_XCPT_MC = 0x12,
4036	/** \#XF - SIMD Floating-Pointer Exception. */
4037	X86_XCPT_XF = 0x13,
4038	/** \#VE - Virtualization Exception. */
4039	X86_XCPT_VE = 0x14,
4040	/** \#SX - Security Exception. */
4041	X86_XCPT_SX = 0x1e
4042	} X86XCPT;
4043	/** Pointer to a x86 exception code. */
4044	typedef X86XCPT *PX86XCPT;
4045	/** Pointer to a const x86 exception code. */
4046	typedef const X86XCPT *PCX86XCPT;
4047	/** The last valid (currently reserved) exception value. */
4048	#define X86_XCPT_LAST 0x1f
4049
4050
4051	/** @name Trap Error Codes
4052	* @{
4053	*/
4054	/** External indicator. */
4055	#define X86_TRAP_ERR_EXTERNAL 1
4056	/** IDT indicator. */
4057	#define X86_TRAP_ERR_IDT 2
4058	/** Descriptor table indicator - If set LDT, if clear GDT. */
4059	#define X86_TRAP_ERR_TI 4
4060	/** Mask for getting the selector. */
4061	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4062	/** Shift for getting the selector table index (C type index). */
4063	#define X86_TRAP_ERR_SEL_SHIFT 3
4064	/** @} */
4065
4066
4067	/** @name \#PF Trap Error Codes
4068	* @{
4069	*/
4070	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4071	#define X86_TRAP_PF_P RT_BIT_32(0)
4072	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4073	#define X86_TRAP_PF_RW RT_BIT_32(1)
4074	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4075	#define X86_TRAP_PF_US RT_BIT_32(2)
4076	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4077	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4078	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4079	#define X86_TRAP_PF_ID RT_BIT_32(4)
4080	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4081	#define X86_TRAP_PF_PK RT_BIT_32(5)
4082	/** @} */
4083
4084	#pragma pack(1)
4085	/**
4086	* 16-bit IDTR.
4087	*/
4088	typedef struct X86IDTR16
4089	{
4090	/** Offset. */
4091	uint16_t offSel;
4092	/** Selector. */
4093	uint16_t uSel;
4094	} X86IDTR16, *PX86IDTR16;
4095	#pragma pack()
4096
4097	#pragma pack(1)
4098	/**
4099	* 32-bit IDTR/GDTR.
4100	*/
4101	typedef struct X86XDTR32
4102	{
4103	/** Size of the descriptor table. */
4104	uint16_t cb;
4105	/** Address of the descriptor table. */
4106	#ifndef VBOX_FOR_DTRACE_LIB
4107	uint32_t uAddr;
4108	#else
4109	uint16_t au16Addr[2];
4110	#endif
4111	} X86XDTR32, *PX86XDTR32;
4112	#pragma pack()
4113
4114	#pragma pack(1)
4115	/**
4116	* 64-bit IDTR/GDTR.
4117	*/
4118	typedef struct X86XDTR64
4119	{
4120	/** Size of the descriptor table. */
4121	uint16_t cb;
4122	/** Address of the descriptor table. */
4123	#ifndef VBOX_FOR_DTRACE_LIB
4124	uint64_t uAddr;
4125	#else
4126	uint16_t au16Addr[4];
4127	#endif
4128	} X86XDTR64, *PX86XDTR64;
4129	#pragma pack()
4130
4131
4132	/** @name ModR/M
4133	* @{ */
4134	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4135	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4136	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4137	#define X86_MODRM_REG_SHIFT 3
4138	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4139	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4140	#define X86_MODRM_MOD_SHIFT 6
4141	#ifndef VBOX_FOR_DTRACE_LIB
4142	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4143	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4144	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4145	/** @def X86_MODRM_MAKE
4146	* @param a_Mod The mod value (0..3).
4147	* @param a_Reg The register value (0..7).
4148	* @param a_RegMem The register or memory value (0..7). */
4149	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4150	#endif
4151	/** @} */
4152
4153	/** @name SIB
4154	* @{ */
4155	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4156	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4157	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4158	#define X86_SIB_INDEX_SHIFT 3
4159	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4160	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4161	#define X86_SIB_SCALE_SHIFT 6
4162	#ifndef VBOX_FOR_DTRACE_LIB
4163	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4164	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4165	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4166	#endif
4167	/** @} */
4168
4169	/** @name General register indexes
4170	* @{ */
4171	#define X86_GREG_xAX 0
4172	#define X86_GREG_xCX 1
4173	#define X86_GREG_xDX 2
4174	#define X86_GREG_xBX 3
4175	#define X86_GREG_xSP 4
4176	#define X86_GREG_xBP 5
4177	#define X86_GREG_xSI 6
4178	#define X86_GREG_xDI 7
4179	#define X86_GREG_x8 8
4180	#define X86_GREG_x9 9
4181	#define X86_GREG_x10 10
4182	#define X86_GREG_x11 11
4183	#define X86_GREG_x12 12
4184	#define X86_GREG_x13 13
4185	#define X86_GREG_x14 14
4186	#define X86_GREG_x15 15
4187	/** @} */
4188
4189	/** @name X86_SREG_XXX - Segment register indexes.
4190	* @{ */
4191	#define X86_SREG_ES 0
4192	#define X86_SREG_CS 1
4193	#define X86_SREG_SS 2
4194	#define X86_SREG_DS 3
4195	#define X86_SREG_FS 4
4196	#define X86_SREG_GS 5
4197	/** @} */
4198	/** Segment register count. */
4199	#define X86_SREG_COUNT 6
4200
4201
4202	/** @name X86_OP_XXX - Prefixes
4203	* @{ */
4204	#define X86_OP_PRF_CS UINT8_C(0x2e)
4205	#define X86_OP_PRF_SS UINT8_C(0x36)
4206	#define X86_OP_PRF_DS UINT8_C(0x3e)
4207	#define X86_OP_PRF_ES UINT8_C(0x26)
4208	#define X86_OP_PRF_FS UINT8_C(0x64)
4209	#define X86_OP_PRF_GS UINT8_C(0x65)
4210	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4211	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4212	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4213	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4214	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4215	#define X86_OP_REX_B UINT8_C(0x41)
4216	#define X86_OP_REX_X UINT8_C(0x42)
4217	#define X86_OP_REX_R UINT8_C(0x44)
4218	#define X86_OP_REX_W UINT8_C(0x48)
4219	/** @} */
4220
4221
4222	/** @} */
4223
4224	#endif
4225

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source: vbox/trunk/include/iprt/x86.h@ 69692

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