VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 72140

Last change on this file since 72140 was 72131, checked in by vboxsync, 7 years ago

x86.h: RTM debug register defines.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 161.6 KB
Line 
1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2017 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT_32(0)
164#define X86_EFL_CF_BIT 0
165/** Bit 1 - Reserved, reads as 1. */
166#define X86_EFL_1 RT_BIT_32(1)
167/** Bit 2 - PF - Parity flag - Status flag. */
168#define X86_EFL_PF RT_BIT_32(2)
169/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170#define X86_EFL_AF RT_BIT_32(4)
171#define X86_EFL_AF_BIT 4
172/** Bit 6 - ZF - Zero flag - Status flag. */
173#define X86_EFL_ZF RT_BIT_32(6)
174#define X86_EFL_ZF_BIT 6
175/** Bit 7 - SF - Signed flag - Status flag. */
176#define X86_EFL_SF RT_BIT_32(7)
177#define X86_EFL_SF_BIT 7
178/** Bit 8 - TF - Trap flag - System flag. */
179#define X86_EFL_TF RT_BIT_32(8)
180/** Bit 9 - IF - Interrupt flag - System flag. */
181#define X86_EFL_IF RT_BIT_32(9)
182/** Bit 10 - DF - Direction flag - Control flag. */
183#define X86_EFL_DF RT_BIT_32(10)
184/** Bit 11 - OF - Overflow flag - Status flag. */
185#define X86_EFL_OF RT_BIT_32(11)
186#define X86_EFL_OF_BIT 11
187/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
189/** Bit 14 - NT - Nested task flag - System flag. */
190#define X86_EFL_NT RT_BIT_32(14)
191/** Bit 16 - RF - Resume flag - System flag. */
192#define X86_EFL_RF RT_BIT_32(16)
193/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194#define X86_EFL_VM RT_BIT_32(17)
195/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196#define X86_EFL_AC RT_BIT_32(18)
197/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198#define X86_EFL_VIF RT_BIT_32(19)
199/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200#define X86_EFL_VIP RT_BIT_32(20)
201/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202#define X86_EFL_ID RT_BIT_32(21)
203/** All live bits. */
204#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205/** Read as 1 bits. */
206#define X86_EFL_RA1_MASK RT_BIT_32(1)
207/** IOPL shift. */
208#define X86_EFL_IOPL_SHIFT 12
209/** The IOPL level from the flags. */
210#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211/** Bits restored by popf */
212#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
213 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
217/** The status bits commonly updated by arithmetic instructions. */
218#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
219/** @} */
220
221
222/** CPUID Feature information - ECX.
223 * CPUID query with EAX=1.
224 */
225#ifndef VBOX_FOR_DTRACE_LIB
226typedef struct X86CPUIDFEATECX
227{
228 /** Bit 0 - SSE3 - Supports SSE3 or not. */
229 unsigned u1SSE3 : 1;
230 /** Bit 1 - PCLMULQDQ. */
231 unsigned u1PCLMULQDQ : 1;
232 /** Bit 2 - DS Area 64-bit layout. */
233 unsigned u1DTE64 : 1;
234 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235 unsigned u1Monitor : 1;
236 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237 unsigned u1CPLDS : 1;
238 /** Bit 5 - VMX - Virtual Machine Technology. */
239 unsigned u1VMX : 1;
240 /** Bit 6 - SMX: Safer Mode Extensions. */
241 unsigned u1SMX : 1;
242 /** Bit 7 - EST - Enh. SpeedStep Tech. */
243 unsigned u1EST : 1;
244 /** Bit 8 - TM2 - Terminal Monitor 2. */
245 unsigned u1TM2 : 1;
246 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247 unsigned u1SSSE3 : 1;
248 /** Bit 10 - CNTX-ID - L1 Context ID. */
249 unsigned u1CNTXID : 1;
250 /** Bit 11 - Reserved. */
251 unsigned u1Reserved1 : 1;
252 /** Bit 12 - FMA. */
253 unsigned u1FMA : 1;
254 /** Bit 13 - CX16 - CMPXCHG16B. */
255 unsigned u1CX16 : 1;
256 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257 unsigned u1TPRUpdate : 1;
258 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259 unsigned u1PDCM : 1;
260 /** Bit 16 - Reserved. */
261 unsigned u1Reserved2 : 1;
262 /** Bit 17 - PCID - Process-context identifiers. */
263 unsigned u1PCID : 1;
264 /** Bit 18 - Direct Cache Access. */
265 unsigned u1DCA : 1;
266 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267 unsigned u1SSE4_1 : 1;
268 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269 unsigned u1SSE4_2 : 1;
270 /** Bit 21 - x2APIC. */
271 unsigned u1x2APIC : 1;
272 /** Bit 22 - MOVBE - Supports MOVBE. */
273 unsigned u1MOVBE : 1;
274 /** Bit 23 - POPCNT - Supports POPCNT. */
275 unsigned u1POPCNT : 1;
276 /** Bit 24 - TSC-Deadline. */
277 unsigned u1TSCDEADLINE : 1;
278 /** Bit 25 - AES. */
279 unsigned u1AES : 1;
280 /** Bit 26 - XSAVE - Supports XSAVE. */
281 unsigned u1XSAVE : 1;
282 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283 unsigned u1OSXSAVE : 1;
284 /** Bit 28 - AVX - Supports AVX instruction extensions. */
285 unsigned u1AVX : 1;
286 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287 unsigned u1F16C : 1;
288 /** Bit 30 - RDRAND - Supports RDRAND. */
289 unsigned u1RDRAND : 1;
290 /** Bit 31 - Hypervisor present (we're a guest). */
291 unsigned u1HVP : 1;
292} X86CPUIDFEATECX;
293#else /* VBOX_FOR_DTRACE_LIB */
294typedef uint32_t X86CPUIDFEATECX;
295#endif /* VBOX_FOR_DTRACE_LIB */
296/** Pointer to CPUID Feature Information - ECX. */
297typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298/** Pointer to const CPUID Feature Information - ECX. */
299typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302/** CPUID Feature Information - EDX.
303 * CPUID query with EAX=1.
304 */
305#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306typedef struct X86CPUIDFEATEDX
307{
308 /** Bit 0 - FPU - x87 FPU on Chip. */
309 unsigned u1FPU : 1;
310 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311 unsigned u1VME : 1;
312 /** Bit 2 - DE - Debugging extensions. */
313 unsigned u1DE : 1;
314 /** Bit 3 - PSE - Page Size Extension. */
315 unsigned u1PSE : 1;
316 /** Bit 4 - TSC - Time Stamp Counter. */
317 unsigned u1TSC : 1;
318 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319 unsigned u1MSR : 1;
320 /** Bit 6 - PAE - Physical Address Extension. */
321 unsigned u1PAE : 1;
322 /** Bit 7 - MCE - Machine Check Exception. */
323 unsigned u1MCE : 1;
324 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
325 unsigned u1CX8 : 1;
326 /** Bit 9 - APIC - APIC On-Chip. */
327 unsigned u1APIC : 1;
328 /** Bit 10 - Reserved. */
329 unsigned u1Reserved1 : 1;
330 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331 unsigned u1SEP : 1;
332 /** Bit 12 - MTRR - Memory Type Range Registers. */
333 unsigned u1MTRR : 1;
334 /** Bit 13 - PGE - PTE Global Bit. */
335 unsigned u1PGE : 1;
336 /** Bit 14 - MCA - Machine Check Architecture. */
337 unsigned u1MCA : 1;
338 /** Bit 15 - CMOV - Conditional Move Instructions. */
339 unsigned u1CMOV : 1;
340 /** Bit 16 - PAT - Page Attribute Table. */
341 unsigned u1PAT : 1;
342 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343 unsigned u1PSE36 : 1;
344 /** Bit 18 - PSN - Processor Serial Number. */
345 unsigned u1PSN : 1;
346 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
347 unsigned u1CLFSH : 1;
348 /** Bit 20 - Reserved. */
349 unsigned u1Reserved2 : 1;
350 /** Bit 21 - DS - Debug Store. */
351 unsigned u1DS : 1;
352 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353 unsigned u1ACPI : 1;
354 /** Bit 23 - MMX - Intel MMX 'Technology'. */
355 unsigned u1MMX : 1;
356 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357 unsigned u1FXSR : 1;
358 /** Bit 25 - SSE - SSE Support. */
359 unsigned u1SSE : 1;
360 /** Bit 26 - SSE2 - SSE2 Support. */
361 unsigned u1SSE2 : 1;
362 /** Bit 27 - SS - Self Snoop. */
363 unsigned u1SS : 1;
364 /** Bit 28 - HTT - Hyper-Threading Technology. */
365 unsigned u1HTT : 1;
366 /** Bit 29 - TM - Thermal Monitor. */
367 unsigned u1TM : 1;
368 /** Bit 30 - Reserved - . */
369 unsigned u1Reserved3 : 1;
370 /** Bit 31 - PBE - Pending Break Enabled. */
371 unsigned u1PBE : 1;
372} X86CPUIDFEATEDX;
373#else /* VBOX_FOR_DTRACE_LIB */
374typedef uint32_t X86CPUIDFEATEDX;
375#endif /* VBOX_FOR_DTRACE_LIB */
376/** Pointer to CPUID Feature Information - EDX. */
377typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378/** Pointer to const CPUID Feature Information - EDX. */
379typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381/** @name CPUID Vendor information.
382 * CPUID query with EAX=0.
383 * @{
384 */
385#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396/** @} */
397
398
399/** @name CPUID Feature information.
400 * CPUID query with EAX=1.
401 * @{
402 */
403/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428/** ECX Bit 12 - FMA. */
429#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436/** ECX Bit 17 - PCID - Process-context identifiers. */
437#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438/** ECX Bit 18 - DCA - Direct Cache Access. */
439#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444/** ECX Bit 21 - x2APIC support. */
445#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446/** ECX Bit 22 - MOVBE instruction. */
447#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448/** ECX Bit 23 - POPCNT instruction. */
449#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450/** ECX Bir 24 - TSC-Deadline. */
451#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452/** ECX Bit 25 - AES instructions. */
453#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454/** ECX Bit 26 - XSAVE instruction. */
455#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458/** ECX Bit 28 - AVX. */
459#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462/** ECX Bit 30 - RDRAND instruction. */
463#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464/** ECX Bit 31 - Hypervisor Present (software only). */
465#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468/** Bit 0 - FPU - x87 FPU on Chip. */
469#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472/** Bit 2 - DE - Debugging extensions. */
473#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474/** Bit 3 - PSE - Page Size Extension. */
475#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
477/** Bit 4 - TSC - Time Stamp Counter. */
478#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481/** Bit 6 - PAE - Physical Address Extension. */
482#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
484/** Bit 7 - MCE - Machine Check Exception. */
485#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488/** Bit 9 - APIC - APIC On-Chip. */
489#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492/** Bit 12 - MTRR - Memory Type Range Registers. */
493#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494/** Bit 13 - PGE - PTE Global Bit. */
495#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496/** Bit 14 - MCA - Machine Check Architecture. */
497#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498/** Bit 15 - CMOV - Conditional Move Instructions. */
499#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500/** Bit 16 - PAT - Page Attribute Table. */
501#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504/** Bit 18 - PSN - Processor Serial Number. */
505#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508/** Bit 21 - DS - Debug Store. */
509#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512/** Bit 23 - MMX - Intel MMX Technology. */
513#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516/** Bit 25 - SSE - SSE Support. */
517#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518/** Bit 26 - SSE2 - SSE2 Support. */
519#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520/** Bit 27 - SS - Self Snoop. */
521#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522/** Bit 28 - HTT - Hyper-Threading Technology. */
523#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524/** Bit 29 - TM - Therm. Monitor. */
525#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526/** Bit 31 - PBE - Pending Break Enabled. */
527#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528/** @} */
529
530/** @name CPUID mwait/monitor information.
531 * CPUID query with EAX=5.
532 * @{
533 */
534/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538/** @} */
539
540
541/** @name CPUID Structured Extended Feature information.
542 * CPUID query with EAX=7.
543 * @{
544 */
545/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
601#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
602/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
603#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
604/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
605#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
606/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
607#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
608/** ECX Bit 22 - RDPID - Support pread process ID. */
609#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
610/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
611#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
612
613/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
614 * IBPB command in IA32_PRED_CMD. */
615#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
616/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
617#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
618
619/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
620#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
621
622/** @} */
623
624
625/** @name CPUID Extended Feature information.
626 * CPUID query with EAX=0x80000001.
627 * @{
628 */
629/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
630#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
631
632/** EDX Bit 11 - SYSCALL/SYSRET. */
633#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
634/** EDX Bit 20 - No-Execute/Execute-Disable. */
635#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
636/** EDX Bit 26 - 1 GB large page. */
637#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
638/** EDX Bit 27 - RDTSCP. */
639#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
640/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
641#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
642/** @}*/
643
644/** @name CPUID AMD Feature information.
645 * CPUID query with EAX=0x80000001.
646 * @{
647 */
648/** Bit 0 - FPU - x87 FPU on Chip. */
649#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
650/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
651#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
652/** Bit 2 - DE - Debugging extensions. */
653#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
654/** Bit 3 - PSE - Page Size Extension. */
655#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
656/** Bit 4 - TSC - Time Stamp Counter. */
657#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
658/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
659#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
660/** Bit 6 - PAE - Physical Address Extension. */
661#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
662/** Bit 7 - MCE - Machine Check Exception. */
663#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
664/** Bit 8 - CX8 - CMPXCHG8B instruction. */
665#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
666/** Bit 9 - APIC - APIC On-Chip. */
667#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
668/** Bit 12 - MTRR - Memory Type Range Registers. */
669#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
670/** Bit 13 - PGE - PTE Global Bit. */
671#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
672/** Bit 14 - MCA - Machine Check Architecture. */
673#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
674/** Bit 15 - CMOV - Conditional Move Instructions. */
675#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
676/** Bit 16 - PAT - Page Attribute Table. */
677#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
678/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
679#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
680/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
681#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
682/** Bit 23 - MMX - Intel MMX Technology. */
683#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
684/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
685#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
686/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
687#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
688/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
689#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
690/** Bit 31 - 3DNOW - AMD 3DNow. */
691#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
692
693/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
694#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
695/** Bit 2 - SVM - AMD VM extensions. */
696#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
697/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
698#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
699/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
700#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
701/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
702#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
703/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
704#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
705/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
706#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
707/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
708#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
709/** Bit 9 - OSVW - AMD OS visible workaround. */
710#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
711/** Bit 10 - IBS - Instruct based sampling. */
712#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
713/** Bit 11 - XOP - Extended operation support (see APM6). */
714#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
715/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
716#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
717/** Bit 13 - WDT - AMD Watchdog timer support. */
718#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
719/** Bit 15 - LWP - Lightweight profiling support. */
720#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
721/** Bit 16 - FMA4 - Four operand FMA instruction support. */
722#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
723/** Bit 19 - NodeId - Indicates support for
724 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
725#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
726/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
727#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
728/** Bit 22 - TopologyExtensions - . */
729#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
730/** @} */
731
732
733/** @name CPUID AMD Feature information.
734 * CPUID query with EAX=0x80000007.
735 * @{
736 */
737/** Bit 0 - TS - Temperature Sensor. */
738#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
739/** Bit 1 - FID - Frequency ID Control. */
740#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
741/** Bit 2 - VID - Voltage ID Control. */
742#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
743/** Bit 3 - TTP - THERMTRIP. */
744#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
745/** Bit 4 - TM - Hardware Thermal Control. */
746#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
747/** Bit 5 - STC - Software Thermal Control. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
749/** Bit 6 - MC - 100 Mhz Multiplier Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
751/** Bit 7 - HWPSTATE - Hardware P-State Control. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
753/** Bit 8 - TSCINVAR - TSC Invariant. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
755/** Bit 9 - CPB - TSC Invariant. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
757/** Bit 10 - EffFreqRO - MPERF/APERF. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
759/** Bit 11 - PFI - Processor feedback interface (see EAX). */
760#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
761/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
762#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
763/** @} */
764
765
766/** @name CPUID AMD extended feature extensions ID (EBX).
767 * CPUID query with EAX=0x80000008.
768 * @{
769 */
770/** Bit 0 - CLZERO - Clear zero instruction. */
771#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
772/** Bit 1 - IRPerf - Instructions retired count support. */
773#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
774/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
775#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
776/* AMD pipeline length: 9 feature bits ;-) */
777/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
778#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
779/** @} */
780
781
782/** @name CPUID AMD SVM Feature information.
783 * CPUID query with EAX=0x8000000a.
784 * @{
785 */
786/** Bit 0 - NP - Nested Paging supported. */
787#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
788/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
789#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
790/** Bit 2 - SVML - SVM locking bit supported. */
791#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
792/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
793#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
794/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
795#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
796/** Bit 5 - VmcbClean - Support VMCB clean bits. */
797#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
798/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
799 * VMCB.TLB_Control is supported. */
800#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
801/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
802#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
803/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
804#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
805/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
806 * intercept filter cycle count threshold. */
807#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
808/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
809#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
810/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
811#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
812/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
813#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
814/** @} */
815
816
817/** @name CR0
818 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
819 * reserved flags.
820 * @{ */
821/** Bit 0 - PE - Protection Enabled */
822#define X86_CR0_PE RT_BIT_32(0)
823#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
824/** Bit 1 - MP - Monitor Coprocessor */
825#define X86_CR0_MP RT_BIT_32(1)
826#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
827/** Bit 2 - EM - Emulation. */
828#define X86_CR0_EM RT_BIT_32(2)
829#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
830/** Bit 3 - TS - Task Switch. */
831#define X86_CR0_TS RT_BIT_32(3)
832#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
833/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
834#define X86_CR0_ET RT_BIT_32(4)
835#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
836/** Bit 5 - NE - Numeric error (486+). */
837#define X86_CR0_NE RT_BIT_32(5)
838#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
839/** Bit 16 - WP - Write Protect (486+). */
840#define X86_CR0_WP RT_BIT_32(16)
841#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
842/** Bit 18 - AM - Alignment Mask (486+). */
843#define X86_CR0_AM RT_BIT_32(18)
844#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
845/** Bit 29 - NW - Not Write-though (486+). */
846#define X86_CR0_NW RT_BIT_32(29)
847#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
848/** Bit 30 - WP - Cache Disable (486+). */
849#define X86_CR0_CD RT_BIT_32(30)
850#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
851/** Bit 31 - PG - Paging. */
852#define X86_CR0_PG RT_BIT_32(31)
853#define X86_CR0_PAGING RT_BIT_32(31)
854/** @} */
855
856
857/** @name CR3
858 * @{ */
859/** Bit 3 - PWT - Page-level Writes Transparent. */
860#define X86_CR3_PWT RT_BIT_32(3)
861/** Bit 4 - PCD - Page-level Cache Disable. */
862#define X86_CR3_PCD RT_BIT_32(4)
863/** Bits 12-31 - - Page directory page number. */
864#define X86_CR3_PAGE_MASK (0xfffff000)
865/** Bits 5-31 - - PAE Page directory page number. */
866#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
867/** Bits 12-51 - - AMD64 Page directory page number. */
868#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
869/** @} */
870
871
872/** @name CR4
873 * @{ */
874/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
875#define X86_CR4_VME RT_BIT_32(0)
876/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
877#define X86_CR4_PVI RT_BIT_32(1)
878/** Bit 2 - TSD - Time Stamp Disable. */
879#define X86_CR4_TSD RT_BIT_32(2)
880/** Bit 3 - DE - Debugging Extensions. */
881#define X86_CR4_DE RT_BIT_32(3)
882/** Bit 4 - PSE - Page Size Extension. */
883#define X86_CR4_PSE RT_BIT_32(4)
884/** Bit 5 - PAE - Physical Address Extension. */
885#define X86_CR4_PAE RT_BIT_32(5)
886/** Bit 6 - MCE - Machine-Check Enable. */
887#define X86_CR4_MCE RT_BIT_32(6)
888/** Bit 7 - PGE - Page Global Enable. */
889#define X86_CR4_PGE RT_BIT_32(7)
890/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
891#define X86_CR4_PCE RT_BIT_32(8)
892/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
893#define X86_CR4_OSFXSR RT_BIT_32(9)
894/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
895#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
896/** Bit 13 - VMXE - VMX mode is enabled. */
897#define X86_CR4_VMXE RT_BIT_32(13)
898/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
899#define X86_CR4_SMXE RT_BIT_32(14)
900/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
901#define X86_CR4_FSGSBASE RT_BIT_32(16)
902/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
903#define X86_CR4_PCIDE RT_BIT_32(17)
904/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
905 * extended states. */
906#define X86_CR4_OSXSAVE RT_BIT_32(18)
907/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
908#define X86_CR4_SMEP RT_BIT_32(20)
909/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
910#define X86_CR4_SMAP RT_BIT_32(21)
911/** Bit 22 - PKE - Protection Key Enable. */
912#define X86_CR4_PKE RT_BIT_32(22)
913/** @} */
914
915
916/** @name DR6
917 * @{ */
918/** Bit 0 - B0 - Breakpoint 0 condition detected. */
919#define X86_DR6_B0 RT_BIT_32(0)
920/** Bit 1 - B1 - Breakpoint 1 condition detected. */
921#define X86_DR6_B1 RT_BIT_32(1)
922/** Bit 2 - B2 - Breakpoint 2 condition detected. */
923#define X86_DR6_B2 RT_BIT_32(2)
924/** Bit 3 - B3 - Breakpoint 3 condition detected. */
925#define X86_DR6_B3 RT_BIT_32(3)
926/** Mask of all the Bx bits. */
927#define X86_DR6_B_MASK UINT64_C(0x0000000f)
928/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
929#define X86_DR6_BD RT_BIT_32(13)
930/** Bit 14 - BS - Single step */
931#define X86_DR6_BS RT_BIT_32(14)
932/** Bit 15 - BT - Task switch. (TSS T bit.) */
933#define X86_DR6_BT RT_BIT_32(15)
934/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
935#define X86_DR6_RTM RT_BIT_32(16)
936/** Value of DR6 after powerup/reset. */
937#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
938/** Bits which must be 1s in DR6. */
939#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
940/** Bits which must be 1s in DR6, when RTM is supported. */
941#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
942/** Bits which must be 0s in DR6. */
943#define X86_DR6_RAZ_MASK RT_BIT_64(12)
944/** Bits which must be 0s on writes to DR6. */
945#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
946/** @} */
947
948/** Get the DR6.Bx bit for a the given breakpoint. */
949#define X86_DR6_B(iBp) RT_BIT_64(iBp)
950
951
952/** @name DR7
953 * @{ */
954/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
955#define X86_DR7_L0 RT_BIT_32(0)
956/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
957#define X86_DR7_G0 RT_BIT_32(1)
958/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
959#define X86_DR7_L1 RT_BIT_32(2)
960/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
961#define X86_DR7_G1 RT_BIT_32(3)
962/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
963#define X86_DR7_L2 RT_BIT_32(4)
964/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
965#define X86_DR7_G2 RT_BIT_32(5)
966/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
967#define X86_DR7_L3 RT_BIT_32(6)
968/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
969#define X86_DR7_G3 RT_BIT_32(7)
970/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
971#define X86_DR7_LE RT_BIT_32(8)
972/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
973#define X86_DR7_GE RT_BIT_32(9)
974
975/** L0, L1, L2, and L3. */
976#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
977/** L0, L1, L2, and L3. */
978#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
979
980/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
981 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
982#define X86_DR7_RTM RT_BIT_32(11)
983/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
984 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
985 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
986 * instruction is executed.
987 * @see http://www.rcollins.org/secrets/DR7.html */
988#define X86_DR7_ICE_IR RT_BIT_32(12)
989/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
990 * any DR register is accessed. */
991#define X86_DR7_GD RT_BIT_32(13)
992/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
993 * Pentium. */
994#define X86_DR7_ICE_TR1 RT_BIT_32(14)
995/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
996#define X86_DR7_ICE_TR2 RT_BIT_32(15)
997/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
998#define X86_DR7_RW0_MASK (3 << 16)
999/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1000#define X86_DR7_LEN0_MASK (3 << 18)
1001/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1002#define X86_DR7_RW1_MASK (3 << 20)
1003/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1004#define X86_DR7_LEN1_MASK (3 << 22)
1005/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1006#define X86_DR7_RW2_MASK (3 << 24)
1007/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1008#define X86_DR7_LEN2_MASK (3 << 26)
1009/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1010#define X86_DR7_RW3_MASK (3 << 28)
1011/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1012#define X86_DR7_LEN3_MASK (3 << 30)
1013
1014/** Bits which reads as 1s. */
1015#define X86_DR7_RA1_MASK RT_BIT_32(10)
1016/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1017#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1018/** Bits which must be 0s when writing to DR7. */
1019#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1020
1021/** Calcs the L bit of Nth breakpoint.
1022 * @param iBp The breakpoint number [0..3].
1023 */
1024#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1025
1026/** Calcs the G bit of Nth breakpoint.
1027 * @param iBp The breakpoint number [0..3].
1028 */
1029#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1030
1031/** Calcs the L and G bits of Nth breakpoint.
1032 * @param iBp The breakpoint number [0..3].
1033 */
1034#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1035
1036/** @name Read/Write values.
1037 * @{ */
1038/** Break on instruction fetch only. */
1039#define X86_DR7_RW_EO UINT32_C(0)
1040/** Break on write only. */
1041#define X86_DR7_RW_WO UINT32_C(1)
1042/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1043#define X86_DR7_RW_IO UINT32_C(2)
1044/** Break on read or write (but not instruction fetches). */
1045#define X86_DR7_RW_RW UINT32_C(3)
1046/** @} */
1047
1048/** Shifts a X86_DR7_RW_* value to its right place.
1049 * @param iBp The breakpoint number [0..3].
1050 * @param fRw One of the X86_DR7_RW_* value.
1051 */
1052#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1053
1054/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1055 * one of the X86_DR7_RW_XXX constants).
1056 *
1057 * @returns X86_DR7_RW_XXX
1058 * @param uDR7 DR7 value
1059 * @param iBp The breakpoint number [0..3].
1060 */
1061#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1062
1063/** R/W0, R/W1, R/W2, and R/W3. */
1064#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1065
1066#ifndef VBOX_FOR_DTRACE_LIB
1067/** Checks if there are any I/O breakpoint types configured in the RW
1068 * registers. Does NOT check if these are enabled, sorry. */
1069# define X86_DR7_ANY_RW_IO(uDR7) \
1070 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1071 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1072AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1073AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1074AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1075AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1076AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1077AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1078AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1079AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1080AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1081#endif /* !VBOX_FOR_DTRACE_LIB */
1082
1083/** @name Length values.
1084 * @{ */
1085#define X86_DR7_LEN_BYTE UINT32_C(0)
1086#define X86_DR7_LEN_WORD UINT32_C(1)
1087#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1088#define X86_DR7_LEN_DWORD UINT32_C(3)
1089/** @} */
1090
1091/** Shifts a X86_DR7_LEN_* value to its right place.
1092 * @param iBp The breakpoint number [0..3].
1093 * @param cb One of the X86_DR7_LEN_* values.
1094 */
1095#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1096
1097/** Fetch the breakpoint length bits from the DR7 value.
1098 * @param uDR7 DR7 value
1099 * @param iBp The breakpoint number [0..3].
1100 */
1101#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1102
1103/** Mask used to check if any breakpoints are enabled. */
1104#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1105
1106/** LEN0, LEN1, LEN2, and LEN3. */
1107#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1108/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1109#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1110
1111/** Value of DR7 after powerup/reset. */
1112#define X86_DR7_INIT_VAL 0x400
1113/** @} */
1114
1115
1116/** @name Machine Specific Registers
1117 * @{
1118 */
1119/** Machine check address register (P5). */
1120#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1121/** Machine check type register (P5). */
1122#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1123/** Time Stamp Counter. */
1124#define MSR_IA32_TSC 0x10
1125#define MSR_IA32_CESR UINT32_C(0x00000011)
1126#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1127#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1128
1129#define MSR_IA32_PLATFORM_ID 0x17
1130
1131#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1132# define MSR_IA32_APICBASE 0x1b
1133/** Local APIC enabled. */
1134# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1135/** X2APIC enabled (requires the EN bit to be set). */
1136# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1137/** The processor is the boot strap processor (BSP). */
1138# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1139/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1140 * width. */
1141# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1142/** The default physical base address of the APIC. */
1143# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1144/** Gets the physical base address from the MSR. */
1145# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1146#endif
1147
1148/** Undocumented intel MSR for reporting thread and core counts.
1149 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1150 * first 16 bits is the thread count. The next 16 bits the core count, except
1151 * on Westmere where it seems it's only the next 4 bits for some reason. */
1152#define MSR_CORE_THREAD_COUNT 0x35
1153
1154/** CPU Feature control. */
1155#define MSR_IA32_FEATURE_CONTROL 0x3A
1156#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
1157#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
1158#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
1159
1160/** Per-processor TSC adjust MSR. */
1161#define MSR_IA32_TSC_ADJUST 0x3B
1162
1163/** Spectre control register.
1164 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1165#define MSR_IA32_SPEC_CTRL 0x48
1166/** IBRS - Indirect branch restricted speculation. */
1167#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1168/** STIBP - Single thread indirect branch predictors. */
1169#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1170
1171/** Prediction command register.
1172 * Write only, logical processor scope, no state since write only. */
1173#define MSR_IA32_PRED_CMD 0x49
1174/** IBPB - Indirect branch prediction barrie when written as 1. */
1175#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1176
1177/** BIOS update trigger (microcode update). */
1178#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1179
1180/** BIOS update signature (microcode). */
1181#define MSR_IA32_BIOS_SIGN_ID 0x8B
1182
1183/** SMM monitor control. */
1184#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1185
1186/** General performance counter no. 0. */
1187#define MSR_IA32_PMC0 0xC1
1188/** General performance counter no. 1. */
1189#define MSR_IA32_PMC1 0xC2
1190/** General performance counter no. 2. */
1191#define MSR_IA32_PMC2 0xC3
1192/** General performance counter no. 3. */
1193#define MSR_IA32_PMC3 0xC4
1194
1195/** Nehalem power control. */
1196#define MSR_IA32_PLATFORM_INFO 0xCE
1197
1198/** Get FSB clock status (Intel-specific). */
1199#define MSR_IA32_FSB_CLOCK_STS 0xCD
1200
1201/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1202#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1203
1204/** C0 Maximum Frequency Clock Count */
1205#define MSR_IA32_MPERF 0xE7
1206/** C0 Actual Frequency Clock Count */
1207#define MSR_IA32_APERF 0xE8
1208
1209/** MTRR Capabilities. */
1210#define MSR_IA32_MTRR_CAP 0xFE
1211
1212/** Architecture capabilities (bugfixes).
1213 * @note May move */
1214#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1215/** CPU is no subject to spectre problems. */
1216#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0)
1217/** CPU has better IBRS and you can leave it on all the time. */
1218#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1)
1219
1220/** Cache control/info. */
1221#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1222
1223#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1224/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1225 * R0 SS == CS + 8
1226 * R3 CS == CS + 16
1227 * R3 SS == CS + 24
1228 */
1229#define MSR_IA32_SYSENTER_CS 0x174
1230/** SYSENTER_ESP - the R0 ESP. */
1231#define MSR_IA32_SYSENTER_ESP 0x175
1232/** SYSENTER_EIP - the R0 EIP. */
1233#define MSR_IA32_SYSENTER_EIP 0x176
1234#endif
1235
1236/** Machine Check Global Capabilities Register. */
1237#define MSR_IA32_MCG_CAP 0x179
1238/** Machine Check Global Status Register. */
1239#define MSR_IA32_MCG_STATUS 0x17A
1240/** Machine Check Global Control Register. */
1241#define MSR_IA32_MCG_CTRL 0x17B
1242
1243/** Page Attribute Table. */
1244#define MSR_IA32_CR_PAT 0x277
1245/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1246 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1247#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1248
1249/** Performance counter MSRs. (Intel only) */
1250#define MSR_IA32_PERFEVTSEL0 0x186
1251#define MSR_IA32_PERFEVTSEL1 0x187
1252/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1253 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1254 * holds a ratio that Apple takes for TSC granularity.
1255 *
1256 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1257#define MSR_FLEX_RATIO 0x194
1258/** Performance state value and starting with Intel core more.
1259 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1260#define MSR_IA32_PERF_STATUS 0x198
1261#define MSR_IA32_PERF_CTL 0x199
1262#define MSR_IA32_THERM_STATUS 0x19c
1263
1264/** Enable misc. processor features (R/W). */
1265#define MSR_IA32_MISC_ENABLE 0x1A0
1266/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1267#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1268/** Automatic Thermal Control Circuit Enable (R/W). */
1269#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1270/** Performance Monitoring Available (R). */
1271#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1272/** Branch Trace Storage Unavailable (R/O). */
1273#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1274/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1275#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1276/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1277#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1278/** If MONITOR/MWAIT is supported (R/W). */
1279#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1280/** Limit CPUID Maxval to 3 leafs (R/W). */
1281#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1282/** When set to 1, xTPR messages are disabled (R/W). */
1283#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1284/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1285#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1286
1287/** Trace/Profile Resource Control (R/W) */
1288#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1289/** Last branch record. */
1290#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1291/** Branch trace flag (single step on branches). */
1292#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1293/** Performance monitoring pin control (AMD only). */
1294#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1295#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1296#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1297#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1298/** Trace message enable (Intel only). */
1299#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1300/** Branch trace store (Intel only). */
1301#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1302/** Branch trace interrupt (Intel only). */
1303#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1304/** Branch trace off in privileged code (Intel only). */
1305#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1306/** Branch trace off in user code (Intel only). */
1307#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1308/** Freeze LBR on PMI flag (Intel only). */
1309#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1310/** Freeze PERFMON on PMI flag (Intel only). */
1311#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1312/** Freeze while SMM enabled (Intel only). */
1313#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1314/** Advanced debugging of RTM regions (Intel only). */
1315#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1316
1317/** The number (0..3 or 0..15) of the last branch record register on P4 and
1318 * related Xeons. */
1319#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1320/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1321 * @{ */
1322#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1323#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1324#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1325#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1326/** @} */
1327
1328
1329#define IA32_MTRR_PHYSBASE0 0x200
1330#define IA32_MTRR_PHYSMASK0 0x201
1331#define IA32_MTRR_PHYSBASE1 0x202
1332#define IA32_MTRR_PHYSMASK1 0x203
1333#define IA32_MTRR_PHYSBASE2 0x204
1334#define IA32_MTRR_PHYSMASK2 0x205
1335#define IA32_MTRR_PHYSBASE3 0x206
1336#define IA32_MTRR_PHYSMASK3 0x207
1337#define IA32_MTRR_PHYSBASE4 0x208
1338#define IA32_MTRR_PHYSMASK4 0x209
1339#define IA32_MTRR_PHYSBASE5 0x20a
1340#define IA32_MTRR_PHYSMASK5 0x20b
1341#define IA32_MTRR_PHYSBASE6 0x20c
1342#define IA32_MTRR_PHYSMASK6 0x20d
1343#define IA32_MTRR_PHYSBASE7 0x20e
1344#define IA32_MTRR_PHYSMASK7 0x20f
1345#define IA32_MTRR_PHYSBASE8 0x210
1346#define IA32_MTRR_PHYSMASK8 0x211
1347#define IA32_MTRR_PHYSBASE9 0x212
1348#define IA32_MTRR_PHYSMASK9 0x213
1349
1350/** Fixed range MTRRs.
1351 * @{ */
1352#define IA32_MTRR_FIX64K_00000 0x250
1353#define IA32_MTRR_FIX16K_80000 0x258
1354#define IA32_MTRR_FIX16K_A0000 0x259
1355#define IA32_MTRR_FIX4K_C0000 0x268
1356#define IA32_MTRR_FIX4K_C8000 0x269
1357#define IA32_MTRR_FIX4K_D0000 0x26a
1358#define IA32_MTRR_FIX4K_D8000 0x26b
1359#define IA32_MTRR_FIX4K_E0000 0x26c
1360#define IA32_MTRR_FIX4K_E8000 0x26d
1361#define IA32_MTRR_FIX4K_F0000 0x26e
1362#define IA32_MTRR_FIX4K_F8000 0x26f
1363/** @} */
1364
1365/** MTRR Default Range. */
1366#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1367
1368/** Global performance counter control facilities (Intel only). */
1369#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1370#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1371#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1372
1373/** Precise Event Based sampling (Intel only). */
1374#define MSR_IA32_PEBS_ENABLE 0x3F1
1375
1376#define MSR_IA32_MC0_CTL 0x400
1377#define MSR_IA32_MC0_STATUS 0x401
1378
1379/** Basic VMX information. */
1380#define MSR_IA32_VMX_BASIC_INFO 0x480
1381/** Allowed settings for pin-based VM execution controls */
1382#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1383/** Allowed settings for proc-based VM execution controls */
1384#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1385/** Allowed settings for the VMX exit controls. */
1386#define MSR_IA32_VMX_EXIT_CTLS 0x483
1387/** Allowed settings for the VMX entry controls. */
1388#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1389/** Misc VMX info. */
1390#define MSR_IA32_VMX_MISC 0x485
1391/** Fixed cleared bits in CR0. */
1392#define MSR_IA32_VMX_CR0_FIXED0 0x486
1393/** Fixed set bits in CR0. */
1394#define MSR_IA32_VMX_CR0_FIXED1 0x487
1395/** Fixed cleared bits in CR4. */
1396#define MSR_IA32_VMX_CR4_FIXED0 0x488
1397/** Fixed set bits in CR4. */
1398#define MSR_IA32_VMX_CR4_FIXED1 0x489
1399/** Information for enumerating fields in the VMCS. */
1400#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1401/** Allowed settings for the VM-functions controls. */
1402#define MSR_IA32_VMX_VMFUNC 0x491
1403/** Allowed settings for secondary proc-based VM execution controls */
1404#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1405/** EPT capabilities. */
1406#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1407/** Allowed settings of all pin-based VM execution controls. */
1408#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1409/** Allowed settings of all proc-based VM execution controls. */
1410#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1411/** Allowed settings of all VMX exit controls. */
1412#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1413/** Allowed settings of all VMX entry controls. */
1414#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1415
1416/** DS Save Area (R/W). */
1417#define MSR_IA32_DS_AREA 0x600
1418/** Running Average Power Limit (RAPL) power units. */
1419#define MSR_RAPL_POWER_UNIT 0x606
1420
1421/** X2APIC MSR range start. */
1422#define MSR_IA32_X2APIC_START 0x800
1423/** X2APIC MSR - APIC ID Register. */
1424#define MSR_IA32_X2APIC_ID 0x802
1425/** X2APIC MSR - APIC Version Register. */
1426#define MSR_IA32_X2APIC_VERSION 0x803
1427/** X2APIC MSR - Task Priority Register. */
1428#define MSR_IA32_X2APIC_TPR 0x808
1429/** X2APIC MSR - Processor Priority register. */
1430#define MSR_IA32_X2APIC_PPR 0x80A
1431/** X2APIC MSR - End Of Interrupt register. */
1432#define MSR_IA32_X2APIC_EOI 0x80B
1433/** X2APIC MSR - Logical Destination Register. */
1434#define MSR_IA32_X2APIC_LDR 0x80D
1435/** X2APIC MSR - Spurious Interrupt Vector Register. */
1436#define MSR_IA32_X2APIC_SVR 0x80F
1437/** X2APIC MSR - In-service Register (bits 31:0). */
1438#define MSR_IA32_X2APIC_ISR0 0x810
1439/** X2APIC MSR - In-service Register (bits 63:32). */
1440#define MSR_IA32_X2APIC_ISR1 0x811
1441/** X2APIC MSR - In-service Register (bits 95:64). */
1442#define MSR_IA32_X2APIC_ISR2 0x812
1443/** X2APIC MSR - In-service Register (bits 127:96). */
1444#define MSR_IA32_X2APIC_ISR3 0x813
1445/** X2APIC MSR - In-service Register (bits 159:128). */
1446#define MSR_IA32_X2APIC_ISR4 0x814
1447/** X2APIC MSR - In-service Register (bits 191:160). */
1448#define MSR_IA32_X2APIC_ISR5 0x815
1449/** X2APIC MSR - In-service Register (bits 223:192). */
1450#define MSR_IA32_X2APIC_ISR6 0x816
1451/** X2APIC MSR - In-service Register (bits 255:224). */
1452#define MSR_IA32_X2APIC_ISR7 0x817
1453/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1454#define MSR_IA32_X2APIC_TMR0 0x818
1455/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1456#define MSR_IA32_X2APIC_TMR1 0x819
1457/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1458#define MSR_IA32_X2APIC_TMR2 0x81A
1459/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1460#define MSR_IA32_X2APIC_TMR3 0x81B
1461/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1462#define MSR_IA32_X2APIC_TMR4 0x81C
1463/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1464#define MSR_IA32_X2APIC_TMR5 0x81D
1465/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1466#define MSR_IA32_X2APIC_TMR6 0x81E
1467/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1468#define MSR_IA32_X2APIC_TMR7 0x81F
1469/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1470#define MSR_IA32_X2APIC_IRR0 0x820
1471/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1472#define MSR_IA32_X2APIC_IRR1 0x821
1473/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1474#define MSR_IA32_X2APIC_IRR2 0x822
1475/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1476#define MSR_IA32_X2APIC_IRR3 0x823
1477/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1478#define MSR_IA32_X2APIC_IRR4 0x824
1479/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1480#define MSR_IA32_X2APIC_IRR5 0x825
1481/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1482#define MSR_IA32_X2APIC_IRR6 0x826
1483/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1484#define MSR_IA32_X2APIC_IRR7 0x827
1485/** X2APIC MSR - Error Status Register. */
1486#define MSR_IA32_X2APIC_ESR 0x828
1487/** X2APIC MSR - LVT CMCI Register. */
1488#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1489/** X2APIC MSR - Interrupt Command Register. */
1490#define MSR_IA32_X2APIC_ICR 0x830
1491/** X2APIC MSR - LVT Timer Register. */
1492#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1493/** X2APIC MSR - LVT Thermal Sensor Register. */
1494#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1495/** X2APIC MSR - LVT Performance Counter Register. */
1496#define MSR_IA32_X2APIC_LVT_PERF 0x834
1497/** X2APIC MSR - LVT LINT0 Register. */
1498#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1499/** X2APIC MSR - LVT LINT1 Register. */
1500#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1501/** X2APIC MSR - LVT Error Register . */
1502#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1503/** X2APIC MSR - Timer Initial Count Register. */
1504#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1505/** X2APIC MSR - Timer Current Count Register. */
1506#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1507/** X2APIC MSR - Timer Divide Configuration Register. */
1508#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1509/** X2APIC MSR - Self IPI. */
1510#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1511/** X2APIC MSR range end. */
1512#define MSR_IA32_X2APIC_END 0xBFF
1513/** X2APIC MSR - LVT start range. */
1514#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1515/** X2APIC MSR - LVT end range (inclusive). */
1516#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1517
1518/** K6 EFER - Extended Feature Enable Register. */
1519#define MSR_K6_EFER UINT32_C(0xc0000080)
1520/** @todo document EFER */
1521/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1522#define MSR_K6_EFER_SCE RT_BIT_32(0)
1523/** Bit 8 - LME - Long mode enabled. (R/W) */
1524#define MSR_K6_EFER_LME RT_BIT_32(8)
1525/** Bit 10 - LMA - Long mode active. (R) */
1526#define MSR_K6_EFER_LMA RT_BIT_32(10)
1527/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1528#define MSR_K6_EFER_NXE RT_BIT_32(11)
1529#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1530/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1531#define MSR_K6_EFER_SVME RT_BIT_32(12)
1532/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1533#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1534/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1535#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1536/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1537#define MSR_K6_EFER_TCE RT_BIT_32(15)
1538/** K6 STAR - SYSCALL/RET targets. */
1539#define MSR_K6_STAR UINT32_C(0xc0000081)
1540/** Shift value for getting the SYSRET CS and SS value. */
1541#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1542/** Shift value for getting the SYSCALL CS and SS value. */
1543#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1544/** Selector mask for use after shifting. */
1545#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1546/** The mask which give the SYSCALL EIP. */
1547#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1548/** K6 WHCR - Write Handling Control Register. */
1549#define MSR_K6_WHCR UINT32_C(0xc0000082)
1550/** K6 UWCCR - UC/WC Cacheability Control Register. */
1551#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1552/** K6 PSOR - Processor State Observability Register. */
1553#define MSR_K6_PSOR UINT32_C(0xc0000087)
1554/** K6 PFIR - Page Flush/Invalidate Register. */
1555#define MSR_K6_PFIR UINT32_C(0xc0000088)
1556
1557/** Performance counter MSRs. (AMD only) */
1558#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1559#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1560#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1561#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1562#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1563#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1564#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1565#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1566
1567/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1568#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1569/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1570#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1571/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1572#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1573/** K8 FS.base - The 64-bit base FS register. */
1574#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1575/** K8 GS.base - The 64-bit base GS register. */
1576#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1577/** K8 KernelGSbase - Used with SWAPGS. */
1578#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1579/** K8 TSC_AUX - Used with RDTSCP. */
1580#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1581#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1582#define MSR_K8_HWCR UINT32_C(0xc0010015)
1583#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1584#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1585#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1586#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1587#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1588#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1589/** North bridge config? See BIOS & Kernel dev guides for
1590 * details. */
1591#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1592
1593/** Hypertransport interrupt pending register.
1594 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1595#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1596
1597/** SVM Control. */
1598#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1599/** Disables HDT (Hardware Debug Tool) and certain internal debug
1600 * features. */
1601#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1602/** If set, non-intercepted INIT signals are converted to \#SX
1603 * exceptions. */
1604#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1605/** Disables A20 masking. */
1606#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1607/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1608#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1609/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1610 * clear, EFER.SVME can be written normally. */
1611#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1612
1613#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1614#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1615/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1616 * host state during world switch. */
1617#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1618
1619/** @} */
1620
1621
1622/** @name Page Table / Directory / Directory Pointers / L4.
1623 * @{
1624 */
1625
1626/** Page table/directory entry as an unsigned integer. */
1627typedef uint32_t X86PGUINT;
1628/** Pointer to a page table/directory table entry as an unsigned integer. */
1629typedef X86PGUINT *PX86PGUINT;
1630/** Pointer to an const page table/directory table entry as an unsigned integer. */
1631typedef X86PGUINT const *PCX86PGUINT;
1632
1633/** Number of entries in a 32-bit PT/PD. */
1634#define X86_PG_ENTRIES 1024
1635
1636
1637/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1638typedef uint64_t X86PGPAEUINT;
1639/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1640typedef X86PGPAEUINT *PX86PGPAEUINT;
1641/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1642typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1643
1644/** Number of entries in a PAE PT/PD. */
1645#define X86_PG_PAE_ENTRIES 512
1646/** Number of entries in a PAE PDPT. */
1647#define X86_PG_PAE_PDPE_ENTRIES 4
1648
1649/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1650#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1651/** Number of entries in an AMD64 PDPT.
1652 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1653#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1654
1655/** The size of a default page. */
1656#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1657/** The page shift of a default page. */
1658#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1659/** The default page offset mask. */
1660#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1661/** The default page base mask for virtual addresses. */
1662#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1663/** The default page base mask for virtual addresses - 32bit version. */
1664#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1665
1666/** The size of a 4KB page. */
1667#define X86_PAGE_4K_SIZE _4K
1668/** The page shift of a 4KB page. */
1669#define X86_PAGE_4K_SHIFT 12
1670/** The 4KB page offset mask. */
1671#define X86_PAGE_4K_OFFSET_MASK 0xfff
1672/** The 4KB page base mask for virtual addresses. */
1673#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1674/** The 4KB page base mask for virtual addresses - 32bit version. */
1675#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1676
1677/** The size of a 2MB page. */
1678#define X86_PAGE_2M_SIZE _2M
1679/** The page shift of a 2MB page. */
1680#define X86_PAGE_2M_SHIFT 21
1681/** The 2MB page offset mask. */
1682#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1683/** The 2MB page base mask for virtual addresses. */
1684#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1685/** The 2MB page base mask for virtual addresses - 32bit version. */
1686#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1687
1688/** The size of a 4MB page. */
1689#define X86_PAGE_4M_SIZE _4M
1690/** The page shift of a 4MB page. */
1691#define X86_PAGE_4M_SHIFT 22
1692/** The 4MB page offset mask. */
1693#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1694/** The 4MB page base mask for virtual addresses. */
1695#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1696/** The 4MB page base mask for virtual addresses - 32bit version. */
1697#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1698
1699/**
1700 * Check if the given address is canonical.
1701 */
1702#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1703
1704
1705/** @name Page Table Entry
1706 * @{
1707 */
1708/** Bit 0 - P - Present bit. */
1709#define X86_PTE_BIT_P 0
1710/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1711#define X86_PTE_BIT_RW 1
1712/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1713#define X86_PTE_BIT_US 2
1714/** Bit 3 - PWT - Page level write thru bit. */
1715#define X86_PTE_BIT_PWT 3
1716/** Bit 4 - PCD - Page level cache disable bit. */
1717#define X86_PTE_BIT_PCD 4
1718/** Bit 5 - A - Access bit. */
1719#define X86_PTE_BIT_A 5
1720/** Bit 6 - D - Dirty bit. */
1721#define X86_PTE_BIT_D 6
1722/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1723#define X86_PTE_BIT_PAT 7
1724/** Bit 8 - G - Global flag. */
1725#define X86_PTE_BIT_G 8
1726/** Bits 63 - NX - PAE/LM - No execution flag. */
1727#define X86_PTE_PAE_BIT_NX 63
1728
1729/** Bit 0 - P - Present bit mask. */
1730#define X86_PTE_P RT_BIT_32(0)
1731/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1732#define X86_PTE_RW RT_BIT_32(1)
1733/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1734#define X86_PTE_US RT_BIT_32(2)
1735/** Bit 3 - PWT - Page level write thru bit mask. */
1736#define X86_PTE_PWT RT_BIT_32(3)
1737/** Bit 4 - PCD - Page level cache disable bit mask. */
1738#define X86_PTE_PCD RT_BIT_32(4)
1739/** Bit 5 - A - Access bit mask. */
1740#define X86_PTE_A RT_BIT_32(5)
1741/** Bit 6 - D - Dirty bit mask. */
1742#define X86_PTE_D RT_BIT_32(6)
1743/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1744#define X86_PTE_PAT RT_BIT_32(7)
1745/** Bit 8 - G - Global bit mask. */
1746#define X86_PTE_G RT_BIT_32(8)
1747
1748/** Bits 9-11 - - Available for use to system software. */
1749#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1750/** Bits 12-31 - - Physical Page number of the next level. */
1751#define X86_PTE_PG_MASK ( 0xfffff000 )
1752
1753/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1754#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1755/** Bits 63 - NX - PAE/LM - No execution flag. */
1756#define X86_PTE_PAE_NX RT_BIT_64(63)
1757/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1758#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1759/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1760#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1761/** No bits - - LM - MBZ bits when NX is active. */
1762#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1763/** Bits 63 - - LM - MBZ bits when no NX. */
1764#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1765
1766/**
1767 * Page table entry.
1768 */
1769typedef struct X86PTEBITS
1770{
1771 /** Flags whether(=1) or not the page is present. */
1772 uint32_t u1Present : 1;
1773 /** Read(=0) / Write(=1) flag. */
1774 uint32_t u1Write : 1;
1775 /** User(=1) / Supervisor (=0) flag. */
1776 uint32_t u1User : 1;
1777 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1778 uint32_t u1WriteThru : 1;
1779 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1780 uint32_t u1CacheDisable : 1;
1781 /** Accessed flag.
1782 * Indicates that the page have been read or written to. */
1783 uint32_t u1Accessed : 1;
1784 /** Dirty flag.
1785 * Indicates that the page has been written to. */
1786 uint32_t u1Dirty : 1;
1787 /** Reserved / If PAT enabled, bit 2 of the index. */
1788 uint32_t u1PAT : 1;
1789 /** Global flag. (Ignored in all but final level.) */
1790 uint32_t u1Global : 1;
1791 /** Available for use to system software. */
1792 uint32_t u3Available : 3;
1793 /** Physical Page number of the next level. */
1794 uint32_t u20PageNo : 20;
1795} X86PTEBITS;
1796#ifndef VBOX_FOR_DTRACE_LIB
1797AssertCompileSize(X86PTEBITS, 4);
1798#endif
1799/** Pointer to a page table entry. */
1800typedef X86PTEBITS *PX86PTEBITS;
1801/** Pointer to a const page table entry. */
1802typedef const X86PTEBITS *PCX86PTEBITS;
1803
1804/**
1805 * Page table entry.
1806 */
1807typedef union X86PTE
1808{
1809 /** Unsigned integer view */
1810 X86PGUINT u;
1811 /** Bit field view. */
1812 X86PTEBITS n;
1813 /** 32-bit view. */
1814 uint32_t au32[1];
1815 /** 16-bit view. */
1816 uint16_t au16[2];
1817 /** 8-bit view. */
1818 uint8_t au8[4];
1819} X86PTE;
1820#ifndef VBOX_FOR_DTRACE_LIB
1821AssertCompileSize(X86PTE, 4);
1822#endif
1823/** Pointer to a page table entry. */
1824typedef X86PTE *PX86PTE;
1825/** Pointer to a const page table entry. */
1826typedef const X86PTE *PCX86PTE;
1827
1828
1829/**
1830 * PAE page table entry.
1831 */
1832typedef struct X86PTEPAEBITS
1833{
1834 /** Flags whether(=1) or not the page is present. */
1835 uint32_t u1Present : 1;
1836 /** Read(=0) / Write(=1) flag. */
1837 uint32_t u1Write : 1;
1838 /** User(=1) / Supervisor(=0) flag. */
1839 uint32_t u1User : 1;
1840 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1841 uint32_t u1WriteThru : 1;
1842 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1843 uint32_t u1CacheDisable : 1;
1844 /** Accessed flag.
1845 * Indicates that the page have been read or written to. */
1846 uint32_t u1Accessed : 1;
1847 /** Dirty flag.
1848 * Indicates that the page has been written to. */
1849 uint32_t u1Dirty : 1;
1850 /** Reserved / If PAT enabled, bit 2 of the index. */
1851 uint32_t u1PAT : 1;
1852 /** Global flag. (Ignored in all but final level.) */
1853 uint32_t u1Global : 1;
1854 /** Available for use to system software. */
1855 uint32_t u3Available : 3;
1856 /** Physical Page number of the next level - Low Part. Don't use this. */
1857 uint32_t u20PageNoLow : 20;
1858 /** Physical Page number of the next level - High Part. Don't use this. */
1859 uint32_t u20PageNoHigh : 20;
1860 /** MBZ bits */
1861 uint32_t u11Reserved : 11;
1862 /** No Execute flag. */
1863 uint32_t u1NoExecute : 1;
1864} X86PTEPAEBITS;
1865#ifndef VBOX_FOR_DTRACE_LIB
1866AssertCompileSize(X86PTEPAEBITS, 8);
1867#endif
1868/** Pointer to a page table entry. */
1869typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1870/** Pointer to a page table entry. */
1871typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1872
1873/**
1874 * PAE Page table entry.
1875 */
1876typedef union X86PTEPAE
1877{
1878 /** Unsigned integer view */
1879 X86PGPAEUINT u;
1880 /** Bit field view. */
1881 X86PTEPAEBITS n;
1882 /** 32-bit view. */
1883 uint32_t au32[2];
1884 /** 16-bit view. */
1885 uint16_t au16[4];
1886 /** 8-bit view. */
1887 uint8_t au8[8];
1888} X86PTEPAE;
1889#ifndef VBOX_FOR_DTRACE_LIB
1890AssertCompileSize(X86PTEPAE, 8);
1891#endif
1892/** Pointer to a PAE page table entry. */
1893typedef X86PTEPAE *PX86PTEPAE;
1894/** Pointer to a const PAE page table entry. */
1895typedef const X86PTEPAE *PCX86PTEPAE;
1896/** @} */
1897
1898/**
1899 * Page table.
1900 */
1901typedef struct X86PT
1902{
1903 /** PTE Array. */
1904 X86PTE a[X86_PG_ENTRIES];
1905} X86PT;
1906#ifndef VBOX_FOR_DTRACE_LIB
1907AssertCompileSize(X86PT, 4096);
1908#endif
1909/** Pointer to a page table. */
1910typedef X86PT *PX86PT;
1911/** Pointer to a const page table. */
1912typedef const X86PT *PCX86PT;
1913
1914/** The page shift to get the PT index. */
1915#define X86_PT_SHIFT 12
1916/** The PT index mask (apply to a shifted page address). */
1917#define X86_PT_MASK 0x3ff
1918
1919
1920/**
1921 * Page directory.
1922 */
1923typedef struct X86PTPAE
1924{
1925 /** PTE Array. */
1926 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1927} X86PTPAE;
1928#ifndef VBOX_FOR_DTRACE_LIB
1929AssertCompileSize(X86PTPAE, 4096);
1930#endif
1931/** Pointer to a page table. */
1932typedef X86PTPAE *PX86PTPAE;
1933/** Pointer to a const page table. */
1934typedef const X86PTPAE *PCX86PTPAE;
1935
1936/** The page shift to get the PA PTE index. */
1937#define X86_PT_PAE_SHIFT 12
1938/** The PAE PT index mask (apply to a shifted page address). */
1939#define X86_PT_PAE_MASK 0x1ff
1940
1941
1942/** @name 4KB Page Directory Entry
1943 * @{
1944 */
1945/** Bit 0 - P - Present bit. */
1946#define X86_PDE_P RT_BIT_32(0)
1947/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1948#define X86_PDE_RW RT_BIT_32(1)
1949/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1950#define X86_PDE_US RT_BIT_32(2)
1951/** Bit 3 - PWT - Page level write thru bit. */
1952#define X86_PDE_PWT RT_BIT_32(3)
1953/** Bit 4 - PCD - Page level cache disable bit. */
1954#define X86_PDE_PCD RT_BIT_32(4)
1955/** Bit 5 - A - Access bit. */
1956#define X86_PDE_A RT_BIT_32(5)
1957/** Bit 7 - PS - Page size attribute.
1958 * Clear mean 4KB pages, set means large pages (2/4MB). */
1959#define X86_PDE_PS RT_BIT_32(7)
1960/** Bits 9-11 - - Available for use to system software. */
1961#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1962/** Bits 12-31 - - Physical Page number of the next level. */
1963#define X86_PDE_PG_MASK ( 0xfffff000 )
1964
1965/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1966#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1967/** Bits 63 - NX - PAE/LM - No execution flag. */
1968#define X86_PDE_PAE_NX RT_BIT_64(63)
1969/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1970#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1971/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1972#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1973/** Bit 7 - - LM - MBZ bits when NX is active. */
1974#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1975/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1976#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1977
1978/**
1979 * Page directory entry.
1980 */
1981typedef struct X86PDEBITS
1982{
1983 /** Flags whether(=1) or not the page is present. */
1984 uint32_t u1Present : 1;
1985 /** Read(=0) / Write(=1) flag. */
1986 uint32_t u1Write : 1;
1987 /** User(=1) / Supervisor (=0) flag. */
1988 uint32_t u1User : 1;
1989 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1990 uint32_t u1WriteThru : 1;
1991 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1992 uint32_t u1CacheDisable : 1;
1993 /** Accessed flag.
1994 * Indicates that the page has been read or written to. */
1995 uint32_t u1Accessed : 1;
1996 /** Reserved / Ignored (dirty bit). */
1997 uint32_t u1Reserved0 : 1;
1998 /** Size bit if PSE is enabled - in any event it's 0. */
1999 uint32_t u1Size : 1;
2000 /** Reserved / Ignored (global bit). */
2001 uint32_t u1Reserved1 : 1;
2002 /** Available for use to system software. */
2003 uint32_t u3Available : 3;
2004 /** Physical Page number of the next level. */
2005 uint32_t u20PageNo : 20;
2006} X86PDEBITS;
2007#ifndef VBOX_FOR_DTRACE_LIB
2008AssertCompileSize(X86PDEBITS, 4);
2009#endif
2010/** Pointer to a page directory entry. */
2011typedef X86PDEBITS *PX86PDEBITS;
2012/** Pointer to a const page directory entry. */
2013typedef const X86PDEBITS *PCX86PDEBITS;
2014
2015
2016/**
2017 * PAE page directory entry.
2018 */
2019typedef struct X86PDEPAEBITS
2020{
2021 /** Flags whether(=1) or not the page is present. */
2022 uint32_t u1Present : 1;
2023 /** Read(=0) / Write(=1) flag. */
2024 uint32_t u1Write : 1;
2025 /** User(=1) / Supervisor (=0) flag. */
2026 uint32_t u1User : 1;
2027 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2028 uint32_t u1WriteThru : 1;
2029 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2030 uint32_t u1CacheDisable : 1;
2031 /** Accessed flag.
2032 * Indicates that the page has been read or written to. */
2033 uint32_t u1Accessed : 1;
2034 /** Reserved / Ignored (dirty bit). */
2035 uint32_t u1Reserved0 : 1;
2036 /** Size bit if PSE is enabled - in any event it's 0. */
2037 uint32_t u1Size : 1;
2038 /** Reserved / Ignored (global bit). / */
2039 uint32_t u1Reserved1 : 1;
2040 /** Available for use to system software. */
2041 uint32_t u3Available : 3;
2042 /** Physical Page number of the next level - Low Part. Don't use! */
2043 uint32_t u20PageNoLow : 20;
2044 /** Physical Page number of the next level - High Part. Don't use! */
2045 uint32_t u20PageNoHigh : 20;
2046 /** MBZ bits */
2047 uint32_t u11Reserved : 11;
2048 /** No Execute flag. */
2049 uint32_t u1NoExecute : 1;
2050} X86PDEPAEBITS;
2051#ifndef VBOX_FOR_DTRACE_LIB
2052AssertCompileSize(X86PDEPAEBITS, 8);
2053#endif
2054/** Pointer to a page directory entry. */
2055typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2056/** Pointer to a const page directory entry. */
2057typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2058
2059/** @} */
2060
2061
2062/** @name 2/4MB Page Directory Entry
2063 * @{
2064 */
2065/** Bit 0 - P - Present bit. */
2066#define X86_PDE4M_P RT_BIT_32(0)
2067/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2068#define X86_PDE4M_RW RT_BIT_32(1)
2069/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2070#define X86_PDE4M_US RT_BIT_32(2)
2071/** Bit 3 - PWT - Page level write thru bit. */
2072#define X86_PDE4M_PWT RT_BIT_32(3)
2073/** Bit 4 - PCD - Page level cache disable bit. */
2074#define X86_PDE4M_PCD RT_BIT_32(4)
2075/** Bit 5 - A - Access bit. */
2076#define X86_PDE4M_A RT_BIT_32(5)
2077/** Bit 6 - D - Dirty bit. */
2078#define X86_PDE4M_D RT_BIT_32(6)
2079/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2080#define X86_PDE4M_PS RT_BIT_32(7)
2081/** Bit 8 - G - Global flag. */
2082#define X86_PDE4M_G RT_BIT_32(8)
2083/** Bits 9-11 - AVL - Available for use to system software. */
2084#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2085/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2086#define X86_PDE4M_PAT RT_BIT_32(12)
2087/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2088#define X86_PDE4M_PAT_SHIFT (12 - 7)
2089/** Bits 22-31 - - Physical Page number. */
2090#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2091/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2092#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2093/** The number of bits to the high part of the page number. */
2094#define X86_PDE4M_PG_HIGH_SHIFT 19
2095/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2096#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2097
2098/** Bits 21-51 - - PAE/LM - Physical Page number.
2099 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2100#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2101/** Bits 63 - NX - PAE/LM - No execution flag. */
2102#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2103/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2104#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2105/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2106#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2107/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2108#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2109/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2110#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2111
2112/**
2113 * 4MB page directory entry.
2114 */
2115typedef struct X86PDE4MBITS
2116{
2117 /** Flags whether(=1) or not the page is present. */
2118 uint32_t u1Present : 1;
2119 /** Read(=0) / Write(=1) flag. */
2120 uint32_t u1Write : 1;
2121 /** User(=1) / Supervisor (=0) flag. */
2122 uint32_t u1User : 1;
2123 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2124 uint32_t u1WriteThru : 1;
2125 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2126 uint32_t u1CacheDisable : 1;
2127 /** Accessed flag.
2128 * Indicates that the page have been read or written to. */
2129 uint32_t u1Accessed : 1;
2130 /** Dirty flag.
2131 * Indicates that the page has been written to. */
2132 uint32_t u1Dirty : 1;
2133 /** Page size flag - always 1 for 4MB entries. */
2134 uint32_t u1Size : 1;
2135 /** Global flag. */
2136 uint32_t u1Global : 1;
2137 /** Available for use to system software. */
2138 uint32_t u3Available : 3;
2139 /** Reserved / If PAT enabled, bit 2 of the index. */
2140 uint32_t u1PAT : 1;
2141 /** Bits 32-39 of the page number on AMD64.
2142 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2143 uint32_t u8PageNoHigh : 8;
2144 /** Reserved. */
2145 uint32_t u1Reserved : 1;
2146 /** Physical Page number of the page. */
2147 uint32_t u10PageNo : 10;
2148} X86PDE4MBITS;
2149#ifndef VBOX_FOR_DTRACE_LIB
2150AssertCompileSize(X86PDE4MBITS, 4);
2151#endif
2152/** Pointer to a page table entry. */
2153typedef X86PDE4MBITS *PX86PDE4MBITS;
2154/** Pointer to a const page table entry. */
2155typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2156
2157
2158/**
2159 * 2MB PAE page directory entry.
2160 */
2161typedef struct X86PDE2MPAEBITS
2162{
2163 /** Flags whether(=1) or not the page is present. */
2164 uint32_t u1Present : 1;
2165 /** Read(=0) / Write(=1) flag. */
2166 uint32_t u1Write : 1;
2167 /** User(=1) / Supervisor(=0) flag. */
2168 uint32_t u1User : 1;
2169 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2170 uint32_t u1WriteThru : 1;
2171 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2172 uint32_t u1CacheDisable : 1;
2173 /** Accessed flag.
2174 * Indicates that the page have been read or written to. */
2175 uint32_t u1Accessed : 1;
2176 /** Dirty flag.
2177 * Indicates that the page has been written to. */
2178 uint32_t u1Dirty : 1;
2179 /** Page size flag - always 1 for 2MB entries. */
2180 uint32_t u1Size : 1;
2181 /** Global flag. */
2182 uint32_t u1Global : 1;
2183 /** Available for use to system software. */
2184 uint32_t u3Available : 3;
2185 /** Reserved / If PAT enabled, bit 2 of the index. */
2186 uint32_t u1PAT : 1;
2187 /** Reserved. */
2188 uint32_t u9Reserved : 9;
2189 /** Physical Page number of the next level - Low part. Don't use! */
2190 uint32_t u10PageNoLow : 10;
2191 /** Physical Page number of the next level - High part. Don't use! */
2192 uint32_t u20PageNoHigh : 20;
2193 /** MBZ bits */
2194 uint32_t u11Reserved : 11;
2195 /** No Execute flag. */
2196 uint32_t u1NoExecute : 1;
2197} X86PDE2MPAEBITS;
2198#ifndef VBOX_FOR_DTRACE_LIB
2199AssertCompileSize(X86PDE2MPAEBITS, 8);
2200#endif
2201/** Pointer to a 2MB PAE page table entry. */
2202typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2203/** Pointer to a 2MB PAE page table entry. */
2204typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2205
2206/** @} */
2207
2208/**
2209 * Page directory entry.
2210 */
2211typedef union X86PDE
2212{
2213 /** Unsigned integer view. */
2214 X86PGUINT u;
2215 /** Normal view. */
2216 X86PDEBITS n;
2217 /** 4MB view (big). */
2218 X86PDE4MBITS b;
2219 /** 8 bit unsigned integer view. */
2220 uint8_t au8[4];
2221 /** 16 bit unsigned integer view. */
2222 uint16_t au16[2];
2223 /** 32 bit unsigned integer view. */
2224 uint32_t au32[1];
2225} X86PDE;
2226#ifndef VBOX_FOR_DTRACE_LIB
2227AssertCompileSize(X86PDE, 4);
2228#endif
2229/** Pointer to a page directory entry. */
2230typedef X86PDE *PX86PDE;
2231/** Pointer to a const page directory entry. */
2232typedef const X86PDE *PCX86PDE;
2233
2234/**
2235 * PAE page directory entry.
2236 */
2237typedef union X86PDEPAE
2238{
2239 /** Unsigned integer view. */
2240 X86PGPAEUINT u;
2241 /** Normal view. */
2242 X86PDEPAEBITS n;
2243 /** 2MB page view (big). */
2244 X86PDE2MPAEBITS b;
2245 /** 8 bit unsigned integer view. */
2246 uint8_t au8[8];
2247 /** 16 bit unsigned integer view. */
2248 uint16_t au16[4];
2249 /** 32 bit unsigned integer view. */
2250 uint32_t au32[2];
2251} X86PDEPAE;
2252#ifndef VBOX_FOR_DTRACE_LIB
2253AssertCompileSize(X86PDEPAE, 8);
2254#endif
2255/** Pointer to a page directory entry. */
2256typedef X86PDEPAE *PX86PDEPAE;
2257/** Pointer to a const page directory entry. */
2258typedef const X86PDEPAE *PCX86PDEPAE;
2259
2260/**
2261 * Page directory.
2262 */
2263typedef struct X86PD
2264{
2265 /** PDE Array. */
2266 X86PDE a[X86_PG_ENTRIES];
2267} X86PD;
2268#ifndef VBOX_FOR_DTRACE_LIB
2269AssertCompileSize(X86PD, 4096);
2270#endif
2271/** Pointer to a page directory. */
2272typedef X86PD *PX86PD;
2273/** Pointer to a const page directory. */
2274typedef const X86PD *PCX86PD;
2275
2276/** The page shift to get the PD index. */
2277#define X86_PD_SHIFT 22
2278/** The PD index mask (apply to a shifted page address). */
2279#define X86_PD_MASK 0x3ff
2280
2281
2282/**
2283 * PAE page directory.
2284 */
2285typedef struct X86PDPAE
2286{
2287 /** PDE Array. */
2288 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2289} X86PDPAE;
2290#ifndef VBOX_FOR_DTRACE_LIB
2291AssertCompileSize(X86PDPAE, 4096);
2292#endif
2293/** Pointer to a PAE page directory. */
2294typedef X86PDPAE *PX86PDPAE;
2295/** Pointer to a const PAE page directory. */
2296typedef const X86PDPAE *PCX86PDPAE;
2297
2298/** The page shift to get the PAE PD index. */
2299#define X86_PD_PAE_SHIFT 21
2300/** The PAE PD index mask (apply to a shifted page address). */
2301#define X86_PD_PAE_MASK 0x1ff
2302
2303
2304/** @name Page Directory Pointer Table Entry (PAE)
2305 * @{
2306 */
2307/** Bit 0 - P - Present bit. */
2308#define X86_PDPE_P RT_BIT_32(0)
2309/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2310#define X86_PDPE_RW RT_BIT_32(1)
2311/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2312#define X86_PDPE_US RT_BIT_32(2)
2313/** Bit 3 - PWT - Page level write thru bit. */
2314#define X86_PDPE_PWT RT_BIT_32(3)
2315/** Bit 4 - PCD - Page level cache disable bit. */
2316#define X86_PDPE_PCD RT_BIT_32(4)
2317/** Bit 5 - A - Access bit. Long Mode only. */
2318#define X86_PDPE_A RT_BIT_32(5)
2319/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2320#define X86_PDPE_LM_PS RT_BIT_32(7)
2321/** Bits 9-11 - - Available for use to system software. */
2322#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2323/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2324#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2325/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2326#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2327/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2328#define X86_PDPE_LM_NX RT_BIT_64(63)
2329/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2330#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2331/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2332#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2333/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2334#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2335/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2336#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2337
2338
2339/**
2340 * Page directory pointer table entry.
2341 */
2342typedef struct X86PDPEBITS
2343{
2344 /** Flags whether(=1) or not the page is present. */
2345 uint32_t u1Present : 1;
2346 /** Chunk of reserved bits. */
2347 uint32_t u2Reserved : 2;
2348 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2349 uint32_t u1WriteThru : 1;
2350 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2351 uint32_t u1CacheDisable : 1;
2352 /** Chunk of reserved bits. */
2353 uint32_t u4Reserved : 4;
2354 /** Available for use to system software. */
2355 uint32_t u3Available : 3;
2356 /** Physical Page number of the next level - Low Part. Don't use! */
2357 uint32_t u20PageNoLow : 20;
2358 /** Physical Page number of the next level - High Part. Don't use! */
2359 uint32_t u20PageNoHigh : 20;
2360 /** MBZ bits */
2361 uint32_t u12Reserved : 12;
2362} X86PDPEBITS;
2363#ifndef VBOX_FOR_DTRACE_LIB
2364AssertCompileSize(X86PDPEBITS, 8);
2365#endif
2366/** Pointer to a page directory pointer table entry. */
2367typedef X86PDPEBITS *PX86PTPEBITS;
2368/** Pointer to a const page directory pointer table entry. */
2369typedef const X86PDPEBITS *PCX86PTPEBITS;
2370
2371/**
2372 * Page directory pointer table entry. AMD64 version
2373 */
2374typedef struct X86PDPEAMD64BITS
2375{
2376 /** Flags whether(=1) or not the page is present. */
2377 uint32_t u1Present : 1;
2378 /** Read(=0) / Write(=1) flag. */
2379 uint32_t u1Write : 1;
2380 /** User(=1) / Supervisor (=0) flag. */
2381 uint32_t u1User : 1;
2382 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2383 uint32_t u1WriteThru : 1;
2384 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2385 uint32_t u1CacheDisable : 1;
2386 /** Accessed flag.
2387 * Indicates that the page have been read or written to. */
2388 uint32_t u1Accessed : 1;
2389 /** Chunk of reserved bits. */
2390 uint32_t u3Reserved : 3;
2391 /** Available for use to system software. */
2392 uint32_t u3Available : 3;
2393 /** Physical Page number of the next level - Low Part. Don't use! */
2394 uint32_t u20PageNoLow : 20;
2395 /** Physical Page number of the next level - High Part. Don't use! */
2396 uint32_t u20PageNoHigh : 20;
2397 /** MBZ bits */
2398 uint32_t u11Reserved : 11;
2399 /** No Execute flag. */
2400 uint32_t u1NoExecute : 1;
2401} X86PDPEAMD64BITS;
2402#ifndef VBOX_FOR_DTRACE_LIB
2403AssertCompileSize(X86PDPEAMD64BITS, 8);
2404#endif
2405/** Pointer to a page directory pointer table entry. */
2406typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2407/** Pointer to a const page directory pointer table entry. */
2408typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2409
2410/**
2411 * Page directory pointer table entry for 1GB page. (AMD64 only)
2412 */
2413typedef struct X86PDPE1GB
2414{
2415 /** 0: Flags whether(=1) or not the page is present. */
2416 uint32_t u1Present : 1;
2417 /** 1: Read(=0) / Write(=1) flag. */
2418 uint32_t u1Write : 1;
2419 /** 2: User(=1) / Supervisor (=0) flag. */
2420 uint32_t u1User : 1;
2421 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2422 uint32_t u1WriteThru : 1;
2423 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2424 uint32_t u1CacheDisable : 1;
2425 /** 5: Accessed flag.
2426 * Indicates that the page have been read or written to. */
2427 uint32_t u1Accessed : 1;
2428 /** 6: Dirty flag for 1GB pages. */
2429 uint32_t u1Dirty : 1;
2430 /** 7: Indicates 1GB page if set. */
2431 uint32_t u1Size : 1;
2432 /** 8: Global 1GB page. */
2433 uint32_t u1Global: 1;
2434 /** 9-11: Available for use to system software. */
2435 uint32_t u3Available : 3;
2436 /** 12: PAT bit for 1GB page. */
2437 uint32_t u1PAT : 1;
2438 /** 13-29: MBZ bits. */
2439 uint32_t u17Reserved : 17;
2440 /** 30-31: Physical page number - Low Part. Don't use! */
2441 uint32_t u2PageNoLow : 2;
2442 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2443 uint32_t u20PageNoHigh : 20;
2444 /** 52-62: MBZ bits */
2445 uint32_t u11Reserved : 11;
2446 /** 63: No Execute flag. */
2447 uint32_t u1NoExecute : 1;
2448} X86PDPE1GB;
2449#ifndef VBOX_FOR_DTRACE_LIB
2450AssertCompileSize(X86PDPE1GB, 8);
2451#endif
2452/** Pointer to a page directory pointer table entry for a 1GB page. */
2453typedef X86PDPE1GB *PX86PDPE1GB;
2454/** Pointer to a const page directory pointer table entry for a 1GB page. */
2455typedef const X86PDPE1GB *PCX86PDPE1GB;
2456
2457/**
2458 * Page directory pointer table entry.
2459 */
2460typedef union X86PDPE
2461{
2462 /** Unsigned integer view. */
2463 X86PGPAEUINT u;
2464 /** Normal view. */
2465 X86PDPEBITS n;
2466 /** AMD64 view. */
2467 X86PDPEAMD64BITS lm;
2468 /** AMD64 big view. */
2469 X86PDPE1GB b;
2470 /** 8 bit unsigned integer view. */
2471 uint8_t au8[8];
2472 /** 16 bit unsigned integer view. */
2473 uint16_t au16[4];
2474 /** 32 bit unsigned integer view. */
2475 uint32_t au32[2];
2476} X86PDPE;
2477#ifndef VBOX_FOR_DTRACE_LIB
2478AssertCompileSize(X86PDPE, 8);
2479#endif
2480/** Pointer to a page directory pointer table entry. */
2481typedef X86PDPE *PX86PDPE;
2482/** Pointer to a const page directory pointer table entry. */
2483typedef const X86PDPE *PCX86PDPE;
2484
2485
2486/**
2487 * Page directory pointer table.
2488 */
2489typedef struct X86PDPT
2490{
2491 /** PDE Array. */
2492 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2493} X86PDPT;
2494#ifndef VBOX_FOR_DTRACE_LIB
2495AssertCompileSize(X86PDPT, 4096);
2496#endif
2497/** Pointer to a page directory pointer table. */
2498typedef X86PDPT *PX86PDPT;
2499/** Pointer to a const page directory pointer table. */
2500typedef const X86PDPT *PCX86PDPT;
2501
2502/** The page shift to get the PDPT index. */
2503#define X86_PDPT_SHIFT 30
2504/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2505#define X86_PDPT_MASK_PAE 0x3
2506/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2507#define X86_PDPT_MASK_AMD64 0x1ff
2508
2509/** @} */
2510
2511
2512/** @name Page Map Level-4 Entry (Long Mode PAE)
2513 * @{
2514 */
2515/** Bit 0 - P - Present bit. */
2516#define X86_PML4E_P RT_BIT_32(0)
2517/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2518#define X86_PML4E_RW RT_BIT_32(1)
2519/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2520#define X86_PML4E_US RT_BIT_32(2)
2521/** Bit 3 - PWT - Page level write thru bit. */
2522#define X86_PML4E_PWT RT_BIT_32(3)
2523/** Bit 4 - PCD - Page level cache disable bit. */
2524#define X86_PML4E_PCD RT_BIT_32(4)
2525/** Bit 5 - A - Access bit. */
2526#define X86_PML4E_A RT_BIT_32(5)
2527/** Bits 9-11 - - Available for use to system software. */
2528#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2529/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2530#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2531/** Bits 8, 7 - - MBZ bits when NX is active. */
2532#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2533/** Bits 63, 7 - - MBZ bits when no NX. */
2534#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2535/** Bits 63 - NX - PAE - No execution flag. */
2536#define X86_PML4E_NX RT_BIT_64(63)
2537
2538/**
2539 * Page Map Level-4 Entry
2540 */
2541typedef struct X86PML4EBITS
2542{
2543 /** Flags whether(=1) or not the page is present. */
2544 uint32_t u1Present : 1;
2545 /** Read(=0) / Write(=1) flag. */
2546 uint32_t u1Write : 1;
2547 /** User(=1) / Supervisor (=0) flag. */
2548 uint32_t u1User : 1;
2549 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2550 uint32_t u1WriteThru : 1;
2551 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2552 uint32_t u1CacheDisable : 1;
2553 /** Accessed flag.
2554 * Indicates that the page have been read or written to. */
2555 uint32_t u1Accessed : 1;
2556 /** Chunk of reserved bits. */
2557 uint32_t u3Reserved : 3;
2558 /** Available for use to system software. */
2559 uint32_t u3Available : 3;
2560 /** Physical Page number of the next level - Low Part. Don't use! */
2561 uint32_t u20PageNoLow : 20;
2562 /** Physical Page number of the next level - High Part. Don't use! */
2563 uint32_t u20PageNoHigh : 20;
2564 /** MBZ bits */
2565 uint32_t u11Reserved : 11;
2566 /** No Execute flag. */
2567 uint32_t u1NoExecute : 1;
2568} X86PML4EBITS;
2569#ifndef VBOX_FOR_DTRACE_LIB
2570AssertCompileSize(X86PML4EBITS, 8);
2571#endif
2572/** Pointer to a page map level-4 entry. */
2573typedef X86PML4EBITS *PX86PML4EBITS;
2574/** Pointer to a const page map level-4 entry. */
2575typedef const X86PML4EBITS *PCX86PML4EBITS;
2576
2577/**
2578 * Page Map Level-4 Entry.
2579 */
2580typedef union X86PML4E
2581{
2582 /** Unsigned integer view. */
2583 X86PGPAEUINT u;
2584 /** Normal view. */
2585 X86PML4EBITS n;
2586 /** 8 bit unsigned integer view. */
2587 uint8_t au8[8];
2588 /** 16 bit unsigned integer view. */
2589 uint16_t au16[4];
2590 /** 32 bit unsigned integer view. */
2591 uint32_t au32[2];
2592} X86PML4E;
2593#ifndef VBOX_FOR_DTRACE_LIB
2594AssertCompileSize(X86PML4E, 8);
2595#endif
2596/** Pointer to a page map level-4 entry. */
2597typedef X86PML4E *PX86PML4E;
2598/** Pointer to a const page map level-4 entry. */
2599typedef const X86PML4E *PCX86PML4E;
2600
2601
2602/**
2603 * Page Map Level-4.
2604 */
2605typedef struct X86PML4
2606{
2607 /** PDE Array. */
2608 X86PML4E a[X86_PG_PAE_ENTRIES];
2609} X86PML4;
2610#ifndef VBOX_FOR_DTRACE_LIB
2611AssertCompileSize(X86PML4, 4096);
2612#endif
2613/** Pointer to a page map level-4. */
2614typedef X86PML4 *PX86PML4;
2615/** Pointer to a const page map level-4. */
2616typedef const X86PML4 *PCX86PML4;
2617
2618/** The page shift to get the PML4 index. */
2619#define X86_PML4_SHIFT 39
2620/** The PML4 index mask (apply to a shifted page address). */
2621#define X86_PML4_MASK 0x1ff
2622
2623/** @} */
2624
2625/** @} */
2626
2627/**
2628 * Intel PCID invalidation types.
2629 */
2630/** Individual address invalidation. */
2631#define X86_INVPCID_TYPE_INDV_ADDR 0
2632/** Single-context invalidation. */
2633#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2634/** All-context including globals invalidation. */
2635#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2636/** All-context excluding globals invalidation. */
2637#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2638/** The maximum valid invalidation type value. */
2639#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2640
2641/**
2642 * 32-bit protected mode FSTENV image.
2643 */
2644typedef struct X86FSTENV32P
2645{
2646 uint16_t FCW;
2647 uint16_t padding1;
2648 uint16_t FSW;
2649 uint16_t padding2;
2650 uint16_t FTW;
2651 uint16_t padding3;
2652 uint32_t FPUIP;
2653 uint16_t FPUCS;
2654 uint16_t FOP;
2655 uint32_t FPUDP;
2656 uint16_t FPUDS;
2657 uint16_t padding4;
2658} X86FSTENV32P;
2659/** Pointer to a 32-bit protected mode FSTENV image. */
2660typedef X86FSTENV32P *PX86FSTENV32P;
2661/** Pointer to a const 32-bit protected mode FSTENV image. */
2662typedef X86FSTENV32P const *PCX86FSTENV32P;
2663
2664
2665/**
2666 * 80-bit MMX/FPU register type.
2667 */
2668typedef struct X86FPUMMX
2669{
2670 uint8_t reg[10];
2671} X86FPUMMX;
2672#ifndef VBOX_FOR_DTRACE_LIB
2673AssertCompileSize(X86FPUMMX, 10);
2674#endif
2675/** Pointer to a 80-bit MMX/FPU register type. */
2676typedef X86FPUMMX *PX86FPUMMX;
2677/** Pointer to a const 80-bit MMX/FPU register type. */
2678typedef const X86FPUMMX *PCX86FPUMMX;
2679
2680/** FPU (x87) register. */
2681typedef union X86FPUREG
2682{
2683 /** MMX view. */
2684 uint64_t mmx;
2685 /** FPU view - todo. */
2686 X86FPUMMX fpu;
2687 /** Extended precision floating point view. */
2688 RTFLOAT80U r80;
2689 /** Extended precision floating point view v2 */
2690 RTFLOAT80U2 r80Ex;
2691 /** 8-bit view. */
2692 uint8_t au8[16];
2693 /** 16-bit view. */
2694 uint16_t au16[8];
2695 /** 32-bit view. */
2696 uint32_t au32[4];
2697 /** 64-bit view. */
2698 uint64_t au64[2];
2699 /** 128-bit view. (yeah, very helpful) */
2700 uint128_t au128[1];
2701} X86FPUREG;
2702#ifndef VBOX_FOR_DTRACE_LIB
2703AssertCompileSize(X86FPUREG, 16);
2704#endif
2705/** Pointer to a FPU register. */
2706typedef X86FPUREG *PX86FPUREG;
2707/** Pointer to a const FPU register. */
2708typedef X86FPUREG const *PCX86FPUREG;
2709
2710/**
2711 * XMM register union.
2712 */
2713typedef union X86XMMREG
2714{
2715 /** XMM Register view. */
2716 uint128_t xmm;
2717 /** 8-bit view. */
2718 uint8_t au8[16];
2719 /** 16-bit view. */
2720 uint16_t au16[8];
2721 /** 32-bit view. */
2722 uint32_t au32[4];
2723 /** 64-bit view. */
2724 uint64_t au64[2];
2725 /** 128-bit view. (yeah, very helpful) */
2726 uint128_t au128[1];
2727 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2728 RTUINT128U uXmm;
2729} X86XMMREG;
2730#ifndef VBOX_FOR_DTRACE_LIB
2731AssertCompileSize(X86XMMREG, 16);
2732#endif
2733/** Pointer to an XMM register state. */
2734typedef X86XMMREG *PX86XMMREG;
2735/** Pointer to a const XMM register state. */
2736typedef X86XMMREG const *PCX86XMMREG;
2737
2738/**
2739 * YMM register union.
2740 */
2741typedef union X86YMMREG
2742{
2743 /** 8-bit view. */
2744 uint8_t au8[32];
2745 /** 16-bit view. */
2746 uint16_t au16[16];
2747 /** 32-bit view. */
2748 uint32_t au32[8];
2749 /** 64-bit view. */
2750 uint64_t au64[4];
2751 /** 128-bit view. (yeah, very helpful) */
2752 uint128_t au128[2];
2753 /** XMM sub register view. */
2754 X86XMMREG aXmm[2];
2755} X86YMMREG;
2756#ifndef VBOX_FOR_DTRACE_LIB
2757AssertCompileSize(X86YMMREG, 32);
2758#endif
2759/** Pointer to an YMM register state. */
2760typedef X86YMMREG *PX86YMMREG;
2761/** Pointer to a const YMM register state. */
2762typedef X86YMMREG const *PCX86YMMREG;
2763
2764/**
2765 * ZMM register union.
2766 */
2767typedef union X86ZMMREG
2768{
2769 /** 8-bit view. */
2770 uint8_t au8[64];
2771 /** 16-bit view. */
2772 uint16_t au16[32];
2773 /** 32-bit view. */
2774 uint32_t au32[16];
2775 /** 64-bit view. */
2776 uint64_t au64[8];
2777 /** 128-bit view. (yeah, very helpful) */
2778 uint128_t au128[4];
2779 /** XMM sub register view. */
2780 X86XMMREG aXmm[4];
2781 /** YMM sub register view. */
2782 X86YMMREG aYmm[2];
2783} X86ZMMREG;
2784#ifndef VBOX_FOR_DTRACE_LIB
2785AssertCompileSize(X86ZMMREG, 64);
2786#endif
2787/** Pointer to an ZMM register state. */
2788typedef X86ZMMREG *PX86ZMMREG;
2789/** Pointer to a const ZMM register state. */
2790typedef X86ZMMREG const *PCX86ZMMREG;
2791
2792
2793/**
2794 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2795 * @todo verify this...
2796 */
2797#pragma pack(1)
2798typedef struct X86FPUSTATE
2799{
2800 /** 0x00 - Control word. */
2801 uint16_t FCW;
2802 /** 0x02 - Alignment word */
2803 uint16_t Dummy1;
2804 /** 0x04 - Status word. */
2805 uint16_t FSW;
2806 /** 0x06 - Alignment word */
2807 uint16_t Dummy2;
2808 /** 0x08 - Tag word */
2809 uint16_t FTW;
2810 /** 0x0a - Alignment word */
2811 uint16_t Dummy3;
2812
2813 /** 0x0c - Instruction pointer. */
2814 uint32_t FPUIP;
2815 /** 0x10 - Code selector. */
2816 uint16_t CS;
2817 /** 0x12 - Opcode. */
2818 uint16_t FOP;
2819 /** 0x14 - FOO. */
2820 uint32_t FPUOO;
2821 /** 0x18 - FOS. */
2822 uint32_t FPUOS;
2823 /** 0x1c - FPU register. */
2824 X86FPUREG regs[8];
2825} X86FPUSTATE;
2826#pragma pack()
2827/** Pointer to a FPU state. */
2828typedef X86FPUSTATE *PX86FPUSTATE;
2829/** Pointer to a const FPU state. */
2830typedef const X86FPUSTATE *PCX86FPUSTATE;
2831
2832/**
2833 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2834 */
2835#pragma pack(1)
2836typedef struct X86FXSTATE
2837{
2838 /** 0x00 - Control word. */
2839 uint16_t FCW;
2840 /** 0x02 - Status word. */
2841 uint16_t FSW;
2842 /** 0x04 - Tag word. (The upper byte is always zero.) */
2843 uint16_t FTW;
2844 /** 0x06 - Opcode. */
2845 uint16_t FOP;
2846 /** 0x08 - Instruction pointer. */
2847 uint32_t FPUIP;
2848 /** 0x0c - Code selector. */
2849 uint16_t CS;
2850 uint16_t Rsrvd1;
2851 /** 0x10 - Data pointer. */
2852 uint32_t FPUDP;
2853 /** 0x14 - Data segment */
2854 uint16_t DS;
2855 /** 0x16 */
2856 uint16_t Rsrvd2;
2857 /** 0x18 */
2858 uint32_t MXCSR;
2859 /** 0x1c */
2860 uint32_t MXCSR_MASK;
2861 /** 0x20 - FPU registers. */
2862 X86FPUREG aRegs[8];
2863 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2864 X86XMMREG aXMM[16];
2865 /* - offset 416 - */
2866 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2867 /* - offset 464 - Software usable reserved bits. */
2868 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2869} X86FXSTATE;
2870#pragma pack()
2871/** Pointer to a FPU Extended state. */
2872typedef X86FXSTATE *PX86FXSTATE;
2873/** Pointer to a const FPU Extended state. */
2874typedef const X86FXSTATE *PCX86FXSTATE;
2875
2876/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2877 * magic. Don't forget to update x86.mac if you change this! */
2878#define X86_OFF_FXSTATE_RSVD 0x1d0
2879/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2880 * forget to update x86.mac if you change this!
2881 * @todo r=bird: This has nothing what-so-ever to do here.... */
2882#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2883#ifndef VBOX_FOR_DTRACE_LIB
2884AssertCompileSize(X86FXSTATE, 512);
2885AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2886#endif
2887
2888/** @name FPU status word flags.
2889 * @{ */
2890/** Exception Flag: Invalid operation. */
2891#define X86_FSW_IE RT_BIT_32(0)
2892/** Exception Flag: Denormalized operand. */
2893#define X86_FSW_DE RT_BIT_32(1)
2894/** Exception Flag: Zero divide. */
2895#define X86_FSW_ZE RT_BIT_32(2)
2896/** Exception Flag: Overflow. */
2897#define X86_FSW_OE RT_BIT_32(3)
2898/** Exception Flag: Underflow. */
2899#define X86_FSW_UE RT_BIT_32(4)
2900/** Exception Flag: Precision. */
2901#define X86_FSW_PE RT_BIT_32(5)
2902/** Stack fault. */
2903#define X86_FSW_SF RT_BIT_32(6)
2904/** Error summary status. */
2905#define X86_FSW_ES RT_BIT_32(7)
2906/** Mask of exceptions flags, excluding the summary bit. */
2907#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2908/** Mask of exceptions flags, including the summary bit. */
2909#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2910/** Condition code 0. */
2911#define X86_FSW_C0 RT_BIT_32(8)
2912/** Condition code 1. */
2913#define X86_FSW_C1 RT_BIT_32(9)
2914/** Condition code 2. */
2915#define X86_FSW_C2 RT_BIT_32(10)
2916/** Top of the stack mask. */
2917#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2918/** TOP shift value. */
2919#define X86_FSW_TOP_SHIFT 11
2920/** Mask for getting TOP value after shifting it right. */
2921#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2922/** Get the TOP value. */
2923#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2924/** Condition code 3. */
2925#define X86_FSW_C3 RT_BIT_32(14)
2926/** Mask of exceptions flags, including the summary bit. */
2927#define X86_FSW_C_MASK UINT16_C(0x4700)
2928/** FPU busy. */
2929#define X86_FSW_B RT_BIT_32(15)
2930/** @} */
2931
2932
2933/** @name FPU control word flags.
2934 * @{ */
2935/** Exception Mask: Invalid operation. */
2936#define X86_FCW_IM RT_BIT_32(0)
2937/** Exception Mask: Denormalized operand. */
2938#define X86_FCW_DM RT_BIT_32(1)
2939/** Exception Mask: Zero divide. */
2940#define X86_FCW_ZM RT_BIT_32(2)
2941/** Exception Mask: Overflow. */
2942#define X86_FCW_OM RT_BIT_32(3)
2943/** Exception Mask: Underflow. */
2944#define X86_FCW_UM RT_BIT_32(4)
2945/** Exception Mask: Precision. */
2946#define X86_FCW_PM RT_BIT_32(5)
2947/** Mask all exceptions, the value typically loaded (by for instance fninit).
2948 * @remarks This includes reserved bit 6. */
2949#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2950/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2951#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2952/** Precision control mask. */
2953#define X86_FCW_PC_MASK UINT16_C(0x0300)
2954/** Precision control: 24-bit. */
2955#define X86_FCW_PC_24 UINT16_C(0x0000)
2956/** Precision control: Reserved. */
2957#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2958/** Precision control: 53-bit. */
2959#define X86_FCW_PC_53 UINT16_C(0x0200)
2960/** Precision control: 64-bit. */
2961#define X86_FCW_PC_64 UINT16_C(0x0300)
2962/** Rounding control mask. */
2963#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2964/** Rounding control: To nearest. */
2965#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2966/** Rounding control: Down. */
2967#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2968/** Rounding control: Up. */
2969#define X86_FCW_RC_UP UINT16_C(0x0800)
2970/** Rounding control: Towards zero. */
2971#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2972/** Bits which should be zero, apparently. */
2973#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2974/** @} */
2975
2976/** @name SSE MXCSR
2977 * @{ */
2978/** Exception Flag: Invalid operation. */
2979#define X86_MXCSR_IE RT_BIT_32(0)
2980/** Exception Flag: Denormalized operand. */
2981#define X86_MXCSR_DE RT_BIT_32(1)
2982/** Exception Flag: Zero divide. */
2983#define X86_MXCSR_ZE RT_BIT_32(2)
2984/** Exception Flag: Overflow. */
2985#define X86_MXCSR_OE RT_BIT_32(3)
2986/** Exception Flag: Underflow. */
2987#define X86_MXCSR_UE RT_BIT_32(4)
2988/** Exception Flag: Precision. */
2989#define X86_MXCSR_PE RT_BIT_32(5)
2990
2991/** Denormals are zero. */
2992#define X86_MXCSR_DAZ RT_BIT_32(6)
2993
2994/** Exception Mask: Invalid operation. */
2995#define X86_MXCSR_IM RT_BIT_32(7)
2996/** Exception Mask: Denormalized operand. */
2997#define X86_MXCSR_DM RT_BIT_32(8)
2998/** Exception Mask: Zero divide. */
2999#define X86_MXCSR_ZM RT_BIT_32(9)
3000/** Exception Mask: Overflow. */
3001#define X86_MXCSR_OM RT_BIT_32(10)
3002/** Exception Mask: Underflow. */
3003#define X86_MXCSR_UM RT_BIT_32(11)
3004/** Exception Mask: Precision. */
3005#define X86_MXCSR_PM RT_BIT_32(12)
3006
3007/** Rounding control mask. */
3008#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3009/** Rounding control: To nearest. */
3010#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3011/** Rounding control: Down. */
3012#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3013/** Rounding control: Up. */
3014#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3015/** Rounding control: Towards zero. */
3016#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3017
3018/** Flush-to-zero for masked underflow. */
3019#define X86_MXCSR_FZ RT_BIT_32(15)
3020
3021/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3022#define X86_MXCSR_MM RT_BIT_32(17)
3023/** @} */
3024
3025/**
3026 * XSAVE header.
3027 */
3028typedef struct X86XSAVEHDR
3029{
3030 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3031 uint64_t bmXState;
3032 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3033 uint64_t bmXComp;
3034 /** Reserved for furture extensions, probably MBZ. */
3035 uint64_t au64Reserved[6];
3036} X86XSAVEHDR;
3037#ifndef VBOX_FOR_DTRACE_LIB
3038AssertCompileSize(X86XSAVEHDR, 64);
3039#endif
3040/** Pointer to an XSAVE header. */
3041typedef X86XSAVEHDR *PX86XSAVEHDR;
3042/** Pointer to a const XSAVE header. */
3043typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3044
3045
3046/**
3047 * The high 128-bit YMM register state (XSAVE_C_YMM).
3048 * (The lower 128-bits being in X86FXSTATE.)
3049 */
3050typedef struct X86XSAVEYMMHI
3051{
3052 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3053 X86XMMREG aYmmHi[16];
3054} X86XSAVEYMMHI;
3055#ifndef VBOX_FOR_DTRACE_LIB
3056AssertCompileSize(X86XSAVEYMMHI, 256);
3057#endif
3058/** Pointer to a high 128-bit YMM register state. */
3059typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3060/** Pointer to a const high 128-bit YMM register state. */
3061typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3062
3063/**
3064 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3065 */
3066typedef struct X86XSAVEBNDREGS
3067{
3068 /** Array of registers (BND0...BND3). */
3069 struct
3070 {
3071 /** Lower bound. */
3072 uint64_t uLowerBound;
3073 /** Upper bound. */
3074 uint64_t uUpperBound;
3075 } aRegs[4];
3076} X86XSAVEBNDREGS;
3077#ifndef VBOX_FOR_DTRACE_LIB
3078AssertCompileSize(X86XSAVEBNDREGS, 64);
3079#endif
3080/** Pointer to a MPX bound register state. */
3081typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3082/** Pointer to a const MPX bound register state. */
3083typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3084
3085/**
3086 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3087 */
3088typedef struct X86XSAVEBNDCFG
3089{
3090 uint64_t fConfig;
3091 uint64_t fStatus;
3092} X86XSAVEBNDCFG;
3093#ifndef VBOX_FOR_DTRACE_LIB
3094AssertCompileSize(X86XSAVEBNDCFG, 16);
3095#endif
3096/** Pointer to a MPX bound config and status register state. */
3097typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3098/** Pointer to a const MPX bound config and status register state. */
3099typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3100
3101/**
3102 * AVX-512 opmask state (XSAVE_C_OPMASK).
3103 */
3104typedef struct X86XSAVEOPMASK
3105{
3106 /** The K0..K7 values. */
3107 uint64_t aKRegs[8];
3108} X86XSAVEOPMASK;
3109#ifndef VBOX_FOR_DTRACE_LIB
3110AssertCompileSize(X86XSAVEOPMASK, 64);
3111#endif
3112/** Pointer to a AVX-512 opmask state. */
3113typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3114/** Pointer to a const AVX-512 opmask state. */
3115typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3116
3117/**
3118 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3119 */
3120typedef struct X86XSAVEZMMHI256
3121{
3122 /** Upper 256-bits of ZMM0-15. */
3123 X86YMMREG aHi256Regs[16];
3124} X86XSAVEZMMHI256;
3125#ifndef VBOX_FOR_DTRACE_LIB
3126AssertCompileSize(X86XSAVEZMMHI256, 512);
3127#endif
3128/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3129typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3130/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3131typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3132
3133/**
3134 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3135 */
3136typedef struct X86XSAVEZMM16HI
3137{
3138 /** ZMM16 thru ZMM31. */
3139 X86ZMMREG aRegs[16];
3140} X86XSAVEZMM16HI;
3141#ifndef VBOX_FOR_DTRACE_LIB
3142AssertCompileSize(X86XSAVEZMM16HI, 1024);
3143#endif
3144/** Pointer to a state comprising ZMM16-32. */
3145typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3146/** Pointer to a const state comprising ZMM16-32. */
3147typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3148
3149/**
3150 * AMD Light weight profiling state (XSAVE_C_LWP).
3151 *
3152 * We probably won't play with this as AMD seems to be dropping from their "zen"
3153 * processor micro architecture.
3154 */
3155typedef struct X86XSAVELWP
3156{
3157 /** Details when needed. */
3158 uint64_t auLater[128/8];
3159} X86XSAVELWP;
3160#ifndef VBOX_FOR_DTRACE_LIB
3161AssertCompileSize(X86XSAVELWP, 128);
3162#endif
3163
3164
3165/**
3166 * x86 FPU/SSE/AVX/XXXX state.
3167 *
3168 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3169 * changes to this structure.
3170 */
3171typedef struct X86XSAVEAREA
3172{
3173 /** The x87 and SSE region (or legacy region if you like). */
3174 X86FXSTATE x87;
3175 /** The XSAVE header. */
3176 X86XSAVEHDR Hdr;
3177 /** Beyond the header, there isn't really a fixed layout, but we can
3178 generally assume the YMM (AVX) register extensions are present and
3179 follows immediately. */
3180 union
3181 {
3182 /** The high 128-bit AVX registers for easy access by IEM.
3183 * @note This ASSUMES they will always be here... */
3184 X86XSAVEYMMHI YmmHi;
3185
3186 /** This is a typical layout on intel CPUs (good for debuggers). */
3187 struct
3188 {
3189 X86XSAVEYMMHI YmmHi;
3190 X86XSAVEBNDREGS BndRegs;
3191 X86XSAVEBNDCFG BndCfg;
3192 uint8_t abFudgeToMatchDocs[0xB0];
3193 X86XSAVEOPMASK Opmask;
3194 X86XSAVEZMMHI256 ZmmHi256;
3195 X86XSAVEZMM16HI Zmm16Hi;
3196 } Intel;
3197
3198 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3199 struct
3200 {
3201 X86XSAVEYMMHI YmmHi;
3202 X86XSAVELWP Lwp;
3203 } AmdBd;
3204
3205 /** To enbling static deployments that have a reasonable chance of working for
3206 * the next 3-6 CPU generations without running short on space, we allocate a
3207 * lot of extra space here, making the structure a round 8KB in size. This
3208 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3209 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3210 uint8_t ab[8192 - 512 - 64];
3211 } u;
3212} X86XSAVEAREA;
3213#ifndef VBOX_FOR_DTRACE_LIB
3214AssertCompileSize(X86XSAVEAREA, 8192);
3215AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3216AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3217AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3218AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3219AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3220AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3221AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3222AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3223#endif
3224/** Pointer to a XSAVE area. */
3225typedef X86XSAVEAREA *PX86XSAVEAREA;
3226/** Pointer to a const XSAVE area. */
3227typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3228
3229
3230/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3231 * @{ */
3232/** Bit 0 - x87 - Legacy FPU state (bit number) */
3233#define XSAVE_C_X87_BIT 0
3234/** Bit 0 - x87 - Legacy FPU state. */
3235#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3236/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3237#define XSAVE_C_SSE_BIT 1
3238/** Bit 1 - SSE - 128-bit SSE state. */
3239#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3240/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3241#define XSAVE_C_YMM_BIT 2
3242/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3243#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3244/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3245#define XSAVE_C_BNDREGS_BIT 3
3246/** Bit 3 - BNDREGS - MPX bound register state. */
3247#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3248/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3249#define XSAVE_C_BNDCSR_BIT 4
3250/** Bit 4 - BNDCSR - MPX bound config and status state. */
3251#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3252/** Bit 5 - Opmask - opmask state (bit number). */
3253#define XSAVE_C_OPMASK_BIT 5
3254/** Bit 5 - Opmask - opmask state. */
3255#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3256/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3257#define XSAVE_C_ZMM_HI256_BIT 6
3258/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3259#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3260/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3261#define XSAVE_C_ZMM_16HI_BIT 7
3262/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3263#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3264/** Bit 9 - PKRU - Protection-key state (bit number). */
3265#define XSAVE_C_PKRU_BIT 9
3266/** Bit 9 - PKRU - Protection-key state. */
3267#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3268/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3269#define XSAVE_C_LWP_BIT 62
3270/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3271#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3272/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3273#define XSAVE_C_X_BIT 63
3274/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3275#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3276/** @} */
3277
3278
3279
3280/** @name Selector Descriptor
3281 * @{
3282 */
3283
3284#ifndef VBOX_FOR_DTRACE_LIB
3285/**
3286 * Descriptor attributes (as seen by VT-x).
3287 */
3288typedef struct X86DESCATTRBITS
3289{
3290 /** 00 - Segment Type. */
3291 unsigned u4Type : 4;
3292 /** 04 - Descriptor Type. System(=0) or code/data selector */
3293 unsigned u1DescType : 1;
3294 /** 05 - Descriptor Privilege level. */
3295 unsigned u2Dpl : 2;
3296 /** 07 - Flags selector present(=1) or not. */
3297 unsigned u1Present : 1;
3298 /** 08 - Segment limit 16-19. */
3299 unsigned u4LimitHigh : 4;
3300 /** 0c - Available for system software. */
3301 unsigned u1Available : 1;
3302 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3303 unsigned u1Long : 1;
3304 /** 0e - This flags meaning depends on the segment type. Try make sense out
3305 * of the intel manual yourself. */
3306 unsigned u1DefBig : 1;
3307 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3308 * clear byte. */
3309 unsigned u1Granularity : 1;
3310 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3311 unsigned u1Unusable : 1;
3312} X86DESCATTRBITS;
3313#endif /* !VBOX_FOR_DTRACE_LIB */
3314
3315/** @name X86DESCATTR masks
3316 * @{ */
3317#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3318#define X86DESCATTR_DT UINT32_C(0x00000010)
3319#define X86DESCATTR_DPL UINT32_C(0x00000060)
3320#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3321#define X86DESCATTR_P UINT32_C(0x00000080)
3322#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3323#define X86DESCATTR_AVL UINT32_C(0x00001000)
3324#define X86DESCATTR_L UINT32_C(0x00002000)
3325#define X86DESCATTR_D UINT32_C(0x00004000)
3326#define X86DESCATTR_G UINT32_C(0x00008000)
3327#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3328/** @} */
3329
3330#pragma pack(1)
3331typedef union X86DESCATTR
3332{
3333 /** Unsigned integer view. */
3334 uint32_t u;
3335#ifndef VBOX_FOR_DTRACE_LIB
3336 /** Normal view. */
3337 X86DESCATTRBITS n;
3338#endif
3339} X86DESCATTR;
3340#pragma pack()
3341/** Pointer to descriptor attributes. */
3342typedef X86DESCATTR *PX86DESCATTR;
3343/** Pointer to const descriptor attributes. */
3344typedef const X86DESCATTR *PCX86DESCATTR;
3345
3346#ifndef VBOX_FOR_DTRACE_LIB
3347
3348/**
3349 * Generic descriptor table entry
3350 */
3351#pragma pack(1)
3352typedef struct X86DESCGENERIC
3353{
3354 /** 00 - Limit - Low word. */
3355 unsigned u16LimitLow : 16;
3356 /** 10 - Base address - low word.
3357 * Don't try set this to 24 because MSC is doing stupid things then. */
3358 unsigned u16BaseLow : 16;
3359 /** 20 - Base address - first 8 bits of high word. */
3360 unsigned u8BaseHigh1 : 8;
3361 /** 28 - Segment Type. */
3362 unsigned u4Type : 4;
3363 /** 2c - Descriptor Type. System(=0) or code/data selector */
3364 unsigned u1DescType : 1;
3365 /** 2d - Descriptor Privilege level. */
3366 unsigned u2Dpl : 2;
3367 /** 2f - Flags selector present(=1) or not. */
3368 unsigned u1Present : 1;
3369 /** 30 - Segment limit 16-19. */
3370 unsigned u4LimitHigh : 4;
3371 /** 34 - Available for system software. */
3372 unsigned u1Available : 1;
3373 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3374 unsigned u1Long : 1;
3375 /** 36 - This flags meaning depends on the segment type. Try make sense out
3376 * of the intel manual yourself. */
3377 unsigned u1DefBig : 1;
3378 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3379 * clear byte. */
3380 unsigned u1Granularity : 1;
3381 /** 38 - Base address - highest 8 bits. */
3382 unsigned u8BaseHigh2 : 8;
3383} X86DESCGENERIC;
3384#pragma pack()
3385/** Pointer to a generic descriptor entry. */
3386typedef X86DESCGENERIC *PX86DESCGENERIC;
3387/** Pointer to a const generic descriptor entry. */
3388typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3389
3390/** @name Bit offsets of X86DESCGENERIC members.
3391 * @{*/
3392#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3393#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3394#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3395#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3396#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3397#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3398#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3399#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3400#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3401#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3402#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3403#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3404#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3405/** @} */
3406
3407
3408/** @name LAR mask
3409 * @{ */
3410#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3411#define X86LAR_F_DT UINT16_C( 0x1000)
3412#define X86LAR_F_DPL UINT16_C( 0x6000)
3413#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3414#define X86LAR_F_P UINT16_C( 0x8000)
3415#define X86LAR_F_AVL UINT32_C(0x00100000)
3416#define X86LAR_F_L UINT32_C(0x00200000)
3417#define X86LAR_F_D UINT32_C(0x00400000)
3418#define X86LAR_F_G UINT32_C(0x00800000)
3419/** @} */
3420
3421
3422/**
3423 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3424 */
3425typedef struct X86DESCGATE
3426{
3427 /** 00 - Target code segment offset - Low word.
3428 * Ignored if task-gate. */
3429 unsigned u16OffsetLow : 16;
3430 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3431 * TSS selector if task-gate. */
3432 unsigned u16Sel : 16;
3433 /** 20 - Number of parameters for a call-gate.
3434 * Ignored if interrupt-, trap- or task-gate. */
3435 unsigned u5ParmCount : 5;
3436 /** 25 - Reserved / ignored. */
3437 unsigned u3Reserved : 3;
3438 /** 28 - Segment Type. */
3439 unsigned u4Type : 4;
3440 /** 2c - Descriptor Type (0 = system). */
3441 unsigned u1DescType : 1;
3442 /** 2d - Descriptor Privilege level. */
3443 unsigned u2Dpl : 2;
3444 /** 2f - Flags selector present(=1) or not. */
3445 unsigned u1Present : 1;
3446 /** 30 - Target code segment offset - High word.
3447 * Ignored if task-gate. */
3448 unsigned u16OffsetHigh : 16;
3449} X86DESCGATE;
3450/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3451typedef X86DESCGATE *PX86DESCGATE;
3452/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3453typedef const X86DESCGATE *PCX86DESCGATE;
3454
3455#endif /* VBOX_FOR_DTRACE_LIB */
3456
3457/**
3458 * Descriptor table entry.
3459 */
3460#pragma pack(1)
3461typedef union X86DESC
3462{
3463#ifndef VBOX_FOR_DTRACE_LIB
3464 /** Generic descriptor view. */
3465 X86DESCGENERIC Gen;
3466 /** Gate descriptor view. */
3467 X86DESCGATE Gate;
3468#endif
3469
3470 /** 8 bit unsigned integer view. */
3471 uint8_t au8[8];
3472 /** 16 bit unsigned integer view. */
3473 uint16_t au16[4];
3474 /** 32 bit unsigned integer view. */
3475 uint32_t au32[2];
3476 /** 64 bit unsigned integer view. */
3477 uint64_t au64[1];
3478 /** Unsigned integer view. */
3479 uint64_t u;
3480} X86DESC;
3481#ifndef VBOX_FOR_DTRACE_LIB
3482AssertCompileSize(X86DESC, 8);
3483#endif
3484#pragma pack()
3485/** Pointer to descriptor table entry. */
3486typedef X86DESC *PX86DESC;
3487/** Pointer to const descriptor table entry. */
3488typedef const X86DESC *PCX86DESC;
3489
3490/** @def X86DESC_BASE
3491 * Return the base address of a descriptor.
3492 */
3493#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3494 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3495 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3496 | ( (a_pDesc)->Gen.u16BaseLow ) )
3497
3498/** @def X86DESC_LIMIT
3499 * Return the limit of a descriptor.
3500 */
3501#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3502 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3503 | ( (a_pDesc)->Gen.u16LimitLow ) )
3504
3505/** @def X86DESC_LIMIT_G
3506 * Return the limit of a descriptor with the granularity bit taken into account.
3507 * @returns Selector limit (uint32_t).
3508 * @param a_pDesc Pointer to the descriptor.
3509 */
3510#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3511 ( (a_pDesc)->Gen.u1Granularity \
3512 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3513 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3514 )
3515
3516/** @def X86DESC_GET_HID_ATTR
3517 * Get the descriptor attributes for the hidden register.
3518 */
3519#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3520 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3521
3522#ifndef VBOX_FOR_DTRACE_LIB
3523
3524/**
3525 * 64 bits generic descriptor table entry
3526 * Note: most of these bits have no meaning in long mode.
3527 */
3528#pragma pack(1)
3529typedef struct X86DESC64GENERIC
3530{
3531 /** Limit - Low word - *IGNORED*. */
3532 uint32_t u16LimitLow : 16;
3533 /** Base address - low word. - *IGNORED*
3534 * Don't try set this to 24 because MSC is doing stupid things then. */
3535 uint32_t u16BaseLow : 16;
3536 /** Base address - first 8 bits of high word. - *IGNORED* */
3537 uint32_t u8BaseHigh1 : 8;
3538 /** Segment Type. */
3539 uint32_t u4Type : 4;
3540 /** Descriptor Type. System(=0) or code/data selector */
3541 uint32_t u1DescType : 1;
3542 /** Descriptor Privilege level. */
3543 uint32_t u2Dpl : 2;
3544 /** Flags selector present(=1) or not. */
3545 uint32_t u1Present : 1;
3546 /** Segment limit 16-19. - *IGNORED* */
3547 uint32_t u4LimitHigh : 4;
3548 /** Available for system software. - *IGNORED* */
3549 uint32_t u1Available : 1;
3550 /** Long mode flag. */
3551 uint32_t u1Long : 1;
3552 /** This flags meaning depends on the segment type. Try make sense out
3553 * of the intel manual yourself. */
3554 uint32_t u1DefBig : 1;
3555 /** Granularity of the limit. If set 4KB granularity is used, if
3556 * clear byte. - *IGNORED* */
3557 uint32_t u1Granularity : 1;
3558 /** Base address - highest 8 bits. - *IGNORED* */
3559 uint32_t u8BaseHigh2 : 8;
3560 /** Base address - bits 63-32. */
3561 uint32_t u32BaseHigh3 : 32;
3562 uint32_t u8Reserved : 8;
3563 uint32_t u5Zeros : 5;
3564 uint32_t u19Reserved : 19;
3565} X86DESC64GENERIC;
3566#pragma pack()
3567/** Pointer to a generic descriptor entry. */
3568typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3569/** Pointer to a const generic descriptor entry. */
3570typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3571
3572/**
3573 * System descriptor table entry (64 bits)
3574 *
3575 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3576 */
3577#pragma pack(1)
3578typedef struct X86DESC64SYSTEM
3579{
3580 /** Limit - Low word. */
3581 uint32_t u16LimitLow : 16;
3582 /** Base address - low word.
3583 * Don't try set this to 24 because MSC is doing stupid things then. */
3584 uint32_t u16BaseLow : 16;
3585 /** Base address - first 8 bits of high word. */
3586 uint32_t u8BaseHigh1 : 8;
3587 /** Segment Type. */
3588 uint32_t u4Type : 4;
3589 /** Descriptor Type. System(=0) or code/data selector */
3590 uint32_t u1DescType : 1;
3591 /** Descriptor Privilege level. */
3592 uint32_t u2Dpl : 2;
3593 /** Flags selector present(=1) or not. */
3594 uint32_t u1Present : 1;
3595 /** Segment limit 16-19. */
3596 uint32_t u4LimitHigh : 4;
3597 /** Available for system software. */
3598 uint32_t u1Available : 1;
3599 /** Reserved - 0. */
3600 uint32_t u1Reserved : 1;
3601 /** This flags meaning depends on the segment type. Try make sense out
3602 * of the intel manual yourself. */
3603 uint32_t u1DefBig : 1;
3604 /** Granularity of the limit. If set 4KB granularity is used, if
3605 * clear byte. */
3606 uint32_t u1Granularity : 1;
3607 /** Base address - bits 31-24. */
3608 uint32_t u8BaseHigh2 : 8;
3609 /** Base address - bits 63-32. */
3610 uint32_t u32BaseHigh3 : 32;
3611 uint32_t u8Reserved : 8;
3612 uint32_t u5Zeros : 5;
3613 uint32_t u19Reserved : 19;
3614} X86DESC64SYSTEM;
3615#pragma pack()
3616/** Pointer to a system descriptor entry. */
3617typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3618/** Pointer to a const system descriptor entry. */
3619typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3620
3621/**
3622 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3623 */
3624typedef struct X86DESC64GATE
3625{
3626 /** Target code segment offset - Low word. */
3627 uint32_t u16OffsetLow : 16;
3628 /** Target code segment selector. */
3629 uint32_t u16Sel : 16;
3630 /** Interrupt stack table for interrupt- and trap-gates.
3631 * Ignored by call-gates. */
3632 uint32_t u3IST : 3;
3633 /** Reserved / ignored. */
3634 uint32_t u5Reserved : 5;
3635 /** Segment Type. */
3636 uint32_t u4Type : 4;
3637 /** Descriptor Type (0 = system). */
3638 uint32_t u1DescType : 1;
3639 /** Descriptor Privilege level. */
3640 uint32_t u2Dpl : 2;
3641 /** Flags selector present(=1) or not. */
3642 uint32_t u1Present : 1;
3643 /** Target code segment offset - High word.
3644 * Ignored if task-gate. */
3645 uint32_t u16OffsetHigh : 16;
3646 /** Target code segment offset - Top dword.
3647 * Ignored if task-gate. */
3648 uint32_t u32OffsetTop : 32;
3649 /** Reserved / ignored / must be zero.
3650 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3651 uint32_t u32Reserved : 32;
3652} X86DESC64GATE;
3653AssertCompileSize(X86DESC64GATE, 16);
3654/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3655typedef X86DESC64GATE *PX86DESC64GATE;
3656/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3657typedef const X86DESC64GATE *PCX86DESC64GATE;
3658
3659#endif /* VBOX_FOR_DTRACE_LIB */
3660
3661/**
3662 * Descriptor table entry.
3663 */
3664#pragma pack(1)
3665typedef union X86DESC64
3666{
3667#ifndef VBOX_FOR_DTRACE_LIB
3668 /** Generic descriptor view. */
3669 X86DESC64GENERIC Gen;
3670 /** System descriptor view. */
3671 X86DESC64SYSTEM System;
3672 /** Gate descriptor view. */
3673 X86DESC64GATE Gate;
3674#endif
3675
3676 /** 8 bit unsigned integer view. */
3677 uint8_t au8[16];
3678 /** 16 bit unsigned integer view. */
3679 uint16_t au16[8];
3680 /** 32 bit unsigned integer view. */
3681 uint32_t au32[4];
3682 /** 64 bit unsigned integer view. */
3683 uint64_t au64[2];
3684} X86DESC64;
3685#ifndef VBOX_FOR_DTRACE_LIB
3686AssertCompileSize(X86DESC64, 16);
3687#endif
3688#pragma pack()
3689/** Pointer to descriptor table entry. */
3690typedef X86DESC64 *PX86DESC64;
3691/** Pointer to const descriptor table entry. */
3692typedef const X86DESC64 *PCX86DESC64;
3693
3694/** @def X86DESC64_BASE
3695 * Return the base of a 64-bit descriptor.
3696 */
3697#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3698 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3699 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3700 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3701 | ( (a_pDesc)->Gen.u16BaseLow ) )
3702
3703
3704
3705/** @name Host system descriptor table entry - Use with care!
3706 * @{ */
3707/** Host system descriptor table entry. */
3708#if HC_ARCH_BITS == 64
3709typedef X86DESC64 X86DESCHC;
3710#else
3711typedef X86DESC X86DESCHC;
3712#endif
3713/** Pointer to a host system descriptor table entry. */
3714#if HC_ARCH_BITS == 64
3715typedef PX86DESC64 PX86DESCHC;
3716#else
3717typedef PX86DESC PX86DESCHC;
3718#endif
3719/** Pointer to a const host system descriptor table entry. */
3720#if HC_ARCH_BITS == 64
3721typedef PCX86DESC64 PCX86DESCHC;
3722#else
3723typedef PCX86DESC PCX86DESCHC;
3724#endif
3725/** @} */
3726
3727
3728/** @name Selector Descriptor Types.
3729 * @{
3730 */
3731
3732/** @name Non-System Selector Types.
3733 * @{ */
3734/** Code(=set)/Data(=clear) bit. */
3735#define X86_SEL_TYPE_CODE 8
3736/** Memory(=set)/System(=clear) bit. */
3737#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3738/** Accessed bit. */
3739#define X86_SEL_TYPE_ACCESSED 1
3740/** Expand down bit (for data selectors only). */
3741#define X86_SEL_TYPE_DOWN 4
3742/** Conforming bit (for code selectors only). */
3743#define X86_SEL_TYPE_CONF 4
3744/** Write bit (for data selectors only). */
3745#define X86_SEL_TYPE_WRITE 2
3746/** Read bit (for code selectors only). */
3747#define X86_SEL_TYPE_READ 2
3748/** The bit number of the code segment read bit (relative to u4Type). */
3749#define X86_SEL_TYPE_READ_BIT 1
3750
3751/** Read only selector type. */
3752#define X86_SEL_TYPE_RO 0
3753/** Accessed read only selector type. */
3754#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3755/** Read write selector type. */
3756#define X86_SEL_TYPE_RW 2
3757/** Accessed read write selector type. */
3758#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3759/** Expand down read only selector type. */
3760#define X86_SEL_TYPE_RO_DOWN 4
3761/** Accessed expand down read only selector type. */
3762#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3763/** Expand down read write selector type. */
3764#define X86_SEL_TYPE_RW_DOWN 6
3765/** Accessed expand down read write selector type. */
3766#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3767/** Execute only selector type. */
3768#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3769/** Accessed execute only selector type. */
3770#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3771/** Execute and read selector type. */
3772#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3773/** Accessed execute and read selector type. */
3774#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3775/** Conforming execute only selector type. */
3776#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3777/** Accessed Conforming execute only selector type. */
3778#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3779/** Conforming execute and write selector type. */
3780#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3781/** Accessed Conforming execute and write selector type. */
3782#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3783/** @} */
3784
3785
3786/** @name System Selector Types.
3787 * @{ */
3788/** The TSS busy bit mask. */
3789#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3790
3791/** Undefined system selector type. */
3792#define X86_SEL_TYPE_SYS_UNDEFINED 0
3793/** 286 TSS selector. */
3794#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3795/** LDT selector. */
3796#define X86_SEL_TYPE_SYS_LDT 2
3797/** 286 TSS selector - Busy. */
3798#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3799/** 286 Callgate selector. */
3800#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3801/** Taskgate selector. */
3802#define X86_SEL_TYPE_SYS_TASK_GATE 5
3803/** 286 Interrupt gate selector. */
3804#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3805/** 286 Trapgate selector. */
3806#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3807/** Undefined system selector. */
3808#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3809/** 386 TSS selector. */
3810#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3811/** Undefined system selector. */
3812#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3813/** 386 TSS selector - Busy. */
3814#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3815/** 386 Callgate selector. */
3816#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3817/** Undefined system selector. */
3818#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3819/** 386 Interruptgate selector. */
3820#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3821/** 386 Trapgate selector. */
3822#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3823/** @} */
3824
3825/** @name AMD64 System Selector Types.
3826 * @{ */
3827/** LDT selector. */
3828#define AMD64_SEL_TYPE_SYS_LDT 2
3829/** TSS selector - Busy. */
3830#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3831/** TSS selector - Busy. */
3832#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3833/** Callgate selector. */
3834#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3835/** Interruptgate selector. */
3836#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3837/** Trapgate selector. */
3838#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3839/** @} */
3840
3841/** @} */
3842
3843
3844/** @name Descriptor Table Entry Flag Masks.
3845 * These are for the 2nd 32-bit word of a descriptor.
3846 * @{ */
3847/** Bits 8-11 - TYPE - Descriptor type mask. */
3848#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3849/** Bit 12 - S - System (=0) or Code/Data (=1). */
3850#define X86_DESC_S RT_BIT_32(12)
3851/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3852#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
3853/** Bit 15 - P - Present. */
3854#define X86_DESC_P RT_BIT_32(15)
3855/** Bit 20 - AVL - Available for system software. */
3856#define X86_DESC_AVL RT_BIT_32(20)
3857/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3858#define X86_DESC_DB RT_BIT_32(22)
3859/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3860 * used, if clear byte. */
3861#define X86_DESC_G RT_BIT_32(23)
3862/** @} */
3863
3864/** @} */
3865
3866
3867/** @name Task Segments.
3868 * @{
3869 */
3870
3871/**
3872 * The minimum TSS descriptor limit for 286 tasks.
3873 */
3874#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3875
3876/**
3877 * The minimum TSS descriptor segment limit for 386 tasks.
3878 */
3879#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3880
3881/**
3882 * 16-bit Task Segment (TSS).
3883 */
3884#pragma pack(1)
3885typedef struct X86TSS16
3886{
3887 /** Back link to previous task. (static) */
3888 RTSEL selPrev;
3889 /** Ring-0 stack pointer. (static) */
3890 uint16_t sp0;
3891 /** Ring-0 stack segment. (static) */
3892 RTSEL ss0;
3893 /** Ring-1 stack pointer. (static) */
3894 uint16_t sp1;
3895 /** Ring-1 stack segment. (static) */
3896 RTSEL ss1;
3897 /** Ring-2 stack pointer. (static) */
3898 uint16_t sp2;
3899 /** Ring-2 stack segment. (static) */
3900 RTSEL ss2;
3901 /** IP before task switch. */
3902 uint16_t ip;
3903 /** FLAGS before task switch. */
3904 uint16_t flags;
3905 /** AX before task switch. */
3906 uint16_t ax;
3907 /** CX before task switch. */
3908 uint16_t cx;
3909 /** DX before task switch. */
3910 uint16_t dx;
3911 /** BX before task switch. */
3912 uint16_t bx;
3913 /** SP before task switch. */
3914 uint16_t sp;
3915 /** BP before task switch. */
3916 uint16_t bp;
3917 /** SI before task switch. */
3918 uint16_t si;
3919 /** DI before task switch. */
3920 uint16_t di;
3921 /** ES before task switch. */
3922 RTSEL es;
3923 /** CS before task switch. */
3924 RTSEL cs;
3925 /** SS before task switch. */
3926 RTSEL ss;
3927 /** DS before task switch. */
3928 RTSEL ds;
3929 /** LDTR before task switch. */
3930 RTSEL selLdt;
3931} X86TSS16;
3932#ifndef VBOX_FOR_DTRACE_LIB
3933AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3934#endif
3935#pragma pack()
3936/** Pointer to a 16-bit task segment. */
3937typedef X86TSS16 *PX86TSS16;
3938/** Pointer to a const 16-bit task segment. */
3939typedef const X86TSS16 *PCX86TSS16;
3940
3941
3942/**
3943 * 32-bit Task Segment (TSS).
3944 */
3945#pragma pack(1)
3946typedef struct X86TSS32
3947{
3948 /** Back link to previous task. (static) */
3949 RTSEL selPrev;
3950 uint16_t padding1;
3951 /** Ring-0 stack pointer. (static) */
3952 uint32_t esp0;
3953 /** Ring-0 stack segment. (static) */
3954 RTSEL ss0;
3955 uint16_t padding_ss0;
3956 /** Ring-1 stack pointer. (static) */
3957 uint32_t esp1;
3958 /** Ring-1 stack segment. (static) */
3959 RTSEL ss1;
3960 uint16_t padding_ss1;
3961 /** Ring-2 stack pointer. (static) */
3962 uint32_t esp2;
3963 /** Ring-2 stack segment. (static) */
3964 RTSEL ss2;
3965 uint16_t padding_ss2;
3966 /** Page directory for the task. (static) */
3967 uint32_t cr3;
3968 /** EIP before task switch. */
3969 uint32_t eip;
3970 /** EFLAGS before task switch. */
3971 uint32_t eflags;
3972 /** EAX before task switch. */
3973 uint32_t eax;
3974 /** ECX before task switch. */
3975 uint32_t ecx;
3976 /** EDX before task switch. */
3977 uint32_t edx;
3978 /** EBX before task switch. */
3979 uint32_t ebx;
3980 /** ESP before task switch. */
3981 uint32_t esp;
3982 /** EBP before task switch. */
3983 uint32_t ebp;
3984 /** ESI before task switch. */
3985 uint32_t esi;
3986 /** EDI before task switch. */
3987 uint32_t edi;
3988 /** ES before task switch. */
3989 RTSEL es;
3990 uint16_t padding_es;
3991 /** CS before task switch. */
3992 RTSEL cs;
3993 uint16_t padding_cs;
3994 /** SS before task switch. */
3995 RTSEL ss;
3996 uint16_t padding_ss;
3997 /** DS before task switch. */
3998 RTSEL ds;
3999 uint16_t padding_ds;
4000 /** FS before task switch. */
4001 RTSEL fs;
4002 uint16_t padding_fs;
4003 /** GS before task switch. */
4004 RTSEL gs;
4005 uint16_t padding_gs;
4006 /** LDTR before task switch. */
4007 RTSEL selLdt;
4008 uint16_t padding_ldt;
4009 /** Debug trap flag */
4010 uint16_t fDebugTrap;
4011 /** Offset relative to the TSS of the start of the I/O Bitmap
4012 * and the end of the interrupt redirection bitmap. */
4013 uint16_t offIoBitmap;
4014} X86TSS32;
4015#pragma pack()
4016/** Pointer to task segment. */
4017typedef X86TSS32 *PX86TSS32;
4018/** Pointer to const task segment. */
4019typedef const X86TSS32 *PCX86TSS32;
4020#ifndef VBOX_FOR_DTRACE_LIB
4021AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4022AssertCompileMemberOffset(X86TSS32, cr3, 28);
4023AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4024#endif
4025
4026/**
4027 * 64-bit Task segment.
4028 */
4029#pragma pack(1)
4030typedef struct X86TSS64
4031{
4032 /** Reserved. */
4033 uint32_t u32Reserved;
4034 /** Ring-0 stack pointer. (static) */
4035 uint64_t rsp0;
4036 /** Ring-1 stack pointer. (static) */
4037 uint64_t rsp1;
4038 /** Ring-2 stack pointer. (static) */
4039 uint64_t rsp2;
4040 /** Reserved. */
4041 uint32_t u32Reserved2[2];
4042 /* IST */
4043 uint64_t ist1;
4044 uint64_t ist2;
4045 uint64_t ist3;
4046 uint64_t ist4;
4047 uint64_t ist5;
4048 uint64_t ist6;
4049 uint64_t ist7;
4050 /* Reserved. */
4051 uint16_t u16Reserved[5];
4052 /** Offset relative to the TSS of the start of the I/O Bitmap
4053 * and the end of the interrupt redirection bitmap. */
4054 uint16_t offIoBitmap;
4055} X86TSS64;
4056#pragma pack()
4057/** Pointer to a 64-bit task segment. */
4058typedef X86TSS64 *PX86TSS64;
4059/** Pointer to a const 64-bit task segment. */
4060typedef const X86TSS64 *PCX86TSS64;
4061#ifndef VBOX_FOR_DTRACE_LIB
4062AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4063#endif
4064
4065/** @} */
4066
4067
4068/** @name Selectors.
4069 * @{
4070 */
4071
4072/**
4073 * The shift used to convert a selector from and to index an index (C).
4074 */
4075#define X86_SEL_SHIFT 3
4076
4077/**
4078 * The mask used to mask off the table indicator and RPL of an selector.
4079 */
4080#define X86_SEL_MASK 0xfff8U
4081
4082/**
4083 * The mask used to mask off the RPL of an selector.
4084 * This is suitable for checking for NULL selectors.
4085 */
4086#define X86_SEL_MASK_OFF_RPL 0xfffcU
4087
4088/**
4089 * The bit indicating that a selector is in the LDT and not in the GDT.
4090 */
4091#define X86_SEL_LDT 0x0004U
4092
4093/**
4094 * The bit mask for getting the RPL of a selector.
4095 */
4096#define X86_SEL_RPL 0x0003U
4097
4098/**
4099 * The mask covering both RPL and LDT.
4100 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4101 * checks.
4102 */
4103#define X86_SEL_RPL_LDT 0x0007U
4104
4105/** @} */
4106
4107
4108/**
4109 * x86 Exceptions/Faults/Traps.
4110 */
4111typedef enum X86XCPT
4112{
4113 /** \#DE - Divide error. */
4114 X86_XCPT_DE = 0x00,
4115 /** \#DB - Debug event (single step, DRx, ..) */
4116 X86_XCPT_DB = 0x01,
4117 /** NMI - Non-Maskable Interrupt */
4118 X86_XCPT_NMI = 0x02,
4119 /** \#BP - Breakpoint (INT3). */
4120 X86_XCPT_BP = 0x03,
4121 /** \#OF - Overflow (INTO). */
4122 X86_XCPT_OF = 0x04,
4123 /** \#BR - Bound range exceeded (BOUND). */
4124 X86_XCPT_BR = 0x05,
4125 /** \#UD - Undefined opcode. */
4126 X86_XCPT_UD = 0x06,
4127 /** \#NM - Device not available (math coprocessor device). */
4128 X86_XCPT_NM = 0x07,
4129 /** \#DF - Double fault. */
4130 X86_XCPT_DF = 0x08,
4131 /** ??? - Coprocessor segment overrun (obsolete). */
4132 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4133 /** \#TS - Taskswitch (TSS). */
4134 X86_XCPT_TS = 0x0a,
4135 /** \#NP - Segment no present. */
4136 X86_XCPT_NP = 0x0b,
4137 /** \#SS - Stack segment fault. */
4138 X86_XCPT_SS = 0x0c,
4139 /** \#GP - General protection fault. */
4140 X86_XCPT_GP = 0x0d,
4141 /** \#PF - Page fault. */
4142 X86_XCPT_PF = 0x0e,
4143 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4144 /** \#MF - Math fault (FPU). */
4145 X86_XCPT_MF = 0x10,
4146 /** \#AC - Alignment check. */
4147 X86_XCPT_AC = 0x11,
4148 /** \#MC - Machine check. */
4149 X86_XCPT_MC = 0x12,
4150 /** \#XF - SIMD Floating-Pointer Exception. */
4151 X86_XCPT_XF = 0x13,
4152 /** \#VE - Virtualization Exception. */
4153 X86_XCPT_VE = 0x14,
4154 /** \#SX - Security Exception. */
4155 X86_XCPT_SX = 0x1e
4156} X86XCPT;
4157/** Pointer to a x86 exception code. */
4158typedef X86XCPT *PX86XCPT;
4159/** Pointer to a const x86 exception code. */
4160typedef const X86XCPT *PCX86XCPT;
4161/** The last valid (currently reserved) exception value. */
4162#define X86_XCPT_LAST 0x1f
4163
4164
4165/** @name Trap Error Codes
4166 * @{
4167 */
4168/** External indicator. */
4169#define X86_TRAP_ERR_EXTERNAL 1
4170/** IDT indicator. */
4171#define X86_TRAP_ERR_IDT 2
4172/** Descriptor table indicator - If set LDT, if clear GDT. */
4173#define X86_TRAP_ERR_TI 4
4174/** Mask for getting the selector. */
4175#define X86_TRAP_ERR_SEL_MASK 0xfff8
4176/** Shift for getting the selector table index (C type index). */
4177#define X86_TRAP_ERR_SEL_SHIFT 3
4178/** @} */
4179
4180
4181/** @name \#PF Trap Error Codes
4182 * @{
4183 */
4184/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4185#define X86_TRAP_PF_P RT_BIT_32(0)
4186/** Bit 1 - R/W - Read (clear) or write (set) access. */
4187#define X86_TRAP_PF_RW RT_BIT_32(1)
4188/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4189#define X86_TRAP_PF_US RT_BIT_32(2)
4190/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4191#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4192/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4193#define X86_TRAP_PF_ID RT_BIT_32(4)
4194/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4195#define X86_TRAP_PF_PK RT_BIT_32(5)
4196/** @} */
4197
4198#pragma pack(1)
4199/**
4200 * 16-bit IDTR.
4201 */
4202typedef struct X86IDTR16
4203{
4204 /** Offset. */
4205 uint16_t offSel;
4206 /** Selector. */
4207 uint16_t uSel;
4208} X86IDTR16, *PX86IDTR16;
4209#pragma pack()
4210
4211#pragma pack(1)
4212/**
4213 * 32-bit IDTR/GDTR.
4214 */
4215typedef struct X86XDTR32
4216{
4217 /** Size of the descriptor table. */
4218 uint16_t cb;
4219 /** Address of the descriptor table. */
4220#ifndef VBOX_FOR_DTRACE_LIB
4221 uint32_t uAddr;
4222#else
4223 uint16_t au16Addr[2];
4224#endif
4225} X86XDTR32, *PX86XDTR32;
4226#pragma pack()
4227
4228#pragma pack(1)
4229/**
4230 * 64-bit IDTR/GDTR.
4231 */
4232typedef struct X86XDTR64
4233{
4234 /** Size of the descriptor table. */
4235 uint16_t cb;
4236 /** Address of the descriptor table. */
4237#ifndef VBOX_FOR_DTRACE_LIB
4238 uint64_t uAddr;
4239#else
4240 uint16_t au16Addr[4];
4241#endif
4242} X86XDTR64, *PX86XDTR64;
4243#pragma pack()
4244
4245
4246/** @name ModR/M
4247 * @{ */
4248#define X86_MODRM_RM_MASK UINT8_C(0x07)
4249#define X86_MODRM_REG_MASK UINT8_C(0x38)
4250#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4251#define X86_MODRM_REG_SHIFT 3
4252#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4253#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4254#define X86_MODRM_MOD_SHIFT 6
4255#ifndef VBOX_FOR_DTRACE_LIB
4256AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4257AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4258AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4259/** @def X86_MODRM_MAKE
4260 * @param a_Mod The mod value (0..3).
4261 * @param a_Reg The register value (0..7).
4262 * @param a_RegMem The register or memory value (0..7). */
4263# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4264#endif
4265/** @} */
4266
4267/** @name SIB
4268 * @{ */
4269#define X86_SIB_BASE_MASK UINT8_C(0x07)
4270#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4271#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4272#define X86_SIB_INDEX_SHIFT 3
4273#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4274#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4275#define X86_SIB_SCALE_SHIFT 6
4276#ifndef VBOX_FOR_DTRACE_LIB
4277AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4278AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4279AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4280#endif
4281/** @} */
4282
4283/** @name General register indexes
4284 * @{ */
4285#define X86_GREG_xAX 0
4286#define X86_GREG_xCX 1
4287#define X86_GREG_xDX 2
4288#define X86_GREG_xBX 3
4289#define X86_GREG_xSP 4
4290#define X86_GREG_xBP 5
4291#define X86_GREG_xSI 6
4292#define X86_GREG_xDI 7
4293#define X86_GREG_x8 8
4294#define X86_GREG_x9 9
4295#define X86_GREG_x10 10
4296#define X86_GREG_x11 11
4297#define X86_GREG_x12 12
4298#define X86_GREG_x13 13
4299#define X86_GREG_x14 14
4300#define X86_GREG_x15 15
4301/** @} */
4302
4303/** @name X86_SREG_XXX - Segment register indexes.
4304 * @{ */
4305#define X86_SREG_ES 0
4306#define X86_SREG_CS 1
4307#define X86_SREG_SS 2
4308#define X86_SREG_DS 3
4309#define X86_SREG_FS 4
4310#define X86_SREG_GS 5
4311/** @} */
4312/** Segment register count. */
4313#define X86_SREG_COUNT 6
4314
4315
4316/** @name X86_OP_XXX - Prefixes
4317 * @{ */
4318#define X86_OP_PRF_CS UINT8_C(0x2e)
4319#define X86_OP_PRF_SS UINT8_C(0x36)
4320#define X86_OP_PRF_DS UINT8_C(0x3e)
4321#define X86_OP_PRF_ES UINT8_C(0x26)
4322#define X86_OP_PRF_FS UINT8_C(0x64)
4323#define X86_OP_PRF_GS UINT8_C(0x65)
4324#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4325#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4326#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4327#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4328#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4329#define X86_OP_REX_B UINT8_C(0x41)
4330#define X86_OP_REX_X UINT8_C(0x42)
4331#define X86_OP_REX_R UINT8_C(0x44)
4332#define X86_OP_REX_W UINT8_C(0x48)
4333/** @} */
4334
4335
4336/** @} */
4337
4338#endif
4339
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette