VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 73264

Last change on this file since 73264 was 73248, checked in by vboxsync, 7 years ago

x86.h: Nested VMX: bugref:9180 Added missing VMX MSR.
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2017 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT_32(0)
164#define X86_EFL_CF_BIT 0
165/** Bit 1 - Reserved, reads as 1. */
166#define X86_EFL_1 RT_BIT_32(1)
167/** Bit 2 - PF - Parity flag - Status flag. */
168#define X86_EFL_PF RT_BIT_32(2)
169/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170#define X86_EFL_AF RT_BIT_32(4)
171#define X86_EFL_AF_BIT 4
172/** Bit 6 - ZF - Zero flag - Status flag. */
173#define X86_EFL_ZF RT_BIT_32(6)
174#define X86_EFL_ZF_BIT 6
175/** Bit 7 - SF - Signed flag - Status flag. */
176#define X86_EFL_SF RT_BIT_32(7)
177#define X86_EFL_SF_BIT 7
178/** Bit 8 - TF - Trap flag - System flag. */
179#define X86_EFL_TF RT_BIT_32(8)
180/** Bit 9 - IF - Interrupt flag - System flag. */
181#define X86_EFL_IF RT_BIT_32(9)
182/** Bit 10 - DF - Direction flag - Control flag. */
183#define X86_EFL_DF RT_BIT_32(10)
184/** Bit 11 - OF - Overflow flag - Status flag. */
185#define X86_EFL_OF RT_BIT_32(11)
186#define X86_EFL_OF_BIT 11
187/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
189/** Bit 14 - NT - Nested task flag - System flag. */
190#define X86_EFL_NT RT_BIT_32(14)
191/** Bit 16 - RF - Resume flag - System flag. */
192#define X86_EFL_RF RT_BIT_32(16)
193/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194#define X86_EFL_VM RT_BIT_32(17)
195/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196#define X86_EFL_AC RT_BIT_32(18)
197/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198#define X86_EFL_VIF RT_BIT_32(19)
199/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200#define X86_EFL_VIP RT_BIT_32(20)
201/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202#define X86_EFL_ID RT_BIT_32(21)
203/** All live bits. */
204#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205/** Read as 1 bits. */
206#define X86_EFL_RA1_MASK RT_BIT_32(1)
207/** IOPL shift. */
208#define X86_EFL_IOPL_SHIFT 12
209/** The IOPL level from the flags. */
210#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211/** Bits restored by popf */
212#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
213 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
217/** The status bits commonly updated by arithmetic instructions. */
218#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
219/** @} */
220
221
222/** CPUID Feature information - ECX.
223 * CPUID query with EAX=1.
224 */
225#ifndef VBOX_FOR_DTRACE_LIB
226typedef struct X86CPUIDFEATECX
227{
228 /** Bit 0 - SSE3 - Supports SSE3 or not. */
229 unsigned u1SSE3 : 1;
230 /** Bit 1 - PCLMULQDQ. */
231 unsigned u1PCLMULQDQ : 1;
232 /** Bit 2 - DS Area 64-bit layout. */
233 unsigned u1DTE64 : 1;
234 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235 unsigned u1Monitor : 1;
236 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237 unsigned u1CPLDS : 1;
238 /** Bit 5 - VMX - Virtual Machine Technology. */
239 unsigned u1VMX : 1;
240 /** Bit 6 - SMX: Safer Mode Extensions. */
241 unsigned u1SMX : 1;
242 /** Bit 7 - EST - Enh. SpeedStep Tech. */
243 unsigned u1EST : 1;
244 /** Bit 8 - TM2 - Terminal Monitor 2. */
245 unsigned u1TM2 : 1;
246 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247 unsigned u1SSSE3 : 1;
248 /** Bit 10 - CNTX-ID - L1 Context ID. */
249 unsigned u1CNTXID : 1;
250 /** Bit 11 - Reserved. */
251 unsigned u1Reserved1 : 1;
252 /** Bit 12 - FMA. */
253 unsigned u1FMA : 1;
254 /** Bit 13 - CX16 - CMPXCHG16B. */
255 unsigned u1CX16 : 1;
256 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257 unsigned u1TPRUpdate : 1;
258 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259 unsigned u1PDCM : 1;
260 /** Bit 16 - Reserved. */
261 unsigned u1Reserved2 : 1;
262 /** Bit 17 - PCID - Process-context identifiers. */
263 unsigned u1PCID : 1;
264 /** Bit 18 - Direct Cache Access. */
265 unsigned u1DCA : 1;
266 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267 unsigned u1SSE4_1 : 1;
268 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269 unsigned u1SSE4_2 : 1;
270 /** Bit 21 - x2APIC. */
271 unsigned u1x2APIC : 1;
272 /** Bit 22 - MOVBE - Supports MOVBE. */
273 unsigned u1MOVBE : 1;
274 /** Bit 23 - POPCNT - Supports POPCNT. */
275 unsigned u1POPCNT : 1;
276 /** Bit 24 - TSC-Deadline. */
277 unsigned u1TSCDEADLINE : 1;
278 /** Bit 25 - AES. */
279 unsigned u1AES : 1;
280 /** Bit 26 - XSAVE - Supports XSAVE. */
281 unsigned u1XSAVE : 1;
282 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283 unsigned u1OSXSAVE : 1;
284 /** Bit 28 - AVX - Supports AVX instruction extensions. */
285 unsigned u1AVX : 1;
286 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287 unsigned u1F16C : 1;
288 /** Bit 30 - RDRAND - Supports RDRAND. */
289 unsigned u1RDRAND : 1;
290 /** Bit 31 - Hypervisor present (we're a guest). */
291 unsigned u1HVP : 1;
292} X86CPUIDFEATECX;
293#else /* VBOX_FOR_DTRACE_LIB */
294typedef uint32_t X86CPUIDFEATECX;
295#endif /* VBOX_FOR_DTRACE_LIB */
296/** Pointer to CPUID Feature Information - ECX. */
297typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298/** Pointer to const CPUID Feature Information - ECX. */
299typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302/** CPUID Feature Information - EDX.
303 * CPUID query with EAX=1.
304 */
305#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306typedef struct X86CPUIDFEATEDX
307{
308 /** Bit 0 - FPU - x87 FPU on Chip. */
309 unsigned u1FPU : 1;
310 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311 unsigned u1VME : 1;
312 /** Bit 2 - DE - Debugging extensions. */
313 unsigned u1DE : 1;
314 /** Bit 3 - PSE - Page Size Extension. */
315 unsigned u1PSE : 1;
316 /** Bit 4 - TSC - Time Stamp Counter. */
317 unsigned u1TSC : 1;
318 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319 unsigned u1MSR : 1;
320 /** Bit 6 - PAE - Physical Address Extension. */
321 unsigned u1PAE : 1;
322 /** Bit 7 - MCE - Machine Check Exception. */
323 unsigned u1MCE : 1;
324 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
325 unsigned u1CX8 : 1;
326 /** Bit 9 - APIC - APIC On-Chip. */
327 unsigned u1APIC : 1;
328 /** Bit 10 - Reserved. */
329 unsigned u1Reserved1 : 1;
330 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331 unsigned u1SEP : 1;
332 /** Bit 12 - MTRR - Memory Type Range Registers. */
333 unsigned u1MTRR : 1;
334 /** Bit 13 - PGE - PTE Global Bit. */
335 unsigned u1PGE : 1;
336 /** Bit 14 - MCA - Machine Check Architecture. */
337 unsigned u1MCA : 1;
338 /** Bit 15 - CMOV - Conditional Move Instructions. */
339 unsigned u1CMOV : 1;
340 /** Bit 16 - PAT - Page Attribute Table. */
341 unsigned u1PAT : 1;
342 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343 unsigned u1PSE36 : 1;
344 /** Bit 18 - PSN - Processor Serial Number. */
345 unsigned u1PSN : 1;
346 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
347 unsigned u1CLFSH : 1;
348 /** Bit 20 - Reserved. */
349 unsigned u1Reserved2 : 1;
350 /** Bit 21 - DS - Debug Store. */
351 unsigned u1DS : 1;
352 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353 unsigned u1ACPI : 1;
354 /** Bit 23 - MMX - Intel MMX 'Technology'. */
355 unsigned u1MMX : 1;
356 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357 unsigned u1FXSR : 1;
358 /** Bit 25 - SSE - SSE Support. */
359 unsigned u1SSE : 1;
360 /** Bit 26 - SSE2 - SSE2 Support. */
361 unsigned u1SSE2 : 1;
362 /** Bit 27 - SS - Self Snoop. */
363 unsigned u1SS : 1;
364 /** Bit 28 - HTT - Hyper-Threading Technology. */
365 unsigned u1HTT : 1;
366 /** Bit 29 - TM - Thermal Monitor. */
367 unsigned u1TM : 1;
368 /** Bit 30 - Reserved - . */
369 unsigned u1Reserved3 : 1;
370 /** Bit 31 - PBE - Pending Break Enabled. */
371 unsigned u1PBE : 1;
372} X86CPUIDFEATEDX;
373#else /* VBOX_FOR_DTRACE_LIB */
374typedef uint32_t X86CPUIDFEATEDX;
375#endif /* VBOX_FOR_DTRACE_LIB */
376/** Pointer to CPUID Feature Information - EDX. */
377typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378/** Pointer to const CPUID Feature Information - EDX. */
379typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381/** @name CPUID Vendor information.
382 * CPUID query with EAX=0.
383 * @{
384 */
385#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396/** @} */
397
398
399/** @name CPUID Feature information.
400 * CPUID query with EAX=1.
401 * @{
402 */
403/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428/** ECX Bit 12 - FMA. */
429#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436/** ECX Bit 17 - PCID - Process-context identifiers. */
437#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438/** ECX Bit 18 - DCA - Direct Cache Access. */
439#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444/** ECX Bit 21 - x2APIC support. */
445#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446/** ECX Bit 22 - MOVBE instruction. */
447#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448/** ECX Bit 23 - POPCNT instruction. */
449#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450/** ECX Bir 24 - TSC-Deadline. */
451#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452/** ECX Bit 25 - AES instructions. */
453#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454/** ECX Bit 26 - XSAVE instruction. */
455#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458/** ECX Bit 28 - AVX. */
459#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462/** ECX Bit 30 - RDRAND instruction. */
463#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464/** ECX Bit 31 - Hypervisor Present (software only). */
465#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468/** Bit 0 - FPU - x87 FPU on Chip. */
469#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472/** Bit 2 - DE - Debugging extensions. */
473#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474/** Bit 3 - PSE - Page Size Extension. */
475#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
477/** Bit 4 - TSC - Time Stamp Counter. */
478#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481/** Bit 6 - PAE - Physical Address Extension. */
482#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
484/** Bit 7 - MCE - Machine Check Exception. */
485#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488/** Bit 9 - APIC - APIC On-Chip. */
489#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492/** Bit 12 - MTRR - Memory Type Range Registers. */
493#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494/** Bit 13 - PGE - PTE Global Bit. */
495#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496/** Bit 14 - MCA - Machine Check Architecture. */
497#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498/** Bit 15 - CMOV - Conditional Move Instructions. */
499#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500/** Bit 16 - PAT - Page Attribute Table. */
501#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504/** Bit 18 - PSN - Processor Serial Number. */
505#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508/** Bit 21 - DS - Debug Store. */
509#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512/** Bit 23 - MMX - Intel MMX Technology. */
513#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516/** Bit 25 - SSE - SSE Support. */
517#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518/** Bit 26 - SSE2 - SSE2 Support. */
519#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520/** Bit 27 - SS - Self Snoop. */
521#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522/** Bit 28 - HTT - Hyper-Threading Technology. */
523#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524/** Bit 29 - TM - Therm. Monitor. */
525#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526/** Bit 31 - PBE - Pending Break Enabled. */
527#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528/** @} */
529
530/** @name CPUID mwait/monitor information.
531 * CPUID query with EAX=5.
532 * @{
533 */
534/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538/** @} */
539
540
541/** @name CPUID Structured Extended Feature information.
542 * CPUID query with EAX=7.
543 * @{
544 */
545/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
601#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
602/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
603#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
604/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
605#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
606/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
607#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
608/** ECX Bit 22 - RDPID - Support pread process ID. */
609#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
610/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
611#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
612
613/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
614 * IBPB command in IA32_PRED_CMD. */
615#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
616/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
617#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
618
619/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
620#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
621
622/** @} */
623
624
625/** @name CPUID Extended Feature information.
626 * CPUID query with EAX=0x80000001.
627 * @{
628 */
629/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
630#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
631
632/** EDX Bit 11 - SYSCALL/SYSRET. */
633#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
634/** EDX Bit 20 - No-Execute/Execute-Disable. */
635#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
636/** EDX Bit 26 - 1 GB large page. */
637#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
638/** EDX Bit 27 - RDTSCP. */
639#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
640/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
641#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
642/** @}*/
643
644/** @name CPUID AMD Feature information.
645 * CPUID query with EAX=0x80000001.
646 * @{
647 */
648/** Bit 0 - FPU - x87 FPU on Chip. */
649#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
650/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
651#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
652/** Bit 2 - DE - Debugging extensions. */
653#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
654/** Bit 3 - PSE - Page Size Extension. */
655#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
656/** Bit 4 - TSC - Time Stamp Counter. */
657#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
658/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
659#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
660/** Bit 6 - PAE - Physical Address Extension. */
661#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
662/** Bit 7 - MCE - Machine Check Exception. */
663#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
664/** Bit 8 - CX8 - CMPXCHG8B instruction. */
665#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
666/** Bit 9 - APIC - APIC On-Chip. */
667#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
668/** Bit 12 - MTRR - Memory Type Range Registers. */
669#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
670/** Bit 13 - PGE - PTE Global Bit. */
671#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
672/** Bit 14 - MCA - Machine Check Architecture. */
673#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
674/** Bit 15 - CMOV - Conditional Move Instructions. */
675#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
676/** Bit 16 - PAT - Page Attribute Table. */
677#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
678/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
679#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
680/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
681#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
682/** Bit 23 - MMX - Intel MMX Technology. */
683#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
684/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
685#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
686/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
687#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
688/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
689#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
690/** Bit 31 - 3DNOW - AMD 3DNow. */
691#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
692
693/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
694#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
695/** Bit 2 - SVM - AMD VM extensions. */
696#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
697/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
698#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
699/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
700#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
701/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
702#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
703/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
704#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
705/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
706#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
707/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
708#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
709/** Bit 9 - OSVW - AMD OS visible workaround. */
710#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
711/** Bit 10 - IBS - Instruct based sampling. */
712#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
713/** Bit 11 - XOP - Extended operation support (see APM6). */
714#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
715/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
716#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
717/** Bit 13 - WDT - AMD Watchdog timer support. */
718#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
719/** Bit 15 - LWP - Lightweight profiling support. */
720#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
721/** Bit 16 - FMA4 - Four operand FMA instruction support. */
722#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
723/** Bit 19 - NodeId - Indicates support for
724 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
725#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
726/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
727#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
728/** Bit 22 - TopologyExtensions - . */
729#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
730/** @} */
731
732
733/** @name CPUID AMD Feature information.
734 * CPUID query with EAX=0x80000007.
735 * @{
736 */
737/** Bit 0 - TS - Temperature Sensor. */
738#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
739/** Bit 1 - FID - Frequency ID Control. */
740#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
741/** Bit 2 - VID - Voltage ID Control. */
742#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
743/** Bit 3 - TTP - THERMTRIP. */
744#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
745/** Bit 4 - TM - Hardware Thermal Control. */
746#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
747/** Bit 5 - STC - Software Thermal Control. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
749/** Bit 6 - MC - 100 Mhz Multiplier Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
751/** Bit 7 - HWPSTATE - Hardware P-State Control. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
753/** Bit 8 - TSCINVAR - TSC Invariant. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
755/** Bit 9 - CPB - TSC Invariant. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
757/** Bit 10 - EffFreqRO - MPERF/APERF. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
759/** Bit 11 - PFI - Processor feedback interface (see EAX). */
760#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
761/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
762#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
763/** @} */
764
765
766/** @name CPUID AMD extended feature extensions ID (EBX).
767 * CPUID query with EAX=0x80000008.
768 * @{
769 */
770/** Bit 0 - CLZERO - Clear zero instruction. */
771#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
772/** Bit 1 - IRPerf - Instructions retired count support. */
773#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
774/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
775#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
776/* AMD pipeline length: 9 feature bits ;-) */
777/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
778#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
779/** @} */
780
781
782/** @name CPUID AMD SVM Feature information.
783 * CPUID query with EAX=0x8000000a.
784 * @{
785 */
786/** Bit 0 - NP - Nested Paging supported. */
787#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
788/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
789#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
790/** Bit 2 - SVML - SVM locking bit supported. */
791#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
792/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
793#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
794/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
795#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
796/** Bit 5 - VmcbClean - Support VMCB clean bits. */
797#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
798/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
799 * VMCB.TLB_Control is supported. */
800#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
801/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
802#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
803/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
804#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
805/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
806 * intercept filter cycle count threshold. */
807#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
808/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
809#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
810/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
811#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
812/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
813#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
814/** @} */
815
816
817/** @name CR0
818 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
819 * reserved flags.
820 * @{ */
821/** Bit 0 - PE - Protection Enabled */
822#define X86_CR0_PE RT_BIT_32(0)
823#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
824/** Bit 1 - MP - Monitor Coprocessor */
825#define X86_CR0_MP RT_BIT_32(1)
826#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
827/** Bit 2 - EM - Emulation. */
828#define X86_CR0_EM RT_BIT_32(2)
829#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
830/** Bit 3 - TS - Task Switch. */
831#define X86_CR0_TS RT_BIT_32(3)
832#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
833/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
834#define X86_CR0_ET RT_BIT_32(4)
835#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
836/** Bit 5 - NE - Numeric error (486+). */
837#define X86_CR0_NE RT_BIT_32(5)
838#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
839/** Bit 16 - WP - Write Protect (486+). */
840#define X86_CR0_WP RT_BIT_32(16)
841#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
842/** Bit 18 - AM - Alignment Mask (486+). */
843#define X86_CR0_AM RT_BIT_32(18)
844#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
845/** Bit 29 - NW - Not Write-though (486+). */
846#define X86_CR0_NW RT_BIT_32(29)
847#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
848/** Bit 30 - WP - Cache Disable (486+). */
849#define X86_CR0_CD RT_BIT_32(30)
850#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
851/** Bit 31 - PG - Paging. */
852#define X86_CR0_PG RT_BIT_32(31)
853#define X86_CR0_PAGING RT_BIT_32(31)
854/** @} */
855
856
857/** @name CR3
858 * @{ */
859/** Bit 3 - PWT - Page-level Writes Transparent. */
860#define X86_CR3_PWT RT_BIT_32(3)
861/** Bit 4 - PCD - Page-level Cache Disable. */
862#define X86_CR3_PCD RT_BIT_32(4)
863/** Bits 12-31 - - Page directory page number. */
864#define X86_CR3_PAGE_MASK (0xfffff000)
865/** Bits 5-31 - - PAE Page directory page number. */
866#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
867/** Bits 12-51 - - AMD64 Page directory page number. */
868#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
869/** @} */
870
871
872/** @name CR4
873 * @{ */
874/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
875#define X86_CR4_VME RT_BIT_32(0)
876/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
877#define X86_CR4_PVI RT_BIT_32(1)
878/** Bit 2 - TSD - Time Stamp Disable. */
879#define X86_CR4_TSD RT_BIT_32(2)
880/** Bit 3 - DE - Debugging Extensions. */
881#define X86_CR4_DE RT_BIT_32(3)
882/** Bit 4 - PSE - Page Size Extension. */
883#define X86_CR4_PSE RT_BIT_32(4)
884/** Bit 5 - PAE - Physical Address Extension. */
885#define X86_CR4_PAE RT_BIT_32(5)
886/** Bit 6 - MCE - Machine-Check Enable. */
887#define X86_CR4_MCE RT_BIT_32(6)
888/** Bit 7 - PGE - Page Global Enable. */
889#define X86_CR4_PGE RT_BIT_32(7)
890/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
891#define X86_CR4_PCE RT_BIT_32(8)
892/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
893#define X86_CR4_OSFXSR RT_BIT_32(9)
894/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
895#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
896/** Bit 13 - VMXE - VMX mode is enabled. */
897#define X86_CR4_VMXE RT_BIT_32(13)
898/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
899#define X86_CR4_SMXE RT_BIT_32(14)
900/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
901#define X86_CR4_FSGSBASE RT_BIT_32(16)
902/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
903#define X86_CR4_PCIDE RT_BIT_32(17)
904/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
905 * extended states. */
906#define X86_CR4_OSXSAVE RT_BIT_32(18)
907/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
908#define X86_CR4_SMEP RT_BIT_32(20)
909/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
910#define X86_CR4_SMAP RT_BIT_32(21)
911/** Bit 22 - PKE - Protection Key Enable. */
912#define X86_CR4_PKE RT_BIT_32(22)
913/** @} */
914
915
916/** @name DR6
917 * @{ */
918/** Bit 0 - B0 - Breakpoint 0 condition detected. */
919#define X86_DR6_B0 RT_BIT_32(0)
920/** Bit 1 - B1 - Breakpoint 1 condition detected. */
921#define X86_DR6_B1 RT_BIT_32(1)
922/** Bit 2 - B2 - Breakpoint 2 condition detected. */
923#define X86_DR6_B2 RT_BIT_32(2)
924/** Bit 3 - B3 - Breakpoint 3 condition detected. */
925#define X86_DR6_B3 RT_BIT_32(3)
926/** Mask of all the Bx bits. */
927#define X86_DR6_B_MASK UINT64_C(0x0000000f)
928/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
929#define X86_DR6_BD RT_BIT_32(13)
930/** Bit 14 - BS - Single step */
931#define X86_DR6_BS RT_BIT_32(14)
932/** Bit 15 - BT - Task switch. (TSS T bit.) */
933#define X86_DR6_BT RT_BIT_32(15)
934/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
935#define X86_DR6_RTM RT_BIT_32(16)
936/** Value of DR6 after powerup/reset. */
937#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
938/** Bits which must be 1s in DR6. */
939#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
940/** Bits which must be 1s in DR6, when RTM is supported. */
941#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
942/** Bits which must be 0s in DR6. */
943#define X86_DR6_RAZ_MASK RT_BIT_64(12)
944/** Bits which must be 0s on writes to DR6. */
945#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
946/** @} */
947
948/** Get the DR6.Bx bit for a the given breakpoint. */
949#define X86_DR6_B(iBp) RT_BIT_64(iBp)
950
951
952/** @name DR7
953 * @{ */
954/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
955#define X86_DR7_L0 RT_BIT_32(0)
956/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
957#define X86_DR7_G0 RT_BIT_32(1)
958/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
959#define X86_DR7_L1 RT_BIT_32(2)
960/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
961#define X86_DR7_G1 RT_BIT_32(3)
962/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
963#define X86_DR7_L2 RT_BIT_32(4)
964/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
965#define X86_DR7_G2 RT_BIT_32(5)
966/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
967#define X86_DR7_L3 RT_BIT_32(6)
968/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
969#define X86_DR7_G3 RT_BIT_32(7)
970/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
971#define X86_DR7_LE RT_BIT_32(8)
972/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
973#define X86_DR7_GE RT_BIT_32(9)
974
975/** L0, L1, L2, and L3. */
976#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
977/** L0, L1, L2, and L3. */
978#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
979
980/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
981 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
982#define X86_DR7_RTM RT_BIT_32(11)
983/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
984 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
985 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
986 * instruction is executed.
987 * @see http://www.rcollins.org/secrets/DR7.html */
988#define X86_DR7_ICE_IR RT_BIT_32(12)
989/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
990 * any DR register is accessed. */
991#define X86_DR7_GD RT_BIT_32(13)
992/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
993 * Pentium. */
994#define X86_DR7_ICE_TR1 RT_BIT_32(14)
995/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
996#define X86_DR7_ICE_TR2 RT_BIT_32(15)
997/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
998#define X86_DR7_RW0_MASK (3 << 16)
999/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1000#define X86_DR7_LEN0_MASK (3 << 18)
1001/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1002#define X86_DR7_RW1_MASK (3 << 20)
1003/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1004#define X86_DR7_LEN1_MASK (3 << 22)
1005/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1006#define X86_DR7_RW2_MASK (3 << 24)
1007/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1008#define X86_DR7_LEN2_MASK (3 << 26)
1009/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1010#define X86_DR7_RW3_MASK (3 << 28)
1011/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1012#define X86_DR7_LEN3_MASK (3 << 30)
1013
1014/** Bits which reads as 1s. */
1015#define X86_DR7_RA1_MASK RT_BIT_32(10)
1016/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1017#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1018/** Bits which must be 0s when writing to DR7. */
1019#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1020
1021/** Calcs the L bit of Nth breakpoint.
1022 * @param iBp The breakpoint number [0..3].
1023 */
1024#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1025
1026/** Calcs the G bit of Nth breakpoint.
1027 * @param iBp The breakpoint number [0..3].
1028 */
1029#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1030
1031/** Calcs the L and G bits of Nth breakpoint.
1032 * @param iBp The breakpoint number [0..3].
1033 */
1034#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1035
1036/** @name Read/Write values.
1037 * @{ */
1038/** Break on instruction fetch only. */
1039#define X86_DR7_RW_EO UINT32_C(0)
1040/** Break on write only. */
1041#define X86_DR7_RW_WO UINT32_C(1)
1042/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1043#define X86_DR7_RW_IO UINT32_C(2)
1044/** Break on read or write (but not instruction fetches). */
1045#define X86_DR7_RW_RW UINT32_C(3)
1046/** @} */
1047
1048/** Shifts a X86_DR7_RW_* value to its right place.
1049 * @param iBp The breakpoint number [0..3].
1050 * @param fRw One of the X86_DR7_RW_* value.
1051 */
1052#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1053
1054/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1055 * one of the X86_DR7_RW_XXX constants).
1056 *
1057 * @returns X86_DR7_RW_XXX
1058 * @param uDR7 DR7 value
1059 * @param iBp The breakpoint number [0..3].
1060 */
1061#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1062
1063/** R/W0, R/W1, R/W2, and R/W3. */
1064#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1065
1066#ifndef VBOX_FOR_DTRACE_LIB
1067/** Checks if there are any I/O breakpoint types configured in the RW
1068 * registers. Does NOT check if these are enabled, sorry. */
1069# define X86_DR7_ANY_RW_IO(uDR7) \
1070 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1071 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1072AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1073AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1074AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1075AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1076AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1077AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1078AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1079AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1080AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1081#endif /* !VBOX_FOR_DTRACE_LIB */
1082
1083/** @name Length values.
1084 * @{ */
1085#define X86_DR7_LEN_BYTE UINT32_C(0)
1086#define X86_DR7_LEN_WORD UINT32_C(1)
1087#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1088#define X86_DR7_LEN_DWORD UINT32_C(3)
1089/** @} */
1090
1091/** Shifts a X86_DR7_LEN_* value to its right place.
1092 * @param iBp The breakpoint number [0..3].
1093 * @param cb One of the X86_DR7_LEN_* values.
1094 */
1095#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1096
1097/** Fetch the breakpoint length bits from the DR7 value.
1098 * @param uDR7 DR7 value
1099 * @param iBp The breakpoint number [0..3].
1100 */
1101#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1102
1103/** Mask used to check if any breakpoints are enabled. */
1104#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1105
1106/** LEN0, LEN1, LEN2, and LEN3. */
1107#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1108/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1109#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1110
1111/** Value of DR7 after powerup/reset. */
1112#define X86_DR7_INIT_VAL 0x400
1113/** @} */
1114
1115
1116/** @name Machine Specific Registers
1117 * @{
1118 */
1119/** Machine check address register (P5). */
1120#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1121/** Machine check type register (P5). */
1122#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1123/** Time Stamp Counter. */
1124#define MSR_IA32_TSC 0x10
1125#define MSR_IA32_CESR UINT32_C(0x00000011)
1126#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1127#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1128
1129#define MSR_IA32_PLATFORM_ID 0x17
1130
1131#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1132# define MSR_IA32_APICBASE 0x1b
1133/** Local APIC enabled. */
1134# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1135/** X2APIC enabled (requires the EN bit to be set). */
1136# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1137/** The processor is the boot strap processor (BSP). */
1138# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1139/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1140 * width. */
1141# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1142/** The default physical base address of the APIC. */
1143# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1144/** Gets the physical base address from the MSR. */
1145# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1146#endif
1147
1148/** Undocumented intel MSR for reporting thread and core counts.
1149 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1150 * first 16 bits is the thread count. The next 16 bits the core count, except
1151 * on Westmere where it seems it's only the next 4 bits for some reason. */
1152#define MSR_CORE_THREAD_COUNT 0x35
1153
1154/** CPU Feature control. */
1155#define MSR_IA32_FEATURE_CONTROL 0x3A
1156/** Feature control - Lock MSR from writes (R/W0). */
1157#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1158/** Feature control - Enable VMX inside SMX operation (R/WL). */
1159#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1160/** Feature control - Enable VMX outside SMX operationr (R/WL). */
1161#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1162/** Feature control - SENTER local functions enable (R/WL). */
1163#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1164#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1165#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1166#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1167#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1168#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1169#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1170/** Feature control - SENTER global enable (R/WL). */
1171#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1172/** Feature control - SGX launch control enable (R/WL). */
1173#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1174/** Feature control - SGX global enable (R/WL). */
1175#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1176/** Feature control - LMCE on (R/WL). */
1177#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1178
1179/** Per-processor TSC adjust MSR. */
1180#define MSR_IA32_TSC_ADJUST 0x3B
1181
1182/** Spectre control register.
1183 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1184#define MSR_IA32_SPEC_CTRL 0x48
1185/** IBRS - Indirect branch restricted speculation. */
1186#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1187/** STIBP - Single thread indirect branch predictors. */
1188#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1189
1190/** Prediction command register.
1191 * Write only, logical processor scope, no state since write only. */
1192#define MSR_IA32_PRED_CMD 0x49
1193/** IBPB - Indirect branch prediction barrie when written as 1. */
1194#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1195
1196/** BIOS update trigger (microcode update). */
1197#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1198
1199/** BIOS update signature (microcode). */
1200#define MSR_IA32_BIOS_SIGN_ID 0x8B
1201
1202/** SMM monitor control. */
1203#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1204
1205/** General performance counter no. 0. */
1206#define MSR_IA32_PMC0 0xC1
1207/** General performance counter no. 1. */
1208#define MSR_IA32_PMC1 0xC2
1209/** General performance counter no. 2. */
1210#define MSR_IA32_PMC2 0xC3
1211/** General performance counter no. 3. */
1212#define MSR_IA32_PMC3 0xC4
1213
1214/** Nehalem power control. */
1215#define MSR_IA32_PLATFORM_INFO 0xCE
1216
1217/** Get FSB clock status (Intel-specific). */
1218#define MSR_IA32_FSB_CLOCK_STS 0xCD
1219
1220/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1221#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1222
1223/** C0 Maximum Frequency Clock Count */
1224#define MSR_IA32_MPERF 0xE7
1225/** C0 Actual Frequency Clock Count */
1226#define MSR_IA32_APERF 0xE8
1227
1228/** MTRR Capabilities. */
1229#define MSR_IA32_MTRR_CAP 0xFE
1230
1231/** Architecture capabilities (bugfixes).
1232 * @note May move */
1233#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1234/** CPU is no subject to spectre problems. */
1235#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0)
1236/** CPU has better IBRS and you can leave it on all the time. */
1237#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1)
1238
1239/** Cache control/info. */
1240#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1241
1242#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1243/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1244 * R0 SS == CS + 8
1245 * R3 CS == CS + 16
1246 * R3 SS == CS + 24
1247 */
1248#define MSR_IA32_SYSENTER_CS 0x174
1249/** SYSENTER_ESP - the R0 ESP. */
1250#define MSR_IA32_SYSENTER_ESP 0x175
1251/** SYSENTER_EIP - the R0 EIP. */
1252#define MSR_IA32_SYSENTER_EIP 0x176
1253#endif
1254
1255/** Machine Check Global Capabilities Register. */
1256#define MSR_IA32_MCG_CAP 0x179
1257/** Machine Check Global Status Register. */
1258#define MSR_IA32_MCG_STATUS 0x17A
1259/** Machine Check Global Control Register. */
1260#define MSR_IA32_MCG_CTRL 0x17B
1261
1262/** Page Attribute Table. */
1263#define MSR_IA32_CR_PAT 0x277
1264/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1265 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1266#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1267
1268/** Performance counter MSRs. (Intel only) */
1269#define MSR_IA32_PERFEVTSEL0 0x186
1270#define MSR_IA32_PERFEVTSEL1 0x187
1271/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1272 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1273 * holds a ratio that Apple takes for TSC granularity.
1274 *
1275 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1276#define MSR_FLEX_RATIO 0x194
1277/** Performance state value and starting with Intel core more.
1278 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1279#define MSR_IA32_PERF_STATUS 0x198
1280#define MSR_IA32_PERF_CTL 0x199
1281#define MSR_IA32_THERM_STATUS 0x19c
1282
1283/** Enable misc. processor features (R/W). */
1284#define MSR_IA32_MISC_ENABLE 0x1A0
1285/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1286#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1287/** Automatic Thermal Control Circuit Enable (R/W). */
1288#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1289/** Performance Monitoring Available (R). */
1290#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1291/** Branch Trace Storage Unavailable (R/O). */
1292#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1293/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1294#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1295/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1296#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1297/** If MONITOR/MWAIT is supported (R/W). */
1298#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1299/** Limit CPUID Maxval to 3 leafs (R/W). */
1300#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1301/** When set to 1, xTPR messages are disabled (R/W). */
1302#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1303/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1304#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1305
1306/** Trace/Profile Resource Control (R/W) */
1307#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1308/** Last branch record. */
1309#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1310/** Branch trace flag (single step on branches). */
1311#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1312/** Performance monitoring pin control (AMD only). */
1313#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1314#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1315#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1316#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1317/** Trace message enable (Intel only). */
1318#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1319/** Branch trace store (Intel only). */
1320#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1321/** Branch trace interrupt (Intel only). */
1322#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1323/** Branch trace off in privileged code (Intel only). */
1324#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1325/** Branch trace off in user code (Intel only). */
1326#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1327/** Freeze LBR on PMI flag (Intel only). */
1328#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1329/** Freeze PERFMON on PMI flag (Intel only). */
1330#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1331/** Freeze while SMM enabled (Intel only). */
1332#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1333/** Advanced debugging of RTM regions (Intel only). */
1334#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1335
1336/** The number (0..3 or 0..15) of the last branch record register on P4 and
1337 * related Xeons. */
1338#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1339/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1340 * @{ */
1341#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1342#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1343#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1344#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1345/** @} */
1346
1347
1348#define IA32_MTRR_PHYSBASE0 0x200
1349#define IA32_MTRR_PHYSMASK0 0x201
1350#define IA32_MTRR_PHYSBASE1 0x202
1351#define IA32_MTRR_PHYSMASK1 0x203
1352#define IA32_MTRR_PHYSBASE2 0x204
1353#define IA32_MTRR_PHYSMASK2 0x205
1354#define IA32_MTRR_PHYSBASE3 0x206
1355#define IA32_MTRR_PHYSMASK3 0x207
1356#define IA32_MTRR_PHYSBASE4 0x208
1357#define IA32_MTRR_PHYSMASK4 0x209
1358#define IA32_MTRR_PHYSBASE5 0x20a
1359#define IA32_MTRR_PHYSMASK5 0x20b
1360#define IA32_MTRR_PHYSBASE6 0x20c
1361#define IA32_MTRR_PHYSMASK6 0x20d
1362#define IA32_MTRR_PHYSBASE7 0x20e
1363#define IA32_MTRR_PHYSMASK7 0x20f
1364#define IA32_MTRR_PHYSBASE8 0x210
1365#define IA32_MTRR_PHYSMASK8 0x211
1366#define IA32_MTRR_PHYSBASE9 0x212
1367#define IA32_MTRR_PHYSMASK9 0x213
1368
1369/** Fixed range MTRRs.
1370 * @{ */
1371#define IA32_MTRR_FIX64K_00000 0x250
1372#define IA32_MTRR_FIX16K_80000 0x258
1373#define IA32_MTRR_FIX16K_A0000 0x259
1374#define IA32_MTRR_FIX4K_C0000 0x268
1375#define IA32_MTRR_FIX4K_C8000 0x269
1376#define IA32_MTRR_FIX4K_D0000 0x26a
1377#define IA32_MTRR_FIX4K_D8000 0x26b
1378#define IA32_MTRR_FIX4K_E0000 0x26c
1379#define IA32_MTRR_FIX4K_E8000 0x26d
1380#define IA32_MTRR_FIX4K_F0000 0x26e
1381#define IA32_MTRR_FIX4K_F8000 0x26f
1382/** @} */
1383
1384/** MTRR Default Range. */
1385#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1386
1387/** Global performance counter control facilities (Intel only). */
1388#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1389#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1390#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1391
1392/** Precise Event Based sampling (Intel only). */
1393#define MSR_IA32_PEBS_ENABLE 0x3F1
1394
1395#define MSR_IA32_MC0_CTL 0x400
1396#define MSR_IA32_MC0_STATUS 0x401
1397
1398/** Basic VMX information. */
1399#define MSR_IA32_VMX_BASIC_INFO 0x480
1400/** Allowed settings for pin-based VM execution controls */
1401#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1402/** Allowed settings for proc-based VM execution controls */
1403#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1404/** Allowed settings for the VMX exit controls. */
1405#define MSR_IA32_VMX_EXIT_CTLS 0x483
1406/** Allowed settings for the VMX entry controls. */
1407#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1408/** Misc VMX info. */
1409#define MSR_IA32_VMX_MISC 0x485
1410/** Fixed cleared bits in CR0. */
1411#define MSR_IA32_VMX_CR0_FIXED0 0x486
1412/** Fixed set bits in CR0. */
1413#define MSR_IA32_VMX_CR0_FIXED1 0x487
1414/** Fixed cleared bits in CR4. */
1415#define MSR_IA32_VMX_CR4_FIXED0 0x488
1416/** Fixed set bits in CR4. */
1417#define MSR_IA32_VMX_CR4_FIXED1 0x489
1418/** Information for enumerating fields in the VMCS. */
1419#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1420/** Allowed settings for the VM-functions controls. */
1421#define MSR_IA32_VMX_VMFUNC 0x491
1422/** Allowed settings for secondary proc-based VM execution controls */
1423#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1424/** EPT capabilities. */
1425#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1426/** Allowed settings of all pin-based VM execution controls. */
1427#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1428/** Allowed settings of all proc-based VM execution controls. */
1429#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1430/** Allowed settings of all VMX exit controls. */
1431#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1432/** Allowed settings of all VMX entry controls. */
1433#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1434/** Allowed settings for the VM-function controls. */
1435#define MSR_IA32_VMX_VMFUNC 0x491
1436
1437/** DS Save Area (R/W). */
1438#define MSR_IA32_DS_AREA 0x600
1439/** Running Average Power Limit (RAPL) power units. */
1440#define MSR_RAPL_POWER_UNIT 0x606
1441
1442/** X2APIC MSR range start. */
1443#define MSR_IA32_X2APIC_START 0x800
1444/** X2APIC MSR - APIC ID Register. */
1445#define MSR_IA32_X2APIC_ID 0x802
1446/** X2APIC MSR - APIC Version Register. */
1447#define MSR_IA32_X2APIC_VERSION 0x803
1448/** X2APIC MSR - Task Priority Register. */
1449#define MSR_IA32_X2APIC_TPR 0x808
1450/** X2APIC MSR - Processor Priority register. */
1451#define MSR_IA32_X2APIC_PPR 0x80A
1452/** X2APIC MSR - End Of Interrupt register. */
1453#define MSR_IA32_X2APIC_EOI 0x80B
1454/** X2APIC MSR - Logical Destination Register. */
1455#define MSR_IA32_X2APIC_LDR 0x80D
1456/** X2APIC MSR - Spurious Interrupt Vector Register. */
1457#define MSR_IA32_X2APIC_SVR 0x80F
1458/** X2APIC MSR - In-service Register (bits 31:0). */
1459#define MSR_IA32_X2APIC_ISR0 0x810
1460/** X2APIC MSR - In-service Register (bits 63:32). */
1461#define MSR_IA32_X2APIC_ISR1 0x811
1462/** X2APIC MSR - In-service Register (bits 95:64). */
1463#define MSR_IA32_X2APIC_ISR2 0x812
1464/** X2APIC MSR - In-service Register (bits 127:96). */
1465#define MSR_IA32_X2APIC_ISR3 0x813
1466/** X2APIC MSR - In-service Register (bits 159:128). */
1467#define MSR_IA32_X2APIC_ISR4 0x814
1468/** X2APIC MSR - In-service Register (bits 191:160). */
1469#define MSR_IA32_X2APIC_ISR5 0x815
1470/** X2APIC MSR - In-service Register (bits 223:192). */
1471#define MSR_IA32_X2APIC_ISR6 0x816
1472/** X2APIC MSR - In-service Register (bits 255:224). */
1473#define MSR_IA32_X2APIC_ISR7 0x817
1474/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1475#define MSR_IA32_X2APIC_TMR0 0x818
1476/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1477#define MSR_IA32_X2APIC_TMR1 0x819
1478/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1479#define MSR_IA32_X2APIC_TMR2 0x81A
1480/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1481#define MSR_IA32_X2APIC_TMR3 0x81B
1482/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1483#define MSR_IA32_X2APIC_TMR4 0x81C
1484/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1485#define MSR_IA32_X2APIC_TMR5 0x81D
1486/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1487#define MSR_IA32_X2APIC_TMR6 0x81E
1488/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1489#define MSR_IA32_X2APIC_TMR7 0x81F
1490/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1491#define MSR_IA32_X2APIC_IRR0 0x820
1492/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1493#define MSR_IA32_X2APIC_IRR1 0x821
1494/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1495#define MSR_IA32_X2APIC_IRR2 0x822
1496/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1497#define MSR_IA32_X2APIC_IRR3 0x823
1498/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1499#define MSR_IA32_X2APIC_IRR4 0x824
1500/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1501#define MSR_IA32_X2APIC_IRR5 0x825
1502/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1503#define MSR_IA32_X2APIC_IRR6 0x826
1504/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1505#define MSR_IA32_X2APIC_IRR7 0x827
1506/** X2APIC MSR - Error Status Register. */
1507#define MSR_IA32_X2APIC_ESR 0x828
1508/** X2APIC MSR - LVT CMCI Register. */
1509#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1510/** X2APIC MSR - Interrupt Command Register. */
1511#define MSR_IA32_X2APIC_ICR 0x830
1512/** X2APIC MSR - LVT Timer Register. */
1513#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1514/** X2APIC MSR - LVT Thermal Sensor Register. */
1515#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1516/** X2APIC MSR - LVT Performance Counter Register. */
1517#define MSR_IA32_X2APIC_LVT_PERF 0x834
1518/** X2APIC MSR - LVT LINT0 Register. */
1519#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1520/** X2APIC MSR - LVT LINT1 Register. */
1521#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1522/** X2APIC MSR - LVT Error Register . */
1523#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1524/** X2APIC MSR - Timer Initial Count Register. */
1525#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1526/** X2APIC MSR - Timer Current Count Register. */
1527#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1528/** X2APIC MSR - Timer Divide Configuration Register. */
1529#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1530/** X2APIC MSR - Self IPI. */
1531#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1532/** X2APIC MSR range end. */
1533#define MSR_IA32_X2APIC_END 0xBFF
1534/** X2APIC MSR - LVT start range. */
1535#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1536/** X2APIC MSR - LVT end range (inclusive). */
1537#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1538
1539/** K6 EFER - Extended Feature Enable Register. */
1540#define MSR_K6_EFER UINT32_C(0xc0000080)
1541/** @todo document EFER */
1542/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1543#define MSR_K6_EFER_SCE RT_BIT_32(0)
1544/** Bit 8 - LME - Long mode enabled. (R/W) */
1545#define MSR_K6_EFER_LME RT_BIT_32(8)
1546/** Bit 10 - LMA - Long mode active. (R) */
1547#define MSR_K6_EFER_LMA RT_BIT_32(10)
1548/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1549#define MSR_K6_EFER_NXE RT_BIT_32(11)
1550#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1551/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1552#define MSR_K6_EFER_SVME RT_BIT_32(12)
1553/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1554#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1555/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1556#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1557/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1558#define MSR_K6_EFER_TCE RT_BIT_32(15)
1559/** K6 STAR - SYSCALL/RET targets. */
1560#define MSR_K6_STAR UINT32_C(0xc0000081)
1561/** Shift value for getting the SYSRET CS and SS value. */
1562#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1563/** Shift value for getting the SYSCALL CS and SS value. */
1564#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1565/** Selector mask for use after shifting. */
1566#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1567/** The mask which give the SYSCALL EIP. */
1568#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1569/** K6 WHCR - Write Handling Control Register. */
1570#define MSR_K6_WHCR UINT32_C(0xc0000082)
1571/** K6 UWCCR - UC/WC Cacheability Control Register. */
1572#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1573/** K6 PSOR - Processor State Observability Register. */
1574#define MSR_K6_PSOR UINT32_C(0xc0000087)
1575/** K6 PFIR - Page Flush/Invalidate Register. */
1576#define MSR_K6_PFIR UINT32_C(0xc0000088)
1577
1578/** Performance counter MSRs. (AMD only) */
1579#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1580#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1581#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1582#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1583#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1584#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1585#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1586#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1587
1588/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1589#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1590/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1591#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1592/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1593#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1594/** K8 FS.base - The 64-bit base FS register. */
1595#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1596/** K8 GS.base - The 64-bit base GS register. */
1597#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1598/** K8 KernelGSbase - Used with SWAPGS. */
1599#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1600/** K8 TSC_AUX - Used with RDTSCP. */
1601#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1602#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1603#define MSR_K8_HWCR UINT32_C(0xc0010015)
1604#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1605#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1606#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1607#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1608#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1609#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1610/** North bridge config? See BIOS & Kernel dev guides for
1611 * details. */
1612#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1613
1614/** Hypertransport interrupt pending register.
1615 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1616#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1617
1618/** SVM Control. */
1619#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1620/** Disables HDT (Hardware Debug Tool) and certain internal debug
1621 * features. */
1622#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1623/** If set, non-intercepted INIT signals are converted to \#SX
1624 * exceptions. */
1625#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1626/** Disables A20 masking. */
1627#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1628/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1629#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1630/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1631 * clear, EFER.SVME can be written normally. */
1632#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1633
1634#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1635#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1636/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1637 * host state during world switch. */
1638#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1639
1640/** @} */
1641
1642
1643/** @name Page Table / Directory / Directory Pointers / L4.
1644 * @{
1645 */
1646
1647/** Page table/directory entry as an unsigned integer. */
1648typedef uint32_t X86PGUINT;
1649/** Pointer to a page table/directory table entry as an unsigned integer. */
1650typedef X86PGUINT *PX86PGUINT;
1651/** Pointer to an const page table/directory table entry as an unsigned integer. */
1652typedef X86PGUINT const *PCX86PGUINT;
1653
1654/** Number of entries in a 32-bit PT/PD. */
1655#define X86_PG_ENTRIES 1024
1656
1657
1658/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1659typedef uint64_t X86PGPAEUINT;
1660/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1661typedef X86PGPAEUINT *PX86PGPAEUINT;
1662/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1663typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1664
1665/** Number of entries in a PAE PT/PD. */
1666#define X86_PG_PAE_ENTRIES 512
1667/** Number of entries in a PAE PDPT. */
1668#define X86_PG_PAE_PDPE_ENTRIES 4
1669
1670/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1671#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1672/** Number of entries in an AMD64 PDPT.
1673 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1674#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1675
1676/** The size of a default page. */
1677#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1678/** The page shift of a default page. */
1679#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1680/** The default page offset mask. */
1681#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1682/** The default page base mask for virtual addresses. */
1683#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1684/** The default page base mask for virtual addresses - 32bit version. */
1685#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1686
1687/** The size of a 4KB page. */
1688#define X86_PAGE_4K_SIZE _4K
1689/** The page shift of a 4KB page. */
1690#define X86_PAGE_4K_SHIFT 12
1691/** The 4KB page offset mask. */
1692#define X86_PAGE_4K_OFFSET_MASK 0xfff
1693/** The 4KB page base mask for virtual addresses. */
1694#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1695/** The 4KB page base mask for virtual addresses - 32bit version. */
1696#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1697
1698/** The size of a 2MB page. */
1699#define X86_PAGE_2M_SIZE _2M
1700/** The page shift of a 2MB page. */
1701#define X86_PAGE_2M_SHIFT 21
1702/** The 2MB page offset mask. */
1703#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1704/** The 2MB page base mask for virtual addresses. */
1705#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1706/** The 2MB page base mask for virtual addresses - 32bit version. */
1707#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1708
1709/** The size of a 4MB page. */
1710#define X86_PAGE_4M_SIZE _4M
1711/** The page shift of a 4MB page. */
1712#define X86_PAGE_4M_SHIFT 22
1713/** The 4MB page offset mask. */
1714#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1715/** The 4MB page base mask for virtual addresses. */
1716#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1717/** The 4MB page base mask for virtual addresses - 32bit version. */
1718#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1719
1720/** The size of a 1GB page. */
1721#define X86_PAGE_1G_SIZE _1G
1722/** The page shift of a 1GB page. */
1723#define X86_PAGE_1G_SHIFT 30
1724/** The 1GB page offset mask. */
1725#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1726/** The 1GB page base mask for virtual addresses. */
1727#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1728
1729/**
1730 * Check if the given address is canonical.
1731 */
1732#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1733
1734
1735/** @name Page Table Entry
1736 * @{
1737 */
1738/** Bit 0 - P - Present bit. */
1739#define X86_PTE_BIT_P 0
1740/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1741#define X86_PTE_BIT_RW 1
1742/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1743#define X86_PTE_BIT_US 2
1744/** Bit 3 - PWT - Page level write thru bit. */
1745#define X86_PTE_BIT_PWT 3
1746/** Bit 4 - PCD - Page level cache disable bit. */
1747#define X86_PTE_BIT_PCD 4
1748/** Bit 5 - A - Access bit. */
1749#define X86_PTE_BIT_A 5
1750/** Bit 6 - D - Dirty bit. */
1751#define X86_PTE_BIT_D 6
1752/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1753#define X86_PTE_BIT_PAT 7
1754/** Bit 8 - G - Global flag. */
1755#define X86_PTE_BIT_G 8
1756/** Bits 63 - NX - PAE/LM - No execution flag. */
1757#define X86_PTE_PAE_BIT_NX 63
1758
1759/** Bit 0 - P - Present bit mask. */
1760#define X86_PTE_P RT_BIT_32(0)
1761/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1762#define X86_PTE_RW RT_BIT_32(1)
1763/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1764#define X86_PTE_US RT_BIT_32(2)
1765/** Bit 3 - PWT - Page level write thru bit mask. */
1766#define X86_PTE_PWT RT_BIT_32(3)
1767/** Bit 4 - PCD - Page level cache disable bit mask. */
1768#define X86_PTE_PCD RT_BIT_32(4)
1769/** Bit 5 - A - Access bit mask. */
1770#define X86_PTE_A RT_BIT_32(5)
1771/** Bit 6 - D - Dirty bit mask. */
1772#define X86_PTE_D RT_BIT_32(6)
1773/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1774#define X86_PTE_PAT RT_BIT_32(7)
1775/** Bit 8 - G - Global bit mask. */
1776#define X86_PTE_G RT_BIT_32(8)
1777
1778/** Bits 9-11 - - Available for use to system software. */
1779#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1780/** Bits 12-31 - - Physical Page number of the next level. */
1781#define X86_PTE_PG_MASK ( 0xfffff000 )
1782
1783/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1784#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1785/** Bits 63 - NX - PAE/LM - No execution flag. */
1786#define X86_PTE_PAE_NX RT_BIT_64(63)
1787/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1788#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1789/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1790#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1791/** No bits - - LM - MBZ bits when NX is active. */
1792#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1793/** Bits 63 - - LM - MBZ bits when no NX. */
1794#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1795
1796/**
1797 * Page table entry.
1798 */
1799typedef struct X86PTEBITS
1800{
1801 /** Flags whether(=1) or not the page is present. */
1802 uint32_t u1Present : 1;
1803 /** Read(=0) / Write(=1) flag. */
1804 uint32_t u1Write : 1;
1805 /** User(=1) / Supervisor (=0) flag. */
1806 uint32_t u1User : 1;
1807 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1808 uint32_t u1WriteThru : 1;
1809 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1810 uint32_t u1CacheDisable : 1;
1811 /** Accessed flag.
1812 * Indicates that the page have been read or written to. */
1813 uint32_t u1Accessed : 1;
1814 /** Dirty flag.
1815 * Indicates that the page has been written to. */
1816 uint32_t u1Dirty : 1;
1817 /** Reserved / If PAT enabled, bit 2 of the index. */
1818 uint32_t u1PAT : 1;
1819 /** Global flag. (Ignored in all but final level.) */
1820 uint32_t u1Global : 1;
1821 /** Available for use to system software. */
1822 uint32_t u3Available : 3;
1823 /** Physical Page number of the next level. */
1824 uint32_t u20PageNo : 20;
1825} X86PTEBITS;
1826#ifndef VBOX_FOR_DTRACE_LIB
1827AssertCompileSize(X86PTEBITS, 4);
1828#endif
1829/** Pointer to a page table entry. */
1830typedef X86PTEBITS *PX86PTEBITS;
1831/** Pointer to a const page table entry. */
1832typedef const X86PTEBITS *PCX86PTEBITS;
1833
1834/**
1835 * Page table entry.
1836 */
1837typedef union X86PTE
1838{
1839 /** Unsigned integer view */
1840 X86PGUINT u;
1841 /** Bit field view. */
1842 X86PTEBITS n;
1843 /** 32-bit view. */
1844 uint32_t au32[1];
1845 /** 16-bit view. */
1846 uint16_t au16[2];
1847 /** 8-bit view. */
1848 uint8_t au8[4];
1849} X86PTE;
1850#ifndef VBOX_FOR_DTRACE_LIB
1851AssertCompileSize(X86PTE, 4);
1852#endif
1853/** Pointer to a page table entry. */
1854typedef X86PTE *PX86PTE;
1855/** Pointer to a const page table entry. */
1856typedef const X86PTE *PCX86PTE;
1857
1858
1859/**
1860 * PAE page table entry.
1861 */
1862typedef struct X86PTEPAEBITS
1863{
1864 /** Flags whether(=1) or not the page is present. */
1865 uint32_t u1Present : 1;
1866 /** Read(=0) / Write(=1) flag. */
1867 uint32_t u1Write : 1;
1868 /** User(=1) / Supervisor(=0) flag. */
1869 uint32_t u1User : 1;
1870 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1871 uint32_t u1WriteThru : 1;
1872 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1873 uint32_t u1CacheDisable : 1;
1874 /** Accessed flag.
1875 * Indicates that the page have been read or written to. */
1876 uint32_t u1Accessed : 1;
1877 /** Dirty flag.
1878 * Indicates that the page has been written to. */
1879 uint32_t u1Dirty : 1;
1880 /** Reserved / If PAT enabled, bit 2 of the index. */
1881 uint32_t u1PAT : 1;
1882 /** Global flag. (Ignored in all but final level.) */
1883 uint32_t u1Global : 1;
1884 /** Available for use to system software. */
1885 uint32_t u3Available : 3;
1886 /** Physical Page number of the next level - Low Part. Don't use this. */
1887 uint32_t u20PageNoLow : 20;
1888 /** Physical Page number of the next level - High Part. Don't use this. */
1889 uint32_t u20PageNoHigh : 20;
1890 /** MBZ bits */
1891 uint32_t u11Reserved : 11;
1892 /** No Execute flag. */
1893 uint32_t u1NoExecute : 1;
1894} X86PTEPAEBITS;
1895#ifndef VBOX_FOR_DTRACE_LIB
1896AssertCompileSize(X86PTEPAEBITS, 8);
1897#endif
1898/** Pointer to a page table entry. */
1899typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1900/** Pointer to a page table entry. */
1901typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1902
1903/**
1904 * PAE Page table entry.
1905 */
1906typedef union X86PTEPAE
1907{
1908 /** Unsigned integer view */
1909 X86PGPAEUINT u;
1910 /** Bit field view. */
1911 X86PTEPAEBITS n;
1912 /** 32-bit view. */
1913 uint32_t au32[2];
1914 /** 16-bit view. */
1915 uint16_t au16[4];
1916 /** 8-bit view. */
1917 uint8_t au8[8];
1918} X86PTEPAE;
1919#ifndef VBOX_FOR_DTRACE_LIB
1920AssertCompileSize(X86PTEPAE, 8);
1921#endif
1922/** Pointer to a PAE page table entry. */
1923typedef X86PTEPAE *PX86PTEPAE;
1924/** Pointer to a const PAE page table entry. */
1925typedef const X86PTEPAE *PCX86PTEPAE;
1926/** @} */
1927
1928/**
1929 * Page table.
1930 */
1931typedef struct X86PT
1932{
1933 /** PTE Array. */
1934 X86PTE a[X86_PG_ENTRIES];
1935} X86PT;
1936#ifndef VBOX_FOR_DTRACE_LIB
1937AssertCompileSize(X86PT, 4096);
1938#endif
1939/** Pointer to a page table. */
1940typedef X86PT *PX86PT;
1941/** Pointer to a const page table. */
1942typedef const X86PT *PCX86PT;
1943
1944/** The page shift to get the PT index. */
1945#define X86_PT_SHIFT 12
1946/** The PT index mask (apply to a shifted page address). */
1947#define X86_PT_MASK 0x3ff
1948
1949
1950/**
1951 * Page directory.
1952 */
1953typedef struct X86PTPAE
1954{
1955 /** PTE Array. */
1956 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1957} X86PTPAE;
1958#ifndef VBOX_FOR_DTRACE_LIB
1959AssertCompileSize(X86PTPAE, 4096);
1960#endif
1961/** Pointer to a page table. */
1962typedef X86PTPAE *PX86PTPAE;
1963/** Pointer to a const page table. */
1964typedef const X86PTPAE *PCX86PTPAE;
1965
1966/** The page shift to get the PA PTE index. */
1967#define X86_PT_PAE_SHIFT 12
1968/** The PAE PT index mask (apply to a shifted page address). */
1969#define X86_PT_PAE_MASK 0x1ff
1970
1971
1972/** @name 4KB Page Directory Entry
1973 * @{
1974 */
1975/** Bit 0 - P - Present bit. */
1976#define X86_PDE_P RT_BIT_32(0)
1977/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1978#define X86_PDE_RW RT_BIT_32(1)
1979/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1980#define X86_PDE_US RT_BIT_32(2)
1981/** Bit 3 - PWT - Page level write thru bit. */
1982#define X86_PDE_PWT RT_BIT_32(3)
1983/** Bit 4 - PCD - Page level cache disable bit. */
1984#define X86_PDE_PCD RT_BIT_32(4)
1985/** Bit 5 - A - Access bit. */
1986#define X86_PDE_A RT_BIT_32(5)
1987/** Bit 7 - PS - Page size attribute.
1988 * Clear mean 4KB pages, set means large pages (2/4MB). */
1989#define X86_PDE_PS RT_BIT_32(7)
1990/** Bits 9-11 - - Available for use to system software. */
1991#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1992/** Bits 12-31 - - Physical Page number of the next level. */
1993#define X86_PDE_PG_MASK ( 0xfffff000 )
1994
1995/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1996#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1997/** Bits 63 - NX - PAE/LM - No execution flag. */
1998#define X86_PDE_PAE_NX RT_BIT_64(63)
1999/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2000#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2001/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2002#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2003/** Bit 7 - - LM - MBZ bits when NX is active. */
2004#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2005/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2006#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2007
2008/**
2009 * Page directory entry.
2010 */
2011typedef struct X86PDEBITS
2012{
2013 /** Flags whether(=1) or not the page is present. */
2014 uint32_t u1Present : 1;
2015 /** Read(=0) / Write(=1) flag. */
2016 uint32_t u1Write : 1;
2017 /** User(=1) / Supervisor (=0) flag. */
2018 uint32_t u1User : 1;
2019 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2020 uint32_t u1WriteThru : 1;
2021 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2022 uint32_t u1CacheDisable : 1;
2023 /** Accessed flag.
2024 * Indicates that the page has been read or written to. */
2025 uint32_t u1Accessed : 1;
2026 /** Reserved / Ignored (dirty bit). */
2027 uint32_t u1Reserved0 : 1;
2028 /** Size bit if PSE is enabled - in any event it's 0. */
2029 uint32_t u1Size : 1;
2030 /** Reserved / Ignored (global bit). */
2031 uint32_t u1Reserved1 : 1;
2032 /** Available for use to system software. */
2033 uint32_t u3Available : 3;
2034 /** Physical Page number of the next level. */
2035 uint32_t u20PageNo : 20;
2036} X86PDEBITS;
2037#ifndef VBOX_FOR_DTRACE_LIB
2038AssertCompileSize(X86PDEBITS, 4);
2039#endif
2040/** Pointer to a page directory entry. */
2041typedef X86PDEBITS *PX86PDEBITS;
2042/** Pointer to a const page directory entry. */
2043typedef const X86PDEBITS *PCX86PDEBITS;
2044
2045
2046/**
2047 * PAE page directory entry.
2048 */
2049typedef struct X86PDEPAEBITS
2050{
2051 /** Flags whether(=1) or not the page is present. */
2052 uint32_t u1Present : 1;
2053 /** Read(=0) / Write(=1) flag. */
2054 uint32_t u1Write : 1;
2055 /** User(=1) / Supervisor (=0) flag. */
2056 uint32_t u1User : 1;
2057 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2058 uint32_t u1WriteThru : 1;
2059 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2060 uint32_t u1CacheDisable : 1;
2061 /** Accessed flag.
2062 * Indicates that the page has been read or written to. */
2063 uint32_t u1Accessed : 1;
2064 /** Reserved / Ignored (dirty bit). */
2065 uint32_t u1Reserved0 : 1;
2066 /** Size bit if PSE is enabled - in any event it's 0. */
2067 uint32_t u1Size : 1;
2068 /** Reserved / Ignored (global bit). / */
2069 uint32_t u1Reserved1 : 1;
2070 /** Available for use to system software. */
2071 uint32_t u3Available : 3;
2072 /** Physical Page number of the next level - Low Part. Don't use! */
2073 uint32_t u20PageNoLow : 20;
2074 /** Physical Page number of the next level - High Part. Don't use! */
2075 uint32_t u20PageNoHigh : 20;
2076 /** MBZ bits */
2077 uint32_t u11Reserved : 11;
2078 /** No Execute flag. */
2079 uint32_t u1NoExecute : 1;
2080} X86PDEPAEBITS;
2081#ifndef VBOX_FOR_DTRACE_LIB
2082AssertCompileSize(X86PDEPAEBITS, 8);
2083#endif
2084/** Pointer to a page directory entry. */
2085typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2086/** Pointer to a const page directory entry. */
2087typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2088
2089/** @} */
2090
2091
2092/** @name 2/4MB Page Directory Entry
2093 * @{
2094 */
2095/** Bit 0 - P - Present bit. */
2096#define X86_PDE4M_P RT_BIT_32(0)
2097/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2098#define X86_PDE4M_RW RT_BIT_32(1)
2099/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2100#define X86_PDE4M_US RT_BIT_32(2)
2101/** Bit 3 - PWT - Page level write thru bit. */
2102#define X86_PDE4M_PWT RT_BIT_32(3)
2103/** Bit 4 - PCD - Page level cache disable bit. */
2104#define X86_PDE4M_PCD RT_BIT_32(4)
2105/** Bit 5 - A - Access bit. */
2106#define X86_PDE4M_A RT_BIT_32(5)
2107/** Bit 6 - D - Dirty bit. */
2108#define X86_PDE4M_D RT_BIT_32(6)
2109/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2110#define X86_PDE4M_PS RT_BIT_32(7)
2111/** Bit 8 - G - Global flag. */
2112#define X86_PDE4M_G RT_BIT_32(8)
2113/** Bits 9-11 - AVL - Available for use to system software. */
2114#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2115/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2116#define X86_PDE4M_PAT RT_BIT_32(12)
2117/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2118#define X86_PDE4M_PAT_SHIFT (12 - 7)
2119/** Bits 22-31 - - Physical Page number. */
2120#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2121/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2122#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2123/** The number of bits to the high part of the page number. */
2124#define X86_PDE4M_PG_HIGH_SHIFT 19
2125/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2126#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2127
2128/** Bits 21-51 - - PAE/LM - Physical Page number.
2129 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2130#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2131/** Bits 63 - NX - PAE/LM - No execution flag. */
2132#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2133/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2134#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2135/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2136#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2137/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2138#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2139/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2140#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2141
2142/**
2143 * 4MB page directory entry.
2144 */
2145typedef struct X86PDE4MBITS
2146{
2147 /** Flags whether(=1) or not the page is present. */
2148 uint32_t u1Present : 1;
2149 /** Read(=0) / Write(=1) flag. */
2150 uint32_t u1Write : 1;
2151 /** User(=1) / Supervisor (=0) flag. */
2152 uint32_t u1User : 1;
2153 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2154 uint32_t u1WriteThru : 1;
2155 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2156 uint32_t u1CacheDisable : 1;
2157 /** Accessed flag.
2158 * Indicates that the page have been read or written to. */
2159 uint32_t u1Accessed : 1;
2160 /** Dirty flag.
2161 * Indicates that the page has been written to. */
2162 uint32_t u1Dirty : 1;
2163 /** Page size flag - always 1 for 4MB entries. */
2164 uint32_t u1Size : 1;
2165 /** Global flag. */
2166 uint32_t u1Global : 1;
2167 /** Available for use to system software. */
2168 uint32_t u3Available : 3;
2169 /** Reserved / If PAT enabled, bit 2 of the index. */
2170 uint32_t u1PAT : 1;
2171 /** Bits 32-39 of the page number on AMD64.
2172 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2173 uint32_t u8PageNoHigh : 8;
2174 /** Reserved. */
2175 uint32_t u1Reserved : 1;
2176 /** Physical Page number of the page. */
2177 uint32_t u10PageNo : 10;
2178} X86PDE4MBITS;
2179#ifndef VBOX_FOR_DTRACE_LIB
2180AssertCompileSize(X86PDE4MBITS, 4);
2181#endif
2182/** Pointer to a page table entry. */
2183typedef X86PDE4MBITS *PX86PDE4MBITS;
2184/** Pointer to a const page table entry. */
2185typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2186
2187
2188/**
2189 * 2MB PAE page directory entry.
2190 */
2191typedef struct X86PDE2MPAEBITS
2192{
2193 /** Flags whether(=1) or not the page is present. */
2194 uint32_t u1Present : 1;
2195 /** Read(=0) / Write(=1) flag. */
2196 uint32_t u1Write : 1;
2197 /** User(=1) / Supervisor(=0) flag. */
2198 uint32_t u1User : 1;
2199 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2200 uint32_t u1WriteThru : 1;
2201 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2202 uint32_t u1CacheDisable : 1;
2203 /** Accessed flag.
2204 * Indicates that the page have been read or written to. */
2205 uint32_t u1Accessed : 1;
2206 /** Dirty flag.
2207 * Indicates that the page has been written to. */
2208 uint32_t u1Dirty : 1;
2209 /** Page size flag - always 1 for 2MB entries. */
2210 uint32_t u1Size : 1;
2211 /** Global flag. */
2212 uint32_t u1Global : 1;
2213 /** Available for use to system software. */
2214 uint32_t u3Available : 3;
2215 /** Reserved / If PAT enabled, bit 2 of the index. */
2216 uint32_t u1PAT : 1;
2217 /** Reserved. */
2218 uint32_t u9Reserved : 9;
2219 /** Physical Page number of the next level - Low part. Don't use! */
2220 uint32_t u10PageNoLow : 10;
2221 /** Physical Page number of the next level - High part. Don't use! */
2222 uint32_t u20PageNoHigh : 20;
2223 /** MBZ bits */
2224 uint32_t u11Reserved : 11;
2225 /** No Execute flag. */
2226 uint32_t u1NoExecute : 1;
2227} X86PDE2MPAEBITS;
2228#ifndef VBOX_FOR_DTRACE_LIB
2229AssertCompileSize(X86PDE2MPAEBITS, 8);
2230#endif
2231/** Pointer to a 2MB PAE page table entry. */
2232typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2233/** Pointer to a 2MB PAE page table entry. */
2234typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2235
2236/** @} */
2237
2238/**
2239 * Page directory entry.
2240 */
2241typedef union X86PDE
2242{
2243 /** Unsigned integer view. */
2244 X86PGUINT u;
2245 /** Normal view. */
2246 X86PDEBITS n;
2247 /** 4MB view (big). */
2248 X86PDE4MBITS b;
2249 /** 8 bit unsigned integer view. */
2250 uint8_t au8[4];
2251 /** 16 bit unsigned integer view. */
2252 uint16_t au16[2];
2253 /** 32 bit unsigned integer view. */
2254 uint32_t au32[1];
2255} X86PDE;
2256#ifndef VBOX_FOR_DTRACE_LIB
2257AssertCompileSize(X86PDE, 4);
2258#endif
2259/** Pointer to a page directory entry. */
2260typedef X86PDE *PX86PDE;
2261/** Pointer to a const page directory entry. */
2262typedef const X86PDE *PCX86PDE;
2263
2264/**
2265 * PAE page directory entry.
2266 */
2267typedef union X86PDEPAE
2268{
2269 /** Unsigned integer view. */
2270 X86PGPAEUINT u;
2271 /** Normal view. */
2272 X86PDEPAEBITS n;
2273 /** 2MB page view (big). */
2274 X86PDE2MPAEBITS b;
2275 /** 8 bit unsigned integer view. */
2276 uint8_t au8[8];
2277 /** 16 bit unsigned integer view. */
2278 uint16_t au16[4];
2279 /** 32 bit unsigned integer view. */
2280 uint32_t au32[2];
2281} X86PDEPAE;
2282#ifndef VBOX_FOR_DTRACE_LIB
2283AssertCompileSize(X86PDEPAE, 8);
2284#endif
2285/** Pointer to a page directory entry. */
2286typedef X86PDEPAE *PX86PDEPAE;
2287/** Pointer to a const page directory entry. */
2288typedef const X86PDEPAE *PCX86PDEPAE;
2289
2290/**
2291 * Page directory.
2292 */
2293typedef struct X86PD
2294{
2295 /** PDE Array. */
2296 X86PDE a[X86_PG_ENTRIES];
2297} X86PD;
2298#ifndef VBOX_FOR_DTRACE_LIB
2299AssertCompileSize(X86PD, 4096);
2300#endif
2301/** Pointer to a page directory. */
2302typedef X86PD *PX86PD;
2303/** Pointer to a const page directory. */
2304typedef const X86PD *PCX86PD;
2305
2306/** The page shift to get the PD index. */
2307#define X86_PD_SHIFT 22
2308/** The PD index mask (apply to a shifted page address). */
2309#define X86_PD_MASK 0x3ff
2310
2311
2312/**
2313 * PAE page directory.
2314 */
2315typedef struct X86PDPAE
2316{
2317 /** PDE Array. */
2318 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2319} X86PDPAE;
2320#ifndef VBOX_FOR_DTRACE_LIB
2321AssertCompileSize(X86PDPAE, 4096);
2322#endif
2323/** Pointer to a PAE page directory. */
2324typedef X86PDPAE *PX86PDPAE;
2325/** Pointer to a const PAE page directory. */
2326typedef const X86PDPAE *PCX86PDPAE;
2327
2328/** The page shift to get the PAE PD index. */
2329#define X86_PD_PAE_SHIFT 21
2330/** The PAE PD index mask (apply to a shifted page address). */
2331#define X86_PD_PAE_MASK 0x1ff
2332
2333
2334/** @name Page Directory Pointer Table Entry (PAE)
2335 * @{
2336 */
2337/** Bit 0 - P - Present bit. */
2338#define X86_PDPE_P RT_BIT_32(0)
2339/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2340#define X86_PDPE_RW RT_BIT_32(1)
2341/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2342#define X86_PDPE_US RT_BIT_32(2)
2343/** Bit 3 - PWT - Page level write thru bit. */
2344#define X86_PDPE_PWT RT_BIT_32(3)
2345/** Bit 4 - PCD - Page level cache disable bit. */
2346#define X86_PDPE_PCD RT_BIT_32(4)
2347/** Bit 5 - A - Access bit. Long Mode only. */
2348#define X86_PDPE_A RT_BIT_32(5)
2349/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2350#define X86_PDPE_LM_PS RT_BIT_32(7)
2351/** Bits 9-11 - - Available for use to system software. */
2352#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2353/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2354#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2355/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2356#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2357/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2358#define X86_PDPE_LM_NX RT_BIT_64(63)
2359/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2360#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2361/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2362#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2363/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2364#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2365/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2366#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2367
2368
2369/**
2370 * Page directory pointer table entry.
2371 */
2372typedef struct X86PDPEBITS
2373{
2374 /** Flags whether(=1) or not the page is present. */
2375 uint32_t u1Present : 1;
2376 /** Chunk of reserved bits. */
2377 uint32_t u2Reserved : 2;
2378 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2379 uint32_t u1WriteThru : 1;
2380 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2381 uint32_t u1CacheDisable : 1;
2382 /** Chunk of reserved bits. */
2383 uint32_t u4Reserved : 4;
2384 /** Available for use to system software. */
2385 uint32_t u3Available : 3;
2386 /** Physical Page number of the next level - Low Part. Don't use! */
2387 uint32_t u20PageNoLow : 20;
2388 /** Physical Page number of the next level - High Part. Don't use! */
2389 uint32_t u20PageNoHigh : 20;
2390 /** MBZ bits */
2391 uint32_t u12Reserved : 12;
2392} X86PDPEBITS;
2393#ifndef VBOX_FOR_DTRACE_LIB
2394AssertCompileSize(X86PDPEBITS, 8);
2395#endif
2396/** Pointer to a page directory pointer table entry. */
2397typedef X86PDPEBITS *PX86PTPEBITS;
2398/** Pointer to a const page directory pointer table entry. */
2399typedef const X86PDPEBITS *PCX86PTPEBITS;
2400
2401/**
2402 * Page directory pointer table entry. AMD64 version
2403 */
2404typedef struct X86PDPEAMD64BITS
2405{
2406 /** Flags whether(=1) or not the page is present. */
2407 uint32_t u1Present : 1;
2408 /** Read(=0) / Write(=1) flag. */
2409 uint32_t u1Write : 1;
2410 /** User(=1) / Supervisor (=0) flag. */
2411 uint32_t u1User : 1;
2412 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2413 uint32_t u1WriteThru : 1;
2414 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2415 uint32_t u1CacheDisable : 1;
2416 /** Accessed flag.
2417 * Indicates that the page have been read or written to. */
2418 uint32_t u1Accessed : 1;
2419 /** Chunk of reserved bits. */
2420 uint32_t u3Reserved : 3;
2421 /** Available for use to system software. */
2422 uint32_t u3Available : 3;
2423 /** Physical Page number of the next level - Low Part. Don't use! */
2424 uint32_t u20PageNoLow : 20;
2425 /** Physical Page number of the next level - High Part. Don't use! */
2426 uint32_t u20PageNoHigh : 20;
2427 /** MBZ bits */
2428 uint32_t u11Reserved : 11;
2429 /** No Execute flag. */
2430 uint32_t u1NoExecute : 1;
2431} X86PDPEAMD64BITS;
2432#ifndef VBOX_FOR_DTRACE_LIB
2433AssertCompileSize(X86PDPEAMD64BITS, 8);
2434#endif
2435/** Pointer to a page directory pointer table entry. */
2436typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2437/** Pointer to a const page directory pointer table entry. */
2438typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2439
2440/**
2441 * Page directory pointer table entry for 1GB page. (AMD64 only)
2442 */
2443typedef struct X86PDPE1GB
2444{
2445 /** 0: Flags whether(=1) or not the page is present. */
2446 uint32_t u1Present : 1;
2447 /** 1: Read(=0) / Write(=1) flag. */
2448 uint32_t u1Write : 1;
2449 /** 2: User(=1) / Supervisor (=0) flag. */
2450 uint32_t u1User : 1;
2451 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2452 uint32_t u1WriteThru : 1;
2453 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2454 uint32_t u1CacheDisable : 1;
2455 /** 5: Accessed flag.
2456 * Indicates that the page have been read or written to. */
2457 uint32_t u1Accessed : 1;
2458 /** 6: Dirty flag for 1GB pages. */
2459 uint32_t u1Dirty : 1;
2460 /** 7: Indicates 1GB page if set. */
2461 uint32_t u1Size : 1;
2462 /** 8: Global 1GB page. */
2463 uint32_t u1Global: 1;
2464 /** 9-11: Available for use to system software. */
2465 uint32_t u3Available : 3;
2466 /** 12: PAT bit for 1GB page. */
2467 uint32_t u1PAT : 1;
2468 /** 13-29: MBZ bits. */
2469 uint32_t u17Reserved : 17;
2470 /** 30-31: Physical page number - Low Part. Don't use! */
2471 uint32_t u2PageNoLow : 2;
2472 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2473 uint32_t u20PageNoHigh : 20;
2474 /** 52-62: MBZ bits */
2475 uint32_t u11Reserved : 11;
2476 /** 63: No Execute flag. */
2477 uint32_t u1NoExecute : 1;
2478} X86PDPE1GB;
2479#ifndef VBOX_FOR_DTRACE_LIB
2480AssertCompileSize(X86PDPE1GB, 8);
2481#endif
2482/** Pointer to a page directory pointer table entry for a 1GB page. */
2483typedef X86PDPE1GB *PX86PDPE1GB;
2484/** Pointer to a const page directory pointer table entry for a 1GB page. */
2485typedef const X86PDPE1GB *PCX86PDPE1GB;
2486
2487/**
2488 * Page directory pointer table entry.
2489 */
2490typedef union X86PDPE
2491{
2492 /** Unsigned integer view. */
2493 X86PGPAEUINT u;
2494 /** Normal view. */
2495 X86PDPEBITS n;
2496 /** AMD64 view. */
2497 X86PDPEAMD64BITS lm;
2498 /** AMD64 big view. */
2499 X86PDPE1GB b;
2500 /** 8 bit unsigned integer view. */
2501 uint8_t au8[8];
2502 /** 16 bit unsigned integer view. */
2503 uint16_t au16[4];
2504 /** 32 bit unsigned integer view. */
2505 uint32_t au32[2];
2506} X86PDPE;
2507#ifndef VBOX_FOR_DTRACE_LIB
2508AssertCompileSize(X86PDPE, 8);
2509#endif
2510/** Pointer to a page directory pointer table entry. */
2511typedef X86PDPE *PX86PDPE;
2512/** Pointer to a const page directory pointer table entry. */
2513typedef const X86PDPE *PCX86PDPE;
2514
2515
2516/**
2517 * Page directory pointer table.
2518 */
2519typedef struct X86PDPT
2520{
2521 /** PDE Array. */
2522 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2523} X86PDPT;
2524#ifndef VBOX_FOR_DTRACE_LIB
2525AssertCompileSize(X86PDPT, 4096);
2526#endif
2527/** Pointer to a page directory pointer table. */
2528typedef X86PDPT *PX86PDPT;
2529/** Pointer to a const page directory pointer table. */
2530typedef const X86PDPT *PCX86PDPT;
2531
2532/** The page shift to get the PDPT index. */
2533#define X86_PDPT_SHIFT 30
2534/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2535#define X86_PDPT_MASK_PAE 0x3
2536/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2537#define X86_PDPT_MASK_AMD64 0x1ff
2538
2539/** @} */
2540
2541
2542/** @name Page Map Level-4 Entry (Long Mode PAE)
2543 * @{
2544 */
2545/** Bit 0 - P - Present bit. */
2546#define X86_PML4E_P RT_BIT_32(0)
2547/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2548#define X86_PML4E_RW RT_BIT_32(1)
2549/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2550#define X86_PML4E_US RT_BIT_32(2)
2551/** Bit 3 - PWT - Page level write thru bit. */
2552#define X86_PML4E_PWT RT_BIT_32(3)
2553/** Bit 4 - PCD - Page level cache disable bit. */
2554#define X86_PML4E_PCD RT_BIT_32(4)
2555/** Bit 5 - A - Access bit. */
2556#define X86_PML4E_A RT_BIT_32(5)
2557/** Bits 9-11 - - Available for use to system software. */
2558#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2559/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2560#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2561/** Bits 8, 7 - - MBZ bits when NX is active. */
2562#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2563/** Bits 63, 7 - - MBZ bits when no NX. */
2564#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2565/** Bits 63 - NX - PAE - No execution flag. */
2566#define X86_PML4E_NX RT_BIT_64(63)
2567
2568/**
2569 * Page Map Level-4 Entry
2570 */
2571typedef struct X86PML4EBITS
2572{
2573 /** Flags whether(=1) or not the page is present. */
2574 uint32_t u1Present : 1;
2575 /** Read(=0) / Write(=1) flag. */
2576 uint32_t u1Write : 1;
2577 /** User(=1) / Supervisor (=0) flag. */
2578 uint32_t u1User : 1;
2579 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2580 uint32_t u1WriteThru : 1;
2581 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2582 uint32_t u1CacheDisable : 1;
2583 /** Accessed flag.
2584 * Indicates that the page have been read or written to. */
2585 uint32_t u1Accessed : 1;
2586 /** Chunk of reserved bits. */
2587 uint32_t u3Reserved : 3;
2588 /** Available for use to system software. */
2589 uint32_t u3Available : 3;
2590 /** Physical Page number of the next level - Low Part. Don't use! */
2591 uint32_t u20PageNoLow : 20;
2592 /** Physical Page number of the next level - High Part. Don't use! */
2593 uint32_t u20PageNoHigh : 20;
2594 /** MBZ bits */
2595 uint32_t u11Reserved : 11;
2596 /** No Execute flag. */
2597 uint32_t u1NoExecute : 1;
2598} X86PML4EBITS;
2599#ifndef VBOX_FOR_DTRACE_LIB
2600AssertCompileSize(X86PML4EBITS, 8);
2601#endif
2602/** Pointer to a page map level-4 entry. */
2603typedef X86PML4EBITS *PX86PML4EBITS;
2604/** Pointer to a const page map level-4 entry. */
2605typedef const X86PML4EBITS *PCX86PML4EBITS;
2606
2607/**
2608 * Page Map Level-4 Entry.
2609 */
2610typedef union X86PML4E
2611{
2612 /** Unsigned integer view. */
2613 X86PGPAEUINT u;
2614 /** Normal view. */
2615 X86PML4EBITS n;
2616 /** 8 bit unsigned integer view. */
2617 uint8_t au8[8];
2618 /** 16 bit unsigned integer view. */
2619 uint16_t au16[4];
2620 /** 32 bit unsigned integer view. */
2621 uint32_t au32[2];
2622} X86PML4E;
2623#ifndef VBOX_FOR_DTRACE_LIB
2624AssertCompileSize(X86PML4E, 8);
2625#endif
2626/** Pointer to a page map level-4 entry. */
2627typedef X86PML4E *PX86PML4E;
2628/** Pointer to a const page map level-4 entry. */
2629typedef const X86PML4E *PCX86PML4E;
2630
2631
2632/**
2633 * Page Map Level-4.
2634 */
2635typedef struct X86PML4
2636{
2637 /** PDE Array. */
2638 X86PML4E a[X86_PG_PAE_ENTRIES];
2639} X86PML4;
2640#ifndef VBOX_FOR_DTRACE_LIB
2641AssertCompileSize(X86PML4, 4096);
2642#endif
2643/** Pointer to a page map level-4. */
2644typedef X86PML4 *PX86PML4;
2645/** Pointer to a const page map level-4. */
2646typedef const X86PML4 *PCX86PML4;
2647
2648/** The page shift to get the PML4 index. */
2649#define X86_PML4_SHIFT 39
2650/** The PML4 index mask (apply to a shifted page address). */
2651#define X86_PML4_MASK 0x1ff
2652
2653/** @} */
2654
2655/** @} */
2656
2657/**
2658 * Intel PCID invalidation types.
2659 */
2660/** Individual address invalidation. */
2661#define X86_INVPCID_TYPE_INDV_ADDR 0
2662/** Single-context invalidation. */
2663#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2664/** All-context including globals invalidation. */
2665#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2666/** All-context excluding globals invalidation. */
2667#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2668/** The maximum valid invalidation type value. */
2669#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2670
2671/**
2672 * 32-bit protected mode FSTENV image.
2673 */
2674typedef struct X86FSTENV32P
2675{
2676 uint16_t FCW;
2677 uint16_t padding1;
2678 uint16_t FSW;
2679 uint16_t padding2;
2680 uint16_t FTW;
2681 uint16_t padding3;
2682 uint32_t FPUIP;
2683 uint16_t FPUCS;
2684 uint16_t FOP;
2685 uint32_t FPUDP;
2686 uint16_t FPUDS;
2687 uint16_t padding4;
2688} X86FSTENV32P;
2689/** Pointer to a 32-bit protected mode FSTENV image. */
2690typedef X86FSTENV32P *PX86FSTENV32P;
2691/** Pointer to a const 32-bit protected mode FSTENV image. */
2692typedef X86FSTENV32P const *PCX86FSTENV32P;
2693
2694
2695/**
2696 * 80-bit MMX/FPU register type.
2697 */
2698typedef struct X86FPUMMX
2699{
2700 uint8_t reg[10];
2701} X86FPUMMX;
2702#ifndef VBOX_FOR_DTRACE_LIB
2703AssertCompileSize(X86FPUMMX, 10);
2704#endif
2705/** Pointer to a 80-bit MMX/FPU register type. */
2706typedef X86FPUMMX *PX86FPUMMX;
2707/** Pointer to a const 80-bit MMX/FPU register type. */
2708typedef const X86FPUMMX *PCX86FPUMMX;
2709
2710/** FPU (x87) register. */
2711typedef union X86FPUREG
2712{
2713 /** MMX view. */
2714 uint64_t mmx;
2715 /** FPU view - todo. */
2716 X86FPUMMX fpu;
2717 /** Extended precision floating point view. */
2718 RTFLOAT80U r80;
2719 /** Extended precision floating point view v2 */
2720 RTFLOAT80U2 r80Ex;
2721 /** 8-bit view. */
2722 uint8_t au8[16];
2723 /** 16-bit view. */
2724 uint16_t au16[8];
2725 /** 32-bit view. */
2726 uint32_t au32[4];
2727 /** 64-bit view. */
2728 uint64_t au64[2];
2729 /** 128-bit view. (yeah, very helpful) */
2730 uint128_t au128[1];
2731} X86FPUREG;
2732#ifndef VBOX_FOR_DTRACE_LIB
2733AssertCompileSize(X86FPUREG, 16);
2734#endif
2735/** Pointer to a FPU register. */
2736typedef X86FPUREG *PX86FPUREG;
2737/** Pointer to a const FPU register. */
2738typedef X86FPUREG const *PCX86FPUREG;
2739
2740/**
2741 * XMM register union.
2742 */
2743typedef union X86XMMREG
2744{
2745 /** XMM Register view. */
2746 uint128_t xmm;
2747 /** 8-bit view. */
2748 uint8_t au8[16];
2749 /** 16-bit view. */
2750 uint16_t au16[8];
2751 /** 32-bit view. */
2752 uint32_t au32[4];
2753 /** 64-bit view. */
2754 uint64_t au64[2];
2755 /** 128-bit view. (yeah, very helpful) */
2756 uint128_t au128[1];
2757 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2758 RTUINT128U uXmm;
2759} X86XMMREG;
2760#ifndef VBOX_FOR_DTRACE_LIB
2761AssertCompileSize(X86XMMREG, 16);
2762#endif
2763/** Pointer to an XMM register state. */
2764typedef X86XMMREG *PX86XMMREG;
2765/** Pointer to a const XMM register state. */
2766typedef X86XMMREG const *PCX86XMMREG;
2767
2768/**
2769 * YMM register union.
2770 */
2771typedef union X86YMMREG
2772{
2773 /** 8-bit view. */
2774 uint8_t au8[32];
2775 /** 16-bit view. */
2776 uint16_t au16[16];
2777 /** 32-bit view. */
2778 uint32_t au32[8];
2779 /** 64-bit view. */
2780 uint64_t au64[4];
2781 /** 128-bit view. (yeah, very helpful) */
2782 uint128_t au128[2];
2783 /** XMM sub register view. */
2784 X86XMMREG aXmm[2];
2785} X86YMMREG;
2786#ifndef VBOX_FOR_DTRACE_LIB
2787AssertCompileSize(X86YMMREG, 32);
2788#endif
2789/** Pointer to an YMM register state. */
2790typedef X86YMMREG *PX86YMMREG;
2791/** Pointer to a const YMM register state. */
2792typedef X86YMMREG const *PCX86YMMREG;
2793
2794/**
2795 * ZMM register union.
2796 */
2797typedef union X86ZMMREG
2798{
2799 /** 8-bit view. */
2800 uint8_t au8[64];
2801 /** 16-bit view. */
2802 uint16_t au16[32];
2803 /** 32-bit view. */
2804 uint32_t au32[16];
2805 /** 64-bit view. */
2806 uint64_t au64[8];
2807 /** 128-bit view. (yeah, very helpful) */
2808 uint128_t au128[4];
2809 /** XMM sub register view. */
2810 X86XMMREG aXmm[4];
2811 /** YMM sub register view. */
2812 X86YMMREG aYmm[2];
2813} X86ZMMREG;
2814#ifndef VBOX_FOR_DTRACE_LIB
2815AssertCompileSize(X86ZMMREG, 64);
2816#endif
2817/** Pointer to an ZMM register state. */
2818typedef X86ZMMREG *PX86ZMMREG;
2819/** Pointer to a const ZMM register state. */
2820typedef X86ZMMREG const *PCX86ZMMREG;
2821
2822
2823/**
2824 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2825 * @todo verify this...
2826 */
2827#pragma pack(1)
2828typedef struct X86FPUSTATE
2829{
2830 /** 0x00 - Control word. */
2831 uint16_t FCW;
2832 /** 0x02 - Alignment word */
2833 uint16_t Dummy1;
2834 /** 0x04 - Status word. */
2835 uint16_t FSW;
2836 /** 0x06 - Alignment word */
2837 uint16_t Dummy2;
2838 /** 0x08 - Tag word */
2839 uint16_t FTW;
2840 /** 0x0a - Alignment word */
2841 uint16_t Dummy3;
2842
2843 /** 0x0c - Instruction pointer. */
2844 uint32_t FPUIP;
2845 /** 0x10 - Code selector. */
2846 uint16_t CS;
2847 /** 0x12 - Opcode. */
2848 uint16_t FOP;
2849 /** 0x14 - FOO. */
2850 uint32_t FPUOO;
2851 /** 0x18 - FOS. */
2852 uint32_t FPUOS;
2853 /** 0x1c - FPU register. */
2854 X86FPUREG regs[8];
2855} X86FPUSTATE;
2856#pragma pack()
2857/** Pointer to a FPU state. */
2858typedef X86FPUSTATE *PX86FPUSTATE;
2859/** Pointer to a const FPU state. */
2860typedef const X86FPUSTATE *PCX86FPUSTATE;
2861
2862/**
2863 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2864 */
2865#pragma pack(1)
2866typedef struct X86FXSTATE
2867{
2868 /** 0x00 - Control word. */
2869 uint16_t FCW;
2870 /** 0x02 - Status word. */
2871 uint16_t FSW;
2872 /** 0x04 - Tag word. (The upper byte is always zero.) */
2873 uint16_t FTW;
2874 /** 0x06 - Opcode. */
2875 uint16_t FOP;
2876 /** 0x08 - Instruction pointer. */
2877 uint32_t FPUIP;
2878 /** 0x0c - Code selector. */
2879 uint16_t CS;
2880 uint16_t Rsrvd1;
2881 /** 0x10 - Data pointer. */
2882 uint32_t FPUDP;
2883 /** 0x14 - Data segment */
2884 uint16_t DS;
2885 /** 0x16 */
2886 uint16_t Rsrvd2;
2887 /** 0x18 */
2888 uint32_t MXCSR;
2889 /** 0x1c */
2890 uint32_t MXCSR_MASK;
2891 /** 0x20 - FPU registers. */
2892 X86FPUREG aRegs[8];
2893 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2894 X86XMMREG aXMM[16];
2895 /* - offset 416 - */
2896 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2897 /* - offset 464 - Software usable reserved bits. */
2898 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2899} X86FXSTATE;
2900#pragma pack()
2901/** Pointer to a FPU Extended state. */
2902typedef X86FXSTATE *PX86FXSTATE;
2903/** Pointer to a const FPU Extended state. */
2904typedef const X86FXSTATE *PCX86FXSTATE;
2905
2906/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2907 * magic. Don't forget to update x86.mac if you change this! */
2908#define X86_OFF_FXSTATE_RSVD 0x1d0
2909/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2910 * forget to update x86.mac if you change this!
2911 * @todo r=bird: This has nothing what-so-ever to do here.... */
2912#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2913#ifndef VBOX_FOR_DTRACE_LIB
2914AssertCompileSize(X86FXSTATE, 512);
2915AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2916#endif
2917
2918/** @name FPU status word flags.
2919 * @{ */
2920/** Exception Flag: Invalid operation. */
2921#define X86_FSW_IE RT_BIT_32(0)
2922/** Exception Flag: Denormalized operand. */
2923#define X86_FSW_DE RT_BIT_32(1)
2924/** Exception Flag: Zero divide. */
2925#define X86_FSW_ZE RT_BIT_32(2)
2926/** Exception Flag: Overflow. */
2927#define X86_FSW_OE RT_BIT_32(3)
2928/** Exception Flag: Underflow. */
2929#define X86_FSW_UE RT_BIT_32(4)
2930/** Exception Flag: Precision. */
2931#define X86_FSW_PE RT_BIT_32(5)
2932/** Stack fault. */
2933#define X86_FSW_SF RT_BIT_32(6)
2934/** Error summary status. */
2935#define X86_FSW_ES RT_BIT_32(7)
2936/** Mask of exceptions flags, excluding the summary bit. */
2937#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2938/** Mask of exceptions flags, including the summary bit. */
2939#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2940/** Condition code 0. */
2941#define X86_FSW_C0 RT_BIT_32(8)
2942/** Condition code 1. */
2943#define X86_FSW_C1 RT_BIT_32(9)
2944/** Condition code 2. */
2945#define X86_FSW_C2 RT_BIT_32(10)
2946/** Top of the stack mask. */
2947#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2948/** TOP shift value. */
2949#define X86_FSW_TOP_SHIFT 11
2950/** Mask for getting TOP value after shifting it right. */
2951#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2952/** Get the TOP value. */
2953#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2954/** Condition code 3. */
2955#define X86_FSW_C3 RT_BIT_32(14)
2956/** Mask of exceptions flags, including the summary bit. */
2957#define X86_FSW_C_MASK UINT16_C(0x4700)
2958/** FPU busy. */
2959#define X86_FSW_B RT_BIT_32(15)
2960/** @} */
2961
2962
2963/** @name FPU control word flags.
2964 * @{ */
2965/** Exception Mask: Invalid operation. */
2966#define X86_FCW_IM RT_BIT_32(0)
2967/** Exception Mask: Denormalized operand. */
2968#define X86_FCW_DM RT_BIT_32(1)
2969/** Exception Mask: Zero divide. */
2970#define X86_FCW_ZM RT_BIT_32(2)
2971/** Exception Mask: Overflow. */
2972#define X86_FCW_OM RT_BIT_32(3)
2973/** Exception Mask: Underflow. */
2974#define X86_FCW_UM RT_BIT_32(4)
2975/** Exception Mask: Precision. */
2976#define X86_FCW_PM RT_BIT_32(5)
2977/** Mask all exceptions, the value typically loaded (by for instance fninit).
2978 * @remarks This includes reserved bit 6. */
2979#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2980/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2981#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2982/** Precision control mask. */
2983#define X86_FCW_PC_MASK UINT16_C(0x0300)
2984/** Precision control: 24-bit. */
2985#define X86_FCW_PC_24 UINT16_C(0x0000)
2986/** Precision control: Reserved. */
2987#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2988/** Precision control: 53-bit. */
2989#define X86_FCW_PC_53 UINT16_C(0x0200)
2990/** Precision control: 64-bit. */
2991#define X86_FCW_PC_64 UINT16_C(0x0300)
2992/** Rounding control mask. */
2993#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2994/** Rounding control: To nearest. */
2995#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2996/** Rounding control: Down. */
2997#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2998/** Rounding control: Up. */
2999#define X86_FCW_RC_UP UINT16_C(0x0800)
3000/** Rounding control: Towards zero. */
3001#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3002/** Bits which should be zero, apparently. */
3003#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3004/** @} */
3005
3006/** @name SSE MXCSR
3007 * @{ */
3008/** Exception Flag: Invalid operation. */
3009#define X86_MXCSR_IE RT_BIT_32(0)
3010/** Exception Flag: Denormalized operand. */
3011#define X86_MXCSR_DE RT_BIT_32(1)
3012/** Exception Flag: Zero divide. */
3013#define X86_MXCSR_ZE RT_BIT_32(2)
3014/** Exception Flag: Overflow. */
3015#define X86_MXCSR_OE RT_BIT_32(3)
3016/** Exception Flag: Underflow. */
3017#define X86_MXCSR_UE RT_BIT_32(4)
3018/** Exception Flag: Precision. */
3019#define X86_MXCSR_PE RT_BIT_32(5)
3020
3021/** Denormals are zero. */
3022#define X86_MXCSR_DAZ RT_BIT_32(6)
3023
3024/** Exception Mask: Invalid operation. */
3025#define X86_MXCSR_IM RT_BIT_32(7)
3026/** Exception Mask: Denormalized operand. */
3027#define X86_MXCSR_DM RT_BIT_32(8)
3028/** Exception Mask: Zero divide. */
3029#define X86_MXCSR_ZM RT_BIT_32(9)
3030/** Exception Mask: Overflow. */
3031#define X86_MXCSR_OM RT_BIT_32(10)
3032/** Exception Mask: Underflow. */
3033#define X86_MXCSR_UM RT_BIT_32(11)
3034/** Exception Mask: Precision. */
3035#define X86_MXCSR_PM RT_BIT_32(12)
3036
3037/** Rounding control mask. */
3038#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3039/** Rounding control: To nearest. */
3040#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3041/** Rounding control: Down. */
3042#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3043/** Rounding control: Up. */
3044#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3045/** Rounding control: Towards zero. */
3046#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3047
3048/** Flush-to-zero for masked underflow. */
3049#define X86_MXCSR_FZ RT_BIT_32(15)
3050
3051/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3052#define X86_MXCSR_MM RT_BIT_32(17)
3053/** @} */
3054
3055/**
3056 * XSAVE header.
3057 */
3058typedef struct X86XSAVEHDR
3059{
3060 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3061 uint64_t bmXState;
3062 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3063 uint64_t bmXComp;
3064 /** Reserved for furture extensions, probably MBZ. */
3065 uint64_t au64Reserved[6];
3066} X86XSAVEHDR;
3067#ifndef VBOX_FOR_DTRACE_LIB
3068AssertCompileSize(X86XSAVEHDR, 64);
3069#endif
3070/** Pointer to an XSAVE header. */
3071typedef X86XSAVEHDR *PX86XSAVEHDR;
3072/** Pointer to a const XSAVE header. */
3073typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3074
3075
3076/**
3077 * The high 128-bit YMM register state (XSAVE_C_YMM).
3078 * (The lower 128-bits being in X86FXSTATE.)
3079 */
3080typedef struct X86XSAVEYMMHI
3081{
3082 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3083 X86XMMREG aYmmHi[16];
3084} X86XSAVEYMMHI;
3085#ifndef VBOX_FOR_DTRACE_LIB
3086AssertCompileSize(X86XSAVEYMMHI, 256);
3087#endif
3088/** Pointer to a high 128-bit YMM register state. */
3089typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3090/** Pointer to a const high 128-bit YMM register state. */
3091typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3092
3093/**
3094 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3095 */
3096typedef struct X86XSAVEBNDREGS
3097{
3098 /** Array of registers (BND0...BND3). */
3099 struct
3100 {
3101 /** Lower bound. */
3102 uint64_t uLowerBound;
3103 /** Upper bound. */
3104 uint64_t uUpperBound;
3105 } aRegs[4];
3106} X86XSAVEBNDREGS;
3107#ifndef VBOX_FOR_DTRACE_LIB
3108AssertCompileSize(X86XSAVEBNDREGS, 64);
3109#endif
3110/** Pointer to a MPX bound register state. */
3111typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3112/** Pointer to a const MPX bound register state. */
3113typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3114
3115/**
3116 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3117 */
3118typedef struct X86XSAVEBNDCFG
3119{
3120 uint64_t fConfig;
3121 uint64_t fStatus;
3122} X86XSAVEBNDCFG;
3123#ifndef VBOX_FOR_DTRACE_LIB
3124AssertCompileSize(X86XSAVEBNDCFG, 16);
3125#endif
3126/** Pointer to a MPX bound config and status register state. */
3127typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3128/** Pointer to a const MPX bound config and status register state. */
3129typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3130
3131/**
3132 * AVX-512 opmask state (XSAVE_C_OPMASK).
3133 */
3134typedef struct X86XSAVEOPMASK
3135{
3136 /** The K0..K7 values. */
3137 uint64_t aKRegs[8];
3138} X86XSAVEOPMASK;
3139#ifndef VBOX_FOR_DTRACE_LIB
3140AssertCompileSize(X86XSAVEOPMASK, 64);
3141#endif
3142/** Pointer to a AVX-512 opmask state. */
3143typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3144/** Pointer to a const AVX-512 opmask state. */
3145typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3146
3147/**
3148 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3149 */
3150typedef struct X86XSAVEZMMHI256
3151{
3152 /** Upper 256-bits of ZMM0-15. */
3153 X86YMMREG aHi256Regs[16];
3154} X86XSAVEZMMHI256;
3155#ifndef VBOX_FOR_DTRACE_LIB
3156AssertCompileSize(X86XSAVEZMMHI256, 512);
3157#endif
3158/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3159typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3160/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3161typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3162
3163/**
3164 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3165 */
3166typedef struct X86XSAVEZMM16HI
3167{
3168 /** ZMM16 thru ZMM31. */
3169 X86ZMMREG aRegs[16];
3170} X86XSAVEZMM16HI;
3171#ifndef VBOX_FOR_DTRACE_LIB
3172AssertCompileSize(X86XSAVEZMM16HI, 1024);
3173#endif
3174/** Pointer to a state comprising ZMM16-32. */
3175typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3176/** Pointer to a const state comprising ZMM16-32. */
3177typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3178
3179/**
3180 * AMD Light weight profiling state (XSAVE_C_LWP).
3181 *
3182 * We probably won't play with this as AMD seems to be dropping from their "zen"
3183 * processor micro architecture.
3184 */
3185typedef struct X86XSAVELWP
3186{
3187 /** Details when needed. */
3188 uint64_t auLater[128/8];
3189} X86XSAVELWP;
3190#ifndef VBOX_FOR_DTRACE_LIB
3191AssertCompileSize(X86XSAVELWP, 128);
3192#endif
3193
3194
3195/**
3196 * x86 FPU/SSE/AVX/XXXX state.
3197 *
3198 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3199 * changes to this structure.
3200 */
3201typedef struct X86XSAVEAREA
3202{
3203 /** The x87 and SSE region (or legacy region if you like). */
3204 X86FXSTATE x87;
3205 /** The XSAVE header. */
3206 X86XSAVEHDR Hdr;
3207 /** Beyond the header, there isn't really a fixed layout, but we can
3208 generally assume the YMM (AVX) register extensions are present and
3209 follows immediately. */
3210 union
3211 {
3212 /** The high 128-bit AVX registers for easy access by IEM.
3213 * @note This ASSUMES they will always be here... */
3214 X86XSAVEYMMHI YmmHi;
3215
3216 /** This is a typical layout on intel CPUs (good for debuggers). */
3217 struct
3218 {
3219 X86XSAVEYMMHI YmmHi;
3220 X86XSAVEBNDREGS BndRegs;
3221 X86XSAVEBNDCFG BndCfg;
3222 uint8_t abFudgeToMatchDocs[0xB0];
3223 X86XSAVEOPMASK Opmask;
3224 X86XSAVEZMMHI256 ZmmHi256;
3225 X86XSAVEZMM16HI Zmm16Hi;
3226 } Intel;
3227
3228 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3229 struct
3230 {
3231 X86XSAVEYMMHI YmmHi;
3232 X86XSAVELWP Lwp;
3233 } AmdBd;
3234
3235 /** To enbling static deployments that have a reasonable chance of working for
3236 * the next 3-6 CPU generations without running short on space, we allocate a
3237 * lot of extra space here, making the structure a round 8KB in size. This
3238 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3239 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3240 uint8_t ab[8192 - 512 - 64];
3241 } u;
3242} X86XSAVEAREA;
3243#ifndef VBOX_FOR_DTRACE_LIB
3244AssertCompileSize(X86XSAVEAREA, 8192);
3245AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3246AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3247AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3248AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3249AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3250AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3251AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3252AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3253#endif
3254/** Pointer to a XSAVE area. */
3255typedef X86XSAVEAREA *PX86XSAVEAREA;
3256/** Pointer to a const XSAVE area. */
3257typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3258
3259
3260/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3261 * @{ */
3262/** Bit 0 - x87 - Legacy FPU state (bit number) */
3263#define XSAVE_C_X87_BIT 0
3264/** Bit 0 - x87 - Legacy FPU state. */
3265#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3266/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3267#define XSAVE_C_SSE_BIT 1
3268/** Bit 1 - SSE - 128-bit SSE state. */
3269#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3270/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3271#define XSAVE_C_YMM_BIT 2
3272/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3273#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3274/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3275#define XSAVE_C_BNDREGS_BIT 3
3276/** Bit 3 - BNDREGS - MPX bound register state. */
3277#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3278/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3279#define XSAVE_C_BNDCSR_BIT 4
3280/** Bit 4 - BNDCSR - MPX bound config and status state. */
3281#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3282/** Bit 5 - Opmask - opmask state (bit number). */
3283#define XSAVE_C_OPMASK_BIT 5
3284/** Bit 5 - Opmask - opmask state. */
3285#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3286/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3287#define XSAVE_C_ZMM_HI256_BIT 6
3288/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3289#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3290/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3291#define XSAVE_C_ZMM_16HI_BIT 7
3292/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3293#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3294/** Bit 9 - PKRU - Protection-key state (bit number). */
3295#define XSAVE_C_PKRU_BIT 9
3296/** Bit 9 - PKRU - Protection-key state. */
3297#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3298/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3299#define XSAVE_C_LWP_BIT 62
3300/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3301#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3302/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3303#define XSAVE_C_X_BIT 63
3304/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3305#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3306/** @} */
3307
3308
3309
3310/** @name Selector Descriptor
3311 * @{
3312 */
3313
3314#ifndef VBOX_FOR_DTRACE_LIB
3315/**
3316 * Descriptor attributes (as seen by VT-x).
3317 */
3318typedef struct X86DESCATTRBITS
3319{
3320 /** 00 - Segment Type. */
3321 unsigned u4Type : 4;
3322 /** 04 - Descriptor Type. System(=0) or code/data selector */
3323 unsigned u1DescType : 1;
3324 /** 05 - Descriptor Privilege level. */
3325 unsigned u2Dpl : 2;
3326 /** 07 - Flags selector present(=1) or not. */
3327 unsigned u1Present : 1;
3328 /** 08 - Segment limit 16-19. */
3329 unsigned u4LimitHigh : 4;
3330 /** 0c - Available for system software. */
3331 unsigned u1Available : 1;
3332 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3333 unsigned u1Long : 1;
3334 /** 0e - This flags meaning depends on the segment type. Try make sense out
3335 * of the intel manual yourself. */
3336 unsigned u1DefBig : 1;
3337 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3338 * clear byte. */
3339 unsigned u1Granularity : 1;
3340 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3341 unsigned u1Unusable : 1;
3342} X86DESCATTRBITS;
3343#endif /* !VBOX_FOR_DTRACE_LIB */
3344
3345/** @name X86DESCATTR masks
3346 * @{ */
3347#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3348#define X86DESCATTR_DT UINT32_C(0x00000010)
3349#define X86DESCATTR_DPL UINT32_C(0x00000060)
3350#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3351#define X86DESCATTR_P UINT32_C(0x00000080)
3352#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3353#define X86DESCATTR_AVL UINT32_C(0x00001000)
3354#define X86DESCATTR_L UINT32_C(0x00002000)
3355#define X86DESCATTR_D UINT32_C(0x00004000)
3356#define X86DESCATTR_G UINT32_C(0x00008000)
3357#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3358/** @} */
3359
3360#pragma pack(1)
3361typedef union X86DESCATTR
3362{
3363 /** Unsigned integer view. */
3364 uint32_t u;
3365#ifndef VBOX_FOR_DTRACE_LIB
3366 /** Normal view. */
3367 X86DESCATTRBITS n;
3368#endif
3369} X86DESCATTR;
3370#pragma pack()
3371/** Pointer to descriptor attributes. */
3372typedef X86DESCATTR *PX86DESCATTR;
3373/** Pointer to const descriptor attributes. */
3374typedef const X86DESCATTR *PCX86DESCATTR;
3375
3376#ifndef VBOX_FOR_DTRACE_LIB
3377
3378/**
3379 * Generic descriptor table entry
3380 */
3381#pragma pack(1)
3382typedef struct X86DESCGENERIC
3383{
3384 /** 00 - Limit - Low word. */
3385 unsigned u16LimitLow : 16;
3386 /** 10 - Base address - low word.
3387 * Don't try set this to 24 because MSC is doing stupid things then. */
3388 unsigned u16BaseLow : 16;
3389 /** 20 - Base address - first 8 bits of high word. */
3390 unsigned u8BaseHigh1 : 8;
3391 /** 28 - Segment Type. */
3392 unsigned u4Type : 4;
3393 /** 2c - Descriptor Type. System(=0) or code/data selector */
3394 unsigned u1DescType : 1;
3395 /** 2d - Descriptor Privilege level. */
3396 unsigned u2Dpl : 2;
3397 /** 2f - Flags selector present(=1) or not. */
3398 unsigned u1Present : 1;
3399 /** 30 - Segment limit 16-19. */
3400 unsigned u4LimitHigh : 4;
3401 /** 34 - Available for system software. */
3402 unsigned u1Available : 1;
3403 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3404 unsigned u1Long : 1;
3405 /** 36 - This flags meaning depends on the segment type. Try make sense out
3406 * of the intel manual yourself. */
3407 unsigned u1DefBig : 1;
3408 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3409 * clear byte. */
3410 unsigned u1Granularity : 1;
3411 /** 38 - Base address - highest 8 bits. */
3412 unsigned u8BaseHigh2 : 8;
3413} X86DESCGENERIC;
3414#pragma pack()
3415/** Pointer to a generic descriptor entry. */
3416typedef X86DESCGENERIC *PX86DESCGENERIC;
3417/** Pointer to a const generic descriptor entry. */
3418typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3419
3420/** @name Bit offsets of X86DESCGENERIC members.
3421 * @{*/
3422#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3423#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3424#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3425#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3426#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3427#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3428#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3429#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3430#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3431#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3432#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3433#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3434#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3435/** @} */
3436
3437
3438/** @name LAR mask
3439 * @{ */
3440#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3441#define X86LAR_F_DT UINT16_C( 0x1000)
3442#define X86LAR_F_DPL UINT16_C( 0x6000)
3443#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3444#define X86LAR_F_P UINT16_C( 0x8000)
3445#define X86LAR_F_AVL UINT32_C(0x00100000)
3446#define X86LAR_F_L UINT32_C(0x00200000)
3447#define X86LAR_F_D UINT32_C(0x00400000)
3448#define X86LAR_F_G UINT32_C(0x00800000)
3449/** @} */
3450
3451
3452/**
3453 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3454 */
3455typedef struct X86DESCGATE
3456{
3457 /** 00 - Target code segment offset - Low word.
3458 * Ignored if task-gate. */
3459 unsigned u16OffsetLow : 16;
3460 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3461 * TSS selector if task-gate. */
3462 unsigned u16Sel : 16;
3463 /** 20 - Number of parameters for a call-gate.
3464 * Ignored if interrupt-, trap- or task-gate. */
3465 unsigned u5ParmCount : 5;
3466 /** 25 - Reserved / ignored. */
3467 unsigned u3Reserved : 3;
3468 /** 28 - Segment Type. */
3469 unsigned u4Type : 4;
3470 /** 2c - Descriptor Type (0 = system). */
3471 unsigned u1DescType : 1;
3472 /** 2d - Descriptor Privilege level. */
3473 unsigned u2Dpl : 2;
3474 /** 2f - Flags selector present(=1) or not. */
3475 unsigned u1Present : 1;
3476 /** 30 - Target code segment offset - High word.
3477 * Ignored if task-gate. */
3478 unsigned u16OffsetHigh : 16;
3479} X86DESCGATE;
3480/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3481typedef X86DESCGATE *PX86DESCGATE;
3482/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3483typedef const X86DESCGATE *PCX86DESCGATE;
3484
3485#endif /* VBOX_FOR_DTRACE_LIB */
3486
3487/**
3488 * Descriptor table entry.
3489 */
3490#pragma pack(1)
3491typedef union X86DESC
3492{
3493#ifndef VBOX_FOR_DTRACE_LIB
3494 /** Generic descriptor view. */
3495 X86DESCGENERIC Gen;
3496 /** Gate descriptor view. */
3497 X86DESCGATE Gate;
3498#endif
3499
3500 /** 8 bit unsigned integer view. */
3501 uint8_t au8[8];
3502 /** 16 bit unsigned integer view. */
3503 uint16_t au16[4];
3504 /** 32 bit unsigned integer view. */
3505 uint32_t au32[2];
3506 /** 64 bit unsigned integer view. */
3507 uint64_t au64[1];
3508 /** Unsigned integer view. */
3509 uint64_t u;
3510} X86DESC;
3511#ifndef VBOX_FOR_DTRACE_LIB
3512AssertCompileSize(X86DESC, 8);
3513#endif
3514#pragma pack()
3515/** Pointer to descriptor table entry. */
3516typedef X86DESC *PX86DESC;
3517/** Pointer to const descriptor table entry. */
3518typedef const X86DESC *PCX86DESC;
3519
3520/** @def X86DESC_BASE
3521 * Return the base address of a descriptor.
3522 */
3523#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3524 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3525 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3526 | ( (a_pDesc)->Gen.u16BaseLow ) )
3527
3528/** @def X86DESC_LIMIT
3529 * Return the limit of a descriptor.
3530 */
3531#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3532 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3533 | ( (a_pDesc)->Gen.u16LimitLow ) )
3534
3535/** @def X86DESC_LIMIT_G
3536 * Return the limit of a descriptor with the granularity bit taken into account.
3537 * @returns Selector limit (uint32_t).
3538 * @param a_pDesc Pointer to the descriptor.
3539 */
3540#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3541 ( (a_pDesc)->Gen.u1Granularity \
3542 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3543 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3544 )
3545
3546/** @def X86DESC_GET_HID_ATTR
3547 * Get the descriptor attributes for the hidden register.
3548 */
3549#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3550 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3551
3552#ifndef VBOX_FOR_DTRACE_LIB
3553
3554/**
3555 * 64 bits generic descriptor table entry
3556 * Note: most of these bits have no meaning in long mode.
3557 */
3558#pragma pack(1)
3559typedef struct X86DESC64GENERIC
3560{
3561 /** Limit - Low word - *IGNORED*. */
3562 uint32_t u16LimitLow : 16;
3563 /** Base address - low word. - *IGNORED*
3564 * Don't try set this to 24 because MSC is doing stupid things then. */
3565 uint32_t u16BaseLow : 16;
3566 /** Base address - first 8 bits of high word. - *IGNORED* */
3567 uint32_t u8BaseHigh1 : 8;
3568 /** Segment Type. */
3569 uint32_t u4Type : 4;
3570 /** Descriptor Type. System(=0) or code/data selector */
3571 uint32_t u1DescType : 1;
3572 /** Descriptor Privilege level. */
3573 uint32_t u2Dpl : 2;
3574 /** Flags selector present(=1) or not. */
3575 uint32_t u1Present : 1;
3576 /** Segment limit 16-19. - *IGNORED* */
3577 uint32_t u4LimitHigh : 4;
3578 /** Available for system software. - *IGNORED* */
3579 uint32_t u1Available : 1;
3580 /** Long mode flag. */
3581 uint32_t u1Long : 1;
3582 /** This flags meaning depends on the segment type. Try make sense out
3583 * of the intel manual yourself. */
3584 uint32_t u1DefBig : 1;
3585 /** Granularity of the limit. If set 4KB granularity is used, if
3586 * clear byte. - *IGNORED* */
3587 uint32_t u1Granularity : 1;
3588 /** Base address - highest 8 bits. - *IGNORED* */
3589 uint32_t u8BaseHigh2 : 8;
3590 /** Base address - bits 63-32. */
3591 uint32_t u32BaseHigh3 : 32;
3592 uint32_t u8Reserved : 8;
3593 uint32_t u5Zeros : 5;
3594 uint32_t u19Reserved : 19;
3595} X86DESC64GENERIC;
3596#pragma pack()
3597/** Pointer to a generic descriptor entry. */
3598typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3599/** Pointer to a const generic descriptor entry. */
3600typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3601
3602/**
3603 * System descriptor table entry (64 bits)
3604 *
3605 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3606 */
3607#pragma pack(1)
3608typedef struct X86DESC64SYSTEM
3609{
3610 /** Limit - Low word. */
3611 uint32_t u16LimitLow : 16;
3612 /** Base address - low word.
3613 * Don't try set this to 24 because MSC is doing stupid things then. */
3614 uint32_t u16BaseLow : 16;
3615 /** Base address - first 8 bits of high word. */
3616 uint32_t u8BaseHigh1 : 8;
3617 /** Segment Type. */
3618 uint32_t u4Type : 4;
3619 /** Descriptor Type. System(=0) or code/data selector */
3620 uint32_t u1DescType : 1;
3621 /** Descriptor Privilege level. */
3622 uint32_t u2Dpl : 2;
3623 /** Flags selector present(=1) or not. */
3624 uint32_t u1Present : 1;
3625 /** Segment limit 16-19. */
3626 uint32_t u4LimitHigh : 4;
3627 /** Available for system software. */
3628 uint32_t u1Available : 1;
3629 /** Reserved - 0. */
3630 uint32_t u1Reserved : 1;
3631 /** This flags meaning depends on the segment type. Try make sense out
3632 * of the intel manual yourself. */
3633 uint32_t u1DefBig : 1;
3634 /** Granularity of the limit. If set 4KB granularity is used, if
3635 * clear byte. */
3636 uint32_t u1Granularity : 1;
3637 /** Base address - bits 31-24. */
3638 uint32_t u8BaseHigh2 : 8;
3639 /** Base address - bits 63-32. */
3640 uint32_t u32BaseHigh3 : 32;
3641 uint32_t u8Reserved : 8;
3642 uint32_t u5Zeros : 5;
3643 uint32_t u19Reserved : 19;
3644} X86DESC64SYSTEM;
3645#pragma pack()
3646/** Pointer to a system descriptor entry. */
3647typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3648/** Pointer to a const system descriptor entry. */
3649typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3650
3651/**
3652 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3653 */
3654typedef struct X86DESC64GATE
3655{
3656 /** Target code segment offset - Low word. */
3657 uint32_t u16OffsetLow : 16;
3658 /** Target code segment selector. */
3659 uint32_t u16Sel : 16;
3660 /** Interrupt stack table for interrupt- and trap-gates.
3661 * Ignored by call-gates. */
3662 uint32_t u3IST : 3;
3663 /** Reserved / ignored. */
3664 uint32_t u5Reserved : 5;
3665 /** Segment Type. */
3666 uint32_t u4Type : 4;
3667 /** Descriptor Type (0 = system). */
3668 uint32_t u1DescType : 1;
3669 /** Descriptor Privilege level. */
3670 uint32_t u2Dpl : 2;
3671 /** Flags selector present(=1) or not. */
3672 uint32_t u1Present : 1;
3673 /** Target code segment offset - High word.
3674 * Ignored if task-gate. */
3675 uint32_t u16OffsetHigh : 16;
3676 /** Target code segment offset - Top dword.
3677 * Ignored if task-gate. */
3678 uint32_t u32OffsetTop : 32;
3679 /** Reserved / ignored / must be zero.
3680 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3681 uint32_t u32Reserved : 32;
3682} X86DESC64GATE;
3683AssertCompileSize(X86DESC64GATE, 16);
3684/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3685typedef X86DESC64GATE *PX86DESC64GATE;
3686/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3687typedef const X86DESC64GATE *PCX86DESC64GATE;
3688
3689#endif /* VBOX_FOR_DTRACE_LIB */
3690
3691/**
3692 * Descriptor table entry.
3693 */
3694#pragma pack(1)
3695typedef union X86DESC64
3696{
3697#ifndef VBOX_FOR_DTRACE_LIB
3698 /** Generic descriptor view. */
3699 X86DESC64GENERIC Gen;
3700 /** System descriptor view. */
3701 X86DESC64SYSTEM System;
3702 /** Gate descriptor view. */
3703 X86DESC64GATE Gate;
3704#endif
3705
3706 /** 8 bit unsigned integer view. */
3707 uint8_t au8[16];
3708 /** 16 bit unsigned integer view. */
3709 uint16_t au16[8];
3710 /** 32 bit unsigned integer view. */
3711 uint32_t au32[4];
3712 /** 64 bit unsigned integer view. */
3713 uint64_t au64[2];
3714} X86DESC64;
3715#ifndef VBOX_FOR_DTRACE_LIB
3716AssertCompileSize(X86DESC64, 16);
3717#endif
3718#pragma pack()
3719/** Pointer to descriptor table entry. */
3720typedef X86DESC64 *PX86DESC64;
3721/** Pointer to const descriptor table entry. */
3722typedef const X86DESC64 *PCX86DESC64;
3723
3724/** @def X86DESC64_BASE
3725 * Return the base of a 64-bit descriptor.
3726 */
3727#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3728 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3729 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3730 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3731 | ( (a_pDesc)->Gen.u16BaseLow ) )
3732
3733
3734
3735/** @name Host system descriptor table entry - Use with care!
3736 * @{ */
3737/** Host system descriptor table entry. */
3738#if HC_ARCH_BITS == 64
3739typedef X86DESC64 X86DESCHC;
3740#else
3741typedef X86DESC X86DESCHC;
3742#endif
3743/** Pointer to a host system descriptor table entry. */
3744#if HC_ARCH_BITS == 64
3745typedef PX86DESC64 PX86DESCHC;
3746#else
3747typedef PX86DESC PX86DESCHC;
3748#endif
3749/** Pointer to a const host system descriptor table entry. */
3750#if HC_ARCH_BITS == 64
3751typedef PCX86DESC64 PCX86DESCHC;
3752#else
3753typedef PCX86DESC PCX86DESCHC;
3754#endif
3755/** @} */
3756
3757
3758/** @name Selector Descriptor Types.
3759 * @{
3760 */
3761
3762/** @name Non-System Selector Types.
3763 * @{ */
3764/** Code(=set)/Data(=clear) bit. */
3765#define X86_SEL_TYPE_CODE 8
3766/** Memory(=set)/System(=clear) bit. */
3767#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3768/** Accessed bit. */
3769#define X86_SEL_TYPE_ACCESSED 1
3770/** Expand down bit (for data selectors only). */
3771#define X86_SEL_TYPE_DOWN 4
3772/** Conforming bit (for code selectors only). */
3773#define X86_SEL_TYPE_CONF 4
3774/** Write bit (for data selectors only). */
3775#define X86_SEL_TYPE_WRITE 2
3776/** Read bit (for code selectors only). */
3777#define X86_SEL_TYPE_READ 2
3778/** The bit number of the code segment read bit (relative to u4Type). */
3779#define X86_SEL_TYPE_READ_BIT 1
3780
3781/** Read only selector type. */
3782#define X86_SEL_TYPE_RO 0
3783/** Accessed read only selector type. */
3784#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3785/** Read write selector type. */
3786#define X86_SEL_TYPE_RW 2
3787/** Accessed read write selector type. */
3788#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3789/** Expand down read only selector type. */
3790#define X86_SEL_TYPE_RO_DOWN 4
3791/** Accessed expand down read only selector type. */
3792#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3793/** Expand down read write selector type. */
3794#define X86_SEL_TYPE_RW_DOWN 6
3795/** Accessed expand down read write selector type. */
3796#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3797/** Execute only selector type. */
3798#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3799/** Accessed execute only selector type. */
3800#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3801/** Execute and read selector type. */
3802#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3803/** Accessed execute and read selector type. */
3804#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3805/** Conforming execute only selector type. */
3806#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3807/** Accessed Conforming execute only selector type. */
3808#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3809/** Conforming execute and write selector type. */
3810#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3811/** Accessed Conforming execute and write selector type. */
3812#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3813/** @} */
3814
3815
3816/** @name System Selector Types.
3817 * @{ */
3818/** The TSS busy bit mask. */
3819#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3820
3821/** Undefined system selector type. */
3822#define X86_SEL_TYPE_SYS_UNDEFINED 0
3823/** 286 TSS selector. */
3824#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3825/** LDT selector. */
3826#define X86_SEL_TYPE_SYS_LDT 2
3827/** 286 TSS selector - Busy. */
3828#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3829/** 286 Callgate selector. */
3830#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3831/** Taskgate selector. */
3832#define X86_SEL_TYPE_SYS_TASK_GATE 5
3833/** 286 Interrupt gate selector. */
3834#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3835/** 286 Trapgate selector. */
3836#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3837/** Undefined system selector. */
3838#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3839/** 386 TSS selector. */
3840#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3841/** Undefined system selector. */
3842#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3843/** 386 TSS selector - Busy. */
3844#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3845/** 386 Callgate selector. */
3846#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3847/** Undefined system selector. */
3848#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3849/** 386 Interruptgate selector. */
3850#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3851/** 386 Trapgate selector. */
3852#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3853/** @} */
3854
3855/** @name AMD64 System Selector Types.
3856 * @{ */
3857/** LDT selector. */
3858#define AMD64_SEL_TYPE_SYS_LDT 2
3859/** TSS selector - Busy. */
3860#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3861/** TSS selector - Busy. */
3862#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3863/** Callgate selector. */
3864#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3865/** Interruptgate selector. */
3866#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3867/** Trapgate selector. */
3868#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3869/** @} */
3870
3871/** @} */
3872
3873
3874/** @name Descriptor Table Entry Flag Masks.
3875 * These are for the 2nd 32-bit word of a descriptor.
3876 * @{ */
3877/** Bits 8-11 - TYPE - Descriptor type mask. */
3878#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3879/** Bit 12 - S - System (=0) or Code/Data (=1). */
3880#define X86_DESC_S RT_BIT_32(12)
3881/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3882#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
3883/** Bit 15 - P - Present. */
3884#define X86_DESC_P RT_BIT_32(15)
3885/** Bit 20 - AVL - Available for system software. */
3886#define X86_DESC_AVL RT_BIT_32(20)
3887/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3888#define X86_DESC_DB RT_BIT_32(22)
3889/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3890 * used, if clear byte. */
3891#define X86_DESC_G RT_BIT_32(23)
3892/** @} */
3893
3894/** @} */
3895
3896
3897/** @name Task Segments.
3898 * @{
3899 */
3900
3901/**
3902 * The minimum TSS descriptor limit for 286 tasks.
3903 */
3904#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3905
3906/**
3907 * The minimum TSS descriptor segment limit for 386 tasks.
3908 */
3909#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3910
3911/**
3912 * 16-bit Task Segment (TSS).
3913 */
3914#pragma pack(1)
3915typedef struct X86TSS16
3916{
3917 /** Back link to previous task. (static) */
3918 RTSEL selPrev;
3919 /** Ring-0 stack pointer. (static) */
3920 uint16_t sp0;
3921 /** Ring-0 stack segment. (static) */
3922 RTSEL ss0;
3923 /** Ring-1 stack pointer. (static) */
3924 uint16_t sp1;
3925 /** Ring-1 stack segment. (static) */
3926 RTSEL ss1;
3927 /** Ring-2 stack pointer. (static) */
3928 uint16_t sp2;
3929 /** Ring-2 stack segment. (static) */
3930 RTSEL ss2;
3931 /** IP before task switch. */
3932 uint16_t ip;
3933 /** FLAGS before task switch. */
3934 uint16_t flags;
3935 /** AX before task switch. */
3936 uint16_t ax;
3937 /** CX before task switch. */
3938 uint16_t cx;
3939 /** DX before task switch. */
3940 uint16_t dx;
3941 /** BX before task switch. */
3942 uint16_t bx;
3943 /** SP before task switch. */
3944 uint16_t sp;
3945 /** BP before task switch. */
3946 uint16_t bp;
3947 /** SI before task switch. */
3948 uint16_t si;
3949 /** DI before task switch. */
3950 uint16_t di;
3951 /** ES before task switch. */
3952 RTSEL es;
3953 /** CS before task switch. */
3954 RTSEL cs;
3955 /** SS before task switch. */
3956 RTSEL ss;
3957 /** DS before task switch. */
3958 RTSEL ds;
3959 /** LDTR before task switch. */
3960 RTSEL selLdt;
3961} X86TSS16;
3962#ifndef VBOX_FOR_DTRACE_LIB
3963AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3964#endif
3965#pragma pack()
3966/** Pointer to a 16-bit task segment. */
3967typedef X86TSS16 *PX86TSS16;
3968/** Pointer to a const 16-bit task segment. */
3969typedef const X86TSS16 *PCX86TSS16;
3970
3971
3972/**
3973 * 32-bit Task Segment (TSS).
3974 */
3975#pragma pack(1)
3976typedef struct X86TSS32
3977{
3978 /** Back link to previous task. (static) */
3979 RTSEL selPrev;
3980 uint16_t padding1;
3981 /** Ring-0 stack pointer. (static) */
3982 uint32_t esp0;
3983 /** Ring-0 stack segment. (static) */
3984 RTSEL ss0;
3985 uint16_t padding_ss0;
3986 /** Ring-1 stack pointer. (static) */
3987 uint32_t esp1;
3988 /** Ring-1 stack segment. (static) */
3989 RTSEL ss1;
3990 uint16_t padding_ss1;
3991 /** Ring-2 stack pointer. (static) */
3992 uint32_t esp2;
3993 /** Ring-2 stack segment. (static) */
3994 RTSEL ss2;
3995 uint16_t padding_ss2;
3996 /** Page directory for the task. (static) */
3997 uint32_t cr3;
3998 /** EIP before task switch. */
3999 uint32_t eip;
4000 /** EFLAGS before task switch. */
4001 uint32_t eflags;
4002 /** EAX before task switch. */
4003 uint32_t eax;
4004 /** ECX before task switch. */
4005 uint32_t ecx;
4006 /** EDX before task switch. */
4007 uint32_t edx;
4008 /** EBX before task switch. */
4009 uint32_t ebx;
4010 /** ESP before task switch. */
4011 uint32_t esp;
4012 /** EBP before task switch. */
4013 uint32_t ebp;
4014 /** ESI before task switch. */
4015 uint32_t esi;
4016 /** EDI before task switch. */
4017 uint32_t edi;
4018 /** ES before task switch. */
4019 RTSEL es;
4020 uint16_t padding_es;
4021 /** CS before task switch. */
4022 RTSEL cs;
4023 uint16_t padding_cs;
4024 /** SS before task switch. */
4025 RTSEL ss;
4026 uint16_t padding_ss;
4027 /** DS before task switch. */
4028 RTSEL ds;
4029 uint16_t padding_ds;
4030 /** FS before task switch. */
4031 RTSEL fs;
4032 uint16_t padding_fs;
4033 /** GS before task switch. */
4034 RTSEL gs;
4035 uint16_t padding_gs;
4036 /** LDTR before task switch. */
4037 RTSEL selLdt;
4038 uint16_t padding_ldt;
4039 /** Debug trap flag */
4040 uint16_t fDebugTrap;
4041 /** Offset relative to the TSS of the start of the I/O Bitmap
4042 * and the end of the interrupt redirection bitmap. */
4043 uint16_t offIoBitmap;
4044} X86TSS32;
4045#pragma pack()
4046/** Pointer to task segment. */
4047typedef X86TSS32 *PX86TSS32;
4048/** Pointer to const task segment. */
4049typedef const X86TSS32 *PCX86TSS32;
4050#ifndef VBOX_FOR_DTRACE_LIB
4051AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4052AssertCompileMemberOffset(X86TSS32, cr3, 28);
4053AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4054#endif
4055
4056/**
4057 * 64-bit Task segment.
4058 */
4059#pragma pack(1)
4060typedef struct X86TSS64
4061{
4062 /** Reserved. */
4063 uint32_t u32Reserved;
4064 /** Ring-0 stack pointer. (static) */
4065 uint64_t rsp0;
4066 /** Ring-1 stack pointer. (static) */
4067 uint64_t rsp1;
4068 /** Ring-2 stack pointer. (static) */
4069 uint64_t rsp2;
4070 /** Reserved. */
4071 uint32_t u32Reserved2[2];
4072 /* IST */
4073 uint64_t ist1;
4074 uint64_t ist2;
4075 uint64_t ist3;
4076 uint64_t ist4;
4077 uint64_t ist5;
4078 uint64_t ist6;
4079 uint64_t ist7;
4080 /* Reserved. */
4081 uint16_t u16Reserved[5];
4082 /** Offset relative to the TSS of the start of the I/O Bitmap
4083 * and the end of the interrupt redirection bitmap. */
4084 uint16_t offIoBitmap;
4085} X86TSS64;
4086#pragma pack()
4087/** Pointer to a 64-bit task segment. */
4088typedef X86TSS64 *PX86TSS64;
4089/** Pointer to a const 64-bit task segment. */
4090typedef const X86TSS64 *PCX86TSS64;
4091#ifndef VBOX_FOR_DTRACE_LIB
4092AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4093#endif
4094
4095/** @} */
4096
4097
4098/** @name Selectors.
4099 * @{
4100 */
4101
4102/**
4103 * The shift used to convert a selector from and to index an index (C).
4104 */
4105#define X86_SEL_SHIFT 3
4106
4107/**
4108 * The mask used to mask off the table indicator and RPL of an selector.
4109 */
4110#define X86_SEL_MASK 0xfff8U
4111
4112/**
4113 * The mask used to mask off the RPL of an selector.
4114 * This is suitable for checking for NULL selectors.
4115 */
4116#define X86_SEL_MASK_OFF_RPL 0xfffcU
4117
4118/**
4119 * The bit indicating that a selector is in the LDT and not in the GDT.
4120 */
4121#define X86_SEL_LDT 0x0004U
4122
4123/**
4124 * The bit mask for getting the RPL of a selector.
4125 */
4126#define X86_SEL_RPL 0x0003U
4127
4128/**
4129 * The mask covering both RPL and LDT.
4130 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4131 * checks.
4132 */
4133#define X86_SEL_RPL_LDT 0x0007U
4134
4135/** @} */
4136
4137
4138/**
4139 * x86 Exceptions/Faults/Traps.
4140 */
4141typedef enum X86XCPT
4142{
4143 /** \#DE - Divide error. */
4144 X86_XCPT_DE = 0x00,
4145 /** \#DB - Debug event (single step, DRx, ..) */
4146 X86_XCPT_DB = 0x01,
4147 /** NMI - Non-Maskable Interrupt */
4148 X86_XCPT_NMI = 0x02,
4149 /** \#BP - Breakpoint (INT3). */
4150 X86_XCPT_BP = 0x03,
4151 /** \#OF - Overflow (INTO). */
4152 X86_XCPT_OF = 0x04,
4153 /** \#BR - Bound range exceeded (BOUND). */
4154 X86_XCPT_BR = 0x05,
4155 /** \#UD - Undefined opcode. */
4156 X86_XCPT_UD = 0x06,
4157 /** \#NM - Device not available (math coprocessor device). */
4158 X86_XCPT_NM = 0x07,
4159 /** \#DF - Double fault. */
4160 X86_XCPT_DF = 0x08,
4161 /** ??? - Coprocessor segment overrun (obsolete). */
4162 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4163 /** \#TS - Taskswitch (TSS). */
4164 X86_XCPT_TS = 0x0a,
4165 /** \#NP - Segment no present. */
4166 X86_XCPT_NP = 0x0b,
4167 /** \#SS - Stack segment fault. */
4168 X86_XCPT_SS = 0x0c,
4169 /** \#GP - General protection fault. */
4170 X86_XCPT_GP = 0x0d,
4171 /** \#PF - Page fault. */
4172 X86_XCPT_PF = 0x0e,
4173 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4174 /** \#MF - Math fault (FPU). */
4175 X86_XCPT_MF = 0x10,
4176 /** \#AC - Alignment check. */
4177 X86_XCPT_AC = 0x11,
4178 /** \#MC - Machine check. */
4179 X86_XCPT_MC = 0x12,
4180 /** \#XF - SIMD Floating-Pointer Exception. */
4181 X86_XCPT_XF = 0x13,
4182 /** \#VE - Virtualization Exception. */
4183 X86_XCPT_VE = 0x14,
4184 /** \#SX - Security Exception. */
4185 X86_XCPT_SX = 0x1e
4186} X86XCPT;
4187/** Pointer to a x86 exception code. */
4188typedef X86XCPT *PX86XCPT;
4189/** Pointer to a const x86 exception code. */
4190typedef const X86XCPT *PCX86XCPT;
4191/** The last valid (currently reserved) exception value. */
4192#define X86_XCPT_LAST 0x1f
4193
4194
4195/** @name Trap Error Codes
4196 * @{
4197 */
4198/** External indicator. */
4199#define X86_TRAP_ERR_EXTERNAL 1
4200/** IDT indicator. */
4201#define X86_TRAP_ERR_IDT 2
4202/** Descriptor table indicator - If set LDT, if clear GDT. */
4203#define X86_TRAP_ERR_TI 4
4204/** Mask for getting the selector. */
4205#define X86_TRAP_ERR_SEL_MASK 0xfff8
4206/** Shift for getting the selector table index (C type index). */
4207#define X86_TRAP_ERR_SEL_SHIFT 3
4208/** @} */
4209
4210
4211/** @name \#PF Trap Error Codes
4212 * @{
4213 */
4214/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4215#define X86_TRAP_PF_P RT_BIT_32(0)
4216/** Bit 1 - R/W - Read (clear) or write (set) access. */
4217#define X86_TRAP_PF_RW RT_BIT_32(1)
4218/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4219#define X86_TRAP_PF_US RT_BIT_32(2)
4220/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4221#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4222/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4223#define X86_TRAP_PF_ID RT_BIT_32(4)
4224/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4225#define X86_TRAP_PF_PK RT_BIT_32(5)
4226/** @} */
4227
4228#pragma pack(1)
4229/**
4230 * 16-bit IDTR.
4231 */
4232typedef struct X86IDTR16
4233{
4234 /** Offset. */
4235 uint16_t offSel;
4236 /** Selector. */
4237 uint16_t uSel;
4238} X86IDTR16, *PX86IDTR16;
4239#pragma pack()
4240
4241#pragma pack(1)
4242/**
4243 * 32-bit IDTR/GDTR.
4244 */
4245typedef struct X86XDTR32
4246{
4247 /** Size of the descriptor table. */
4248 uint16_t cb;
4249 /** Address of the descriptor table. */
4250#ifndef VBOX_FOR_DTRACE_LIB
4251 uint32_t uAddr;
4252#else
4253 uint16_t au16Addr[2];
4254#endif
4255} X86XDTR32, *PX86XDTR32;
4256#pragma pack()
4257
4258#pragma pack(1)
4259/**
4260 * 64-bit IDTR/GDTR.
4261 */
4262typedef struct X86XDTR64
4263{
4264 /** Size of the descriptor table. */
4265 uint16_t cb;
4266 /** Address of the descriptor table. */
4267#ifndef VBOX_FOR_DTRACE_LIB
4268 uint64_t uAddr;
4269#else
4270 uint16_t au16Addr[4];
4271#endif
4272} X86XDTR64, *PX86XDTR64;
4273#pragma pack()
4274
4275
4276/** @name ModR/M
4277 * @{ */
4278#define X86_MODRM_RM_MASK UINT8_C(0x07)
4279#define X86_MODRM_REG_MASK UINT8_C(0x38)
4280#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4281#define X86_MODRM_REG_SHIFT 3
4282#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4283#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4284#define X86_MODRM_MOD_SHIFT 6
4285#ifndef VBOX_FOR_DTRACE_LIB
4286AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4287AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4288AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4289/** @def X86_MODRM_MAKE
4290 * @param a_Mod The mod value (0..3).
4291 * @param a_Reg The register value (0..7).
4292 * @param a_RegMem The register or memory value (0..7). */
4293# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4294#endif
4295/** @} */
4296
4297/** @name SIB
4298 * @{ */
4299#define X86_SIB_BASE_MASK UINT8_C(0x07)
4300#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4301#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4302#define X86_SIB_INDEX_SHIFT 3
4303#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4304#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4305#define X86_SIB_SCALE_SHIFT 6
4306#ifndef VBOX_FOR_DTRACE_LIB
4307AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4308AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4309AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4310#endif
4311/** @} */
4312
4313/** @name General register indexes
4314 * @{ */
4315#define X86_GREG_xAX 0
4316#define X86_GREG_xCX 1
4317#define X86_GREG_xDX 2
4318#define X86_GREG_xBX 3
4319#define X86_GREG_xSP 4
4320#define X86_GREG_xBP 5
4321#define X86_GREG_xSI 6
4322#define X86_GREG_xDI 7
4323#define X86_GREG_x8 8
4324#define X86_GREG_x9 9
4325#define X86_GREG_x10 10
4326#define X86_GREG_x11 11
4327#define X86_GREG_x12 12
4328#define X86_GREG_x13 13
4329#define X86_GREG_x14 14
4330#define X86_GREG_x15 15
4331/** @} */
4332
4333/** @name X86_SREG_XXX - Segment register indexes.
4334 * @{ */
4335#define X86_SREG_ES 0
4336#define X86_SREG_CS 1
4337#define X86_SREG_SS 2
4338#define X86_SREG_DS 3
4339#define X86_SREG_FS 4
4340#define X86_SREG_GS 5
4341/** @} */
4342/** Segment register count. */
4343#define X86_SREG_COUNT 6
4344
4345
4346/** @name X86_OP_XXX - Prefixes
4347 * @{ */
4348#define X86_OP_PRF_CS UINT8_C(0x2e)
4349#define X86_OP_PRF_SS UINT8_C(0x36)
4350#define X86_OP_PRF_DS UINT8_C(0x3e)
4351#define X86_OP_PRF_ES UINT8_C(0x26)
4352#define X86_OP_PRF_FS UINT8_C(0x64)
4353#define X86_OP_PRF_GS UINT8_C(0x65)
4354#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4355#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4356#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4357#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4358#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4359#define X86_OP_REX_B UINT8_C(0x41)
4360#define X86_OP_REX_X UINT8_C(0x42)
4361#define X86_OP_REX_R UINT8_C(0x44)
4362#define X86_OP_REX_W UINT8_C(0x48)
4363/** @} */
4364
4365
4366/** @} */
4367
4368#endif
4369
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