VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 74131

Last change on this file since 74131 was 74131, checked in by vboxsync, 6 years ago

x86.h: Added IA32_DEBUG_CTL MSR's valid mask (Intel specific).
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2017 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT_32(0)
164#define X86_EFL_CF_BIT 0
165/** Bit 1 - Reserved, reads as 1. */
166#define X86_EFL_1 RT_BIT_32(1)
167/** Bit 2 - PF - Parity flag - Status flag. */
168#define X86_EFL_PF RT_BIT_32(2)
169/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170#define X86_EFL_AF RT_BIT_32(4)
171#define X86_EFL_AF_BIT 4
172/** Bit 6 - ZF - Zero flag - Status flag. */
173#define X86_EFL_ZF RT_BIT_32(6)
174#define X86_EFL_ZF_BIT 6
175/** Bit 7 - SF - Signed flag - Status flag. */
176#define X86_EFL_SF RT_BIT_32(7)
177#define X86_EFL_SF_BIT 7
178/** Bit 8 - TF - Trap flag - System flag. */
179#define X86_EFL_TF RT_BIT_32(8)
180/** Bit 9 - IF - Interrupt flag - System flag. */
181#define X86_EFL_IF RT_BIT_32(9)
182/** Bit 10 - DF - Direction flag - Control flag. */
183#define X86_EFL_DF RT_BIT_32(10)
184/** Bit 11 - OF - Overflow flag - Status flag. */
185#define X86_EFL_OF RT_BIT_32(11)
186#define X86_EFL_OF_BIT 11
187/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
189/** Bit 14 - NT - Nested task flag - System flag. */
190#define X86_EFL_NT RT_BIT_32(14)
191/** Bit 16 - RF - Resume flag - System flag. */
192#define X86_EFL_RF RT_BIT_32(16)
193/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194#define X86_EFL_VM RT_BIT_32(17)
195/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196#define X86_EFL_AC RT_BIT_32(18)
197/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198#define X86_EFL_VIF RT_BIT_32(19)
199/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200#define X86_EFL_VIP RT_BIT_32(20)
201/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202#define X86_EFL_ID RT_BIT_32(21)
203/** All live bits. */
204#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205/** Read as 1 bits. */
206#define X86_EFL_RA1_MASK RT_BIT_32(1)
207/** IOPL shift. */
208#define X86_EFL_IOPL_SHIFT 12
209/** The IOPL level from the flags. */
210#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211/** Bits restored by popf */
212#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
213 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
217/** The status bits commonly updated by arithmetic instructions. */
218#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
219/** @} */
220
221
222/** CPUID Feature information - ECX.
223 * CPUID query with EAX=1.
224 */
225#ifndef VBOX_FOR_DTRACE_LIB
226typedef struct X86CPUIDFEATECX
227{
228 /** Bit 0 - SSE3 - Supports SSE3 or not. */
229 unsigned u1SSE3 : 1;
230 /** Bit 1 - PCLMULQDQ. */
231 unsigned u1PCLMULQDQ : 1;
232 /** Bit 2 - DS Area 64-bit layout. */
233 unsigned u1DTE64 : 1;
234 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235 unsigned u1Monitor : 1;
236 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237 unsigned u1CPLDS : 1;
238 /** Bit 5 - VMX - Virtual Machine Technology. */
239 unsigned u1VMX : 1;
240 /** Bit 6 - SMX: Safer Mode Extensions. */
241 unsigned u1SMX : 1;
242 /** Bit 7 - EST - Enh. SpeedStep Tech. */
243 unsigned u1EST : 1;
244 /** Bit 8 - TM2 - Terminal Monitor 2. */
245 unsigned u1TM2 : 1;
246 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247 unsigned u1SSSE3 : 1;
248 /** Bit 10 - CNTX-ID - L1 Context ID. */
249 unsigned u1CNTXID : 1;
250 /** Bit 11 - Reserved. */
251 unsigned u1Reserved1 : 1;
252 /** Bit 12 - FMA. */
253 unsigned u1FMA : 1;
254 /** Bit 13 - CX16 - CMPXCHG16B. */
255 unsigned u1CX16 : 1;
256 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257 unsigned u1TPRUpdate : 1;
258 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259 unsigned u1PDCM : 1;
260 /** Bit 16 - Reserved. */
261 unsigned u1Reserved2 : 1;
262 /** Bit 17 - PCID - Process-context identifiers. */
263 unsigned u1PCID : 1;
264 /** Bit 18 - Direct Cache Access. */
265 unsigned u1DCA : 1;
266 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267 unsigned u1SSE4_1 : 1;
268 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269 unsigned u1SSE4_2 : 1;
270 /** Bit 21 - x2APIC. */
271 unsigned u1x2APIC : 1;
272 /** Bit 22 - MOVBE - Supports MOVBE. */
273 unsigned u1MOVBE : 1;
274 /** Bit 23 - POPCNT - Supports POPCNT. */
275 unsigned u1POPCNT : 1;
276 /** Bit 24 - TSC-Deadline. */
277 unsigned u1TSCDEADLINE : 1;
278 /** Bit 25 - AES. */
279 unsigned u1AES : 1;
280 /** Bit 26 - XSAVE - Supports XSAVE. */
281 unsigned u1XSAVE : 1;
282 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283 unsigned u1OSXSAVE : 1;
284 /** Bit 28 - AVX - Supports AVX instruction extensions. */
285 unsigned u1AVX : 1;
286 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287 unsigned u1F16C : 1;
288 /** Bit 30 - RDRAND - Supports RDRAND. */
289 unsigned u1RDRAND : 1;
290 /** Bit 31 - Hypervisor present (we're a guest). */
291 unsigned u1HVP : 1;
292} X86CPUIDFEATECX;
293#else /* VBOX_FOR_DTRACE_LIB */
294typedef uint32_t X86CPUIDFEATECX;
295#endif /* VBOX_FOR_DTRACE_LIB */
296/** Pointer to CPUID Feature Information - ECX. */
297typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298/** Pointer to const CPUID Feature Information - ECX. */
299typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302/** CPUID Feature Information - EDX.
303 * CPUID query with EAX=1.
304 */
305#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306typedef struct X86CPUIDFEATEDX
307{
308 /** Bit 0 - FPU - x87 FPU on Chip. */
309 unsigned u1FPU : 1;
310 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311 unsigned u1VME : 1;
312 /** Bit 2 - DE - Debugging extensions. */
313 unsigned u1DE : 1;
314 /** Bit 3 - PSE - Page Size Extension. */
315 unsigned u1PSE : 1;
316 /** Bit 4 - TSC - Time Stamp Counter. */
317 unsigned u1TSC : 1;
318 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319 unsigned u1MSR : 1;
320 /** Bit 6 - PAE - Physical Address Extension. */
321 unsigned u1PAE : 1;
322 /** Bit 7 - MCE - Machine Check Exception. */
323 unsigned u1MCE : 1;
324 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
325 unsigned u1CX8 : 1;
326 /** Bit 9 - APIC - APIC On-Chip. */
327 unsigned u1APIC : 1;
328 /** Bit 10 - Reserved. */
329 unsigned u1Reserved1 : 1;
330 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331 unsigned u1SEP : 1;
332 /** Bit 12 - MTRR - Memory Type Range Registers. */
333 unsigned u1MTRR : 1;
334 /** Bit 13 - PGE - PTE Global Bit. */
335 unsigned u1PGE : 1;
336 /** Bit 14 - MCA - Machine Check Architecture. */
337 unsigned u1MCA : 1;
338 /** Bit 15 - CMOV - Conditional Move Instructions. */
339 unsigned u1CMOV : 1;
340 /** Bit 16 - PAT - Page Attribute Table. */
341 unsigned u1PAT : 1;
342 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343 unsigned u1PSE36 : 1;
344 /** Bit 18 - PSN - Processor Serial Number. */
345 unsigned u1PSN : 1;
346 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
347 unsigned u1CLFSH : 1;
348 /** Bit 20 - Reserved. */
349 unsigned u1Reserved2 : 1;
350 /** Bit 21 - DS - Debug Store. */
351 unsigned u1DS : 1;
352 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353 unsigned u1ACPI : 1;
354 /** Bit 23 - MMX - Intel MMX 'Technology'. */
355 unsigned u1MMX : 1;
356 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357 unsigned u1FXSR : 1;
358 /** Bit 25 - SSE - SSE Support. */
359 unsigned u1SSE : 1;
360 /** Bit 26 - SSE2 - SSE2 Support. */
361 unsigned u1SSE2 : 1;
362 /** Bit 27 - SS - Self Snoop. */
363 unsigned u1SS : 1;
364 /** Bit 28 - HTT - Hyper-Threading Technology. */
365 unsigned u1HTT : 1;
366 /** Bit 29 - TM - Thermal Monitor. */
367 unsigned u1TM : 1;
368 /** Bit 30 - Reserved - . */
369 unsigned u1Reserved3 : 1;
370 /** Bit 31 - PBE - Pending Break Enabled. */
371 unsigned u1PBE : 1;
372} X86CPUIDFEATEDX;
373#else /* VBOX_FOR_DTRACE_LIB */
374typedef uint32_t X86CPUIDFEATEDX;
375#endif /* VBOX_FOR_DTRACE_LIB */
376/** Pointer to CPUID Feature Information - EDX. */
377typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378/** Pointer to const CPUID Feature Information - EDX. */
379typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381/** @name CPUID Vendor information.
382 * CPUID query with EAX=0.
383 * @{
384 */
385#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396/** @} */
397
398
399/** @name CPUID Feature information.
400 * CPUID query with EAX=1.
401 * @{
402 */
403/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428/** ECX Bit 12 - FMA. */
429#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436/** ECX Bit 17 - PCID - Process-context identifiers. */
437#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438/** ECX Bit 18 - DCA - Direct Cache Access. */
439#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444/** ECX Bit 21 - x2APIC support. */
445#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446/** ECX Bit 22 - MOVBE instruction. */
447#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448/** ECX Bit 23 - POPCNT instruction. */
449#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450/** ECX Bir 24 - TSC-Deadline. */
451#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452/** ECX Bit 25 - AES instructions. */
453#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454/** ECX Bit 26 - XSAVE instruction. */
455#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458/** ECX Bit 28 - AVX. */
459#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462/** ECX Bit 30 - RDRAND instruction. */
463#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464/** ECX Bit 31 - Hypervisor Present (software only). */
465#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468/** Bit 0 - FPU - x87 FPU on Chip. */
469#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472/** Bit 2 - DE - Debugging extensions. */
473#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474/** Bit 3 - PSE - Page Size Extension. */
475#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
477/** Bit 4 - TSC - Time Stamp Counter. */
478#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481/** Bit 6 - PAE - Physical Address Extension. */
482#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
484/** Bit 7 - MCE - Machine Check Exception. */
485#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488/** Bit 9 - APIC - APIC On-Chip. */
489#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492/** Bit 12 - MTRR - Memory Type Range Registers. */
493#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494/** Bit 13 - PGE - PTE Global Bit. */
495#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496/** Bit 14 - MCA - Machine Check Architecture. */
497#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498/** Bit 15 - CMOV - Conditional Move Instructions. */
499#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500/** Bit 16 - PAT - Page Attribute Table. */
501#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504/** Bit 18 - PSN - Processor Serial Number. */
505#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508/** Bit 21 - DS - Debug Store. */
509#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512/** Bit 23 - MMX - Intel MMX Technology. */
513#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516/** Bit 25 - SSE - SSE Support. */
517#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518/** Bit 26 - SSE2 - SSE2 Support. */
519#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520/** Bit 27 - SS - Self Snoop. */
521#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522/** Bit 28 - HTT - Hyper-Threading Technology. */
523#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524/** Bit 29 - TM - Therm. Monitor. */
525#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526/** Bit 31 - PBE - Pending Break Enabled. */
527#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528/** @} */
529
530/** @name CPUID mwait/monitor information.
531 * CPUID query with EAX=5.
532 * @{
533 */
534/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538/** @} */
539
540
541/** @name CPUID Structured Extended Feature information.
542 * CPUID query with EAX=7.
543 * @{
544 */
545/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
601#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
602/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
603#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
604/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
605#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
606/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
607#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
608/** ECX Bit 22 - RDPID - Support pread process ID. */
609#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
610/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
611#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
612
613/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
614 * IBPB command in IA32_PRED_CMD. */
615#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
616/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
617#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
618
619/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
620#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
621
622/** @} */
623
624
625/** @name CPUID Extended Feature information.
626 * CPUID query with EAX=0x80000001.
627 * @{
628 */
629/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
630#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
631
632/** EDX Bit 11 - SYSCALL/SYSRET. */
633#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
634/** EDX Bit 20 - No-Execute/Execute-Disable. */
635#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
636/** EDX Bit 26 - 1 GB large page. */
637#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
638/** EDX Bit 27 - RDTSCP. */
639#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
640/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
641#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
642/** @}*/
643
644/** @name CPUID AMD Feature information.
645 * CPUID query with EAX=0x80000001.
646 * @{
647 */
648/** Bit 0 - FPU - x87 FPU on Chip. */
649#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
650/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
651#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
652/** Bit 2 - DE - Debugging extensions. */
653#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
654/** Bit 3 - PSE - Page Size Extension. */
655#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
656/** Bit 4 - TSC - Time Stamp Counter. */
657#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
658/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
659#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
660/** Bit 6 - PAE - Physical Address Extension. */
661#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
662/** Bit 7 - MCE - Machine Check Exception. */
663#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
664/** Bit 8 - CX8 - CMPXCHG8B instruction. */
665#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
666/** Bit 9 - APIC - APIC On-Chip. */
667#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
668/** Bit 12 - MTRR - Memory Type Range Registers. */
669#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
670/** Bit 13 - PGE - PTE Global Bit. */
671#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
672/** Bit 14 - MCA - Machine Check Architecture. */
673#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
674/** Bit 15 - CMOV - Conditional Move Instructions. */
675#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
676/** Bit 16 - PAT - Page Attribute Table. */
677#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
678/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
679#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
680/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
681#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
682/** Bit 23 - MMX - Intel MMX Technology. */
683#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
684/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
685#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
686/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
687#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
688/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
689#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
690/** Bit 31 - 3DNOW - AMD 3DNow. */
691#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
692
693/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
694#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
695/** Bit 2 - SVM - AMD VM extensions. */
696#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
697/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
698#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
699/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
700#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
701/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
702#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
703/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
704#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
705/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
706#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
707/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
708#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
709/** Bit 9 - OSVW - AMD OS visible workaround. */
710#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
711/** Bit 10 - IBS - Instruct based sampling. */
712#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
713/** Bit 11 - XOP - Extended operation support (see APM6). */
714#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
715/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
716#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
717/** Bit 13 - WDT - AMD Watchdog timer support. */
718#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
719/** Bit 15 - LWP - Lightweight profiling support. */
720#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
721/** Bit 16 - FMA4 - Four operand FMA instruction support. */
722#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
723/** Bit 19 - NodeId - Indicates support for
724 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
725#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
726/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
727#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
728/** Bit 22 - TopologyExtensions - . */
729#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
730/** @} */
731
732
733/** @name CPUID AMD Feature information.
734 * CPUID query with EAX=0x80000007.
735 * @{
736 */
737/** Bit 0 - TS - Temperature Sensor. */
738#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
739/** Bit 1 - FID - Frequency ID Control. */
740#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
741/** Bit 2 - VID - Voltage ID Control. */
742#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
743/** Bit 3 - TTP - THERMTRIP. */
744#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
745/** Bit 4 - TM - Hardware Thermal Control. */
746#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
747/** Bit 5 - STC - Software Thermal Control. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
749/** Bit 6 - MC - 100 Mhz Multiplier Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
751/** Bit 7 - HWPSTATE - Hardware P-State Control. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
753/** Bit 8 - TSCINVAR - TSC Invariant. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
755/** Bit 9 - CPB - TSC Invariant. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
757/** Bit 10 - EffFreqRO - MPERF/APERF. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
759/** Bit 11 - PFI - Processor feedback interface (see EAX). */
760#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
761/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
762#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
763/** @} */
764
765
766/** @name CPUID AMD extended feature extensions ID (EBX).
767 * CPUID query with EAX=0x80000008.
768 * @{
769 */
770/** Bit 0 - CLZERO - Clear zero instruction. */
771#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
772/** Bit 1 - IRPerf - Instructions retired count support. */
773#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
774/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
775#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
776/* AMD pipeline length: 9 feature bits ;-) */
777/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
778#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
779/** @} */
780
781
782/** @name CPUID AMD SVM Feature information.
783 * CPUID query with EAX=0x8000000a.
784 * @{
785 */
786/** Bit 0 - NP - Nested Paging supported. */
787#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
788/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
789#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
790/** Bit 2 - SVML - SVM locking bit supported. */
791#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
792/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
793#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
794/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
795#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
796/** Bit 5 - VmcbClean - Support VMCB clean bits. */
797#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
798/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
799 * VMCB.TLB_Control is supported. */
800#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
801/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
802#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
803/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
804#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
805/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
806 * intercept filter cycle count threshold. */
807#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
808/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
809#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
810/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
811#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
812/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
813#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
814/** @} */
815
816
817/** @name CR0
818 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
819 * reserved flags.
820 * @{ */
821/** Bit 0 - PE - Protection Enabled */
822#define X86_CR0_PE RT_BIT_32(0)
823#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
824/** Bit 1 - MP - Monitor Coprocessor */
825#define X86_CR0_MP RT_BIT_32(1)
826#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
827/** Bit 2 - EM - Emulation. */
828#define X86_CR0_EM RT_BIT_32(2)
829#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
830/** Bit 3 - TS - Task Switch. */
831#define X86_CR0_TS RT_BIT_32(3)
832#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
833/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
834#define X86_CR0_ET RT_BIT_32(4)
835#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
836/** Bit 5 - NE - Numeric error (486+). */
837#define X86_CR0_NE RT_BIT_32(5)
838#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
839/** Bit 16 - WP - Write Protect (486+). */
840#define X86_CR0_WP RT_BIT_32(16)
841#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
842/** Bit 18 - AM - Alignment Mask (486+). */
843#define X86_CR0_AM RT_BIT_32(18)
844#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
845/** Bit 29 - NW - Not Write-though (486+). */
846#define X86_CR0_NW RT_BIT_32(29)
847#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
848/** Bit 30 - WP - Cache Disable (486+). */
849#define X86_CR0_CD RT_BIT_32(30)
850#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
851/** Bit 31 - PG - Paging. */
852#define X86_CR0_PG RT_BIT_32(31)
853#define X86_CR0_PAGING RT_BIT_32(31)
854#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
855/** @} */
856
857
858/** @name CR3
859 * @{ */
860/** Bit 3 - PWT - Page-level Writes Transparent. */
861#define X86_CR3_PWT RT_BIT_32(3)
862/** Bit 4 - PCD - Page-level Cache Disable. */
863#define X86_CR3_PCD RT_BIT_32(4)
864/** Bits 12-31 - - Page directory page number. */
865#define X86_CR3_PAGE_MASK (0xfffff000)
866/** Bits 5-31 - - PAE Page directory page number. */
867#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
868/** Bits 12-51 - - AMD64 Page directory page number. */
869#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
870/** @} */
871
872
873/** @name CR4
874 * @{ */
875/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
876#define X86_CR4_VME RT_BIT_32(0)
877/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
878#define X86_CR4_PVI RT_BIT_32(1)
879/** Bit 2 - TSD - Time Stamp Disable. */
880#define X86_CR4_TSD RT_BIT_32(2)
881/** Bit 3 - DE - Debugging Extensions. */
882#define X86_CR4_DE RT_BIT_32(3)
883/** Bit 4 - PSE - Page Size Extension. */
884#define X86_CR4_PSE RT_BIT_32(4)
885/** Bit 5 - PAE - Physical Address Extension. */
886#define X86_CR4_PAE RT_BIT_32(5)
887/** Bit 6 - MCE - Machine-Check Enable. */
888#define X86_CR4_MCE RT_BIT_32(6)
889/** Bit 7 - PGE - Page Global Enable. */
890#define X86_CR4_PGE RT_BIT_32(7)
891/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
892#define X86_CR4_PCE RT_BIT_32(8)
893/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
894#define X86_CR4_OSFXSR RT_BIT_32(9)
895/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
896#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
897/** Bit 13 - VMXE - VMX mode is enabled. */
898#define X86_CR4_VMXE RT_BIT_32(13)
899/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
900#define X86_CR4_SMXE RT_BIT_32(14)
901/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
902#define X86_CR4_FSGSBASE RT_BIT_32(16)
903/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
904#define X86_CR4_PCIDE RT_BIT_32(17)
905/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
906 * extended states. */
907#define X86_CR4_OSXSAVE RT_BIT_32(18)
908/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
909#define X86_CR4_SMEP RT_BIT_32(20)
910/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
911#define X86_CR4_SMAP RT_BIT_32(21)
912/** Bit 22 - PKE - Protection Key Enable. */
913#define X86_CR4_PKE RT_BIT_32(22)
914/** @} */
915
916
917/** @name DR6
918 * @{ */
919/** Bit 0 - B0 - Breakpoint 0 condition detected. */
920#define X86_DR6_B0 RT_BIT_32(0)
921/** Bit 1 - B1 - Breakpoint 1 condition detected. */
922#define X86_DR6_B1 RT_BIT_32(1)
923/** Bit 2 - B2 - Breakpoint 2 condition detected. */
924#define X86_DR6_B2 RT_BIT_32(2)
925/** Bit 3 - B3 - Breakpoint 3 condition detected. */
926#define X86_DR6_B3 RT_BIT_32(3)
927/** Mask of all the Bx bits. */
928#define X86_DR6_B_MASK UINT64_C(0x0000000f)
929/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
930#define X86_DR6_BD RT_BIT_32(13)
931/** Bit 14 - BS - Single step */
932#define X86_DR6_BS RT_BIT_32(14)
933/** Bit 15 - BT - Task switch. (TSS T bit.) */
934#define X86_DR6_BT RT_BIT_32(15)
935/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
936#define X86_DR6_RTM RT_BIT_32(16)
937/** Value of DR6 after powerup/reset. */
938#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
939/** Bits which must be 1s in DR6. */
940#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
941/** Bits which must be 1s in DR6, when RTM is supported. */
942#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
943/** Bits which must be 0s in DR6. */
944#define X86_DR6_RAZ_MASK RT_BIT_64(12)
945/** Bits which must be 0s on writes to DR6. */
946#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
947/** @} */
948
949/** Get the DR6.Bx bit for a the given breakpoint. */
950#define X86_DR6_B(iBp) RT_BIT_64(iBp)
951
952
953/** @name DR7
954 * @{ */
955/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
956#define X86_DR7_L0 RT_BIT_32(0)
957/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
958#define X86_DR7_G0 RT_BIT_32(1)
959/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
960#define X86_DR7_L1 RT_BIT_32(2)
961/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
962#define X86_DR7_G1 RT_BIT_32(3)
963/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
964#define X86_DR7_L2 RT_BIT_32(4)
965/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
966#define X86_DR7_G2 RT_BIT_32(5)
967/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
968#define X86_DR7_L3 RT_BIT_32(6)
969/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
970#define X86_DR7_G3 RT_BIT_32(7)
971/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
972#define X86_DR7_LE RT_BIT_32(8)
973/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
974#define X86_DR7_GE RT_BIT_32(9)
975
976/** L0, L1, L2, and L3. */
977#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
978/** L0, L1, L2, and L3. */
979#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
980
981/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
982 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
983#define X86_DR7_RTM RT_BIT_32(11)
984/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
985 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
986 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
987 * instruction is executed.
988 * @see http://www.rcollins.org/secrets/DR7.html */
989#define X86_DR7_ICE_IR RT_BIT_32(12)
990/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
991 * any DR register is accessed. */
992#define X86_DR7_GD RT_BIT_32(13)
993/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
994 * Pentium. */
995#define X86_DR7_ICE_TR1 RT_BIT_32(14)
996/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
997#define X86_DR7_ICE_TR2 RT_BIT_32(15)
998/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
999#define X86_DR7_RW0_MASK (3 << 16)
1000/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1001#define X86_DR7_LEN0_MASK (3 << 18)
1002/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1003#define X86_DR7_RW1_MASK (3 << 20)
1004/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1005#define X86_DR7_LEN1_MASK (3 << 22)
1006/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1007#define X86_DR7_RW2_MASK (3 << 24)
1008/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1009#define X86_DR7_LEN2_MASK (3 << 26)
1010/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1011#define X86_DR7_RW3_MASK (3 << 28)
1012/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1013#define X86_DR7_LEN3_MASK (3 << 30)
1014
1015/** Bits which reads as 1s. */
1016#define X86_DR7_RA1_MASK RT_BIT_32(10)
1017/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1018#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1019/** Bits which must be 0s when writing to DR7. */
1020#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1021
1022/** Calcs the L bit of Nth breakpoint.
1023 * @param iBp The breakpoint number [0..3].
1024 */
1025#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1026
1027/** Calcs the G bit of Nth breakpoint.
1028 * @param iBp The breakpoint number [0..3].
1029 */
1030#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1031
1032/** Calcs the L and G bits of Nth breakpoint.
1033 * @param iBp The breakpoint number [0..3].
1034 */
1035#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1036
1037/** @name Read/Write values.
1038 * @{ */
1039/** Break on instruction fetch only. */
1040#define X86_DR7_RW_EO UINT32_C(0)
1041/** Break on write only. */
1042#define X86_DR7_RW_WO UINT32_C(1)
1043/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1044#define X86_DR7_RW_IO UINT32_C(2)
1045/** Break on read or write (but not instruction fetches). */
1046#define X86_DR7_RW_RW UINT32_C(3)
1047/** @} */
1048
1049/** Shifts a X86_DR7_RW_* value to its right place.
1050 * @param iBp The breakpoint number [0..3].
1051 * @param fRw One of the X86_DR7_RW_* value.
1052 */
1053#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1054
1055/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1056 * one of the X86_DR7_RW_XXX constants).
1057 *
1058 * @returns X86_DR7_RW_XXX
1059 * @param uDR7 DR7 value
1060 * @param iBp The breakpoint number [0..3].
1061 */
1062#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1063
1064/** R/W0, R/W1, R/W2, and R/W3. */
1065#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1066
1067#ifndef VBOX_FOR_DTRACE_LIB
1068/** Checks if there are any I/O breakpoint types configured in the RW
1069 * registers. Does NOT check if these are enabled, sorry. */
1070# define X86_DR7_ANY_RW_IO(uDR7) \
1071 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1072 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1073AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1074AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1075AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1076AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1077AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1078AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1079AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1080AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1081AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1082#endif /* !VBOX_FOR_DTRACE_LIB */
1083
1084/** @name Length values.
1085 * @{ */
1086#define X86_DR7_LEN_BYTE UINT32_C(0)
1087#define X86_DR7_LEN_WORD UINT32_C(1)
1088#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1089#define X86_DR7_LEN_DWORD UINT32_C(3)
1090/** @} */
1091
1092/** Shifts a X86_DR7_LEN_* value to its right place.
1093 * @param iBp The breakpoint number [0..3].
1094 * @param cb One of the X86_DR7_LEN_* values.
1095 */
1096#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1097
1098/** Fetch the breakpoint length bits from the DR7 value.
1099 * @param uDR7 DR7 value
1100 * @param iBp The breakpoint number [0..3].
1101 */
1102#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1103
1104/** Mask used to check if any breakpoints are enabled. */
1105#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1106
1107/** LEN0, LEN1, LEN2, and LEN3. */
1108#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1109/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1110#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1111
1112/** Value of DR7 after powerup/reset. */
1113#define X86_DR7_INIT_VAL 0x400
1114/** @} */
1115
1116
1117/** @name Machine Specific Registers
1118 * @{
1119 */
1120/** Machine check address register (P5). */
1121#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1122/** Machine check type register (P5). */
1123#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1124/** Time Stamp Counter. */
1125#define MSR_IA32_TSC 0x10
1126#define MSR_IA32_CESR UINT32_C(0x00000011)
1127#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1128#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1129
1130#define MSR_IA32_PLATFORM_ID 0x17
1131
1132#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1133# define MSR_IA32_APICBASE 0x1b
1134/** Local APIC enabled. */
1135# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1136/** X2APIC enabled (requires the EN bit to be set). */
1137# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1138/** The processor is the boot strap processor (BSP). */
1139# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1140/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1141 * width. */
1142# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1143/** The default physical base address of the APIC. */
1144# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1145/** Gets the physical base address from the MSR. */
1146# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1147#endif
1148
1149/** Undocumented intel MSR for reporting thread and core counts.
1150 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1151 * first 16 bits is the thread count. The next 16 bits the core count, except
1152 * on Westmere where it seems it's only the next 4 bits for some reason. */
1153#define MSR_CORE_THREAD_COUNT 0x35
1154
1155/** CPU Feature control. */
1156#define MSR_IA32_FEATURE_CONTROL 0x3A
1157/** Feature control - Lock MSR from writes (R/W0). */
1158#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1159/** Feature control - Enable VMX inside SMX operation (R/WL). */
1160#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1161/** Feature control - Enable VMX outside SMX operation (R/WL). */
1162#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1163/** Feature control - SENTER local functions enable (R/WL). */
1164#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1165#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1166#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1167#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1168#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1169#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1170#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1171/** Feature control - SENTER global enable (R/WL). */
1172#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1173/** Feature control - SGX launch control enable (R/WL). */
1174#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1175/** Feature control - SGX global enable (R/WL). */
1176#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1177/** Feature control - LMCE on (R/WL). */
1178#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1179
1180/** Per-processor TSC adjust MSR. */
1181#define MSR_IA32_TSC_ADJUST 0x3B
1182
1183/** Spectre control register.
1184 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1185#define MSR_IA32_SPEC_CTRL 0x48
1186/** IBRS - Indirect branch restricted speculation. */
1187#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1188/** STIBP - Single thread indirect branch predictors. */
1189#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1190
1191/** Prediction command register.
1192 * Write only, logical processor scope, no state since write only. */
1193#define MSR_IA32_PRED_CMD 0x49
1194/** IBPB - Indirect branch prediction barrie when written as 1. */
1195#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1196
1197/** BIOS update trigger (microcode update). */
1198#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1199
1200/** BIOS update signature (microcode). */
1201#define MSR_IA32_BIOS_SIGN_ID 0x8B
1202
1203/** SMM monitor control. */
1204#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1205/** SMM control - Valid. */
1206#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1207/** SMM control - VMXOFF unblocks SMI. */
1208#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1209/** SMM control - MSEG base physical address. */
1210#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1211
1212/** General performance counter no. 0. */
1213#define MSR_IA32_PMC0 0xC1
1214/** General performance counter no. 1. */
1215#define MSR_IA32_PMC1 0xC2
1216/** General performance counter no. 2. */
1217#define MSR_IA32_PMC2 0xC3
1218/** General performance counter no. 3. */
1219#define MSR_IA32_PMC3 0xC4
1220
1221/** Nehalem power control. */
1222#define MSR_IA32_PLATFORM_INFO 0xCE
1223
1224/** Get FSB clock status (Intel-specific). */
1225#define MSR_IA32_FSB_CLOCK_STS 0xCD
1226
1227/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1228#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1229
1230/** C0 Maximum Frequency Clock Count */
1231#define MSR_IA32_MPERF 0xE7
1232/** C0 Actual Frequency Clock Count */
1233#define MSR_IA32_APERF 0xE8
1234
1235/** MTRR Capabilities. */
1236#define MSR_IA32_MTRR_CAP 0xFE
1237
1238/** Architecture capabilities (bugfixes).
1239 * @note May move */
1240#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1241/** CPU is no subject to spectre problems. */
1242#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0)
1243/** CPU has better IBRS and you can leave it on all the time. */
1244#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1)
1245
1246/** Cache control/info. */
1247#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1248
1249#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1250/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1251 * R0 SS == CS + 8
1252 * R3 CS == CS + 16
1253 * R3 SS == CS + 24
1254 */
1255#define MSR_IA32_SYSENTER_CS 0x174
1256/** SYSENTER_ESP - the R0 ESP. */
1257#define MSR_IA32_SYSENTER_ESP 0x175
1258/** SYSENTER_EIP - the R0 EIP. */
1259#define MSR_IA32_SYSENTER_EIP 0x176
1260#endif
1261
1262/** Machine Check Global Capabilities Register. */
1263#define MSR_IA32_MCG_CAP 0x179
1264/** Machine Check Global Status Register. */
1265#define MSR_IA32_MCG_STATUS 0x17A
1266/** Machine Check Global Control Register. */
1267#define MSR_IA32_MCG_CTRL 0x17B
1268
1269/** Page Attribute Table. */
1270#define MSR_IA32_CR_PAT 0x277
1271/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1272 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1273#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1274
1275/** Performance counter MSRs. (Intel only) */
1276#define MSR_IA32_PERFEVTSEL0 0x186
1277#define MSR_IA32_PERFEVTSEL1 0x187
1278/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1279 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1280 * holds a ratio that Apple takes for TSC granularity.
1281 *
1282 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1283#define MSR_FLEX_RATIO 0x194
1284/** Performance state value and starting with Intel core more.
1285 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1286#define MSR_IA32_PERF_STATUS 0x198
1287#define MSR_IA32_PERF_CTL 0x199
1288#define MSR_IA32_THERM_STATUS 0x19c
1289
1290/** Enable misc. processor features (R/W). */
1291#define MSR_IA32_MISC_ENABLE 0x1A0
1292/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1293#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1294/** Automatic Thermal Control Circuit Enable (R/W). */
1295#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1296/** Performance Monitoring Available (R). */
1297#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1298/** Branch Trace Storage Unavailable (R/O). */
1299#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1300/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1301#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1302/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1303#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1304/** If MONITOR/MWAIT is supported (R/W). */
1305#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1306/** Limit CPUID Maxval to 3 leafs (R/W). */
1307#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1308/** When set to 1, xTPR messages are disabled (R/W). */
1309#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1310/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1311#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1312
1313/** Trace/Profile Resource Control (R/W) */
1314#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1315/** Last branch record. */
1316#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1317/** Branch trace flag (single step on branches). */
1318#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1319/** Performance monitoring pin control (AMD only). */
1320#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1321#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1322#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1323#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1324/** Trace message enable (Intel only). */
1325#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1326/** Branch trace store (Intel only). */
1327#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1328/** Branch trace interrupt (Intel only). */
1329#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1330/** Branch trace off in privileged code (Intel only). */
1331#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1332/** Branch trace off in user code (Intel only). */
1333#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1334/** Freeze LBR on PMI flag (Intel only). */
1335#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1336/** Freeze PERFMON on PMI flag (Intel only). */
1337#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1338/** Freeze while SMM enabled (Intel only). */
1339#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1340/** Advanced debugging of RTM regions (Intel only). */
1341#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1342/** Debug control MSR valid bits (Intel only). */
1343#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1344 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1345 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1346 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1347 | MSR_IA32_DEBUGCTL_RTM)
1348
1349/** The number (0..3 or 0..15) of the last branch record register on P4 and
1350 * related Xeons. */
1351#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1352/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1353 * @{ */
1354#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1355#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1356#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1357#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1358/** @} */
1359
1360
1361#define IA32_MTRR_PHYSBASE0 0x200
1362#define IA32_MTRR_PHYSMASK0 0x201
1363#define IA32_MTRR_PHYSBASE1 0x202
1364#define IA32_MTRR_PHYSMASK1 0x203
1365#define IA32_MTRR_PHYSBASE2 0x204
1366#define IA32_MTRR_PHYSMASK2 0x205
1367#define IA32_MTRR_PHYSBASE3 0x206
1368#define IA32_MTRR_PHYSMASK3 0x207
1369#define IA32_MTRR_PHYSBASE4 0x208
1370#define IA32_MTRR_PHYSMASK4 0x209
1371#define IA32_MTRR_PHYSBASE5 0x20a
1372#define IA32_MTRR_PHYSMASK5 0x20b
1373#define IA32_MTRR_PHYSBASE6 0x20c
1374#define IA32_MTRR_PHYSMASK6 0x20d
1375#define IA32_MTRR_PHYSBASE7 0x20e
1376#define IA32_MTRR_PHYSMASK7 0x20f
1377#define IA32_MTRR_PHYSBASE8 0x210
1378#define IA32_MTRR_PHYSMASK8 0x211
1379#define IA32_MTRR_PHYSBASE9 0x212
1380#define IA32_MTRR_PHYSMASK9 0x213
1381
1382/** Fixed range MTRRs.
1383 * @{ */
1384#define IA32_MTRR_FIX64K_00000 0x250
1385#define IA32_MTRR_FIX16K_80000 0x258
1386#define IA32_MTRR_FIX16K_A0000 0x259
1387#define IA32_MTRR_FIX4K_C0000 0x268
1388#define IA32_MTRR_FIX4K_C8000 0x269
1389#define IA32_MTRR_FIX4K_D0000 0x26a
1390#define IA32_MTRR_FIX4K_D8000 0x26b
1391#define IA32_MTRR_FIX4K_E0000 0x26c
1392#define IA32_MTRR_FIX4K_E8000 0x26d
1393#define IA32_MTRR_FIX4K_F0000 0x26e
1394#define IA32_MTRR_FIX4K_F8000 0x26f
1395/** @} */
1396
1397/** MTRR Default Range. */
1398#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1399
1400/** Global performance counter control facilities (Intel only). */
1401#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1402#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1403#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1404
1405/** Precise Event Based sampling (Intel only). */
1406#define MSR_IA32_PEBS_ENABLE 0x3F1
1407
1408#define MSR_IA32_MC0_CTL 0x400
1409#define MSR_IA32_MC0_STATUS 0x401
1410
1411/** Basic VMX information. */
1412#define MSR_IA32_VMX_BASIC 0x480
1413/** Allowed settings for pin-based VM execution controls. */
1414#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1415/** Allowed settings for proc-based VM execution controls. */
1416#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1417/** Allowed settings for the VM-exit controls. */
1418#define MSR_IA32_VMX_EXIT_CTLS 0x483
1419/** Allowed settings for the VM-entry controls. */
1420#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1421/** Misc VMX info. */
1422#define MSR_IA32_VMX_MISC 0x485
1423/** Fixed cleared bits in CR0. */
1424#define MSR_IA32_VMX_CR0_FIXED0 0x486
1425/** Fixed set bits in CR0. */
1426#define MSR_IA32_VMX_CR0_FIXED1 0x487
1427/** Fixed cleared bits in CR4. */
1428#define MSR_IA32_VMX_CR4_FIXED0 0x488
1429/** Fixed set bits in CR4. */
1430#define MSR_IA32_VMX_CR4_FIXED1 0x489
1431/** Information for enumerating fields in the VMCS. */
1432#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1433/** Allowed settings for the VM-functions controls. */
1434#define MSR_IA32_VMX_VMFUNC 0x491
1435/** Allowed settings for secondary proc-based VM execution controls */
1436#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1437/** EPT capabilities. */
1438#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1439/** Allowed settings of all pin-based VM execution controls. */
1440#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1441/** Allowed settings of all proc-based VM execution controls. */
1442#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1443/** Allowed settings of all VMX exit controls. */
1444#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1445/** Allowed settings of all VMX entry controls. */
1446#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1447/** Allowed settings for the VM-function controls. */
1448#define MSR_IA32_VMX_VMFUNC 0x491
1449
1450
1451/** DS Save Area (R/W). */
1452#define MSR_IA32_DS_AREA 0x600
1453/** Running Average Power Limit (RAPL) power units. */
1454#define MSR_RAPL_POWER_UNIT 0x606
1455
1456/** X2APIC MSR range start. */
1457#define MSR_IA32_X2APIC_START 0x800
1458/** X2APIC MSR - APIC ID Register. */
1459#define MSR_IA32_X2APIC_ID 0x802
1460/** X2APIC MSR - APIC Version Register. */
1461#define MSR_IA32_X2APIC_VERSION 0x803
1462/** X2APIC MSR - Task Priority Register. */
1463#define MSR_IA32_X2APIC_TPR 0x808
1464/** X2APIC MSR - Processor Priority register. */
1465#define MSR_IA32_X2APIC_PPR 0x80A
1466/** X2APIC MSR - End Of Interrupt register. */
1467#define MSR_IA32_X2APIC_EOI 0x80B
1468/** X2APIC MSR - Logical Destination Register. */
1469#define MSR_IA32_X2APIC_LDR 0x80D
1470/** X2APIC MSR - Spurious Interrupt Vector Register. */
1471#define MSR_IA32_X2APIC_SVR 0x80F
1472/** X2APIC MSR - In-service Register (bits 31:0). */
1473#define MSR_IA32_X2APIC_ISR0 0x810
1474/** X2APIC MSR - In-service Register (bits 63:32). */
1475#define MSR_IA32_X2APIC_ISR1 0x811
1476/** X2APIC MSR - In-service Register (bits 95:64). */
1477#define MSR_IA32_X2APIC_ISR2 0x812
1478/** X2APIC MSR - In-service Register (bits 127:96). */
1479#define MSR_IA32_X2APIC_ISR3 0x813
1480/** X2APIC MSR - In-service Register (bits 159:128). */
1481#define MSR_IA32_X2APIC_ISR4 0x814
1482/** X2APIC MSR - In-service Register (bits 191:160). */
1483#define MSR_IA32_X2APIC_ISR5 0x815
1484/** X2APIC MSR - In-service Register (bits 223:192). */
1485#define MSR_IA32_X2APIC_ISR6 0x816
1486/** X2APIC MSR - In-service Register (bits 255:224). */
1487#define MSR_IA32_X2APIC_ISR7 0x817
1488/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1489#define MSR_IA32_X2APIC_TMR0 0x818
1490/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1491#define MSR_IA32_X2APIC_TMR1 0x819
1492/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1493#define MSR_IA32_X2APIC_TMR2 0x81A
1494/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1495#define MSR_IA32_X2APIC_TMR3 0x81B
1496/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1497#define MSR_IA32_X2APIC_TMR4 0x81C
1498/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1499#define MSR_IA32_X2APIC_TMR5 0x81D
1500/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1501#define MSR_IA32_X2APIC_TMR6 0x81E
1502/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1503#define MSR_IA32_X2APIC_TMR7 0x81F
1504/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1505#define MSR_IA32_X2APIC_IRR0 0x820
1506/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1507#define MSR_IA32_X2APIC_IRR1 0x821
1508/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1509#define MSR_IA32_X2APIC_IRR2 0x822
1510/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1511#define MSR_IA32_X2APIC_IRR3 0x823
1512/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1513#define MSR_IA32_X2APIC_IRR4 0x824
1514/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1515#define MSR_IA32_X2APIC_IRR5 0x825
1516/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1517#define MSR_IA32_X2APIC_IRR6 0x826
1518/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1519#define MSR_IA32_X2APIC_IRR7 0x827
1520/** X2APIC MSR - Error Status Register. */
1521#define MSR_IA32_X2APIC_ESR 0x828
1522/** X2APIC MSR - LVT CMCI Register. */
1523#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1524/** X2APIC MSR - Interrupt Command Register. */
1525#define MSR_IA32_X2APIC_ICR 0x830
1526/** X2APIC MSR - LVT Timer Register. */
1527#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1528/** X2APIC MSR - LVT Thermal Sensor Register. */
1529#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1530/** X2APIC MSR - LVT Performance Counter Register. */
1531#define MSR_IA32_X2APIC_LVT_PERF 0x834
1532/** X2APIC MSR - LVT LINT0 Register. */
1533#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1534/** X2APIC MSR - LVT LINT1 Register. */
1535#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1536/** X2APIC MSR - LVT Error Register . */
1537#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1538/** X2APIC MSR - Timer Initial Count Register. */
1539#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1540/** X2APIC MSR - Timer Current Count Register. */
1541#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1542/** X2APIC MSR - Timer Divide Configuration Register. */
1543#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1544/** X2APIC MSR - Self IPI. */
1545#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1546/** X2APIC MSR range end. */
1547#define MSR_IA32_X2APIC_END 0xBFF
1548/** X2APIC MSR - LVT start range. */
1549#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1550/** X2APIC MSR - LVT end range (inclusive). */
1551#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1552
1553/** K6 EFER - Extended Feature Enable Register. */
1554#define MSR_K6_EFER UINT32_C(0xc0000080)
1555/** @todo document EFER */
1556/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1557#define MSR_K6_EFER_SCE RT_BIT_32(0)
1558/** Bit 8 - LME - Long mode enabled. (R/W) */
1559#define MSR_K6_EFER_LME RT_BIT_32(8)
1560#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1561/** Bit 10 - LMA - Long mode active. (R) */
1562#define MSR_K6_EFER_LMA RT_BIT_32(10)
1563#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1564/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1565#define MSR_K6_EFER_NXE RT_BIT_32(11)
1566#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1567/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1568#define MSR_K6_EFER_SVME RT_BIT_32(12)
1569/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1570#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1571/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1572#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1573/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1574#define MSR_K6_EFER_TCE RT_BIT_32(15)
1575/** K6 STAR - SYSCALL/RET targets. */
1576#define MSR_K6_STAR UINT32_C(0xc0000081)
1577/** Shift value for getting the SYSRET CS and SS value. */
1578#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1579/** Shift value for getting the SYSCALL CS and SS value. */
1580#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1581/** Selector mask for use after shifting. */
1582#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1583/** The mask which give the SYSCALL EIP. */
1584#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1585/** K6 WHCR - Write Handling Control Register. */
1586#define MSR_K6_WHCR UINT32_C(0xc0000082)
1587/** K6 UWCCR - UC/WC Cacheability Control Register. */
1588#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1589/** K6 PSOR - Processor State Observability Register. */
1590#define MSR_K6_PSOR UINT32_C(0xc0000087)
1591/** K6 PFIR - Page Flush/Invalidate Register. */
1592#define MSR_K6_PFIR UINT32_C(0xc0000088)
1593
1594/** Performance counter MSRs. (AMD only) */
1595#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1596#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1597#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1598#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1599#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1600#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1601#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1602#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1603
1604/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1605#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1606/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1607#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1608/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1609#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1610/** K8 FS.base - The 64-bit base FS register. */
1611#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1612/** K8 GS.base - The 64-bit base GS register. */
1613#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1614/** K8 KernelGSbase - Used with SWAPGS. */
1615#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1616/** K8 TSC_AUX - Used with RDTSCP. */
1617#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1618#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1619#define MSR_K8_HWCR UINT32_C(0xc0010015)
1620#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1621#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1622#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1623#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1624#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1625#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1626/** North bridge config? See BIOS & Kernel dev guides for
1627 * details. */
1628#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1629
1630/** Hypertransport interrupt pending register.
1631 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1632#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1633
1634/** SVM Control. */
1635#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1636/** Disables HDT (Hardware Debug Tool) and certain internal debug
1637 * features. */
1638#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1639/** If set, non-intercepted INIT signals are converted to \#SX
1640 * exceptions. */
1641#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1642/** Disables A20 masking. */
1643#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1644/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1645#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1646/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1647 * clear, EFER.SVME can be written normally. */
1648#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1649
1650#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1651#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1652/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1653 * host state during world switch. */
1654#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1655
1656/** @} */
1657
1658
1659/** @name Page Table / Directory / Directory Pointers / L4.
1660 * @{
1661 */
1662
1663/** Page table/directory entry as an unsigned integer. */
1664typedef uint32_t X86PGUINT;
1665/** Pointer to a page table/directory table entry as an unsigned integer. */
1666typedef X86PGUINT *PX86PGUINT;
1667/** Pointer to an const page table/directory table entry as an unsigned integer. */
1668typedef X86PGUINT const *PCX86PGUINT;
1669
1670/** Number of entries in a 32-bit PT/PD. */
1671#define X86_PG_ENTRIES 1024
1672
1673
1674/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1675typedef uint64_t X86PGPAEUINT;
1676/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1677typedef X86PGPAEUINT *PX86PGPAEUINT;
1678/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1679typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1680
1681/** Number of entries in a PAE PT/PD. */
1682#define X86_PG_PAE_ENTRIES 512
1683/** Number of entries in a PAE PDPT. */
1684#define X86_PG_PAE_PDPE_ENTRIES 4
1685
1686/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1687#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1688/** Number of entries in an AMD64 PDPT.
1689 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1690#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1691
1692/** The size of a default page. */
1693#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1694/** The page shift of a default page. */
1695#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1696/** The default page offset mask. */
1697#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1698/** The default page base mask for virtual addresses. */
1699#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1700/** The default page base mask for virtual addresses - 32bit version. */
1701#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1702
1703/** The size of a 4KB page. */
1704#define X86_PAGE_4K_SIZE _4K
1705/** The page shift of a 4KB page. */
1706#define X86_PAGE_4K_SHIFT 12
1707/** The 4KB page offset mask. */
1708#define X86_PAGE_4K_OFFSET_MASK 0xfff
1709/** The 4KB page base mask for virtual addresses. */
1710#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1711/** The 4KB page base mask for virtual addresses - 32bit version. */
1712#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1713
1714/** The size of a 2MB page. */
1715#define X86_PAGE_2M_SIZE _2M
1716/** The page shift of a 2MB page. */
1717#define X86_PAGE_2M_SHIFT 21
1718/** The 2MB page offset mask. */
1719#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1720/** The 2MB page base mask for virtual addresses. */
1721#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1722/** The 2MB page base mask for virtual addresses - 32bit version. */
1723#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1724
1725/** The size of a 4MB page. */
1726#define X86_PAGE_4M_SIZE _4M
1727/** The page shift of a 4MB page. */
1728#define X86_PAGE_4M_SHIFT 22
1729/** The 4MB page offset mask. */
1730#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1731/** The 4MB page base mask for virtual addresses. */
1732#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1733/** The 4MB page base mask for virtual addresses - 32bit version. */
1734#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1735
1736/** The size of a 1GB page. */
1737#define X86_PAGE_1G_SIZE _1G
1738/** The page shift of a 1GB page. */
1739#define X86_PAGE_1G_SHIFT 30
1740/** The 1GB page offset mask. */
1741#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1742/** The 1GB page base mask for virtual addresses. */
1743#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1744
1745/**
1746 * Check if the given address is canonical.
1747 */
1748#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1749
1750
1751/** @name Page Table Entry
1752 * @{
1753 */
1754/** Bit 0 - P - Present bit. */
1755#define X86_PTE_BIT_P 0
1756/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1757#define X86_PTE_BIT_RW 1
1758/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1759#define X86_PTE_BIT_US 2
1760/** Bit 3 - PWT - Page level write thru bit. */
1761#define X86_PTE_BIT_PWT 3
1762/** Bit 4 - PCD - Page level cache disable bit. */
1763#define X86_PTE_BIT_PCD 4
1764/** Bit 5 - A - Access bit. */
1765#define X86_PTE_BIT_A 5
1766/** Bit 6 - D - Dirty bit. */
1767#define X86_PTE_BIT_D 6
1768/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1769#define X86_PTE_BIT_PAT 7
1770/** Bit 8 - G - Global flag. */
1771#define X86_PTE_BIT_G 8
1772/** Bits 63 - NX - PAE/LM - No execution flag. */
1773#define X86_PTE_PAE_BIT_NX 63
1774
1775/** Bit 0 - P - Present bit mask. */
1776#define X86_PTE_P RT_BIT_32(0)
1777/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1778#define X86_PTE_RW RT_BIT_32(1)
1779/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1780#define X86_PTE_US RT_BIT_32(2)
1781/** Bit 3 - PWT - Page level write thru bit mask. */
1782#define X86_PTE_PWT RT_BIT_32(3)
1783/** Bit 4 - PCD - Page level cache disable bit mask. */
1784#define X86_PTE_PCD RT_BIT_32(4)
1785/** Bit 5 - A - Access bit mask. */
1786#define X86_PTE_A RT_BIT_32(5)
1787/** Bit 6 - D - Dirty bit mask. */
1788#define X86_PTE_D RT_BIT_32(6)
1789/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1790#define X86_PTE_PAT RT_BIT_32(7)
1791/** Bit 8 - G - Global bit mask. */
1792#define X86_PTE_G RT_BIT_32(8)
1793
1794/** Bits 9-11 - - Available for use to system software. */
1795#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1796/** Bits 12-31 - - Physical Page number of the next level. */
1797#define X86_PTE_PG_MASK ( 0xfffff000 )
1798
1799/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1800#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1801/** Bits 63 - NX - PAE/LM - No execution flag. */
1802#define X86_PTE_PAE_NX RT_BIT_64(63)
1803/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1804#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1805/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1806#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1807/** No bits - - LM - MBZ bits when NX is active. */
1808#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1809/** Bits 63 - - LM - MBZ bits when no NX. */
1810#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1811
1812/**
1813 * Page table entry.
1814 */
1815typedef struct X86PTEBITS
1816{
1817 /** Flags whether(=1) or not the page is present. */
1818 uint32_t u1Present : 1;
1819 /** Read(=0) / Write(=1) flag. */
1820 uint32_t u1Write : 1;
1821 /** User(=1) / Supervisor (=0) flag. */
1822 uint32_t u1User : 1;
1823 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1824 uint32_t u1WriteThru : 1;
1825 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1826 uint32_t u1CacheDisable : 1;
1827 /** Accessed flag.
1828 * Indicates that the page have been read or written to. */
1829 uint32_t u1Accessed : 1;
1830 /** Dirty flag.
1831 * Indicates that the page has been written to. */
1832 uint32_t u1Dirty : 1;
1833 /** Reserved / If PAT enabled, bit 2 of the index. */
1834 uint32_t u1PAT : 1;
1835 /** Global flag. (Ignored in all but final level.) */
1836 uint32_t u1Global : 1;
1837 /** Available for use to system software. */
1838 uint32_t u3Available : 3;
1839 /** Physical Page number of the next level. */
1840 uint32_t u20PageNo : 20;
1841} X86PTEBITS;
1842#ifndef VBOX_FOR_DTRACE_LIB
1843AssertCompileSize(X86PTEBITS, 4);
1844#endif
1845/** Pointer to a page table entry. */
1846typedef X86PTEBITS *PX86PTEBITS;
1847/** Pointer to a const page table entry. */
1848typedef const X86PTEBITS *PCX86PTEBITS;
1849
1850/**
1851 * Page table entry.
1852 */
1853typedef union X86PTE
1854{
1855 /** Unsigned integer view */
1856 X86PGUINT u;
1857 /** Bit field view. */
1858 X86PTEBITS n;
1859 /** 32-bit view. */
1860 uint32_t au32[1];
1861 /** 16-bit view. */
1862 uint16_t au16[2];
1863 /** 8-bit view. */
1864 uint8_t au8[4];
1865} X86PTE;
1866#ifndef VBOX_FOR_DTRACE_LIB
1867AssertCompileSize(X86PTE, 4);
1868#endif
1869/** Pointer to a page table entry. */
1870typedef X86PTE *PX86PTE;
1871/** Pointer to a const page table entry. */
1872typedef const X86PTE *PCX86PTE;
1873
1874
1875/**
1876 * PAE page table entry.
1877 */
1878typedef struct X86PTEPAEBITS
1879{
1880 /** Flags whether(=1) or not the page is present. */
1881 uint32_t u1Present : 1;
1882 /** Read(=0) / Write(=1) flag. */
1883 uint32_t u1Write : 1;
1884 /** User(=1) / Supervisor(=0) flag. */
1885 uint32_t u1User : 1;
1886 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1887 uint32_t u1WriteThru : 1;
1888 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1889 uint32_t u1CacheDisable : 1;
1890 /** Accessed flag.
1891 * Indicates that the page have been read or written to. */
1892 uint32_t u1Accessed : 1;
1893 /** Dirty flag.
1894 * Indicates that the page has been written to. */
1895 uint32_t u1Dirty : 1;
1896 /** Reserved / If PAT enabled, bit 2 of the index. */
1897 uint32_t u1PAT : 1;
1898 /** Global flag. (Ignored in all but final level.) */
1899 uint32_t u1Global : 1;
1900 /** Available for use to system software. */
1901 uint32_t u3Available : 3;
1902 /** Physical Page number of the next level - Low Part. Don't use this. */
1903 uint32_t u20PageNoLow : 20;
1904 /** Physical Page number of the next level - High Part. Don't use this. */
1905 uint32_t u20PageNoHigh : 20;
1906 /** MBZ bits */
1907 uint32_t u11Reserved : 11;
1908 /** No Execute flag. */
1909 uint32_t u1NoExecute : 1;
1910} X86PTEPAEBITS;
1911#ifndef VBOX_FOR_DTRACE_LIB
1912AssertCompileSize(X86PTEPAEBITS, 8);
1913#endif
1914/** Pointer to a page table entry. */
1915typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1916/** Pointer to a page table entry. */
1917typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1918
1919/**
1920 * PAE Page table entry.
1921 */
1922typedef union X86PTEPAE
1923{
1924 /** Unsigned integer view */
1925 X86PGPAEUINT u;
1926 /** Bit field view. */
1927 X86PTEPAEBITS n;
1928 /** 32-bit view. */
1929 uint32_t au32[2];
1930 /** 16-bit view. */
1931 uint16_t au16[4];
1932 /** 8-bit view. */
1933 uint8_t au8[8];
1934} X86PTEPAE;
1935#ifndef VBOX_FOR_DTRACE_LIB
1936AssertCompileSize(X86PTEPAE, 8);
1937#endif
1938/** Pointer to a PAE page table entry. */
1939typedef X86PTEPAE *PX86PTEPAE;
1940/** Pointer to a const PAE page table entry. */
1941typedef const X86PTEPAE *PCX86PTEPAE;
1942/** @} */
1943
1944/**
1945 * Page table.
1946 */
1947typedef struct X86PT
1948{
1949 /** PTE Array. */
1950 X86PTE a[X86_PG_ENTRIES];
1951} X86PT;
1952#ifndef VBOX_FOR_DTRACE_LIB
1953AssertCompileSize(X86PT, 4096);
1954#endif
1955/** Pointer to a page table. */
1956typedef X86PT *PX86PT;
1957/** Pointer to a const page table. */
1958typedef const X86PT *PCX86PT;
1959
1960/** The page shift to get the PT index. */
1961#define X86_PT_SHIFT 12
1962/** The PT index mask (apply to a shifted page address). */
1963#define X86_PT_MASK 0x3ff
1964
1965
1966/**
1967 * Page directory.
1968 */
1969typedef struct X86PTPAE
1970{
1971 /** PTE Array. */
1972 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1973} X86PTPAE;
1974#ifndef VBOX_FOR_DTRACE_LIB
1975AssertCompileSize(X86PTPAE, 4096);
1976#endif
1977/** Pointer to a page table. */
1978typedef X86PTPAE *PX86PTPAE;
1979/** Pointer to a const page table. */
1980typedef const X86PTPAE *PCX86PTPAE;
1981
1982/** The page shift to get the PA PTE index. */
1983#define X86_PT_PAE_SHIFT 12
1984/** The PAE PT index mask (apply to a shifted page address). */
1985#define X86_PT_PAE_MASK 0x1ff
1986
1987
1988/** @name 4KB Page Directory Entry
1989 * @{
1990 */
1991/** Bit 0 - P - Present bit. */
1992#define X86_PDE_P RT_BIT_32(0)
1993/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1994#define X86_PDE_RW RT_BIT_32(1)
1995/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1996#define X86_PDE_US RT_BIT_32(2)
1997/** Bit 3 - PWT - Page level write thru bit. */
1998#define X86_PDE_PWT RT_BIT_32(3)
1999/** Bit 4 - PCD - Page level cache disable bit. */
2000#define X86_PDE_PCD RT_BIT_32(4)
2001/** Bit 5 - A - Access bit. */
2002#define X86_PDE_A RT_BIT_32(5)
2003/** Bit 7 - PS - Page size attribute.
2004 * Clear mean 4KB pages, set means large pages (2/4MB). */
2005#define X86_PDE_PS RT_BIT_32(7)
2006/** Bits 9-11 - - Available for use to system software. */
2007#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2008/** Bits 12-31 - - Physical Page number of the next level. */
2009#define X86_PDE_PG_MASK ( 0xfffff000 )
2010
2011/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2012#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2013/** Bits 63 - NX - PAE/LM - No execution flag. */
2014#define X86_PDE_PAE_NX RT_BIT_64(63)
2015/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2016#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2017/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2018#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2019/** Bit 7 - - LM - MBZ bits when NX is active. */
2020#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2021/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2022#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2023
2024/**
2025 * Page directory entry.
2026 */
2027typedef struct X86PDEBITS
2028{
2029 /** Flags whether(=1) or not the page is present. */
2030 uint32_t u1Present : 1;
2031 /** Read(=0) / Write(=1) flag. */
2032 uint32_t u1Write : 1;
2033 /** User(=1) / Supervisor (=0) flag. */
2034 uint32_t u1User : 1;
2035 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2036 uint32_t u1WriteThru : 1;
2037 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2038 uint32_t u1CacheDisable : 1;
2039 /** Accessed flag.
2040 * Indicates that the page has been read or written to. */
2041 uint32_t u1Accessed : 1;
2042 /** Reserved / Ignored (dirty bit). */
2043 uint32_t u1Reserved0 : 1;
2044 /** Size bit if PSE is enabled - in any event it's 0. */
2045 uint32_t u1Size : 1;
2046 /** Reserved / Ignored (global bit). */
2047 uint32_t u1Reserved1 : 1;
2048 /** Available for use to system software. */
2049 uint32_t u3Available : 3;
2050 /** Physical Page number of the next level. */
2051 uint32_t u20PageNo : 20;
2052} X86PDEBITS;
2053#ifndef VBOX_FOR_DTRACE_LIB
2054AssertCompileSize(X86PDEBITS, 4);
2055#endif
2056/** Pointer to a page directory entry. */
2057typedef X86PDEBITS *PX86PDEBITS;
2058/** Pointer to a const page directory entry. */
2059typedef const X86PDEBITS *PCX86PDEBITS;
2060
2061
2062/**
2063 * PAE page directory entry.
2064 */
2065typedef struct X86PDEPAEBITS
2066{
2067 /** Flags whether(=1) or not the page is present. */
2068 uint32_t u1Present : 1;
2069 /** Read(=0) / Write(=1) flag. */
2070 uint32_t u1Write : 1;
2071 /** User(=1) / Supervisor (=0) flag. */
2072 uint32_t u1User : 1;
2073 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2074 uint32_t u1WriteThru : 1;
2075 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2076 uint32_t u1CacheDisable : 1;
2077 /** Accessed flag.
2078 * Indicates that the page has been read or written to. */
2079 uint32_t u1Accessed : 1;
2080 /** Reserved / Ignored (dirty bit). */
2081 uint32_t u1Reserved0 : 1;
2082 /** Size bit if PSE is enabled - in any event it's 0. */
2083 uint32_t u1Size : 1;
2084 /** Reserved / Ignored (global bit). / */
2085 uint32_t u1Reserved1 : 1;
2086 /** Available for use to system software. */
2087 uint32_t u3Available : 3;
2088 /** Physical Page number of the next level - Low Part. Don't use! */
2089 uint32_t u20PageNoLow : 20;
2090 /** Physical Page number of the next level - High Part. Don't use! */
2091 uint32_t u20PageNoHigh : 20;
2092 /** MBZ bits */
2093 uint32_t u11Reserved : 11;
2094 /** No Execute flag. */
2095 uint32_t u1NoExecute : 1;
2096} X86PDEPAEBITS;
2097#ifndef VBOX_FOR_DTRACE_LIB
2098AssertCompileSize(X86PDEPAEBITS, 8);
2099#endif
2100/** Pointer to a page directory entry. */
2101typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2102/** Pointer to a const page directory entry. */
2103typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2104
2105/** @} */
2106
2107
2108/** @name 2/4MB Page Directory Entry
2109 * @{
2110 */
2111/** Bit 0 - P - Present bit. */
2112#define X86_PDE4M_P RT_BIT_32(0)
2113/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2114#define X86_PDE4M_RW RT_BIT_32(1)
2115/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2116#define X86_PDE4M_US RT_BIT_32(2)
2117/** Bit 3 - PWT - Page level write thru bit. */
2118#define X86_PDE4M_PWT RT_BIT_32(3)
2119/** Bit 4 - PCD - Page level cache disable bit. */
2120#define X86_PDE4M_PCD RT_BIT_32(4)
2121/** Bit 5 - A - Access bit. */
2122#define X86_PDE4M_A RT_BIT_32(5)
2123/** Bit 6 - D - Dirty bit. */
2124#define X86_PDE4M_D RT_BIT_32(6)
2125/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2126#define X86_PDE4M_PS RT_BIT_32(7)
2127/** Bit 8 - G - Global flag. */
2128#define X86_PDE4M_G RT_BIT_32(8)
2129/** Bits 9-11 - AVL - Available for use to system software. */
2130#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2131/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2132#define X86_PDE4M_PAT RT_BIT_32(12)
2133/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2134#define X86_PDE4M_PAT_SHIFT (12 - 7)
2135/** Bits 22-31 - - Physical Page number. */
2136#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2137/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2138#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2139/** The number of bits to the high part of the page number. */
2140#define X86_PDE4M_PG_HIGH_SHIFT 19
2141/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2142#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2143
2144/** Bits 21-51 - - PAE/LM - Physical Page number.
2145 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2146#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2147/** Bits 63 - NX - PAE/LM - No execution flag. */
2148#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2149/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2150#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2151/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2152#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2153/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2154#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2155/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2156#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2157
2158/**
2159 * 4MB page directory entry.
2160 */
2161typedef struct X86PDE4MBITS
2162{
2163 /** Flags whether(=1) or not the page is present. */
2164 uint32_t u1Present : 1;
2165 /** Read(=0) / Write(=1) flag. */
2166 uint32_t u1Write : 1;
2167 /** User(=1) / Supervisor (=0) flag. */
2168 uint32_t u1User : 1;
2169 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2170 uint32_t u1WriteThru : 1;
2171 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2172 uint32_t u1CacheDisable : 1;
2173 /** Accessed flag.
2174 * Indicates that the page have been read or written to. */
2175 uint32_t u1Accessed : 1;
2176 /** Dirty flag.
2177 * Indicates that the page has been written to. */
2178 uint32_t u1Dirty : 1;
2179 /** Page size flag - always 1 for 4MB entries. */
2180 uint32_t u1Size : 1;
2181 /** Global flag. */
2182 uint32_t u1Global : 1;
2183 /** Available for use to system software. */
2184 uint32_t u3Available : 3;
2185 /** Reserved / If PAT enabled, bit 2 of the index. */
2186 uint32_t u1PAT : 1;
2187 /** Bits 32-39 of the page number on AMD64.
2188 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2189 uint32_t u8PageNoHigh : 8;
2190 /** Reserved. */
2191 uint32_t u1Reserved : 1;
2192 /** Physical Page number of the page. */
2193 uint32_t u10PageNo : 10;
2194} X86PDE4MBITS;
2195#ifndef VBOX_FOR_DTRACE_LIB
2196AssertCompileSize(X86PDE4MBITS, 4);
2197#endif
2198/** Pointer to a page table entry. */
2199typedef X86PDE4MBITS *PX86PDE4MBITS;
2200/** Pointer to a const page table entry. */
2201typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2202
2203
2204/**
2205 * 2MB PAE page directory entry.
2206 */
2207typedef struct X86PDE2MPAEBITS
2208{
2209 /** Flags whether(=1) or not the page is present. */
2210 uint32_t u1Present : 1;
2211 /** Read(=0) / Write(=1) flag. */
2212 uint32_t u1Write : 1;
2213 /** User(=1) / Supervisor(=0) flag. */
2214 uint32_t u1User : 1;
2215 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2216 uint32_t u1WriteThru : 1;
2217 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2218 uint32_t u1CacheDisable : 1;
2219 /** Accessed flag.
2220 * Indicates that the page have been read or written to. */
2221 uint32_t u1Accessed : 1;
2222 /** Dirty flag.
2223 * Indicates that the page has been written to. */
2224 uint32_t u1Dirty : 1;
2225 /** Page size flag - always 1 for 2MB entries. */
2226 uint32_t u1Size : 1;
2227 /** Global flag. */
2228 uint32_t u1Global : 1;
2229 /** Available for use to system software. */
2230 uint32_t u3Available : 3;
2231 /** Reserved / If PAT enabled, bit 2 of the index. */
2232 uint32_t u1PAT : 1;
2233 /** Reserved. */
2234 uint32_t u9Reserved : 9;
2235 /** Physical Page number of the next level - Low part. Don't use! */
2236 uint32_t u10PageNoLow : 10;
2237 /** Physical Page number of the next level - High part. Don't use! */
2238 uint32_t u20PageNoHigh : 20;
2239 /** MBZ bits */
2240 uint32_t u11Reserved : 11;
2241 /** No Execute flag. */
2242 uint32_t u1NoExecute : 1;
2243} X86PDE2MPAEBITS;
2244#ifndef VBOX_FOR_DTRACE_LIB
2245AssertCompileSize(X86PDE2MPAEBITS, 8);
2246#endif
2247/** Pointer to a 2MB PAE page table entry. */
2248typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2249/** Pointer to a 2MB PAE page table entry. */
2250typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2251
2252/** @} */
2253
2254/**
2255 * Page directory entry.
2256 */
2257typedef union X86PDE
2258{
2259 /** Unsigned integer view. */
2260 X86PGUINT u;
2261 /** Normal view. */
2262 X86PDEBITS n;
2263 /** 4MB view (big). */
2264 X86PDE4MBITS b;
2265 /** 8 bit unsigned integer view. */
2266 uint8_t au8[4];
2267 /** 16 bit unsigned integer view. */
2268 uint16_t au16[2];
2269 /** 32 bit unsigned integer view. */
2270 uint32_t au32[1];
2271} X86PDE;
2272#ifndef VBOX_FOR_DTRACE_LIB
2273AssertCompileSize(X86PDE, 4);
2274#endif
2275/** Pointer to a page directory entry. */
2276typedef X86PDE *PX86PDE;
2277/** Pointer to a const page directory entry. */
2278typedef const X86PDE *PCX86PDE;
2279
2280/**
2281 * PAE page directory entry.
2282 */
2283typedef union X86PDEPAE
2284{
2285 /** Unsigned integer view. */
2286 X86PGPAEUINT u;
2287 /** Normal view. */
2288 X86PDEPAEBITS n;
2289 /** 2MB page view (big). */
2290 X86PDE2MPAEBITS b;
2291 /** 8 bit unsigned integer view. */
2292 uint8_t au8[8];
2293 /** 16 bit unsigned integer view. */
2294 uint16_t au16[4];
2295 /** 32 bit unsigned integer view. */
2296 uint32_t au32[2];
2297} X86PDEPAE;
2298#ifndef VBOX_FOR_DTRACE_LIB
2299AssertCompileSize(X86PDEPAE, 8);
2300#endif
2301/** Pointer to a page directory entry. */
2302typedef X86PDEPAE *PX86PDEPAE;
2303/** Pointer to a const page directory entry. */
2304typedef const X86PDEPAE *PCX86PDEPAE;
2305
2306/**
2307 * Page directory.
2308 */
2309typedef struct X86PD
2310{
2311 /** PDE Array. */
2312 X86PDE a[X86_PG_ENTRIES];
2313} X86PD;
2314#ifndef VBOX_FOR_DTRACE_LIB
2315AssertCompileSize(X86PD, 4096);
2316#endif
2317/** Pointer to a page directory. */
2318typedef X86PD *PX86PD;
2319/** Pointer to a const page directory. */
2320typedef const X86PD *PCX86PD;
2321
2322/** The page shift to get the PD index. */
2323#define X86_PD_SHIFT 22
2324/** The PD index mask (apply to a shifted page address). */
2325#define X86_PD_MASK 0x3ff
2326
2327
2328/**
2329 * PAE page directory.
2330 */
2331typedef struct X86PDPAE
2332{
2333 /** PDE Array. */
2334 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2335} X86PDPAE;
2336#ifndef VBOX_FOR_DTRACE_LIB
2337AssertCompileSize(X86PDPAE, 4096);
2338#endif
2339/** Pointer to a PAE page directory. */
2340typedef X86PDPAE *PX86PDPAE;
2341/** Pointer to a const PAE page directory. */
2342typedef const X86PDPAE *PCX86PDPAE;
2343
2344/** The page shift to get the PAE PD index. */
2345#define X86_PD_PAE_SHIFT 21
2346/** The PAE PD index mask (apply to a shifted page address). */
2347#define X86_PD_PAE_MASK 0x1ff
2348
2349
2350/** @name Page Directory Pointer Table Entry (PAE)
2351 * @{
2352 */
2353/** Bit 0 - P - Present bit. */
2354#define X86_PDPE_P RT_BIT_32(0)
2355/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2356#define X86_PDPE_RW RT_BIT_32(1)
2357/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2358#define X86_PDPE_US RT_BIT_32(2)
2359/** Bit 3 - PWT - Page level write thru bit. */
2360#define X86_PDPE_PWT RT_BIT_32(3)
2361/** Bit 4 - PCD - Page level cache disable bit. */
2362#define X86_PDPE_PCD RT_BIT_32(4)
2363/** Bit 5 - A - Access bit. Long Mode only. */
2364#define X86_PDPE_A RT_BIT_32(5)
2365/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2366#define X86_PDPE_LM_PS RT_BIT_32(7)
2367/** Bits 9-11 - - Available for use to system software. */
2368#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2369/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2370#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2371/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2372#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2373/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2374#define X86_PDPE_LM_NX RT_BIT_64(63)
2375/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2376#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2377/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2378#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2379/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2380#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2381/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2382#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2383
2384
2385/**
2386 * Page directory pointer table entry.
2387 */
2388typedef struct X86PDPEBITS
2389{
2390 /** Flags whether(=1) or not the page is present. */
2391 uint32_t u1Present : 1;
2392 /** Chunk of reserved bits. */
2393 uint32_t u2Reserved : 2;
2394 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2395 uint32_t u1WriteThru : 1;
2396 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2397 uint32_t u1CacheDisable : 1;
2398 /** Chunk of reserved bits. */
2399 uint32_t u4Reserved : 4;
2400 /** Available for use to system software. */
2401 uint32_t u3Available : 3;
2402 /** Physical Page number of the next level - Low Part. Don't use! */
2403 uint32_t u20PageNoLow : 20;
2404 /** Physical Page number of the next level - High Part. Don't use! */
2405 uint32_t u20PageNoHigh : 20;
2406 /** MBZ bits */
2407 uint32_t u12Reserved : 12;
2408} X86PDPEBITS;
2409#ifndef VBOX_FOR_DTRACE_LIB
2410AssertCompileSize(X86PDPEBITS, 8);
2411#endif
2412/** Pointer to a page directory pointer table entry. */
2413typedef X86PDPEBITS *PX86PTPEBITS;
2414/** Pointer to a const page directory pointer table entry. */
2415typedef const X86PDPEBITS *PCX86PTPEBITS;
2416
2417/**
2418 * Page directory pointer table entry. AMD64 version
2419 */
2420typedef struct X86PDPEAMD64BITS
2421{
2422 /** Flags whether(=1) or not the page is present. */
2423 uint32_t u1Present : 1;
2424 /** Read(=0) / Write(=1) flag. */
2425 uint32_t u1Write : 1;
2426 /** User(=1) / Supervisor (=0) flag. */
2427 uint32_t u1User : 1;
2428 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2429 uint32_t u1WriteThru : 1;
2430 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2431 uint32_t u1CacheDisable : 1;
2432 /** Accessed flag.
2433 * Indicates that the page have been read or written to. */
2434 uint32_t u1Accessed : 1;
2435 /** Chunk of reserved bits. */
2436 uint32_t u3Reserved : 3;
2437 /** Available for use to system software. */
2438 uint32_t u3Available : 3;
2439 /** Physical Page number of the next level - Low Part. Don't use! */
2440 uint32_t u20PageNoLow : 20;
2441 /** Physical Page number of the next level - High Part. Don't use! */
2442 uint32_t u20PageNoHigh : 20;
2443 /** MBZ bits */
2444 uint32_t u11Reserved : 11;
2445 /** No Execute flag. */
2446 uint32_t u1NoExecute : 1;
2447} X86PDPEAMD64BITS;
2448#ifndef VBOX_FOR_DTRACE_LIB
2449AssertCompileSize(X86PDPEAMD64BITS, 8);
2450#endif
2451/** Pointer to a page directory pointer table entry. */
2452typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2453/** Pointer to a const page directory pointer table entry. */
2454typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2455
2456/**
2457 * Page directory pointer table entry for 1GB page. (AMD64 only)
2458 */
2459typedef struct X86PDPE1GB
2460{
2461 /** 0: Flags whether(=1) or not the page is present. */
2462 uint32_t u1Present : 1;
2463 /** 1: Read(=0) / Write(=1) flag. */
2464 uint32_t u1Write : 1;
2465 /** 2: User(=1) / Supervisor (=0) flag. */
2466 uint32_t u1User : 1;
2467 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2468 uint32_t u1WriteThru : 1;
2469 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2470 uint32_t u1CacheDisable : 1;
2471 /** 5: Accessed flag.
2472 * Indicates that the page have been read or written to. */
2473 uint32_t u1Accessed : 1;
2474 /** 6: Dirty flag for 1GB pages. */
2475 uint32_t u1Dirty : 1;
2476 /** 7: Indicates 1GB page if set. */
2477 uint32_t u1Size : 1;
2478 /** 8: Global 1GB page. */
2479 uint32_t u1Global: 1;
2480 /** 9-11: Available for use to system software. */
2481 uint32_t u3Available : 3;
2482 /** 12: PAT bit for 1GB page. */
2483 uint32_t u1PAT : 1;
2484 /** 13-29: MBZ bits. */
2485 uint32_t u17Reserved : 17;
2486 /** 30-31: Physical page number - Low Part. Don't use! */
2487 uint32_t u2PageNoLow : 2;
2488 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2489 uint32_t u20PageNoHigh : 20;
2490 /** 52-62: MBZ bits */
2491 uint32_t u11Reserved : 11;
2492 /** 63: No Execute flag. */
2493 uint32_t u1NoExecute : 1;
2494} X86PDPE1GB;
2495#ifndef VBOX_FOR_DTRACE_LIB
2496AssertCompileSize(X86PDPE1GB, 8);
2497#endif
2498/** Pointer to a page directory pointer table entry for a 1GB page. */
2499typedef X86PDPE1GB *PX86PDPE1GB;
2500/** Pointer to a const page directory pointer table entry for a 1GB page. */
2501typedef const X86PDPE1GB *PCX86PDPE1GB;
2502
2503/**
2504 * Page directory pointer table entry.
2505 */
2506typedef union X86PDPE
2507{
2508 /** Unsigned integer view. */
2509 X86PGPAEUINT u;
2510 /** Normal view. */
2511 X86PDPEBITS n;
2512 /** AMD64 view. */
2513 X86PDPEAMD64BITS lm;
2514 /** AMD64 big view. */
2515 X86PDPE1GB b;
2516 /** 8 bit unsigned integer view. */
2517 uint8_t au8[8];
2518 /** 16 bit unsigned integer view. */
2519 uint16_t au16[4];
2520 /** 32 bit unsigned integer view. */
2521 uint32_t au32[2];
2522} X86PDPE;
2523#ifndef VBOX_FOR_DTRACE_LIB
2524AssertCompileSize(X86PDPE, 8);
2525#endif
2526/** Pointer to a page directory pointer table entry. */
2527typedef X86PDPE *PX86PDPE;
2528/** Pointer to a const page directory pointer table entry. */
2529typedef const X86PDPE *PCX86PDPE;
2530
2531
2532/**
2533 * Page directory pointer table.
2534 */
2535typedef struct X86PDPT
2536{
2537 /** PDE Array. */
2538 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2539} X86PDPT;
2540#ifndef VBOX_FOR_DTRACE_LIB
2541AssertCompileSize(X86PDPT, 4096);
2542#endif
2543/** Pointer to a page directory pointer table. */
2544typedef X86PDPT *PX86PDPT;
2545/** Pointer to a const page directory pointer table. */
2546typedef const X86PDPT *PCX86PDPT;
2547
2548/** The page shift to get the PDPT index. */
2549#define X86_PDPT_SHIFT 30
2550/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2551#define X86_PDPT_MASK_PAE 0x3
2552/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2553#define X86_PDPT_MASK_AMD64 0x1ff
2554
2555/** @} */
2556
2557
2558/** @name Page Map Level-4 Entry (Long Mode PAE)
2559 * @{
2560 */
2561/** Bit 0 - P - Present bit. */
2562#define X86_PML4E_P RT_BIT_32(0)
2563/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2564#define X86_PML4E_RW RT_BIT_32(1)
2565/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2566#define X86_PML4E_US RT_BIT_32(2)
2567/** Bit 3 - PWT - Page level write thru bit. */
2568#define X86_PML4E_PWT RT_BIT_32(3)
2569/** Bit 4 - PCD - Page level cache disable bit. */
2570#define X86_PML4E_PCD RT_BIT_32(4)
2571/** Bit 5 - A - Access bit. */
2572#define X86_PML4E_A RT_BIT_32(5)
2573/** Bits 9-11 - - Available for use to system software. */
2574#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2575/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2576#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2577/** Bits 8, 7 - - MBZ bits when NX is active. */
2578#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2579/** Bits 63, 7 - - MBZ bits when no NX. */
2580#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2581/** Bits 63 - NX - PAE - No execution flag. */
2582#define X86_PML4E_NX RT_BIT_64(63)
2583
2584/**
2585 * Page Map Level-4 Entry
2586 */
2587typedef struct X86PML4EBITS
2588{
2589 /** Flags whether(=1) or not the page is present. */
2590 uint32_t u1Present : 1;
2591 /** Read(=0) / Write(=1) flag. */
2592 uint32_t u1Write : 1;
2593 /** User(=1) / Supervisor (=0) flag. */
2594 uint32_t u1User : 1;
2595 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2596 uint32_t u1WriteThru : 1;
2597 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2598 uint32_t u1CacheDisable : 1;
2599 /** Accessed flag.
2600 * Indicates that the page have been read or written to. */
2601 uint32_t u1Accessed : 1;
2602 /** Chunk of reserved bits. */
2603 uint32_t u3Reserved : 3;
2604 /** Available for use to system software. */
2605 uint32_t u3Available : 3;
2606 /** Physical Page number of the next level - Low Part. Don't use! */
2607 uint32_t u20PageNoLow : 20;
2608 /** Physical Page number of the next level - High Part. Don't use! */
2609 uint32_t u20PageNoHigh : 20;
2610 /** MBZ bits */
2611 uint32_t u11Reserved : 11;
2612 /** No Execute flag. */
2613 uint32_t u1NoExecute : 1;
2614} X86PML4EBITS;
2615#ifndef VBOX_FOR_DTRACE_LIB
2616AssertCompileSize(X86PML4EBITS, 8);
2617#endif
2618/** Pointer to a page map level-4 entry. */
2619typedef X86PML4EBITS *PX86PML4EBITS;
2620/** Pointer to a const page map level-4 entry. */
2621typedef const X86PML4EBITS *PCX86PML4EBITS;
2622
2623/**
2624 * Page Map Level-4 Entry.
2625 */
2626typedef union X86PML4E
2627{
2628 /** Unsigned integer view. */
2629 X86PGPAEUINT u;
2630 /** Normal view. */
2631 X86PML4EBITS n;
2632 /** 8 bit unsigned integer view. */
2633 uint8_t au8[8];
2634 /** 16 bit unsigned integer view. */
2635 uint16_t au16[4];
2636 /** 32 bit unsigned integer view. */
2637 uint32_t au32[2];
2638} X86PML4E;
2639#ifndef VBOX_FOR_DTRACE_LIB
2640AssertCompileSize(X86PML4E, 8);
2641#endif
2642/** Pointer to a page map level-4 entry. */
2643typedef X86PML4E *PX86PML4E;
2644/** Pointer to a const page map level-4 entry. */
2645typedef const X86PML4E *PCX86PML4E;
2646
2647
2648/**
2649 * Page Map Level-4.
2650 */
2651typedef struct X86PML4
2652{
2653 /** PDE Array. */
2654 X86PML4E a[X86_PG_PAE_ENTRIES];
2655} X86PML4;
2656#ifndef VBOX_FOR_DTRACE_LIB
2657AssertCompileSize(X86PML4, 4096);
2658#endif
2659/** Pointer to a page map level-4. */
2660typedef X86PML4 *PX86PML4;
2661/** Pointer to a const page map level-4. */
2662typedef const X86PML4 *PCX86PML4;
2663
2664/** The page shift to get the PML4 index. */
2665#define X86_PML4_SHIFT 39
2666/** The PML4 index mask (apply to a shifted page address). */
2667#define X86_PML4_MASK 0x1ff
2668
2669/** @} */
2670
2671/** @} */
2672
2673/**
2674 * Intel PCID invalidation types.
2675 */
2676/** Individual address invalidation. */
2677#define X86_INVPCID_TYPE_INDV_ADDR 0
2678/** Single-context invalidation. */
2679#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2680/** All-context including globals invalidation. */
2681#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2682/** All-context excluding globals invalidation. */
2683#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2684/** The maximum valid invalidation type value. */
2685#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2686
2687/**
2688 * 32-bit protected mode FSTENV image.
2689 */
2690typedef struct X86FSTENV32P
2691{
2692 uint16_t FCW;
2693 uint16_t padding1;
2694 uint16_t FSW;
2695 uint16_t padding2;
2696 uint16_t FTW;
2697 uint16_t padding3;
2698 uint32_t FPUIP;
2699 uint16_t FPUCS;
2700 uint16_t FOP;
2701 uint32_t FPUDP;
2702 uint16_t FPUDS;
2703 uint16_t padding4;
2704} X86FSTENV32P;
2705/** Pointer to a 32-bit protected mode FSTENV image. */
2706typedef X86FSTENV32P *PX86FSTENV32P;
2707/** Pointer to a const 32-bit protected mode FSTENV image. */
2708typedef X86FSTENV32P const *PCX86FSTENV32P;
2709
2710
2711/**
2712 * 80-bit MMX/FPU register type.
2713 */
2714typedef struct X86FPUMMX
2715{
2716 uint8_t reg[10];
2717} X86FPUMMX;
2718#ifndef VBOX_FOR_DTRACE_LIB
2719AssertCompileSize(X86FPUMMX, 10);
2720#endif
2721/** Pointer to a 80-bit MMX/FPU register type. */
2722typedef X86FPUMMX *PX86FPUMMX;
2723/** Pointer to a const 80-bit MMX/FPU register type. */
2724typedef const X86FPUMMX *PCX86FPUMMX;
2725
2726/** FPU (x87) register. */
2727typedef union X86FPUREG
2728{
2729 /** MMX view. */
2730 uint64_t mmx;
2731 /** FPU view - todo. */
2732 X86FPUMMX fpu;
2733 /** Extended precision floating point view. */
2734 RTFLOAT80U r80;
2735 /** Extended precision floating point view v2 */
2736 RTFLOAT80U2 r80Ex;
2737 /** 8-bit view. */
2738 uint8_t au8[16];
2739 /** 16-bit view. */
2740 uint16_t au16[8];
2741 /** 32-bit view. */
2742 uint32_t au32[4];
2743 /** 64-bit view. */
2744 uint64_t au64[2];
2745 /** 128-bit view. (yeah, very helpful) */
2746 uint128_t au128[1];
2747} X86FPUREG;
2748#ifndef VBOX_FOR_DTRACE_LIB
2749AssertCompileSize(X86FPUREG, 16);
2750#endif
2751/** Pointer to a FPU register. */
2752typedef X86FPUREG *PX86FPUREG;
2753/** Pointer to a const FPU register. */
2754typedef X86FPUREG const *PCX86FPUREG;
2755
2756/**
2757 * XMM register union.
2758 */
2759typedef union X86XMMREG
2760{
2761 /** XMM Register view. */
2762 uint128_t xmm;
2763 /** 8-bit view. */
2764 uint8_t au8[16];
2765 /** 16-bit view. */
2766 uint16_t au16[8];
2767 /** 32-bit view. */
2768 uint32_t au32[4];
2769 /** 64-bit view. */
2770 uint64_t au64[2];
2771 /** 128-bit view. (yeah, very helpful) */
2772 uint128_t au128[1];
2773 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2774 RTUINT128U uXmm;
2775} X86XMMREG;
2776#ifndef VBOX_FOR_DTRACE_LIB
2777AssertCompileSize(X86XMMREG, 16);
2778#endif
2779/** Pointer to an XMM register state. */
2780typedef X86XMMREG *PX86XMMREG;
2781/** Pointer to a const XMM register state. */
2782typedef X86XMMREG const *PCX86XMMREG;
2783
2784/**
2785 * YMM register union.
2786 */
2787typedef union X86YMMREG
2788{
2789 /** 8-bit view. */
2790 uint8_t au8[32];
2791 /** 16-bit view. */
2792 uint16_t au16[16];
2793 /** 32-bit view. */
2794 uint32_t au32[8];
2795 /** 64-bit view. */
2796 uint64_t au64[4];
2797 /** 128-bit view. (yeah, very helpful) */
2798 uint128_t au128[2];
2799 /** XMM sub register view. */
2800 X86XMMREG aXmm[2];
2801} X86YMMREG;
2802#ifndef VBOX_FOR_DTRACE_LIB
2803AssertCompileSize(X86YMMREG, 32);
2804#endif
2805/** Pointer to an YMM register state. */
2806typedef X86YMMREG *PX86YMMREG;
2807/** Pointer to a const YMM register state. */
2808typedef X86YMMREG const *PCX86YMMREG;
2809
2810/**
2811 * ZMM register union.
2812 */
2813typedef union X86ZMMREG
2814{
2815 /** 8-bit view. */
2816 uint8_t au8[64];
2817 /** 16-bit view. */
2818 uint16_t au16[32];
2819 /** 32-bit view. */
2820 uint32_t au32[16];
2821 /** 64-bit view. */
2822 uint64_t au64[8];
2823 /** 128-bit view. (yeah, very helpful) */
2824 uint128_t au128[4];
2825 /** XMM sub register view. */
2826 X86XMMREG aXmm[4];
2827 /** YMM sub register view. */
2828 X86YMMREG aYmm[2];
2829} X86ZMMREG;
2830#ifndef VBOX_FOR_DTRACE_LIB
2831AssertCompileSize(X86ZMMREG, 64);
2832#endif
2833/** Pointer to an ZMM register state. */
2834typedef X86ZMMREG *PX86ZMMREG;
2835/** Pointer to a const ZMM register state. */
2836typedef X86ZMMREG const *PCX86ZMMREG;
2837
2838
2839/**
2840 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2841 * @todo verify this...
2842 */
2843#pragma pack(1)
2844typedef struct X86FPUSTATE
2845{
2846 /** 0x00 - Control word. */
2847 uint16_t FCW;
2848 /** 0x02 - Alignment word */
2849 uint16_t Dummy1;
2850 /** 0x04 - Status word. */
2851 uint16_t FSW;
2852 /** 0x06 - Alignment word */
2853 uint16_t Dummy2;
2854 /** 0x08 - Tag word */
2855 uint16_t FTW;
2856 /** 0x0a - Alignment word */
2857 uint16_t Dummy3;
2858
2859 /** 0x0c - Instruction pointer. */
2860 uint32_t FPUIP;
2861 /** 0x10 - Code selector. */
2862 uint16_t CS;
2863 /** 0x12 - Opcode. */
2864 uint16_t FOP;
2865 /** 0x14 - FOO. */
2866 uint32_t FPUOO;
2867 /** 0x18 - FOS. */
2868 uint32_t FPUOS;
2869 /** 0x1c - FPU register. */
2870 X86FPUREG regs[8];
2871} X86FPUSTATE;
2872#pragma pack()
2873/** Pointer to a FPU state. */
2874typedef X86FPUSTATE *PX86FPUSTATE;
2875/** Pointer to a const FPU state. */
2876typedef const X86FPUSTATE *PCX86FPUSTATE;
2877
2878/**
2879 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2880 */
2881#pragma pack(1)
2882typedef struct X86FXSTATE
2883{
2884 /** 0x00 - Control word. */
2885 uint16_t FCW;
2886 /** 0x02 - Status word. */
2887 uint16_t FSW;
2888 /** 0x04 - Tag word. (The upper byte is always zero.) */
2889 uint16_t FTW;
2890 /** 0x06 - Opcode. */
2891 uint16_t FOP;
2892 /** 0x08 - Instruction pointer. */
2893 uint32_t FPUIP;
2894 /** 0x0c - Code selector. */
2895 uint16_t CS;
2896 uint16_t Rsrvd1;
2897 /** 0x10 - Data pointer. */
2898 uint32_t FPUDP;
2899 /** 0x14 - Data segment */
2900 uint16_t DS;
2901 /** 0x16 */
2902 uint16_t Rsrvd2;
2903 /** 0x18 */
2904 uint32_t MXCSR;
2905 /** 0x1c */
2906 uint32_t MXCSR_MASK;
2907 /** 0x20 - FPU registers. */
2908 X86FPUREG aRegs[8];
2909 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2910 X86XMMREG aXMM[16];
2911 /* - offset 416 - */
2912 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2913 /* - offset 464 - Software usable reserved bits. */
2914 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2915} X86FXSTATE;
2916#pragma pack()
2917/** Pointer to a FPU Extended state. */
2918typedef X86FXSTATE *PX86FXSTATE;
2919/** Pointer to a const FPU Extended state. */
2920typedef const X86FXSTATE *PCX86FXSTATE;
2921
2922/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2923 * magic. Don't forget to update x86.mac if you change this! */
2924#define X86_OFF_FXSTATE_RSVD 0x1d0
2925/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2926 * forget to update x86.mac if you change this!
2927 * @todo r=bird: This has nothing what-so-ever to do here.... */
2928#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2929#ifndef VBOX_FOR_DTRACE_LIB
2930AssertCompileSize(X86FXSTATE, 512);
2931AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2932#endif
2933
2934/** @name FPU status word flags.
2935 * @{ */
2936/** Exception Flag: Invalid operation. */
2937#define X86_FSW_IE RT_BIT_32(0)
2938/** Exception Flag: Denormalized operand. */
2939#define X86_FSW_DE RT_BIT_32(1)
2940/** Exception Flag: Zero divide. */
2941#define X86_FSW_ZE RT_BIT_32(2)
2942/** Exception Flag: Overflow. */
2943#define X86_FSW_OE RT_BIT_32(3)
2944/** Exception Flag: Underflow. */
2945#define X86_FSW_UE RT_BIT_32(4)
2946/** Exception Flag: Precision. */
2947#define X86_FSW_PE RT_BIT_32(5)
2948/** Stack fault. */
2949#define X86_FSW_SF RT_BIT_32(6)
2950/** Error summary status. */
2951#define X86_FSW_ES RT_BIT_32(7)
2952/** Mask of exceptions flags, excluding the summary bit. */
2953#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2954/** Mask of exceptions flags, including the summary bit. */
2955#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2956/** Condition code 0. */
2957#define X86_FSW_C0 RT_BIT_32(8)
2958/** Condition code 1. */
2959#define X86_FSW_C1 RT_BIT_32(9)
2960/** Condition code 2. */
2961#define X86_FSW_C2 RT_BIT_32(10)
2962/** Top of the stack mask. */
2963#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2964/** TOP shift value. */
2965#define X86_FSW_TOP_SHIFT 11
2966/** Mask for getting TOP value after shifting it right. */
2967#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2968/** Get the TOP value. */
2969#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2970/** Condition code 3. */
2971#define X86_FSW_C3 RT_BIT_32(14)
2972/** Mask of exceptions flags, including the summary bit. */
2973#define X86_FSW_C_MASK UINT16_C(0x4700)
2974/** FPU busy. */
2975#define X86_FSW_B RT_BIT_32(15)
2976/** @} */
2977
2978
2979/** @name FPU control word flags.
2980 * @{ */
2981/** Exception Mask: Invalid operation. */
2982#define X86_FCW_IM RT_BIT_32(0)
2983/** Exception Mask: Denormalized operand. */
2984#define X86_FCW_DM RT_BIT_32(1)
2985/** Exception Mask: Zero divide. */
2986#define X86_FCW_ZM RT_BIT_32(2)
2987/** Exception Mask: Overflow. */
2988#define X86_FCW_OM RT_BIT_32(3)
2989/** Exception Mask: Underflow. */
2990#define X86_FCW_UM RT_BIT_32(4)
2991/** Exception Mask: Precision. */
2992#define X86_FCW_PM RT_BIT_32(5)
2993/** Mask all exceptions, the value typically loaded (by for instance fninit).
2994 * @remarks This includes reserved bit 6. */
2995#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2996/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2997#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2998/** Precision control mask. */
2999#define X86_FCW_PC_MASK UINT16_C(0x0300)
3000/** Precision control: 24-bit. */
3001#define X86_FCW_PC_24 UINT16_C(0x0000)
3002/** Precision control: Reserved. */
3003#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3004/** Precision control: 53-bit. */
3005#define X86_FCW_PC_53 UINT16_C(0x0200)
3006/** Precision control: 64-bit. */
3007#define X86_FCW_PC_64 UINT16_C(0x0300)
3008/** Rounding control mask. */
3009#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3010/** Rounding control: To nearest. */
3011#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3012/** Rounding control: Down. */
3013#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3014/** Rounding control: Up. */
3015#define X86_FCW_RC_UP UINT16_C(0x0800)
3016/** Rounding control: Towards zero. */
3017#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3018/** Bits which should be zero, apparently. */
3019#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3020/** @} */
3021
3022/** @name SSE MXCSR
3023 * @{ */
3024/** Exception Flag: Invalid operation. */
3025#define X86_MXCSR_IE RT_BIT_32(0)
3026/** Exception Flag: Denormalized operand. */
3027#define X86_MXCSR_DE RT_BIT_32(1)
3028/** Exception Flag: Zero divide. */
3029#define X86_MXCSR_ZE RT_BIT_32(2)
3030/** Exception Flag: Overflow. */
3031#define X86_MXCSR_OE RT_BIT_32(3)
3032/** Exception Flag: Underflow. */
3033#define X86_MXCSR_UE RT_BIT_32(4)
3034/** Exception Flag: Precision. */
3035#define X86_MXCSR_PE RT_BIT_32(5)
3036
3037/** Denormals are zero. */
3038#define X86_MXCSR_DAZ RT_BIT_32(6)
3039
3040/** Exception Mask: Invalid operation. */
3041#define X86_MXCSR_IM RT_BIT_32(7)
3042/** Exception Mask: Denormalized operand. */
3043#define X86_MXCSR_DM RT_BIT_32(8)
3044/** Exception Mask: Zero divide. */
3045#define X86_MXCSR_ZM RT_BIT_32(9)
3046/** Exception Mask: Overflow. */
3047#define X86_MXCSR_OM RT_BIT_32(10)
3048/** Exception Mask: Underflow. */
3049#define X86_MXCSR_UM RT_BIT_32(11)
3050/** Exception Mask: Precision. */
3051#define X86_MXCSR_PM RT_BIT_32(12)
3052
3053/** Rounding control mask. */
3054#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3055/** Rounding control: To nearest. */
3056#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3057/** Rounding control: Down. */
3058#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3059/** Rounding control: Up. */
3060#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3061/** Rounding control: Towards zero. */
3062#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3063
3064/** Flush-to-zero for masked underflow. */
3065#define X86_MXCSR_FZ RT_BIT_32(15)
3066
3067/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3068#define X86_MXCSR_MM RT_BIT_32(17)
3069/** @} */
3070
3071/**
3072 * XSAVE header.
3073 */
3074typedef struct X86XSAVEHDR
3075{
3076 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3077 uint64_t bmXState;
3078 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3079 uint64_t bmXComp;
3080 /** Reserved for furture extensions, probably MBZ. */
3081 uint64_t au64Reserved[6];
3082} X86XSAVEHDR;
3083#ifndef VBOX_FOR_DTRACE_LIB
3084AssertCompileSize(X86XSAVEHDR, 64);
3085#endif
3086/** Pointer to an XSAVE header. */
3087typedef X86XSAVEHDR *PX86XSAVEHDR;
3088/** Pointer to a const XSAVE header. */
3089typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3090
3091
3092/**
3093 * The high 128-bit YMM register state (XSAVE_C_YMM).
3094 * (The lower 128-bits being in X86FXSTATE.)
3095 */
3096typedef struct X86XSAVEYMMHI
3097{
3098 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3099 X86XMMREG aYmmHi[16];
3100} X86XSAVEYMMHI;
3101#ifndef VBOX_FOR_DTRACE_LIB
3102AssertCompileSize(X86XSAVEYMMHI, 256);
3103#endif
3104/** Pointer to a high 128-bit YMM register state. */
3105typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3106/** Pointer to a const high 128-bit YMM register state. */
3107typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3108
3109/**
3110 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3111 */
3112typedef struct X86XSAVEBNDREGS
3113{
3114 /** Array of registers (BND0...BND3). */
3115 struct
3116 {
3117 /** Lower bound. */
3118 uint64_t uLowerBound;
3119 /** Upper bound. */
3120 uint64_t uUpperBound;
3121 } aRegs[4];
3122} X86XSAVEBNDREGS;
3123#ifndef VBOX_FOR_DTRACE_LIB
3124AssertCompileSize(X86XSAVEBNDREGS, 64);
3125#endif
3126/** Pointer to a MPX bound register state. */
3127typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3128/** Pointer to a const MPX bound register state. */
3129typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3130
3131/**
3132 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3133 */
3134typedef struct X86XSAVEBNDCFG
3135{
3136 uint64_t fConfig;
3137 uint64_t fStatus;
3138} X86XSAVEBNDCFG;
3139#ifndef VBOX_FOR_DTRACE_LIB
3140AssertCompileSize(X86XSAVEBNDCFG, 16);
3141#endif
3142/** Pointer to a MPX bound config and status register state. */
3143typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3144/** Pointer to a const MPX bound config and status register state. */
3145typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3146
3147/**
3148 * AVX-512 opmask state (XSAVE_C_OPMASK).
3149 */
3150typedef struct X86XSAVEOPMASK
3151{
3152 /** The K0..K7 values. */
3153 uint64_t aKRegs[8];
3154} X86XSAVEOPMASK;
3155#ifndef VBOX_FOR_DTRACE_LIB
3156AssertCompileSize(X86XSAVEOPMASK, 64);
3157#endif
3158/** Pointer to a AVX-512 opmask state. */
3159typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3160/** Pointer to a const AVX-512 opmask state. */
3161typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3162
3163/**
3164 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3165 */
3166typedef struct X86XSAVEZMMHI256
3167{
3168 /** Upper 256-bits of ZMM0-15. */
3169 X86YMMREG aHi256Regs[16];
3170} X86XSAVEZMMHI256;
3171#ifndef VBOX_FOR_DTRACE_LIB
3172AssertCompileSize(X86XSAVEZMMHI256, 512);
3173#endif
3174/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3175typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3176/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3177typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3178
3179/**
3180 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3181 */
3182typedef struct X86XSAVEZMM16HI
3183{
3184 /** ZMM16 thru ZMM31. */
3185 X86ZMMREG aRegs[16];
3186} X86XSAVEZMM16HI;
3187#ifndef VBOX_FOR_DTRACE_LIB
3188AssertCompileSize(X86XSAVEZMM16HI, 1024);
3189#endif
3190/** Pointer to a state comprising ZMM16-32. */
3191typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3192/** Pointer to a const state comprising ZMM16-32. */
3193typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3194
3195/**
3196 * AMD Light weight profiling state (XSAVE_C_LWP).
3197 *
3198 * We probably won't play with this as AMD seems to be dropping from their "zen"
3199 * processor micro architecture.
3200 */
3201typedef struct X86XSAVELWP
3202{
3203 /** Details when needed. */
3204 uint64_t auLater[128/8];
3205} X86XSAVELWP;
3206#ifndef VBOX_FOR_DTRACE_LIB
3207AssertCompileSize(X86XSAVELWP, 128);
3208#endif
3209
3210
3211/**
3212 * x86 FPU/SSE/AVX/XXXX state.
3213 *
3214 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3215 * changes to this structure.
3216 */
3217typedef struct X86XSAVEAREA
3218{
3219 /** The x87 and SSE region (or legacy region if you like). */
3220 X86FXSTATE x87;
3221 /** The XSAVE header. */
3222 X86XSAVEHDR Hdr;
3223 /** Beyond the header, there isn't really a fixed layout, but we can
3224 generally assume the YMM (AVX) register extensions are present and
3225 follows immediately. */
3226 union
3227 {
3228 /** The high 128-bit AVX registers for easy access by IEM.
3229 * @note This ASSUMES they will always be here... */
3230 X86XSAVEYMMHI YmmHi;
3231
3232 /** This is a typical layout on intel CPUs (good for debuggers). */
3233 struct
3234 {
3235 X86XSAVEYMMHI YmmHi;
3236 X86XSAVEBNDREGS BndRegs;
3237 X86XSAVEBNDCFG BndCfg;
3238 uint8_t abFudgeToMatchDocs[0xB0];
3239 X86XSAVEOPMASK Opmask;
3240 X86XSAVEZMMHI256 ZmmHi256;
3241 X86XSAVEZMM16HI Zmm16Hi;
3242 } Intel;
3243
3244 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3245 struct
3246 {
3247 X86XSAVEYMMHI YmmHi;
3248 X86XSAVELWP Lwp;
3249 } AmdBd;
3250
3251 /** To enbling static deployments that have a reasonable chance of working for
3252 * the next 3-6 CPU generations without running short on space, we allocate a
3253 * lot of extra space here, making the structure a round 8KB in size. This
3254 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3255 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3256 uint8_t ab[8192 - 512 - 64];
3257 } u;
3258} X86XSAVEAREA;
3259#ifndef VBOX_FOR_DTRACE_LIB
3260AssertCompileSize(X86XSAVEAREA, 8192);
3261AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3262AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3263AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3264AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3265AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3266AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3267AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3268AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3269#endif
3270/** Pointer to a XSAVE area. */
3271typedef X86XSAVEAREA *PX86XSAVEAREA;
3272/** Pointer to a const XSAVE area. */
3273typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3274
3275
3276/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3277 * @{ */
3278/** Bit 0 - x87 - Legacy FPU state (bit number) */
3279#define XSAVE_C_X87_BIT 0
3280/** Bit 0 - x87 - Legacy FPU state. */
3281#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3282/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3283#define XSAVE_C_SSE_BIT 1
3284/** Bit 1 - SSE - 128-bit SSE state. */
3285#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3286/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3287#define XSAVE_C_YMM_BIT 2
3288/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3289#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3290/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3291#define XSAVE_C_BNDREGS_BIT 3
3292/** Bit 3 - BNDREGS - MPX bound register state. */
3293#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3294/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3295#define XSAVE_C_BNDCSR_BIT 4
3296/** Bit 4 - BNDCSR - MPX bound config and status state. */
3297#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3298/** Bit 5 - Opmask - opmask state (bit number). */
3299#define XSAVE_C_OPMASK_BIT 5
3300/** Bit 5 - Opmask - opmask state. */
3301#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3302/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3303#define XSAVE_C_ZMM_HI256_BIT 6
3304/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3305#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3306/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3307#define XSAVE_C_ZMM_16HI_BIT 7
3308/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3309#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3310/** Bit 9 - PKRU - Protection-key state (bit number). */
3311#define XSAVE_C_PKRU_BIT 9
3312/** Bit 9 - PKRU - Protection-key state. */
3313#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3314/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3315#define XSAVE_C_LWP_BIT 62
3316/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3317#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3318/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3319#define XSAVE_C_X_BIT 63
3320/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3321#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3322/** @} */
3323
3324
3325
3326/** @name Selector Descriptor
3327 * @{
3328 */
3329
3330#ifndef VBOX_FOR_DTRACE_LIB
3331/**
3332 * Descriptor attributes (as seen by VT-x).
3333 */
3334typedef struct X86DESCATTRBITS
3335{
3336 /** 00 - Segment Type. */
3337 unsigned u4Type : 4;
3338 /** 04 - Descriptor Type. System(=0) or code/data selector */
3339 unsigned u1DescType : 1;
3340 /** 05 - Descriptor Privilege level. */
3341 unsigned u2Dpl : 2;
3342 /** 07 - Flags selector present(=1) or not. */
3343 unsigned u1Present : 1;
3344 /** 08 - Segment limit 16-19. */
3345 unsigned u4LimitHigh : 4;
3346 /** 0c - Available for system software. */
3347 unsigned u1Available : 1;
3348 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3349 unsigned u1Long : 1;
3350 /** 0e - This flags meaning depends on the segment type. Try make sense out
3351 * of the intel manual yourself. */
3352 unsigned u1DefBig : 1;
3353 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3354 * clear byte. */
3355 unsigned u1Granularity : 1;
3356 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3357 unsigned u1Unusable : 1;
3358} X86DESCATTRBITS;
3359#endif /* !VBOX_FOR_DTRACE_LIB */
3360
3361/** @name X86DESCATTR masks
3362 * @{ */
3363#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3364#define X86DESCATTR_DT UINT32_C(0x00000010)
3365#define X86DESCATTR_DPL UINT32_C(0x00000060)
3366#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3367#define X86DESCATTR_P UINT32_C(0x00000080)
3368#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3369#define X86DESCATTR_AVL UINT32_C(0x00001000)
3370#define X86DESCATTR_L UINT32_C(0x00002000)
3371#define X86DESCATTR_D UINT32_C(0x00004000)
3372#define X86DESCATTR_G UINT32_C(0x00008000)
3373#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3374/** @} */
3375
3376#pragma pack(1)
3377typedef union X86DESCATTR
3378{
3379 /** Unsigned integer view. */
3380 uint32_t u;
3381#ifndef VBOX_FOR_DTRACE_LIB
3382 /** Normal view. */
3383 X86DESCATTRBITS n;
3384#endif
3385} X86DESCATTR;
3386#pragma pack()
3387/** Pointer to descriptor attributes. */
3388typedef X86DESCATTR *PX86DESCATTR;
3389/** Pointer to const descriptor attributes. */
3390typedef const X86DESCATTR *PCX86DESCATTR;
3391
3392#ifndef VBOX_FOR_DTRACE_LIB
3393
3394/**
3395 * Generic descriptor table entry
3396 */
3397#pragma pack(1)
3398typedef struct X86DESCGENERIC
3399{
3400 /** 00 - Limit - Low word. */
3401 unsigned u16LimitLow : 16;
3402 /** 10 - Base address - low word.
3403 * Don't try set this to 24 because MSC is doing stupid things then. */
3404 unsigned u16BaseLow : 16;
3405 /** 20 - Base address - first 8 bits of high word. */
3406 unsigned u8BaseHigh1 : 8;
3407 /** 28 - Segment Type. */
3408 unsigned u4Type : 4;
3409 /** 2c - Descriptor Type. System(=0) or code/data selector */
3410 unsigned u1DescType : 1;
3411 /** 2d - Descriptor Privilege level. */
3412 unsigned u2Dpl : 2;
3413 /** 2f - Flags selector present(=1) or not. */
3414 unsigned u1Present : 1;
3415 /** 30 - Segment limit 16-19. */
3416 unsigned u4LimitHigh : 4;
3417 /** 34 - Available for system software. */
3418 unsigned u1Available : 1;
3419 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3420 unsigned u1Long : 1;
3421 /** 36 - This flags meaning depends on the segment type. Try make sense out
3422 * of the intel manual yourself. */
3423 unsigned u1DefBig : 1;
3424 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3425 * clear byte. */
3426 unsigned u1Granularity : 1;
3427 /** 38 - Base address - highest 8 bits. */
3428 unsigned u8BaseHigh2 : 8;
3429} X86DESCGENERIC;
3430#pragma pack()
3431/** Pointer to a generic descriptor entry. */
3432typedef X86DESCGENERIC *PX86DESCGENERIC;
3433/** Pointer to a const generic descriptor entry. */
3434typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3435
3436/** @name Bit offsets of X86DESCGENERIC members.
3437 * @{*/
3438#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3439#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3440#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3441#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3442#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3443#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3444#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3445#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3446#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3447#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3448#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3449#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3450#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3451/** @} */
3452
3453
3454/** @name LAR mask
3455 * @{ */
3456#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3457#define X86LAR_F_DT UINT16_C( 0x1000)
3458#define X86LAR_F_DPL UINT16_C( 0x6000)
3459#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3460#define X86LAR_F_P UINT16_C( 0x8000)
3461#define X86LAR_F_AVL UINT32_C(0x00100000)
3462#define X86LAR_F_L UINT32_C(0x00200000)
3463#define X86LAR_F_D UINT32_C(0x00400000)
3464#define X86LAR_F_G UINT32_C(0x00800000)
3465/** @} */
3466
3467
3468/**
3469 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3470 */
3471typedef struct X86DESCGATE
3472{
3473 /** 00 - Target code segment offset - Low word.
3474 * Ignored if task-gate. */
3475 unsigned u16OffsetLow : 16;
3476 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3477 * TSS selector if task-gate. */
3478 unsigned u16Sel : 16;
3479 /** 20 - Number of parameters for a call-gate.
3480 * Ignored if interrupt-, trap- or task-gate. */
3481 unsigned u5ParmCount : 5;
3482 /** 25 - Reserved / ignored. */
3483 unsigned u3Reserved : 3;
3484 /** 28 - Segment Type. */
3485 unsigned u4Type : 4;
3486 /** 2c - Descriptor Type (0 = system). */
3487 unsigned u1DescType : 1;
3488 /** 2d - Descriptor Privilege level. */
3489 unsigned u2Dpl : 2;
3490 /** 2f - Flags selector present(=1) or not. */
3491 unsigned u1Present : 1;
3492 /** 30 - Target code segment offset - High word.
3493 * Ignored if task-gate. */
3494 unsigned u16OffsetHigh : 16;
3495} X86DESCGATE;
3496/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3497typedef X86DESCGATE *PX86DESCGATE;
3498/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3499typedef const X86DESCGATE *PCX86DESCGATE;
3500
3501#endif /* VBOX_FOR_DTRACE_LIB */
3502
3503/**
3504 * Descriptor table entry.
3505 */
3506#pragma pack(1)
3507typedef union X86DESC
3508{
3509#ifndef VBOX_FOR_DTRACE_LIB
3510 /** Generic descriptor view. */
3511 X86DESCGENERIC Gen;
3512 /** Gate descriptor view. */
3513 X86DESCGATE Gate;
3514#endif
3515
3516 /** 8 bit unsigned integer view. */
3517 uint8_t au8[8];
3518 /** 16 bit unsigned integer view. */
3519 uint16_t au16[4];
3520 /** 32 bit unsigned integer view. */
3521 uint32_t au32[2];
3522 /** 64 bit unsigned integer view. */
3523 uint64_t au64[1];
3524 /** Unsigned integer view. */
3525 uint64_t u;
3526} X86DESC;
3527#ifndef VBOX_FOR_DTRACE_LIB
3528AssertCompileSize(X86DESC, 8);
3529#endif
3530#pragma pack()
3531/** Pointer to descriptor table entry. */
3532typedef X86DESC *PX86DESC;
3533/** Pointer to const descriptor table entry. */
3534typedef const X86DESC *PCX86DESC;
3535
3536/** @def X86DESC_BASE
3537 * Return the base address of a descriptor.
3538 */
3539#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3540 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3541 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3542 | ( (a_pDesc)->Gen.u16BaseLow ) )
3543
3544/** @def X86DESC_LIMIT
3545 * Return the limit of a descriptor.
3546 */
3547#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3548 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3549 | ( (a_pDesc)->Gen.u16LimitLow ) )
3550
3551/** @def X86DESC_LIMIT_G
3552 * Return the limit of a descriptor with the granularity bit taken into account.
3553 * @returns Selector limit (uint32_t).
3554 * @param a_pDesc Pointer to the descriptor.
3555 */
3556#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3557 ( (a_pDesc)->Gen.u1Granularity \
3558 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3559 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3560 )
3561
3562/** @def X86DESC_GET_HID_ATTR
3563 * Get the descriptor attributes for the hidden register.
3564 */
3565#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3566 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3567
3568#ifndef VBOX_FOR_DTRACE_LIB
3569
3570/**
3571 * 64 bits generic descriptor table entry
3572 * Note: most of these bits have no meaning in long mode.
3573 */
3574#pragma pack(1)
3575typedef struct X86DESC64GENERIC
3576{
3577 /** Limit - Low word - *IGNORED*. */
3578 uint32_t u16LimitLow : 16;
3579 /** Base address - low word. - *IGNORED*
3580 * Don't try set this to 24 because MSC is doing stupid things then. */
3581 uint32_t u16BaseLow : 16;
3582 /** Base address - first 8 bits of high word. - *IGNORED* */
3583 uint32_t u8BaseHigh1 : 8;
3584 /** Segment Type. */
3585 uint32_t u4Type : 4;
3586 /** Descriptor Type. System(=0) or code/data selector */
3587 uint32_t u1DescType : 1;
3588 /** Descriptor Privilege level. */
3589 uint32_t u2Dpl : 2;
3590 /** Flags selector present(=1) or not. */
3591 uint32_t u1Present : 1;
3592 /** Segment limit 16-19. - *IGNORED* */
3593 uint32_t u4LimitHigh : 4;
3594 /** Available for system software. - *IGNORED* */
3595 uint32_t u1Available : 1;
3596 /** Long mode flag. */
3597 uint32_t u1Long : 1;
3598 /** This flags meaning depends on the segment type. Try make sense out
3599 * of the intel manual yourself. */
3600 uint32_t u1DefBig : 1;
3601 /** Granularity of the limit. If set 4KB granularity is used, if
3602 * clear byte. - *IGNORED* */
3603 uint32_t u1Granularity : 1;
3604 /** Base address - highest 8 bits. - *IGNORED* */
3605 uint32_t u8BaseHigh2 : 8;
3606 /** Base address - bits 63-32. */
3607 uint32_t u32BaseHigh3 : 32;
3608 uint32_t u8Reserved : 8;
3609 uint32_t u5Zeros : 5;
3610 uint32_t u19Reserved : 19;
3611} X86DESC64GENERIC;
3612#pragma pack()
3613/** Pointer to a generic descriptor entry. */
3614typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3615/** Pointer to a const generic descriptor entry. */
3616typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3617
3618/**
3619 * System descriptor table entry (64 bits)
3620 *
3621 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3622 */
3623#pragma pack(1)
3624typedef struct X86DESC64SYSTEM
3625{
3626 /** Limit - Low word. */
3627 uint32_t u16LimitLow : 16;
3628 /** Base address - low word.
3629 * Don't try set this to 24 because MSC is doing stupid things then. */
3630 uint32_t u16BaseLow : 16;
3631 /** Base address - first 8 bits of high word. */
3632 uint32_t u8BaseHigh1 : 8;
3633 /** Segment Type. */
3634 uint32_t u4Type : 4;
3635 /** Descriptor Type. System(=0) or code/data selector */
3636 uint32_t u1DescType : 1;
3637 /** Descriptor Privilege level. */
3638 uint32_t u2Dpl : 2;
3639 /** Flags selector present(=1) or not. */
3640 uint32_t u1Present : 1;
3641 /** Segment limit 16-19. */
3642 uint32_t u4LimitHigh : 4;
3643 /** Available for system software. */
3644 uint32_t u1Available : 1;
3645 /** Reserved - 0. */
3646 uint32_t u1Reserved : 1;
3647 /** This flags meaning depends on the segment type. Try make sense out
3648 * of the intel manual yourself. */
3649 uint32_t u1DefBig : 1;
3650 /** Granularity of the limit. If set 4KB granularity is used, if
3651 * clear byte. */
3652 uint32_t u1Granularity : 1;
3653 /** Base address - bits 31-24. */
3654 uint32_t u8BaseHigh2 : 8;
3655 /** Base address - bits 63-32. */
3656 uint32_t u32BaseHigh3 : 32;
3657 uint32_t u8Reserved : 8;
3658 uint32_t u5Zeros : 5;
3659 uint32_t u19Reserved : 19;
3660} X86DESC64SYSTEM;
3661#pragma pack()
3662/** Pointer to a system descriptor entry. */
3663typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3664/** Pointer to a const system descriptor entry. */
3665typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3666
3667/**
3668 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3669 */
3670typedef struct X86DESC64GATE
3671{
3672 /** Target code segment offset - Low word. */
3673 uint32_t u16OffsetLow : 16;
3674 /** Target code segment selector. */
3675 uint32_t u16Sel : 16;
3676 /** Interrupt stack table for interrupt- and trap-gates.
3677 * Ignored by call-gates. */
3678 uint32_t u3IST : 3;
3679 /** Reserved / ignored. */
3680 uint32_t u5Reserved : 5;
3681 /** Segment Type. */
3682 uint32_t u4Type : 4;
3683 /** Descriptor Type (0 = system). */
3684 uint32_t u1DescType : 1;
3685 /** Descriptor Privilege level. */
3686 uint32_t u2Dpl : 2;
3687 /** Flags selector present(=1) or not. */
3688 uint32_t u1Present : 1;
3689 /** Target code segment offset - High word.
3690 * Ignored if task-gate. */
3691 uint32_t u16OffsetHigh : 16;
3692 /** Target code segment offset - Top dword.
3693 * Ignored if task-gate. */
3694 uint32_t u32OffsetTop : 32;
3695 /** Reserved / ignored / must be zero.
3696 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3697 uint32_t u32Reserved : 32;
3698} X86DESC64GATE;
3699AssertCompileSize(X86DESC64GATE, 16);
3700/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3701typedef X86DESC64GATE *PX86DESC64GATE;
3702/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3703typedef const X86DESC64GATE *PCX86DESC64GATE;
3704
3705#endif /* VBOX_FOR_DTRACE_LIB */
3706
3707/**
3708 * Descriptor table entry.
3709 */
3710#pragma pack(1)
3711typedef union X86DESC64
3712{
3713#ifndef VBOX_FOR_DTRACE_LIB
3714 /** Generic descriptor view. */
3715 X86DESC64GENERIC Gen;
3716 /** System descriptor view. */
3717 X86DESC64SYSTEM System;
3718 /** Gate descriptor view. */
3719 X86DESC64GATE Gate;
3720#endif
3721
3722 /** 8 bit unsigned integer view. */
3723 uint8_t au8[16];
3724 /** 16 bit unsigned integer view. */
3725 uint16_t au16[8];
3726 /** 32 bit unsigned integer view. */
3727 uint32_t au32[4];
3728 /** 64 bit unsigned integer view. */
3729 uint64_t au64[2];
3730} X86DESC64;
3731#ifndef VBOX_FOR_DTRACE_LIB
3732AssertCompileSize(X86DESC64, 16);
3733#endif
3734#pragma pack()
3735/** Pointer to descriptor table entry. */
3736typedef X86DESC64 *PX86DESC64;
3737/** Pointer to const descriptor table entry. */
3738typedef const X86DESC64 *PCX86DESC64;
3739
3740/** @def X86DESC64_BASE
3741 * Return the base of a 64-bit descriptor.
3742 */
3743#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3744 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3745 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3746 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3747 | ( (a_pDesc)->Gen.u16BaseLow ) )
3748
3749
3750
3751/** @name Host system descriptor table entry - Use with care!
3752 * @{ */
3753/** Host system descriptor table entry. */
3754#if HC_ARCH_BITS == 64
3755typedef X86DESC64 X86DESCHC;
3756#else
3757typedef X86DESC X86DESCHC;
3758#endif
3759/** Pointer to a host system descriptor table entry. */
3760#if HC_ARCH_BITS == 64
3761typedef PX86DESC64 PX86DESCHC;
3762#else
3763typedef PX86DESC PX86DESCHC;
3764#endif
3765/** Pointer to a const host system descriptor table entry. */
3766#if HC_ARCH_BITS == 64
3767typedef PCX86DESC64 PCX86DESCHC;
3768#else
3769typedef PCX86DESC PCX86DESCHC;
3770#endif
3771/** @} */
3772
3773
3774/** @name Selector Descriptor Types.
3775 * @{
3776 */
3777
3778/** @name Non-System Selector Types.
3779 * @{ */
3780/** Code(=set)/Data(=clear) bit. */
3781#define X86_SEL_TYPE_CODE 8
3782/** Memory(=set)/System(=clear) bit. */
3783#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3784/** Accessed bit. */
3785#define X86_SEL_TYPE_ACCESSED 1
3786/** Expand down bit (for data selectors only). */
3787#define X86_SEL_TYPE_DOWN 4
3788/** Conforming bit (for code selectors only). */
3789#define X86_SEL_TYPE_CONF 4
3790/** Write bit (for data selectors only). */
3791#define X86_SEL_TYPE_WRITE 2
3792/** Read bit (for code selectors only). */
3793#define X86_SEL_TYPE_READ 2
3794/** The bit number of the code segment read bit (relative to u4Type). */
3795#define X86_SEL_TYPE_READ_BIT 1
3796
3797/** Read only selector type. */
3798#define X86_SEL_TYPE_RO 0
3799/** Accessed read only selector type. */
3800#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3801/** Read write selector type. */
3802#define X86_SEL_TYPE_RW 2
3803/** Accessed read write selector type. */
3804#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3805/** Expand down read only selector type. */
3806#define X86_SEL_TYPE_RO_DOWN 4
3807/** Accessed expand down read only selector type. */
3808#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3809/** Expand down read write selector type. */
3810#define X86_SEL_TYPE_RW_DOWN 6
3811/** Accessed expand down read write selector type. */
3812#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3813/** Execute only selector type. */
3814#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3815/** Accessed execute only selector type. */
3816#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3817/** Execute and read selector type. */
3818#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3819/** Accessed execute and read selector type. */
3820#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3821/** Conforming execute only selector type. */
3822#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3823/** Accessed Conforming execute only selector type. */
3824#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3825/** Conforming execute and write selector type. */
3826#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3827/** Accessed Conforming execute and write selector type. */
3828#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3829/** @} */
3830
3831
3832/** @name System Selector Types.
3833 * @{ */
3834/** The TSS busy bit mask. */
3835#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3836
3837/** Undefined system selector type. */
3838#define X86_SEL_TYPE_SYS_UNDEFINED 0
3839/** 286 TSS selector. */
3840#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3841/** LDT selector. */
3842#define X86_SEL_TYPE_SYS_LDT 2
3843/** 286 TSS selector - Busy. */
3844#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3845/** 286 Callgate selector. */
3846#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3847/** Taskgate selector. */
3848#define X86_SEL_TYPE_SYS_TASK_GATE 5
3849/** 286 Interrupt gate selector. */
3850#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3851/** 286 Trapgate selector. */
3852#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3853/** Undefined system selector. */
3854#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3855/** 386 TSS selector. */
3856#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3857/** Undefined system selector. */
3858#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3859/** 386 TSS selector - Busy. */
3860#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3861/** 386 Callgate selector. */
3862#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3863/** Undefined system selector. */
3864#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3865/** 386 Interruptgate selector. */
3866#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3867/** 386 Trapgate selector. */
3868#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3869/** @} */
3870
3871/** @name AMD64 System Selector Types.
3872 * @{ */
3873/** LDT selector. */
3874#define AMD64_SEL_TYPE_SYS_LDT 2
3875/** TSS selector - Busy. */
3876#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3877/** TSS selector - Busy. */
3878#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3879/** Callgate selector. */
3880#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3881/** Interruptgate selector. */
3882#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3883/** Trapgate selector. */
3884#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3885/** @} */
3886
3887/** @} */
3888
3889
3890/** @name Descriptor Table Entry Flag Masks.
3891 * These are for the 2nd 32-bit word of a descriptor.
3892 * @{ */
3893/** Bits 8-11 - TYPE - Descriptor type mask. */
3894#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3895/** Bit 12 - S - System (=0) or Code/Data (=1). */
3896#define X86_DESC_S RT_BIT_32(12)
3897/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3898#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
3899/** Bit 15 - P - Present. */
3900#define X86_DESC_P RT_BIT_32(15)
3901/** Bit 20 - AVL - Available for system software. */
3902#define X86_DESC_AVL RT_BIT_32(20)
3903/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3904#define X86_DESC_DB RT_BIT_32(22)
3905/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3906 * used, if clear byte. */
3907#define X86_DESC_G RT_BIT_32(23)
3908/** @} */
3909
3910/** @} */
3911
3912
3913/** @name Task Segments.
3914 * @{
3915 */
3916
3917/**
3918 * The minimum TSS descriptor limit for 286 tasks.
3919 */
3920#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3921
3922/**
3923 * The minimum TSS descriptor segment limit for 386 tasks.
3924 */
3925#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3926
3927/**
3928 * 16-bit Task Segment (TSS).
3929 */
3930#pragma pack(1)
3931typedef struct X86TSS16
3932{
3933 /** Back link to previous task. (static) */
3934 RTSEL selPrev;
3935 /** Ring-0 stack pointer. (static) */
3936 uint16_t sp0;
3937 /** Ring-0 stack segment. (static) */
3938 RTSEL ss0;
3939 /** Ring-1 stack pointer. (static) */
3940 uint16_t sp1;
3941 /** Ring-1 stack segment. (static) */
3942 RTSEL ss1;
3943 /** Ring-2 stack pointer. (static) */
3944 uint16_t sp2;
3945 /** Ring-2 stack segment. (static) */
3946 RTSEL ss2;
3947 /** IP before task switch. */
3948 uint16_t ip;
3949 /** FLAGS before task switch. */
3950 uint16_t flags;
3951 /** AX before task switch. */
3952 uint16_t ax;
3953 /** CX before task switch. */
3954 uint16_t cx;
3955 /** DX before task switch. */
3956 uint16_t dx;
3957 /** BX before task switch. */
3958 uint16_t bx;
3959 /** SP before task switch. */
3960 uint16_t sp;
3961 /** BP before task switch. */
3962 uint16_t bp;
3963 /** SI before task switch. */
3964 uint16_t si;
3965 /** DI before task switch. */
3966 uint16_t di;
3967 /** ES before task switch. */
3968 RTSEL es;
3969 /** CS before task switch. */
3970 RTSEL cs;
3971 /** SS before task switch. */
3972 RTSEL ss;
3973 /** DS before task switch. */
3974 RTSEL ds;
3975 /** LDTR before task switch. */
3976 RTSEL selLdt;
3977} X86TSS16;
3978#ifndef VBOX_FOR_DTRACE_LIB
3979AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3980#endif
3981#pragma pack()
3982/** Pointer to a 16-bit task segment. */
3983typedef X86TSS16 *PX86TSS16;
3984/** Pointer to a const 16-bit task segment. */
3985typedef const X86TSS16 *PCX86TSS16;
3986
3987
3988/**
3989 * 32-bit Task Segment (TSS).
3990 */
3991#pragma pack(1)
3992typedef struct X86TSS32
3993{
3994 /** Back link to previous task. (static) */
3995 RTSEL selPrev;
3996 uint16_t padding1;
3997 /** Ring-0 stack pointer. (static) */
3998 uint32_t esp0;
3999 /** Ring-0 stack segment. (static) */
4000 RTSEL ss0;
4001 uint16_t padding_ss0;
4002 /** Ring-1 stack pointer. (static) */
4003 uint32_t esp1;
4004 /** Ring-1 stack segment. (static) */
4005 RTSEL ss1;
4006 uint16_t padding_ss1;
4007 /** Ring-2 stack pointer. (static) */
4008 uint32_t esp2;
4009 /** Ring-2 stack segment. (static) */
4010 RTSEL ss2;
4011 uint16_t padding_ss2;
4012 /** Page directory for the task. (static) */
4013 uint32_t cr3;
4014 /** EIP before task switch. */
4015 uint32_t eip;
4016 /** EFLAGS before task switch. */
4017 uint32_t eflags;
4018 /** EAX before task switch. */
4019 uint32_t eax;
4020 /** ECX before task switch. */
4021 uint32_t ecx;
4022 /** EDX before task switch. */
4023 uint32_t edx;
4024 /** EBX before task switch. */
4025 uint32_t ebx;
4026 /** ESP before task switch. */
4027 uint32_t esp;
4028 /** EBP before task switch. */
4029 uint32_t ebp;
4030 /** ESI before task switch. */
4031 uint32_t esi;
4032 /** EDI before task switch. */
4033 uint32_t edi;
4034 /** ES before task switch. */
4035 RTSEL es;
4036 uint16_t padding_es;
4037 /** CS before task switch. */
4038 RTSEL cs;
4039 uint16_t padding_cs;
4040 /** SS before task switch. */
4041 RTSEL ss;
4042 uint16_t padding_ss;
4043 /** DS before task switch. */
4044 RTSEL ds;
4045 uint16_t padding_ds;
4046 /** FS before task switch. */
4047 RTSEL fs;
4048 uint16_t padding_fs;
4049 /** GS before task switch. */
4050 RTSEL gs;
4051 uint16_t padding_gs;
4052 /** LDTR before task switch. */
4053 RTSEL selLdt;
4054 uint16_t padding_ldt;
4055 /** Debug trap flag */
4056 uint16_t fDebugTrap;
4057 /** Offset relative to the TSS of the start of the I/O Bitmap
4058 * and the end of the interrupt redirection bitmap. */
4059 uint16_t offIoBitmap;
4060} X86TSS32;
4061#pragma pack()
4062/** Pointer to task segment. */
4063typedef X86TSS32 *PX86TSS32;
4064/** Pointer to const task segment. */
4065typedef const X86TSS32 *PCX86TSS32;
4066#ifndef VBOX_FOR_DTRACE_LIB
4067AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4068AssertCompileMemberOffset(X86TSS32, cr3, 28);
4069AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4070#endif
4071
4072/**
4073 * 64-bit Task segment.
4074 */
4075#pragma pack(1)
4076typedef struct X86TSS64
4077{
4078 /** Reserved. */
4079 uint32_t u32Reserved;
4080 /** Ring-0 stack pointer. (static) */
4081 uint64_t rsp0;
4082 /** Ring-1 stack pointer. (static) */
4083 uint64_t rsp1;
4084 /** Ring-2 stack pointer. (static) */
4085 uint64_t rsp2;
4086 /** Reserved. */
4087 uint32_t u32Reserved2[2];
4088 /* IST */
4089 uint64_t ist1;
4090 uint64_t ist2;
4091 uint64_t ist3;
4092 uint64_t ist4;
4093 uint64_t ist5;
4094 uint64_t ist6;
4095 uint64_t ist7;
4096 /* Reserved. */
4097 uint16_t u16Reserved[5];
4098 /** Offset relative to the TSS of the start of the I/O Bitmap
4099 * and the end of the interrupt redirection bitmap. */
4100 uint16_t offIoBitmap;
4101} X86TSS64;
4102#pragma pack()
4103/** Pointer to a 64-bit task segment. */
4104typedef X86TSS64 *PX86TSS64;
4105/** Pointer to a const 64-bit task segment. */
4106typedef const X86TSS64 *PCX86TSS64;
4107#ifndef VBOX_FOR_DTRACE_LIB
4108AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4109#endif
4110
4111/** @} */
4112
4113
4114/** @name Selectors.
4115 * @{
4116 */
4117
4118/**
4119 * The shift used to convert a selector from and to index an index (C).
4120 */
4121#define X86_SEL_SHIFT 3
4122
4123/**
4124 * The mask used to mask off the table indicator and RPL of an selector.
4125 */
4126#define X86_SEL_MASK 0xfff8U
4127
4128/**
4129 * The mask used to mask off the RPL of an selector.
4130 * This is suitable for checking for NULL selectors.
4131 */
4132#define X86_SEL_MASK_OFF_RPL 0xfffcU
4133
4134/**
4135 * The bit indicating that a selector is in the LDT and not in the GDT.
4136 */
4137#define X86_SEL_LDT 0x0004U
4138
4139/**
4140 * The bit mask for getting the RPL of a selector.
4141 */
4142#define X86_SEL_RPL 0x0003U
4143
4144/**
4145 * The mask covering both RPL and LDT.
4146 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4147 * checks.
4148 */
4149#define X86_SEL_RPL_LDT 0x0007U
4150
4151/** @} */
4152
4153
4154/**
4155 * x86 Exceptions/Faults/Traps.
4156 */
4157typedef enum X86XCPT
4158{
4159 /** \#DE - Divide error. */
4160 X86_XCPT_DE = 0x00,
4161 /** \#DB - Debug event (single step, DRx, ..) */
4162 X86_XCPT_DB = 0x01,
4163 /** NMI - Non-Maskable Interrupt */
4164 X86_XCPT_NMI = 0x02,
4165 /** \#BP - Breakpoint (INT3). */
4166 X86_XCPT_BP = 0x03,
4167 /** \#OF - Overflow (INTO). */
4168 X86_XCPT_OF = 0x04,
4169 /** \#BR - Bound range exceeded (BOUND). */
4170 X86_XCPT_BR = 0x05,
4171 /** \#UD - Undefined opcode. */
4172 X86_XCPT_UD = 0x06,
4173 /** \#NM - Device not available (math coprocessor device). */
4174 X86_XCPT_NM = 0x07,
4175 /** \#DF - Double fault. */
4176 X86_XCPT_DF = 0x08,
4177 /** ??? - Coprocessor segment overrun (obsolete). */
4178 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4179 /** \#TS - Taskswitch (TSS). */
4180 X86_XCPT_TS = 0x0a,
4181 /** \#NP - Segment no present. */
4182 X86_XCPT_NP = 0x0b,
4183 /** \#SS - Stack segment fault. */
4184 X86_XCPT_SS = 0x0c,
4185 /** \#GP - General protection fault. */
4186 X86_XCPT_GP = 0x0d,
4187 /** \#PF - Page fault. */
4188 X86_XCPT_PF = 0x0e,
4189 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4190 /** \#MF - Math fault (FPU). */
4191 X86_XCPT_MF = 0x10,
4192 /** \#AC - Alignment check. */
4193 X86_XCPT_AC = 0x11,
4194 /** \#MC - Machine check. */
4195 X86_XCPT_MC = 0x12,
4196 /** \#XF - SIMD Floating-Pointer Exception. */
4197 X86_XCPT_XF = 0x13,
4198 /** \#VE - Virtualization Exception. */
4199 X86_XCPT_VE = 0x14,
4200 /** \#SX - Security Exception. */
4201 X86_XCPT_SX = 0x1e
4202} X86XCPT;
4203/** Pointer to a x86 exception code. */
4204typedef X86XCPT *PX86XCPT;
4205/** Pointer to a const x86 exception code. */
4206typedef const X86XCPT *PCX86XCPT;
4207/** The last valid (currently reserved) exception value. */
4208#define X86_XCPT_LAST 0x1f
4209
4210
4211/** @name Trap Error Codes
4212 * @{
4213 */
4214/** External indicator. */
4215#define X86_TRAP_ERR_EXTERNAL 1
4216/** IDT indicator. */
4217#define X86_TRAP_ERR_IDT 2
4218/** Descriptor table indicator - If set LDT, if clear GDT. */
4219#define X86_TRAP_ERR_TI 4
4220/** Mask for getting the selector. */
4221#define X86_TRAP_ERR_SEL_MASK 0xfff8
4222/** Shift for getting the selector table index (C type index). */
4223#define X86_TRAP_ERR_SEL_SHIFT 3
4224/** @} */
4225
4226
4227/** @name \#PF Trap Error Codes
4228 * @{
4229 */
4230/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4231#define X86_TRAP_PF_P RT_BIT_32(0)
4232/** Bit 1 - R/W - Read (clear) or write (set) access. */
4233#define X86_TRAP_PF_RW RT_BIT_32(1)
4234/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4235#define X86_TRAP_PF_US RT_BIT_32(2)
4236/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4237#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4238/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4239#define X86_TRAP_PF_ID RT_BIT_32(4)
4240/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4241#define X86_TRAP_PF_PK RT_BIT_32(5)
4242/** @} */
4243
4244#pragma pack(1)
4245/**
4246 * 16-bit IDTR.
4247 */
4248typedef struct X86IDTR16
4249{
4250 /** Offset. */
4251 uint16_t offSel;
4252 /** Selector. */
4253 uint16_t uSel;
4254} X86IDTR16, *PX86IDTR16;
4255#pragma pack()
4256
4257#pragma pack(1)
4258/**
4259 * 32-bit IDTR/GDTR.
4260 */
4261typedef struct X86XDTR32
4262{
4263 /** Size of the descriptor table. */
4264 uint16_t cb;
4265 /** Address of the descriptor table. */
4266#ifndef VBOX_FOR_DTRACE_LIB
4267 uint32_t uAddr;
4268#else
4269 uint16_t au16Addr[2];
4270#endif
4271} X86XDTR32, *PX86XDTR32;
4272#pragma pack()
4273
4274#pragma pack(1)
4275/**
4276 * 64-bit IDTR/GDTR.
4277 */
4278typedef struct X86XDTR64
4279{
4280 /** Size of the descriptor table. */
4281 uint16_t cb;
4282 /** Address of the descriptor table. */
4283#ifndef VBOX_FOR_DTRACE_LIB
4284 uint64_t uAddr;
4285#else
4286 uint16_t au16Addr[4];
4287#endif
4288} X86XDTR64, *PX86XDTR64;
4289#pragma pack()
4290
4291
4292/** @name ModR/M
4293 * @{ */
4294#define X86_MODRM_RM_MASK UINT8_C(0x07)
4295#define X86_MODRM_REG_MASK UINT8_C(0x38)
4296#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4297#define X86_MODRM_REG_SHIFT 3
4298#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4299#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4300#define X86_MODRM_MOD_SHIFT 6
4301#ifndef VBOX_FOR_DTRACE_LIB
4302AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4303AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4304AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4305/** @def X86_MODRM_MAKE
4306 * @param a_Mod The mod value (0..3).
4307 * @param a_Reg The register value (0..7).
4308 * @param a_RegMem The register or memory value (0..7). */
4309# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4310#endif
4311/** @} */
4312
4313/** @name SIB
4314 * @{ */
4315#define X86_SIB_BASE_MASK UINT8_C(0x07)
4316#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4317#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4318#define X86_SIB_INDEX_SHIFT 3
4319#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4320#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4321#define X86_SIB_SCALE_SHIFT 6
4322#ifndef VBOX_FOR_DTRACE_LIB
4323AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4324AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4325AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4326#endif
4327/** @} */
4328
4329/** @name General register indexes
4330 * @{ */
4331#define X86_GREG_xAX 0
4332#define X86_GREG_xCX 1
4333#define X86_GREG_xDX 2
4334#define X86_GREG_xBX 3
4335#define X86_GREG_xSP 4
4336#define X86_GREG_xBP 5
4337#define X86_GREG_xSI 6
4338#define X86_GREG_xDI 7
4339#define X86_GREG_x8 8
4340#define X86_GREG_x9 9
4341#define X86_GREG_x10 10
4342#define X86_GREG_x11 11
4343#define X86_GREG_x12 12
4344#define X86_GREG_x13 13
4345#define X86_GREG_x14 14
4346#define X86_GREG_x15 15
4347/** @} */
4348
4349/** @name X86_SREG_XXX - Segment register indexes.
4350 * @{ */
4351#define X86_SREG_ES 0
4352#define X86_SREG_CS 1
4353#define X86_SREG_SS 2
4354#define X86_SREG_DS 3
4355#define X86_SREG_FS 4
4356#define X86_SREG_GS 5
4357/** @} */
4358/** Segment register count. */
4359#define X86_SREG_COUNT 6
4360
4361
4362/** @name X86_OP_XXX - Prefixes
4363 * @{ */
4364#define X86_OP_PRF_CS UINT8_C(0x2e)
4365#define X86_OP_PRF_SS UINT8_C(0x36)
4366#define X86_OP_PRF_DS UINT8_C(0x3e)
4367#define X86_OP_PRF_ES UINT8_C(0x26)
4368#define X86_OP_PRF_FS UINT8_C(0x64)
4369#define X86_OP_PRF_GS UINT8_C(0x65)
4370#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4371#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4372#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4373#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4374#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4375#define X86_OP_REX_B UINT8_C(0x41)
4376#define X86_OP_REX_X UINT8_C(0x42)
4377#define X86_OP_REX_R UINT8_C(0x44)
4378#define X86_OP_REX_W UINT8_C(0x48)
4379/** @} */
4380
4381
4382/** @} */
4383
4384#endif
4385
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