x86.h@ 76687

Last change on this file since 76687 was 76678, checked in by vboxsync, 6 years ago
Port r124260, r124263, r124271, r124273, r124277, r124278, r124279, r124284, r124285, r124286, r124287, r124288, r124289 and r124290 (Ported fixes over from 5.2, see bugref:9179 for more information)
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2019 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef IPRT_INCLUDED_x86_h
29	#define IPRT_INCLUDED_x86_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef VBOX_FOR_DTRACE_LIB
35	# include <iprt/types.h>
36	# include <iprt/assert.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	#endif
40
41	/* Workaround for Solaris sys/regset.h defining CS, DS */
42	#ifdef RT_OS_SOLARIS
43	# undef CS
44	# undef DS
45	#endif
46
47	/** @defgroup grp_rt_x86 x86 Types and Definitions
48	* @ingroup grp_rt
49	* @{
50	*/
51
52	#ifndef VBOX_FOR_DTRACE_LIB
53	/**
54	* EFLAGS Bits.
55	*/
56	typedef struct X86EFLAGSBITS
57	{
58	/** Bit 0 - CF - Carry flag - Status flag. */
59	unsigned u1CF : 1;
60	/** Bit 1 - 1 - Reserved flag. */
61	unsigned u1Reserved0 : 1;
62	/** Bit 2 - PF - Parity flag - Status flag. */
63	unsigned u1PF : 1;
64	/** Bit 3 - 0 - Reserved flag. */
65	unsigned u1Reserved1 : 1;
66	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67	unsigned u1AF : 1;
68	/** Bit 5 - 0 - Reserved flag. */
69	unsigned u1Reserved2 : 1;
70	/** Bit 6 - ZF - Zero flag - Status flag. */
71	unsigned u1ZF : 1;
72	/** Bit 7 - SF - Signed flag - Status flag. */
73	unsigned u1SF : 1;
74	/** Bit 8 - TF - Trap flag - System flag. */
75	unsigned u1TF : 1;
76	/** Bit 9 - IF - Interrupt flag - System flag. */
77	unsigned u1IF : 1;
78	/** Bit 10 - DF - Direction flag - Control flag. */
79	unsigned u1DF : 1;
80	/** Bit 11 - OF - Overflow flag - Status flag. */
81	unsigned u1OF : 1;
82	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83	unsigned u2IOPL : 2;
84	/** Bit 14 - NT - Nested task flag - System flag. */
85	unsigned u1NT : 1;
86	/** Bit 15 - 0 - Reserved flag. */
87	unsigned u1Reserved3 : 1;
88	/** Bit 16 - RF - Resume flag - System flag. */
89	unsigned u1RF : 1;
90	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
91	unsigned u1VM : 1;
92	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93	unsigned u1AC : 1;
94	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95	unsigned u1VIF : 1;
96	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97	unsigned u1VIP : 1;
98	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99	unsigned u1ID : 1;
100	/** Bit 22-31 - 0 - Reserved flag. */
101	unsigned u10Reserved4 : 10;
102	} X86EFLAGSBITS;
103	/** Pointer to EFLAGS bits. */
104	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105	/** Pointer to const EFLAGS bits. */
106	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107	#endif /* !VBOX_FOR_DTRACE_LIB */
108
109	/**
110	* EFLAGS.
111	*/
112	typedef union X86EFLAGS
113	{
114	/** The plain unsigned view. */
115	uint32_t u;
116	#ifndef VBOX_FOR_DTRACE_LIB
117	/** The bitfield view. */
118	X86EFLAGSBITS Bits;
119	#endif
120	/** The 8-bit view. */
121	uint8_t au8[4];
122	/** The 16-bit view. */
123	uint16_t au16[2];
124	/** The 32-bit view. */
125	uint32_t au32[1];
126	/** The 32-bit view. */
127	uint32_t u32;
128	} X86EFLAGS;
129	/** Pointer to EFLAGS. */
130	typedef X86EFLAGS *PX86EFLAGS;
131	/** Pointer to const EFLAGS. */
132	typedef const X86EFLAGS *PCX86EFLAGS;
133
134	/**
135	* RFLAGS (32 upper bits are reserved).
136	*/
137	typedef union X86RFLAGS
138	{
139	/** The plain unsigned view. */
140	uint64_t u;
141	#ifndef VBOX_FOR_DTRACE_LIB
142	/** The bitfield view. */
143	X86EFLAGSBITS Bits;
144	#endif
145	/** The 8-bit view. */
146	uint8_t au8[8];
147	/** The 16-bit view. */
148	uint16_t au16[4];
149	/** The 32-bit view. */
150	uint32_t au32[2];
151	/** The 64-bit view. */
152	uint64_t au64[1];
153	/** The 64-bit view. */
154	uint64_t u64;
155	} X86RFLAGS;
156	/** Pointer to RFLAGS. */
157	typedef X86RFLAGS *PX86RFLAGS;
158	/** Pointer to const RFLAGS. */
159	typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162	/** @name EFLAGS
163	* @{
164	*/
165	/** Bit 0 - CF - Carry flag - Status flag. */
166	#define X86_EFL_CF RT_BIT_32(0)
167	#define X86_EFL_CF_BIT 0
168	/** Bit 1 - Reserved, reads as 1. */
169	#define X86_EFL_1 RT_BIT_32(1)
170	/** Bit 2 - PF - Parity flag - Status flag. */
171	#define X86_EFL_PF RT_BIT_32(2)
172	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173	#define X86_EFL_AF RT_BIT_32(4)
174	#define X86_EFL_AF_BIT 4
175	/** Bit 6 - ZF - Zero flag - Status flag. */
176	#define X86_EFL_ZF RT_BIT_32(6)
177	#define X86_EFL_ZF_BIT 6
178	/** Bit 7 - SF - Signed flag - Status flag. */
179	#define X86_EFL_SF RT_BIT_32(7)
180	#define X86_EFL_SF_BIT 7
181	/** Bit 8 - TF - Trap flag - System flag. */
182	#define X86_EFL_TF RT_BIT_32(8)
183	/** Bit 9 - IF - Interrupt flag - System flag. */
184	#define X86_EFL_IF RT_BIT_32(9)
185	/** Bit 10 - DF - Direction flag - Control flag. */
186	#define X86_EFL_DF RT_BIT_32(10)
187	/** Bit 11 - OF - Overflow flag - Status flag. */
188	#define X86_EFL_OF RT_BIT_32(11)
189	#define X86_EFL_OF_BIT 11
190	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
192	/** Bit 14 - NT - Nested task flag - System flag. */
193	#define X86_EFL_NT RT_BIT_32(14)
194	/** Bit 16 - RF - Resume flag - System flag. */
195	#define X86_EFL_RF RT_BIT_32(16)
196	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197	#define X86_EFL_VM RT_BIT_32(17)
198	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199	#define X86_EFL_AC RT_BIT_32(18)
200	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201	#define X86_EFL_VIF RT_BIT_32(19)
202	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203	#define X86_EFL_VIP RT_BIT_32(20)
204	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205	#define X86_EFL_ID RT_BIT_32(21)
206	/** All live bits. */
207	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208	/** Read as 1 bits. */
209	#define X86_EFL_RA1_MASK RT_BIT_32(1)
210	/** IOPL shift. */
211	#define X86_EFL_IOPL_SHIFT 12
212	/** The IOPL level from the flags. */
213	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214	/** Bits restored by popf */
215	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
216	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
217	/** Bits restored by popf */
218	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
219	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
220	/** The status bits commonly updated by arithmetic instructions. */
221	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
222	/** @} */
223
224
225	/** CPUID Feature information - ECX.
226	* CPUID query with EAX=1.
227	*/
228	#ifndef VBOX_FOR_DTRACE_LIB
229	typedef struct X86CPUIDFEATECX
230	{
231	/** Bit 0 - SSE3 - Supports SSE3 or not. */
232	unsigned u1SSE3 : 1;
233	/** Bit 1 - PCLMULQDQ. */
234	unsigned u1PCLMULQDQ : 1;
235	/** Bit 2 - DS Area 64-bit layout. */
236	unsigned u1DTE64 : 1;
237	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238	unsigned u1Monitor : 1;
239	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240	unsigned u1CPLDS : 1;
241	/** Bit 5 - VMX - Virtual Machine Technology. */
242	unsigned u1VMX : 1;
243	/** Bit 6 - SMX: Safer Mode Extensions. */
244	unsigned u1SMX : 1;
245	/** Bit 7 - EST - Enh. SpeedStep Tech. */
246	unsigned u1EST : 1;
247	/** Bit 8 - TM2 - Terminal Monitor 2. */
248	unsigned u1TM2 : 1;
249	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250	unsigned u1SSSE3 : 1;
251	/** Bit 10 - CNTX-ID - L1 Context ID. */
252	unsigned u1CNTXID : 1;
253	/** Bit 11 - Reserved. */
254	unsigned u1Reserved1 : 1;
255	/** Bit 12 - FMA. */
256	unsigned u1FMA : 1;
257	/** Bit 13 - CX16 - CMPXCHG16B. */
258	unsigned u1CX16 : 1;
259	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260	unsigned u1TPRUpdate : 1;
261	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262	unsigned u1PDCM : 1;
263	/** Bit 16 - Reserved. */
264	unsigned u1Reserved2 : 1;
265	/** Bit 17 - PCID - Process-context identifiers. */
266	unsigned u1PCID : 1;
267	/** Bit 18 - Direct Cache Access. */
268	unsigned u1DCA : 1;
269	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270	unsigned u1SSE4_1 : 1;
271	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272	unsigned u1SSE4_2 : 1;
273	/** Bit 21 - x2APIC. */
274	unsigned u1x2APIC : 1;
275	/** Bit 22 - MOVBE - Supports MOVBE. */
276	unsigned u1MOVBE : 1;
277	/** Bit 23 - POPCNT - Supports POPCNT. */
278	unsigned u1POPCNT : 1;
279	/** Bit 24 - TSC-Deadline. */
280	unsigned u1TSCDEADLINE : 1;
281	/** Bit 25 - AES. */
282	unsigned u1AES : 1;
283	/** Bit 26 - XSAVE - Supports XSAVE. */
284	unsigned u1XSAVE : 1;
285	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286	unsigned u1OSXSAVE : 1;
287	/** Bit 28 - AVX - Supports AVX instruction extensions. */
288	unsigned u1AVX : 1;
289	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290	unsigned u1F16C : 1;
291	/** Bit 30 - RDRAND - Supports RDRAND. */
292	unsigned u1RDRAND : 1;
293	/** Bit 31 - Hypervisor present (we're a guest). */
294	unsigned u1HVP : 1;
295	} X86CPUIDFEATECX;
296	#else /* VBOX_FOR_DTRACE_LIB */
297	typedef uint32_t X86CPUIDFEATECX;
298	#endif /* VBOX_FOR_DTRACE_LIB */
299	/** Pointer to CPUID Feature Information - ECX. */
300	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301	/** Pointer to const CPUID Feature Information - ECX. */
302	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305	/** CPUID Feature Information - EDX.
306	* CPUID query with EAX=1.
307	*/
308	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309	typedef struct X86CPUIDFEATEDX
310	{
311	/** Bit 0 - FPU - x87 FPU on Chip. */
312	unsigned u1FPU : 1;
313	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314	unsigned u1VME : 1;
315	/** Bit 2 - DE - Debugging extensions. */
316	unsigned u1DE : 1;
317	/** Bit 3 - PSE - Page Size Extension. */
318	unsigned u1PSE : 1;
319	/** Bit 4 - TSC - Time Stamp Counter. */
320	unsigned u1TSC : 1;
321	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322	unsigned u1MSR : 1;
323	/** Bit 6 - PAE - Physical Address Extension. */
324	unsigned u1PAE : 1;
325	/** Bit 7 - MCE - Machine Check Exception. */
326	unsigned u1MCE : 1;
327	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
328	unsigned u1CX8 : 1;
329	/** Bit 9 - APIC - APIC On-Chip. */
330	unsigned u1APIC : 1;
331	/** Bit 10 - Reserved. */
332	unsigned u1Reserved1 : 1;
333	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334	unsigned u1SEP : 1;
335	/** Bit 12 - MTRR - Memory Type Range Registers. */
336	unsigned u1MTRR : 1;
337	/** Bit 13 - PGE - PTE Global Bit. */
338	unsigned u1PGE : 1;
339	/** Bit 14 - MCA - Machine Check Architecture. */
340	unsigned u1MCA : 1;
341	/** Bit 15 - CMOV - Conditional Move Instructions. */
342	unsigned u1CMOV : 1;
343	/** Bit 16 - PAT - Page Attribute Table. */
344	unsigned u1PAT : 1;
345	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346	unsigned u1PSE36 : 1;
347	/** Bit 18 - PSN - Processor Serial Number. */
348	unsigned u1PSN : 1;
349	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
350	unsigned u1CLFSH : 1;
351	/** Bit 20 - Reserved. */
352	unsigned u1Reserved2 : 1;
353	/** Bit 21 - DS - Debug Store. */
354	unsigned u1DS : 1;
355	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356	unsigned u1ACPI : 1;
357	/** Bit 23 - MMX - Intel MMX 'Technology'. */
358	unsigned u1MMX : 1;
359	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360	unsigned u1FXSR : 1;
361	/** Bit 25 - SSE - SSE Support. */
362	unsigned u1SSE : 1;
363	/** Bit 26 - SSE2 - SSE2 Support. */
364	unsigned u1SSE2 : 1;
365	/** Bit 27 - SS - Self Snoop. */
366	unsigned u1SS : 1;
367	/** Bit 28 - HTT - Hyper-Threading Technology. */
368	unsigned u1HTT : 1;
369	/** Bit 29 - TM - Thermal Monitor. */
370	unsigned u1TM : 1;
371	/** Bit 30 - Reserved - . */
372	unsigned u1Reserved3 : 1;
373	/** Bit 31 - PBE - Pending Break Enabled. */
374	unsigned u1PBE : 1;
375	} X86CPUIDFEATEDX;
376	#else /* VBOX_FOR_DTRACE_LIB */
377	typedef uint32_t X86CPUIDFEATEDX;
378	#endif /* VBOX_FOR_DTRACE_LIB */
379	/** Pointer to CPUID Feature Information - EDX. */
380	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381	/** Pointer to const CPUID Feature Information - EDX. */
382	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384	/** @name CPUID Vendor information.
385	* CPUID query with EAX=0.
386	* @{
387	*/
388	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399	/** @} */
400
401
402	/** @name CPUID Feature information.
403	* CPUID query with EAX=1.
404	* @{
405	*/
406	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
407	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
408	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
409	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
410	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
411	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
412	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
413	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
414	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
415	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
416	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
417	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
418	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
419	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
420	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
421	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
422	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
423	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
424	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
425	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
426	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
427	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
428	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
429	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
430	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
431	/** ECX Bit 12 - FMA. */
432	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
433	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
434	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
435	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
436	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
437	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
438	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
439	/** ECX Bit 17 - PCID - Process-context identifiers. */
440	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
441	/** ECX Bit 18 - DCA - Direct Cache Access. */
442	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
443	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
444	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
445	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
446	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
447	/** ECX Bit 21 - x2APIC support. */
448	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
449	/** ECX Bit 22 - MOVBE instruction. */
450	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
451	/** ECX Bit 23 - POPCNT instruction. */
452	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
453	/** ECX Bir 24 - TSC-Deadline. */
454	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
455	/** ECX Bit 25 - AES instructions. */
456	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
457	/** ECX Bit 26 - XSAVE instruction. */
458	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
459	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
460	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
461	/** ECX Bit 28 - AVX. */
462	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
463	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
464	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
465	/** ECX Bit 30 - RDRAND instruction. */
466	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
467	/** ECX Bit 31 - Hypervisor Present (software only). */
468	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
469
470
471	/** Bit 0 - FPU - x87 FPU on Chip. */
472	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
473	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
474	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
475	/** Bit 2 - DE - Debugging extensions. */
476	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
477	/** Bit 3 - PSE - Page Size Extension. */
478	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
479	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
480	/** Bit 4 - TSC - Time Stamp Counter. */
481	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
482	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
483	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
484	/** Bit 6 - PAE - Physical Address Extension. */
485	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
486	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
487	/** Bit 7 - MCE - Machine Check Exception. */
488	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
489	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
490	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
491	/** Bit 9 - APIC - APIC On-Chip. */
492	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
493	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
494	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
495	/** Bit 12 - MTRR - Memory Type Range Registers. */
496	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
497	/** Bit 13 - PGE - PTE Global Bit. */
498	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
499	/** Bit 14 - MCA - Machine Check Architecture. */
500	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
501	/** Bit 15 - CMOV - Conditional Move Instructions. */
502	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
503	/** Bit 16 - PAT - Page Attribute Table. */
504	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
505	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
506	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
507	/** Bit 18 - PSN - Processor Serial Number. */
508	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
509	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
510	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
511	/** Bit 21 - DS - Debug Store. */
512	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
513	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
514	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
515	/** Bit 23 - MMX - Intel MMX Technology. */
516	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
517	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
518	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
519	/** Bit 25 - SSE - SSE Support. */
520	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
521	/** Bit 26 - SSE2 - SSE2 Support. */
522	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
523	/** Bit 27 - SS - Self Snoop. */
524	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
525	/** Bit 28 - HTT - Hyper-Threading Technology. */
526	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
527	/** Bit 29 - TM - Therm. Monitor. */
528	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
529	/** Bit 31 - PBE - Pending Break Enabled. */
530	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
531	/** @} */
532
533	/** @name CPUID mwait/monitor information.
534	* CPUID query with EAX=5.
535	* @{
536	*/
537	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
538	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
539	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
540	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
541	/** @} */
542
543
544	/** @name CPUID Structured Extended Feature information.
545	* CPUID query with EAX=7.
546	* @{
547	*/
548	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
549	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
550	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
551	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
552	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
553	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
554	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
555	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
556	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
557	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
558	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
559	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
560	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
561	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
562	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
563	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
564	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
565	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
566	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
567	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
568	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
569	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
570	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
571	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
572	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
573	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
574	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
575	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
576	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
577	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
578	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
579	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
580	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
581	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
582	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
583	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
584	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
585	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
586	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
588	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
589	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
590	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
591	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
592	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
593	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
594	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
595	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
596	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
597	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
598	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
599	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
600
601	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
602	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
603	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
604	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
605	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
606	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
607	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
608	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
609	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
610	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
611	/** ECX Bit 22 - RDPID - Support pread process ID. */
612	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
613	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
614	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
615
616	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
617	* IBPB command in IA32_PRED_CMD. */
618	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
619	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
620	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
621	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
622	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
623	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
624	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
625
626	/** @} */
627
628
629	/** @name CPUID Extended Feature information.
630	* CPUID query with EAX=0x80000001.
631	* @{
632	*/
633	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
634	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
635
636	/** EDX Bit 11 - SYSCALL/SYSRET. */
637	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
638	/** EDX Bit 20 - No-Execute/Execute-Disable. */
639	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
640	/** EDX Bit 26 - 1 GB large page. */
641	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
642	/** EDX Bit 27 - RDTSCP. */
643	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
644	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
645	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
646	/** @}*/
647
648	/** @name CPUID AMD Feature information.
649	* CPUID query with EAX=0x80000001.
650	* @{
651	*/
652	/** Bit 0 - FPU - x87 FPU on Chip. */
653	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
654	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
655	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
656	/** Bit 2 - DE - Debugging extensions. */
657	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
658	/** Bit 3 - PSE - Page Size Extension. */
659	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
660	/** Bit 4 - TSC - Time Stamp Counter. */
661	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
662	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
663	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
664	/** Bit 6 - PAE - Physical Address Extension. */
665	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
666	/** Bit 7 - MCE - Machine Check Exception. */
667	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
668	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
669	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
670	/** Bit 9 - APIC - APIC On-Chip. */
671	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
672	/** Bit 12 - MTRR - Memory Type Range Registers. */
673	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
674	/** Bit 13 - PGE - PTE Global Bit. */
675	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
676	/** Bit 14 - MCA - Machine Check Architecture. */
677	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
678	/** Bit 15 - CMOV - Conditional Move Instructions. */
679	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
680	/** Bit 16 - PAT - Page Attribute Table. */
681	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
682	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
683	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
684	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
685	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
686	/** Bit 23 - MMX - Intel MMX Technology. */
687	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
688	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
689	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
690	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
691	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
692	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
693	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
694	/** Bit 31 - 3DNOW - AMD 3DNow. */
695	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
696
697	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
698	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
699	/** Bit 2 - SVM - AMD VM extensions. */
700	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
701	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
702	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
703	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
704	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
705	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
706	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
707	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
708	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
709	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
710	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
711	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
712	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
713	/** Bit 9 - OSVW - AMD OS visible workaround. */
714	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
715	/** Bit 10 - IBS - Instruct based sampling. */
716	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
717	/** Bit 11 - XOP - Extended operation support (see APM6). */
718	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
719	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
720	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
721	/** Bit 13 - WDT - AMD Watchdog timer support. */
722	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
723	/** Bit 15 - LWP - Lightweight profiling support. */
724	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
725	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
726	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
727	/** Bit 19 - NodeId - Indicates support for
728	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
729	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
730	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
731	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
732	/** Bit 22 - TopologyExtensions - . */
733	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
734	/** @} */
735
736
737	/** @name CPUID AMD Feature information.
738	* CPUID query with EAX=0x80000007.
739	* @{
740	*/
741	/** Bit 0 - TS - Temperature Sensor. */
742	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
743	/** Bit 1 - FID - Frequency ID Control. */
744	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
745	/** Bit 2 - VID - Voltage ID Control. */
746	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
747	/** Bit 3 - TTP - THERMTRIP. */
748	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
749	/** Bit 4 - TM - Hardware Thermal Control. */
750	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
751	/** Bit 5 - STC - Software Thermal Control. */
752	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
753	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
754	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
755	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
756	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
757	/** Bit 8 - TSCINVAR - TSC Invariant. */
758	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
759	/** Bit 9 - CPB - TSC Invariant. */
760	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
761	/** Bit 10 - EffFreqRO - MPERF/APERF. */
762	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
763	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
764	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
765	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
766	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
767	/** @} */
768
769
770	/** @name CPUID AMD extended feature extensions ID (EBX).
771	* CPUID query with EAX=0x80000008.
772	* @{
773	*/
774	/** Bit 0 - CLZERO - Clear zero instruction. */
775	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
776	/** Bit 1 - IRPerf - Instructions retired count support. */
777	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
778	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
779	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
780	/* AMD pipeline length: 9 feature bits ;-) */
781	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
782	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
783	/** @} */
784
785
786	/** @name CPUID AMD SVM Feature information.
787	* CPUID query with EAX=0x8000000a.
788	* @{
789	*/
790	/** Bit 0 - NP - Nested Paging supported. */
791	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
792	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
793	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
794	/** Bit 2 - SVML - SVM locking bit supported. */
795	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
796	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
797	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
798	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
799	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
800	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
801	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
802	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
803	* VMCB.TLB_Control is supported. */
804	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
805	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
806	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
807	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
808	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
809	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
810	* intercept filter cycle count threshold. */
811	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
812	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
813	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
814	/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
815	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
816	/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
817	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
818	/** @} */
819
820
821	/** @name CR0
822	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
823	* reserved flags.
824	* @{ */
825	/** Bit 0 - PE - Protection Enabled */
826	#define X86_CR0_PE RT_BIT_32(0)
827	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
828	/** Bit 1 - MP - Monitor Coprocessor */
829	#define X86_CR0_MP RT_BIT_32(1)
830	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
831	/** Bit 2 - EM - Emulation. */
832	#define X86_CR0_EM RT_BIT_32(2)
833	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
834	/** Bit 3 - TS - Task Switch. */
835	#define X86_CR0_TS RT_BIT_32(3)
836	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
837	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
838	#define X86_CR0_ET RT_BIT_32(4)
839	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
840	/** Bit 5 - NE - Numeric error (486+). */
841	#define X86_CR0_NE RT_BIT_32(5)
842	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
843	/** Bit 16 - WP - Write Protect (486+). */
844	#define X86_CR0_WP RT_BIT_32(16)
845	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
846	/** Bit 18 - AM - Alignment Mask (486+). */
847	#define X86_CR0_AM RT_BIT_32(18)
848	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
849	/** Bit 29 - NW - Not Write-though (486+). */
850	#define X86_CR0_NW RT_BIT_32(29)
851	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
852	/** Bit 30 - WP - Cache Disable (486+). */
853	#define X86_CR0_CD RT_BIT_32(30)
854	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
855	/** Bit 31 - PG - Paging. */
856	#define X86_CR0_PG RT_BIT_32(31)
857	#define X86_CR0_PAGING RT_BIT_32(31)
858	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
859	/** @} */
860
861
862	/** @name CR3
863	* @{ */
864	/** Bit 3 - PWT - Page-level Writes Transparent. */
865	#define X86_CR3_PWT RT_BIT_32(3)
866	/** Bit 4 - PCD - Page-level Cache Disable. */
867	#define X86_CR3_PCD RT_BIT_32(4)
868	/** Bits 12-31 - - Page directory page number. */
869	#define X86_CR3_PAGE_MASK (0xfffff000)
870	/** Bits 5-31 - - PAE Page directory page number. */
871	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
872	/** Bits 12-51 - - AMD64 Page directory page number. */
873	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
874	/** @} */
875
876
877	/** @name CR4
878	* @{ */
879	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
880	#define X86_CR4_VME RT_BIT_32(0)
881	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
882	#define X86_CR4_PVI RT_BIT_32(1)
883	/** Bit 2 - TSD - Time Stamp Disable. */
884	#define X86_CR4_TSD RT_BIT_32(2)
885	/** Bit 3 - DE - Debugging Extensions. */
886	#define X86_CR4_DE RT_BIT_32(3)
887	/** Bit 4 - PSE - Page Size Extension. */
888	#define X86_CR4_PSE RT_BIT_32(4)
889	/** Bit 5 - PAE - Physical Address Extension. */
890	#define X86_CR4_PAE RT_BIT_32(5)
891	/** Bit 6 - MCE - Machine-Check Enable. */
892	#define X86_CR4_MCE RT_BIT_32(6)
893	/** Bit 7 - PGE - Page Global Enable. */
894	#define X86_CR4_PGE RT_BIT_32(7)
895	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
896	#define X86_CR4_PCE RT_BIT_32(8)
897	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
898	#define X86_CR4_OSFXSR RT_BIT_32(9)
899	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
900	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
901	/** Bit 13 - VMXE - VMX mode is enabled. */
902	#define X86_CR4_VMXE RT_BIT_32(13)
903	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
904	#define X86_CR4_SMXE RT_BIT_32(14)
905	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
906	#define X86_CR4_FSGSBASE RT_BIT_32(16)
907	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
908	#define X86_CR4_PCIDE RT_BIT_32(17)
909	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
910	* extended states. */
911	#define X86_CR4_OSXSAVE RT_BIT_32(18)
912	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
913	#define X86_CR4_SMEP RT_BIT_32(20)
914	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
915	#define X86_CR4_SMAP RT_BIT_32(21)
916	/** Bit 22 - PKE - Protection Key Enable. */
917	#define X86_CR4_PKE RT_BIT_32(22)
918	/** @} */
919
920
921	/** @name DR6
922	* @{ */
923	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
924	#define X86_DR6_B0 RT_BIT_32(0)
925	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
926	#define X86_DR6_B1 RT_BIT_32(1)
927	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
928	#define X86_DR6_B2 RT_BIT_32(2)
929	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
930	#define X86_DR6_B3 RT_BIT_32(3)
931	/** Mask of all the Bx bits. */
932	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
933	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
934	#define X86_DR6_BD RT_BIT_32(13)
935	/** Bit 14 - BS - Single step */
936	#define X86_DR6_BS RT_BIT_32(14)
937	/** Bit 15 - BT - Task switch. (TSS T bit.) */
938	#define X86_DR6_BT RT_BIT_32(15)
939	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
940	#define X86_DR6_RTM RT_BIT_32(16)
941	/** Value of DR6 after powerup/reset. */
942	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
943	/** Bits which must be 1s in DR6. */
944	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
945	/** Bits which must be 1s in DR6, when RTM is supported. */
946	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
947	/** Bits which must be 0s in DR6. */
948	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
949	/** Bits which must be 0s on writes to DR6. */
950	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
951	/** @} */
952
953	/** Get the DR6.Bx bit for a the given breakpoint. */
954	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
955
956
957	/** @name DR7
958	* @{ */
959	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
960	#define X86_DR7_L0 RT_BIT_32(0)
961	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
962	#define X86_DR7_G0 RT_BIT_32(1)
963	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
964	#define X86_DR7_L1 RT_BIT_32(2)
965	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
966	#define X86_DR7_G1 RT_BIT_32(3)
967	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
968	#define X86_DR7_L2 RT_BIT_32(4)
969	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
970	#define X86_DR7_G2 RT_BIT_32(5)
971	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
972	#define X86_DR7_L3 RT_BIT_32(6)
973	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
974	#define X86_DR7_G3 RT_BIT_32(7)
975	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
976	#define X86_DR7_LE RT_BIT_32(8)
977	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
978	#define X86_DR7_GE RT_BIT_32(9)
979
980	/** L0, L1, L2, and L3. */
981	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
982	/** L0, L1, L2, and L3. */
983	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
984
985	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
986	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
987	#define X86_DR7_RTM RT_BIT_32(11)
988	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
989	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
990	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
991	* instruction is executed.
992	* @see http://www.rcollins.org/secrets/DR7.html */
993	#define X86_DR7_ICE_IR RT_BIT_32(12)
994	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
995	* any DR register is accessed. */
996	#define X86_DR7_GD RT_BIT_32(13)
997	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
998	* Pentium. */
999	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1000	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1001	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1002	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1003	#define X86_DR7_RW0_MASK (3 << 16)
1004	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1005	#define X86_DR7_LEN0_MASK (3 << 18)
1006	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1007	#define X86_DR7_RW1_MASK (3 << 20)
1008	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1009	#define X86_DR7_LEN1_MASK (3 << 22)
1010	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1011	#define X86_DR7_RW2_MASK (3 << 24)
1012	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1013	#define X86_DR7_LEN2_MASK (3 << 26)
1014	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1015	#define X86_DR7_RW3_MASK (3 << 28)
1016	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1017	#define X86_DR7_LEN3_MASK (3 << 30)
1018
1019	/** Bits which reads as 1s. */
1020	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1021	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1022	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1023	/** Bits which must be 0s when writing to DR7. */
1024	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1025
1026	/** Calcs the L bit of Nth breakpoint.
1027	* @param iBp The breakpoint number [0..3].
1028	*/
1029	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1030
1031	/** Calcs the G bit of Nth breakpoint.
1032	* @param iBp The breakpoint number [0..3].
1033	*/
1034	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1035
1036	/** Calcs the L and G bits of Nth breakpoint.
1037	* @param iBp The breakpoint number [0..3].
1038	*/
1039	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1040
1041	/** @name Read/Write values.
1042	* @{ */
1043	/** Break on instruction fetch only. */
1044	#define X86_DR7_RW_EO UINT32_C(0)
1045	/** Break on write only. */
1046	#define X86_DR7_RW_WO UINT32_C(1)
1047	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1048	#define X86_DR7_RW_IO UINT32_C(2)
1049	/** Break on read or write (but not instruction fetches). */
1050	#define X86_DR7_RW_RW UINT32_C(3)
1051	/** @} */
1052
1053	/** Shifts a X86_DR7_RW_* value to its right place.
1054	* @param iBp The breakpoint number [0..3].
1055	* @param fRw One of the X86_DR7_RW_* value.
1056	*/
1057	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1058
1059	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1060	* one of the X86_DR7_RW_XXX constants).
1061	*
1062	* @returns X86_DR7_RW_XXX
1063	* @param uDR7 DR7 value
1064	* @param iBp The breakpoint number [0..3].
1065	*/
1066	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1067
1068	/** R/W0, R/W1, R/W2, and R/W3. */
1069	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1070
1071	#ifndef VBOX_FOR_DTRACE_LIB
1072	/** Checks if there are any I/O breakpoint types configured in the RW
1073	* registers. Does NOT check if these are enabled, sorry. */
1074	# define X86_DR7_ANY_RW_IO(uDR7) \
1075	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1076	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1077	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1078	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1079	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1080	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1081	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1082	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1083	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1084	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1085	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1086	#endif /* !VBOX_FOR_DTRACE_LIB */
1087
1088	/** @name Length values.
1089	* @{ */
1090	#define X86_DR7_LEN_BYTE UINT32_C(0)
1091	#define X86_DR7_LEN_WORD UINT32_C(1)
1092	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1093	#define X86_DR7_LEN_DWORD UINT32_C(3)
1094	/** @} */
1095
1096	/** Shifts a X86_DR7_LEN_* value to its right place.
1097	* @param iBp The breakpoint number [0..3].
1098	* @param cb One of the X86_DR7_LEN_* values.
1099	*/
1100	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1101
1102	/** Fetch the breakpoint length bits from the DR7 value.
1103	* @param uDR7 DR7 value
1104	* @param iBp The breakpoint number [0..3].
1105	*/
1106	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1107
1108	/** Mask used to check if any breakpoints are enabled. */
1109	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1110
1111	/** LEN0, LEN1, LEN2, and LEN3. */
1112	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1113	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1114	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1115
1116	/** Value of DR7 after powerup/reset. */
1117	#define X86_DR7_INIT_VAL 0x400
1118	/** @} */
1119
1120
1121	/** @name Machine Specific Registers
1122	* @{
1123	*/
1124	/** Machine check address register (P5). */
1125	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1126	/** Machine check type register (P5). */
1127	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1128	/** Time Stamp Counter. */
1129	#define MSR_IA32_TSC 0x10
1130	#define MSR_IA32_CESR UINT32_C(0x00000011)
1131	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1132	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1133
1134	#define MSR_IA32_PLATFORM_ID 0x17
1135
1136	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1137	# define MSR_IA32_APICBASE 0x1b
1138	/** Local APIC enabled. */
1139	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1140	/** X2APIC enabled (requires the EN bit to be set). */
1141	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1142	/** The processor is the boot strap processor (BSP). */
1143	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1144	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1145	* width. */
1146	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1147	/** The default physical base address of the APIC. */
1148	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1149	/** Gets the physical base address from the MSR. */
1150	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1151	#endif
1152
1153	/** Undocumented intel MSR for reporting thread and core counts.
1154	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1155	* first 16 bits is the thread count. The next 16 bits the core count, except
1156	* on Westmere where it seems it's only the next 4 bits for some reason. */
1157	#define MSR_CORE_THREAD_COUNT 0x35
1158
1159	/** CPU Feature control. */
1160	#define MSR_IA32_FEATURE_CONTROL 0x3A
1161	/** Feature control - Lock MSR from writes (R/W0). */
1162	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1163	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1164	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1165	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1166	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1167	/** Feature control - SENTER local functions enable (R/WL). */
1168	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1169	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1170	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1171	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1172	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1173	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1174	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1175	/** Feature control - SENTER global enable (R/WL). */
1176	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1177	/** Feature control - SGX launch control enable (R/WL). */
1178	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1179	/** Feature control - SGX global enable (R/WL). */
1180	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1181	/** Feature control - LMCE on (R/WL). */
1182	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1183
1184	/** Per-processor TSC adjust MSR. */
1185	#define MSR_IA32_TSC_ADJUST 0x3B
1186
1187	/** Spectre control register.
1188	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1189	#define MSR_IA32_SPEC_CTRL 0x48
1190	/** IBRS - Indirect branch restricted speculation. */
1191	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1192	/** STIBP - Single thread indirect branch predictors. */
1193	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1194
1195	/** Prediction command register.
1196	* Write only, logical processor scope, no state since write only. */
1197	#define MSR_IA32_PRED_CMD 0x49
1198	/** IBPB - Indirect branch prediction barrie when written as 1. */
1199	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1200
1201	/** BIOS update trigger (microcode update). */
1202	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1203
1204	/** BIOS update signature (microcode). */
1205	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1206
1207	/** SMM monitor control. */
1208	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1209	/** SMM control - Valid. */
1210	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1211	/** SMM control - VMXOFF unblocks SMI. */
1212	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1213	/** SMM control - MSEG base physical address. */
1214	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1215
1216	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1217	#define MSR_IA32_SMBASE 0x9E
1218
1219	/** General performance counter no. 0. */
1220	#define MSR_IA32_PMC0 0xC1
1221	/** General performance counter no. 1. */
1222	#define MSR_IA32_PMC1 0xC2
1223	/** General performance counter no. 2. */
1224	#define MSR_IA32_PMC2 0xC3
1225	/** General performance counter no. 3. */
1226	#define MSR_IA32_PMC3 0xC4
1227
1228	/** Nehalem power control. */
1229	#define MSR_IA32_PLATFORM_INFO 0xCE
1230
1231	/** Get FSB clock status (Intel-specific). */
1232	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1233
1234	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1235	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1236
1237	/** C0 Maximum Frequency Clock Count */
1238	#define MSR_IA32_MPERF 0xE7
1239	/** C0 Actual Frequency Clock Count */
1240	#define MSR_IA32_APERF 0xE8
1241
1242	/** MTRR Capabilities. */
1243	#define MSR_IA32_MTRR_CAP 0xFE
1244
1245	/** Architecture capabilities (bugfixes). */
1246	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1247	/** CPU is no subject to meltdown problems. */
1248	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1249	/** CPU has better IBRS and you can leave it on all the time. */
1250	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1251	/** CPU has return stack buffer (RSB) override. */
1252	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1253	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1254	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1255	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1256
1257	/** Flush command register. */
1258	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1259	/** Flush the level 1 data cache when this bit is written. */
1260	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1261
1262	/** Cache control/info. */
1263	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1264
1265	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1266	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1267	* R0 SS == CS + 8
1268	* R3 CS == CS + 16
1269	* R3 SS == CS + 24
1270	*/
1271	#define MSR_IA32_SYSENTER_CS 0x174
1272	/** SYSENTER_ESP - the R0 ESP. */
1273	#define MSR_IA32_SYSENTER_ESP 0x175
1274	/** SYSENTER_EIP - the R0 EIP. */
1275	#define MSR_IA32_SYSENTER_EIP 0x176
1276	#endif
1277
1278	/** Machine Check Global Capabilities Register. */
1279	#define MSR_IA32_MCG_CAP 0x179
1280	/** Machine Check Global Status Register. */
1281	#define MSR_IA32_MCG_STATUS 0x17A
1282	/** Machine Check Global Control Register. */
1283	#define MSR_IA32_MCG_CTRL 0x17B
1284
1285	/** Page Attribute Table. */
1286	#define MSR_IA32_CR_PAT 0x277
1287	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1288	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1289	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1290
1291	/** Performance counter MSRs. (Intel only) */
1292	#define MSR_IA32_PERFEVTSEL0 0x186
1293	#define MSR_IA32_PERFEVTSEL1 0x187
1294	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1295	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1296	* holds a ratio that Apple takes for TSC granularity.
1297	*
1298	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1299	#define MSR_FLEX_RATIO 0x194
1300	/** Performance state value and starting with Intel core more.
1301	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1302	#define MSR_IA32_PERF_STATUS 0x198
1303	#define MSR_IA32_PERF_CTL 0x199
1304	#define MSR_IA32_THERM_STATUS 0x19c
1305
1306	/** Enable misc. processor features (R/W). */
1307	#define MSR_IA32_MISC_ENABLE 0x1A0
1308	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1309	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1310	/** Automatic Thermal Control Circuit Enable (R/W). */
1311	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1312	/** Performance Monitoring Available (R). */
1313	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1314	/** Branch Trace Storage Unavailable (R/O). */
1315	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1316	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1317	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1318	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1319	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1320	/** If MONITOR/MWAIT is supported (R/W). */
1321	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1322	/** Limit CPUID Maxval to 3 leafs (R/W). */
1323	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1324	/** When set to 1, xTPR messages are disabled (R/W). */
1325	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1326	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1327	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1328
1329	/** Trace/Profile Resource Control (R/W) */
1330	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1331	/** Last branch record. */
1332	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1333	/** Branch trace flag (single step on branches). */
1334	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1335	/** Performance monitoring pin control (AMD only). */
1336	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1337	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1338	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1339	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1340	/** Trace message enable (Intel only). */
1341	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1342	/** Branch trace store (Intel only). */
1343	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1344	/** Branch trace interrupt (Intel only). */
1345	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1346	/** Branch trace off in privileged code (Intel only). */
1347	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1348	/** Branch trace off in user code (Intel only). */
1349	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1350	/** Freeze LBR on PMI flag (Intel only). */
1351	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1352	/** Freeze PERFMON on PMI flag (Intel only). */
1353	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1354	/** Freeze while SMM enabled (Intel only). */
1355	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1356	/** Advanced debugging of RTM regions (Intel only). */
1357	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1358	/** Debug control MSR valid bits (Intel only). */
1359	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1360	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1361	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1362	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1363	\| MSR_IA32_DEBUGCTL_RTM)
1364
1365	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1366	* related Xeons. */
1367	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1368	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1369	* @{ */
1370	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1371	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1372	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1373	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1374	/** @} */
1375
1376
1377	#define IA32_MTRR_PHYSBASE0 0x200
1378	#define IA32_MTRR_PHYSMASK0 0x201
1379	#define IA32_MTRR_PHYSBASE1 0x202
1380	#define IA32_MTRR_PHYSMASK1 0x203
1381	#define IA32_MTRR_PHYSBASE2 0x204
1382	#define IA32_MTRR_PHYSMASK2 0x205
1383	#define IA32_MTRR_PHYSBASE3 0x206
1384	#define IA32_MTRR_PHYSMASK3 0x207
1385	#define IA32_MTRR_PHYSBASE4 0x208
1386	#define IA32_MTRR_PHYSMASK4 0x209
1387	#define IA32_MTRR_PHYSBASE5 0x20a
1388	#define IA32_MTRR_PHYSMASK5 0x20b
1389	#define IA32_MTRR_PHYSBASE6 0x20c
1390	#define IA32_MTRR_PHYSMASK6 0x20d
1391	#define IA32_MTRR_PHYSBASE7 0x20e
1392	#define IA32_MTRR_PHYSMASK7 0x20f
1393	#define IA32_MTRR_PHYSBASE8 0x210
1394	#define IA32_MTRR_PHYSMASK8 0x211
1395	#define IA32_MTRR_PHYSBASE9 0x212
1396	#define IA32_MTRR_PHYSMASK9 0x213
1397
1398	/** Fixed range MTRRs.
1399	* @{ */
1400	#define IA32_MTRR_FIX64K_00000 0x250
1401	#define IA32_MTRR_FIX16K_80000 0x258
1402	#define IA32_MTRR_FIX16K_A0000 0x259
1403	#define IA32_MTRR_FIX4K_C0000 0x268
1404	#define IA32_MTRR_FIX4K_C8000 0x269
1405	#define IA32_MTRR_FIX4K_D0000 0x26a
1406	#define IA32_MTRR_FIX4K_D8000 0x26b
1407	#define IA32_MTRR_FIX4K_E0000 0x26c
1408	#define IA32_MTRR_FIX4K_E8000 0x26d
1409	#define IA32_MTRR_FIX4K_F0000 0x26e
1410	#define IA32_MTRR_FIX4K_F8000 0x26f
1411	/** @} */
1412
1413	/** MTRR Default Range. */
1414	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1415
1416	/** Global performance counter control facilities (Intel only). */
1417	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1418	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1419	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1420
1421	/** Precise Event Based sampling (Intel only). */
1422	#define MSR_IA32_PEBS_ENABLE 0x3F1
1423
1424	#define MSR_IA32_MC0_CTL 0x400
1425	#define MSR_IA32_MC0_STATUS 0x401
1426
1427	/** Basic VMX information. */
1428	#define MSR_IA32_VMX_BASIC 0x480
1429	/** Allowed settings for pin-based VM execution controls. */
1430	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1431	/** Allowed settings for proc-based VM execution controls. */
1432	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1433	/** Allowed settings for the VM-exit controls. */
1434	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1435	/** Allowed settings for the VM-entry controls. */
1436	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1437	/** Misc VMX info. */
1438	#define MSR_IA32_VMX_MISC 0x485
1439	/** Fixed cleared bits in CR0. */
1440	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1441	/** Fixed set bits in CR0. */
1442	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1443	/** Fixed cleared bits in CR4. */
1444	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1445	/** Fixed set bits in CR4. */
1446	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1447	/** Information for enumerating fields in the VMCS. */
1448	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1449	/** Allowed settings for secondary proc-based VM execution controls */
1450	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1451	/** EPT capabilities. */
1452	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1453	/** Allowed settings of all pin-based VM execution controls. */
1454	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1455	/** Allowed settings of all proc-based VM execution controls. */
1456	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1457	/** Allowed settings of all VMX exit controls. */
1458	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1459	/** Allowed settings of all VMX entry controls. */
1460	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1461	/** Allowed settings for the VM-function controls. */
1462	#define MSR_IA32_VMX_VMFUNC 0x491
1463
1464	/** Intel PT - Enable and control for trace packet generation. */
1465	#define MSR_IA32_RTIT_CTL 0x570
1466
1467	/** DS Save Area (R/W). */
1468	#define MSR_IA32_DS_AREA 0x600
1469	/** Running Average Power Limit (RAPL) power units. */
1470	#define MSR_RAPL_POWER_UNIT 0x606
1471
1472	/** X2APIC MSR range start. */
1473	#define MSR_IA32_X2APIC_START 0x800
1474	/** X2APIC MSR - APIC ID Register. */
1475	#define MSR_IA32_X2APIC_ID 0x802
1476	/** X2APIC MSR - APIC Version Register. */
1477	#define MSR_IA32_X2APIC_VERSION 0x803
1478	/** X2APIC MSR - Task Priority Register. */
1479	#define MSR_IA32_X2APIC_TPR 0x808
1480	/** X2APIC MSR - Processor Priority register. */
1481	#define MSR_IA32_X2APIC_PPR 0x80A
1482	/** X2APIC MSR - End Of Interrupt register. */
1483	#define MSR_IA32_X2APIC_EOI 0x80B
1484	/** X2APIC MSR - Logical Destination Register. */
1485	#define MSR_IA32_X2APIC_LDR 0x80D
1486	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1487	#define MSR_IA32_X2APIC_SVR 0x80F
1488	/** X2APIC MSR - In-service Register (bits 31:0). */
1489	#define MSR_IA32_X2APIC_ISR0 0x810
1490	/** X2APIC MSR - In-service Register (bits 63:32). */
1491	#define MSR_IA32_X2APIC_ISR1 0x811
1492	/** X2APIC MSR - In-service Register (bits 95:64). */
1493	#define MSR_IA32_X2APIC_ISR2 0x812
1494	/** X2APIC MSR - In-service Register (bits 127:96). */
1495	#define MSR_IA32_X2APIC_ISR3 0x813
1496	/** X2APIC MSR - In-service Register (bits 159:128). */
1497	#define MSR_IA32_X2APIC_ISR4 0x814
1498	/** X2APIC MSR - In-service Register (bits 191:160). */
1499	#define MSR_IA32_X2APIC_ISR5 0x815
1500	/** X2APIC MSR - In-service Register (bits 223:192). */
1501	#define MSR_IA32_X2APIC_ISR6 0x816
1502	/** X2APIC MSR - In-service Register (bits 255:224). */
1503	#define MSR_IA32_X2APIC_ISR7 0x817
1504	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1505	#define MSR_IA32_X2APIC_TMR0 0x818
1506	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1507	#define MSR_IA32_X2APIC_TMR1 0x819
1508	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1509	#define MSR_IA32_X2APIC_TMR2 0x81A
1510	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1511	#define MSR_IA32_X2APIC_TMR3 0x81B
1512	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1513	#define MSR_IA32_X2APIC_TMR4 0x81C
1514	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1515	#define MSR_IA32_X2APIC_TMR5 0x81D
1516	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1517	#define MSR_IA32_X2APIC_TMR6 0x81E
1518	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1519	#define MSR_IA32_X2APIC_TMR7 0x81F
1520	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1521	#define MSR_IA32_X2APIC_IRR0 0x820
1522	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1523	#define MSR_IA32_X2APIC_IRR1 0x821
1524	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1525	#define MSR_IA32_X2APIC_IRR2 0x822
1526	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1527	#define MSR_IA32_X2APIC_IRR3 0x823
1528	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1529	#define MSR_IA32_X2APIC_IRR4 0x824
1530	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1531	#define MSR_IA32_X2APIC_IRR5 0x825
1532	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1533	#define MSR_IA32_X2APIC_IRR6 0x826
1534	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1535	#define MSR_IA32_X2APIC_IRR7 0x827
1536	/** X2APIC MSR - Error Status Register. */
1537	#define MSR_IA32_X2APIC_ESR 0x828
1538	/** X2APIC MSR - LVT CMCI Register. */
1539	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1540	/** X2APIC MSR - Interrupt Command Register. */
1541	#define MSR_IA32_X2APIC_ICR 0x830
1542	/** X2APIC MSR - LVT Timer Register. */
1543	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1544	/** X2APIC MSR - LVT Thermal Sensor Register. */
1545	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1546	/** X2APIC MSR - LVT Performance Counter Register. */
1547	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1548	/** X2APIC MSR - LVT LINT0 Register. */
1549	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1550	/** X2APIC MSR - LVT LINT1 Register. */
1551	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1552	/** X2APIC MSR - LVT Error Register . */
1553	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1554	/** X2APIC MSR - Timer Initial Count Register. */
1555	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1556	/** X2APIC MSR - Timer Current Count Register. */
1557	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1558	/** X2APIC MSR - Timer Divide Configuration Register. */
1559	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1560	/** X2APIC MSR - Self IPI. */
1561	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1562	/** X2APIC MSR range end. */
1563	#define MSR_IA32_X2APIC_END 0xBFF
1564	/** X2APIC MSR - LVT start range. */
1565	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1566	/** X2APIC MSR - LVT end range (inclusive). */
1567	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1568
1569	/** K6 EFER - Extended Feature Enable Register. */
1570	#define MSR_K6_EFER UINT32_C(0xc0000080)
1571	/** @todo document EFER */
1572	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1573	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1574	/** Bit 8 - LME - Long mode enabled. (R/W) */
1575	#define MSR_K6_EFER_LME RT_BIT_32(8)
1576	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1577	/** Bit 10 - LMA - Long mode active. (R) */
1578	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1579	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1580	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1581	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1582	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1583	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1584	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1585	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1586	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1587	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1588	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1589	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1590	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1591	/** K6 STAR - SYSCALL/RET targets. */
1592	#define MSR_K6_STAR UINT32_C(0xc0000081)
1593	/** Shift value for getting the SYSRET CS and SS value. */
1594	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1595	/** Shift value for getting the SYSCALL CS and SS value. */
1596	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1597	/** Selector mask for use after shifting. */
1598	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1599	/** The mask which give the SYSCALL EIP. */
1600	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1601	/** K6 WHCR - Write Handling Control Register. */
1602	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1603	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1604	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1605	/** K6 PSOR - Processor State Observability Register. */
1606	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1607	/** K6 PFIR - Page Flush/Invalidate Register. */
1608	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1609
1610	/** Performance counter MSRs. (AMD only) */
1611	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1612	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1613	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1614	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1615	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1616	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1617	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1618	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1619
1620	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1621	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1622	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1623	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1624	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1625	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1626	/** K8 FS.base - The 64-bit base FS register. */
1627	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1628	/** K8 GS.base - The 64-bit base GS register. */
1629	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1630	/** K8 KernelGSbase - Used with SWAPGS. */
1631	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1632	/** K8 TSC_AUX - Used with RDTSCP. */
1633	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1634	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1635	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1636	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1637	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1638	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1639	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1640	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1641	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1642	/** North bridge config? See BIOS & Kernel dev guides for
1643	* details. */
1644	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1645
1646	/** Hypertransport interrupt pending register.
1647	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1648	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1649
1650	/** SVM Control. */
1651	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1652	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1653	* features. */
1654	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1655	/** If set, non-intercepted INIT signals are converted to \#SX
1656	* exceptions. */
1657	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1658	/** Disables A20 masking. */
1659	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1660	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1661	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1662	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1663	* clear, EFER.SVME can be written normally. */
1664	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1665
1666	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1667	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1668	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1669	* host state during world switch. */
1670	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1671
1672	/** @} */
1673
1674
1675	/** @name Page Table / Directory / Directory Pointers / L4.
1676	* @{
1677	*/
1678
1679	/** Page table/directory entry as an unsigned integer. */
1680	typedef uint32_t X86PGUINT;
1681	/** Pointer to a page table/directory table entry as an unsigned integer. */
1682	typedef X86PGUINT *PX86PGUINT;
1683	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1684	typedef X86PGUINT const *PCX86PGUINT;
1685
1686	/** Number of entries in a 32-bit PT/PD. */
1687	#define X86_PG_ENTRIES 1024
1688
1689
1690	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1691	typedef uint64_t X86PGPAEUINT;
1692	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1693	typedef X86PGPAEUINT *PX86PGPAEUINT;
1694	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1695	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1696
1697	/** Number of entries in a PAE PT/PD. */
1698	#define X86_PG_PAE_ENTRIES 512
1699	/** Number of entries in a PAE PDPT. */
1700	#define X86_PG_PAE_PDPE_ENTRIES 4
1701
1702	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1703	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1704	/** Number of entries in an AMD64 PDPT.
1705	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1706	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1707
1708	/** The size of a default page. */
1709	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1710	/** The page shift of a default page. */
1711	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1712	/** The default page offset mask. */
1713	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1714	/** The default page base mask for virtual addresses. */
1715	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1716	/** The default page base mask for virtual addresses - 32bit version. */
1717	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1718
1719	/** The size of a 4KB page. */
1720	#define X86_PAGE_4K_SIZE _4K
1721	/** The page shift of a 4KB page. */
1722	#define X86_PAGE_4K_SHIFT 12
1723	/** The 4KB page offset mask. */
1724	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1725	/** The 4KB page base mask for virtual addresses. */
1726	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1727	/** The 4KB page base mask for virtual addresses - 32bit version. */
1728	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1729
1730	/** The size of a 2MB page. */
1731	#define X86_PAGE_2M_SIZE _2M
1732	/** The page shift of a 2MB page. */
1733	#define X86_PAGE_2M_SHIFT 21
1734	/** The 2MB page offset mask. */
1735	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1736	/** The 2MB page base mask for virtual addresses. */
1737	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1738	/** The 2MB page base mask for virtual addresses - 32bit version. */
1739	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1740
1741	/** The size of a 4MB page. */
1742	#define X86_PAGE_4M_SIZE _4M
1743	/** The page shift of a 4MB page. */
1744	#define X86_PAGE_4M_SHIFT 22
1745	/** The 4MB page offset mask. */
1746	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1747	/** The 4MB page base mask for virtual addresses. */
1748	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1749	/** The 4MB page base mask for virtual addresses - 32bit version. */
1750	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1751
1752	/** The size of a 1GB page. */
1753	#define X86_PAGE_1G_SIZE _1G
1754	/** The page shift of a 1GB page. */
1755	#define X86_PAGE_1G_SHIFT 30
1756	/** The 1GB page offset mask. */
1757	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1758	/** The 1GB page base mask for virtual addresses. */
1759	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1760
1761	/**
1762	* Check if the given address is canonical.
1763	*/
1764	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1765
1766
1767	/** @name Page Table Entry
1768	* @{
1769	*/
1770	/** Bit 0 - P - Present bit. */
1771	#define X86_PTE_BIT_P 0
1772	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1773	#define X86_PTE_BIT_RW 1
1774	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1775	#define X86_PTE_BIT_US 2
1776	/** Bit 3 - PWT - Page level write thru bit. */
1777	#define X86_PTE_BIT_PWT 3
1778	/** Bit 4 - PCD - Page level cache disable bit. */
1779	#define X86_PTE_BIT_PCD 4
1780	/** Bit 5 - A - Access bit. */
1781	#define X86_PTE_BIT_A 5
1782	/** Bit 6 - D - Dirty bit. */
1783	#define X86_PTE_BIT_D 6
1784	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1785	#define X86_PTE_BIT_PAT 7
1786	/** Bit 8 - G - Global flag. */
1787	#define X86_PTE_BIT_G 8
1788	/** Bits 63 - NX - PAE/LM - No execution flag. */
1789	#define X86_PTE_PAE_BIT_NX 63
1790
1791	/** Bit 0 - P - Present bit mask. */
1792	#define X86_PTE_P RT_BIT_32(0)
1793	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1794	#define X86_PTE_RW RT_BIT_32(1)
1795	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1796	#define X86_PTE_US RT_BIT_32(2)
1797	/** Bit 3 - PWT - Page level write thru bit mask. */
1798	#define X86_PTE_PWT RT_BIT_32(3)
1799	/** Bit 4 - PCD - Page level cache disable bit mask. */
1800	#define X86_PTE_PCD RT_BIT_32(4)
1801	/** Bit 5 - A - Access bit mask. */
1802	#define X86_PTE_A RT_BIT_32(5)
1803	/** Bit 6 - D - Dirty bit mask. */
1804	#define X86_PTE_D RT_BIT_32(6)
1805	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1806	#define X86_PTE_PAT RT_BIT_32(7)
1807	/** Bit 8 - G - Global bit mask. */
1808	#define X86_PTE_G RT_BIT_32(8)
1809
1810	/** Bits 9-11 - - Available for use to system software. */
1811	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1812	/** Bits 12-31 - - Physical Page number of the next level. */
1813	#define X86_PTE_PG_MASK ( 0xfffff000 )
1814
1815	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1816	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1817	/** Bits 63 - NX - PAE/LM - No execution flag. */
1818	#define X86_PTE_PAE_NX RT_BIT_64(63)
1819	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1820	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1821	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1822	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1823	/** No bits - - LM - MBZ bits when NX is active. */
1824	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1825	/** Bits 63 - - LM - MBZ bits when no NX. */
1826	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1827
1828	/**
1829	* Page table entry.
1830	*/
1831	typedef struct X86PTEBITS
1832	{
1833	/** Flags whether(=1) or not the page is present. */
1834	uint32_t u1Present : 1;
1835	/** Read(=0) / Write(=1) flag. */
1836	uint32_t u1Write : 1;
1837	/** User(=1) / Supervisor (=0) flag. */
1838	uint32_t u1User : 1;
1839	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1840	uint32_t u1WriteThru : 1;
1841	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1842	uint32_t u1CacheDisable : 1;
1843	/** Accessed flag.
1844	* Indicates that the page have been read or written to. */
1845	uint32_t u1Accessed : 1;
1846	/** Dirty flag.
1847	* Indicates that the page has been written to. */
1848	uint32_t u1Dirty : 1;
1849	/** Reserved / If PAT enabled, bit 2 of the index. */
1850	uint32_t u1PAT : 1;
1851	/** Global flag. (Ignored in all but final level.) */
1852	uint32_t u1Global : 1;
1853	/** Available for use to system software. */
1854	uint32_t u3Available : 3;
1855	/** Physical Page number of the next level. */
1856	uint32_t u20PageNo : 20;
1857	} X86PTEBITS;
1858	#ifndef VBOX_FOR_DTRACE_LIB
1859	AssertCompileSize(X86PTEBITS, 4);
1860	#endif
1861	/** Pointer to a page table entry. */
1862	typedef X86PTEBITS *PX86PTEBITS;
1863	/** Pointer to a const page table entry. */
1864	typedef const X86PTEBITS *PCX86PTEBITS;
1865
1866	/**
1867	* Page table entry.
1868	*/
1869	typedef union X86PTE
1870	{
1871	/** Unsigned integer view */
1872	X86PGUINT u;
1873	/** Bit field view. */
1874	X86PTEBITS n;
1875	/** 32-bit view. */
1876	uint32_t au32[1];
1877	/** 16-bit view. */
1878	uint16_t au16[2];
1879	/** 8-bit view. */
1880	uint8_t au8[4];
1881	} X86PTE;
1882	#ifndef VBOX_FOR_DTRACE_LIB
1883	AssertCompileSize(X86PTE, 4);
1884	#endif
1885	/** Pointer to a page table entry. */
1886	typedef X86PTE *PX86PTE;
1887	/** Pointer to a const page table entry. */
1888	typedef const X86PTE *PCX86PTE;
1889
1890
1891	/**
1892	* PAE page table entry.
1893	*/
1894	typedef struct X86PTEPAEBITS
1895	{
1896	/** Flags whether(=1) or not the page is present. */
1897	uint32_t u1Present : 1;
1898	/** Read(=0) / Write(=1) flag. */
1899	uint32_t u1Write : 1;
1900	/** User(=1) / Supervisor(=0) flag. */
1901	uint32_t u1User : 1;
1902	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1903	uint32_t u1WriteThru : 1;
1904	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1905	uint32_t u1CacheDisable : 1;
1906	/** Accessed flag.
1907	* Indicates that the page have been read or written to. */
1908	uint32_t u1Accessed : 1;
1909	/** Dirty flag.
1910	* Indicates that the page has been written to. */
1911	uint32_t u1Dirty : 1;
1912	/** Reserved / If PAT enabled, bit 2 of the index. */
1913	uint32_t u1PAT : 1;
1914	/** Global flag. (Ignored in all but final level.) */
1915	uint32_t u1Global : 1;
1916	/** Available for use to system software. */
1917	uint32_t u3Available : 3;
1918	/** Physical Page number of the next level - Low Part. Don't use this. */
1919	uint32_t u20PageNoLow : 20;
1920	/** Physical Page number of the next level - High Part. Don't use this. */
1921	uint32_t u20PageNoHigh : 20;
1922	/** MBZ bits */
1923	uint32_t u11Reserved : 11;
1924	/** No Execute flag. */
1925	uint32_t u1NoExecute : 1;
1926	} X86PTEPAEBITS;
1927	#ifndef VBOX_FOR_DTRACE_LIB
1928	AssertCompileSize(X86PTEPAEBITS, 8);
1929	#endif
1930	/** Pointer to a page table entry. */
1931	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1932	/** Pointer to a page table entry. */
1933	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1934
1935	/**
1936	* PAE Page table entry.
1937	*/
1938	typedef union X86PTEPAE
1939	{
1940	/** Unsigned integer view */
1941	X86PGPAEUINT u;
1942	/** Bit field view. */
1943	X86PTEPAEBITS n;
1944	/** 32-bit view. */
1945	uint32_t au32[2];
1946	/** 16-bit view. */
1947	uint16_t au16[4];
1948	/** 8-bit view. */
1949	uint8_t au8[8];
1950	} X86PTEPAE;
1951	#ifndef VBOX_FOR_DTRACE_LIB
1952	AssertCompileSize(X86PTEPAE, 8);
1953	#endif
1954	/** Pointer to a PAE page table entry. */
1955	typedef X86PTEPAE *PX86PTEPAE;
1956	/** Pointer to a const PAE page table entry. */
1957	typedef const X86PTEPAE *PCX86PTEPAE;
1958	/** @} */
1959
1960	/**
1961	* Page table.
1962	*/
1963	typedef struct X86PT
1964	{
1965	/** PTE Array. */
1966	X86PTE a[X86_PG_ENTRIES];
1967	} X86PT;
1968	#ifndef VBOX_FOR_DTRACE_LIB
1969	AssertCompileSize(X86PT, 4096);
1970	#endif
1971	/** Pointer to a page table. */
1972	typedef X86PT *PX86PT;
1973	/** Pointer to a const page table. */
1974	typedef const X86PT *PCX86PT;
1975
1976	/** The page shift to get the PT index. */
1977	#define X86_PT_SHIFT 12
1978	/** The PT index mask (apply to a shifted page address). */
1979	#define X86_PT_MASK 0x3ff
1980
1981
1982	/**
1983	* Page directory.
1984	*/
1985	typedef struct X86PTPAE
1986	{
1987	/** PTE Array. */
1988	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1989	} X86PTPAE;
1990	#ifndef VBOX_FOR_DTRACE_LIB
1991	AssertCompileSize(X86PTPAE, 4096);
1992	#endif
1993	/** Pointer to a page table. */
1994	typedef X86PTPAE *PX86PTPAE;
1995	/** Pointer to a const page table. */
1996	typedef const X86PTPAE *PCX86PTPAE;
1997
1998	/** The page shift to get the PA PTE index. */
1999	#define X86_PT_PAE_SHIFT 12
2000	/** The PAE PT index mask (apply to a shifted page address). */
2001	#define X86_PT_PAE_MASK 0x1ff
2002
2003
2004	/** @name 4KB Page Directory Entry
2005	* @{
2006	*/
2007	/** Bit 0 - P - Present bit. */
2008	#define X86_PDE_P RT_BIT_32(0)
2009	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2010	#define X86_PDE_RW RT_BIT_32(1)
2011	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2012	#define X86_PDE_US RT_BIT_32(2)
2013	/** Bit 3 - PWT - Page level write thru bit. */
2014	#define X86_PDE_PWT RT_BIT_32(3)
2015	/** Bit 4 - PCD - Page level cache disable bit. */
2016	#define X86_PDE_PCD RT_BIT_32(4)
2017	/** Bit 5 - A - Access bit. */
2018	#define X86_PDE_A RT_BIT_32(5)
2019	/** Bit 7 - PS - Page size attribute.
2020	* Clear mean 4KB pages, set means large pages (2/4MB). */
2021	#define X86_PDE_PS RT_BIT_32(7)
2022	/** Bits 9-11 - - Available for use to system software. */
2023	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2024	/** Bits 12-31 - - Physical Page number of the next level. */
2025	#define X86_PDE_PG_MASK ( 0xfffff000 )
2026
2027	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2028	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2029	/** Bits 63 - NX - PAE/LM - No execution flag. */
2030	#define X86_PDE_PAE_NX RT_BIT_64(63)
2031	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2032	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2033	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2034	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2035	/** Bit 7 - - LM - MBZ bits when NX is active. */
2036	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2037	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2038	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2039
2040	/**
2041	* Page directory entry.
2042	*/
2043	typedef struct X86PDEBITS
2044	{
2045	/** Flags whether(=1) or not the page is present. */
2046	uint32_t u1Present : 1;
2047	/** Read(=0) / Write(=1) flag. */
2048	uint32_t u1Write : 1;
2049	/** User(=1) / Supervisor (=0) flag. */
2050	uint32_t u1User : 1;
2051	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2052	uint32_t u1WriteThru : 1;
2053	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2054	uint32_t u1CacheDisable : 1;
2055	/** Accessed flag.
2056	* Indicates that the page has been read or written to. */
2057	uint32_t u1Accessed : 1;
2058	/** Reserved / Ignored (dirty bit). */
2059	uint32_t u1Reserved0 : 1;
2060	/** Size bit if PSE is enabled - in any event it's 0. */
2061	uint32_t u1Size : 1;
2062	/** Reserved / Ignored (global bit). */
2063	uint32_t u1Reserved1 : 1;
2064	/** Available for use to system software. */
2065	uint32_t u3Available : 3;
2066	/** Physical Page number of the next level. */
2067	uint32_t u20PageNo : 20;
2068	} X86PDEBITS;
2069	#ifndef VBOX_FOR_DTRACE_LIB
2070	AssertCompileSize(X86PDEBITS, 4);
2071	#endif
2072	/** Pointer to a page directory entry. */
2073	typedef X86PDEBITS *PX86PDEBITS;
2074	/** Pointer to a const page directory entry. */
2075	typedef const X86PDEBITS *PCX86PDEBITS;
2076
2077
2078	/**
2079	* PAE page directory entry.
2080	*/
2081	typedef struct X86PDEPAEBITS
2082	{
2083	/** Flags whether(=1) or not the page is present. */
2084	uint32_t u1Present : 1;
2085	/** Read(=0) / Write(=1) flag. */
2086	uint32_t u1Write : 1;
2087	/** User(=1) / Supervisor (=0) flag. */
2088	uint32_t u1User : 1;
2089	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2090	uint32_t u1WriteThru : 1;
2091	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2092	uint32_t u1CacheDisable : 1;
2093	/** Accessed flag.
2094	* Indicates that the page has been read or written to. */
2095	uint32_t u1Accessed : 1;
2096	/** Reserved / Ignored (dirty bit). */
2097	uint32_t u1Reserved0 : 1;
2098	/** Size bit if PSE is enabled - in any event it's 0. */
2099	uint32_t u1Size : 1;
2100	/** Reserved / Ignored (global bit). / */
2101	uint32_t u1Reserved1 : 1;
2102	/** Available for use to system software. */
2103	uint32_t u3Available : 3;
2104	/** Physical Page number of the next level - Low Part. Don't use! */
2105	uint32_t u20PageNoLow : 20;
2106	/** Physical Page number of the next level - High Part. Don't use! */
2107	uint32_t u20PageNoHigh : 20;
2108	/** MBZ bits */
2109	uint32_t u11Reserved : 11;
2110	/** No Execute flag. */
2111	uint32_t u1NoExecute : 1;
2112	} X86PDEPAEBITS;
2113	#ifndef VBOX_FOR_DTRACE_LIB
2114	AssertCompileSize(X86PDEPAEBITS, 8);
2115	#endif
2116	/** Pointer to a page directory entry. */
2117	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2118	/** Pointer to a const page directory entry. */
2119	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2120
2121	/** @} */
2122
2123
2124	/** @name 2/4MB Page Directory Entry
2125	* @{
2126	*/
2127	/** Bit 0 - P - Present bit. */
2128	#define X86_PDE4M_P RT_BIT_32(0)
2129	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2130	#define X86_PDE4M_RW RT_BIT_32(1)
2131	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2132	#define X86_PDE4M_US RT_BIT_32(2)
2133	/** Bit 3 - PWT - Page level write thru bit. */
2134	#define X86_PDE4M_PWT RT_BIT_32(3)
2135	/** Bit 4 - PCD - Page level cache disable bit. */
2136	#define X86_PDE4M_PCD RT_BIT_32(4)
2137	/** Bit 5 - A - Access bit. */
2138	#define X86_PDE4M_A RT_BIT_32(5)
2139	/** Bit 6 - D - Dirty bit. */
2140	#define X86_PDE4M_D RT_BIT_32(6)
2141	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2142	#define X86_PDE4M_PS RT_BIT_32(7)
2143	/** Bit 8 - G - Global flag. */
2144	#define X86_PDE4M_G RT_BIT_32(8)
2145	/** Bits 9-11 - AVL - Available for use to system software. */
2146	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2147	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2148	#define X86_PDE4M_PAT RT_BIT_32(12)
2149	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2150	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2151	/** Bits 22-31 - - Physical Page number. */
2152	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2153	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2154	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2155	/** The number of bits to the high part of the page number. */
2156	#define X86_PDE4M_PG_HIGH_SHIFT 19
2157	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2158	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2159
2160	/** Bits 21-51 - - PAE/LM - Physical Page number.
2161	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2162	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2163	/** Bits 63 - NX - PAE/LM - No execution flag. */
2164	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2165	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2166	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2167	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2168	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2169	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2170	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2171	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2172	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2173
2174	/**
2175	* 4MB page directory entry.
2176	*/
2177	typedef struct X86PDE4MBITS
2178	{
2179	/** Flags whether(=1) or not the page is present. */
2180	uint32_t u1Present : 1;
2181	/** Read(=0) / Write(=1) flag. */
2182	uint32_t u1Write : 1;
2183	/** User(=1) / Supervisor (=0) flag. */
2184	uint32_t u1User : 1;
2185	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2186	uint32_t u1WriteThru : 1;
2187	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2188	uint32_t u1CacheDisable : 1;
2189	/** Accessed flag.
2190	* Indicates that the page have been read or written to. */
2191	uint32_t u1Accessed : 1;
2192	/** Dirty flag.
2193	* Indicates that the page has been written to. */
2194	uint32_t u1Dirty : 1;
2195	/** Page size flag - always 1 for 4MB entries. */
2196	uint32_t u1Size : 1;
2197	/** Global flag. */
2198	uint32_t u1Global : 1;
2199	/** Available for use to system software. */
2200	uint32_t u3Available : 3;
2201	/** Reserved / If PAT enabled, bit 2 of the index. */
2202	uint32_t u1PAT : 1;
2203	/** Bits 32-39 of the page number on AMD64.
2204	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2205	uint32_t u8PageNoHigh : 8;
2206	/** Reserved. */
2207	uint32_t u1Reserved : 1;
2208	/** Physical Page number of the page. */
2209	uint32_t u10PageNo : 10;
2210	} X86PDE4MBITS;
2211	#ifndef VBOX_FOR_DTRACE_LIB
2212	AssertCompileSize(X86PDE4MBITS, 4);
2213	#endif
2214	/** Pointer to a page table entry. */
2215	typedef X86PDE4MBITS *PX86PDE4MBITS;
2216	/** Pointer to a const page table entry. */
2217	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2218
2219
2220	/**
2221	* 2MB PAE page directory entry.
2222	*/
2223	typedef struct X86PDE2MPAEBITS
2224	{
2225	/** Flags whether(=1) or not the page is present. */
2226	uint32_t u1Present : 1;
2227	/** Read(=0) / Write(=1) flag. */
2228	uint32_t u1Write : 1;
2229	/** User(=1) / Supervisor(=0) flag. */
2230	uint32_t u1User : 1;
2231	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2232	uint32_t u1WriteThru : 1;
2233	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2234	uint32_t u1CacheDisable : 1;
2235	/** Accessed flag.
2236	* Indicates that the page have been read or written to. */
2237	uint32_t u1Accessed : 1;
2238	/** Dirty flag.
2239	* Indicates that the page has been written to. */
2240	uint32_t u1Dirty : 1;
2241	/** Page size flag - always 1 for 2MB entries. */
2242	uint32_t u1Size : 1;
2243	/** Global flag. */
2244	uint32_t u1Global : 1;
2245	/** Available for use to system software. */
2246	uint32_t u3Available : 3;
2247	/** Reserved / If PAT enabled, bit 2 of the index. */
2248	uint32_t u1PAT : 1;
2249	/** Reserved. */
2250	uint32_t u9Reserved : 9;
2251	/** Physical Page number of the next level - Low part. Don't use! */
2252	uint32_t u10PageNoLow : 10;
2253	/** Physical Page number of the next level - High part. Don't use! */
2254	uint32_t u20PageNoHigh : 20;
2255	/** MBZ bits */
2256	uint32_t u11Reserved : 11;
2257	/** No Execute flag. */
2258	uint32_t u1NoExecute : 1;
2259	} X86PDE2MPAEBITS;
2260	#ifndef VBOX_FOR_DTRACE_LIB
2261	AssertCompileSize(X86PDE2MPAEBITS, 8);
2262	#endif
2263	/** Pointer to a 2MB PAE page table entry. */
2264	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2265	/** Pointer to a 2MB PAE page table entry. */
2266	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2267
2268	/** @} */
2269
2270	/**
2271	* Page directory entry.
2272	*/
2273	typedef union X86PDE
2274	{
2275	/** Unsigned integer view. */
2276	X86PGUINT u;
2277	/** Normal view. */
2278	X86PDEBITS n;
2279	/** 4MB view (big). */
2280	X86PDE4MBITS b;
2281	/** 8 bit unsigned integer view. */
2282	uint8_t au8[4];
2283	/** 16 bit unsigned integer view. */
2284	uint16_t au16[2];
2285	/** 32 bit unsigned integer view. */
2286	uint32_t au32[1];
2287	} X86PDE;
2288	#ifndef VBOX_FOR_DTRACE_LIB
2289	AssertCompileSize(X86PDE, 4);
2290	#endif
2291	/** Pointer to a page directory entry. */
2292	typedef X86PDE *PX86PDE;
2293	/** Pointer to a const page directory entry. */
2294	typedef const X86PDE *PCX86PDE;
2295
2296	/**
2297	* PAE page directory entry.
2298	*/
2299	typedef union X86PDEPAE
2300	{
2301	/** Unsigned integer view. */
2302	X86PGPAEUINT u;
2303	/** Normal view. */
2304	X86PDEPAEBITS n;
2305	/** 2MB page view (big). */
2306	X86PDE2MPAEBITS b;
2307	/** 8 bit unsigned integer view. */
2308	uint8_t au8[8];
2309	/** 16 bit unsigned integer view. */
2310	uint16_t au16[4];
2311	/** 32 bit unsigned integer view. */
2312	uint32_t au32[2];
2313	} X86PDEPAE;
2314	#ifndef VBOX_FOR_DTRACE_LIB
2315	AssertCompileSize(X86PDEPAE, 8);
2316	#endif
2317	/** Pointer to a page directory entry. */
2318	typedef X86PDEPAE *PX86PDEPAE;
2319	/** Pointer to a const page directory entry. */
2320	typedef const X86PDEPAE *PCX86PDEPAE;
2321
2322	/**
2323	* Page directory.
2324	*/
2325	typedef struct X86PD
2326	{
2327	/** PDE Array. */
2328	X86PDE a[X86_PG_ENTRIES];
2329	} X86PD;
2330	#ifndef VBOX_FOR_DTRACE_LIB
2331	AssertCompileSize(X86PD, 4096);
2332	#endif
2333	/** Pointer to a page directory. */
2334	typedef X86PD *PX86PD;
2335	/** Pointer to a const page directory. */
2336	typedef const X86PD *PCX86PD;
2337
2338	/** The page shift to get the PD index. */
2339	#define X86_PD_SHIFT 22
2340	/** The PD index mask (apply to a shifted page address). */
2341	#define X86_PD_MASK 0x3ff
2342
2343
2344	/**
2345	* PAE page directory.
2346	*/
2347	typedef struct X86PDPAE
2348	{
2349	/** PDE Array. */
2350	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2351	} X86PDPAE;
2352	#ifndef VBOX_FOR_DTRACE_LIB
2353	AssertCompileSize(X86PDPAE, 4096);
2354	#endif
2355	/** Pointer to a PAE page directory. */
2356	typedef X86PDPAE *PX86PDPAE;
2357	/** Pointer to a const PAE page directory. */
2358	typedef const X86PDPAE *PCX86PDPAE;
2359
2360	/** The page shift to get the PAE PD index. */
2361	#define X86_PD_PAE_SHIFT 21
2362	/** The PAE PD index mask (apply to a shifted page address). */
2363	#define X86_PD_PAE_MASK 0x1ff
2364
2365
2366	/** @name Page Directory Pointer Table Entry (PAE)
2367	* @{
2368	*/
2369	/** Bit 0 - P - Present bit. */
2370	#define X86_PDPE_P RT_BIT_32(0)
2371	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2372	#define X86_PDPE_RW RT_BIT_32(1)
2373	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2374	#define X86_PDPE_US RT_BIT_32(2)
2375	/** Bit 3 - PWT - Page level write thru bit. */
2376	#define X86_PDPE_PWT RT_BIT_32(3)
2377	/** Bit 4 - PCD - Page level cache disable bit. */
2378	#define X86_PDPE_PCD RT_BIT_32(4)
2379	/** Bit 5 - A - Access bit. Long Mode only. */
2380	#define X86_PDPE_A RT_BIT_32(5)
2381	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2382	#define X86_PDPE_LM_PS RT_BIT_32(7)
2383	/** Bits 9-11 - - Available for use to system software. */
2384	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2385	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2386	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2387	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2388	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2389	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2390	#define X86_PDPE_LM_NX RT_BIT_64(63)
2391	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2392	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2393	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2394	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2395	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2396	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2397	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2398	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2399
2400
2401	/**
2402	* Page directory pointer table entry.
2403	*/
2404	typedef struct X86PDPEBITS
2405	{
2406	/** Flags whether(=1) or not the page is present. */
2407	uint32_t u1Present : 1;
2408	/** Chunk of reserved bits. */
2409	uint32_t u2Reserved : 2;
2410	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2411	uint32_t u1WriteThru : 1;
2412	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2413	uint32_t u1CacheDisable : 1;
2414	/** Chunk of reserved bits. */
2415	uint32_t u4Reserved : 4;
2416	/** Available for use to system software. */
2417	uint32_t u3Available : 3;
2418	/** Physical Page number of the next level - Low Part. Don't use! */
2419	uint32_t u20PageNoLow : 20;
2420	/** Physical Page number of the next level - High Part. Don't use! */
2421	uint32_t u20PageNoHigh : 20;
2422	/** MBZ bits */
2423	uint32_t u12Reserved : 12;
2424	} X86PDPEBITS;
2425	#ifndef VBOX_FOR_DTRACE_LIB
2426	AssertCompileSize(X86PDPEBITS, 8);
2427	#endif
2428	/** Pointer to a page directory pointer table entry. */
2429	typedef X86PDPEBITS *PX86PTPEBITS;
2430	/** Pointer to a const page directory pointer table entry. */
2431	typedef const X86PDPEBITS *PCX86PTPEBITS;
2432
2433	/**
2434	* Page directory pointer table entry. AMD64 version
2435	*/
2436	typedef struct X86PDPEAMD64BITS
2437	{
2438	/** Flags whether(=1) or not the page is present. */
2439	uint32_t u1Present : 1;
2440	/** Read(=0) / Write(=1) flag. */
2441	uint32_t u1Write : 1;
2442	/** User(=1) / Supervisor (=0) flag. */
2443	uint32_t u1User : 1;
2444	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2445	uint32_t u1WriteThru : 1;
2446	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2447	uint32_t u1CacheDisable : 1;
2448	/** Accessed flag.
2449	* Indicates that the page have been read or written to. */
2450	uint32_t u1Accessed : 1;
2451	/** Chunk of reserved bits. */
2452	uint32_t u3Reserved : 3;
2453	/** Available for use to system software. */
2454	uint32_t u3Available : 3;
2455	/** Physical Page number of the next level - Low Part. Don't use! */
2456	uint32_t u20PageNoLow : 20;
2457	/** Physical Page number of the next level - High Part. Don't use! */
2458	uint32_t u20PageNoHigh : 20;
2459	/** MBZ bits */
2460	uint32_t u11Reserved : 11;
2461	/** No Execute flag. */
2462	uint32_t u1NoExecute : 1;
2463	} X86PDPEAMD64BITS;
2464	#ifndef VBOX_FOR_DTRACE_LIB
2465	AssertCompileSize(X86PDPEAMD64BITS, 8);
2466	#endif
2467	/** Pointer to a page directory pointer table entry. */
2468	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2469	/** Pointer to a const page directory pointer table entry. */
2470	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2471
2472	/**
2473	* Page directory pointer table entry for 1GB page. (AMD64 only)
2474	*/
2475	typedef struct X86PDPE1GB
2476	{
2477	/** 0: Flags whether(=1) or not the page is present. */
2478	uint32_t u1Present : 1;
2479	/** 1: Read(=0) / Write(=1) flag. */
2480	uint32_t u1Write : 1;
2481	/** 2: User(=1) / Supervisor (=0) flag. */
2482	uint32_t u1User : 1;
2483	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2484	uint32_t u1WriteThru : 1;
2485	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2486	uint32_t u1CacheDisable : 1;
2487	/** 5: Accessed flag.
2488	* Indicates that the page have been read or written to. */
2489	uint32_t u1Accessed : 1;
2490	/** 6: Dirty flag for 1GB pages. */
2491	uint32_t u1Dirty : 1;
2492	/** 7: Indicates 1GB page if set. */
2493	uint32_t u1Size : 1;
2494	/** 8: Global 1GB page. */
2495	uint32_t u1Global: 1;
2496	/** 9-11: Available for use to system software. */
2497	uint32_t u3Available : 3;
2498	/** 12: PAT bit for 1GB page. */
2499	uint32_t u1PAT : 1;
2500	/** 13-29: MBZ bits. */
2501	uint32_t u17Reserved : 17;
2502	/** 30-31: Physical page number - Low Part. Don't use! */
2503	uint32_t u2PageNoLow : 2;
2504	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2505	uint32_t u20PageNoHigh : 20;
2506	/** 52-62: MBZ bits */
2507	uint32_t u11Reserved : 11;
2508	/** 63: No Execute flag. */
2509	uint32_t u1NoExecute : 1;
2510	} X86PDPE1GB;
2511	#ifndef VBOX_FOR_DTRACE_LIB
2512	AssertCompileSize(X86PDPE1GB, 8);
2513	#endif
2514	/** Pointer to a page directory pointer table entry for a 1GB page. */
2515	typedef X86PDPE1GB *PX86PDPE1GB;
2516	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2517	typedef const X86PDPE1GB *PCX86PDPE1GB;
2518
2519	/**
2520	* Page directory pointer table entry.
2521	*/
2522	typedef union X86PDPE
2523	{
2524	/** Unsigned integer view. */
2525	X86PGPAEUINT u;
2526	/** Normal view. */
2527	X86PDPEBITS n;
2528	/** AMD64 view. */
2529	X86PDPEAMD64BITS lm;
2530	/** AMD64 big view. */
2531	X86PDPE1GB b;
2532	/** 8 bit unsigned integer view. */
2533	uint8_t au8[8];
2534	/** 16 bit unsigned integer view. */
2535	uint16_t au16[4];
2536	/** 32 bit unsigned integer view. */
2537	uint32_t au32[2];
2538	} X86PDPE;
2539	#ifndef VBOX_FOR_DTRACE_LIB
2540	AssertCompileSize(X86PDPE, 8);
2541	#endif
2542	/** Pointer to a page directory pointer table entry. */
2543	typedef X86PDPE *PX86PDPE;
2544	/** Pointer to a const page directory pointer table entry. */
2545	typedef const X86PDPE *PCX86PDPE;
2546
2547
2548	/**
2549	* Page directory pointer table.
2550	*/
2551	typedef struct X86PDPT
2552	{
2553	/** PDE Array. */
2554	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2555	} X86PDPT;
2556	#ifndef VBOX_FOR_DTRACE_LIB
2557	AssertCompileSize(X86PDPT, 4096);
2558	#endif
2559	/** Pointer to a page directory pointer table. */
2560	typedef X86PDPT *PX86PDPT;
2561	/** Pointer to a const page directory pointer table. */
2562	typedef const X86PDPT *PCX86PDPT;
2563
2564	/** The page shift to get the PDPT index. */
2565	#define X86_PDPT_SHIFT 30
2566	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2567	#define X86_PDPT_MASK_PAE 0x3
2568	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2569	#define X86_PDPT_MASK_AMD64 0x1ff
2570
2571	/** @} */
2572
2573
2574	/** @name Page Map Level-4 Entry (Long Mode PAE)
2575	* @{
2576	*/
2577	/** Bit 0 - P - Present bit. */
2578	#define X86_PML4E_P RT_BIT_32(0)
2579	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2580	#define X86_PML4E_RW RT_BIT_32(1)
2581	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2582	#define X86_PML4E_US RT_BIT_32(2)
2583	/** Bit 3 - PWT - Page level write thru bit. */
2584	#define X86_PML4E_PWT RT_BIT_32(3)
2585	/** Bit 4 - PCD - Page level cache disable bit. */
2586	#define X86_PML4E_PCD RT_BIT_32(4)
2587	/** Bit 5 - A - Access bit. */
2588	#define X86_PML4E_A RT_BIT_32(5)
2589	/** Bits 9-11 - - Available for use to system software. */
2590	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2591	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2592	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2593	/** Bits 8, 7 - - MBZ bits when NX is active. */
2594	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2595	/** Bits 63, 7 - - MBZ bits when no NX. */
2596	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2597	/** Bits 63 - NX - PAE - No execution flag. */
2598	#define X86_PML4E_NX RT_BIT_64(63)
2599
2600	/**
2601	* Page Map Level-4 Entry
2602	*/
2603	typedef struct X86PML4EBITS
2604	{
2605	/** Flags whether(=1) or not the page is present. */
2606	uint32_t u1Present : 1;
2607	/** Read(=0) / Write(=1) flag. */
2608	uint32_t u1Write : 1;
2609	/** User(=1) / Supervisor (=0) flag. */
2610	uint32_t u1User : 1;
2611	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2612	uint32_t u1WriteThru : 1;
2613	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2614	uint32_t u1CacheDisable : 1;
2615	/** Accessed flag.
2616	* Indicates that the page have been read or written to. */
2617	uint32_t u1Accessed : 1;
2618	/** Chunk of reserved bits. */
2619	uint32_t u3Reserved : 3;
2620	/** Available for use to system software. */
2621	uint32_t u3Available : 3;
2622	/** Physical Page number of the next level - Low Part. Don't use! */
2623	uint32_t u20PageNoLow : 20;
2624	/** Physical Page number of the next level - High Part. Don't use! */
2625	uint32_t u20PageNoHigh : 20;
2626	/** MBZ bits */
2627	uint32_t u11Reserved : 11;
2628	/** No Execute flag. */
2629	uint32_t u1NoExecute : 1;
2630	} X86PML4EBITS;
2631	#ifndef VBOX_FOR_DTRACE_LIB
2632	AssertCompileSize(X86PML4EBITS, 8);
2633	#endif
2634	/** Pointer to a page map level-4 entry. */
2635	typedef X86PML4EBITS *PX86PML4EBITS;
2636	/** Pointer to a const page map level-4 entry. */
2637	typedef const X86PML4EBITS *PCX86PML4EBITS;
2638
2639	/**
2640	* Page Map Level-4 Entry.
2641	*/
2642	typedef union X86PML4E
2643	{
2644	/** Unsigned integer view. */
2645	X86PGPAEUINT u;
2646	/** Normal view. */
2647	X86PML4EBITS n;
2648	/** 8 bit unsigned integer view. */
2649	uint8_t au8[8];
2650	/** 16 bit unsigned integer view. */
2651	uint16_t au16[4];
2652	/** 32 bit unsigned integer view. */
2653	uint32_t au32[2];
2654	} X86PML4E;
2655	#ifndef VBOX_FOR_DTRACE_LIB
2656	AssertCompileSize(X86PML4E, 8);
2657	#endif
2658	/** Pointer to a page map level-4 entry. */
2659	typedef X86PML4E *PX86PML4E;
2660	/** Pointer to a const page map level-4 entry. */
2661	typedef const X86PML4E *PCX86PML4E;
2662
2663
2664	/**
2665	* Page Map Level-4.
2666	*/
2667	typedef struct X86PML4
2668	{
2669	/** PDE Array. */
2670	X86PML4E a[X86_PG_PAE_ENTRIES];
2671	} X86PML4;
2672	#ifndef VBOX_FOR_DTRACE_LIB
2673	AssertCompileSize(X86PML4, 4096);
2674	#endif
2675	/** Pointer to a page map level-4. */
2676	typedef X86PML4 *PX86PML4;
2677	/** Pointer to a const page map level-4. */
2678	typedef const X86PML4 *PCX86PML4;
2679
2680	/** The page shift to get the PML4 index. */
2681	#define X86_PML4_SHIFT 39
2682	/** The PML4 index mask (apply to a shifted page address). */
2683	#define X86_PML4_MASK 0x1ff
2684
2685	/** @} */
2686
2687	/** @} */
2688
2689	/**
2690	* Intel PCID invalidation types.
2691	*/
2692	/** Individual address invalidation. */
2693	#define X86_INVPCID_TYPE_INDV_ADDR 0
2694	/** Single-context invalidation. */
2695	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2696	/** All-context including globals invalidation. */
2697	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2698	/** All-context excluding globals invalidation. */
2699	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2700	/** The maximum valid invalidation type value. */
2701	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2702
2703	/**
2704	* 32-bit protected mode FSTENV image.
2705	*/
2706	typedef struct X86FSTENV32P
2707	{
2708	uint16_t FCW;
2709	uint16_t padding1;
2710	uint16_t FSW;
2711	uint16_t padding2;
2712	uint16_t FTW;
2713	uint16_t padding3;
2714	uint32_t FPUIP;
2715	uint16_t FPUCS;
2716	uint16_t FOP;
2717	uint32_t FPUDP;
2718	uint16_t FPUDS;
2719	uint16_t padding4;
2720	} X86FSTENV32P;
2721	/** Pointer to a 32-bit protected mode FSTENV image. */
2722	typedef X86FSTENV32P *PX86FSTENV32P;
2723	/** Pointer to a const 32-bit protected mode FSTENV image. */
2724	typedef X86FSTENV32P const *PCX86FSTENV32P;
2725
2726
2727	/**
2728	* 80-bit MMX/FPU register type.
2729	*/
2730	typedef struct X86FPUMMX
2731	{
2732	uint8_t reg[10];
2733	} X86FPUMMX;
2734	#ifndef VBOX_FOR_DTRACE_LIB
2735	AssertCompileSize(X86FPUMMX, 10);
2736	#endif
2737	/** Pointer to a 80-bit MMX/FPU register type. */
2738	typedef X86FPUMMX *PX86FPUMMX;
2739	/** Pointer to a const 80-bit MMX/FPU register type. */
2740	typedef const X86FPUMMX *PCX86FPUMMX;
2741
2742	/** FPU (x87) register. */
2743	typedef union X86FPUREG
2744	{
2745	/** MMX view. */
2746	uint64_t mmx;
2747	/** FPU view - todo. */
2748	X86FPUMMX fpu;
2749	/** Extended precision floating point view. */
2750	RTFLOAT80U r80;
2751	/** Extended precision floating point view v2 */
2752	RTFLOAT80U2 r80Ex;
2753	/** 8-bit view. */
2754	uint8_t au8[16];
2755	/** 16-bit view. */
2756	uint16_t au16[8];
2757	/** 32-bit view. */
2758	uint32_t au32[4];
2759	/** 64-bit view. */
2760	uint64_t au64[2];
2761	/** 128-bit view. (yeah, very helpful) */
2762	uint128_t au128[1];
2763	} X86FPUREG;
2764	#ifndef VBOX_FOR_DTRACE_LIB
2765	AssertCompileSize(X86FPUREG, 16);
2766	#endif
2767	/** Pointer to a FPU register. */
2768	typedef X86FPUREG *PX86FPUREG;
2769	/** Pointer to a const FPU register. */
2770	typedef X86FPUREG const *PCX86FPUREG;
2771
2772	/**
2773	* XMM register union.
2774	*/
2775	typedef union X86XMMREG
2776	{
2777	/** XMM Register view. */
2778	uint128_t xmm;
2779	/** 8-bit view. */
2780	uint8_t au8[16];
2781	/** 16-bit view. */
2782	uint16_t au16[8];
2783	/** 32-bit view. */
2784	uint32_t au32[4];
2785	/** 64-bit view. */
2786	uint64_t au64[2];
2787	/** 128-bit view. (yeah, very helpful) */
2788	uint128_t au128[1];
2789	#ifndef VBOX_FOR_DTRACE_LIB
2790	/** Confusing nested 128-bit union view (this is what xmm should've been). */
2791	RTUINT128U uXmm;
2792	#endif
2793	} X86XMMREG;
2794	#ifndef VBOX_FOR_DTRACE_LIB
2795	AssertCompileSize(X86XMMREG, 16);
2796	#endif
2797	/** Pointer to an XMM register state. */
2798	typedef X86XMMREG *PX86XMMREG;
2799	/** Pointer to a const XMM register state. */
2800	typedef X86XMMREG const *PCX86XMMREG;
2801
2802	/**
2803	* YMM register union.
2804	*/
2805	typedef union X86YMMREG
2806	{
2807	/** 8-bit view. */
2808	uint8_t au8[32];
2809	/** 16-bit view. */
2810	uint16_t au16[16];
2811	/** 32-bit view. */
2812	uint32_t au32[8];
2813	/** 64-bit view. */
2814	uint64_t au64[4];
2815	/** 128-bit view. (yeah, very helpful) */
2816	uint128_t au128[2];
2817	/** XMM sub register view. */
2818	X86XMMREG aXmm[2];
2819	} X86YMMREG;
2820	#ifndef VBOX_FOR_DTRACE_LIB
2821	AssertCompileSize(X86YMMREG, 32);
2822	#endif
2823	/** Pointer to an YMM register state. */
2824	typedef X86YMMREG *PX86YMMREG;
2825	/** Pointer to a const YMM register state. */
2826	typedef X86YMMREG const *PCX86YMMREG;
2827
2828	/**
2829	* ZMM register union.
2830	*/
2831	typedef union X86ZMMREG
2832	{
2833	/** 8-bit view. */
2834	uint8_t au8[64];
2835	/** 16-bit view. */
2836	uint16_t au16[32];
2837	/** 32-bit view. */
2838	uint32_t au32[16];
2839	/** 64-bit view. */
2840	uint64_t au64[8];
2841	/** 128-bit view. (yeah, very helpful) */
2842	uint128_t au128[4];
2843	/** XMM sub register view. */
2844	X86XMMREG aXmm[4];
2845	/** YMM sub register view. */
2846	X86YMMREG aYmm[2];
2847	} X86ZMMREG;
2848	#ifndef VBOX_FOR_DTRACE_LIB
2849	AssertCompileSize(X86ZMMREG, 64);
2850	#endif
2851	/** Pointer to an ZMM register state. */
2852	typedef X86ZMMREG *PX86ZMMREG;
2853	/** Pointer to a const ZMM register state. */
2854	typedef X86ZMMREG const *PCX86ZMMREG;
2855
2856
2857	/**
2858	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2859	* @todo verify this...
2860	*/
2861	#pragma pack(1)
2862	typedef struct X86FPUSTATE
2863	{
2864	/** 0x00 - Control word. */
2865	uint16_t FCW;
2866	/** 0x02 - Alignment word */
2867	uint16_t Dummy1;
2868	/** 0x04 - Status word. */
2869	uint16_t FSW;
2870	/** 0x06 - Alignment word */
2871	uint16_t Dummy2;
2872	/** 0x08 - Tag word */
2873	uint16_t FTW;
2874	/** 0x0a - Alignment word */
2875	uint16_t Dummy3;
2876
2877	/** 0x0c - Instruction pointer. */
2878	uint32_t FPUIP;
2879	/** 0x10 - Code selector. */
2880	uint16_t CS;
2881	/** 0x12 - Opcode. */
2882	uint16_t FOP;
2883	/** 0x14 - FOO. */
2884	uint32_t FPUOO;
2885	/** 0x18 - FOS. */
2886	uint32_t FPUOS;
2887	/** 0x1c - FPU register. */
2888	X86FPUREG regs[8];
2889	} X86FPUSTATE;
2890	#pragma pack()
2891	/** Pointer to a FPU state. */
2892	typedef X86FPUSTATE *PX86FPUSTATE;
2893	/** Pointer to a const FPU state. */
2894	typedef const X86FPUSTATE *PCX86FPUSTATE;
2895
2896	/**
2897	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2898	*/
2899	#pragma pack(1)
2900	typedef struct X86FXSTATE
2901	{
2902	/** 0x00 - Control word. */
2903	uint16_t FCW;
2904	/** 0x02 - Status word. */
2905	uint16_t FSW;
2906	/** 0x04 - Tag word. (The upper byte is always zero.) */
2907	uint16_t FTW;
2908	/** 0x06 - Opcode. */
2909	uint16_t FOP;
2910	/** 0x08 - Instruction pointer. */
2911	uint32_t FPUIP;
2912	/** 0x0c - Code selector. */
2913	uint16_t CS;
2914	uint16_t Rsrvd1;
2915	/** 0x10 - Data pointer. */
2916	uint32_t FPUDP;
2917	/** 0x14 - Data segment */
2918	uint16_t DS;
2919	/** 0x16 */
2920	uint16_t Rsrvd2;
2921	/** 0x18 */
2922	uint32_t MXCSR;
2923	/** 0x1c */
2924	uint32_t MXCSR_MASK;
2925	/** 0x20 - FPU registers. */
2926	X86FPUREG aRegs[8];
2927	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2928	X86XMMREG aXMM[16];
2929	/* - offset 416 - */
2930	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2931	/* - offset 464 - Software usable reserved bits. */
2932	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2933	} X86FXSTATE;
2934	#pragma pack()
2935	/** Pointer to a FPU Extended state. */
2936	typedef X86FXSTATE *PX86FXSTATE;
2937	/** Pointer to a const FPU Extended state. */
2938	typedef const X86FXSTATE *PCX86FXSTATE;
2939
2940	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2941	* magic. Don't forget to update x86.mac if you change this! */
2942	#define X86_OFF_FXSTATE_RSVD 0x1d0
2943	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2944	* forget to update x86.mac if you change this!
2945	* @todo r=bird: This has nothing what-so-ever to do here.... */
2946	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2947	#ifndef VBOX_FOR_DTRACE_LIB
2948	AssertCompileSize(X86FXSTATE, 512);
2949	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2950	#endif
2951
2952	/** @name FPU status word flags.
2953	* @{ */
2954	/** Exception Flag: Invalid operation. */
2955	#define X86_FSW_IE RT_BIT_32(0)
2956	/** Exception Flag: Denormalized operand. */
2957	#define X86_FSW_DE RT_BIT_32(1)
2958	/** Exception Flag: Zero divide. */
2959	#define X86_FSW_ZE RT_BIT_32(2)
2960	/** Exception Flag: Overflow. */
2961	#define X86_FSW_OE RT_BIT_32(3)
2962	/** Exception Flag: Underflow. */
2963	#define X86_FSW_UE RT_BIT_32(4)
2964	/** Exception Flag: Precision. */
2965	#define X86_FSW_PE RT_BIT_32(5)
2966	/** Stack fault. */
2967	#define X86_FSW_SF RT_BIT_32(6)
2968	/** Error summary status. */
2969	#define X86_FSW_ES RT_BIT_32(7)
2970	/** Mask of exceptions flags, excluding the summary bit. */
2971	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2972	/** Mask of exceptions flags, including the summary bit. */
2973	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2974	/** Condition code 0. */
2975	#define X86_FSW_C0 RT_BIT_32(8)
2976	/** Condition code 1. */
2977	#define X86_FSW_C1 RT_BIT_32(9)
2978	/** Condition code 2. */
2979	#define X86_FSW_C2 RT_BIT_32(10)
2980	/** Top of the stack mask. */
2981	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2982	/** TOP shift value. */
2983	#define X86_FSW_TOP_SHIFT 11
2984	/** Mask for getting TOP value after shifting it right. */
2985	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2986	/** Get the TOP value. */
2987	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2988	/** Condition code 3. */
2989	#define X86_FSW_C3 RT_BIT_32(14)
2990	/** Mask of exceptions flags, including the summary bit. */
2991	#define X86_FSW_C_MASK UINT16_C(0x4700)
2992	/** FPU busy. */
2993	#define X86_FSW_B RT_BIT_32(15)
2994	/** @} */
2995
2996
2997	/** @name FPU control word flags.
2998	* @{ */
2999	/** Exception Mask: Invalid operation. */
3000	#define X86_FCW_IM RT_BIT_32(0)
3001	/** Exception Mask: Denormalized operand. */
3002	#define X86_FCW_DM RT_BIT_32(1)
3003	/** Exception Mask: Zero divide. */
3004	#define X86_FCW_ZM RT_BIT_32(2)
3005	/** Exception Mask: Overflow. */
3006	#define X86_FCW_OM RT_BIT_32(3)
3007	/** Exception Mask: Underflow. */
3008	#define X86_FCW_UM RT_BIT_32(4)
3009	/** Exception Mask: Precision. */
3010	#define X86_FCW_PM RT_BIT_32(5)
3011	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3012	* @remarks This includes reserved bit 6. */
3013	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3014	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3015	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3016	/** Precision control mask. */
3017	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3018	/** Precision control: 24-bit. */
3019	#define X86_FCW_PC_24 UINT16_C(0x0000)
3020	/** Precision control: Reserved. */
3021	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3022	/** Precision control: 53-bit. */
3023	#define X86_FCW_PC_53 UINT16_C(0x0200)
3024	/** Precision control: 64-bit. */
3025	#define X86_FCW_PC_64 UINT16_C(0x0300)
3026	/** Rounding control mask. */
3027	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3028	/** Rounding control: To nearest. */
3029	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3030	/** Rounding control: Down. */
3031	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3032	/** Rounding control: Up. */
3033	#define X86_FCW_RC_UP UINT16_C(0x0800)
3034	/** Rounding control: Towards zero. */
3035	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3036	/** Bits which should be zero, apparently. */
3037	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3038	/** @} */
3039
3040	/** @name SSE MXCSR
3041	* @{ */
3042	/** Exception Flag: Invalid operation. */
3043	#define X86_MXCSR_IE RT_BIT_32(0)
3044	/** Exception Flag: Denormalized operand. */
3045	#define X86_MXCSR_DE RT_BIT_32(1)
3046	/** Exception Flag: Zero divide. */
3047	#define X86_MXCSR_ZE RT_BIT_32(2)
3048	/** Exception Flag: Overflow. */
3049	#define X86_MXCSR_OE RT_BIT_32(3)
3050	/** Exception Flag: Underflow. */
3051	#define X86_MXCSR_UE RT_BIT_32(4)
3052	/** Exception Flag: Precision. */
3053	#define X86_MXCSR_PE RT_BIT_32(5)
3054
3055	/** Denormals are zero. */
3056	#define X86_MXCSR_DAZ RT_BIT_32(6)
3057
3058	/** Exception Mask: Invalid operation. */
3059	#define X86_MXCSR_IM RT_BIT_32(7)
3060	/** Exception Mask: Denormalized operand. */
3061	#define X86_MXCSR_DM RT_BIT_32(8)
3062	/** Exception Mask: Zero divide. */
3063	#define X86_MXCSR_ZM RT_BIT_32(9)
3064	/** Exception Mask: Overflow. */
3065	#define X86_MXCSR_OM RT_BIT_32(10)
3066	/** Exception Mask: Underflow. */
3067	#define X86_MXCSR_UM RT_BIT_32(11)
3068	/** Exception Mask: Precision. */
3069	#define X86_MXCSR_PM RT_BIT_32(12)
3070
3071	/** Rounding control mask. */
3072	#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3073	/** Rounding control: To nearest. */
3074	#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3075	/** Rounding control: Down. */
3076	#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3077	/** Rounding control: Up. */
3078	#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3079	/** Rounding control: Towards zero. */
3080	#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3081
3082	/** Flush-to-zero for masked underflow. */
3083	#define X86_MXCSR_FZ RT_BIT_32(15)
3084
3085	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3086	#define X86_MXCSR_MM RT_BIT_32(17)
3087	/** @} */
3088
3089	/**
3090	* XSAVE header.
3091	*/
3092	typedef struct X86XSAVEHDR
3093	{
3094	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3095	uint64_t bmXState;
3096	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3097	uint64_t bmXComp;
3098	/** Reserved for furture extensions, probably MBZ. */
3099	uint64_t au64Reserved[6];
3100	} X86XSAVEHDR;
3101	#ifndef VBOX_FOR_DTRACE_LIB
3102	AssertCompileSize(X86XSAVEHDR, 64);
3103	#endif
3104	/** Pointer to an XSAVE header. */
3105	typedef X86XSAVEHDR *PX86XSAVEHDR;
3106	/** Pointer to a const XSAVE header. */
3107	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3108
3109
3110	/**
3111	* The high 128-bit YMM register state (XSAVE_C_YMM).
3112	* (The lower 128-bits being in X86FXSTATE.)
3113	*/
3114	typedef struct X86XSAVEYMMHI
3115	{
3116	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3117	X86XMMREG aYmmHi[16];
3118	} X86XSAVEYMMHI;
3119	#ifndef VBOX_FOR_DTRACE_LIB
3120	AssertCompileSize(X86XSAVEYMMHI, 256);
3121	#endif
3122	/** Pointer to a high 128-bit YMM register state. */
3123	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3124	/** Pointer to a const high 128-bit YMM register state. */
3125	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3126
3127	/**
3128	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3129	*/
3130	typedef struct X86XSAVEBNDREGS
3131	{
3132	/** Array of registers (BND0...BND3). */
3133	struct
3134	{
3135	/** Lower bound. */
3136	uint64_t uLowerBound;
3137	/** Upper bound. */
3138	uint64_t uUpperBound;
3139	} aRegs[4];
3140	} X86XSAVEBNDREGS;
3141	#ifndef VBOX_FOR_DTRACE_LIB
3142	AssertCompileSize(X86XSAVEBNDREGS, 64);
3143	#endif
3144	/** Pointer to a MPX bound register state. */
3145	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3146	/** Pointer to a const MPX bound register state. */
3147	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3148
3149	/**
3150	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3151	*/
3152	typedef struct X86XSAVEBNDCFG
3153	{
3154	uint64_t fConfig;
3155	uint64_t fStatus;
3156	} X86XSAVEBNDCFG;
3157	#ifndef VBOX_FOR_DTRACE_LIB
3158	AssertCompileSize(X86XSAVEBNDCFG, 16);
3159	#endif
3160	/** Pointer to a MPX bound config and status register state. */
3161	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3162	/** Pointer to a const MPX bound config and status register state. */
3163	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3164
3165	/**
3166	* AVX-512 opmask state (XSAVE_C_OPMASK).
3167	*/
3168	typedef struct X86XSAVEOPMASK
3169	{
3170	/** The K0..K7 values. */
3171	uint64_t aKRegs[8];
3172	} X86XSAVEOPMASK;
3173	#ifndef VBOX_FOR_DTRACE_LIB
3174	AssertCompileSize(X86XSAVEOPMASK, 64);
3175	#endif
3176	/** Pointer to a AVX-512 opmask state. */
3177	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3178	/** Pointer to a const AVX-512 opmask state. */
3179	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3180
3181	/**
3182	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3183	*/
3184	typedef struct X86XSAVEZMMHI256
3185	{
3186	/** Upper 256-bits of ZMM0-15. */
3187	X86YMMREG aHi256Regs[16];
3188	} X86XSAVEZMMHI256;
3189	#ifndef VBOX_FOR_DTRACE_LIB
3190	AssertCompileSize(X86XSAVEZMMHI256, 512);
3191	#endif
3192	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3193	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3194	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3195	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3196
3197	/**
3198	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3199	*/
3200	typedef struct X86XSAVEZMM16HI
3201	{
3202	/** ZMM16 thru ZMM31. */
3203	X86ZMMREG aRegs[16];
3204	} X86XSAVEZMM16HI;
3205	#ifndef VBOX_FOR_DTRACE_LIB
3206	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3207	#endif
3208	/** Pointer to a state comprising ZMM16-32. */
3209	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3210	/** Pointer to a const state comprising ZMM16-32. */
3211	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3212
3213	/**
3214	* AMD Light weight profiling state (XSAVE_C_LWP).
3215	*
3216	* We probably won't play with this as AMD seems to be dropping from their "zen"
3217	* processor micro architecture.
3218	*/
3219	typedef struct X86XSAVELWP
3220	{
3221	/** Details when needed. */
3222	uint64_t auLater[128/8];
3223	} X86XSAVELWP;
3224	#ifndef VBOX_FOR_DTRACE_LIB
3225	AssertCompileSize(X86XSAVELWP, 128);
3226	#endif
3227
3228
3229	/**
3230	* x86 FPU/SSE/AVX/XXXX state.
3231	*
3232	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3233	* changes to this structure.
3234	*/
3235	typedef struct X86XSAVEAREA
3236	{
3237	/** The x87 and SSE region (or legacy region if you like). */
3238	X86FXSTATE x87;
3239	/** The XSAVE header. */
3240	X86XSAVEHDR Hdr;
3241	/** Beyond the header, there isn't really a fixed layout, but we can
3242	generally assume the YMM (AVX) register extensions are present and
3243	follows immediately. */
3244	union
3245	{
3246	/** The high 128-bit AVX registers for easy access by IEM.
3247	* @note This ASSUMES they will always be here... */
3248	X86XSAVEYMMHI YmmHi;
3249
3250	/** This is a typical layout on intel CPUs (good for debuggers). */
3251	struct
3252	{
3253	X86XSAVEYMMHI YmmHi;
3254	X86XSAVEBNDREGS BndRegs;
3255	X86XSAVEBNDCFG BndCfg;
3256	uint8_t abFudgeToMatchDocs[0xB0];
3257	X86XSAVEOPMASK Opmask;
3258	X86XSAVEZMMHI256 ZmmHi256;
3259	X86XSAVEZMM16HI Zmm16Hi;
3260	} Intel;
3261
3262	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3263	struct
3264	{
3265	X86XSAVEYMMHI YmmHi;
3266	X86XSAVELWP Lwp;
3267	} AmdBd;
3268
3269	/** To enbling static deployments that have a reasonable chance of working for
3270	* the next 3-6 CPU generations without running short on space, we allocate a
3271	* lot of extra space here, making the structure a round 8KB in size. This
3272	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3273	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3274	uint8_t ab[8192 - 512 - 64];
3275	} u;
3276	} X86XSAVEAREA;
3277	#ifndef VBOX_FOR_DTRACE_LIB
3278	AssertCompileSize(X86XSAVEAREA, 8192);
3279	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3280	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3281	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3282	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3283	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3284	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3285	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3286	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3287	#endif
3288	/** Pointer to a XSAVE area. */
3289	typedef X86XSAVEAREA *PX86XSAVEAREA;
3290	/** Pointer to a const XSAVE area. */
3291	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3292
3293
3294	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3295	* @{ */
3296	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3297	#define XSAVE_C_X87_BIT 0
3298	/** Bit 0 - x87 - Legacy FPU state. */
3299	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3300	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3301	#define XSAVE_C_SSE_BIT 1
3302	/** Bit 1 - SSE - 128-bit SSE state. */
3303	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3304	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3305	#define XSAVE_C_YMM_BIT 2
3306	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3307	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3308	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3309	#define XSAVE_C_BNDREGS_BIT 3
3310	/** Bit 3 - BNDREGS - MPX bound register state. */
3311	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3312	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3313	#define XSAVE_C_BNDCSR_BIT 4
3314	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3315	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3316	/** Bit 5 - Opmask - opmask state (bit number). */
3317	#define XSAVE_C_OPMASK_BIT 5
3318	/** Bit 5 - Opmask - opmask state. */
3319	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3320	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3321	#define XSAVE_C_ZMM_HI256_BIT 6
3322	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3323	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3324	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3325	#define XSAVE_C_ZMM_16HI_BIT 7
3326	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3327	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3328	/** Bit 9 - PKRU - Protection-key state (bit number). */
3329	#define XSAVE_C_PKRU_BIT 9
3330	/** Bit 9 - PKRU - Protection-key state. */
3331	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3332	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3333	#define XSAVE_C_LWP_BIT 62
3334	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3335	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3336	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3337	#define XSAVE_C_X_BIT 63
3338	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3339	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3340	/** @} */
3341
3342
3343
3344	/** @name Selector Descriptor
3345	* @{
3346	*/
3347
3348	#ifndef VBOX_FOR_DTRACE_LIB
3349	/**
3350	* Descriptor attributes (as seen by VT-x).
3351	*/
3352	typedef struct X86DESCATTRBITS
3353	{
3354	/** 00 - Segment Type. */
3355	unsigned u4Type : 4;
3356	/** 04 - Descriptor Type. System(=0) or code/data selector */
3357	unsigned u1DescType : 1;
3358	/** 05 - Descriptor Privilege level. */
3359	unsigned u2Dpl : 2;
3360	/** 07 - Flags selector present(=1) or not. */
3361	unsigned u1Present : 1;
3362	/** 08 - Segment limit 16-19. */
3363	unsigned u4LimitHigh : 4;
3364	/** 0c - Available for system software. */
3365	unsigned u1Available : 1;
3366	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3367	unsigned u1Long : 1;
3368	/** 0e - This flags meaning depends on the segment type. Try make sense out
3369	* of the intel manual yourself. */
3370	unsigned u1DefBig : 1;
3371	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3372	* clear byte. */
3373	unsigned u1Granularity : 1;
3374	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3375	unsigned u1Unusable : 1;
3376	} X86DESCATTRBITS;
3377	#endif /* !VBOX_FOR_DTRACE_LIB */
3378
3379	/** @name X86DESCATTR masks
3380	* @{ */
3381	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3382	#define X86DESCATTR_DT UINT32_C(0x00000010)
3383	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3384	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3385	#define X86DESCATTR_P UINT32_C(0x00000080)
3386	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3387	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3388	#define X86DESCATTR_L UINT32_C(0x00002000)
3389	#define X86DESCATTR_D UINT32_C(0x00004000)
3390	#define X86DESCATTR_G UINT32_C(0x00008000)
3391	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3392	/** @} */
3393
3394	#pragma pack(1)
3395	typedef union X86DESCATTR
3396	{
3397	/** Unsigned integer view. */
3398	uint32_t u;
3399	#ifndef VBOX_FOR_DTRACE_LIB
3400	/** Normal view. */
3401	X86DESCATTRBITS n;
3402	#endif
3403	} X86DESCATTR;
3404	#pragma pack()
3405	/** Pointer to descriptor attributes. */
3406	typedef X86DESCATTR *PX86DESCATTR;
3407	/** Pointer to const descriptor attributes. */
3408	typedef const X86DESCATTR *PCX86DESCATTR;
3409
3410	#ifndef VBOX_FOR_DTRACE_LIB
3411
3412	/**
3413	* Generic descriptor table entry
3414	*/
3415	#pragma pack(1)
3416	typedef struct X86DESCGENERIC
3417	{
3418	/** 00 - Limit - Low word. */
3419	unsigned u16LimitLow : 16;
3420	/** 10 - Base address - low word.
3421	* Don't try set this to 24 because MSC is doing stupid things then. */
3422	unsigned u16BaseLow : 16;
3423	/** 20 - Base address - first 8 bits of high word. */
3424	unsigned u8BaseHigh1 : 8;
3425	/** 28 - Segment Type. */
3426	unsigned u4Type : 4;
3427	/** 2c - Descriptor Type. System(=0) or code/data selector */
3428	unsigned u1DescType : 1;
3429	/** 2d - Descriptor Privilege level. */
3430	unsigned u2Dpl : 2;
3431	/** 2f - Flags selector present(=1) or not. */
3432	unsigned u1Present : 1;
3433	/** 30 - Segment limit 16-19. */
3434	unsigned u4LimitHigh : 4;
3435	/** 34 - Available for system software. */
3436	unsigned u1Available : 1;
3437	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3438	unsigned u1Long : 1;
3439	/** 36 - This flags meaning depends on the segment type. Try make sense out
3440	* of the intel manual yourself. */
3441	unsigned u1DefBig : 1;
3442	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3443	* clear byte. */
3444	unsigned u1Granularity : 1;
3445	/** 38 - Base address - highest 8 bits. */
3446	unsigned u8BaseHigh2 : 8;
3447	} X86DESCGENERIC;
3448	#pragma pack()
3449	/** Pointer to a generic descriptor entry. */
3450	typedef X86DESCGENERIC *PX86DESCGENERIC;
3451	/** Pointer to a const generic descriptor entry. */
3452	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3453
3454	/** @name Bit offsets of X86DESCGENERIC members.
3455	* @{*/
3456	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3457	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3458	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3459	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3460	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3461	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3462	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3463	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3464	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3465	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3466	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3467	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3468	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3469	/** @} */
3470
3471
3472	/** @name LAR mask
3473	* @{ */
3474	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3475	#define X86LAR_F_DT UINT16_C( 0x1000)
3476	#define X86LAR_F_DPL UINT16_C( 0x6000)
3477	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3478	#define X86LAR_F_P UINT16_C( 0x8000)
3479	#define X86LAR_F_AVL UINT32_C(0x00100000)
3480	#define X86LAR_F_L UINT32_C(0x00200000)
3481	#define X86LAR_F_D UINT32_C(0x00400000)
3482	#define X86LAR_F_G UINT32_C(0x00800000)
3483	/** @} */
3484
3485
3486	/**
3487	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3488	*/
3489	typedef struct X86DESCGATE
3490	{
3491	/** 00 - Target code segment offset - Low word.
3492	* Ignored if task-gate. */
3493	unsigned u16OffsetLow : 16;
3494	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3495	* TSS selector if task-gate. */
3496	unsigned u16Sel : 16;
3497	/** 20 - Number of parameters for a call-gate.
3498	* Ignored if interrupt-, trap- or task-gate. */
3499	unsigned u5ParmCount : 5;
3500	/** 25 - Reserved / ignored. */
3501	unsigned u3Reserved : 3;
3502	/** 28 - Segment Type. */
3503	unsigned u4Type : 4;
3504	/** 2c - Descriptor Type (0 = system). */
3505	unsigned u1DescType : 1;
3506	/** 2d - Descriptor Privilege level. */
3507	unsigned u2Dpl : 2;
3508	/** 2f - Flags selector present(=1) or not. */
3509	unsigned u1Present : 1;
3510	/** 30 - Target code segment offset - High word.
3511	* Ignored if task-gate. */
3512	unsigned u16OffsetHigh : 16;
3513	} X86DESCGATE;
3514	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3515	typedef X86DESCGATE *PX86DESCGATE;
3516	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3517	typedef const X86DESCGATE *PCX86DESCGATE;
3518
3519	#endif /* VBOX_FOR_DTRACE_LIB */
3520
3521	/**
3522	* Descriptor table entry.
3523	*/
3524	#pragma pack(1)
3525	typedef union X86DESC
3526	{
3527	#ifndef VBOX_FOR_DTRACE_LIB
3528	/** Generic descriptor view. */
3529	X86DESCGENERIC Gen;
3530	/** Gate descriptor view. */
3531	X86DESCGATE Gate;
3532	#endif
3533
3534	/** 8 bit unsigned integer view. */
3535	uint8_t au8[8];
3536	/** 16 bit unsigned integer view. */
3537	uint16_t au16[4];
3538	/** 32 bit unsigned integer view. */
3539	uint32_t au32[2];
3540	/** 64 bit unsigned integer view. */
3541	uint64_t au64[1];
3542	/** Unsigned integer view. */
3543	uint64_t u;
3544	} X86DESC;
3545	#ifndef VBOX_FOR_DTRACE_LIB
3546	AssertCompileSize(X86DESC, 8);
3547	#endif
3548	#pragma pack()
3549	/** Pointer to descriptor table entry. */
3550	typedef X86DESC *PX86DESC;
3551	/** Pointer to const descriptor table entry. */
3552	typedef const X86DESC *PCX86DESC;
3553
3554	/** @def X86DESC_BASE
3555	* Return the base address of a descriptor.
3556	*/
3557	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3558	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3559	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3560	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3561
3562	/** @def X86DESC_LIMIT
3563	* Return the limit of a descriptor.
3564	*/
3565	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3566	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3567	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3568
3569	/** @def X86DESC_LIMIT_G
3570	* Return the limit of a descriptor with the granularity bit taken into account.
3571	* @returns Selector limit (uint32_t).
3572	* @param a_pDesc Pointer to the descriptor.
3573	*/
3574	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3575	( (a_pDesc)->Gen.u1Granularity \
3576	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3577	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3578	)
3579
3580	/** @def X86DESC_GET_HID_ATTR
3581	* Get the descriptor attributes for the hidden register.
3582	*/
3583	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3584	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3585
3586	#ifndef VBOX_FOR_DTRACE_LIB
3587
3588	/**
3589	* 64 bits generic descriptor table entry
3590	* Note: most of these bits have no meaning in long mode.
3591	*/
3592	#pragma pack(1)
3593	typedef struct X86DESC64GENERIC
3594	{
3595	/** Limit - Low word - IGNORED. */
3596	uint32_t u16LimitLow : 16;
3597	/** Base address - low word. - IGNORED
3598	* Don't try set this to 24 because MSC is doing stupid things then. */
3599	uint32_t u16BaseLow : 16;
3600	/** Base address - first 8 bits of high word. - IGNORED */
3601	uint32_t u8BaseHigh1 : 8;
3602	/** Segment Type. */
3603	uint32_t u4Type : 4;
3604	/** Descriptor Type. System(=0) or code/data selector */
3605	uint32_t u1DescType : 1;
3606	/** Descriptor Privilege level. */
3607	uint32_t u2Dpl : 2;
3608	/** Flags selector present(=1) or not. */
3609	uint32_t u1Present : 1;
3610	/** Segment limit 16-19. - IGNORED */
3611	uint32_t u4LimitHigh : 4;
3612	/** Available for system software. - IGNORED */
3613	uint32_t u1Available : 1;
3614	/** Long mode flag. */
3615	uint32_t u1Long : 1;
3616	/** This flags meaning depends on the segment type. Try make sense out
3617	* of the intel manual yourself. */
3618	uint32_t u1DefBig : 1;
3619	/** Granularity of the limit. If set 4KB granularity is used, if
3620	* clear byte. - IGNORED */
3621	uint32_t u1Granularity : 1;
3622	/** Base address - highest 8 bits. - IGNORED */
3623	uint32_t u8BaseHigh2 : 8;
3624	/** Base address - bits 63-32. */
3625	uint32_t u32BaseHigh3 : 32;
3626	uint32_t u8Reserved : 8;
3627	uint32_t u5Zeros : 5;
3628	uint32_t u19Reserved : 19;
3629	} X86DESC64GENERIC;
3630	#pragma pack()
3631	/** Pointer to a generic descriptor entry. */
3632	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3633	/** Pointer to a const generic descriptor entry. */
3634	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3635
3636	/**
3637	* System descriptor table entry (64 bits)
3638	*
3639	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3640	*/
3641	#pragma pack(1)
3642	typedef struct X86DESC64SYSTEM
3643	{
3644	/** Limit - Low word. */
3645	uint32_t u16LimitLow : 16;
3646	/** Base address - low word.
3647	* Don't try set this to 24 because MSC is doing stupid things then. */
3648	uint32_t u16BaseLow : 16;
3649	/** Base address - first 8 bits of high word. */
3650	uint32_t u8BaseHigh1 : 8;
3651	/** Segment Type. */
3652	uint32_t u4Type : 4;
3653	/** Descriptor Type. System(=0) or code/data selector */
3654	uint32_t u1DescType : 1;
3655	/** Descriptor Privilege level. */
3656	uint32_t u2Dpl : 2;
3657	/** Flags selector present(=1) or not. */
3658	uint32_t u1Present : 1;
3659	/** Segment limit 16-19. */
3660	uint32_t u4LimitHigh : 4;
3661	/** Available for system software. */
3662	uint32_t u1Available : 1;
3663	/** Reserved - 0. */
3664	uint32_t u1Reserved : 1;
3665	/** This flags meaning depends on the segment type. Try make sense out
3666	* of the intel manual yourself. */
3667	uint32_t u1DefBig : 1;
3668	/** Granularity of the limit. If set 4KB granularity is used, if
3669	* clear byte. */
3670	uint32_t u1Granularity : 1;
3671	/** Base address - bits 31-24. */
3672	uint32_t u8BaseHigh2 : 8;
3673	/** Base address - bits 63-32. */
3674	uint32_t u32BaseHigh3 : 32;
3675	uint32_t u8Reserved : 8;
3676	uint32_t u5Zeros : 5;
3677	uint32_t u19Reserved : 19;
3678	} X86DESC64SYSTEM;
3679	#pragma pack()
3680	/** Pointer to a system descriptor entry. */
3681	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3682	/** Pointer to a const system descriptor entry. */
3683	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3684
3685	/**
3686	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3687	*/
3688	typedef struct X86DESC64GATE
3689	{
3690	/** Target code segment offset - Low word. */
3691	uint32_t u16OffsetLow : 16;
3692	/** Target code segment selector. */
3693	uint32_t u16Sel : 16;
3694	/** Interrupt stack table for interrupt- and trap-gates.
3695	* Ignored by call-gates. */
3696	uint32_t u3IST : 3;
3697	/** Reserved / ignored. */
3698	uint32_t u5Reserved : 5;
3699	/** Segment Type. */
3700	uint32_t u4Type : 4;
3701	/** Descriptor Type (0 = system). */
3702	uint32_t u1DescType : 1;
3703	/** Descriptor Privilege level. */
3704	uint32_t u2Dpl : 2;
3705	/** Flags selector present(=1) or not. */
3706	uint32_t u1Present : 1;
3707	/** Target code segment offset - High word.
3708	* Ignored if task-gate. */
3709	uint32_t u16OffsetHigh : 16;
3710	/** Target code segment offset - Top dword.
3711	* Ignored if task-gate. */
3712	uint32_t u32OffsetTop : 32;
3713	/** Reserved / ignored / must be zero.
3714	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3715	uint32_t u32Reserved : 32;
3716	} X86DESC64GATE;
3717	AssertCompileSize(X86DESC64GATE, 16);
3718	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3719	typedef X86DESC64GATE *PX86DESC64GATE;
3720	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3721	typedef const X86DESC64GATE *PCX86DESC64GATE;
3722
3723	#endif /* VBOX_FOR_DTRACE_LIB */
3724
3725	/**
3726	* Descriptor table entry.
3727	*/
3728	#pragma pack(1)
3729	typedef union X86DESC64
3730	{
3731	#ifndef VBOX_FOR_DTRACE_LIB
3732	/** Generic descriptor view. */
3733	X86DESC64GENERIC Gen;
3734	/** System descriptor view. */
3735	X86DESC64SYSTEM System;
3736	/** Gate descriptor view. */
3737	X86DESC64GATE Gate;
3738	#endif
3739
3740	/** 8 bit unsigned integer view. */
3741	uint8_t au8[16];
3742	/** 16 bit unsigned integer view. */
3743	uint16_t au16[8];
3744	/** 32 bit unsigned integer view. */
3745	uint32_t au32[4];
3746	/** 64 bit unsigned integer view. */
3747	uint64_t au64[2];
3748	} X86DESC64;
3749	#ifndef VBOX_FOR_DTRACE_LIB
3750	AssertCompileSize(X86DESC64, 16);
3751	#endif
3752	#pragma pack()
3753	/** Pointer to descriptor table entry. */
3754	typedef X86DESC64 *PX86DESC64;
3755	/** Pointer to const descriptor table entry. */
3756	typedef const X86DESC64 *PCX86DESC64;
3757
3758	/** @def X86DESC64_BASE
3759	* Return the base of a 64-bit descriptor.
3760	*/
3761	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3762	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3763	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3764	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3765	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3766
3767
3768
3769	/** @name Host system descriptor table entry - Use with care!
3770	* @{ */
3771	/** Host system descriptor table entry. */
3772	#if HC_ARCH_BITS == 64
3773	typedef X86DESC64 X86DESCHC;
3774	#else
3775	typedef X86DESC X86DESCHC;
3776	#endif
3777	/** Pointer to a host system descriptor table entry. */
3778	#if HC_ARCH_BITS == 64
3779	typedef PX86DESC64 PX86DESCHC;
3780	#else
3781	typedef PX86DESC PX86DESCHC;
3782	#endif
3783	/** Pointer to a const host system descriptor table entry. */
3784	#if HC_ARCH_BITS == 64
3785	typedef PCX86DESC64 PCX86DESCHC;
3786	#else
3787	typedef PCX86DESC PCX86DESCHC;
3788	#endif
3789	/** @} */
3790
3791
3792	/** @name Selector Descriptor Types.
3793	* @{
3794	*/
3795
3796	/** @name Non-System Selector Types.
3797	* @{ */
3798	/** Code(=set)/Data(=clear) bit. */
3799	#define X86_SEL_TYPE_CODE 8
3800	/** Memory(=set)/System(=clear) bit. */
3801	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3802	/** Accessed bit. */
3803	#define X86_SEL_TYPE_ACCESSED 1
3804	/** Expand down bit (for data selectors only). */
3805	#define X86_SEL_TYPE_DOWN 4
3806	/** Conforming bit (for code selectors only). */
3807	#define X86_SEL_TYPE_CONF 4
3808	/** Write bit (for data selectors only). */
3809	#define X86_SEL_TYPE_WRITE 2
3810	/** Read bit (for code selectors only). */
3811	#define X86_SEL_TYPE_READ 2
3812	/** The bit number of the code segment read bit (relative to u4Type). */
3813	#define X86_SEL_TYPE_READ_BIT 1
3814
3815	/** Read only selector type. */
3816	#define X86_SEL_TYPE_RO 0
3817	/** Accessed read only selector type. */
3818	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3819	/** Read write selector type. */
3820	#define X86_SEL_TYPE_RW 2
3821	/** Accessed read write selector type. */
3822	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3823	/** Expand down read only selector type. */
3824	#define X86_SEL_TYPE_RO_DOWN 4
3825	/** Accessed expand down read only selector type. */
3826	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3827	/** Expand down read write selector type. */
3828	#define X86_SEL_TYPE_RW_DOWN 6
3829	/** Accessed expand down read write selector type. */
3830	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3831	/** Execute only selector type. */
3832	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3833	/** Accessed execute only selector type. */
3834	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3835	/** Execute and read selector type. */
3836	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3837	/** Accessed execute and read selector type. */
3838	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3839	/** Conforming execute only selector type. */
3840	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3841	/** Accessed Conforming execute only selector type. */
3842	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3843	/** Conforming execute and write selector type. */
3844	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3845	/** Accessed Conforming execute and write selector type. */
3846	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3847	/** @} */
3848
3849
3850	/** @name System Selector Types.
3851	* @{ */
3852	/** The TSS busy bit mask. */
3853	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3854
3855	/** Undefined system selector type. */
3856	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3857	/** 286 TSS selector. */
3858	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3859	/** LDT selector. */
3860	#define X86_SEL_TYPE_SYS_LDT 2
3861	/** 286 TSS selector - Busy. */
3862	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3863	/** 286 Callgate selector. */
3864	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3865	/** Taskgate selector. */
3866	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3867	/** 286 Interrupt gate selector. */
3868	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3869	/** 286 Trapgate selector. */
3870	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3871	/** Undefined system selector. */
3872	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3873	/** 386 TSS selector. */
3874	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3875	/** Undefined system selector. */
3876	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3877	/** 386 TSS selector - Busy. */
3878	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3879	/** 386 Callgate selector. */
3880	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3881	/** Undefined system selector. */
3882	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3883	/** 386 Interruptgate selector. */
3884	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3885	/** 386 Trapgate selector. */
3886	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3887	/** @} */
3888
3889	/** @name AMD64 System Selector Types.
3890	* @{ */
3891	/** LDT selector. */
3892	#define AMD64_SEL_TYPE_SYS_LDT 2
3893	/** TSS selector - Busy. */
3894	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3895	/** TSS selector - Busy. */
3896	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3897	/** Callgate selector. */
3898	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3899	/** Interruptgate selector. */
3900	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3901	/** Trapgate selector. */
3902	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3903	/** @} */
3904
3905	/** @} */
3906
3907
3908	/** @name Descriptor Table Entry Flag Masks.
3909	* These are for the 2nd 32-bit word of a descriptor.
3910	* @{ */
3911	/** Bits 8-11 - TYPE - Descriptor type mask. */
3912	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3913	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3914	#define X86_DESC_S RT_BIT_32(12)
3915	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3916	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
3917	/** Bit 15 - P - Present. */
3918	#define X86_DESC_P RT_BIT_32(15)
3919	/** Bit 20 - AVL - Available for system software. */
3920	#define X86_DESC_AVL RT_BIT_32(20)
3921	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3922	#define X86_DESC_DB RT_BIT_32(22)
3923	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3924	* used, if clear byte. */
3925	#define X86_DESC_G RT_BIT_32(23)
3926	/** @} */
3927
3928	/** @} */
3929
3930
3931	/** @name Task Segments.
3932	* @{
3933	*/
3934
3935	/**
3936	* The minimum TSS descriptor limit for 286 tasks.
3937	*/
3938	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3939
3940	/**
3941	* The minimum TSS descriptor segment limit for 386 tasks.
3942	*/
3943	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3944
3945	/**
3946	* 16-bit Task Segment (TSS).
3947	*/
3948	#pragma pack(1)
3949	typedef struct X86TSS16
3950	{
3951	/** Back link to previous task. (static) */
3952	RTSEL selPrev;
3953	/** Ring-0 stack pointer. (static) */
3954	uint16_t sp0;
3955	/** Ring-0 stack segment. (static) */
3956	RTSEL ss0;
3957	/** Ring-1 stack pointer. (static) */
3958	uint16_t sp1;
3959	/** Ring-1 stack segment. (static) */
3960	RTSEL ss1;
3961	/** Ring-2 stack pointer. (static) */
3962	uint16_t sp2;
3963	/** Ring-2 stack segment. (static) */
3964	RTSEL ss2;
3965	/** IP before task switch. */
3966	uint16_t ip;
3967	/** FLAGS before task switch. */
3968	uint16_t flags;
3969	/** AX before task switch. */
3970	uint16_t ax;
3971	/** CX before task switch. */
3972	uint16_t cx;
3973	/** DX before task switch. */
3974	uint16_t dx;
3975	/** BX before task switch. */
3976	uint16_t bx;
3977	/** SP before task switch. */
3978	uint16_t sp;
3979	/** BP before task switch. */
3980	uint16_t bp;
3981	/** SI before task switch. */
3982	uint16_t si;
3983	/** DI before task switch. */
3984	uint16_t di;
3985	/** ES before task switch. */
3986	RTSEL es;
3987	/** CS before task switch. */
3988	RTSEL cs;
3989	/** SS before task switch. */
3990	RTSEL ss;
3991	/** DS before task switch. */
3992	RTSEL ds;
3993	/** LDTR before task switch. */
3994	RTSEL selLdt;
3995	} X86TSS16;
3996	#ifndef VBOX_FOR_DTRACE_LIB
3997	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3998	#endif
3999	#pragma pack()
4000	/** Pointer to a 16-bit task segment. */
4001	typedef X86TSS16 *PX86TSS16;
4002	/** Pointer to a const 16-bit task segment. */
4003	typedef const X86TSS16 *PCX86TSS16;
4004
4005
4006	/**
4007	* 32-bit Task Segment (TSS).
4008	*/
4009	#pragma pack(1)
4010	typedef struct X86TSS32
4011	{
4012	/** Back link to previous task. (static) */
4013	RTSEL selPrev;
4014	uint16_t padding1;
4015	/** Ring-0 stack pointer. (static) */
4016	uint32_t esp0;
4017	/** Ring-0 stack segment. (static) */
4018	RTSEL ss0;
4019	uint16_t padding_ss0;
4020	/** Ring-1 stack pointer. (static) */
4021	uint32_t esp1;
4022	/** Ring-1 stack segment. (static) */
4023	RTSEL ss1;
4024	uint16_t padding_ss1;
4025	/** Ring-2 stack pointer. (static) */
4026	uint32_t esp2;
4027	/** Ring-2 stack segment. (static) */
4028	RTSEL ss2;
4029	uint16_t padding_ss2;
4030	/** Page directory for the task. (static) */
4031	uint32_t cr3;
4032	/** EIP before task switch. */
4033	uint32_t eip;
4034	/** EFLAGS before task switch. */
4035	uint32_t eflags;
4036	/** EAX before task switch. */
4037	uint32_t eax;
4038	/** ECX before task switch. */
4039	uint32_t ecx;
4040	/** EDX before task switch. */
4041	uint32_t edx;
4042	/** EBX before task switch. */
4043	uint32_t ebx;
4044	/** ESP before task switch. */
4045	uint32_t esp;
4046	/** EBP before task switch. */
4047	uint32_t ebp;
4048	/** ESI before task switch. */
4049	uint32_t esi;
4050	/** EDI before task switch. */
4051	uint32_t edi;
4052	/** ES before task switch. */
4053	RTSEL es;
4054	uint16_t padding_es;
4055	/** CS before task switch. */
4056	RTSEL cs;
4057	uint16_t padding_cs;
4058	/** SS before task switch. */
4059	RTSEL ss;
4060	uint16_t padding_ss;
4061	/** DS before task switch. */
4062	RTSEL ds;
4063	uint16_t padding_ds;
4064	/** FS before task switch. */
4065	RTSEL fs;
4066	uint16_t padding_fs;
4067	/** GS before task switch. */
4068	RTSEL gs;
4069	uint16_t padding_gs;
4070	/** LDTR before task switch. */
4071	RTSEL selLdt;
4072	uint16_t padding_ldt;
4073	/** Debug trap flag */
4074	uint16_t fDebugTrap;
4075	/** Offset relative to the TSS of the start of the I/O Bitmap
4076	* and the end of the interrupt redirection bitmap. */
4077	uint16_t offIoBitmap;
4078	} X86TSS32;
4079	#pragma pack()
4080	/** Pointer to task segment. */
4081	typedef X86TSS32 *PX86TSS32;
4082	/** Pointer to const task segment. */
4083	typedef const X86TSS32 *PCX86TSS32;
4084	#ifndef VBOX_FOR_DTRACE_LIB
4085	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4086	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4087	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4088	#endif
4089
4090	/**
4091	* 64-bit Task segment.
4092	*/
4093	#pragma pack(1)
4094	typedef struct X86TSS64
4095	{
4096	/** Reserved. */
4097	uint32_t u32Reserved;
4098	/** Ring-0 stack pointer. (static) */
4099	uint64_t rsp0;
4100	/** Ring-1 stack pointer. (static) */
4101	uint64_t rsp1;
4102	/** Ring-2 stack pointer. (static) */
4103	uint64_t rsp2;
4104	/** Reserved. */
4105	uint32_t u32Reserved2[2];
4106	/* IST */
4107	uint64_t ist1;
4108	uint64_t ist2;
4109	uint64_t ist3;
4110	uint64_t ist4;
4111	uint64_t ist5;
4112	uint64_t ist6;
4113	uint64_t ist7;
4114	/* Reserved. */
4115	uint16_t u16Reserved[5];
4116	/** Offset relative to the TSS of the start of the I/O Bitmap
4117	* and the end of the interrupt redirection bitmap. */
4118	uint16_t offIoBitmap;
4119	} X86TSS64;
4120	#pragma pack()
4121	/** Pointer to a 64-bit task segment. */
4122	typedef X86TSS64 *PX86TSS64;
4123	/** Pointer to a const 64-bit task segment. */
4124	typedef const X86TSS64 *PCX86TSS64;
4125	#ifndef VBOX_FOR_DTRACE_LIB
4126	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4127	#endif
4128
4129	/** @} */
4130
4131
4132	/** @name Selectors.
4133	* @{
4134	*/
4135
4136	/**
4137	* The shift used to convert a selector from and to index an index (C).
4138	*/
4139	#define X86_SEL_SHIFT 3
4140
4141	/**
4142	* The mask used to mask off the table indicator and RPL of an selector.
4143	*/
4144	#define X86_SEL_MASK 0xfff8U
4145
4146	/**
4147	* The mask used to mask off the RPL of an selector.
4148	* This is suitable for checking for NULL selectors.
4149	*/
4150	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4151
4152	/**
4153	* The bit indicating that a selector is in the LDT and not in the GDT.
4154	*/
4155	#define X86_SEL_LDT 0x0004U
4156
4157	/**
4158	* The bit mask for getting the RPL of a selector.
4159	*/
4160	#define X86_SEL_RPL 0x0003U
4161
4162	/**
4163	* The mask covering both RPL and LDT.
4164	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4165	* checks.
4166	*/
4167	#define X86_SEL_RPL_LDT 0x0007U
4168
4169	/** @} */
4170
4171
4172	/**
4173	* x86 Exceptions/Faults/Traps.
4174	*/
4175	typedef enum X86XCPT
4176	{
4177	/** \#DE - Divide error. */
4178	X86_XCPT_DE = 0x00,
4179	/** \#DB - Debug event (single step, DRx, ..) */
4180	X86_XCPT_DB = 0x01,
4181	/** NMI - Non-Maskable Interrupt */
4182	X86_XCPT_NMI = 0x02,
4183	/** \#BP - Breakpoint (INT3). */
4184	X86_XCPT_BP = 0x03,
4185	/** \#OF - Overflow (INTO). */
4186	X86_XCPT_OF = 0x04,
4187	/** \#BR - Bound range exceeded (BOUND). */
4188	X86_XCPT_BR = 0x05,
4189	/** \#UD - Undefined opcode. */
4190	X86_XCPT_UD = 0x06,
4191	/** \#NM - Device not available (math coprocessor device). */
4192	X86_XCPT_NM = 0x07,
4193	/** \#DF - Double fault. */
4194	X86_XCPT_DF = 0x08,
4195	/** ??? - Coprocessor segment overrun (obsolete). */
4196	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4197	/** \#TS - Taskswitch (TSS). */
4198	X86_XCPT_TS = 0x0a,
4199	/** \#NP - Segment no present. */
4200	X86_XCPT_NP = 0x0b,
4201	/** \#SS - Stack segment fault. */
4202	X86_XCPT_SS = 0x0c,
4203	/** \#GP - General protection fault. */
4204	X86_XCPT_GP = 0x0d,
4205	/** \#PF - Page fault. */
4206	X86_XCPT_PF = 0x0e,
4207	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4208	/** \#MF - Math fault (FPU). */
4209	X86_XCPT_MF = 0x10,
4210	/** \#AC - Alignment check. */
4211	X86_XCPT_AC = 0x11,
4212	/** \#MC - Machine check. */
4213	X86_XCPT_MC = 0x12,
4214	/** \#XF - SIMD Floating-Pointer Exception. */
4215	X86_XCPT_XF = 0x13,
4216	/** \#VE - Virtualization Exception. */
4217	X86_XCPT_VE = 0x14,
4218	/** \#SX - Security Exception. */
4219	X86_XCPT_SX = 0x1e
4220	} X86XCPT;
4221	/** Pointer to a x86 exception code. */
4222	typedef X86XCPT *PX86XCPT;
4223	/** Pointer to a const x86 exception code. */
4224	typedef const X86XCPT *PCX86XCPT;
4225	/** The last valid (currently reserved) exception value. */
4226	#define X86_XCPT_LAST 0x1f
4227
4228
4229	/** @name Trap Error Codes
4230	* @{
4231	*/
4232	/** External indicator. */
4233	#define X86_TRAP_ERR_EXTERNAL 1
4234	/** IDT indicator. */
4235	#define X86_TRAP_ERR_IDT 2
4236	/** Descriptor table indicator - If set LDT, if clear GDT. */
4237	#define X86_TRAP_ERR_TI 4
4238	/** Mask for getting the selector. */
4239	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4240	/** Shift for getting the selector table index (C type index). */
4241	#define X86_TRAP_ERR_SEL_SHIFT 3
4242	/** @} */
4243
4244
4245	/** @name \#PF Trap Error Codes
4246	* @{
4247	*/
4248	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4249	#define X86_TRAP_PF_P RT_BIT_32(0)
4250	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4251	#define X86_TRAP_PF_RW RT_BIT_32(1)
4252	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4253	#define X86_TRAP_PF_US RT_BIT_32(2)
4254	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4255	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4256	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4257	#define X86_TRAP_PF_ID RT_BIT_32(4)
4258	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4259	#define X86_TRAP_PF_PK RT_BIT_32(5)
4260	/** @} */
4261
4262	#pragma pack(1)
4263	/**
4264	* 16-bit IDTR.
4265	*/
4266	typedef struct X86IDTR16
4267	{
4268	/** Offset. */
4269	uint16_t offSel;
4270	/** Selector. */
4271	uint16_t uSel;
4272	} X86IDTR16, *PX86IDTR16;
4273	#pragma pack()
4274
4275	#pragma pack(1)
4276	/**
4277	* 32-bit IDTR/GDTR.
4278	*/
4279	typedef struct X86XDTR32
4280	{
4281	/** Size of the descriptor table. */
4282	uint16_t cb;
4283	/** Address of the descriptor table. */
4284	#ifndef VBOX_FOR_DTRACE_LIB
4285	uint32_t uAddr;
4286	#else
4287	uint16_t au16Addr[2];
4288	#endif
4289	} X86XDTR32, *PX86XDTR32;
4290	#pragma pack()
4291
4292	#pragma pack(1)
4293	/**
4294	* 64-bit IDTR/GDTR.
4295	*/
4296	typedef struct X86XDTR64
4297	{
4298	/** Size of the descriptor table. */
4299	uint16_t cb;
4300	/** Address of the descriptor table. */
4301	#ifndef VBOX_FOR_DTRACE_LIB
4302	uint64_t uAddr;
4303	#else
4304	uint16_t au16Addr[4];
4305	#endif
4306	} X86XDTR64, *PX86XDTR64;
4307	#pragma pack()
4308
4309
4310	/** @name ModR/M
4311	* @{ */
4312	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4313	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4314	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4315	#define X86_MODRM_REG_SHIFT 3
4316	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4317	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4318	#define X86_MODRM_MOD_SHIFT 6
4319	#ifndef VBOX_FOR_DTRACE_LIB
4320	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4321	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4322	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4323	/** @def X86_MODRM_MAKE
4324	* @param a_Mod The mod value (0..3).
4325	* @param a_Reg The register value (0..7).
4326	* @param a_RegMem The register or memory value (0..7). */
4327	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4328	#endif
4329	/** @} */
4330
4331	/** @name SIB
4332	* @{ */
4333	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4334	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4335	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4336	#define X86_SIB_INDEX_SHIFT 3
4337	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4338	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4339	#define X86_SIB_SCALE_SHIFT 6
4340	#ifndef VBOX_FOR_DTRACE_LIB
4341	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4342	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4343	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4344	#endif
4345	/** @} */
4346
4347	/** @name General register indexes
4348	* @{ */
4349	#define X86_GREG_xAX 0
4350	#define X86_GREG_xCX 1
4351	#define X86_GREG_xDX 2
4352	#define X86_GREG_xBX 3
4353	#define X86_GREG_xSP 4
4354	#define X86_GREG_xBP 5
4355	#define X86_GREG_xSI 6
4356	#define X86_GREG_xDI 7
4357	#define X86_GREG_x8 8
4358	#define X86_GREG_x9 9
4359	#define X86_GREG_x10 10
4360	#define X86_GREG_x11 11
4361	#define X86_GREG_x12 12
4362	#define X86_GREG_x13 13
4363	#define X86_GREG_x14 14
4364	#define X86_GREG_x15 15
4365	/** @} */
4366
4367	/** @name X86_SREG_XXX - Segment register indexes.
4368	* @{ */
4369	#define X86_SREG_ES 0
4370	#define X86_SREG_CS 1
4371	#define X86_SREG_SS 2
4372	#define X86_SREG_DS 3
4373	#define X86_SREG_FS 4
4374	#define X86_SREG_GS 5
4375	/** @} */
4376	/** Segment register count. */
4377	#define X86_SREG_COUNT 6
4378
4379
4380	/** @name X86_OP_XXX - Prefixes
4381	* @{ */
4382	#define X86_OP_PRF_CS UINT8_C(0x2e)
4383	#define X86_OP_PRF_SS UINT8_C(0x36)
4384	#define X86_OP_PRF_DS UINT8_C(0x3e)
4385	#define X86_OP_PRF_ES UINT8_C(0x26)
4386	#define X86_OP_PRF_FS UINT8_C(0x64)
4387	#define X86_OP_PRF_GS UINT8_C(0x65)
4388	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4389	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4390	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4391	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4392	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4393	#define X86_OP_REX_B UINT8_C(0x41)
4394	#define X86_OP_REX_X UINT8_C(0x42)
4395	#define X86_OP_REX_R UINT8_C(0x44)
4396	#define X86_OP_REX_W UINT8_C(0x48)
4397	/** @} */
4398
4399
4400	/** @} */
4401
4402	#endif /* !IPRT_INCLUDED_x86_h */
4403

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source: vbox/trunk/include/iprt/x86.h@ 76687

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