VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 81204

Last change on this file since 81204 was 80505, checked in by vboxsync, 5 years ago

x86.h: Added LBR to/from IP (instruction pointer) MSRs.
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File size: 170.5 KB
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2019 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef IPRT_INCLUDED_x86_h
29#define IPRT_INCLUDED_x86_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <iprt/types.h>
36# include <iprt/assert.h>
37#else
38# pragma D depends_on library vbox-types.d
39#endif
40
41/* Workaround for Solaris sys/regset.h defining CS, DS */
42#ifdef RT_OS_SOLARIS
43# undef CS
44# undef DS
45#endif
46
47/** @defgroup grp_rt_x86 x86 Types and Definitions
48 * @ingroup grp_rt
49 * @{
50 */
51
52#ifndef VBOX_FOR_DTRACE_LIB
53/**
54 * EFLAGS Bits.
55 */
56typedef struct X86EFLAGSBITS
57{
58 /** Bit 0 - CF - Carry flag - Status flag. */
59 unsigned u1CF : 1;
60 /** Bit 1 - 1 - Reserved flag. */
61 unsigned u1Reserved0 : 1;
62 /** Bit 2 - PF - Parity flag - Status flag. */
63 unsigned u1PF : 1;
64 /** Bit 3 - 0 - Reserved flag. */
65 unsigned u1Reserved1 : 1;
66 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67 unsigned u1AF : 1;
68 /** Bit 5 - 0 - Reserved flag. */
69 unsigned u1Reserved2 : 1;
70 /** Bit 6 - ZF - Zero flag - Status flag. */
71 unsigned u1ZF : 1;
72 /** Bit 7 - SF - Signed flag - Status flag. */
73 unsigned u1SF : 1;
74 /** Bit 8 - TF - Trap flag - System flag. */
75 unsigned u1TF : 1;
76 /** Bit 9 - IF - Interrupt flag - System flag. */
77 unsigned u1IF : 1;
78 /** Bit 10 - DF - Direction flag - Control flag. */
79 unsigned u1DF : 1;
80 /** Bit 11 - OF - Overflow flag - Status flag. */
81 unsigned u1OF : 1;
82 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83 unsigned u2IOPL : 2;
84 /** Bit 14 - NT - Nested task flag - System flag. */
85 unsigned u1NT : 1;
86 /** Bit 15 - 0 - Reserved flag. */
87 unsigned u1Reserved3 : 1;
88 /** Bit 16 - RF - Resume flag - System flag. */
89 unsigned u1RF : 1;
90 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
91 unsigned u1VM : 1;
92 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93 unsigned u1AC : 1;
94 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95 unsigned u1VIF : 1;
96 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97 unsigned u1VIP : 1;
98 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99 unsigned u1ID : 1;
100 /** Bit 22-31 - 0 - Reserved flag. */
101 unsigned u10Reserved4 : 10;
102} X86EFLAGSBITS;
103/** Pointer to EFLAGS bits. */
104typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105/** Pointer to const EFLAGS bits. */
106typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107#endif /* !VBOX_FOR_DTRACE_LIB */
108
109/**
110 * EFLAGS.
111 */
112typedef union X86EFLAGS
113{
114 /** The plain unsigned view. */
115 uint32_t u;
116#ifndef VBOX_FOR_DTRACE_LIB
117 /** The bitfield view. */
118 X86EFLAGSBITS Bits;
119#endif
120 /** The 8-bit view. */
121 uint8_t au8[4];
122 /** The 16-bit view. */
123 uint16_t au16[2];
124 /** The 32-bit view. */
125 uint32_t au32[1];
126 /** The 32-bit view. */
127 uint32_t u32;
128} X86EFLAGS;
129/** Pointer to EFLAGS. */
130typedef X86EFLAGS *PX86EFLAGS;
131/** Pointer to const EFLAGS. */
132typedef const X86EFLAGS *PCX86EFLAGS;
133
134/**
135 * RFLAGS (32 upper bits are reserved).
136 */
137typedef union X86RFLAGS
138{
139 /** The plain unsigned view. */
140 uint64_t u;
141#ifndef VBOX_FOR_DTRACE_LIB
142 /** The bitfield view. */
143 X86EFLAGSBITS Bits;
144#endif
145 /** The 8-bit view. */
146 uint8_t au8[8];
147 /** The 16-bit view. */
148 uint16_t au16[4];
149 /** The 32-bit view. */
150 uint32_t au32[2];
151 /** The 64-bit view. */
152 uint64_t au64[1];
153 /** The 64-bit view. */
154 uint64_t u64;
155} X86RFLAGS;
156/** Pointer to RFLAGS. */
157typedef X86RFLAGS *PX86RFLAGS;
158/** Pointer to const RFLAGS. */
159typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162/** @name EFLAGS
163 * @{
164 */
165/** Bit 0 - CF - Carry flag - Status flag. */
166#define X86_EFL_CF RT_BIT_32(0)
167#define X86_EFL_CF_BIT 0
168/** Bit 1 - Reserved, reads as 1. */
169#define X86_EFL_1 RT_BIT_32(1)
170/** Bit 2 - PF - Parity flag - Status flag. */
171#define X86_EFL_PF RT_BIT_32(2)
172/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173#define X86_EFL_AF RT_BIT_32(4)
174#define X86_EFL_AF_BIT 4
175/** Bit 6 - ZF - Zero flag - Status flag. */
176#define X86_EFL_ZF RT_BIT_32(6)
177#define X86_EFL_ZF_BIT 6
178/** Bit 7 - SF - Signed flag - Status flag. */
179#define X86_EFL_SF RT_BIT_32(7)
180#define X86_EFL_SF_BIT 7
181/** Bit 8 - TF - Trap flag - System flag. */
182#define X86_EFL_TF RT_BIT_32(8)
183/** Bit 9 - IF - Interrupt flag - System flag. */
184#define X86_EFL_IF RT_BIT_32(9)
185/** Bit 10 - DF - Direction flag - Control flag. */
186#define X86_EFL_DF RT_BIT_32(10)
187/** Bit 11 - OF - Overflow flag - Status flag. */
188#define X86_EFL_OF RT_BIT_32(11)
189#define X86_EFL_OF_BIT 11
190/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
192/** Bit 14 - NT - Nested task flag - System flag. */
193#define X86_EFL_NT RT_BIT_32(14)
194/** Bit 16 - RF - Resume flag - System flag. */
195#define X86_EFL_RF RT_BIT_32(16)
196/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197#define X86_EFL_VM RT_BIT_32(17)
198/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199#define X86_EFL_AC RT_BIT_32(18)
200/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201#define X86_EFL_VIF RT_BIT_32(19)
202/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203#define X86_EFL_VIP RT_BIT_32(20)
204/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205#define X86_EFL_ID RT_BIT_32(21)
206/** All live bits. */
207#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208/** Read as 1 bits. */
209#define X86_EFL_RA1_MASK RT_BIT_32(1)
210/** IOPL shift. */
211#define X86_EFL_IOPL_SHIFT 12
212/** The IOPL level from the flags. */
213#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
217/** Bits restored by popf */
218#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
219 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
220/** The status bits commonly updated by arithmetic instructions. */
221#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
222/** @} */
223
224
225/** CPUID Feature information - ECX.
226 * CPUID query with EAX=1.
227 */
228#ifndef VBOX_FOR_DTRACE_LIB
229typedef struct X86CPUIDFEATECX
230{
231 /** Bit 0 - SSE3 - Supports SSE3 or not. */
232 unsigned u1SSE3 : 1;
233 /** Bit 1 - PCLMULQDQ. */
234 unsigned u1PCLMULQDQ : 1;
235 /** Bit 2 - DS Area 64-bit layout. */
236 unsigned u1DTE64 : 1;
237 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238 unsigned u1Monitor : 1;
239 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240 unsigned u1CPLDS : 1;
241 /** Bit 5 - VMX - Virtual Machine Technology. */
242 unsigned u1VMX : 1;
243 /** Bit 6 - SMX: Safer Mode Extensions. */
244 unsigned u1SMX : 1;
245 /** Bit 7 - EST - Enh. SpeedStep Tech. */
246 unsigned u1EST : 1;
247 /** Bit 8 - TM2 - Terminal Monitor 2. */
248 unsigned u1TM2 : 1;
249 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250 unsigned u1SSSE3 : 1;
251 /** Bit 10 - CNTX-ID - L1 Context ID. */
252 unsigned u1CNTXID : 1;
253 /** Bit 11 - Reserved. */
254 unsigned u1Reserved1 : 1;
255 /** Bit 12 - FMA. */
256 unsigned u1FMA : 1;
257 /** Bit 13 - CX16 - CMPXCHG16B. */
258 unsigned u1CX16 : 1;
259 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260 unsigned u1TPRUpdate : 1;
261 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262 unsigned u1PDCM : 1;
263 /** Bit 16 - Reserved. */
264 unsigned u1Reserved2 : 1;
265 /** Bit 17 - PCID - Process-context identifiers. */
266 unsigned u1PCID : 1;
267 /** Bit 18 - Direct Cache Access. */
268 unsigned u1DCA : 1;
269 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270 unsigned u1SSE4_1 : 1;
271 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272 unsigned u1SSE4_2 : 1;
273 /** Bit 21 - x2APIC. */
274 unsigned u1x2APIC : 1;
275 /** Bit 22 - MOVBE - Supports MOVBE. */
276 unsigned u1MOVBE : 1;
277 /** Bit 23 - POPCNT - Supports POPCNT. */
278 unsigned u1POPCNT : 1;
279 /** Bit 24 - TSC-Deadline. */
280 unsigned u1TSCDEADLINE : 1;
281 /** Bit 25 - AES. */
282 unsigned u1AES : 1;
283 /** Bit 26 - XSAVE - Supports XSAVE. */
284 unsigned u1XSAVE : 1;
285 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286 unsigned u1OSXSAVE : 1;
287 /** Bit 28 - AVX - Supports AVX instruction extensions. */
288 unsigned u1AVX : 1;
289 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290 unsigned u1F16C : 1;
291 /** Bit 30 - RDRAND - Supports RDRAND. */
292 unsigned u1RDRAND : 1;
293 /** Bit 31 - Hypervisor present (we're a guest). */
294 unsigned u1HVP : 1;
295} X86CPUIDFEATECX;
296#else /* VBOX_FOR_DTRACE_LIB */
297typedef uint32_t X86CPUIDFEATECX;
298#endif /* VBOX_FOR_DTRACE_LIB */
299/** Pointer to CPUID Feature Information - ECX. */
300typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301/** Pointer to const CPUID Feature Information - ECX. */
302typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305/** CPUID Feature Information - EDX.
306 * CPUID query with EAX=1.
307 */
308#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309typedef struct X86CPUIDFEATEDX
310{
311 /** Bit 0 - FPU - x87 FPU on Chip. */
312 unsigned u1FPU : 1;
313 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314 unsigned u1VME : 1;
315 /** Bit 2 - DE - Debugging extensions. */
316 unsigned u1DE : 1;
317 /** Bit 3 - PSE - Page Size Extension. */
318 unsigned u1PSE : 1;
319 /** Bit 4 - TSC - Time Stamp Counter. */
320 unsigned u1TSC : 1;
321 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322 unsigned u1MSR : 1;
323 /** Bit 6 - PAE - Physical Address Extension. */
324 unsigned u1PAE : 1;
325 /** Bit 7 - MCE - Machine Check Exception. */
326 unsigned u1MCE : 1;
327 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
328 unsigned u1CX8 : 1;
329 /** Bit 9 - APIC - APIC On-Chip. */
330 unsigned u1APIC : 1;
331 /** Bit 10 - Reserved. */
332 unsigned u1Reserved1 : 1;
333 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334 unsigned u1SEP : 1;
335 /** Bit 12 - MTRR - Memory Type Range Registers. */
336 unsigned u1MTRR : 1;
337 /** Bit 13 - PGE - PTE Global Bit. */
338 unsigned u1PGE : 1;
339 /** Bit 14 - MCA - Machine Check Architecture. */
340 unsigned u1MCA : 1;
341 /** Bit 15 - CMOV - Conditional Move Instructions. */
342 unsigned u1CMOV : 1;
343 /** Bit 16 - PAT - Page Attribute Table. */
344 unsigned u1PAT : 1;
345 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346 unsigned u1PSE36 : 1;
347 /** Bit 18 - PSN - Processor Serial Number. */
348 unsigned u1PSN : 1;
349 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
350 unsigned u1CLFSH : 1;
351 /** Bit 20 - Reserved. */
352 unsigned u1Reserved2 : 1;
353 /** Bit 21 - DS - Debug Store. */
354 unsigned u1DS : 1;
355 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356 unsigned u1ACPI : 1;
357 /** Bit 23 - MMX - Intel MMX 'Technology'. */
358 unsigned u1MMX : 1;
359 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360 unsigned u1FXSR : 1;
361 /** Bit 25 - SSE - SSE Support. */
362 unsigned u1SSE : 1;
363 /** Bit 26 - SSE2 - SSE2 Support. */
364 unsigned u1SSE2 : 1;
365 /** Bit 27 - SS - Self Snoop. */
366 unsigned u1SS : 1;
367 /** Bit 28 - HTT - Hyper-Threading Technology. */
368 unsigned u1HTT : 1;
369 /** Bit 29 - TM - Thermal Monitor. */
370 unsigned u1TM : 1;
371 /** Bit 30 - Reserved - . */
372 unsigned u1Reserved3 : 1;
373 /** Bit 31 - PBE - Pending Break Enabled. */
374 unsigned u1PBE : 1;
375} X86CPUIDFEATEDX;
376#else /* VBOX_FOR_DTRACE_LIB */
377typedef uint32_t X86CPUIDFEATEDX;
378#endif /* VBOX_FOR_DTRACE_LIB */
379/** Pointer to CPUID Feature Information - EDX. */
380typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381/** Pointer to const CPUID Feature Information - EDX. */
382typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384/** @name CPUID Vendor information.
385 * CPUID query with EAX=0.
386 * @{
387 */
388#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399
400#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
401#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
402#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
403/** @} */
404
405
406/** @name CPUID Feature information.
407 * CPUID query with EAX=1.
408 * @{
409 */
410/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
411#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
412/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
413#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
414/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
415#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
416/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
417#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
418/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
419#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
420/** ECX Bit 5 - VMX - Virtual Machine Technology. */
421#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
422/** ECX Bit 6 - SMX - Safer Mode Extensions. */
423#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
424/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
425#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
426/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
427#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
428/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
429#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
430/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
431#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
432/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
433 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
434#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
435/** ECX Bit 12 - FMA. */
436#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
437/** ECX Bit 13 - CX16 - CMPXCHG16B. */
438#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
439/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
440#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
441/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
442#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
443/** ECX Bit 17 - PCID - Process-context identifiers. */
444#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
445/** ECX Bit 18 - DCA - Direct Cache Access. */
446#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
447/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
448#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
449/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
450#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
451/** ECX Bit 21 - x2APIC support. */
452#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
453/** ECX Bit 22 - MOVBE instruction. */
454#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
455/** ECX Bit 23 - POPCNT instruction. */
456#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
457/** ECX Bir 24 - TSC-Deadline. */
458#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
459/** ECX Bit 25 - AES instructions. */
460#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
461/** ECX Bit 26 - XSAVE instruction. */
462#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
463/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
464#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
465/** ECX Bit 28 - AVX. */
466#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
467/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
468#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
469/** ECX Bit 30 - RDRAND instruction. */
470#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
471/** ECX Bit 31 - Hypervisor Present (software only). */
472#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
473
474
475/** Bit 0 - FPU - x87 FPU on Chip. */
476#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
477/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
478#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
479/** Bit 2 - DE - Debugging extensions. */
480#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
481/** Bit 3 - PSE - Page Size Extension. */
482#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
483#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
484/** Bit 4 - TSC - Time Stamp Counter. */
485#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
486/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
487#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
488/** Bit 6 - PAE - Physical Address Extension. */
489#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
490#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
491/** Bit 7 - MCE - Machine Check Exception. */
492#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
493/** Bit 8 - CX8 - CMPXCHG8B instruction. */
494#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
495/** Bit 9 - APIC - APIC On-Chip. */
496#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
497/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
498#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
499/** Bit 12 - MTRR - Memory Type Range Registers. */
500#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
501/** Bit 13 - PGE - PTE Global Bit. */
502#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
503/** Bit 14 - MCA - Machine Check Architecture. */
504#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
505/** Bit 15 - CMOV - Conditional Move Instructions. */
506#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
507/** Bit 16 - PAT - Page Attribute Table. */
508#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
509/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
510#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
511/** Bit 18 - PSN - Processor Serial Number. */
512#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
513/** Bit 19 - CLFSH - CLFLUSH Instruction. */
514#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
515/** Bit 21 - DS - Debug Store. */
516#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
517/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
518#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
519/** Bit 23 - MMX - Intel MMX Technology. */
520#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
521/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
522#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
523/** Bit 25 - SSE - SSE Support. */
524#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
525/** Bit 26 - SSE2 - SSE2 Support. */
526#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
527/** Bit 27 - SS - Self Snoop. */
528#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
529/** Bit 28 - HTT - Hyper-Threading Technology. */
530#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
531/** Bit 29 - TM - Therm. Monitor. */
532#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
533/** Bit 31 - PBE - Pending Break Enabled. */
534#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
535/** @} */
536
537/** @name CPUID mwait/monitor information.
538 * CPUID query with EAX=5.
539 * @{
540 */
541/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
542#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
543/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
544#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
545/** @} */
546
547
548/** @name CPUID Structured Extended Feature information.
549 * CPUID query with EAX=7.
550 * @{
551 */
552/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
553#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
554/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
555#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
556/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
557#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
558/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
559#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
560/** EBX Bit 4 - HLE - Hardware Lock Elision. */
561#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
562/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
563#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
564/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
565#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
566/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
567#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
568/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
569#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
570/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
571#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
572/** EBX Bit 10 - INVPCID - Supports INVPCID. */
573#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
574/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
575#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
576/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
577#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
578/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
579#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
580/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
581#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
582/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
583#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
584/** EBX Bit 16 - AVX512F - Supports AVX512F. */
585#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
586/** EBX Bit 18 - RDSEED - Supports RDSEED. */
587#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
588/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
589#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
590/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
591#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
592/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
593#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
594/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
595#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
596/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
597#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
598/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
599#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
600/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
601#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
602/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
603#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
604
605/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
606#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
607/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
608#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
609/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
610#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
611/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
612#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
613/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
614#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
615/** ECX Bit 22 - RDPID - Support pread process ID. */
616#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
617/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
618#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
619
620/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
621#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
622/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
623 * IBPB command in IA32_PRED_CMD. */
624#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
625/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
626#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
627/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
628#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
629/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
630#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
631
632/** @} */
633
634
635/** @name CPUID Extended Feature information.
636 * CPUID query with EAX=0x80000001.
637 * @{
638 */
639/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
640#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
641
642/** EDX Bit 11 - SYSCALL/SYSRET. */
643#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
644/** EDX Bit 20 - No-Execute/Execute-Disable. */
645#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
646/** EDX Bit 26 - 1 GB large page. */
647#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
648/** EDX Bit 27 - RDTSCP. */
649#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
650/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
651#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
652/** @}*/
653
654/** @name CPUID AMD Feature information.
655 * CPUID query with EAX=0x80000001.
656 * @{
657 */
658/** Bit 0 - FPU - x87 FPU on Chip. */
659#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
660/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
661#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
662/** Bit 2 - DE - Debugging extensions. */
663#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
664/** Bit 3 - PSE - Page Size Extension. */
665#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
666/** Bit 4 - TSC - Time Stamp Counter. */
667#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
668/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
669#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
670/** Bit 6 - PAE - Physical Address Extension. */
671#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
672/** Bit 7 - MCE - Machine Check Exception. */
673#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
674/** Bit 8 - CX8 - CMPXCHG8B instruction. */
675#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
676/** Bit 9 - APIC - APIC On-Chip. */
677#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
678/** Bit 12 - MTRR - Memory Type Range Registers. */
679#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
680/** Bit 13 - PGE - PTE Global Bit. */
681#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
682/** Bit 14 - MCA - Machine Check Architecture. */
683#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
684/** Bit 15 - CMOV - Conditional Move Instructions. */
685#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
686/** Bit 16 - PAT - Page Attribute Table. */
687#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
688/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
689#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
690/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
691#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
692/** Bit 23 - MMX - Intel MMX Technology. */
693#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
694/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
695#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
696/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
697#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
698/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
699#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
700/** Bit 31 - 3DNOW - AMD 3DNow. */
701#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
702
703/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
704#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
705/** Bit 2 - SVM - AMD VM extensions. */
706#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
707/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
708#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
709/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
710#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
711/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
712#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
713/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
714#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
715/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
716#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
717/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
718#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
719/** Bit 9 - OSVW - AMD OS visible workaround. */
720#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
721/** Bit 10 - IBS - Instruct based sampling. */
722#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
723/** Bit 11 - XOP - Extended operation support (see APM6). */
724#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
725/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
726#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
727/** Bit 13 - WDT - AMD Watchdog timer support. */
728#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
729/** Bit 15 - LWP - Lightweight profiling support. */
730#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
731/** Bit 16 - FMA4 - Four operand FMA instruction support. */
732#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
733/** Bit 19 - NodeId - Indicates support for
734 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
735#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
736/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
737#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
738/** Bit 22 - TopologyExtensions - . */
739#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
740/** @} */
741
742
743/** @name CPUID AMD Feature information.
744 * CPUID query with EAX=0x80000007.
745 * @{
746 */
747/** Bit 0 - TS - Temperature Sensor. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
749/** Bit 1 - FID - Frequency ID Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
751/** Bit 2 - VID - Voltage ID Control. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
753/** Bit 3 - TTP - THERMTRIP. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
755/** Bit 4 - TM - Hardware Thermal Control. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
757/** Bit 5 - STC - Software Thermal Control. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
759/** Bit 6 - MC - 100 Mhz Multiplier Control. */
760#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
761/** Bit 7 - HWPSTATE - Hardware P-State Control. */
762#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
763/** Bit 8 - TSCINVAR - TSC Invariant. */
764#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
765/** Bit 9 - CPB - TSC Invariant. */
766#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
767/** Bit 10 - EffFreqRO - MPERF/APERF. */
768#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
769/** Bit 11 - PFI - Processor feedback interface (see EAX). */
770#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
771/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
772#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
773/** @} */
774
775
776/** @name CPUID AMD extended feature extensions ID (EBX).
777 * CPUID query with EAX=0x80000008.
778 * @{
779 */
780/** Bit 0 - CLZERO - Clear zero instruction. */
781#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
782/** Bit 1 - IRPerf - Instructions retired count support. */
783#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
784/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
785#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
786/* AMD pipeline length: 9 feature bits ;-) */
787/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
788#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
789/** @} */
790
791
792/** @name CPUID AMD SVM Feature information.
793 * CPUID query with EAX=0x8000000a.
794 * @{
795 */
796/** Bit 0 - NP - Nested Paging supported. */
797#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
798/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
799#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
800/** Bit 2 - SVML - SVM locking bit supported. */
801#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
802/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
803#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
804/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
805#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
806/** Bit 5 - VmcbClean - Support VMCB clean bits. */
807#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
808/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
809 * VMCB.TLB_Control is supported. */
810#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
811/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
812#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
813/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
814#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
815/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
816 * intercept filter cycle count threshold. */
817#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
818/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
819#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
820/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
821#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
822/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
823#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
824/** @} */
825
826
827/** @name CR0
828 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
829 * reserved flags.
830 * @{ */
831/** Bit 0 - PE - Protection Enabled */
832#define X86_CR0_PE RT_BIT_32(0)
833#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
834/** Bit 1 - MP - Monitor Coprocessor */
835#define X86_CR0_MP RT_BIT_32(1)
836#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
837/** Bit 2 - EM - Emulation. */
838#define X86_CR0_EM RT_BIT_32(2)
839#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
840/** Bit 3 - TS - Task Switch. */
841#define X86_CR0_TS RT_BIT_32(3)
842#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
843/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
844#define X86_CR0_ET RT_BIT_32(4)
845#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
846/** Bit 5 - NE - Numeric error (486+). */
847#define X86_CR0_NE RT_BIT_32(5)
848#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
849/** Bit 16 - WP - Write Protect (486+). */
850#define X86_CR0_WP RT_BIT_32(16)
851#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
852/** Bit 18 - AM - Alignment Mask (486+). */
853#define X86_CR0_AM RT_BIT_32(18)
854#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
855/** Bit 29 - NW - Not Write-though (486+). */
856#define X86_CR0_NW RT_BIT_32(29)
857#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
858/** Bit 30 - WP - Cache Disable (486+). */
859#define X86_CR0_CD RT_BIT_32(30)
860#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
861/** Bit 31 - PG - Paging. */
862#define X86_CR0_PG RT_BIT_32(31)
863#define X86_CR0_PAGING RT_BIT_32(31)
864#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
865/** @} */
866
867
868/** @name CR3
869 * @{ */
870/** Bit 3 - PWT - Page-level Writes Transparent. */
871#define X86_CR3_PWT RT_BIT_32(3)
872/** Bit 4 - PCD - Page-level Cache Disable. */
873#define X86_CR3_PCD RT_BIT_32(4)
874/** Bits 12-31 - - Page directory page number. */
875#define X86_CR3_PAGE_MASK (0xfffff000)
876/** Bits 5-31 - - PAE Page directory page number. */
877#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
878/** Bits 12-51 - - AMD64 Page directory page number. */
879#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
880/** @} */
881
882
883/** @name CR4
884 * @{ */
885/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
886#define X86_CR4_VME RT_BIT_32(0)
887/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
888#define X86_CR4_PVI RT_BIT_32(1)
889/** Bit 2 - TSD - Time Stamp Disable. */
890#define X86_CR4_TSD RT_BIT_32(2)
891/** Bit 3 - DE - Debugging Extensions. */
892#define X86_CR4_DE RT_BIT_32(3)
893/** Bit 4 - PSE - Page Size Extension. */
894#define X86_CR4_PSE RT_BIT_32(4)
895/** Bit 5 - PAE - Physical Address Extension. */
896#define X86_CR4_PAE RT_BIT_32(5)
897/** Bit 6 - MCE - Machine-Check Enable. */
898#define X86_CR4_MCE RT_BIT_32(6)
899/** Bit 7 - PGE - Page Global Enable. */
900#define X86_CR4_PGE RT_BIT_32(7)
901/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
902#define X86_CR4_PCE RT_BIT_32(8)
903/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
904#define X86_CR4_OSFXSR RT_BIT_32(9)
905/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
906#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
907/** Bit 13 - VMXE - VMX mode is enabled. */
908#define X86_CR4_VMXE RT_BIT_32(13)
909/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
910#define X86_CR4_SMXE RT_BIT_32(14)
911/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
912#define X86_CR4_FSGSBASE RT_BIT_32(16)
913/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
914#define X86_CR4_PCIDE RT_BIT_32(17)
915/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
916 * extended states. */
917#define X86_CR4_OSXSAVE RT_BIT_32(18)
918/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
919#define X86_CR4_SMEP RT_BIT_32(20)
920/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
921#define X86_CR4_SMAP RT_BIT_32(21)
922/** Bit 22 - PKE - Protection Key Enable. */
923#define X86_CR4_PKE RT_BIT_32(22)
924/** @} */
925
926
927/** @name DR6
928 * @{ */
929/** Bit 0 - B0 - Breakpoint 0 condition detected. */
930#define X86_DR6_B0 RT_BIT_32(0)
931/** Bit 1 - B1 - Breakpoint 1 condition detected. */
932#define X86_DR6_B1 RT_BIT_32(1)
933/** Bit 2 - B2 - Breakpoint 2 condition detected. */
934#define X86_DR6_B2 RT_BIT_32(2)
935/** Bit 3 - B3 - Breakpoint 3 condition detected. */
936#define X86_DR6_B3 RT_BIT_32(3)
937/** Mask of all the Bx bits. */
938#define X86_DR6_B_MASK UINT64_C(0x0000000f)
939/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
940#define X86_DR6_BD RT_BIT_32(13)
941/** Bit 14 - BS - Single step */
942#define X86_DR6_BS RT_BIT_32(14)
943/** Bit 15 - BT - Task switch. (TSS T bit.) */
944#define X86_DR6_BT RT_BIT_32(15)
945/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
946#define X86_DR6_RTM RT_BIT_32(16)
947/** Value of DR6 after powerup/reset. */
948#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
949/** Bits which must be 1s in DR6. */
950#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
951/** Bits which must be 1s in DR6, when RTM is supported. */
952#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
953/** Bits which must be 0s in DR6. */
954#define X86_DR6_RAZ_MASK RT_BIT_64(12)
955/** Bits which must be 0s on writes to DR6. */
956#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
957/** @} */
958
959/** Get the DR6.Bx bit for a the given breakpoint. */
960#define X86_DR6_B(iBp) RT_BIT_64(iBp)
961
962
963/** @name DR7
964 * @{ */
965/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
966#define X86_DR7_L0 RT_BIT_32(0)
967/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
968#define X86_DR7_G0 RT_BIT_32(1)
969/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
970#define X86_DR7_L1 RT_BIT_32(2)
971/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
972#define X86_DR7_G1 RT_BIT_32(3)
973/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
974#define X86_DR7_L2 RT_BIT_32(4)
975/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
976#define X86_DR7_G2 RT_BIT_32(5)
977/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
978#define X86_DR7_L3 RT_BIT_32(6)
979/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
980#define X86_DR7_G3 RT_BIT_32(7)
981/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
982#define X86_DR7_LE RT_BIT_32(8)
983/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
984#define X86_DR7_GE RT_BIT_32(9)
985
986/** L0, L1, L2, and L3. */
987#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
988/** L0, L1, L2, and L3. */
989#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
990
991/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
992 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
993#define X86_DR7_RTM RT_BIT_32(11)
994/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
995 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
996 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
997 * instruction is executed.
998 * @see http://www.rcollins.org/secrets/DR7.html */
999#define X86_DR7_ICE_IR RT_BIT_32(12)
1000/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1001 * any DR register is accessed. */
1002#define X86_DR7_GD RT_BIT_32(13)
1003/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1004 * Pentium. */
1005#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1006/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1007#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1008/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1009#define X86_DR7_RW0_MASK (3 << 16)
1010/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1011#define X86_DR7_LEN0_MASK (3 << 18)
1012/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1013#define X86_DR7_RW1_MASK (3 << 20)
1014/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1015#define X86_DR7_LEN1_MASK (3 << 22)
1016/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1017#define X86_DR7_RW2_MASK (3 << 24)
1018/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1019#define X86_DR7_LEN2_MASK (3 << 26)
1020/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1021#define X86_DR7_RW3_MASK (3 << 28)
1022/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1023#define X86_DR7_LEN3_MASK (3 << 30)
1024
1025/** Bits which reads as 1s. */
1026#define X86_DR7_RA1_MASK RT_BIT_32(10)
1027/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1028#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1029/** Bits which must be 0s when writing to DR7. */
1030#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1031
1032/** Calcs the L bit of Nth breakpoint.
1033 * @param iBp The breakpoint number [0..3].
1034 */
1035#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1036
1037/** Calcs the G bit of Nth breakpoint.
1038 * @param iBp The breakpoint number [0..3].
1039 */
1040#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1041
1042/** Calcs the L and G bits of Nth breakpoint.
1043 * @param iBp The breakpoint number [0..3].
1044 */
1045#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1046
1047/** @name Read/Write values.
1048 * @{ */
1049/** Break on instruction fetch only. */
1050#define X86_DR7_RW_EO UINT32_C(0)
1051/** Break on write only. */
1052#define X86_DR7_RW_WO UINT32_C(1)
1053/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1054#define X86_DR7_RW_IO UINT32_C(2)
1055/** Break on read or write (but not instruction fetches). */
1056#define X86_DR7_RW_RW UINT32_C(3)
1057/** @} */
1058
1059/** Shifts a X86_DR7_RW_* value to its right place.
1060 * @param iBp The breakpoint number [0..3].
1061 * @param fRw One of the X86_DR7_RW_* value.
1062 */
1063#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1064
1065/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1066 * one of the X86_DR7_RW_XXX constants).
1067 *
1068 * @returns X86_DR7_RW_XXX
1069 * @param uDR7 DR7 value
1070 * @param iBp The breakpoint number [0..3].
1071 */
1072#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1073
1074/** R/W0, R/W1, R/W2, and R/W3. */
1075#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1076
1077#ifndef VBOX_FOR_DTRACE_LIB
1078/** Checks if there are any I/O breakpoint types configured in the RW
1079 * registers. Does NOT check if these are enabled, sorry. */
1080# define X86_DR7_ANY_RW_IO(uDR7) \
1081 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1082 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1083AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1084AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1085AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1086AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1087AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1088AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1089AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1090AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1091AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1092#endif /* !VBOX_FOR_DTRACE_LIB */
1093
1094/** @name Length values.
1095 * @{ */
1096#define X86_DR7_LEN_BYTE UINT32_C(0)
1097#define X86_DR7_LEN_WORD UINT32_C(1)
1098#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1099#define X86_DR7_LEN_DWORD UINT32_C(3)
1100/** @} */
1101
1102/** Shifts a X86_DR7_LEN_* value to its right place.
1103 * @param iBp The breakpoint number [0..3].
1104 * @param cb One of the X86_DR7_LEN_* values.
1105 */
1106#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1107
1108/** Fetch the breakpoint length bits from the DR7 value.
1109 * @param uDR7 DR7 value
1110 * @param iBp The breakpoint number [0..3].
1111 */
1112#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1113
1114/** Mask used to check if any breakpoints are enabled. */
1115#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1116
1117/** LEN0, LEN1, LEN2, and LEN3. */
1118#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1119/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1120#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1121
1122/** Value of DR7 after powerup/reset. */
1123#define X86_DR7_INIT_VAL 0x400
1124/** @} */
1125
1126
1127/** @name Machine Specific Registers
1128 * @{
1129 */
1130/** Machine check address register (P5). */
1131#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1132/** Machine check type register (P5). */
1133#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1134/** Time Stamp Counter. */
1135#define MSR_IA32_TSC 0x10
1136#define MSR_IA32_CESR UINT32_C(0x00000011)
1137#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1138#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1139
1140#define MSR_IA32_PLATFORM_ID 0x17
1141
1142#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1143# define MSR_IA32_APICBASE 0x1b
1144/** Local APIC enabled. */
1145# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1146/** X2APIC enabled (requires the EN bit to be set). */
1147# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1148/** The processor is the boot strap processor (BSP). */
1149# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1150/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1151 * width. */
1152# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1153/** The default physical base address of the APIC. */
1154# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1155/** Gets the physical base address from the MSR. */
1156# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1157#endif
1158
1159/** Undocumented intel MSR for reporting thread and core counts.
1160 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1161 * first 16 bits is the thread count. The next 16 bits the core count, except
1162 * on Westmere where it seems it's only the next 4 bits for some reason. */
1163#define MSR_CORE_THREAD_COUNT 0x35
1164
1165/** CPU Feature control. */
1166#define MSR_IA32_FEATURE_CONTROL 0x3A
1167/** Feature control - Lock MSR from writes (R/W0). */
1168#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1169/** Feature control - Enable VMX inside SMX operation (R/WL). */
1170#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1171/** Feature control - Enable VMX outside SMX operation (R/WL). */
1172#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1173/** Feature control - SENTER local functions enable (R/WL). */
1174#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1175#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1176#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1177#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1178#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1179#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1180#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1181/** Feature control - SENTER global enable (R/WL). */
1182#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1183/** Feature control - SGX launch control enable (R/WL). */
1184#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1185/** Feature control - SGX global enable (R/WL). */
1186#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1187/** Feature control - LMCE on (R/WL). */
1188#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1189
1190/** Per-processor TSC adjust MSR. */
1191#define MSR_IA32_TSC_ADJUST 0x3B
1192
1193/** Spectre control register.
1194 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1195#define MSR_IA32_SPEC_CTRL 0x48
1196/** IBRS - Indirect branch restricted speculation. */
1197#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1198/** STIBP - Single thread indirect branch predictors. */
1199#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1200
1201/** Prediction command register.
1202 * Write only, logical processor scope, no state since write only. */
1203#define MSR_IA32_PRED_CMD 0x49
1204/** IBPB - Indirect branch prediction barrie when written as 1. */
1205#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1206
1207/** BIOS update trigger (microcode update). */
1208#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1209
1210/** BIOS update signature (microcode). */
1211#define MSR_IA32_BIOS_SIGN_ID 0x8B
1212
1213/** SMM monitor control. */
1214#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1215/** SMM control - Valid. */
1216#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1217/** SMM control - VMXOFF unblocks SMI. */
1218#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1219/** SMM control - MSEG base physical address. */
1220#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1221
1222/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1223#define MSR_IA32_SMBASE 0x9E
1224
1225/** General performance counter no. 0. */
1226#define MSR_IA32_PMC0 0xC1
1227/** General performance counter no. 1. */
1228#define MSR_IA32_PMC1 0xC2
1229/** General performance counter no. 2. */
1230#define MSR_IA32_PMC2 0xC3
1231/** General performance counter no. 3. */
1232#define MSR_IA32_PMC3 0xC4
1233
1234/** Nehalem power control. */
1235#define MSR_IA32_PLATFORM_INFO 0xCE
1236
1237/** Get FSB clock status (Intel-specific). */
1238#define MSR_IA32_FSB_CLOCK_STS 0xCD
1239
1240/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1241#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1242
1243/** C0 Maximum Frequency Clock Count */
1244#define MSR_IA32_MPERF 0xE7
1245/** C0 Actual Frequency Clock Count */
1246#define MSR_IA32_APERF 0xE8
1247
1248/** MTRR Capabilities. */
1249#define MSR_IA32_MTRR_CAP 0xFE
1250
1251/** Architecture capabilities (bugfixes). */
1252#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1253/** CPU is no subject to meltdown problems. */
1254#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1255/** CPU has better IBRS and you can leave it on all the time. */
1256#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1257/** CPU has return stack buffer (RSB) override. */
1258#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1259/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1260 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1261#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1262/** CPU does not suffer from MDS issues. */
1263#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1264
1265/** Flush command register. */
1266#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1267/** Flush the level 1 data cache when this bit is written. */
1268#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1269
1270/** Cache control/info. */
1271#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1272
1273#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1274/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1275 * R0 SS == CS + 8
1276 * R3 CS == CS + 16
1277 * R3 SS == CS + 24
1278 */
1279#define MSR_IA32_SYSENTER_CS 0x174
1280/** SYSENTER_ESP - the R0 ESP. */
1281#define MSR_IA32_SYSENTER_ESP 0x175
1282/** SYSENTER_EIP - the R0 EIP. */
1283#define MSR_IA32_SYSENTER_EIP 0x176
1284#endif
1285
1286/** Machine Check Global Capabilities Register. */
1287#define MSR_IA32_MCG_CAP 0x179
1288/** Machine Check Global Status Register. */
1289#define MSR_IA32_MCG_STATUS 0x17A
1290/** Machine Check Global Control Register. */
1291#define MSR_IA32_MCG_CTRL 0x17B
1292
1293/** Page Attribute Table. */
1294#define MSR_IA32_CR_PAT 0x277
1295/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1296 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1297#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1298
1299/** Performance counter MSRs. (Intel only) */
1300#define MSR_IA32_PERFEVTSEL0 0x186
1301#define MSR_IA32_PERFEVTSEL1 0x187
1302/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1303 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1304 * holds a ratio that Apple takes for TSC granularity.
1305 *
1306 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1307#define MSR_FLEX_RATIO 0x194
1308/** Performance state value and starting with Intel core more.
1309 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1310#define MSR_IA32_PERF_STATUS 0x198
1311#define MSR_IA32_PERF_CTL 0x199
1312#define MSR_IA32_THERM_STATUS 0x19c
1313
1314/** Enable misc. processor features (R/W). */
1315#define MSR_IA32_MISC_ENABLE 0x1A0
1316/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1317#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1318/** Automatic Thermal Control Circuit Enable (R/W). */
1319#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1320/** Performance Monitoring Available (R). */
1321#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1322/** Branch Trace Storage Unavailable (R/O). */
1323#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1324/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1325#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1326/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1327#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1328/** If MONITOR/MWAIT is supported (R/W). */
1329#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1330/** Limit CPUID Maxval to 3 leafs (R/W). */
1331#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1332/** When set to 1, xTPR messages are disabled (R/W). */
1333#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1334/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1335#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1336
1337/** Trace/Profile Resource Control (R/W) */
1338#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1339/** Last branch record. */
1340#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1341/** Branch trace flag (single step on branches). */
1342#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1343/** Performance monitoring pin control (AMD only). */
1344#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1345#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1346#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1347#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1348/** Trace message enable (Intel only). */
1349#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1350/** Branch trace store (Intel only). */
1351#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1352/** Branch trace interrupt (Intel only). */
1353#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1354/** Branch trace off in privileged code (Intel only). */
1355#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1356/** Branch trace off in user code (Intel only). */
1357#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1358/** Freeze LBR on PMI flag (Intel only). */
1359#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1360/** Freeze PERFMON on PMI flag (Intel only). */
1361#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1362/** Freeze while SMM enabled (Intel only). */
1363#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1364/** Advanced debugging of RTM regions (Intel only). */
1365#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1366/** Debug control MSR valid bits (Intel only). */
1367#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1368 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1369 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1370 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1371 | MSR_IA32_DEBUGCTL_RTM)
1372
1373/** The number (0..3 or 0..15) of the last branch record register on P4 and
1374 * related Xeons. */
1375#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1376/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1377 * @{ */
1378#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1379#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1380#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1381#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1382/** @} */
1383
1384
1385#define IA32_MTRR_PHYSBASE0 0x200
1386#define IA32_MTRR_PHYSMASK0 0x201
1387#define IA32_MTRR_PHYSBASE1 0x202
1388#define IA32_MTRR_PHYSMASK1 0x203
1389#define IA32_MTRR_PHYSBASE2 0x204
1390#define IA32_MTRR_PHYSMASK2 0x205
1391#define IA32_MTRR_PHYSBASE3 0x206
1392#define IA32_MTRR_PHYSMASK3 0x207
1393#define IA32_MTRR_PHYSBASE4 0x208
1394#define IA32_MTRR_PHYSMASK4 0x209
1395#define IA32_MTRR_PHYSBASE5 0x20a
1396#define IA32_MTRR_PHYSMASK5 0x20b
1397#define IA32_MTRR_PHYSBASE6 0x20c
1398#define IA32_MTRR_PHYSMASK6 0x20d
1399#define IA32_MTRR_PHYSBASE7 0x20e
1400#define IA32_MTRR_PHYSMASK7 0x20f
1401#define IA32_MTRR_PHYSBASE8 0x210
1402#define IA32_MTRR_PHYSMASK8 0x211
1403#define IA32_MTRR_PHYSBASE9 0x212
1404#define IA32_MTRR_PHYSMASK9 0x213
1405
1406/** Fixed range MTRRs.
1407 * @{ */
1408#define IA32_MTRR_FIX64K_00000 0x250
1409#define IA32_MTRR_FIX16K_80000 0x258
1410#define IA32_MTRR_FIX16K_A0000 0x259
1411#define IA32_MTRR_FIX4K_C0000 0x268
1412#define IA32_MTRR_FIX4K_C8000 0x269
1413#define IA32_MTRR_FIX4K_D0000 0x26a
1414#define IA32_MTRR_FIX4K_D8000 0x26b
1415#define IA32_MTRR_FIX4K_E0000 0x26c
1416#define IA32_MTRR_FIX4K_E8000 0x26d
1417#define IA32_MTRR_FIX4K_F0000 0x26e
1418#define IA32_MTRR_FIX4K_F8000 0x26f
1419/** @} */
1420
1421/** MTRR Default Range. */
1422#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1423
1424/** Global performance counter control facilities (Intel only). */
1425#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1426#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1427#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1428
1429/** Precise Event Based sampling (Intel only). */
1430#define MSR_IA32_PEBS_ENABLE 0x3F1
1431
1432#define MSR_IA32_MC0_CTL 0x400
1433#define MSR_IA32_MC0_STATUS 0x401
1434
1435/** Basic VMX information. */
1436#define MSR_IA32_VMX_BASIC 0x480
1437/** Allowed settings for pin-based VM execution controls. */
1438#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1439/** Allowed settings for proc-based VM execution controls. */
1440#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1441/** Allowed settings for the VM-exit controls. */
1442#define MSR_IA32_VMX_EXIT_CTLS 0x483
1443/** Allowed settings for the VM-entry controls. */
1444#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1445/** Misc VMX info. */
1446#define MSR_IA32_VMX_MISC 0x485
1447/** Fixed cleared bits in CR0. */
1448#define MSR_IA32_VMX_CR0_FIXED0 0x486
1449/** Fixed set bits in CR0. */
1450#define MSR_IA32_VMX_CR0_FIXED1 0x487
1451/** Fixed cleared bits in CR4. */
1452#define MSR_IA32_VMX_CR4_FIXED0 0x488
1453/** Fixed set bits in CR4. */
1454#define MSR_IA32_VMX_CR4_FIXED1 0x489
1455/** Information for enumerating fields in the VMCS. */
1456#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1457/** Allowed settings for secondary proc-based VM execution controls */
1458#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1459/** EPT capabilities. */
1460#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1461/** Allowed settings of all pin-based VM execution controls. */
1462#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1463/** Allowed settings of all proc-based VM execution controls. */
1464#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1465/** Allowed settings of all VMX exit controls. */
1466#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1467/** Allowed settings of all VMX entry controls. */
1468#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1469/** Allowed settings for the VM-function controls. */
1470#define MSR_IA32_VMX_VMFUNC 0x491
1471
1472/** Intel PT - Enable and control for trace packet generation. */
1473#define MSR_IA32_RTIT_CTL 0x570
1474
1475/** DS Save Area (R/W). */
1476#define MSR_IA32_DS_AREA 0x600
1477/** Running Average Power Limit (RAPL) power units. */
1478#define MSR_RAPL_POWER_UNIT 0x606
1479/** Package C3 Interrupt Response Limit. */
1480#define MSR_PKGC3_IRTL 0x60a
1481/** Package C6/C7S Interrupt Response Limit 1. */
1482#define MSR_PKGC_IRTL1 0x60b
1483/** Package C6/C7S Interrupt Response Limit 2. */
1484#define MSR_PKGC_IRTL2 0x60c
1485/** Package C2 Residency Counter. */
1486#define MSR_PKG_C2_RESIDENCY 0x60d
1487/** PKG RAPL Power Limit Control. */
1488#define MSR_PKG_POWER_LIMIT 0x610
1489/** PKG Energy Status. */
1490#define MSR_PKG_ENERGY_STATUS 0x611
1491/** PKG Perf Status. */
1492#define MSR_PKG_PERF_STATUS 0x613
1493/** PKG RAPL Parameters. */
1494#define MSR_PKG_POWER_INFO 0x614
1495/** DRAM RAPL Power Limit Control. */
1496#define MSR_DRAM_POWER_LIMIT 0x618
1497/** DRAM Energy Status. */
1498#define MSR_DRAM_ENERGY_STATUS 0x619
1499/** DRAM Performance Throttling Status. */
1500#define MSR_DRAM_PERF_STATUS 0x61b
1501/** DRAM RAPL Parameters. */
1502#define MSR_DRAM_POWER_INFO 0x61c
1503/** Package C10 Residency Counter. */
1504#define MSR_PKG_C10_RESIDENCY 0x632
1505/** PP0 Energy Status. */
1506#define MSR_PP0_ENERGY_STATUS 0x639
1507/** PP1 Energy Status. */
1508#define MSR_PP1_ENERGY_STATUS 0x641
1509/** Turbo Activation Ratio. */
1510#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1511/** Core Performance Limit Reasons. */
1512#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1513
1514/** Last branch record from IP MSRs.
1515 * @{ */
1516#define MSR_LASTBRANCH_0_FROM_IP 0x680
1517#define MSR_LASTBRANCH_1_FROM_IP 0x681
1518#define MSR_LASTBRANCH_2_FROM_IP 0x682
1519#define MSR_LASTBRANCH_3_FROM_IP 0x683
1520#define MSR_LASTBRANCH_4_FROM_IP 0x684
1521#define MSR_LASTBRANCH_5_FROM_IP 0x685
1522#define MSR_LASTBRANCH_6_FROM_IP 0x686
1523#define MSR_LASTBRANCH_7_FROM_IP 0x687
1524#define MSR_LASTBRANCH_8_FROM_IP 0x688
1525#define MSR_LASTBRANCH_9_FROM_IP 0x689
1526#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1527#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1528#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1529#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1530#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1531#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1532#define MSR_LASTBRANCH_16_FROM_IP 0x690
1533#define MSR_LASTBRANCH_17_FROM_IP 0x691
1534#define MSR_LASTBRANCH_18_FROM_IP 0x692
1535#define MSR_LASTBRANCH_19_FROM_IP 0x693
1536#define MSR_LASTBRANCH_20_FROM_IP 0x694
1537#define MSR_LASTBRANCH_21_FROM_IP 0x695
1538#define MSR_LASTBRANCH_22_FROM_IP 0x696
1539#define MSR_LASTBRANCH_23_FROM_IP 0x697
1540#define MSR_LASTBRANCH_24_FROM_IP 0x698
1541#define MSR_LASTBRANCH_25_FROM_IP 0x699
1542#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1543#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1544#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1545#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1546#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1547#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1548/** @} */
1549
1550/** Last branch record to IP MSRs.
1551 * @{ */
1552#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1553#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1554#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1555#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1556#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1557#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1558#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1559#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1560#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1561#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1562#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1563#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1564#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1565#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1566#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1567#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1568#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1569#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1570#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1571#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1572#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1573#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1574#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1575#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1576#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1577#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1578#define MSR_LASTBRANCH_26_TO_IP 0x6da
1579#define MSR_LASTBRANCH_27_TO_IP 0x6db
1580#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1581#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1582#define MSR_LASTBRANCH_30_TO_IP 0x6de
1583#define MSR_LASTBRANCH_31_TO_IP 0x6df
1584/** @} */
1585
1586/** X2APIC MSR range start. */
1587#define MSR_IA32_X2APIC_START 0x800
1588/** X2APIC MSR - APIC ID Register. */
1589#define MSR_IA32_X2APIC_ID 0x802
1590/** X2APIC MSR - APIC Version Register. */
1591#define MSR_IA32_X2APIC_VERSION 0x803
1592/** X2APIC MSR - Task Priority Register. */
1593#define MSR_IA32_X2APIC_TPR 0x808
1594/** X2APIC MSR - Processor Priority register. */
1595#define MSR_IA32_X2APIC_PPR 0x80A
1596/** X2APIC MSR - End Of Interrupt register. */
1597#define MSR_IA32_X2APIC_EOI 0x80B
1598/** X2APIC MSR - Logical Destination Register. */
1599#define MSR_IA32_X2APIC_LDR 0x80D
1600/** X2APIC MSR - Spurious Interrupt Vector Register. */
1601#define MSR_IA32_X2APIC_SVR 0x80F
1602/** X2APIC MSR - In-service Register (bits 31:0). */
1603#define MSR_IA32_X2APIC_ISR0 0x810
1604/** X2APIC MSR - In-service Register (bits 63:32). */
1605#define MSR_IA32_X2APIC_ISR1 0x811
1606/** X2APIC MSR - In-service Register (bits 95:64). */
1607#define MSR_IA32_X2APIC_ISR2 0x812
1608/** X2APIC MSR - In-service Register (bits 127:96). */
1609#define MSR_IA32_X2APIC_ISR3 0x813
1610/** X2APIC MSR - In-service Register (bits 159:128). */
1611#define MSR_IA32_X2APIC_ISR4 0x814
1612/** X2APIC MSR - In-service Register (bits 191:160). */
1613#define MSR_IA32_X2APIC_ISR5 0x815
1614/** X2APIC MSR - In-service Register (bits 223:192). */
1615#define MSR_IA32_X2APIC_ISR6 0x816
1616/** X2APIC MSR - In-service Register (bits 255:224). */
1617#define MSR_IA32_X2APIC_ISR7 0x817
1618/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1619#define MSR_IA32_X2APIC_TMR0 0x818
1620/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1621#define MSR_IA32_X2APIC_TMR1 0x819
1622/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1623#define MSR_IA32_X2APIC_TMR2 0x81A
1624/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1625#define MSR_IA32_X2APIC_TMR3 0x81B
1626/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1627#define MSR_IA32_X2APIC_TMR4 0x81C
1628/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1629#define MSR_IA32_X2APIC_TMR5 0x81D
1630/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1631#define MSR_IA32_X2APIC_TMR6 0x81E
1632/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1633#define MSR_IA32_X2APIC_TMR7 0x81F
1634/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1635#define MSR_IA32_X2APIC_IRR0 0x820
1636/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1637#define MSR_IA32_X2APIC_IRR1 0x821
1638/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1639#define MSR_IA32_X2APIC_IRR2 0x822
1640/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1641#define MSR_IA32_X2APIC_IRR3 0x823
1642/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1643#define MSR_IA32_X2APIC_IRR4 0x824
1644/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1645#define MSR_IA32_X2APIC_IRR5 0x825
1646/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1647#define MSR_IA32_X2APIC_IRR6 0x826
1648/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1649#define MSR_IA32_X2APIC_IRR7 0x827
1650/** X2APIC MSR - Error Status Register. */
1651#define MSR_IA32_X2APIC_ESR 0x828
1652/** X2APIC MSR - LVT CMCI Register. */
1653#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1654/** X2APIC MSR - Interrupt Command Register. */
1655#define MSR_IA32_X2APIC_ICR 0x830
1656/** X2APIC MSR - LVT Timer Register. */
1657#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1658/** X2APIC MSR - LVT Thermal Sensor Register. */
1659#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1660/** X2APIC MSR - LVT Performance Counter Register. */
1661#define MSR_IA32_X2APIC_LVT_PERF 0x834
1662/** X2APIC MSR - LVT LINT0 Register. */
1663#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1664/** X2APIC MSR - LVT LINT1 Register. */
1665#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1666/** X2APIC MSR - LVT Error Register . */
1667#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1668/** X2APIC MSR - Timer Initial Count Register. */
1669#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1670/** X2APIC MSR - Timer Current Count Register. */
1671#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1672/** X2APIC MSR - Timer Divide Configuration Register. */
1673#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1674/** X2APIC MSR - Self IPI. */
1675#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1676/** X2APIC MSR range end. */
1677#define MSR_IA32_X2APIC_END 0xBFF
1678/** X2APIC MSR - LVT start range. */
1679#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1680/** X2APIC MSR - LVT end range (inclusive). */
1681#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1682
1683/** K6 EFER - Extended Feature Enable Register. */
1684#define MSR_K6_EFER UINT32_C(0xc0000080)
1685/** @todo document EFER */
1686/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1687#define MSR_K6_EFER_SCE RT_BIT_32(0)
1688/** Bit 8 - LME - Long mode enabled. (R/W) */
1689#define MSR_K6_EFER_LME RT_BIT_32(8)
1690#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1691/** Bit 10 - LMA - Long mode active. (R) */
1692#define MSR_K6_EFER_LMA RT_BIT_32(10)
1693#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1694/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1695#define MSR_K6_EFER_NXE RT_BIT_32(11)
1696#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1697/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1698#define MSR_K6_EFER_SVME RT_BIT_32(12)
1699/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1700#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1701/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1702#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1703/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1704#define MSR_K6_EFER_TCE RT_BIT_32(15)
1705/** K6 STAR - SYSCALL/RET targets. */
1706#define MSR_K6_STAR UINT32_C(0xc0000081)
1707/** Shift value for getting the SYSRET CS and SS value. */
1708#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1709/** Shift value for getting the SYSCALL CS and SS value. */
1710#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1711/** Selector mask for use after shifting. */
1712#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1713/** The mask which give the SYSCALL EIP. */
1714#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1715/** K6 WHCR - Write Handling Control Register. */
1716#define MSR_K6_WHCR UINT32_C(0xc0000082)
1717/** K6 UWCCR - UC/WC Cacheability Control Register. */
1718#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1719/** K6 PSOR - Processor State Observability Register. */
1720#define MSR_K6_PSOR UINT32_C(0xc0000087)
1721/** K6 PFIR - Page Flush/Invalidate Register. */
1722#define MSR_K6_PFIR UINT32_C(0xc0000088)
1723
1724/** Performance counter MSRs. (AMD only) */
1725#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1726#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1727#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1728#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1729#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1730#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1731#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1732#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1733
1734/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1735#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1736/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1737#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1738/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1739#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1740/** K8 FS.base - The 64-bit base FS register. */
1741#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1742/** K8 GS.base - The 64-bit base GS register. */
1743#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1744/** K8 KernelGSbase - Used with SWAPGS. */
1745#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1746/** K8 TSC_AUX - Used with RDTSCP. */
1747#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1748#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1749#define MSR_K8_HWCR UINT32_C(0xc0010015)
1750#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1751#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1752#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1753#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1754#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1755#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1756/** North bridge config? See BIOS & Kernel dev guides for
1757 * details. */
1758#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1759
1760/** Hypertransport interrupt pending register.
1761 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1762#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1763
1764/** SVM Control. */
1765#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1766/** Disables HDT (Hardware Debug Tool) and certain internal debug
1767 * features. */
1768#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1769/** If set, non-intercepted INIT signals are converted to \#SX
1770 * exceptions. */
1771#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1772/** Disables A20 masking. */
1773#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1774/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1775#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1776/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1777 * clear, EFER.SVME can be written normally. */
1778#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1779
1780#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1781#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1782/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1783 * host state during world switch. */
1784#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1785
1786/** @} */
1787
1788
1789/** @name Page Table / Directory / Directory Pointers / L4.
1790 * @{
1791 */
1792
1793/** Page table/directory entry as an unsigned integer. */
1794typedef uint32_t X86PGUINT;
1795/** Pointer to a page table/directory table entry as an unsigned integer. */
1796typedef X86PGUINT *PX86PGUINT;
1797/** Pointer to an const page table/directory table entry as an unsigned integer. */
1798typedef X86PGUINT const *PCX86PGUINT;
1799
1800/** Number of entries in a 32-bit PT/PD. */
1801#define X86_PG_ENTRIES 1024
1802
1803
1804/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1805typedef uint64_t X86PGPAEUINT;
1806/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1807typedef X86PGPAEUINT *PX86PGPAEUINT;
1808/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1809typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1810
1811/** Number of entries in a PAE PT/PD. */
1812#define X86_PG_PAE_ENTRIES 512
1813/** Number of entries in a PAE PDPT. */
1814#define X86_PG_PAE_PDPE_ENTRIES 4
1815
1816/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1817#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1818/** Number of entries in an AMD64 PDPT.
1819 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1820#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1821
1822/** The size of a default page. */
1823#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1824/** The page shift of a default page. */
1825#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1826/** The default page offset mask. */
1827#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1828/** The default page base mask for virtual addresses. */
1829#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1830/** The default page base mask for virtual addresses - 32bit version. */
1831#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1832
1833/** The size of a 4KB page. */
1834#define X86_PAGE_4K_SIZE _4K
1835/** The page shift of a 4KB page. */
1836#define X86_PAGE_4K_SHIFT 12
1837/** The 4KB page offset mask. */
1838#define X86_PAGE_4K_OFFSET_MASK 0xfff
1839/** The 4KB page base mask for virtual addresses. */
1840#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1841/** The 4KB page base mask for virtual addresses - 32bit version. */
1842#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1843
1844/** The size of a 2MB page. */
1845#define X86_PAGE_2M_SIZE _2M
1846/** The page shift of a 2MB page. */
1847#define X86_PAGE_2M_SHIFT 21
1848/** The 2MB page offset mask. */
1849#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1850/** The 2MB page base mask for virtual addresses. */
1851#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1852/** The 2MB page base mask for virtual addresses - 32bit version. */
1853#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1854
1855/** The size of a 4MB page. */
1856#define X86_PAGE_4M_SIZE _4M
1857/** The page shift of a 4MB page. */
1858#define X86_PAGE_4M_SHIFT 22
1859/** The 4MB page offset mask. */
1860#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1861/** The 4MB page base mask for virtual addresses. */
1862#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1863/** The 4MB page base mask for virtual addresses - 32bit version. */
1864#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1865
1866/** The size of a 1GB page. */
1867#define X86_PAGE_1G_SIZE _1G
1868/** The page shift of a 1GB page. */
1869#define X86_PAGE_1G_SHIFT 30
1870/** The 1GB page offset mask. */
1871#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1872/** The 1GB page base mask for virtual addresses. */
1873#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1874
1875/**
1876 * Check if the given address is canonical.
1877 */
1878#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1879
1880
1881/** @name Page Table Entry
1882 * @{
1883 */
1884/** Bit 0 - P - Present bit. */
1885#define X86_PTE_BIT_P 0
1886/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1887#define X86_PTE_BIT_RW 1
1888/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1889#define X86_PTE_BIT_US 2
1890/** Bit 3 - PWT - Page level write thru bit. */
1891#define X86_PTE_BIT_PWT 3
1892/** Bit 4 - PCD - Page level cache disable bit. */
1893#define X86_PTE_BIT_PCD 4
1894/** Bit 5 - A - Access bit. */
1895#define X86_PTE_BIT_A 5
1896/** Bit 6 - D - Dirty bit. */
1897#define X86_PTE_BIT_D 6
1898/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1899#define X86_PTE_BIT_PAT 7
1900/** Bit 8 - G - Global flag. */
1901#define X86_PTE_BIT_G 8
1902/** Bits 63 - NX - PAE/LM - No execution flag. */
1903#define X86_PTE_PAE_BIT_NX 63
1904
1905/** Bit 0 - P - Present bit mask. */
1906#define X86_PTE_P RT_BIT_32(0)
1907/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1908#define X86_PTE_RW RT_BIT_32(1)
1909/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1910#define X86_PTE_US RT_BIT_32(2)
1911/** Bit 3 - PWT - Page level write thru bit mask. */
1912#define X86_PTE_PWT RT_BIT_32(3)
1913/** Bit 4 - PCD - Page level cache disable bit mask. */
1914#define X86_PTE_PCD RT_BIT_32(4)
1915/** Bit 5 - A - Access bit mask. */
1916#define X86_PTE_A RT_BIT_32(5)
1917/** Bit 6 - D - Dirty bit mask. */
1918#define X86_PTE_D RT_BIT_32(6)
1919/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1920#define X86_PTE_PAT RT_BIT_32(7)
1921/** Bit 8 - G - Global bit mask. */
1922#define X86_PTE_G RT_BIT_32(8)
1923
1924/** Bits 9-11 - - Available for use to system software. */
1925#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1926/** Bits 12-31 - - Physical Page number of the next level. */
1927#define X86_PTE_PG_MASK ( 0xfffff000 )
1928
1929/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1930#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1931/** Bits 63 - NX - PAE/LM - No execution flag. */
1932#define X86_PTE_PAE_NX RT_BIT_64(63)
1933/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1934#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1935/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1936#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1937/** No bits - - LM - MBZ bits when NX is active. */
1938#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1939/** Bits 63 - - LM - MBZ bits when no NX. */
1940#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1941
1942/**
1943 * Page table entry.
1944 */
1945typedef struct X86PTEBITS
1946{
1947 /** Flags whether(=1) or not the page is present. */
1948 uint32_t u1Present : 1;
1949 /** Read(=0) / Write(=1) flag. */
1950 uint32_t u1Write : 1;
1951 /** User(=1) / Supervisor (=0) flag. */
1952 uint32_t u1User : 1;
1953 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1954 uint32_t u1WriteThru : 1;
1955 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1956 uint32_t u1CacheDisable : 1;
1957 /** Accessed flag.
1958 * Indicates that the page have been read or written to. */
1959 uint32_t u1Accessed : 1;
1960 /** Dirty flag.
1961 * Indicates that the page has been written to. */
1962 uint32_t u1Dirty : 1;
1963 /** Reserved / If PAT enabled, bit 2 of the index. */
1964 uint32_t u1PAT : 1;
1965 /** Global flag. (Ignored in all but final level.) */
1966 uint32_t u1Global : 1;
1967 /** Available for use to system software. */
1968 uint32_t u3Available : 3;
1969 /** Physical Page number of the next level. */
1970 uint32_t u20PageNo : 20;
1971} X86PTEBITS;
1972#ifndef VBOX_FOR_DTRACE_LIB
1973AssertCompileSize(X86PTEBITS, 4);
1974#endif
1975/** Pointer to a page table entry. */
1976typedef X86PTEBITS *PX86PTEBITS;
1977/** Pointer to a const page table entry. */
1978typedef const X86PTEBITS *PCX86PTEBITS;
1979
1980/**
1981 * Page table entry.
1982 */
1983typedef union X86PTE
1984{
1985 /** Unsigned integer view */
1986 X86PGUINT u;
1987 /** Bit field view. */
1988 X86PTEBITS n;
1989 /** 32-bit view. */
1990 uint32_t au32[1];
1991 /** 16-bit view. */
1992 uint16_t au16[2];
1993 /** 8-bit view. */
1994 uint8_t au8[4];
1995} X86PTE;
1996#ifndef VBOX_FOR_DTRACE_LIB
1997AssertCompileSize(X86PTE, 4);
1998#endif
1999/** Pointer to a page table entry. */
2000typedef X86PTE *PX86PTE;
2001/** Pointer to a const page table entry. */
2002typedef const X86PTE *PCX86PTE;
2003
2004
2005/**
2006 * PAE page table entry.
2007 */
2008typedef struct X86PTEPAEBITS
2009{
2010 /** Flags whether(=1) or not the page is present. */
2011 uint32_t u1Present : 1;
2012 /** Read(=0) / Write(=1) flag. */
2013 uint32_t u1Write : 1;
2014 /** User(=1) / Supervisor(=0) flag. */
2015 uint32_t u1User : 1;
2016 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2017 uint32_t u1WriteThru : 1;
2018 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2019 uint32_t u1CacheDisable : 1;
2020 /** Accessed flag.
2021 * Indicates that the page have been read or written to. */
2022 uint32_t u1Accessed : 1;
2023 /** Dirty flag.
2024 * Indicates that the page has been written to. */
2025 uint32_t u1Dirty : 1;
2026 /** Reserved / If PAT enabled, bit 2 of the index. */
2027 uint32_t u1PAT : 1;
2028 /** Global flag. (Ignored in all but final level.) */
2029 uint32_t u1Global : 1;
2030 /** Available for use to system software. */
2031 uint32_t u3Available : 3;
2032 /** Physical Page number of the next level - Low Part. Don't use this. */
2033 uint32_t u20PageNoLow : 20;
2034 /** Physical Page number of the next level - High Part. Don't use this. */
2035 uint32_t u20PageNoHigh : 20;
2036 /** MBZ bits */
2037 uint32_t u11Reserved : 11;
2038 /** No Execute flag. */
2039 uint32_t u1NoExecute : 1;
2040} X86PTEPAEBITS;
2041#ifndef VBOX_FOR_DTRACE_LIB
2042AssertCompileSize(X86PTEPAEBITS, 8);
2043#endif
2044/** Pointer to a page table entry. */
2045typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2046/** Pointer to a page table entry. */
2047typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2048
2049/**
2050 * PAE Page table entry.
2051 */
2052typedef union X86PTEPAE
2053{
2054 /** Unsigned integer view */
2055 X86PGPAEUINT u;
2056 /** Bit field view. */
2057 X86PTEPAEBITS n;
2058 /** 32-bit view. */
2059 uint32_t au32[2];
2060 /** 16-bit view. */
2061 uint16_t au16[4];
2062 /** 8-bit view. */
2063 uint8_t au8[8];
2064} X86PTEPAE;
2065#ifndef VBOX_FOR_DTRACE_LIB
2066AssertCompileSize(X86PTEPAE, 8);
2067#endif
2068/** Pointer to a PAE page table entry. */
2069typedef X86PTEPAE *PX86PTEPAE;
2070/** Pointer to a const PAE page table entry. */
2071typedef const X86PTEPAE *PCX86PTEPAE;
2072/** @} */
2073
2074/**
2075 * Page table.
2076 */
2077typedef struct X86PT
2078{
2079 /** PTE Array. */
2080 X86PTE a[X86_PG_ENTRIES];
2081} X86PT;
2082#ifndef VBOX_FOR_DTRACE_LIB
2083AssertCompileSize(X86PT, 4096);
2084#endif
2085/** Pointer to a page table. */
2086typedef X86PT *PX86PT;
2087/** Pointer to a const page table. */
2088typedef const X86PT *PCX86PT;
2089
2090/** The page shift to get the PT index. */
2091#define X86_PT_SHIFT 12
2092/** The PT index mask (apply to a shifted page address). */
2093#define X86_PT_MASK 0x3ff
2094
2095
2096/**
2097 * Page directory.
2098 */
2099typedef struct X86PTPAE
2100{
2101 /** PTE Array. */
2102 X86PTEPAE a[X86_PG_PAE_ENTRIES];
2103} X86PTPAE;
2104#ifndef VBOX_FOR_DTRACE_LIB
2105AssertCompileSize(X86PTPAE, 4096);
2106#endif
2107/** Pointer to a page table. */
2108typedef X86PTPAE *PX86PTPAE;
2109/** Pointer to a const page table. */
2110typedef const X86PTPAE *PCX86PTPAE;
2111
2112/** The page shift to get the PA PTE index. */
2113#define X86_PT_PAE_SHIFT 12
2114/** The PAE PT index mask (apply to a shifted page address). */
2115#define X86_PT_PAE_MASK 0x1ff
2116
2117
2118/** @name 4KB Page Directory Entry
2119 * @{
2120 */
2121/** Bit 0 - P - Present bit. */
2122#define X86_PDE_P RT_BIT_32(0)
2123/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2124#define X86_PDE_RW RT_BIT_32(1)
2125/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2126#define X86_PDE_US RT_BIT_32(2)
2127/** Bit 3 - PWT - Page level write thru bit. */
2128#define X86_PDE_PWT RT_BIT_32(3)
2129/** Bit 4 - PCD - Page level cache disable bit. */
2130#define X86_PDE_PCD RT_BIT_32(4)
2131/** Bit 5 - A - Access bit. */
2132#define X86_PDE_A RT_BIT_32(5)
2133/** Bit 7 - PS - Page size attribute.
2134 * Clear mean 4KB pages, set means large pages (2/4MB). */
2135#define X86_PDE_PS RT_BIT_32(7)
2136/** Bits 9-11 - - Available for use to system software. */
2137#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2138/** Bits 12-31 - - Physical Page number of the next level. */
2139#define X86_PDE_PG_MASK ( 0xfffff000 )
2140
2141/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2142#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2143/** Bits 63 - NX - PAE/LM - No execution flag. */
2144#define X86_PDE_PAE_NX RT_BIT_64(63)
2145/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2146#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2147/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2148#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2149/** Bit 7 - - LM - MBZ bits when NX is active. */
2150#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2151/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2152#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2153
2154/**
2155 * Page directory entry.
2156 */
2157typedef struct X86PDEBITS
2158{
2159 /** Flags whether(=1) or not the page is present. */
2160 uint32_t u1Present : 1;
2161 /** Read(=0) / Write(=1) flag. */
2162 uint32_t u1Write : 1;
2163 /** User(=1) / Supervisor (=0) flag. */
2164 uint32_t u1User : 1;
2165 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2166 uint32_t u1WriteThru : 1;
2167 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2168 uint32_t u1CacheDisable : 1;
2169 /** Accessed flag.
2170 * Indicates that the page has been read or written to. */
2171 uint32_t u1Accessed : 1;
2172 /** Reserved / Ignored (dirty bit). */
2173 uint32_t u1Reserved0 : 1;
2174 /** Size bit if PSE is enabled - in any event it's 0. */
2175 uint32_t u1Size : 1;
2176 /** Reserved / Ignored (global bit). */
2177 uint32_t u1Reserved1 : 1;
2178 /** Available for use to system software. */
2179 uint32_t u3Available : 3;
2180 /** Physical Page number of the next level. */
2181 uint32_t u20PageNo : 20;
2182} X86PDEBITS;
2183#ifndef VBOX_FOR_DTRACE_LIB
2184AssertCompileSize(X86PDEBITS, 4);
2185#endif
2186/** Pointer to a page directory entry. */
2187typedef X86PDEBITS *PX86PDEBITS;
2188/** Pointer to a const page directory entry. */
2189typedef const X86PDEBITS *PCX86PDEBITS;
2190
2191
2192/**
2193 * PAE page directory entry.
2194 */
2195typedef struct X86PDEPAEBITS
2196{
2197 /** Flags whether(=1) or not the page is present. */
2198 uint32_t u1Present : 1;
2199 /** Read(=0) / Write(=1) flag. */
2200 uint32_t u1Write : 1;
2201 /** User(=1) / Supervisor (=0) flag. */
2202 uint32_t u1User : 1;
2203 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2204 uint32_t u1WriteThru : 1;
2205 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2206 uint32_t u1CacheDisable : 1;
2207 /** Accessed flag.
2208 * Indicates that the page has been read or written to. */
2209 uint32_t u1Accessed : 1;
2210 /** Reserved / Ignored (dirty bit). */
2211 uint32_t u1Reserved0 : 1;
2212 /** Size bit if PSE is enabled - in any event it's 0. */
2213 uint32_t u1Size : 1;
2214 /** Reserved / Ignored (global bit). / */
2215 uint32_t u1Reserved1 : 1;
2216 /** Available for use to system software. */
2217 uint32_t u3Available : 3;
2218 /** Physical Page number of the next level - Low Part. Don't use! */
2219 uint32_t u20PageNoLow : 20;
2220 /** Physical Page number of the next level - High Part. Don't use! */
2221 uint32_t u20PageNoHigh : 20;
2222 /** MBZ bits */
2223 uint32_t u11Reserved : 11;
2224 /** No Execute flag. */
2225 uint32_t u1NoExecute : 1;
2226} X86PDEPAEBITS;
2227#ifndef VBOX_FOR_DTRACE_LIB
2228AssertCompileSize(X86PDEPAEBITS, 8);
2229#endif
2230/** Pointer to a page directory entry. */
2231typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2232/** Pointer to a const page directory entry. */
2233typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2234
2235/** @} */
2236
2237
2238/** @name 2/4MB Page Directory Entry
2239 * @{
2240 */
2241/** Bit 0 - P - Present bit. */
2242#define X86_PDE4M_P RT_BIT_32(0)
2243/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2244#define X86_PDE4M_RW RT_BIT_32(1)
2245/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2246#define X86_PDE4M_US RT_BIT_32(2)
2247/** Bit 3 - PWT - Page level write thru bit. */
2248#define X86_PDE4M_PWT RT_BIT_32(3)
2249/** Bit 4 - PCD - Page level cache disable bit. */
2250#define X86_PDE4M_PCD RT_BIT_32(4)
2251/** Bit 5 - A - Access bit. */
2252#define X86_PDE4M_A RT_BIT_32(5)
2253/** Bit 6 - D - Dirty bit. */
2254#define X86_PDE4M_D RT_BIT_32(6)
2255/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2256#define X86_PDE4M_PS RT_BIT_32(7)
2257/** Bit 8 - G - Global flag. */
2258#define X86_PDE4M_G RT_BIT_32(8)
2259/** Bits 9-11 - AVL - Available for use to system software. */
2260#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2261/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2262#define X86_PDE4M_PAT RT_BIT_32(12)
2263/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2264#define X86_PDE4M_PAT_SHIFT (12 - 7)
2265/** Bits 22-31 - - Physical Page number. */
2266#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2267/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2268#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2269/** The number of bits to the high part of the page number. */
2270#define X86_PDE4M_PG_HIGH_SHIFT 19
2271/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2272#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2273
2274/** Bits 21-51 - - PAE/LM - Physical Page number.
2275 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2276#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2277/** Bits 63 - NX - PAE/LM - No execution flag. */
2278#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2279/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2280#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2281/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2282#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2283/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2284#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2285/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2286#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2287
2288/**
2289 * 4MB page directory entry.
2290 */
2291typedef struct X86PDE4MBITS
2292{
2293 /** Flags whether(=1) or not the page is present. */
2294 uint32_t u1Present : 1;
2295 /** Read(=0) / Write(=1) flag. */
2296 uint32_t u1Write : 1;
2297 /** User(=1) / Supervisor (=0) flag. */
2298 uint32_t u1User : 1;
2299 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2300 uint32_t u1WriteThru : 1;
2301 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2302 uint32_t u1CacheDisable : 1;
2303 /** Accessed flag.
2304 * Indicates that the page have been read or written to. */
2305 uint32_t u1Accessed : 1;
2306 /** Dirty flag.
2307 * Indicates that the page has been written to. */
2308 uint32_t u1Dirty : 1;
2309 /** Page size flag - always 1 for 4MB entries. */
2310 uint32_t u1Size : 1;
2311 /** Global flag. */
2312 uint32_t u1Global : 1;
2313 /** Available for use to system software. */
2314 uint32_t u3Available : 3;
2315 /** Reserved / If PAT enabled, bit 2 of the index. */
2316 uint32_t u1PAT : 1;
2317 /** Bits 32-39 of the page number on AMD64.
2318 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2319 uint32_t u8PageNoHigh : 8;
2320 /** Reserved. */
2321 uint32_t u1Reserved : 1;
2322 /** Physical Page number of the page. */
2323 uint32_t u10PageNo : 10;
2324} X86PDE4MBITS;
2325#ifndef VBOX_FOR_DTRACE_LIB
2326AssertCompileSize(X86PDE4MBITS, 4);
2327#endif
2328/** Pointer to a page table entry. */
2329typedef X86PDE4MBITS *PX86PDE4MBITS;
2330/** Pointer to a const page table entry. */
2331typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2332
2333
2334/**
2335 * 2MB PAE page directory entry.
2336 */
2337typedef struct X86PDE2MPAEBITS
2338{
2339 /** Flags whether(=1) or not the page is present. */
2340 uint32_t u1Present : 1;
2341 /** Read(=0) / Write(=1) flag. */
2342 uint32_t u1Write : 1;
2343 /** User(=1) / Supervisor(=0) flag. */
2344 uint32_t u1User : 1;
2345 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2346 uint32_t u1WriteThru : 1;
2347 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2348 uint32_t u1CacheDisable : 1;
2349 /** Accessed flag.
2350 * Indicates that the page have been read or written to. */
2351 uint32_t u1Accessed : 1;
2352 /** Dirty flag.
2353 * Indicates that the page has been written to. */
2354 uint32_t u1Dirty : 1;
2355 /** Page size flag - always 1 for 2MB entries. */
2356 uint32_t u1Size : 1;
2357 /** Global flag. */
2358 uint32_t u1Global : 1;
2359 /** Available for use to system software. */
2360 uint32_t u3Available : 3;
2361 /** Reserved / If PAT enabled, bit 2 of the index. */
2362 uint32_t u1PAT : 1;
2363 /** Reserved. */
2364 uint32_t u9Reserved : 9;
2365 /** Physical Page number of the next level - Low part. Don't use! */
2366 uint32_t u10PageNoLow : 10;
2367 /** Physical Page number of the next level - High part. Don't use! */
2368 uint32_t u20PageNoHigh : 20;
2369 /** MBZ bits */
2370 uint32_t u11Reserved : 11;
2371 /** No Execute flag. */
2372 uint32_t u1NoExecute : 1;
2373} X86PDE2MPAEBITS;
2374#ifndef VBOX_FOR_DTRACE_LIB
2375AssertCompileSize(X86PDE2MPAEBITS, 8);
2376#endif
2377/** Pointer to a 2MB PAE page table entry. */
2378typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2379/** Pointer to a 2MB PAE page table entry. */
2380typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2381
2382/** @} */
2383
2384/**
2385 * Page directory entry.
2386 */
2387typedef union X86PDE
2388{
2389 /** Unsigned integer view. */
2390 X86PGUINT u;
2391 /** Normal view. */
2392 X86PDEBITS n;
2393 /** 4MB view (big). */
2394 X86PDE4MBITS b;
2395 /** 8 bit unsigned integer view. */
2396 uint8_t au8[4];
2397 /** 16 bit unsigned integer view. */
2398 uint16_t au16[2];
2399 /** 32 bit unsigned integer view. */
2400 uint32_t au32[1];
2401} X86PDE;
2402#ifndef VBOX_FOR_DTRACE_LIB
2403AssertCompileSize(X86PDE, 4);
2404#endif
2405/** Pointer to a page directory entry. */
2406typedef X86PDE *PX86PDE;
2407/** Pointer to a const page directory entry. */
2408typedef const X86PDE *PCX86PDE;
2409
2410/**
2411 * PAE page directory entry.
2412 */
2413typedef union X86PDEPAE
2414{
2415 /** Unsigned integer view. */
2416 X86PGPAEUINT u;
2417 /** Normal view. */
2418 X86PDEPAEBITS n;
2419 /** 2MB page view (big). */
2420 X86PDE2MPAEBITS b;
2421 /** 8 bit unsigned integer view. */
2422 uint8_t au8[8];
2423 /** 16 bit unsigned integer view. */
2424 uint16_t au16[4];
2425 /** 32 bit unsigned integer view. */
2426 uint32_t au32[2];
2427} X86PDEPAE;
2428#ifndef VBOX_FOR_DTRACE_LIB
2429AssertCompileSize(X86PDEPAE, 8);
2430#endif
2431/** Pointer to a page directory entry. */
2432typedef X86PDEPAE *PX86PDEPAE;
2433/** Pointer to a const page directory entry. */
2434typedef const X86PDEPAE *PCX86PDEPAE;
2435
2436/**
2437 * Page directory.
2438 */
2439typedef struct X86PD
2440{
2441 /** PDE Array. */
2442 X86PDE a[X86_PG_ENTRIES];
2443} X86PD;
2444#ifndef VBOX_FOR_DTRACE_LIB
2445AssertCompileSize(X86PD, 4096);
2446#endif
2447/** Pointer to a page directory. */
2448typedef X86PD *PX86PD;
2449/** Pointer to a const page directory. */
2450typedef const X86PD *PCX86PD;
2451
2452/** The page shift to get the PD index. */
2453#define X86_PD_SHIFT 22
2454/** The PD index mask (apply to a shifted page address). */
2455#define X86_PD_MASK 0x3ff
2456
2457
2458/**
2459 * PAE page directory.
2460 */
2461typedef struct X86PDPAE
2462{
2463 /** PDE Array. */
2464 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2465} X86PDPAE;
2466#ifndef VBOX_FOR_DTRACE_LIB
2467AssertCompileSize(X86PDPAE, 4096);
2468#endif
2469/** Pointer to a PAE page directory. */
2470typedef X86PDPAE *PX86PDPAE;
2471/** Pointer to a const PAE page directory. */
2472typedef const X86PDPAE *PCX86PDPAE;
2473
2474/** The page shift to get the PAE PD index. */
2475#define X86_PD_PAE_SHIFT 21
2476/** The PAE PD index mask (apply to a shifted page address). */
2477#define X86_PD_PAE_MASK 0x1ff
2478
2479
2480/** @name Page Directory Pointer Table Entry (PAE)
2481 * @{
2482 */
2483/** Bit 0 - P - Present bit. */
2484#define X86_PDPE_P RT_BIT_32(0)
2485/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2486#define X86_PDPE_RW RT_BIT_32(1)
2487/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2488#define X86_PDPE_US RT_BIT_32(2)
2489/** Bit 3 - PWT - Page level write thru bit. */
2490#define X86_PDPE_PWT RT_BIT_32(3)
2491/** Bit 4 - PCD - Page level cache disable bit. */
2492#define X86_PDPE_PCD RT_BIT_32(4)
2493/** Bit 5 - A - Access bit. Long Mode only. */
2494#define X86_PDPE_A RT_BIT_32(5)
2495/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2496#define X86_PDPE_LM_PS RT_BIT_32(7)
2497/** Bits 9-11 - - Available for use to system software. */
2498#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2499/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2500#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2501/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2502#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2503/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2504#define X86_PDPE_LM_NX RT_BIT_64(63)
2505/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2506#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2507/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2508#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2509/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2510#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2511/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2512#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2513
2514
2515/**
2516 * Page directory pointer table entry.
2517 */
2518typedef struct X86PDPEBITS
2519{
2520 /** Flags whether(=1) or not the page is present. */
2521 uint32_t u1Present : 1;
2522 /** Chunk of reserved bits. */
2523 uint32_t u2Reserved : 2;
2524 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2525 uint32_t u1WriteThru : 1;
2526 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2527 uint32_t u1CacheDisable : 1;
2528 /** Chunk of reserved bits. */
2529 uint32_t u4Reserved : 4;
2530 /** Available for use to system software. */
2531 uint32_t u3Available : 3;
2532 /** Physical Page number of the next level - Low Part. Don't use! */
2533 uint32_t u20PageNoLow : 20;
2534 /** Physical Page number of the next level - High Part. Don't use! */
2535 uint32_t u20PageNoHigh : 20;
2536 /** MBZ bits */
2537 uint32_t u12Reserved : 12;
2538} X86PDPEBITS;
2539#ifndef VBOX_FOR_DTRACE_LIB
2540AssertCompileSize(X86PDPEBITS, 8);
2541#endif
2542/** Pointer to a page directory pointer table entry. */
2543typedef X86PDPEBITS *PX86PTPEBITS;
2544/** Pointer to a const page directory pointer table entry. */
2545typedef const X86PDPEBITS *PCX86PTPEBITS;
2546
2547/**
2548 * Page directory pointer table entry. AMD64 version
2549 */
2550typedef struct X86PDPEAMD64BITS
2551{
2552 /** Flags whether(=1) or not the page is present. */
2553 uint32_t u1Present : 1;
2554 /** Read(=0) / Write(=1) flag. */
2555 uint32_t u1Write : 1;
2556 /** User(=1) / Supervisor (=0) flag. */
2557 uint32_t u1User : 1;
2558 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2559 uint32_t u1WriteThru : 1;
2560 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2561 uint32_t u1CacheDisable : 1;
2562 /** Accessed flag.
2563 * Indicates that the page have been read or written to. */
2564 uint32_t u1Accessed : 1;
2565 /** Chunk of reserved bits. */
2566 uint32_t u3Reserved : 3;
2567 /** Available for use to system software. */
2568 uint32_t u3Available : 3;
2569 /** Physical Page number of the next level - Low Part. Don't use! */
2570 uint32_t u20PageNoLow : 20;
2571 /** Physical Page number of the next level - High Part. Don't use! */
2572 uint32_t u20PageNoHigh : 20;
2573 /** MBZ bits */
2574 uint32_t u11Reserved : 11;
2575 /** No Execute flag. */
2576 uint32_t u1NoExecute : 1;
2577} X86PDPEAMD64BITS;
2578#ifndef VBOX_FOR_DTRACE_LIB
2579AssertCompileSize(X86PDPEAMD64BITS, 8);
2580#endif
2581/** Pointer to a page directory pointer table entry. */
2582typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2583/** Pointer to a const page directory pointer table entry. */
2584typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2585
2586/**
2587 * Page directory pointer table entry for 1GB page. (AMD64 only)
2588 */
2589typedef struct X86PDPE1GB
2590{
2591 /** 0: Flags whether(=1) or not the page is present. */
2592 uint32_t u1Present : 1;
2593 /** 1: Read(=0) / Write(=1) flag. */
2594 uint32_t u1Write : 1;
2595 /** 2: User(=1) / Supervisor (=0) flag. */
2596 uint32_t u1User : 1;
2597 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2598 uint32_t u1WriteThru : 1;
2599 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2600 uint32_t u1CacheDisable : 1;
2601 /** 5: Accessed flag.
2602 * Indicates that the page have been read or written to. */
2603 uint32_t u1Accessed : 1;
2604 /** 6: Dirty flag for 1GB pages. */
2605 uint32_t u1Dirty : 1;
2606 /** 7: Indicates 1GB page if set. */
2607 uint32_t u1Size : 1;
2608 /** 8: Global 1GB page. */
2609 uint32_t u1Global: 1;
2610 /** 9-11: Available for use to system software. */
2611 uint32_t u3Available : 3;
2612 /** 12: PAT bit for 1GB page. */
2613 uint32_t u1PAT : 1;
2614 /** 13-29: MBZ bits. */
2615 uint32_t u17Reserved : 17;
2616 /** 30-31: Physical page number - Low Part. Don't use! */
2617 uint32_t u2PageNoLow : 2;
2618 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2619 uint32_t u20PageNoHigh : 20;
2620 /** 52-62: MBZ bits */
2621 uint32_t u11Reserved : 11;
2622 /** 63: No Execute flag. */
2623 uint32_t u1NoExecute : 1;
2624} X86PDPE1GB;
2625#ifndef VBOX_FOR_DTRACE_LIB
2626AssertCompileSize(X86PDPE1GB, 8);
2627#endif
2628/** Pointer to a page directory pointer table entry for a 1GB page. */
2629typedef X86PDPE1GB *PX86PDPE1GB;
2630/** Pointer to a const page directory pointer table entry for a 1GB page. */
2631typedef const X86PDPE1GB *PCX86PDPE1GB;
2632
2633/**
2634 * Page directory pointer table entry.
2635 */
2636typedef union X86PDPE
2637{
2638 /** Unsigned integer view. */
2639 X86PGPAEUINT u;
2640 /** Normal view. */
2641 X86PDPEBITS n;
2642 /** AMD64 view. */
2643 X86PDPEAMD64BITS lm;
2644 /** AMD64 big view. */
2645 X86PDPE1GB b;
2646 /** 8 bit unsigned integer view. */
2647 uint8_t au8[8];
2648 /** 16 bit unsigned integer view. */
2649 uint16_t au16[4];
2650 /** 32 bit unsigned integer view. */
2651 uint32_t au32[2];
2652} X86PDPE;
2653#ifndef VBOX_FOR_DTRACE_LIB
2654AssertCompileSize(X86PDPE, 8);
2655#endif
2656/** Pointer to a page directory pointer table entry. */
2657typedef X86PDPE *PX86PDPE;
2658/** Pointer to a const page directory pointer table entry. */
2659typedef const X86PDPE *PCX86PDPE;
2660
2661
2662/**
2663 * Page directory pointer table.
2664 */
2665typedef struct X86PDPT
2666{
2667 /** PDE Array. */
2668 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2669} X86PDPT;
2670#ifndef VBOX_FOR_DTRACE_LIB
2671AssertCompileSize(X86PDPT, 4096);
2672#endif
2673/** Pointer to a page directory pointer table. */
2674typedef X86PDPT *PX86PDPT;
2675/** Pointer to a const page directory pointer table. */
2676typedef const X86PDPT *PCX86PDPT;
2677
2678/** The page shift to get the PDPT index. */
2679#define X86_PDPT_SHIFT 30
2680/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2681#define X86_PDPT_MASK_PAE 0x3
2682/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2683#define X86_PDPT_MASK_AMD64 0x1ff
2684
2685/** @} */
2686
2687
2688/** @name Page Map Level-4 Entry (Long Mode PAE)
2689 * @{
2690 */
2691/** Bit 0 - P - Present bit. */
2692#define X86_PML4E_P RT_BIT_32(0)
2693/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2694#define X86_PML4E_RW RT_BIT_32(1)
2695/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2696#define X86_PML4E_US RT_BIT_32(2)
2697/** Bit 3 - PWT - Page level write thru bit. */
2698#define X86_PML4E_PWT RT_BIT_32(3)
2699/** Bit 4 - PCD - Page level cache disable bit. */
2700#define X86_PML4E_PCD RT_BIT_32(4)
2701/** Bit 5 - A - Access bit. */
2702#define X86_PML4E_A RT_BIT_32(5)
2703/** Bits 9-11 - - Available for use to system software. */
2704#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2705/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2706#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2707/** Bits 8, 7 - - MBZ bits when NX is active. */
2708#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2709/** Bits 63, 7 - - MBZ bits when no NX. */
2710#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2711/** Bits 63 - NX - PAE - No execution flag. */
2712#define X86_PML4E_NX RT_BIT_64(63)
2713
2714/**
2715 * Page Map Level-4 Entry
2716 */
2717typedef struct X86PML4EBITS
2718{
2719 /** Flags whether(=1) or not the page is present. */
2720 uint32_t u1Present : 1;
2721 /** Read(=0) / Write(=1) flag. */
2722 uint32_t u1Write : 1;
2723 /** User(=1) / Supervisor (=0) flag. */
2724 uint32_t u1User : 1;
2725 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2726 uint32_t u1WriteThru : 1;
2727 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2728 uint32_t u1CacheDisable : 1;
2729 /** Accessed flag.
2730 * Indicates that the page have been read or written to. */
2731 uint32_t u1Accessed : 1;
2732 /** Chunk of reserved bits. */
2733 uint32_t u3Reserved : 3;
2734 /** Available for use to system software. */
2735 uint32_t u3Available : 3;
2736 /** Physical Page number of the next level - Low Part. Don't use! */
2737 uint32_t u20PageNoLow : 20;
2738 /** Physical Page number of the next level - High Part. Don't use! */
2739 uint32_t u20PageNoHigh : 20;
2740 /** MBZ bits */
2741 uint32_t u11Reserved : 11;
2742 /** No Execute flag. */
2743 uint32_t u1NoExecute : 1;
2744} X86PML4EBITS;
2745#ifndef VBOX_FOR_DTRACE_LIB
2746AssertCompileSize(X86PML4EBITS, 8);
2747#endif
2748/** Pointer to a page map level-4 entry. */
2749typedef X86PML4EBITS *PX86PML4EBITS;
2750/** Pointer to a const page map level-4 entry. */
2751typedef const X86PML4EBITS *PCX86PML4EBITS;
2752
2753/**
2754 * Page Map Level-4 Entry.
2755 */
2756typedef union X86PML4E
2757{
2758 /** Unsigned integer view. */
2759 X86PGPAEUINT u;
2760 /** Normal view. */
2761 X86PML4EBITS n;
2762 /** 8 bit unsigned integer view. */
2763 uint8_t au8[8];
2764 /** 16 bit unsigned integer view. */
2765 uint16_t au16[4];
2766 /** 32 bit unsigned integer view. */
2767 uint32_t au32[2];
2768} X86PML4E;
2769#ifndef VBOX_FOR_DTRACE_LIB
2770AssertCompileSize(X86PML4E, 8);
2771#endif
2772/** Pointer to a page map level-4 entry. */
2773typedef X86PML4E *PX86PML4E;
2774/** Pointer to a const page map level-4 entry. */
2775typedef const X86PML4E *PCX86PML4E;
2776
2777
2778/**
2779 * Page Map Level-4.
2780 */
2781typedef struct X86PML4
2782{
2783 /** PDE Array. */
2784 X86PML4E a[X86_PG_PAE_ENTRIES];
2785} X86PML4;
2786#ifndef VBOX_FOR_DTRACE_LIB
2787AssertCompileSize(X86PML4, 4096);
2788#endif
2789/** Pointer to a page map level-4. */
2790typedef X86PML4 *PX86PML4;
2791/** Pointer to a const page map level-4. */
2792typedef const X86PML4 *PCX86PML4;
2793
2794/** The page shift to get the PML4 index. */
2795#define X86_PML4_SHIFT 39
2796/** The PML4 index mask (apply to a shifted page address). */
2797#define X86_PML4_MASK 0x1ff
2798
2799/** @} */
2800
2801/** @} */
2802
2803/**
2804 * Intel PCID invalidation types.
2805 */
2806/** Individual address invalidation. */
2807#define X86_INVPCID_TYPE_INDV_ADDR 0
2808/** Single-context invalidation. */
2809#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2810/** All-context including globals invalidation. */
2811#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2812/** All-context excluding globals invalidation. */
2813#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2814/** The maximum valid invalidation type value. */
2815#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2816
2817/**
2818 * 32-bit protected mode FSTENV image.
2819 */
2820typedef struct X86FSTENV32P
2821{
2822 uint16_t FCW;
2823 uint16_t padding1;
2824 uint16_t FSW;
2825 uint16_t padding2;
2826 uint16_t FTW;
2827 uint16_t padding3;
2828 uint32_t FPUIP;
2829 uint16_t FPUCS;
2830 uint16_t FOP;
2831 uint32_t FPUDP;
2832 uint16_t FPUDS;
2833 uint16_t padding4;
2834} X86FSTENV32P;
2835/** Pointer to a 32-bit protected mode FSTENV image. */
2836typedef X86FSTENV32P *PX86FSTENV32P;
2837/** Pointer to a const 32-bit protected mode FSTENV image. */
2838typedef X86FSTENV32P const *PCX86FSTENV32P;
2839
2840
2841/**
2842 * 80-bit MMX/FPU register type.
2843 */
2844typedef struct X86FPUMMX
2845{
2846 uint8_t reg[10];
2847} X86FPUMMX;
2848#ifndef VBOX_FOR_DTRACE_LIB
2849AssertCompileSize(X86FPUMMX, 10);
2850#endif
2851/** Pointer to a 80-bit MMX/FPU register type. */
2852typedef X86FPUMMX *PX86FPUMMX;
2853/** Pointer to a const 80-bit MMX/FPU register type. */
2854typedef const X86FPUMMX *PCX86FPUMMX;
2855
2856/** FPU (x87) register. */
2857typedef union X86FPUREG
2858{
2859 /** MMX view. */
2860 uint64_t mmx;
2861 /** FPU view - todo. */
2862 X86FPUMMX fpu;
2863 /** Extended precision floating point view. */
2864 RTFLOAT80U r80;
2865 /** Extended precision floating point view v2 */
2866 RTFLOAT80U2 r80Ex;
2867 /** 8-bit view. */
2868 uint8_t au8[16];
2869 /** 16-bit view. */
2870 uint16_t au16[8];
2871 /** 32-bit view. */
2872 uint32_t au32[4];
2873 /** 64-bit view. */
2874 uint64_t au64[2];
2875 /** 128-bit view. (yeah, very helpful) */
2876 uint128_t au128[1];
2877} X86FPUREG;
2878#ifndef VBOX_FOR_DTRACE_LIB
2879AssertCompileSize(X86FPUREG, 16);
2880#endif
2881/** Pointer to a FPU register. */
2882typedef X86FPUREG *PX86FPUREG;
2883/** Pointer to a const FPU register. */
2884typedef X86FPUREG const *PCX86FPUREG;
2885
2886/**
2887 * XMM register union.
2888 */
2889typedef union X86XMMREG
2890{
2891 /** XMM Register view. */
2892 uint128_t xmm;
2893 /** 8-bit view. */
2894 uint8_t au8[16];
2895 /** 16-bit view. */
2896 uint16_t au16[8];
2897 /** 32-bit view. */
2898 uint32_t au32[4];
2899 /** 64-bit view. */
2900 uint64_t au64[2];
2901 /** 128-bit view. (yeah, very helpful) */
2902 uint128_t au128[1];
2903#ifndef VBOX_FOR_DTRACE_LIB
2904 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2905 RTUINT128U uXmm;
2906#endif
2907} X86XMMREG;
2908#ifndef VBOX_FOR_DTRACE_LIB
2909AssertCompileSize(X86XMMREG, 16);
2910#endif
2911/** Pointer to an XMM register state. */
2912typedef X86XMMREG *PX86XMMREG;
2913/** Pointer to a const XMM register state. */
2914typedef X86XMMREG const *PCX86XMMREG;
2915
2916/**
2917 * YMM register union.
2918 */
2919typedef union X86YMMREG
2920{
2921 /** 8-bit view. */
2922 uint8_t au8[32];
2923 /** 16-bit view. */
2924 uint16_t au16[16];
2925 /** 32-bit view. */
2926 uint32_t au32[8];
2927 /** 64-bit view. */
2928 uint64_t au64[4];
2929 /** 128-bit view. (yeah, very helpful) */
2930 uint128_t au128[2];
2931 /** XMM sub register view. */
2932 X86XMMREG aXmm[2];
2933} X86YMMREG;
2934#ifndef VBOX_FOR_DTRACE_LIB
2935AssertCompileSize(X86YMMREG, 32);
2936#endif
2937/** Pointer to an YMM register state. */
2938typedef X86YMMREG *PX86YMMREG;
2939/** Pointer to a const YMM register state. */
2940typedef X86YMMREG const *PCX86YMMREG;
2941
2942/**
2943 * ZMM register union.
2944 */
2945typedef union X86ZMMREG
2946{
2947 /** 8-bit view. */
2948 uint8_t au8[64];
2949 /** 16-bit view. */
2950 uint16_t au16[32];
2951 /** 32-bit view. */
2952 uint32_t au32[16];
2953 /** 64-bit view. */
2954 uint64_t au64[8];
2955 /** 128-bit view. (yeah, very helpful) */
2956 uint128_t au128[4];
2957 /** XMM sub register view. */
2958 X86XMMREG aXmm[4];
2959 /** YMM sub register view. */
2960 X86YMMREG aYmm[2];
2961} X86ZMMREG;
2962#ifndef VBOX_FOR_DTRACE_LIB
2963AssertCompileSize(X86ZMMREG, 64);
2964#endif
2965/** Pointer to an ZMM register state. */
2966typedef X86ZMMREG *PX86ZMMREG;
2967/** Pointer to a const ZMM register state. */
2968typedef X86ZMMREG const *PCX86ZMMREG;
2969
2970
2971/**
2972 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2973 * @todo verify this...
2974 */
2975#pragma pack(1)
2976typedef struct X86FPUSTATE
2977{
2978 /** 0x00 - Control word. */
2979 uint16_t FCW;
2980 /** 0x02 - Alignment word */
2981 uint16_t Dummy1;
2982 /** 0x04 - Status word. */
2983 uint16_t FSW;
2984 /** 0x06 - Alignment word */
2985 uint16_t Dummy2;
2986 /** 0x08 - Tag word */
2987 uint16_t FTW;
2988 /** 0x0a - Alignment word */
2989 uint16_t Dummy3;
2990
2991 /** 0x0c - Instruction pointer. */
2992 uint32_t FPUIP;
2993 /** 0x10 - Code selector. */
2994 uint16_t CS;
2995 /** 0x12 - Opcode. */
2996 uint16_t FOP;
2997 /** 0x14 - FOO. */
2998 uint32_t FPUOO;
2999 /** 0x18 - FOS. */
3000 uint32_t FPUOS;
3001 /** 0x1c - FPU register. */
3002 X86FPUREG regs[8];
3003} X86FPUSTATE;
3004#pragma pack()
3005/** Pointer to a FPU state. */
3006typedef X86FPUSTATE *PX86FPUSTATE;
3007/** Pointer to a const FPU state. */
3008typedef const X86FPUSTATE *PCX86FPUSTATE;
3009
3010/**
3011 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3012 */
3013#pragma pack(1)
3014typedef struct X86FXSTATE
3015{
3016 /** 0x00 - Control word. */
3017 uint16_t FCW;
3018 /** 0x02 - Status word. */
3019 uint16_t FSW;
3020 /** 0x04 - Tag word. (The upper byte is always zero.) */
3021 uint16_t FTW;
3022 /** 0x06 - Opcode. */
3023 uint16_t FOP;
3024 /** 0x08 - Instruction pointer. */
3025 uint32_t FPUIP;
3026 /** 0x0c - Code selector. */
3027 uint16_t CS;
3028 uint16_t Rsrvd1;
3029 /** 0x10 - Data pointer. */
3030 uint32_t FPUDP;
3031 /** 0x14 - Data segment */
3032 uint16_t DS;
3033 /** 0x16 */
3034 uint16_t Rsrvd2;
3035 /** 0x18 */
3036 uint32_t MXCSR;
3037 /** 0x1c */
3038 uint32_t MXCSR_MASK;
3039 /** 0x20 - FPU registers. */
3040 X86FPUREG aRegs[8];
3041 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3042 X86XMMREG aXMM[16];
3043 /* - offset 416 - */
3044 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3045 /* - offset 464 - Software usable reserved bits. */
3046 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3047} X86FXSTATE;
3048#pragma pack()
3049/** Pointer to a FPU Extended state. */
3050typedef X86FXSTATE *PX86FXSTATE;
3051/** Pointer to a const FPU Extended state. */
3052typedef const X86FXSTATE *PCX86FXSTATE;
3053
3054/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3055 * magic. Don't forget to update x86.mac if you change this! */
3056#define X86_OFF_FXSTATE_RSVD 0x1d0
3057/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3058 * forget to update x86.mac if you change this!
3059 * @todo r=bird: This has nothing what-so-ever to do here.... */
3060#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3061#ifndef VBOX_FOR_DTRACE_LIB
3062AssertCompileSize(X86FXSTATE, 512);
3063AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3064#endif
3065
3066/** @name FPU status word flags.
3067 * @{ */
3068/** Exception Flag: Invalid operation. */
3069#define X86_FSW_IE RT_BIT_32(0)
3070/** Exception Flag: Denormalized operand. */
3071#define X86_FSW_DE RT_BIT_32(1)
3072/** Exception Flag: Zero divide. */
3073#define X86_FSW_ZE RT_BIT_32(2)
3074/** Exception Flag: Overflow. */
3075#define X86_FSW_OE RT_BIT_32(3)
3076/** Exception Flag: Underflow. */
3077#define X86_FSW_UE RT_BIT_32(4)
3078/** Exception Flag: Precision. */
3079#define X86_FSW_PE RT_BIT_32(5)
3080/** Stack fault. */
3081#define X86_FSW_SF RT_BIT_32(6)
3082/** Error summary status. */
3083#define X86_FSW_ES RT_BIT_32(7)
3084/** Mask of exceptions flags, excluding the summary bit. */
3085#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3086/** Mask of exceptions flags, including the summary bit. */
3087#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3088/** Condition code 0. */
3089#define X86_FSW_C0 RT_BIT_32(8)
3090/** Condition code 1. */
3091#define X86_FSW_C1 RT_BIT_32(9)
3092/** Condition code 2. */
3093#define X86_FSW_C2 RT_BIT_32(10)
3094/** Top of the stack mask. */
3095#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3096/** TOP shift value. */
3097#define X86_FSW_TOP_SHIFT 11
3098/** Mask for getting TOP value after shifting it right. */
3099#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3100/** Get the TOP value. */
3101#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3102/** Condition code 3. */
3103#define X86_FSW_C3 RT_BIT_32(14)
3104/** Mask of exceptions flags, including the summary bit. */
3105#define X86_FSW_C_MASK UINT16_C(0x4700)
3106/** FPU busy. */
3107#define X86_FSW_B RT_BIT_32(15)
3108/** @} */
3109
3110
3111/** @name FPU control word flags.
3112 * @{ */
3113/** Exception Mask: Invalid operation. */
3114#define X86_FCW_IM RT_BIT_32(0)
3115/** Exception Mask: Denormalized operand. */
3116#define X86_FCW_DM RT_BIT_32(1)
3117/** Exception Mask: Zero divide. */
3118#define X86_FCW_ZM RT_BIT_32(2)
3119/** Exception Mask: Overflow. */
3120#define X86_FCW_OM RT_BIT_32(3)
3121/** Exception Mask: Underflow. */
3122#define X86_FCW_UM RT_BIT_32(4)
3123/** Exception Mask: Precision. */
3124#define X86_FCW_PM RT_BIT_32(5)
3125/** Mask all exceptions, the value typically loaded (by for instance fninit).
3126 * @remarks This includes reserved bit 6. */
3127#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3128/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3129#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3130/** Precision control mask. */
3131#define X86_FCW_PC_MASK UINT16_C(0x0300)
3132/** Precision control: 24-bit. */
3133#define X86_FCW_PC_24 UINT16_C(0x0000)
3134/** Precision control: Reserved. */
3135#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3136/** Precision control: 53-bit. */
3137#define X86_FCW_PC_53 UINT16_C(0x0200)
3138/** Precision control: 64-bit. */
3139#define X86_FCW_PC_64 UINT16_C(0x0300)
3140/** Rounding control mask. */
3141#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3142/** Rounding control: To nearest. */
3143#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3144/** Rounding control: Down. */
3145#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3146/** Rounding control: Up. */
3147#define X86_FCW_RC_UP UINT16_C(0x0800)
3148/** Rounding control: Towards zero. */
3149#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3150/** Bits which should be zero, apparently. */
3151#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3152/** @} */
3153
3154/** @name SSE MXCSR
3155 * @{ */
3156/** Exception Flag: Invalid operation. */
3157#define X86_MXCSR_IE RT_BIT_32(0)
3158/** Exception Flag: Denormalized operand. */
3159#define X86_MXCSR_DE RT_BIT_32(1)
3160/** Exception Flag: Zero divide. */
3161#define X86_MXCSR_ZE RT_BIT_32(2)
3162/** Exception Flag: Overflow. */
3163#define X86_MXCSR_OE RT_BIT_32(3)
3164/** Exception Flag: Underflow. */
3165#define X86_MXCSR_UE RT_BIT_32(4)
3166/** Exception Flag: Precision. */
3167#define X86_MXCSR_PE RT_BIT_32(5)
3168
3169/** Denormals are zero. */
3170#define X86_MXCSR_DAZ RT_BIT_32(6)
3171
3172/** Exception Mask: Invalid operation. */
3173#define X86_MXCSR_IM RT_BIT_32(7)
3174/** Exception Mask: Denormalized operand. */
3175#define X86_MXCSR_DM RT_BIT_32(8)
3176/** Exception Mask: Zero divide. */
3177#define X86_MXCSR_ZM RT_BIT_32(9)
3178/** Exception Mask: Overflow. */
3179#define X86_MXCSR_OM RT_BIT_32(10)
3180/** Exception Mask: Underflow. */
3181#define X86_MXCSR_UM RT_BIT_32(11)
3182/** Exception Mask: Precision. */
3183#define X86_MXCSR_PM RT_BIT_32(12)
3184
3185/** Rounding control mask. */
3186#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3187/** Rounding control: To nearest. */
3188#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3189/** Rounding control: Down. */
3190#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3191/** Rounding control: Up. */
3192#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3193/** Rounding control: Towards zero. */
3194#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3195
3196/** Flush-to-zero for masked underflow. */
3197#define X86_MXCSR_FZ RT_BIT_32(15)
3198
3199/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3200#define X86_MXCSR_MM RT_BIT_32(17)
3201/** @} */
3202
3203/**
3204 * XSAVE header.
3205 */
3206typedef struct X86XSAVEHDR
3207{
3208 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3209 uint64_t bmXState;
3210 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3211 uint64_t bmXComp;
3212 /** Reserved for furture extensions, probably MBZ. */
3213 uint64_t au64Reserved[6];
3214} X86XSAVEHDR;
3215#ifndef VBOX_FOR_DTRACE_LIB
3216AssertCompileSize(X86XSAVEHDR, 64);
3217#endif
3218/** Pointer to an XSAVE header. */
3219typedef X86XSAVEHDR *PX86XSAVEHDR;
3220/** Pointer to a const XSAVE header. */
3221typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3222
3223
3224/**
3225 * The high 128-bit YMM register state (XSAVE_C_YMM).
3226 * (The lower 128-bits being in X86FXSTATE.)
3227 */
3228typedef struct X86XSAVEYMMHI
3229{
3230 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3231 X86XMMREG aYmmHi[16];
3232} X86XSAVEYMMHI;
3233#ifndef VBOX_FOR_DTRACE_LIB
3234AssertCompileSize(X86XSAVEYMMHI, 256);
3235#endif
3236/** Pointer to a high 128-bit YMM register state. */
3237typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3238/** Pointer to a const high 128-bit YMM register state. */
3239typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3240
3241/**
3242 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3243 */
3244typedef struct X86XSAVEBNDREGS
3245{
3246 /** Array of registers (BND0...BND3). */
3247 struct
3248 {
3249 /** Lower bound. */
3250 uint64_t uLowerBound;
3251 /** Upper bound. */
3252 uint64_t uUpperBound;
3253 } aRegs[4];
3254} X86XSAVEBNDREGS;
3255#ifndef VBOX_FOR_DTRACE_LIB
3256AssertCompileSize(X86XSAVEBNDREGS, 64);
3257#endif
3258/** Pointer to a MPX bound register state. */
3259typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3260/** Pointer to a const MPX bound register state. */
3261typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3262
3263/**
3264 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3265 */
3266typedef struct X86XSAVEBNDCFG
3267{
3268 uint64_t fConfig;
3269 uint64_t fStatus;
3270} X86XSAVEBNDCFG;
3271#ifndef VBOX_FOR_DTRACE_LIB
3272AssertCompileSize(X86XSAVEBNDCFG, 16);
3273#endif
3274/** Pointer to a MPX bound config and status register state. */
3275typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3276/** Pointer to a const MPX bound config and status register state. */
3277typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3278
3279/**
3280 * AVX-512 opmask state (XSAVE_C_OPMASK).
3281 */
3282typedef struct X86XSAVEOPMASK
3283{
3284 /** The K0..K7 values. */
3285 uint64_t aKRegs[8];
3286} X86XSAVEOPMASK;
3287#ifndef VBOX_FOR_DTRACE_LIB
3288AssertCompileSize(X86XSAVEOPMASK, 64);
3289#endif
3290/** Pointer to a AVX-512 opmask state. */
3291typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3292/** Pointer to a const AVX-512 opmask state. */
3293typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3294
3295/**
3296 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3297 */
3298typedef struct X86XSAVEZMMHI256
3299{
3300 /** Upper 256-bits of ZMM0-15. */
3301 X86YMMREG aHi256Regs[16];
3302} X86XSAVEZMMHI256;
3303#ifndef VBOX_FOR_DTRACE_LIB
3304AssertCompileSize(X86XSAVEZMMHI256, 512);
3305#endif
3306/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3307typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3308/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3309typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3310
3311/**
3312 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3313 */
3314typedef struct X86XSAVEZMM16HI
3315{
3316 /** ZMM16 thru ZMM31. */
3317 X86ZMMREG aRegs[16];
3318} X86XSAVEZMM16HI;
3319#ifndef VBOX_FOR_DTRACE_LIB
3320AssertCompileSize(X86XSAVEZMM16HI, 1024);
3321#endif
3322/** Pointer to a state comprising ZMM16-32. */
3323typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3324/** Pointer to a const state comprising ZMM16-32. */
3325typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3326
3327/**
3328 * AMD Light weight profiling state (XSAVE_C_LWP).
3329 *
3330 * We probably won't play with this as AMD seems to be dropping from their "zen"
3331 * processor micro architecture.
3332 */
3333typedef struct X86XSAVELWP
3334{
3335 /** Details when needed. */
3336 uint64_t auLater[128/8];
3337} X86XSAVELWP;
3338#ifndef VBOX_FOR_DTRACE_LIB
3339AssertCompileSize(X86XSAVELWP, 128);
3340#endif
3341
3342
3343/**
3344 * x86 FPU/SSE/AVX/XXXX state.
3345 *
3346 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3347 * changes to this structure.
3348 */
3349typedef struct X86XSAVEAREA
3350{
3351 /** The x87 and SSE region (or legacy region if you like). */
3352 X86FXSTATE x87;
3353 /** The XSAVE header. */
3354 X86XSAVEHDR Hdr;
3355 /** Beyond the header, there isn't really a fixed layout, but we can
3356 generally assume the YMM (AVX) register extensions are present and
3357 follows immediately. */
3358 union
3359 {
3360 /** The high 128-bit AVX registers for easy access by IEM.
3361 * @note This ASSUMES they will always be here... */
3362 X86XSAVEYMMHI YmmHi;
3363
3364 /** This is a typical layout on intel CPUs (good for debuggers). */
3365 struct
3366 {
3367 X86XSAVEYMMHI YmmHi;
3368 X86XSAVEBNDREGS BndRegs;
3369 X86XSAVEBNDCFG BndCfg;
3370 uint8_t abFudgeToMatchDocs[0xB0];
3371 X86XSAVEOPMASK Opmask;
3372 X86XSAVEZMMHI256 ZmmHi256;
3373 X86XSAVEZMM16HI Zmm16Hi;
3374 } Intel;
3375
3376 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3377 struct
3378 {
3379 X86XSAVEYMMHI YmmHi;
3380 X86XSAVELWP Lwp;
3381 } AmdBd;
3382
3383 /** To enbling static deployments that have a reasonable chance of working for
3384 * the next 3-6 CPU generations without running short on space, we allocate a
3385 * lot of extra space here, making the structure a round 8KB in size. This
3386 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3387 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3388 uint8_t ab[8192 - 512 - 64];
3389 } u;
3390} X86XSAVEAREA;
3391#ifndef VBOX_FOR_DTRACE_LIB
3392AssertCompileSize(X86XSAVEAREA, 8192);
3393AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3394AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3395AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3396AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3397AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3398AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3399AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3400AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3401#endif
3402/** Pointer to a XSAVE area. */
3403typedef X86XSAVEAREA *PX86XSAVEAREA;
3404/** Pointer to a const XSAVE area. */
3405typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3406
3407
3408/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3409 * @{ */
3410/** Bit 0 - x87 - Legacy FPU state (bit number) */
3411#define XSAVE_C_X87_BIT 0
3412/** Bit 0 - x87 - Legacy FPU state. */
3413#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3414/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3415#define XSAVE_C_SSE_BIT 1
3416/** Bit 1 - SSE - 128-bit SSE state. */
3417#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3418/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3419#define XSAVE_C_YMM_BIT 2
3420/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3421#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3422/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3423#define XSAVE_C_BNDREGS_BIT 3
3424/** Bit 3 - BNDREGS - MPX bound register state. */
3425#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3426/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3427#define XSAVE_C_BNDCSR_BIT 4
3428/** Bit 4 - BNDCSR - MPX bound config and status state. */
3429#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3430/** Bit 5 - Opmask - opmask state (bit number). */
3431#define XSAVE_C_OPMASK_BIT 5
3432/** Bit 5 - Opmask - opmask state. */
3433#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3434/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3435#define XSAVE_C_ZMM_HI256_BIT 6
3436/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3437#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3438/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3439#define XSAVE_C_ZMM_16HI_BIT 7
3440/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3441#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3442/** Bit 9 - PKRU - Protection-key state (bit number). */
3443#define XSAVE_C_PKRU_BIT 9
3444/** Bit 9 - PKRU - Protection-key state. */
3445#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3446/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3447#define XSAVE_C_LWP_BIT 62
3448/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3449#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3450/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3451#define XSAVE_C_X_BIT 63
3452/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3453#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3454/** @} */
3455
3456
3457
3458/** @name Selector Descriptor
3459 * @{
3460 */
3461
3462#ifndef VBOX_FOR_DTRACE_LIB
3463/**
3464 * Descriptor attributes (as seen by VT-x).
3465 */
3466typedef struct X86DESCATTRBITS
3467{
3468 /** 00 - Segment Type. */
3469 unsigned u4Type : 4;
3470 /** 04 - Descriptor Type. System(=0) or code/data selector */
3471 unsigned u1DescType : 1;
3472 /** 05 - Descriptor Privilege level. */
3473 unsigned u2Dpl : 2;
3474 /** 07 - Flags selector present(=1) or not. */
3475 unsigned u1Present : 1;
3476 /** 08 - Segment limit 16-19. */
3477 unsigned u4LimitHigh : 4;
3478 /** 0c - Available for system software. */
3479 unsigned u1Available : 1;
3480 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3481 unsigned u1Long : 1;
3482 /** 0e - This flags meaning depends on the segment type. Try make sense out
3483 * of the intel manual yourself. */
3484 unsigned u1DefBig : 1;
3485 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3486 * clear byte. */
3487 unsigned u1Granularity : 1;
3488 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3489 unsigned u1Unusable : 1;
3490} X86DESCATTRBITS;
3491#endif /* !VBOX_FOR_DTRACE_LIB */
3492
3493/** @name X86DESCATTR masks
3494 * @{ */
3495#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3496#define X86DESCATTR_DT UINT32_C(0x00000010)
3497#define X86DESCATTR_DPL UINT32_C(0x00000060)
3498#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3499#define X86DESCATTR_P UINT32_C(0x00000080)
3500#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3501#define X86DESCATTR_AVL UINT32_C(0x00001000)
3502#define X86DESCATTR_L UINT32_C(0x00002000)
3503#define X86DESCATTR_D UINT32_C(0x00004000)
3504#define X86DESCATTR_G UINT32_C(0x00008000)
3505#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3506/** @} */
3507
3508#pragma pack(1)
3509typedef union X86DESCATTR
3510{
3511 /** Unsigned integer view. */
3512 uint32_t u;
3513#ifndef VBOX_FOR_DTRACE_LIB
3514 /** Normal view. */
3515 X86DESCATTRBITS n;
3516#endif
3517} X86DESCATTR;
3518#pragma pack()
3519/** Pointer to descriptor attributes. */
3520typedef X86DESCATTR *PX86DESCATTR;
3521/** Pointer to const descriptor attributes. */
3522typedef const X86DESCATTR *PCX86DESCATTR;
3523
3524#ifndef VBOX_FOR_DTRACE_LIB
3525
3526/**
3527 * Generic descriptor table entry
3528 */
3529#pragma pack(1)
3530typedef struct X86DESCGENERIC
3531{
3532 /** 00 - Limit - Low word. */
3533 unsigned u16LimitLow : 16;
3534 /** 10 - Base address - low word.
3535 * Don't try set this to 24 because MSC is doing stupid things then. */
3536 unsigned u16BaseLow : 16;
3537 /** 20 - Base address - first 8 bits of high word. */
3538 unsigned u8BaseHigh1 : 8;
3539 /** 28 - Segment Type. */
3540 unsigned u4Type : 4;
3541 /** 2c - Descriptor Type. System(=0) or code/data selector */
3542 unsigned u1DescType : 1;
3543 /** 2d - Descriptor Privilege level. */
3544 unsigned u2Dpl : 2;
3545 /** 2f - Flags selector present(=1) or not. */
3546 unsigned u1Present : 1;
3547 /** 30 - Segment limit 16-19. */
3548 unsigned u4LimitHigh : 4;
3549 /** 34 - Available for system software. */
3550 unsigned u1Available : 1;
3551 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3552 unsigned u1Long : 1;
3553 /** 36 - This flags meaning depends on the segment type. Try make sense out
3554 * of the intel manual yourself. */
3555 unsigned u1DefBig : 1;
3556 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3557 * clear byte. */
3558 unsigned u1Granularity : 1;
3559 /** 38 - Base address - highest 8 bits. */
3560 unsigned u8BaseHigh2 : 8;
3561} X86DESCGENERIC;
3562#pragma pack()
3563/** Pointer to a generic descriptor entry. */
3564typedef X86DESCGENERIC *PX86DESCGENERIC;
3565/** Pointer to a const generic descriptor entry. */
3566typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3567
3568/** @name Bit offsets of X86DESCGENERIC members.
3569 * @{*/
3570#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3571#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3572#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3573#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3574#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3575#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3576#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3577#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3578#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3579#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3580#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3581#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3582#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3583/** @} */
3584
3585
3586/** @name LAR mask
3587 * @{ */
3588#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3589#define X86LAR_F_DT UINT16_C( 0x1000)
3590#define X86LAR_F_DPL UINT16_C( 0x6000)
3591#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3592#define X86LAR_F_P UINT16_C( 0x8000)
3593#define X86LAR_F_AVL UINT32_C(0x00100000)
3594#define X86LAR_F_L UINT32_C(0x00200000)
3595#define X86LAR_F_D UINT32_C(0x00400000)
3596#define X86LAR_F_G UINT32_C(0x00800000)
3597/** @} */
3598
3599
3600/**
3601 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3602 */
3603typedef struct X86DESCGATE
3604{
3605 /** 00 - Target code segment offset - Low word.
3606 * Ignored if task-gate. */
3607 unsigned u16OffsetLow : 16;
3608 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3609 * TSS selector if task-gate. */
3610 unsigned u16Sel : 16;
3611 /** 20 - Number of parameters for a call-gate.
3612 * Ignored if interrupt-, trap- or task-gate. */
3613 unsigned u5ParmCount : 5;
3614 /** 25 - Reserved / ignored. */
3615 unsigned u3Reserved : 3;
3616 /** 28 - Segment Type. */
3617 unsigned u4Type : 4;
3618 /** 2c - Descriptor Type (0 = system). */
3619 unsigned u1DescType : 1;
3620 /** 2d - Descriptor Privilege level. */
3621 unsigned u2Dpl : 2;
3622 /** 2f - Flags selector present(=1) or not. */
3623 unsigned u1Present : 1;
3624 /** 30 - Target code segment offset - High word.
3625 * Ignored if task-gate. */
3626 unsigned u16OffsetHigh : 16;
3627} X86DESCGATE;
3628/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3629typedef X86DESCGATE *PX86DESCGATE;
3630/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3631typedef const X86DESCGATE *PCX86DESCGATE;
3632
3633#endif /* VBOX_FOR_DTRACE_LIB */
3634
3635/**
3636 * Descriptor table entry.
3637 */
3638#pragma pack(1)
3639typedef union X86DESC
3640{
3641#ifndef VBOX_FOR_DTRACE_LIB
3642 /** Generic descriptor view. */
3643 X86DESCGENERIC Gen;
3644 /** Gate descriptor view. */
3645 X86DESCGATE Gate;
3646#endif
3647
3648 /** 8 bit unsigned integer view. */
3649 uint8_t au8[8];
3650 /** 16 bit unsigned integer view. */
3651 uint16_t au16[4];
3652 /** 32 bit unsigned integer view. */
3653 uint32_t au32[2];
3654 /** 64 bit unsigned integer view. */
3655 uint64_t au64[1];
3656 /** Unsigned integer view. */
3657 uint64_t u;
3658} X86DESC;
3659#ifndef VBOX_FOR_DTRACE_LIB
3660AssertCompileSize(X86DESC, 8);
3661#endif
3662#pragma pack()
3663/** Pointer to descriptor table entry. */
3664typedef X86DESC *PX86DESC;
3665/** Pointer to const descriptor table entry. */
3666typedef const X86DESC *PCX86DESC;
3667
3668/** @def X86DESC_BASE
3669 * Return the base address of a descriptor.
3670 */
3671#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3672 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3673 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3674 | ( (a_pDesc)->Gen.u16BaseLow ) )
3675
3676/** @def X86DESC_LIMIT
3677 * Return the limit of a descriptor.
3678 */
3679#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3680 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3681 | ( (a_pDesc)->Gen.u16LimitLow ) )
3682
3683/** @def X86DESC_LIMIT_G
3684 * Return the limit of a descriptor with the granularity bit taken into account.
3685 * @returns Selector limit (uint32_t).
3686 * @param a_pDesc Pointer to the descriptor.
3687 */
3688#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3689 ( (a_pDesc)->Gen.u1Granularity \
3690 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3691 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3692 )
3693
3694/** @def X86DESC_GET_HID_ATTR
3695 * Get the descriptor attributes for the hidden register.
3696 */
3697#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3698 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3699
3700#ifndef VBOX_FOR_DTRACE_LIB
3701
3702/**
3703 * 64 bits generic descriptor table entry
3704 * Note: most of these bits have no meaning in long mode.
3705 */
3706#pragma pack(1)
3707typedef struct X86DESC64GENERIC
3708{
3709 /** Limit - Low word - *IGNORED*. */
3710 uint32_t u16LimitLow : 16;
3711 /** Base address - low word. - *IGNORED*
3712 * Don't try set this to 24 because MSC is doing stupid things then. */
3713 uint32_t u16BaseLow : 16;
3714 /** Base address - first 8 bits of high word. - *IGNORED* */
3715 uint32_t u8BaseHigh1 : 8;
3716 /** Segment Type. */
3717 uint32_t u4Type : 4;
3718 /** Descriptor Type. System(=0) or code/data selector */
3719 uint32_t u1DescType : 1;
3720 /** Descriptor Privilege level. */
3721 uint32_t u2Dpl : 2;
3722 /** Flags selector present(=1) or not. */
3723 uint32_t u1Present : 1;
3724 /** Segment limit 16-19. - *IGNORED* */
3725 uint32_t u4LimitHigh : 4;
3726 /** Available for system software. - *IGNORED* */
3727 uint32_t u1Available : 1;
3728 /** Long mode flag. */
3729 uint32_t u1Long : 1;
3730 /** This flags meaning depends on the segment type. Try make sense out
3731 * of the intel manual yourself. */
3732 uint32_t u1DefBig : 1;
3733 /** Granularity of the limit. If set 4KB granularity is used, if
3734 * clear byte. - *IGNORED* */
3735 uint32_t u1Granularity : 1;
3736 /** Base address - highest 8 bits. - *IGNORED* */
3737 uint32_t u8BaseHigh2 : 8;
3738 /** Base address - bits 63-32. */
3739 uint32_t u32BaseHigh3 : 32;
3740 uint32_t u8Reserved : 8;
3741 uint32_t u5Zeros : 5;
3742 uint32_t u19Reserved : 19;
3743} X86DESC64GENERIC;
3744#pragma pack()
3745/** Pointer to a generic descriptor entry. */
3746typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3747/** Pointer to a const generic descriptor entry. */
3748typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3749
3750/**
3751 * System descriptor table entry (64 bits)
3752 *
3753 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3754 */
3755#pragma pack(1)
3756typedef struct X86DESC64SYSTEM
3757{
3758 /** Limit - Low word. */
3759 uint32_t u16LimitLow : 16;
3760 /** Base address - low word.
3761 * Don't try set this to 24 because MSC is doing stupid things then. */
3762 uint32_t u16BaseLow : 16;
3763 /** Base address - first 8 bits of high word. */
3764 uint32_t u8BaseHigh1 : 8;
3765 /** Segment Type. */
3766 uint32_t u4Type : 4;
3767 /** Descriptor Type. System(=0) or code/data selector */
3768 uint32_t u1DescType : 1;
3769 /** Descriptor Privilege level. */
3770 uint32_t u2Dpl : 2;
3771 /** Flags selector present(=1) or not. */
3772 uint32_t u1Present : 1;
3773 /** Segment limit 16-19. */
3774 uint32_t u4LimitHigh : 4;
3775 /** Available for system software. */
3776 uint32_t u1Available : 1;
3777 /** Reserved - 0. */
3778 uint32_t u1Reserved : 1;
3779 /** This flags meaning depends on the segment type. Try make sense out
3780 * of the intel manual yourself. */
3781 uint32_t u1DefBig : 1;
3782 /** Granularity of the limit. If set 4KB granularity is used, if
3783 * clear byte. */
3784 uint32_t u1Granularity : 1;
3785 /** Base address - bits 31-24. */
3786 uint32_t u8BaseHigh2 : 8;
3787 /** Base address - bits 63-32. */
3788 uint32_t u32BaseHigh3 : 32;
3789 uint32_t u8Reserved : 8;
3790 uint32_t u5Zeros : 5;
3791 uint32_t u19Reserved : 19;
3792} X86DESC64SYSTEM;
3793#pragma pack()
3794/** Pointer to a system descriptor entry. */
3795typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3796/** Pointer to a const system descriptor entry. */
3797typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3798
3799/**
3800 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3801 */
3802typedef struct X86DESC64GATE
3803{
3804 /** Target code segment offset - Low word. */
3805 uint32_t u16OffsetLow : 16;
3806 /** Target code segment selector. */
3807 uint32_t u16Sel : 16;
3808 /** Interrupt stack table for interrupt- and trap-gates.
3809 * Ignored by call-gates. */
3810 uint32_t u3IST : 3;
3811 /** Reserved / ignored. */
3812 uint32_t u5Reserved : 5;
3813 /** Segment Type. */
3814 uint32_t u4Type : 4;
3815 /** Descriptor Type (0 = system). */
3816 uint32_t u1DescType : 1;
3817 /** Descriptor Privilege level. */
3818 uint32_t u2Dpl : 2;
3819 /** Flags selector present(=1) or not. */
3820 uint32_t u1Present : 1;
3821 /** Target code segment offset - High word.
3822 * Ignored if task-gate. */
3823 uint32_t u16OffsetHigh : 16;
3824 /** Target code segment offset - Top dword.
3825 * Ignored if task-gate. */
3826 uint32_t u32OffsetTop : 32;
3827 /** Reserved / ignored / must be zero.
3828 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3829 uint32_t u32Reserved : 32;
3830} X86DESC64GATE;
3831AssertCompileSize(X86DESC64GATE, 16);
3832/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3833typedef X86DESC64GATE *PX86DESC64GATE;
3834/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3835typedef const X86DESC64GATE *PCX86DESC64GATE;
3836
3837#endif /* VBOX_FOR_DTRACE_LIB */
3838
3839/**
3840 * Descriptor table entry.
3841 */
3842#pragma pack(1)
3843typedef union X86DESC64
3844{
3845#ifndef VBOX_FOR_DTRACE_LIB
3846 /** Generic descriptor view. */
3847 X86DESC64GENERIC Gen;
3848 /** System descriptor view. */
3849 X86DESC64SYSTEM System;
3850 /** Gate descriptor view. */
3851 X86DESC64GATE Gate;
3852#endif
3853
3854 /** 8 bit unsigned integer view. */
3855 uint8_t au8[16];
3856 /** 16 bit unsigned integer view. */
3857 uint16_t au16[8];
3858 /** 32 bit unsigned integer view. */
3859 uint32_t au32[4];
3860 /** 64 bit unsigned integer view. */
3861 uint64_t au64[2];
3862} X86DESC64;
3863#ifndef VBOX_FOR_DTRACE_LIB
3864AssertCompileSize(X86DESC64, 16);
3865#endif
3866#pragma pack()
3867/** Pointer to descriptor table entry. */
3868typedef X86DESC64 *PX86DESC64;
3869/** Pointer to const descriptor table entry. */
3870typedef const X86DESC64 *PCX86DESC64;
3871
3872/** @def X86DESC64_BASE
3873 * Return the base of a 64-bit descriptor.
3874 */
3875#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3876 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3877 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3878 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3879 | ( (a_pDesc)->Gen.u16BaseLow ) )
3880
3881
3882
3883/** @name Host system descriptor table entry - Use with care!
3884 * @{ */
3885/** Host system descriptor table entry. */
3886#if HC_ARCH_BITS == 64
3887typedef X86DESC64 X86DESCHC;
3888#else
3889typedef X86DESC X86DESCHC;
3890#endif
3891/** Pointer to a host system descriptor table entry. */
3892#if HC_ARCH_BITS == 64
3893typedef PX86DESC64 PX86DESCHC;
3894#else
3895typedef PX86DESC PX86DESCHC;
3896#endif
3897/** Pointer to a const host system descriptor table entry. */
3898#if HC_ARCH_BITS == 64
3899typedef PCX86DESC64 PCX86DESCHC;
3900#else
3901typedef PCX86DESC PCX86DESCHC;
3902#endif
3903/** @} */
3904
3905
3906/** @name Selector Descriptor Types.
3907 * @{
3908 */
3909
3910/** @name Non-System Selector Types.
3911 * @{ */
3912/** Code(=set)/Data(=clear) bit. */
3913#define X86_SEL_TYPE_CODE 8
3914/** Memory(=set)/System(=clear) bit. */
3915#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3916/** Accessed bit. */
3917#define X86_SEL_TYPE_ACCESSED 1
3918/** Expand down bit (for data selectors only). */
3919#define X86_SEL_TYPE_DOWN 4
3920/** Conforming bit (for code selectors only). */
3921#define X86_SEL_TYPE_CONF 4
3922/** Write bit (for data selectors only). */
3923#define X86_SEL_TYPE_WRITE 2
3924/** Read bit (for code selectors only). */
3925#define X86_SEL_TYPE_READ 2
3926/** The bit number of the code segment read bit (relative to u4Type). */
3927#define X86_SEL_TYPE_READ_BIT 1
3928
3929/** Read only selector type. */
3930#define X86_SEL_TYPE_RO 0
3931/** Accessed read only selector type. */
3932#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3933/** Read write selector type. */
3934#define X86_SEL_TYPE_RW 2
3935/** Accessed read write selector type. */
3936#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3937/** Expand down read only selector type. */
3938#define X86_SEL_TYPE_RO_DOWN 4
3939/** Accessed expand down read only selector type. */
3940#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3941/** Expand down read write selector type. */
3942#define X86_SEL_TYPE_RW_DOWN 6
3943/** Accessed expand down read write selector type. */
3944#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3945/** Execute only selector type. */
3946#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3947/** Accessed execute only selector type. */
3948#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3949/** Execute and read selector type. */
3950#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3951/** Accessed execute and read selector type. */
3952#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3953/** Conforming execute only selector type. */
3954#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3955/** Accessed Conforming execute only selector type. */
3956#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3957/** Conforming execute and write selector type. */
3958#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3959/** Accessed Conforming execute and write selector type. */
3960#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3961/** @} */
3962
3963
3964/** @name System Selector Types.
3965 * @{ */
3966/** The TSS busy bit mask. */
3967#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3968
3969/** Undefined system selector type. */
3970#define X86_SEL_TYPE_SYS_UNDEFINED 0
3971/** 286 TSS selector. */
3972#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3973/** LDT selector. */
3974#define X86_SEL_TYPE_SYS_LDT 2
3975/** 286 TSS selector - Busy. */
3976#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3977/** 286 Callgate selector. */
3978#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3979/** Taskgate selector. */
3980#define X86_SEL_TYPE_SYS_TASK_GATE 5
3981/** 286 Interrupt gate selector. */
3982#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3983/** 286 Trapgate selector. */
3984#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3985/** Undefined system selector. */
3986#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3987/** 386 TSS selector. */
3988#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3989/** Undefined system selector. */
3990#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3991/** 386 TSS selector - Busy. */
3992#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3993/** 386 Callgate selector. */
3994#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3995/** Undefined system selector. */
3996#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3997/** 386 Interruptgate selector. */
3998#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3999/** 386 Trapgate selector. */
4000#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4001/** @} */
4002
4003/** @name AMD64 System Selector Types.
4004 * @{ */
4005/** LDT selector. */
4006#define AMD64_SEL_TYPE_SYS_LDT 2
4007/** TSS selector - Busy. */
4008#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4009/** TSS selector - Busy. */
4010#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4011/** Callgate selector. */
4012#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4013/** Interruptgate selector. */
4014#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4015/** Trapgate selector. */
4016#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4017/** @} */
4018
4019/** @} */
4020
4021
4022/** @name Descriptor Table Entry Flag Masks.
4023 * These are for the 2nd 32-bit word of a descriptor.
4024 * @{ */
4025/** Bits 8-11 - TYPE - Descriptor type mask. */
4026#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
4027/** Bit 12 - S - System (=0) or Code/Data (=1). */
4028#define X86_DESC_S RT_BIT_32(12)
4029/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4030#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
4031/** Bit 15 - P - Present. */
4032#define X86_DESC_P RT_BIT_32(15)
4033/** Bit 20 - AVL - Available for system software. */
4034#define X86_DESC_AVL RT_BIT_32(20)
4035/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4036#define X86_DESC_DB RT_BIT_32(22)
4037/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4038 * used, if clear byte. */
4039#define X86_DESC_G RT_BIT_32(23)
4040/** @} */
4041
4042/** @} */
4043
4044
4045/** @name Task Segments.
4046 * @{
4047 */
4048
4049/**
4050 * The minimum TSS descriptor limit for 286 tasks.
4051 */
4052#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4053
4054/**
4055 * The minimum TSS descriptor segment limit for 386 tasks.
4056 */
4057#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4058
4059/**
4060 * 16-bit Task Segment (TSS).
4061 */
4062#pragma pack(1)
4063typedef struct X86TSS16
4064{
4065 /** Back link to previous task. (static) */
4066 RTSEL selPrev;
4067 /** Ring-0 stack pointer. (static) */
4068 uint16_t sp0;
4069 /** Ring-0 stack segment. (static) */
4070 RTSEL ss0;
4071 /** Ring-1 stack pointer. (static) */
4072 uint16_t sp1;
4073 /** Ring-1 stack segment. (static) */
4074 RTSEL ss1;
4075 /** Ring-2 stack pointer. (static) */
4076 uint16_t sp2;
4077 /** Ring-2 stack segment. (static) */
4078 RTSEL ss2;
4079 /** IP before task switch. */
4080 uint16_t ip;
4081 /** FLAGS before task switch. */
4082 uint16_t flags;
4083 /** AX before task switch. */
4084 uint16_t ax;
4085 /** CX before task switch. */
4086 uint16_t cx;
4087 /** DX before task switch. */
4088 uint16_t dx;
4089 /** BX before task switch. */
4090 uint16_t bx;
4091 /** SP before task switch. */
4092 uint16_t sp;
4093 /** BP before task switch. */
4094 uint16_t bp;
4095 /** SI before task switch. */
4096 uint16_t si;
4097 /** DI before task switch. */
4098 uint16_t di;
4099 /** ES before task switch. */
4100 RTSEL es;
4101 /** CS before task switch. */
4102 RTSEL cs;
4103 /** SS before task switch. */
4104 RTSEL ss;
4105 /** DS before task switch. */
4106 RTSEL ds;
4107 /** LDTR before task switch. */
4108 RTSEL selLdt;
4109} X86TSS16;
4110#ifndef VBOX_FOR_DTRACE_LIB
4111AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4112#endif
4113#pragma pack()
4114/** Pointer to a 16-bit task segment. */
4115typedef X86TSS16 *PX86TSS16;
4116/** Pointer to a const 16-bit task segment. */
4117typedef const X86TSS16 *PCX86TSS16;
4118
4119
4120/**
4121 * 32-bit Task Segment (TSS).
4122 */
4123#pragma pack(1)
4124typedef struct X86TSS32
4125{
4126 /** Back link to previous task. (static) */
4127 RTSEL selPrev;
4128 uint16_t padding1;
4129 /** Ring-0 stack pointer. (static) */
4130 uint32_t esp0;
4131 /** Ring-0 stack segment. (static) */
4132 RTSEL ss0;
4133 uint16_t padding_ss0;
4134 /** Ring-1 stack pointer. (static) */
4135 uint32_t esp1;
4136 /** Ring-1 stack segment. (static) */
4137 RTSEL ss1;
4138 uint16_t padding_ss1;
4139 /** Ring-2 stack pointer. (static) */
4140 uint32_t esp2;
4141 /** Ring-2 stack segment. (static) */
4142 RTSEL ss2;
4143 uint16_t padding_ss2;
4144 /** Page directory for the task. (static) */
4145 uint32_t cr3;
4146 /** EIP before task switch. */
4147 uint32_t eip;
4148 /** EFLAGS before task switch. */
4149 uint32_t eflags;
4150 /** EAX before task switch. */
4151 uint32_t eax;
4152 /** ECX before task switch. */
4153 uint32_t ecx;
4154 /** EDX before task switch. */
4155 uint32_t edx;
4156 /** EBX before task switch. */
4157 uint32_t ebx;
4158 /** ESP before task switch. */
4159 uint32_t esp;
4160 /** EBP before task switch. */
4161 uint32_t ebp;
4162 /** ESI before task switch. */
4163 uint32_t esi;
4164 /** EDI before task switch. */
4165 uint32_t edi;
4166 /** ES before task switch. */
4167 RTSEL es;
4168 uint16_t padding_es;
4169 /** CS before task switch. */
4170 RTSEL cs;
4171 uint16_t padding_cs;
4172 /** SS before task switch. */
4173 RTSEL ss;
4174 uint16_t padding_ss;
4175 /** DS before task switch. */
4176 RTSEL ds;
4177 uint16_t padding_ds;
4178 /** FS before task switch. */
4179 RTSEL fs;
4180 uint16_t padding_fs;
4181 /** GS before task switch. */
4182 RTSEL gs;
4183 uint16_t padding_gs;
4184 /** LDTR before task switch. */
4185 RTSEL selLdt;
4186 uint16_t padding_ldt;
4187 /** Debug trap flag */
4188 uint16_t fDebugTrap;
4189 /** Offset relative to the TSS of the start of the I/O Bitmap
4190 * and the end of the interrupt redirection bitmap. */
4191 uint16_t offIoBitmap;
4192} X86TSS32;
4193#pragma pack()
4194/** Pointer to task segment. */
4195typedef X86TSS32 *PX86TSS32;
4196/** Pointer to const task segment. */
4197typedef const X86TSS32 *PCX86TSS32;
4198#ifndef VBOX_FOR_DTRACE_LIB
4199AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4200AssertCompileMemberOffset(X86TSS32, cr3, 28);
4201AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4202#endif
4203
4204/**
4205 * 64-bit Task segment.
4206 */
4207#pragma pack(1)
4208typedef struct X86TSS64
4209{
4210 /** Reserved. */
4211 uint32_t u32Reserved;
4212 /** Ring-0 stack pointer. (static) */
4213 uint64_t rsp0;
4214 /** Ring-1 stack pointer. (static) */
4215 uint64_t rsp1;
4216 /** Ring-2 stack pointer. (static) */
4217 uint64_t rsp2;
4218 /** Reserved. */
4219 uint32_t u32Reserved2[2];
4220 /* IST */
4221 uint64_t ist1;
4222 uint64_t ist2;
4223 uint64_t ist3;
4224 uint64_t ist4;
4225 uint64_t ist5;
4226 uint64_t ist6;
4227 uint64_t ist7;
4228 /* Reserved. */
4229 uint16_t u16Reserved[5];
4230 /** Offset relative to the TSS of the start of the I/O Bitmap
4231 * and the end of the interrupt redirection bitmap. */
4232 uint16_t offIoBitmap;
4233} X86TSS64;
4234#pragma pack()
4235/** Pointer to a 64-bit task segment. */
4236typedef X86TSS64 *PX86TSS64;
4237/** Pointer to a const 64-bit task segment. */
4238typedef const X86TSS64 *PCX86TSS64;
4239#ifndef VBOX_FOR_DTRACE_LIB
4240AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4241#endif
4242
4243/** @} */
4244
4245
4246/** @name Selectors.
4247 * @{
4248 */
4249
4250/**
4251 * The shift used to convert a selector from and to index an index (C).
4252 */
4253#define X86_SEL_SHIFT 3
4254
4255/**
4256 * The mask used to mask off the table indicator and RPL of an selector.
4257 */
4258#define X86_SEL_MASK 0xfff8U
4259
4260/**
4261 * The mask used to mask off the RPL of an selector.
4262 * This is suitable for checking for NULL selectors.
4263 */
4264#define X86_SEL_MASK_OFF_RPL 0xfffcU
4265
4266/**
4267 * The bit indicating that a selector is in the LDT and not in the GDT.
4268 */
4269#define X86_SEL_LDT 0x0004U
4270
4271/**
4272 * The bit mask for getting the RPL of a selector.
4273 */
4274#define X86_SEL_RPL 0x0003U
4275
4276/**
4277 * The mask covering both RPL and LDT.
4278 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4279 * checks.
4280 */
4281#define X86_SEL_RPL_LDT 0x0007U
4282
4283/** @} */
4284
4285
4286/**
4287 * x86 Exceptions/Faults/Traps.
4288 */
4289typedef enum X86XCPT
4290{
4291 /** \#DE - Divide error. */
4292 X86_XCPT_DE = 0x00,
4293 /** \#DB - Debug event (single step, DRx, ..) */
4294 X86_XCPT_DB = 0x01,
4295 /** NMI - Non-Maskable Interrupt */
4296 X86_XCPT_NMI = 0x02,
4297 /** \#BP - Breakpoint (INT3). */
4298 X86_XCPT_BP = 0x03,
4299 /** \#OF - Overflow (INTO). */
4300 X86_XCPT_OF = 0x04,
4301 /** \#BR - Bound range exceeded (BOUND). */
4302 X86_XCPT_BR = 0x05,
4303 /** \#UD - Undefined opcode. */
4304 X86_XCPT_UD = 0x06,
4305 /** \#NM - Device not available (math coprocessor device). */
4306 X86_XCPT_NM = 0x07,
4307 /** \#DF - Double fault. */
4308 X86_XCPT_DF = 0x08,
4309 /** ??? - Coprocessor segment overrun (obsolete). */
4310 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4311 /** \#TS - Taskswitch (TSS). */
4312 X86_XCPT_TS = 0x0a,
4313 /** \#NP - Segment no present. */
4314 X86_XCPT_NP = 0x0b,
4315 /** \#SS - Stack segment fault. */
4316 X86_XCPT_SS = 0x0c,
4317 /** \#GP - General protection fault. */
4318 X86_XCPT_GP = 0x0d,
4319 /** \#PF - Page fault. */
4320 X86_XCPT_PF = 0x0e,
4321 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4322 /** \#MF - Math fault (FPU). */
4323 X86_XCPT_MF = 0x10,
4324 /** \#AC - Alignment check. */
4325 X86_XCPT_AC = 0x11,
4326 /** \#MC - Machine check. */
4327 X86_XCPT_MC = 0x12,
4328 /** \#XF - SIMD Floating-Pointer Exception. */
4329 X86_XCPT_XF = 0x13,
4330 /** \#VE - Virtualization Exception. */
4331 X86_XCPT_VE = 0x14,
4332 /** \#SX - Security Exception. */
4333 X86_XCPT_SX = 0x1e
4334} X86XCPT;
4335/** Pointer to a x86 exception code. */
4336typedef X86XCPT *PX86XCPT;
4337/** Pointer to a const x86 exception code. */
4338typedef const X86XCPT *PCX86XCPT;
4339/** The last valid (currently reserved) exception value. */
4340#define X86_XCPT_LAST 0x1f
4341
4342
4343/** @name Trap Error Codes
4344 * @{
4345 */
4346/** External indicator. */
4347#define X86_TRAP_ERR_EXTERNAL 1
4348/** IDT indicator. */
4349#define X86_TRAP_ERR_IDT 2
4350/** Descriptor table indicator - If set LDT, if clear GDT. */
4351#define X86_TRAP_ERR_TI 4
4352/** Mask for getting the selector. */
4353#define X86_TRAP_ERR_SEL_MASK 0xfff8
4354/** Shift for getting the selector table index (C type index). */
4355#define X86_TRAP_ERR_SEL_SHIFT 3
4356/** @} */
4357
4358
4359/** @name \#PF Trap Error Codes
4360 * @{
4361 */
4362/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4363#define X86_TRAP_PF_P RT_BIT_32(0)
4364/** Bit 1 - R/W - Read (clear) or write (set) access. */
4365#define X86_TRAP_PF_RW RT_BIT_32(1)
4366/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4367#define X86_TRAP_PF_US RT_BIT_32(2)
4368/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4369#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4370/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4371#define X86_TRAP_PF_ID RT_BIT_32(4)
4372/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4373#define X86_TRAP_PF_PK RT_BIT_32(5)
4374/** @} */
4375
4376#pragma pack(1)
4377/**
4378 * 16-bit IDTR.
4379 */
4380typedef struct X86IDTR16
4381{
4382 /** Offset. */
4383 uint16_t offSel;
4384 /** Selector. */
4385 uint16_t uSel;
4386} X86IDTR16, *PX86IDTR16;
4387#pragma pack()
4388
4389#pragma pack(1)
4390/**
4391 * 32-bit IDTR/GDTR.
4392 */
4393typedef struct X86XDTR32
4394{
4395 /** Size of the descriptor table. */
4396 uint16_t cb;
4397 /** Address of the descriptor table. */
4398#ifndef VBOX_FOR_DTRACE_LIB
4399 uint32_t uAddr;
4400#else
4401 uint16_t au16Addr[2];
4402#endif
4403} X86XDTR32, *PX86XDTR32;
4404#pragma pack()
4405
4406#pragma pack(1)
4407/**
4408 * 64-bit IDTR/GDTR.
4409 */
4410typedef struct X86XDTR64
4411{
4412 /** Size of the descriptor table. */
4413 uint16_t cb;
4414 /** Address of the descriptor table. */
4415#ifndef VBOX_FOR_DTRACE_LIB
4416 uint64_t uAddr;
4417#else
4418 uint16_t au16Addr[4];
4419#endif
4420} X86XDTR64, *PX86XDTR64;
4421#pragma pack()
4422
4423
4424/** @name ModR/M
4425 * @{ */
4426#define X86_MODRM_RM_MASK UINT8_C(0x07)
4427#define X86_MODRM_REG_MASK UINT8_C(0x38)
4428#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4429#define X86_MODRM_REG_SHIFT 3
4430#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4431#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4432#define X86_MODRM_MOD_SHIFT 6
4433#ifndef VBOX_FOR_DTRACE_LIB
4434AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4435AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4436AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4437/** @def X86_MODRM_MAKE
4438 * @param a_Mod The mod value (0..3).
4439 * @param a_Reg The register value (0..7).
4440 * @param a_RegMem The register or memory value (0..7). */
4441# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4442#endif
4443/** @} */
4444
4445/** @name SIB
4446 * @{ */
4447#define X86_SIB_BASE_MASK UINT8_C(0x07)
4448#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4449#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4450#define X86_SIB_INDEX_SHIFT 3
4451#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4452#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4453#define X86_SIB_SCALE_SHIFT 6
4454#ifndef VBOX_FOR_DTRACE_LIB
4455AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4456AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4457AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4458#endif
4459/** @} */
4460
4461/** @name General register indexes.
4462 * @{ */
4463#define X86_GREG_xAX 0
4464#define X86_GREG_xCX 1
4465#define X86_GREG_xDX 2
4466#define X86_GREG_xBX 3
4467#define X86_GREG_xSP 4
4468#define X86_GREG_xBP 5
4469#define X86_GREG_xSI 6
4470#define X86_GREG_xDI 7
4471#define X86_GREG_x8 8
4472#define X86_GREG_x9 9
4473#define X86_GREG_x10 10
4474#define X86_GREG_x11 11
4475#define X86_GREG_x12 12
4476#define X86_GREG_x13 13
4477#define X86_GREG_x14 14
4478#define X86_GREG_x15 15
4479/** @} */
4480/** General register count. */
4481#define X86_GREG_COUNT 16
4482
4483/** @name X86_SREG_XXX - Segment register indexes.
4484 * @{ */
4485#define X86_SREG_ES 0
4486#define X86_SREG_CS 1
4487#define X86_SREG_SS 2
4488#define X86_SREG_DS 3
4489#define X86_SREG_FS 4
4490#define X86_SREG_GS 5
4491/** @} */
4492/** Segment register count. */
4493#define X86_SREG_COUNT 6
4494
4495
4496/** @name X86_OP_XXX - Prefixes
4497 * @{ */
4498#define X86_OP_PRF_CS UINT8_C(0x2e)
4499#define X86_OP_PRF_SS UINT8_C(0x36)
4500#define X86_OP_PRF_DS UINT8_C(0x3e)
4501#define X86_OP_PRF_ES UINT8_C(0x26)
4502#define X86_OP_PRF_FS UINT8_C(0x64)
4503#define X86_OP_PRF_GS UINT8_C(0x65)
4504#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4505#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4506#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4507#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4508#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4509#define X86_OP_REX_B UINT8_C(0x41)
4510#define X86_OP_REX_X UINT8_C(0x42)
4511#define X86_OP_REX_R UINT8_C(0x44)
4512#define X86_OP_REX_W UINT8_C(0x48)
4513/** @} */
4514
4515
4516/** @} */
4517
4518#endif /* !IPRT_INCLUDED_x86_h */
4519
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