VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 81602

Last change on this file since 81602 was 81602, checked in by vboxsync, 5 years ago

x86.h: Add MSR_IA32_PMC[4-7].
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2019 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef IPRT_INCLUDED_x86_h
29#define IPRT_INCLUDED_x86_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <iprt/types.h>
36# include <iprt/assert.h>
37#else
38# pragma D depends_on library vbox-types.d
39#endif
40
41/* Workaround for Solaris sys/regset.h defining CS, DS */
42#ifdef RT_OS_SOLARIS
43# undef CS
44# undef DS
45#endif
46
47/** @defgroup grp_rt_x86 x86 Types and Definitions
48 * @ingroup grp_rt
49 * @{
50 */
51
52#ifndef VBOX_FOR_DTRACE_LIB
53/**
54 * EFLAGS Bits.
55 */
56typedef struct X86EFLAGSBITS
57{
58 /** Bit 0 - CF - Carry flag - Status flag. */
59 unsigned u1CF : 1;
60 /** Bit 1 - 1 - Reserved flag. */
61 unsigned u1Reserved0 : 1;
62 /** Bit 2 - PF - Parity flag - Status flag. */
63 unsigned u1PF : 1;
64 /** Bit 3 - 0 - Reserved flag. */
65 unsigned u1Reserved1 : 1;
66 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67 unsigned u1AF : 1;
68 /** Bit 5 - 0 - Reserved flag. */
69 unsigned u1Reserved2 : 1;
70 /** Bit 6 - ZF - Zero flag - Status flag. */
71 unsigned u1ZF : 1;
72 /** Bit 7 - SF - Signed flag - Status flag. */
73 unsigned u1SF : 1;
74 /** Bit 8 - TF - Trap flag - System flag. */
75 unsigned u1TF : 1;
76 /** Bit 9 - IF - Interrupt flag - System flag. */
77 unsigned u1IF : 1;
78 /** Bit 10 - DF - Direction flag - Control flag. */
79 unsigned u1DF : 1;
80 /** Bit 11 - OF - Overflow flag - Status flag. */
81 unsigned u1OF : 1;
82 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83 unsigned u2IOPL : 2;
84 /** Bit 14 - NT - Nested task flag - System flag. */
85 unsigned u1NT : 1;
86 /** Bit 15 - 0 - Reserved flag. */
87 unsigned u1Reserved3 : 1;
88 /** Bit 16 - RF - Resume flag - System flag. */
89 unsigned u1RF : 1;
90 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
91 unsigned u1VM : 1;
92 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93 unsigned u1AC : 1;
94 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95 unsigned u1VIF : 1;
96 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97 unsigned u1VIP : 1;
98 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99 unsigned u1ID : 1;
100 /** Bit 22-31 - 0 - Reserved flag. */
101 unsigned u10Reserved4 : 10;
102} X86EFLAGSBITS;
103/** Pointer to EFLAGS bits. */
104typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105/** Pointer to const EFLAGS bits. */
106typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107#endif /* !VBOX_FOR_DTRACE_LIB */
108
109/**
110 * EFLAGS.
111 */
112typedef union X86EFLAGS
113{
114 /** The plain unsigned view. */
115 uint32_t u;
116#ifndef VBOX_FOR_DTRACE_LIB
117 /** The bitfield view. */
118 X86EFLAGSBITS Bits;
119#endif
120 /** The 8-bit view. */
121 uint8_t au8[4];
122 /** The 16-bit view. */
123 uint16_t au16[2];
124 /** The 32-bit view. */
125 uint32_t au32[1];
126 /** The 32-bit view. */
127 uint32_t u32;
128} X86EFLAGS;
129/** Pointer to EFLAGS. */
130typedef X86EFLAGS *PX86EFLAGS;
131/** Pointer to const EFLAGS. */
132typedef const X86EFLAGS *PCX86EFLAGS;
133
134/**
135 * RFLAGS (32 upper bits are reserved).
136 */
137typedef union X86RFLAGS
138{
139 /** The plain unsigned view. */
140 uint64_t u;
141#ifndef VBOX_FOR_DTRACE_LIB
142 /** The bitfield view. */
143 X86EFLAGSBITS Bits;
144#endif
145 /** The 8-bit view. */
146 uint8_t au8[8];
147 /** The 16-bit view. */
148 uint16_t au16[4];
149 /** The 32-bit view. */
150 uint32_t au32[2];
151 /** The 64-bit view. */
152 uint64_t au64[1];
153 /** The 64-bit view. */
154 uint64_t u64;
155} X86RFLAGS;
156/** Pointer to RFLAGS. */
157typedef X86RFLAGS *PX86RFLAGS;
158/** Pointer to const RFLAGS. */
159typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162/** @name EFLAGS
163 * @{
164 */
165/** Bit 0 - CF - Carry flag - Status flag. */
166#define X86_EFL_CF RT_BIT_32(0)
167#define X86_EFL_CF_BIT 0
168/** Bit 1 - Reserved, reads as 1. */
169#define X86_EFL_1 RT_BIT_32(1)
170/** Bit 2 - PF - Parity flag - Status flag. */
171#define X86_EFL_PF RT_BIT_32(2)
172/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173#define X86_EFL_AF RT_BIT_32(4)
174#define X86_EFL_AF_BIT 4
175/** Bit 6 - ZF - Zero flag - Status flag. */
176#define X86_EFL_ZF RT_BIT_32(6)
177#define X86_EFL_ZF_BIT 6
178/** Bit 7 - SF - Signed flag - Status flag. */
179#define X86_EFL_SF RT_BIT_32(7)
180#define X86_EFL_SF_BIT 7
181/** Bit 8 - TF - Trap flag - System flag. */
182#define X86_EFL_TF RT_BIT_32(8)
183/** Bit 9 - IF - Interrupt flag - System flag. */
184#define X86_EFL_IF RT_BIT_32(9)
185/** Bit 10 - DF - Direction flag - Control flag. */
186#define X86_EFL_DF RT_BIT_32(10)
187/** Bit 11 - OF - Overflow flag - Status flag. */
188#define X86_EFL_OF RT_BIT_32(11)
189#define X86_EFL_OF_BIT 11
190/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
192/** Bit 14 - NT - Nested task flag - System flag. */
193#define X86_EFL_NT RT_BIT_32(14)
194/** Bit 16 - RF - Resume flag - System flag. */
195#define X86_EFL_RF RT_BIT_32(16)
196/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197#define X86_EFL_VM RT_BIT_32(17)
198/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199#define X86_EFL_AC RT_BIT_32(18)
200/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201#define X86_EFL_VIF RT_BIT_32(19)
202/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203#define X86_EFL_VIP RT_BIT_32(20)
204/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205#define X86_EFL_ID RT_BIT_32(21)
206/** All live bits. */
207#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208/** Read as 1 bits. */
209#define X86_EFL_RA1_MASK RT_BIT_32(1)
210/** IOPL shift. */
211#define X86_EFL_IOPL_SHIFT 12
212/** The IOPL level from the flags. */
213#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
217/** Bits restored by popf */
218#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
219 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
220/** The status bits commonly updated by arithmetic instructions. */
221#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
222/** @} */
223
224
225/** CPUID Feature information - ECX.
226 * CPUID query with EAX=1.
227 */
228#ifndef VBOX_FOR_DTRACE_LIB
229typedef struct X86CPUIDFEATECX
230{
231 /** Bit 0 - SSE3 - Supports SSE3 or not. */
232 unsigned u1SSE3 : 1;
233 /** Bit 1 - PCLMULQDQ. */
234 unsigned u1PCLMULQDQ : 1;
235 /** Bit 2 - DS Area 64-bit layout. */
236 unsigned u1DTE64 : 1;
237 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238 unsigned u1Monitor : 1;
239 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240 unsigned u1CPLDS : 1;
241 /** Bit 5 - VMX - Virtual Machine Technology. */
242 unsigned u1VMX : 1;
243 /** Bit 6 - SMX: Safer Mode Extensions. */
244 unsigned u1SMX : 1;
245 /** Bit 7 - EST - Enh. SpeedStep Tech. */
246 unsigned u1EST : 1;
247 /** Bit 8 - TM2 - Terminal Monitor 2. */
248 unsigned u1TM2 : 1;
249 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250 unsigned u1SSSE3 : 1;
251 /** Bit 10 - CNTX-ID - L1 Context ID. */
252 unsigned u1CNTXID : 1;
253 /** Bit 11 - Reserved. */
254 unsigned u1Reserved1 : 1;
255 /** Bit 12 - FMA. */
256 unsigned u1FMA : 1;
257 /** Bit 13 - CX16 - CMPXCHG16B. */
258 unsigned u1CX16 : 1;
259 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260 unsigned u1TPRUpdate : 1;
261 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262 unsigned u1PDCM : 1;
263 /** Bit 16 - Reserved. */
264 unsigned u1Reserved2 : 1;
265 /** Bit 17 - PCID - Process-context identifiers. */
266 unsigned u1PCID : 1;
267 /** Bit 18 - Direct Cache Access. */
268 unsigned u1DCA : 1;
269 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270 unsigned u1SSE4_1 : 1;
271 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272 unsigned u1SSE4_2 : 1;
273 /** Bit 21 - x2APIC. */
274 unsigned u1x2APIC : 1;
275 /** Bit 22 - MOVBE - Supports MOVBE. */
276 unsigned u1MOVBE : 1;
277 /** Bit 23 - POPCNT - Supports POPCNT. */
278 unsigned u1POPCNT : 1;
279 /** Bit 24 - TSC-Deadline. */
280 unsigned u1TSCDEADLINE : 1;
281 /** Bit 25 - AES. */
282 unsigned u1AES : 1;
283 /** Bit 26 - XSAVE - Supports XSAVE. */
284 unsigned u1XSAVE : 1;
285 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286 unsigned u1OSXSAVE : 1;
287 /** Bit 28 - AVX - Supports AVX instruction extensions. */
288 unsigned u1AVX : 1;
289 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290 unsigned u1F16C : 1;
291 /** Bit 30 - RDRAND - Supports RDRAND. */
292 unsigned u1RDRAND : 1;
293 /** Bit 31 - Hypervisor present (we're a guest). */
294 unsigned u1HVP : 1;
295} X86CPUIDFEATECX;
296#else /* VBOX_FOR_DTRACE_LIB */
297typedef uint32_t X86CPUIDFEATECX;
298#endif /* VBOX_FOR_DTRACE_LIB */
299/** Pointer to CPUID Feature Information - ECX. */
300typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301/** Pointer to const CPUID Feature Information - ECX. */
302typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305/** CPUID Feature Information - EDX.
306 * CPUID query with EAX=1.
307 */
308#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309typedef struct X86CPUIDFEATEDX
310{
311 /** Bit 0 - FPU - x87 FPU on Chip. */
312 unsigned u1FPU : 1;
313 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314 unsigned u1VME : 1;
315 /** Bit 2 - DE - Debugging extensions. */
316 unsigned u1DE : 1;
317 /** Bit 3 - PSE - Page Size Extension. */
318 unsigned u1PSE : 1;
319 /** Bit 4 - TSC - Time Stamp Counter. */
320 unsigned u1TSC : 1;
321 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322 unsigned u1MSR : 1;
323 /** Bit 6 - PAE - Physical Address Extension. */
324 unsigned u1PAE : 1;
325 /** Bit 7 - MCE - Machine Check Exception. */
326 unsigned u1MCE : 1;
327 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
328 unsigned u1CX8 : 1;
329 /** Bit 9 - APIC - APIC On-Chip. */
330 unsigned u1APIC : 1;
331 /** Bit 10 - Reserved. */
332 unsigned u1Reserved1 : 1;
333 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334 unsigned u1SEP : 1;
335 /** Bit 12 - MTRR - Memory Type Range Registers. */
336 unsigned u1MTRR : 1;
337 /** Bit 13 - PGE - PTE Global Bit. */
338 unsigned u1PGE : 1;
339 /** Bit 14 - MCA - Machine Check Architecture. */
340 unsigned u1MCA : 1;
341 /** Bit 15 - CMOV - Conditional Move Instructions. */
342 unsigned u1CMOV : 1;
343 /** Bit 16 - PAT - Page Attribute Table. */
344 unsigned u1PAT : 1;
345 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346 unsigned u1PSE36 : 1;
347 /** Bit 18 - PSN - Processor Serial Number. */
348 unsigned u1PSN : 1;
349 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
350 unsigned u1CLFSH : 1;
351 /** Bit 20 - Reserved. */
352 unsigned u1Reserved2 : 1;
353 /** Bit 21 - DS - Debug Store. */
354 unsigned u1DS : 1;
355 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356 unsigned u1ACPI : 1;
357 /** Bit 23 - MMX - Intel MMX 'Technology'. */
358 unsigned u1MMX : 1;
359 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360 unsigned u1FXSR : 1;
361 /** Bit 25 - SSE - SSE Support. */
362 unsigned u1SSE : 1;
363 /** Bit 26 - SSE2 - SSE2 Support. */
364 unsigned u1SSE2 : 1;
365 /** Bit 27 - SS - Self Snoop. */
366 unsigned u1SS : 1;
367 /** Bit 28 - HTT - Hyper-Threading Technology. */
368 unsigned u1HTT : 1;
369 /** Bit 29 - TM - Thermal Monitor. */
370 unsigned u1TM : 1;
371 /** Bit 30 - Reserved - . */
372 unsigned u1Reserved3 : 1;
373 /** Bit 31 - PBE - Pending Break Enabled. */
374 unsigned u1PBE : 1;
375} X86CPUIDFEATEDX;
376#else /* VBOX_FOR_DTRACE_LIB */
377typedef uint32_t X86CPUIDFEATEDX;
378#endif /* VBOX_FOR_DTRACE_LIB */
379/** Pointer to CPUID Feature Information - EDX. */
380typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381/** Pointer to const CPUID Feature Information - EDX. */
382typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384/** @name CPUID Vendor information.
385 * CPUID query with EAX=0.
386 * @{
387 */
388#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399
400#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
401#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
402#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
403/** @} */
404
405
406/** @name CPUID Feature information.
407 * CPUID query with EAX=1.
408 * @{
409 */
410/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
411#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
412/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
413#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
414/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
415#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
416/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
417#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
418/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
419#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
420/** ECX Bit 5 - VMX - Virtual Machine Technology. */
421#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
422/** ECX Bit 6 - SMX - Safer Mode Extensions. */
423#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
424/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
425#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
426/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
427#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
428/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
429#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
430/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
431#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
432/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
433 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
434#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
435/** ECX Bit 12 - FMA. */
436#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
437/** ECX Bit 13 - CX16 - CMPXCHG16B. */
438#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
439/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
440#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
441/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
442#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
443/** ECX Bit 17 - PCID - Process-context identifiers. */
444#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
445/** ECX Bit 18 - DCA - Direct Cache Access. */
446#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
447/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
448#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
449/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
450#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
451/** ECX Bit 21 - x2APIC support. */
452#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
453/** ECX Bit 22 - MOVBE instruction. */
454#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
455/** ECX Bit 23 - POPCNT instruction. */
456#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
457/** ECX Bir 24 - TSC-Deadline. */
458#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
459/** ECX Bit 25 - AES instructions. */
460#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
461/** ECX Bit 26 - XSAVE instruction. */
462#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
463/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
464#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
465/** ECX Bit 28 - AVX. */
466#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
467/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
468#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
469/** ECX Bit 30 - RDRAND instruction. */
470#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
471/** ECX Bit 31 - Hypervisor Present (software only). */
472#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
473
474
475/** Bit 0 - FPU - x87 FPU on Chip. */
476#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
477/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
478#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
479/** Bit 2 - DE - Debugging extensions. */
480#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
481/** Bit 3 - PSE - Page Size Extension. */
482#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
483#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
484/** Bit 4 - TSC - Time Stamp Counter. */
485#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
486/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
487#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
488/** Bit 6 - PAE - Physical Address Extension. */
489#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
490#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
491/** Bit 7 - MCE - Machine Check Exception. */
492#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
493/** Bit 8 - CX8 - CMPXCHG8B instruction. */
494#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
495/** Bit 9 - APIC - APIC On-Chip. */
496#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
497/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
498#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
499/** Bit 12 - MTRR - Memory Type Range Registers. */
500#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
501/** Bit 13 - PGE - PTE Global Bit. */
502#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
503/** Bit 14 - MCA - Machine Check Architecture. */
504#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
505/** Bit 15 - CMOV - Conditional Move Instructions. */
506#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
507/** Bit 16 - PAT - Page Attribute Table. */
508#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
509/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
510#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
511/** Bit 18 - PSN - Processor Serial Number. */
512#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
513/** Bit 19 - CLFSH - CLFLUSH Instruction. */
514#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
515/** Bit 21 - DS - Debug Store. */
516#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
517/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
518#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
519/** Bit 23 - MMX - Intel MMX Technology. */
520#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
521/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
522#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
523/** Bit 25 - SSE - SSE Support. */
524#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
525/** Bit 26 - SSE2 - SSE2 Support. */
526#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
527/** Bit 27 - SS - Self Snoop. */
528#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
529/** Bit 28 - HTT - Hyper-Threading Technology. */
530#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
531/** Bit 29 - TM - Therm. Monitor. */
532#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
533/** Bit 31 - PBE - Pending Break Enabled. */
534#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
535/** @} */
536
537/** @name CPUID mwait/monitor information.
538 * CPUID query with EAX=5.
539 * @{
540 */
541/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
542#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
543/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
544#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
545/** @} */
546
547
548/** @name CPUID Structured Extended Feature information.
549 * CPUID query with EAX=7.
550 * @{
551 */
552/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
553#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
554/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
555#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
556/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
557#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
558/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
559#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
560/** EBX Bit 4 - HLE - Hardware Lock Elision. */
561#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
562/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
563#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
564/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
565#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
566/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
567#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
568/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
569#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
570/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
571#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
572/** EBX Bit 10 - INVPCID - Supports INVPCID. */
573#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
574/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
575#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
576/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
577#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
578/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
579#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
580/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
581#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
582/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
583#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
584/** EBX Bit 16 - AVX512F - Supports AVX512F. */
585#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
586/** EBX Bit 18 - RDSEED - Supports RDSEED. */
587#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
588/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
589#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
590/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
591#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
592/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
593#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
594/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
595#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
596/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
597#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
598/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
599#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
600/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
601#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
602/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
603#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
604
605/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
606#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
607/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
608#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
609/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
610#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
611/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
612#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
613/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
614#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
615/** ECX Bit 22 - RDPID - Support pread process ID. */
616#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
617/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
618#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
619
620/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
621#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
622/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
623 * IBPB command in IA32_PRED_CMD. */
624#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
625/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
626#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
627/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
628#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
629/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
630#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
631
632/** @} */
633
634
635/** @name CPUID Extended Feature information.
636 * CPUID query with EAX=0x80000001.
637 * @{
638 */
639/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
640#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
641
642/** EDX Bit 11 - SYSCALL/SYSRET. */
643#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
644/** EDX Bit 20 - No-Execute/Execute-Disable. */
645#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
646/** EDX Bit 26 - 1 GB large page. */
647#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
648/** EDX Bit 27 - RDTSCP. */
649#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
650/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
651#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
652/** @}*/
653
654/** @name CPUID AMD Feature information.
655 * CPUID query with EAX=0x80000001.
656 * @{
657 */
658/** Bit 0 - FPU - x87 FPU on Chip. */
659#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
660/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
661#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
662/** Bit 2 - DE - Debugging extensions. */
663#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
664/** Bit 3 - PSE - Page Size Extension. */
665#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
666/** Bit 4 - TSC - Time Stamp Counter. */
667#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
668/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
669#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
670/** Bit 6 - PAE - Physical Address Extension. */
671#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
672/** Bit 7 - MCE - Machine Check Exception. */
673#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
674/** Bit 8 - CX8 - CMPXCHG8B instruction. */
675#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
676/** Bit 9 - APIC - APIC On-Chip. */
677#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
678/** Bit 12 - MTRR - Memory Type Range Registers. */
679#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
680/** Bit 13 - PGE - PTE Global Bit. */
681#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
682/** Bit 14 - MCA - Machine Check Architecture. */
683#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
684/** Bit 15 - CMOV - Conditional Move Instructions. */
685#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
686/** Bit 16 - PAT - Page Attribute Table. */
687#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
688/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
689#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
690/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
691#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
692/** Bit 23 - MMX - Intel MMX Technology. */
693#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
694/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
695#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
696/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
697#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
698/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
699#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
700/** Bit 31 - 3DNOW - AMD 3DNow. */
701#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
702
703/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
704#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
705/** Bit 2 - SVM - AMD VM extensions. */
706#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
707/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
708#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
709/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
710#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
711/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
712#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
713/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
714#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
715/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
716#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
717/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
718#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
719/** Bit 9 - OSVW - AMD OS visible workaround. */
720#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
721/** Bit 10 - IBS - Instruct based sampling. */
722#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
723/** Bit 11 - XOP - Extended operation support (see APM6). */
724#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
725/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
726#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
727/** Bit 13 - WDT - AMD Watchdog timer support. */
728#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
729/** Bit 15 - LWP - Lightweight profiling support. */
730#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
731/** Bit 16 - FMA4 - Four operand FMA instruction support. */
732#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
733/** Bit 19 - NodeId - Indicates support for
734 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
735#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
736/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
737#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
738/** Bit 22 - TopologyExtensions - . */
739#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
740/** @} */
741
742
743/** @name CPUID AMD Feature information.
744 * CPUID query with EAX=0x80000007.
745 * @{
746 */
747/** Bit 0 - TS - Temperature Sensor. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
749/** Bit 1 - FID - Frequency ID Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
751/** Bit 2 - VID - Voltage ID Control. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
753/** Bit 3 - TTP - THERMTRIP. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
755/** Bit 4 - TM - Hardware Thermal Control. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
757/** Bit 5 - STC - Software Thermal Control. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
759/** Bit 6 - MC - 100 Mhz Multiplier Control. */
760#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
761/** Bit 7 - HWPSTATE - Hardware P-State Control. */
762#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
763/** Bit 8 - TSCINVAR - TSC Invariant. */
764#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
765/** Bit 9 - CPB - TSC Invariant. */
766#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
767/** Bit 10 - EffFreqRO - MPERF/APERF. */
768#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
769/** Bit 11 - PFI - Processor feedback interface (see EAX). */
770#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
771/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
772#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
773/** @} */
774
775
776/** @name CPUID AMD extended feature extensions ID (EBX).
777 * CPUID query with EAX=0x80000008.
778 * @{
779 */
780/** Bit 0 - CLZERO - Clear zero instruction. */
781#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
782/** Bit 1 - IRPerf - Instructions retired count support. */
783#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
784/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
785#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
786/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
787#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
788/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
789#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
790/* AMD pipeline length: 9 feature bits ;-) */
791/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
792#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
793/** @} */
794
795
796/** @name CPUID AMD SVM Feature information.
797 * CPUID query with EAX=0x8000000a.
798 * @{
799 */
800/** Bit 0 - NP - Nested Paging supported. */
801#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
802/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
803#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
804/** Bit 2 - SVML - SVM locking bit supported. */
805#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
806/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
807#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
808/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
809#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
810/** Bit 5 - VmcbClean - Support VMCB clean bits. */
811#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
812/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
813 * VMCB.TLB_Control is supported. */
814#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
815/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
816#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
817/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
818#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
819/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
820 * intercept filter cycle count threshold. */
821#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
822/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
823#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
824/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
825#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
826/** Bit 16 - VGIF - Supports virtualized GIF. */
827#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
828/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
829#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
830
831/** @} */
832
833
834/** @name CR0
835 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
836 * reserved flags.
837 * @{ */
838/** Bit 0 - PE - Protection Enabled */
839#define X86_CR0_PE RT_BIT_32(0)
840#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
841/** Bit 1 - MP - Monitor Coprocessor */
842#define X86_CR0_MP RT_BIT_32(1)
843#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
844/** Bit 2 - EM - Emulation. */
845#define X86_CR0_EM RT_BIT_32(2)
846#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
847/** Bit 3 - TS - Task Switch. */
848#define X86_CR0_TS RT_BIT_32(3)
849#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
850/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
851#define X86_CR0_ET RT_BIT_32(4)
852#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
853/** Bit 5 - NE - Numeric error (486+). */
854#define X86_CR0_NE RT_BIT_32(5)
855#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
856/** Bit 16 - WP - Write Protect (486+). */
857#define X86_CR0_WP RT_BIT_32(16)
858#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
859/** Bit 18 - AM - Alignment Mask (486+). */
860#define X86_CR0_AM RT_BIT_32(18)
861#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
862/** Bit 29 - NW - Not Write-though (486+). */
863#define X86_CR0_NW RT_BIT_32(29)
864#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
865/** Bit 30 - WP - Cache Disable (486+). */
866#define X86_CR0_CD RT_BIT_32(30)
867#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
868/** Bit 31 - PG - Paging. */
869#define X86_CR0_PG RT_BIT_32(31)
870#define X86_CR0_PAGING RT_BIT_32(31)
871#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
872/** @} */
873
874
875/** @name CR3
876 * @{ */
877/** Bit 3 - PWT - Page-level Writes Transparent. */
878#define X86_CR3_PWT RT_BIT_32(3)
879/** Bit 4 - PCD - Page-level Cache Disable. */
880#define X86_CR3_PCD RT_BIT_32(4)
881/** Bits 12-31 - - Page directory page number. */
882#define X86_CR3_PAGE_MASK (0xfffff000)
883/** Bits 5-31 - - PAE Page directory page number. */
884#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
885/** Bits 12-51 - - AMD64 Page directory page number. */
886#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
887/** @} */
888
889
890/** @name CR4
891 * @{ */
892/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
893#define X86_CR4_VME RT_BIT_32(0)
894/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
895#define X86_CR4_PVI RT_BIT_32(1)
896/** Bit 2 - TSD - Time Stamp Disable. */
897#define X86_CR4_TSD RT_BIT_32(2)
898/** Bit 3 - DE - Debugging Extensions. */
899#define X86_CR4_DE RT_BIT_32(3)
900/** Bit 4 - PSE - Page Size Extension. */
901#define X86_CR4_PSE RT_BIT_32(4)
902/** Bit 5 - PAE - Physical Address Extension. */
903#define X86_CR4_PAE RT_BIT_32(5)
904/** Bit 6 - MCE - Machine-Check Enable. */
905#define X86_CR4_MCE RT_BIT_32(6)
906/** Bit 7 - PGE - Page Global Enable. */
907#define X86_CR4_PGE RT_BIT_32(7)
908/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
909#define X86_CR4_PCE RT_BIT_32(8)
910/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
911#define X86_CR4_OSFXSR RT_BIT_32(9)
912/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
913#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
914/** Bit 13 - VMXE - VMX mode is enabled. */
915#define X86_CR4_VMXE RT_BIT_32(13)
916/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
917#define X86_CR4_SMXE RT_BIT_32(14)
918/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
919#define X86_CR4_FSGSBASE RT_BIT_32(16)
920/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
921#define X86_CR4_PCIDE RT_BIT_32(17)
922/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
923 * extended states. */
924#define X86_CR4_OSXSAVE RT_BIT_32(18)
925/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
926#define X86_CR4_SMEP RT_BIT_32(20)
927/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
928#define X86_CR4_SMAP RT_BIT_32(21)
929/** Bit 22 - PKE - Protection Key Enable. */
930#define X86_CR4_PKE RT_BIT_32(22)
931/** @} */
932
933
934/** @name DR6
935 * @{ */
936/** Bit 0 - B0 - Breakpoint 0 condition detected. */
937#define X86_DR6_B0 RT_BIT_32(0)
938/** Bit 1 - B1 - Breakpoint 1 condition detected. */
939#define X86_DR6_B1 RT_BIT_32(1)
940/** Bit 2 - B2 - Breakpoint 2 condition detected. */
941#define X86_DR6_B2 RT_BIT_32(2)
942/** Bit 3 - B3 - Breakpoint 3 condition detected. */
943#define X86_DR6_B3 RT_BIT_32(3)
944/** Mask of all the Bx bits. */
945#define X86_DR6_B_MASK UINT64_C(0x0000000f)
946/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
947#define X86_DR6_BD RT_BIT_32(13)
948/** Bit 14 - BS - Single step */
949#define X86_DR6_BS RT_BIT_32(14)
950/** Bit 15 - BT - Task switch. (TSS T bit.) */
951#define X86_DR6_BT RT_BIT_32(15)
952/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
953#define X86_DR6_RTM RT_BIT_32(16)
954/** Value of DR6 after powerup/reset. */
955#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
956/** Bits which must be 1s in DR6. */
957#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
958/** Bits which must be 1s in DR6, when RTM is supported. */
959#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
960/** Bits which must be 0s in DR6. */
961#define X86_DR6_RAZ_MASK RT_BIT_64(12)
962/** Bits which must be 0s on writes to DR6. */
963#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
964/** @} */
965
966/** Get the DR6.Bx bit for a the given breakpoint. */
967#define X86_DR6_B(iBp) RT_BIT_64(iBp)
968
969
970/** @name DR7
971 * @{ */
972/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
973#define X86_DR7_L0 RT_BIT_32(0)
974/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
975#define X86_DR7_G0 RT_BIT_32(1)
976/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
977#define X86_DR7_L1 RT_BIT_32(2)
978/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
979#define X86_DR7_G1 RT_BIT_32(3)
980/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
981#define X86_DR7_L2 RT_BIT_32(4)
982/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
983#define X86_DR7_G2 RT_BIT_32(5)
984/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
985#define X86_DR7_L3 RT_BIT_32(6)
986/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
987#define X86_DR7_G3 RT_BIT_32(7)
988/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
989#define X86_DR7_LE RT_BIT_32(8)
990/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
991#define X86_DR7_GE RT_BIT_32(9)
992
993/** L0, L1, L2, and L3. */
994#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
995/** L0, L1, L2, and L3. */
996#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
997
998/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
999 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1000#define X86_DR7_RTM RT_BIT_32(11)
1001/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1002 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1003 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1004 * instruction is executed.
1005 * @see http://www.rcollins.org/secrets/DR7.html */
1006#define X86_DR7_ICE_IR RT_BIT_32(12)
1007/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1008 * any DR register is accessed. */
1009#define X86_DR7_GD RT_BIT_32(13)
1010/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1011 * Pentium. */
1012#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1013/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1014#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1015/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1016#define X86_DR7_RW0_MASK (3 << 16)
1017/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1018#define X86_DR7_LEN0_MASK (3 << 18)
1019/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1020#define X86_DR7_RW1_MASK (3 << 20)
1021/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1022#define X86_DR7_LEN1_MASK (3 << 22)
1023/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1024#define X86_DR7_RW2_MASK (3 << 24)
1025/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1026#define X86_DR7_LEN2_MASK (3 << 26)
1027/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1028#define X86_DR7_RW3_MASK (3 << 28)
1029/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1030#define X86_DR7_LEN3_MASK (3 << 30)
1031
1032/** Bits which reads as 1s. */
1033#define X86_DR7_RA1_MASK RT_BIT_32(10)
1034/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1035#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1036/** Bits which must be 0s when writing to DR7. */
1037#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1038
1039/** Calcs the L bit of Nth breakpoint.
1040 * @param iBp The breakpoint number [0..3].
1041 */
1042#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1043
1044/** Calcs the G bit of Nth breakpoint.
1045 * @param iBp The breakpoint number [0..3].
1046 */
1047#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1048
1049/** Calcs the L and G bits of Nth breakpoint.
1050 * @param iBp The breakpoint number [0..3].
1051 */
1052#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1053
1054/** @name Read/Write values.
1055 * @{ */
1056/** Break on instruction fetch only. */
1057#define X86_DR7_RW_EO UINT32_C(0)
1058/** Break on write only. */
1059#define X86_DR7_RW_WO UINT32_C(1)
1060/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1061#define X86_DR7_RW_IO UINT32_C(2)
1062/** Break on read or write (but not instruction fetches). */
1063#define X86_DR7_RW_RW UINT32_C(3)
1064/** @} */
1065
1066/** Shifts a X86_DR7_RW_* value to its right place.
1067 * @param iBp The breakpoint number [0..3].
1068 * @param fRw One of the X86_DR7_RW_* value.
1069 */
1070#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1071
1072/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1073 * one of the X86_DR7_RW_XXX constants).
1074 *
1075 * @returns X86_DR7_RW_XXX
1076 * @param uDR7 DR7 value
1077 * @param iBp The breakpoint number [0..3].
1078 */
1079#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1080
1081/** R/W0, R/W1, R/W2, and R/W3. */
1082#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1083
1084#ifndef VBOX_FOR_DTRACE_LIB
1085/** Checks if there are any I/O breakpoint types configured in the RW
1086 * registers. Does NOT check if these are enabled, sorry. */
1087# define X86_DR7_ANY_RW_IO(uDR7) \
1088 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1089 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1090AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1091AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1092AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1093AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1094AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1095AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1096AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1097AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1098AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1099#endif /* !VBOX_FOR_DTRACE_LIB */
1100
1101/** @name Length values.
1102 * @{ */
1103#define X86_DR7_LEN_BYTE UINT32_C(0)
1104#define X86_DR7_LEN_WORD UINT32_C(1)
1105#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1106#define X86_DR7_LEN_DWORD UINT32_C(3)
1107/** @} */
1108
1109/** Shifts a X86_DR7_LEN_* value to its right place.
1110 * @param iBp The breakpoint number [0..3].
1111 * @param cb One of the X86_DR7_LEN_* values.
1112 */
1113#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1114
1115/** Fetch the breakpoint length bits from the DR7 value.
1116 * @param uDR7 DR7 value
1117 * @param iBp The breakpoint number [0..3].
1118 */
1119#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1120
1121/** Mask used to check if any breakpoints are enabled. */
1122#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1123
1124/** LEN0, LEN1, LEN2, and LEN3. */
1125#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1126/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1127#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1128
1129/** Value of DR7 after powerup/reset. */
1130#define X86_DR7_INIT_VAL 0x400
1131/** @} */
1132
1133
1134/** @name Machine Specific Registers
1135 * @{
1136 */
1137/** Machine check address register (P5). */
1138#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1139/** Machine check type register (P5). */
1140#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1141/** Time Stamp Counter. */
1142#define MSR_IA32_TSC 0x10
1143#define MSR_IA32_CESR UINT32_C(0x00000011)
1144#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1145#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1146
1147#define MSR_IA32_PLATFORM_ID 0x17
1148
1149#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1150# define MSR_IA32_APICBASE 0x1b
1151/** Local APIC enabled. */
1152# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1153/** X2APIC enabled (requires the EN bit to be set). */
1154# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1155/** The processor is the boot strap processor (BSP). */
1156# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1157/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1158 * width. */
1159# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1160/** The default physical base address of the APIC. */
1161# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1162/** Gets the physical base address from the MSR. */
1163# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1164#endif
1165
1166/** Undocumented intel MSR for reporting thread and core counts.
1167 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1168 * first 16 bits is the thread count. The next 16 bits the core count, except
1169 * on Westmere where it seems it's only the next 4 bits for some reason. */
1170#define MSR_CORE_THREAD_COUNT 0x35
1171
1172/** CPU Feature control. */
1173#define MSR_IA32_FEATURE_CONTROL 0x3A
1174/** Feature control - Lock MSR from writes (R/W0). */
1175#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1176/** Feature control - Enable VMX inside SMX operation (R/WL). */
1177#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1178/** Feature control - Enable VMX outside SMX operation (R/WL). */
1179#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1180/** Feature control - SENTER local functions enable (R/WL). */
1181#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1182#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1183#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1184#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1185#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1186#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1187#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1188/** Feature control - SENTER global enable (R/WL). */
1189#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1190/** Feature control - SGX launch control enable (R/WL). */
1191#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1192/** Feature control - SGX global enable (R/WL). */
1193#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1194/** Feature control - LMCE on (R/WL). */
1195#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1196
1197/** Per-processor TSC adjust MSR. */
1198#define MSR_IA32_TSC_ADJUST 0x3B
1199
1200/** Spectre control register.
1201 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1202#define MSR_IA32_SPEC_CTRL 0x48
1203/** IBRS - Indirect branch restricted speculation. */
1204#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1205/** STIBP - Single thread indirect branch predictors. */
1206#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1207
1208/** Prediction command register.
1209 * Write only, logical processor scope, no state since write only. */
1210#define MSR_IA32_PRED_CMD 0x49
1211/** IBPB - Indirect branch prediction barrie when written as 1. */
1212#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1213
1214/** BIOS update trigger (microcode update). */
1215#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1216
1217/** BIOS update signature (microcode). */
1218#define MSR_IA32_BIOS_SIGN_ID 0x8B
1219
1220/** SMM monitor control. */
1221#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1222/** SMM control - Valid. */
1223#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1224/** SMM control - VMXOFF unblocks SMI. */
1225#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1226/** SMM control - MSEG base physical address. */
1227#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1228
1229/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1230#define MSR_IA32_SMBASE 0x9E
1231
1232/** General performance counter no. 0. */
1233#define MSR_IA32_PMC0 0xC1
1234/** General performance counter no. 1. */
1235#define MSR_IA32_PMC1 0xC2
1236/** General performance counter no. 2. */
1237#define MSR_IA32_PMC2 0xC3
1238/** General performance counter no. 3. */
1239#define MSR_IA32_PMC3 0xC4
1240/** General performance counter no. 4. */
1241#define MSR_IA32_PMC4 0xC5
1242/** General performance counter no. 5. */
1243#define MSR_IA32_PMC5 0xC6
1244/** General performance counter no. 6. */
1245#define MSR_IA32_PMC6 0xC7
1246/** General performance counter no. 7. */
1247#define MSR_IA32_PMC7 0xC8
1248
1249/** Nehalem power control. */
1250#define MSR_IA32_PLATFORM_INFO 0xCE
1251
1252/** Get FSB clock status (Intel-specific). */
1253#define MSR_IA32_FSB_CLOCK_STS 0xCD
1254
1255/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1256#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1257
1258/** C0 Maximum Frequency Clock Count */
1259#define MSR_IA32_MPERF 0xE7
1260/** C0 Actual Frequency Clock Count */
1261#define MSR_IA32_APERF 0xE8
1262
1263/** MTRR Capabilities. */
1264#define MSR_IA32_MTRR_CAP 0xFE
1265
1266/** Architecture capabilities (bugfixes). */
1267#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1268/** CPU is no subject to meltdown problems. */
1269#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1270/** CPU has better IBRS and you can leave it on all the time. */
1271#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1272/** CPU has return stack buffer (RSB) override. */
1273#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1274/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1275 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1276#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1277/** CPU does not suffer from MDS issues. */
1278#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1279
1280/** Flush command register. */
1281#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1282/** Flush the level 1 data cache when this bit is written. */
1283#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1284
1285/** Cache control/info. */
1286#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1287
1288#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1289/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1290 * R0 SS == CS + 8
1291 * R3 CS == CS + 16
1292 * R3 SS == CS + 24
1293 */
1294#define MSR_IA32_SYSENTER_CS 0x174
1295/** SYSENTER_ESP - the R0 ESP. */
1296#define MSR_IA32_SYSENTER_ESP 0x175
1297/** SYSENTER_EIP - the R0 EIP. */
1298#define MSR_IA32_SYSENTER_EIP 0x176
1299#endif
1300
1301/** Machine Check Global Capabilities Register. */
1302#define MSR_IA32_MCG_CAP 0x179
1303/** Machine Check Global Status Register. */
1304#define MSR_IA32_MCG_STATUS 0x17A
1305/** Machine Check Global Control Register. */
1306#define MSR_IA32_MCG_CTRL 0x17B
1307
1308/** Page Attribute Table. */
1309#define MSR_IA32_CR_PAT 0x277
1310/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1311 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1312#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1313
1314/** Performance event select MSRs. (Intel only) */
1315#define MSR_IA32_PERFEVTSEL0 0x186
1316#define MSR_IA32_PERFEVTSEL1 0x187
1317#define MSR_IA32_PERFEVTSEL2 0x188
1318#define MSR_IA32_PERFEVTSEL3 0x189
1319
1320/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1321 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1322 * holds a ratio that Apple takes for TSC granularity.
1323 *
1324 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1325#define MSR_FLEX_RATIO 0x194
1326/** Performance state value and starting with Intel core more.
1327 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1328#define MSR_IA32_PERF_STATUS 0x198
1329#define MSR_IA32_PERF_CTL 0x199
1330#define MSR_IA32_THERM_STATUS 0x19c
1331
1332/** Offcore response event select registers. */
1333#define MSR_OFFCORE_RSP_0 0x1a6
1334#define MSR_OFFCORE_RSP_1 0x1a7
1335
1336/** Enable misc. processor features (R/W). */
1337#define MSR_IA32_MISC_ENABLE 0x1A0
1338/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1339#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1340/** Automatic Thermal Control Circuit Enable (R/W). */
1341#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1342/** Performance Monitoring Available (R). */
1343#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1344/** Branch Trace Storage Unavailable (R/O). */
1345#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1346/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1347#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1348/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1349#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1350/** If MONITOR/MWAIT is supported (R/W). */
1351#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1352/** Limit CPUID Maxval to 3 leafs (R/W). */
1353#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1354/** When set to 1, xTPR messages are disabled (R/W). */
1355#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1356/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1357#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1358
1359/** Trace/Profile Resource Control (R/W) */
1360#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1361/** Last branch record. */
1362#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1363/** Branch trace flag (single step on branches). */
1364#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1365/** Performance monitoring pin control (AMD only). */
1366#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1367#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1368#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1369#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1370/** Trace message enable (Intel only). */
1371#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1372/** Branch trace store (Intel only). */
1373#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1374/** Branch trace interrupt (Intel only). */
1375#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1376/** Branch trace off in privileged code (Intel only). */
1377#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1378/** Branch trace off in user code (Intel only). */
1379#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1380/** Freeze LBR on PMI flag (Intel only). */
1381#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1382/** Freeze PERFMON on PMI flag (Intel only). */
1383#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1384/** Freeze while SMM enabled (Intel only). */
1385#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1386/** Advanced debugging of RTM regions (Intel only). */
1387#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1388/** Debug control MSR valid bits (Intel only). */
1389#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1390 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1391 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1392 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1393 | MSR_IA32_DEBUGCTL_RTM)
1394
1395/** The number (0..3 or 0..15) of the last branch record register on P4 and
1396 * related Xeons. */
1397#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1398/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1399 * @{ */
1400#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1401#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1402#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1403#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1404/** @} */
1405
1406
1407#define IA32_MTRR_PHYSBASE0 0x200
1408#define IA32_MTRR_PHYSMASK0 0x201
1409#define IA32_MTRR_PHYSBASE1 0x202
1410#define IA32_MTRR_PHYSMASK1 0x203
1411#define IA32_MTRR_PHYSBASE2 0x204
1412#define IA32_MTRR_PHYSMASK2 0x205
1413#define IA32_MTRR_PHYSBASE3 0x206
1414#define IA32_MTRR_PHYSMASK3 0x207
1415#define IA32_MTRR_PHYSBASE4 0x208
1416#define IA32_MTRR_PHYSMASK4 0x209
1417#define IA32_MTRR_PHYSBASE5 0x20a
1418#define IA32_MTRR_PHYSMASK5 0x20b
1419#define IA32_MTRR_PHYSBASE6 0x20c
1420#define IA32_MTRR_PHYSMASK6 0x20d
1421#define IA32_MTRR_PHYSBASE7 0x20e
1422#define IA32_MTRR_PHYSMASK7 0x20f
1423#define IA32_MTRR_PHYSBASE8 0x210
1424#define IA32_MTRR_PHYSMASK8 0x211
1425#define IA32_MTRR_PHYSBASE9 0x212
1426#define IA32_MTRR_PHYSMASK9 0x213
1427
1428/** Fixed range MTRRs.
1429 * @{ */
1430#define IA32_MTRR_FIX64K_00000 0x250
1431#define IA32_MTRR_FIX16K_80000 0x258
1432#define IA32_MTRR_FIX16K_A0000 0x259
1433#define IA32_MTRR_FIX4K_C0000 0x268
1434#define IA32_MTRR_FIX4K_C8000 0x269
1435#define IA32_MTRR_FIX4K_D0000 0x26a
1436#define IA32_MTRR_FIX4K_D8000 0x26b
1437#define IA32_MTRR_FIX4K_E0000 0x26c
1438#define IA32_MTRR_FIX4K_E8000 0x26d
1439#define IA32_MTRR_FIX4K_F0000 0x26e
1440#define IA32_MTRR_FIX4K_F8000 0x26f
1441/** @} */
1442
1443/** MTRR Default Range. */
1444#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1445
1446/** Global performance counter control facilities (Intel only). */
1447#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1448#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1449#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1450
1451/** Precise Event Based sampling (Intel only). */
1452#define MSR_IA32_PEBS_ENABLE 0x3F1
1453
1454#define MSR_IA32_MC0_CTL 0x400
1455#define MSR_IA32_MC0_STATUS 0x401
1456
1457/** Basic VMX information. */
1458#define MSR_IA32_VMX_BASIC 0x480
1459/** Allowed settings for pin-based VM execution controls. */
1460#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1461/** Allowed settings for proc-based VM execution controls. */
1462#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1463/** Allowed settings for the VM-exit controls. */
1464#define MSR_IA32_VMX_EXIT_CTLS 0x483
1465/** Allowed settings for the VM-entry controls. */
1466#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1467/** Misc VMX info. */
1468#define MSR_IA32_VMX_MISC 0x485
1469/** Fixed cleared bits in CR0. */
1470#define MSR_IA32_VMX_CR0_FIXED0 0x486
1471/** Fixed set bits in CR0. */
1472#define MSR_IA32_VMX_CR0_FIXED1 0x487
1473/** Fixed cleared bits in CR4. */
1474#define MSR_IA32_VMX_CR4_FIXED0 0x488
1475/** Fixed set bits in CR4. */
1476#define MSR_IA32_VMX_CR4_FIXED1 0x489
1477/** Information for enumerating fields in the VMCS. */
1478#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1479/** Allowed settings for secondary proc-based VM execution controls */
1480#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1481/** EPT capabilities. */
1482#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1483/** Allowed settings of all pin-based VM execution controls. */
1484#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1485/** Allowed settings of all proc-based VM execution controls. */
1486#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1487/** Allowed settings of all VMX exit controls. */
1488#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1489/** Allowed settings of all VMX entry controls. */
1490#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1491/** Allowed settings for the VM-function controls. */
1492#define MSR_IA32_VMX_VMFUNC 0x491
1493
1494/** Intel PT - Enable and control for trace packet generation. */
1495#define MSR_IA32_RTIT_CTL 0x570
1496
1497/** DS Save Area (R/W). */
1498#define MSR_IA32_DS_AREA 0x600
1499/** Running Average Power Limit (RAPL) power units. */
1500#define MSR_RAPL_POWER_UNIT 0x606
1501/** Package C3 Interrupt Response Limit. */
1502#define MSR_PKGC3_IRTL 0x60a
1503/** Package C6/C7S Interrupt Response Limit 1. */
1504#define MSR_PKGC_IRTL1 0x60b
1505/** Package C6/C7S Interrupt Response Limit 2. */
1506#define MSR_PKGC_IRTL2 0x60c
1507/** Package C2 Residency Counter. */
1508#define MSR_PKG_C2_RESIDENCY 0x60d
1509/** PKG RAPL Power Limit Control. */
1510#define MSR_PKG_POWER_LIMIT 0x610
1511/** PKG Energy Status. */
1512#define MSR_PKG_ENERGY_STATUS 0x611
1513/** PKG Perf Status. */
1514#define MSR_PKG_PERF_STATUS 0x613
1515/** PKG RAPL Parameters. */
1516#define MSR_PKG_POWER_INFO 0x614
1517/** DRAM RAPL Power Limit Control. */
1518#define MSR_DRAM_POWER_LIMIT 0x618
1519/** DRAM Energy Status. */
1520#define MSR_DRAM_ENERGY_STATUS 0x619
1521/** DRAM Performance Throttling Status. */
1522#define MSR_DRAM_PERF_STATUS 0x61b
1523/** DRAM RAPL Parameters. */
1524#define MSR_DRAM_POWER_INFO 0x61c
1525/** Package C10 Residency Counter. */
1526#define MSR_PKG_C10_RESIDENCY 0x632
1527/** PP0 Energy Status. */
1528#define MSR_PP0_ENERGY_STATUS 0x639
1529/** PP1 Energy Status. */
1530#define MSR_PP1_ENERGY_STATUS 0x641
1531/** Turbo Activation Ratio. */
1532#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1533/** Core Performance Limit Reasons. */
1534#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1535
1536/** Last branch record from IP MSRs.
1537 * @{ */
1538#define MSR_LASTBRANCH_0_FROM_IP 0x680
1539#define MSR_LASTBRANCH_1_FROM_IP 0x681
1540#define MSR_LASTBRANCH_2_FROM_IP 0x682
1541#define MSR_LASTBRANCH_3_FROM_IP 0x683
1542#define MSR_LASTBRANCH_4_FROM_IP 0x684
1543#define MSR_LASTBRANCH_5_FROM_IP 0x685
1544#define MSR_LASTBRANCH_6_FROM_IP 0x686
1545#define MSR_LASTBRANCH_7_FROM_IP 0x687
1546#define MSR_LASTBRANCH_8_FROM_IP 0x688
1547#define MSR_LASTBRANCH_9_FROM_IP 0x689
1548#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1549#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1550#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1551#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1552#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1553#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1554#define MSR_LASTBRANCH_16_FROM_IP 0x690
1555#define MSR_LASTBRANCH_17_FROM_IP 0x691
1556#define MSR_LASTBRANCH_18_FROM_IP 0x692
1557#define MSR_LASTBRANCH_19_FROM_IP 0x693
1558#define MSR_LASTBRANCH_20_FROM_IP 0x694
1559#define MSR_LASTBRANCH_21_FROM_IP 0x695
1560#define MSR_LASTBRANCH_22_FROM_IP 0x696
1561#define MSR_LASTBRANCH_23_FROM_IP 0x697
1562#define MSR_LASTBRANCH_24_FROM_IP 0x698
1563#define MSR_LASTBRANCH_25_FROM_IP 0x699
1564#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1565#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1566#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1567#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1568#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1569#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1570/** @} */
1571
1572/** Last branch record to IP MSRs.
1573 * @{ */
1574#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1575#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1576#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1577#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1578#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1579#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1580#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1581#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1582#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1583#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1584#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1585#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1586#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1587#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1588#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1589#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1590#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1591#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1592#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1593#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1594#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1595#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1596#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1597#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1598#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1599#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1600#define MSR_LASTBRANCH_26_TO_IP 0x6da
1601#define MSR_LASTBRANCH_27_TO_IP 0x6db
1602#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1603#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1604#define MSR_LASTBRANCH_30_TO_IP 0x6de
1605#define MSR_LASTBRANCH_31_TO_IP 0x6df
1606/** @} */
1607
1608/** X2APIC MSR range start. */
1609#define MSR_IA32_X2APIC_START 0x800
1610/** X2APIC MSR - APIC ID Register. */
1611#define MSR_IA32_X2APIC_ID 0x802
1612/** X2APIC MSR - APIC Version Register. */
1613#define MSR_IA32_X2APIC_VERSION 0x803
1614/** X2APIC MSR - Task Priority Register. */
1615#define MSR_IA32_X2APIC_TPR 0x808
1616/** X2APIC MSR - Processor Priority register. */
1617#define MSR_IA32_X2APIC_PPR 0x80A
1618/** X2APIC MSR - End Of Interrupt register. */
1619#define MSR_IA32_X2APIC_EOI 0x80B
1620/** X2APIC MSR - Logical Destination Register. */
1621#define MSR_IA32_X2APIC_LDR 0x80D
1622/** X2APIC MSR - Spurious Interrupt Vector Register. */
1623#define MSR_IA32_X2APIC_SVR 0x80F
1624/** X2APIC MSR - In-service Register (bits 31:0). */
1625#define MSR_IA32_X2APIC_ISR0 0x810
1626/** X2APIC MSR - In-service Register (bits 63:32). */
1627#define MSR_IA32_X2APIC_ISR1 0x811
1628/** X2APIC MSR - In-service Register (bits 95:64). */
1629#define MSR_IA32_X2APIC_ISR2 0x812
1630/** X2APIC MSR - In-service Register (bits 127:96). */
1631#define MSR_IA32_X2APIC_ISR3 0x813
1632/** X2APIC MSR - In-service Register (bits 159:128). */
1633#define MSR_IA32_X2APIC_ISR4 0x814
1634/** X2APIC MSR - In-service Register (bits 191:160). */
1635#define MSR_IA32_X2APIC_ISR5 0x815
1636/** X2APIC MSR - In-service Register (bits 223:192). */
1637#define MSR_IA32_X2APIC_ISR6 0x816
1638/** X2APIC MSR - In-service Register (bits 255:224). */
1639#define MSR_IA32_X2APIC_ISR7 0x817
1640/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1641#define MSR_IA32_X2APIC_TMR0 0x818
1642/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1643#define MSR_IA32_X2APIC_TMR1 0x819
1644/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1645#define MSR_IA32_X2APIC_TMR2 0x81A
1646/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1647#define MSR_IA32_X2APIC_TMR3 0x81B
1648/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1649#define MSR_IA32_X2APIC_TMR4 0x81C
1650/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1651#define MSR_IA32_X2APIC_TMR5 0x81D
1652/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1653#define MSR_IA32_X2APIC_TMR6 0x81E
1654/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1655#define MSR_IA32_X2APIC_TMR7 0x81F
1656/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1657#define MSR_IA32_X2APIC_IRR0 0x820
1658/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1659#define MSR_IA32_X2APIC_IRR1 0x821
1660/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1661#define MSR_IA32_X2APIC_IRR2 0x822
1662/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1663#define MSR_IA32_X2APIC_IRR3 0x823
1664/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1665#define MSR_IA32_X2APIC_IRR4 0x824
1666/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1667#define MSR_IA32_X2APIC_IRR5 0x825
1668/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1669#define MSR_IA32_X2APIC_IRR6 0x826
1670/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1671#define MSR_IA32_X2APIC_IRR7 0x827
1672/** X2APIC MSR - Error Status Register. */
1673#define MSR_IA32_X2APIC_ESR 0x828
1674/** X2APIC MSR - LVT CMCI Register. */
1675#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1676/** X2APIC MSR - Interrupt Command Register. */
1677#define MSR_IA32_X2APIC_ICR 0x830
1678/** X2APIC MSR - LVT Timer Register. */
1679#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1680/** X2APIC MSR - LVT Thermal Sensor Register. */
1681#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1682/** X2APIC MSR - LVT Performance Counter Register. */
1683#define MSR_IA32_X2APIC_LVT_PERF 0x834
1684/** X2APIC MSR - LVT LINT0 Register. */
1685#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1686/** X2APIC MSR - LVT LINT1 Register. */
1687#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1688/** X2APIC MSR - LVT Error Register . */
1689#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1690/** X2APIC MSR - Timer Initial Count Register. */
1691#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1692/** X2APIC MSR - Timer Current Count Register. */
1693#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1694/** X2APIC MSR - Timer Divide Configuration Register. */
1695#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1696/** X2APIC MSR - Self IPI. */
1697#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1698/** X2APIC MSR range end. */
1699#define MSR_IA32_X2APIC_END 0xBFF
1700/** X2APIC MSR - LVT start range. */
1701#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1702/** X2APIC MSR - LVT end range (inclusive). */
1703#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1704
1705/** K6 EFER - Extended Feature Enable Register. */
1706#define MSR_K6_EFER UINT32_C(0xc0000080)
1707/** @todo document EFER */
1708/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1709#define MSR_K6_EFER_SCE RT_BIT_32(0)
1710/** Bit 8 - LME - Long mode enabled. (R/W) */
1711#define MSR_K6_EFER_LME RT_BIT_32(8)
1712#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1713/** Bit 10 - LMA - Long mode active. (R) */
1714#define MSR_K6_EFER_LMA RT_BIT_32(10)
1715#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1716/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1717#define MSR_K6_EFER_NXE RT_BIT_32(11)
1718#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1719/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1720#define MSR_K6_EFER_SVME RT_BIT_32(12)
1721/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1722#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1723/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1724#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1725/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1726#define MSR_K6_EFER_TCE RT_BIT_32(15)
1727/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1728#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1729
1730/** K6 STAR - SYSCALL/RET targets. */
1731#define MSR_K6_STAR UINT32_C(0xc0000081)
1732/** Shift value for getting the SYSRET CS and SS value. */
1733#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1734/** Shift value for getting the SYSCALL CS and SS value. */
1735#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1736/** Selector mask for use after shifting. */
1737#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1738/** The mask which give the SYSCALL EIP. */
1739#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1740/** K6 WHCR - Write Handling Control Register. */
1741#define MSR_K6_WHCR UINT32_C(0xc0000082)
1742/** K6 UWCCR - UC/WC Cacheability Control Register. */
1743#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1744/** K6 PSOR - Processor State Observability Register. */
1745#define MSR_K6_PSOR UINT32_C(0xc0000087)
1746/** K6 PFIR - Page Flush/Invalidate Register. */
1747#define MSR_K6_PFIR UINT32_C(0xc0000088)
1748
1749/** Performance counter MSRs. (AMD only) */
1750#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1751#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1752#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1753#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1754#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1755#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1756#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1757#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1758
1759/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1760#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1761/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1762#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1763/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1764#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1765/** K8 FS.base - The 64-bit base FS register. */
1766#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1767/** K8 GS.base - The 64-bit base GS register. */
1768#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1769/** K8 KernelGSbase - Used with SWAPGS. */
1770#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1771/** K8 TSC_AUX - Used with RDTSCP. */
1772#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1773#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1774#define MSR_K8_HWCR UINT32_C(0xc0010015)
1775#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1776#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1777#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1778#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1779#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1780#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1781/** North bridge config? See BIOS & Kernel dev guides for
1782 * details. */
1783#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1784
1785/** Hypertransport interrupt pending register.
1786 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1787#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1788
1789/** SVM Control. */
1790#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1791/** Disables HDT (Hardware Debug Tool) and certain internal debug
1792 * features. */
1793#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1794/** If set, non-intercepted INIT signals are converted to \#SX
1795 * exceptions. */
1796#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1797/** Disables A20 masking. */
1798#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1799/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1800#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1801/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1802 * clear, EFER.SVME can be written normally. */
1803#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1804
1805#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1806#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1807/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1808 * host state during world switch. */
1809#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1810
1811/** @} */
1812
1813
1814/** @name Page Table / Directory / Directory Pointers / L4.
1815 * @{
1816 */
1817
1818/** Page table/directory entry as an unsigned integer. */
1819typedef uint32_t X86PGUINT;
1820/** Pointer to a page table/directory table entry as an unsigned integer. */
1821typedef X86PGUINT *PX86PGUINT;
1822/** Pointer to an const page table/directory table entry as an unsigned integer. */
1823typedef X86PGUINT const *PCX86PGUINT;
1824
1825/** Number of entries in a 32-bit PT/PD. */
1826#define X86_PG_ENTRIES 1024
1827
1828
1829/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1830typedef uint64_t X86PGPAEUINT;
1831/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1832typedef X86PGPAEUINT *PX86PGPAEUINT;
1833/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1834typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1835
1836/** Number of entries in a PAE PT/PD. */
1837#define X86_PG_PAE_ENTRIES 512
1838/** Number of entries in a PAE PDPT. */
1839#define X86_PG_PAE_PDPE_ENTRIES 4
1840
1841/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1842#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1843/** Number of entries in an AMD64 PDPT.
1844 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1845#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1846
1847/** The size of a default page. */
1848#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1849/** The page shift of a default page. */
1850#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1851/** The default page offset mask. */
1852#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1853/** The default page base mask for virtual addresses. */
1854#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1855/** The default page base mask for virtual addresses - 32bit version. */
1856#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1857
1858/** The size of a 4KB page. */
1859#define X86_PAGE_4K_SIZE _4K
1860/** The page shift of a 4KB page. */
1861#define X86_PAGE_4K_SHIFT 12
1862/** The 4KB page offset mask. */
1863#define X86_PAGE_4K_OFFSET_MASK 0xfff
1864/** The 4KB page base mask for virtual addresses. */
1865#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1866/** The 4KB page base mask for virtual addresses - 32bit version. */
1867#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1868
1869/** The size of a 2MB page. */
1870#define X86_PAGE_2M_SIZE _2M
1871/** The page shift of a 2MB page. */
1872#define X86_PAGE_2M_SHIFT 21
1873/** The 2MB page offset mask. */
1874#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1875/** The 2MB page base mask for virtual addresses. */
1876#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1877/** The 2MB page base mask for virtual addresses - 32bit version. */
1878#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1879
1880/** The size of a 4MB page. */
1881#define X86_PAGE_4M_SIZE _4M
1882/** The page shift of a 4MB page. */
1883#define X86_PAGE_4M_SHIFT 22
1884/** The 4MB page offset mask. */
1885#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1886/** The 4MB page base mask for virtual addresses. */
1887#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1888/** The 4MB page base mask for virtual addresses - 32bit version. */
1889#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1890
1891/** The size of a 1GB page. */
1892#define X86_PAGE_1G_SIZE _1G
1893/** The page shift of a 1GB page. */
1894#define X86_PAGE_1G_SHIFT 30
1895/** The 1GB page offset mask. */
1896#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1897/** The 1GB page base mask for virtual addresses. */
1898#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1899
1900/**
1901 * Check if the given address is canonical.
1902 */
1903#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1904
1905
1906/** @name Page Table Entry
1907 * @{
1908 */
1909/** Bit 0 - P - Present bit. */
1910#define X86_PTE_BIT_P 0
1911/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1912#define X86_PTE_BIT_RW 1
1913/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1914#define X86_PTE_BIT_US 2
1915/** Bit 3 - PWT - Page level write thru bit. */
1916#define X86_PTE_BIT_PWT 3
1917/** Bit 4 - PCD - Page level cache disable bit. */
1918#define X86_PTE_BIT_PCD 4
1919/** Bit 5 - A - Access bit. */
1920#define X86_PTE_BIT_A 5
1921/** Bit 6 - D - Dirty bit. */
1922#define X86_PTE_BIT_D 6
1923/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1924#define X86_PTE_BIT_PAT 7
1925/** Bit 8 - G - Global flag. */
1926#define X86_PTE_BIT_G 8
1927/** Bits 63 - NX - PAE/LM - No execution flag. */
1928#define X86_PTE_PAE_BIT_NX 63
1929
1930/** Bit 0 - P - Present bit mask. */
1931#define X86_PTE_P RT_BIT_32(0)
1932/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1933#define X86_PTE_RW RT_BIT_32(1)
1934/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1935#define X86_PTE_US RT_BIT_32(2)
1936/** Bit 3 - PWT - Page level write thru bit mask. */
1937#define X86_PTE_PWT RT_BIT_32(3)
1938/** Bit 4 - PCD - Page level cache disable bit mask. */
1939#define X86_PTE_PCD RT_BIT_32(4)
1940/** Bit 5 - A - Access bit mask. */
1941#define X86_PTE_A RT_BIT_32(5)
1942/** Bit 6 - D - Dirty bit mask. */
1943#define X86_PTE_D RT_BIT_32(6)
1944/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1945#define X86_PTE_PAT RT_BIT_32(7)
1946/** Bit 8 - G - Global bit mask. */
1947#define X86_PTE_G RT_BIT_32(8)
1948
1949/** Bits 9-11 - - Available for use to system software. */
1950#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1951/** Bits 12-31 - - Physical Page number of the next level. */
1952#define X86_PTE_PG_MASK ( 0xfffff000 )
1953
1954/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1955#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1956/** Bits 63 - NX - PAE/LM - No execution flag. */
1957#define X86_PTE_PAE_NX RT_BIT_64(63)
1958/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1959#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1960/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1961#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1962/** No bits - - LM - MBZ bits when NX is active. */
1963#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1964/** Bits 63 - - LM - MBZ bits when no NX. */
1965#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1966
1967/**
1968 * Page table entry.
1969 */
1970typedef struct X86PTEBITS
1971{
1972 /** Flags whether(=1) or not the page is present. */
1973 uint32_t u1Present : 1;
1974 /** Read(=0) / Write(=1) flag. */
1975 uint32_t u1Write : 1;
1976 /** User(=1) / Supervisor (=0) flag. */
1977 uint32_t u1User : 1;
1978 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1979 uint32_t u1WriteThru : 1;
1980 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1981 uint32_t u1CacheDisable : 1;
1982 /** Accessed flag.
1983 * Indicates that the page have been read or written to. */
1984 uint32_t u1Accessed : 1;
1985 /** Dirty flag.
1986 * Indicates that the page has been written to. */
1987 uint32_t u1Dirty : 1;
1988 /** Reserved / If PAT enabled, bit 2 of the index. */
1989 uint32_t u1PAT : 1;
1990 /** Global flag. (Ignored in all but final level.) */
1991 uint32_t u1Global : 1;
1992 /** Available for use to system software. */
1993 uint32_t u3Available : 3;
1994 /** Physical Page number of the next level. */
1995 uint32_t u20PageNo : 20;
1996} X86PTEBITS;
1997#ifndef VBOX_FOR_DTRACE_LIB
1998AssertCompileSize(X86PTEBITS, 4);
1999#endif
2000/** Pointer to a page table entry. */
2001typedef X86PTEBITS *PX86PTEBITS;
2002/** Pointer to a const page table entry. */
2003typedef const X86PTEBITS *PCX86PTEBITS;
2004
2005/**
2006 * Page table entry.
2007 */
2008typedef union X86PTE
2009{
2010 /** Unsigned integer view */
2011 X86PGUINT u;
2012 /** Bit field view. */
2013 X86PTEBITS n;
2014 /** 32-bit view. */
2015 uint32_t au32[1];
2016 /** 16-bit view. */
2017 uint16_t au16[2];
2018 /** 8-bit view. */
2019 uint8_t au8[4];
2020} X86PTE;
2021#ifndef VBOX_FOR_DTRACE_LIB
2022AssertCompileSize(X86PTE, 4);
2023#endif
2024/** Pointer to a page table entry. */
2025typedef X86PTE *PX86PTE;
2026/** Pointer to a const page table entry. */
2027typedef const X86PTE *PCX86PTE;
2028
2029
2030/**
2031 * PAE page table entry.
2032 */
2033typedef struct X86PTEPAEBITS
2034{
2035 /** Flags whether(=1) or not the page is present. */
2036 uint32_t u1Present : 1;
2037 /** Read(=0) / Write(=1) flag. */
2038 uint32_t u1Write : 1;
2039 /** User(=1) / Supervisor(=0) flag. */
2040 uint32_t u1User : 1;
2041 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2042 uint32_t u1WriteThru : 1;
2043 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2044 uint32_t u1CacheDisable : 1;
2045 /** Accessed flag.
2046 * Indicates that the page have been read or written to. */
2047 uint32_t u1Accessed : 1;
2048 /** Dirty flag.
2049 * Indicates that the page has been written to. */
2050 uint32_t u1Dirty : 1;
2051 /** Reserved / If PAT enabled, bit 2 of the index. */
2052 uint32_t u1PAT : 1;
2053 /** Global flag. (Ignored in all but final level.) */
2054 uint32_t u1Global : 1;
2055 /** Available for use to system software. */
2056 uint32_t u3Available : 3;
2057 /** Physical Page number of the next level - Low Part. Don't use this. */
2058 uint32_t u20PageNoLow : 20;
2059 /** Physical Page number of the next level - High Part. Don't use this. */
2060 uint32_t u20PageNoHigh : 20;
2061 /** MBZ bits */
2062 uint32_t u11Reserved : 11;
2063 /** No Execute flag. */
2064 uint32_t u1NoExecute : 1;
2065} X86PTEPAEBITS;
2066#ifndef VBOX_FOR_DTRACE_LIB
2067AssertCompileSize(X86PTEPAEBITS, 8);
2068#endif
2069/** Pointer to a page table entry. */
2070typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2071/** Pointer to a page table entry. */
2072typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2073
2074/**
2075 * PAE Page table entry.
2076 */
2077typedef union X86PTEPAE
2078{
2079 /** Unsigned integer view */
2080 X86PGPAEUINT u;
2081 /** Bit field view. */
2082 X86PTEPAEBITS n;
2083 /** 32-bit view. */
2084 uint32_t au32[2];
2085 /** 16-bit view. */
2086 uint16_t au16[4];
2087 /** 8-bit view. */
2088 uint8_t au8[8];
2089} X86PTEPAE;
2090#ifndef VBOX_FOR_DTRACE_LIB
2091AssertCompileSize(X86PTEPAE, 8);
2092#endif
2093/** Pointer to a PAE page table entry. */
2094typedef X86PTEPAE *PX86PTEPAE;
2095/** Pointer to a const PAE page table entry. */
2096typedef const X86PTEPAE *PCX86PTEPAE;
2097/** @} */
2098
2099/**
2100 * Page table.
2101 */
2102typedef struct X86PT
2103{
2104 /** PTE Array. */
2105 X86PTE a[X86_PG_ENTRIES];
2106} X86PT;
2107#ifndef VBOX_FOR_DTRACE_LIB
2108AssertCompileSize(X86PT, 4096);
2109#endif
2110/** Pointer to a page table. */
2111typedef X86PT *PX86PT;
2112/** Pointer to a const page table. */
2113typedef const X86PT *PCX86PT;
2114
2115/** The page shift to get the PT index. */
2116#define X86_PT_SHIFT 12
2117/** The PT index mask (apply to a shifted page address). */
2118#define X86_PT_MASK 0x3ff
2119
2120
2121/**
2122 * Page directory.
2123 */
2124typedef struct X86PTPAE
2125{
2126 /** PTE Array. */
2127 X86PTEPAE a[X86_PG_PAE_ENTRIES];
2128} X86PTPAE;
2129#ifndef VBOX_FOR_DTRACE_LIB
2130AssertCompileSize(X86PTPAE, 4096);
2131#endif
2132/** Pointer to a page table. */
2133typedef X86PTPAE *PX86PTPAE;
2134/** Pointer to a const page table. */
2135typedef const X86PTPAE *PCX86PTPAE;
2136
2137/** The page shift to get the PA PTE index. */
2138#define X86_PT_PAE_SHIFT 12
2139/** The PAE PT index mask (apply to a shifted page address). */
2140#define X86_PT_PAE_MASK 0x1ff
2141
2142
2143/** @name 4KB Page Directory Entry
2144 * @{
2145 */
2146/** Bit 0 - P - Present bit. */
2147#define X86_PDE_P RT_BIT_32(0)
2148/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2149#define X86_PDE_RW RT_BIT_32(1)
2150/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2151#define X86_PDE_US RT_BIT_32(2)
2152/** Bit 3 - PWT - Page level write thru bit. */
2153#define X86_PDE_PWT RT_BIT_32(3)
2154/** Bit 4 - PCD - Page level cache disable bit. */
2155#define X86_PDE_PCD RT_BIT_32(4)
2156/** Bit 5 - A - Access bit. */
2157#define X86_PDE_A RT_BIT_32(5)
2158/** Bit 7 - PS - Page size attribute.
2159 * Clear mean 4KB pages, set means large pages (2/4MB). */
2160#define X86_PDE_PS RT_BIT_32(7)
2161/** Bits 9-11 - - Available for use to system software. */
2162#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2163/** Bits 12-31 - - Physical Page number of the next level. */
2164#define X86_PDE_PG_MASK ( 0xfffff000 )
2165
2166/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2167#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2168/** Bits 63 - NX - PAE/LM - No execution flag. */
2169#define X86_PDE_PAE_NX RT_BIT_64(63)
2170/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2171#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2172/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2173#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2174/** Bit 7 - - LM - MBZ bits when NX is active. */
2175#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2176/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2177#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2178
2179/**
2180 * Page directory entry.
2181 */
2182typedef struct X86PDEBITS
2183{
2184 /** Flags whether(=1) or not the page is present. */
2185 uint32_t u1Present : 1;
2186 /** Read(=0) / Write(=1) flag. */
2187 uint32_t u1Write : 1;
2188 /** User(=1) / Supervisor (=0) flag. */
2189 uint32_t u1User : 1;
2190 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2191 uint32_t u1WriteThru : 1;
2192 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2193 uint32_t u1CacheDisable : 1;
2194 /** Accessed flag.
2195 * Indicates that the page has been read or written to. */
2196 uint32_t u1Accessed : 1;
2197 /** Reserved / Ignored (dirty bit). */
2198 uint32_t u1Reserved0 : 1;
2199 /** Size bit if PSE is enabled - in any event it's 0. */
2200 uint32_t u1Size : 1;
2201 /** Reserved / Ignored (global bit). */
2202 uint32_t u1Reserved1 : 1;
2203 /** Available for use to system software. */
2204 uint32_t u3Available : 3;
2205 /** Physical Page number of the next level. */
2206 uint32_t u20PageNo : 20;
2207} X86PDEBITS;
2208#ifndef VBOX_FOR_DTRACE_LIB
2209AssertCompileSize(X86PDEBITS, 4);
2210#endif
2211/** Pointer to a page directory entry. */
2212typedef X86PDEBITS *PX86PDEBITS;
2213/** Pointer to a const page directory entry. */
2214typedef const X86PDEBITS *PCX86PDEBITS;
2215
2216
2217/**
2218 * PAE page directory entry.
2219 */
2220typedef struct X86PDEPAEBITS
2221{
2222 /** Flags whether(=1) or not the page is present. */
2223 uint32_t u1Present : 1;
2224 /** Read(=0) / Write(=1) flag. */
2225 uint32_t u1Write : 1;
2226 /** User(=1) / Supervisor (=0) flag. */
2227 uint32_t u1User : 1;
2228 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2229 uint32_t u1WriteThru : 1;
2230 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2231 uint32_t u1CacheDisable : 1;
2232 /** Accessed flag.
2233 * Indicates that the page has been read or written to. */
2234 uint32_t u1Accessed : 1;
2235 /** Reserved / Ignored (dirty bit). */
2236 uint32_t u1Reserved0 : 1;
2237 /** Size bit if PSE is enabled - in any event it's 0. */
2238 uint32_t u1Size : 1;
2239 /** Reserved / Ignored (global bit). / */
2240 uint32_t u1Reserved1 : 1;
2241 /** Available for use to system software. */
2242 uint32_t u3Available : 3;
2243 /** Physical Page number of the next level - Low Part. Don't use! */
2244 uint32_t u20PageNoLow : 20;
2245 /** Physical Page number of the next level - High Part. Don't use! */
2246 uint32_t u20PageNoHigh : 20;
2247 /** MBZ bits */
2248 uint32_t u11Reserved : 11;
2249 /** No Execute flag. */
2250 uint32_t u1NoExecute : 1;
2251} X86PDEPAEBITS;
2252#ifndef VBOX_FOR_DTRACE_LIB
2253AssertCompileSize(X86PDEPAEBITS, 8);
2254#endif
2255/** Pointer to a page directory entry. */
2256typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2257/** Pointer to a const page directory entry. */
2258typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2259
2260/** @} */
2261
2262
2263/** @name 2/4MB Page Directory Entry
2264 * @{
2265 */
2266/** Bit 0 - P - Present bit. */
2267#define X86_PDE4M_P RT_BIT_32(0)
2268/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2269#define X86_PDE4M_RW RT_BIT_32(1)
2270/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2271#define X86_PDE4M_US RT_BIT_32(2)
2272/** Bit 3 - PWT - Page level write thru bit. */
2273#define X86_PDE4M_PWT RT_BIT_32(3)
2274/** Bit 4 - PCD - Page level cache disable bit. */
2275#define X86_PDE4M_PCD RT_BIT_32(4)
2276/** Bit 5 - A - Access bit. */
2277#define X86_PDE4M_A RT_BIT_32(5)
2278/** Bit 6 - D - Dirty bit. */
2279#define X86_PDE4M_D RT_BIT_32(6)
2280/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2281#define X86_PDE4M_PS RT_BIT_32(7)
2282/** Bit 8 - G - Global flag. */
2283#define X86_PDE4M_G RT_BIT_32(8)
2284/** Bits 9-11 - AVL - Available for use to system software. */
2285#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2286/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2287#define X86_PDE4M_PAT RT_BIT_32(12)
2288/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2289#define X86_PDE4M_PAT_SHIFT (12 - 7)
2290/** Bits 22-31 - - Physical Page number. */
2291#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2292/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2293#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2294/** The number of bits to the high part of the page number. */
2295#define X86_PDE4M_PG_HIGH_SHIFT 19
2296/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2297#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2298
2299/** Bits 21-51 - - PAE/LM - Physical Page number.
2300 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2301#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2302/** Bits 63 - NX - PAE/LM - No execution flag. */
2303#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2304/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2305#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2306/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2307#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2308/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2309#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2310/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2311#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2312
2313/**
2314 * 4MB page directory entry.
2315 */
2316typedef struct X86PDE4MBITS
2317{
2318 /** Flags whether(=1) or not the page is present. */
2319 uint32_t u1Present : 1;
2320 /** Read(=0) / Write(=1) flag. */
2321 uint32_t u1Write : 1;
2322 /** User(=1) / Supervisor (=0) flag. */
2323 uint32_t u1User : 1;
2324 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2325 uint32_t u1WriteThru : 1;
2326 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2327 uint32_t u1CacheDisable : 1;
2328 /** Accessed flag.
2329 * Indicates that the page have been read or written to. */
2330 uint32_t u1Accessed : 1;
2331 /** Dirty flag.
2332 * Indicates that the page has been written to. */
2333 uint32_t u1Dirty : 1;
2334 /** Page size flag - always 1 for 4MB entries. */
2335 uint32_t u1Size : 1;
2336 /** Global flag. */
2337 uint32_t u1Global : 1;
2338 /** Available for use to system software. */
2339 uint32_t u3Available : 3;
2340 /** Reserved / If PAT enabled, bit 2 of the index. */
2341 uint32_t u1PAT : 1;
2342 /** Bits 32-39 of the page number on AMD64.
2343 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2344 uint32_t u8PageNoHigh : 8;
2345 /** Reserved. */
2346 uint32_t u1Reserved : 1;
2347 /** Physical Page number of the page. */
2348 uint32_t u10PageNo : 10;
2349} X86PDE4MBITS;
2350#ifndef VBOX_FOR_DTRACE_LIB
2351AssertCompileSize(X86PDE4MBITS, 4);
2352#endif
2353/** Pointer to a page table entry. */
2354typedef X86PDE4MBITS *PX86PDE4MBITS;
2355/** Pointer to a const page table entry. */
2356typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2357
2358
2359/**
2360 * 2MB PAE page directory entry.
2361 */
2362typedef struct X86PDE2MPAEBITS
2363{
2364 /** Flags whether(=1) or not the page is present. */
2365 uint32_t u1Present : 1;
2366 /** Read(=0) / Write(=1) flag. */
2367 uint32_t u1Write : 1;
2368 /** User(=1) / Supervisor(=0) flag. */
2369 uint32_t u1User : 1;
2370 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2371 uint32_t u1WriteThru : 1;
2372 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2373 uint32_t u1CacheDisable : 1;
2374 /** Accessed flag.
2375 * Indicates that the page have been read or written to. */
2376 uint32_t u1Accessed : 1;
2377 /** Dirty flag.
2378 * Indicates that the page has been written to. */
2379 uint32_t u1Dirty : 1;
2380 /** Page size flag - always 1 for 2MB entries. */
2381 uint32_t u1Size : 1;
2382 /** Global flag. */
2383 uint32_t u1Global : 1;
2384 /** Available for use to system software. */
2385 uint32_t u3Available : 3;
2386 /** Reserved / If PAT enabled, bit 2 of the index. */
2387 uint32_t u1PAT : 1;
2388 /** Reserved. */
2389 uint32_t u9Reserved : 9;
2390 /** Physical Page number of the next level - Low part. Don't use! */
2391 uint32_t u10PageNoLow : 10;
2392 /** Physical Page number of the next level - High part. Don't use! */
2393 uint32_t u20PageNoHigh : 20;
2394 /** MBZ bits */
2395 uint32_t u11Reserved : 11;
2396 /** No Execute flag. */
2397 uint32_t u1NoExecute : 1;
2398} X86PDE2MPAEBITS;
2399#ifndef VBOX_FOR_DTRACE_LIB
2400AssertCompileSize(X86PDE2MPAEBITS, 8);
2401#endif
2402/** Pointer to a 2MB PAE page table entry. */
2403typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2404/** Pointer to a 2MB PAE page table entry. */
2405typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2406
2407/** @} */
2408
2409/**
2410 * Page directory entry.
2411 */
2412typedef union X86PDE
2413{
2414 /** Unsigned integer view. */
2415 X86PGUINT u;
2416 /** Normal view. */
2417 X86PDEBITS n;
2418 /** 4MB view (big). */
2419 X86PDE4MBITS b;
2420 /** 8 bit unsigned integer view. */
2421 uint8_t au8[4];
2422 /** 16 bit unsigned integer view. */
2423 uint16_t au16[2];
2424 /** 32 bit unsigned integer view. */
2425 uint32_t au32[1];
2426} X86PDE;
2427#ifndef VBOX_FOR_DTRACE_LIB
2428AssertCompileSize(X86PDE, 4);
2429#endif
2430/** Pointer to a page directory entry. */
2431typedef X86PDE *PX86PDE;
2432/** Pointer to a const page directory entry. */
2433typedef const X86PDE *PCX86PDE;
2434
2435/**
2436 * PAE page directory entry.
2437 */
2438typedef union X86PDEPAE
2439{
2440 /** Unsigned integer view. */
2441 X86PGPAEUINT u;
2442 /** Normal view. */
2443 X86PDEPAEBITS n;
2444 /** 2MB page view (big). */
2445 X86PDE2MPAEBITS b;
2446 /** 8 bit unsigned integer view. */
2447 uint8_t au8[8];
2448 /** 16 bit unsigned integer view. */
2449 uint16_t au16[4];
2450 /** 32 bit unsigned integer view. */
2451 uint32_t au32[2];
2452} X86PDEPAE;
2453#ifndef VBOX_FOR_DTRACE_LIB
2454AssertCompileSize(X86PDEPAE, 8);
2455#endif
2456/** Pointer to a page directory entry. */
2457typedef X86PDEPAE *PX86PDEPAE;
2458/** Pointer to a const page directory entry. */
2459typedef const X86PDEPAE *PCX86PDEPAE;
2460
2461/**
2462 * Page directory.
2463 */
2464typedef struct X86PD
2465{
2466 /** PDE Array. */
2467 X86PDE a[X86_PG_ENTRIES];
2468} X86PD;
2469#ifndef VBOX_FOR_DTRACE_LIB
2470AssertCompileSize(X86PD, 4096);
2471#endif
2472/** Pointer to a page directory. */
2473typedef X86PD *PX86PD;
2474/** Pointer to a const page directory. */
2475typedef const X86PD *PCX86PD;
2476
2477/** The page shift to get the PD index. */
2478#define X86_PD_SHIFT 22
2479/** The PD index mask (apply to a shifted page address). */
2480#define X86_PD_MASK 0x3ff
2481
2482
2483/**
2484 * PAE page directory.
2485 */
2486typedef struct X86PDPAE
2487{
2488 /** PDE Array. */
2489 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2490} X86PDPAE;
2491#ifndef VBOX_FOR_DTRACE_LIB
2492AssertCompileSize(X86PDPAE, 4096);
2493#endif
2494/** Pointer to a PAE page directory. */
2495typedef X86PDPAE *PX86PDPAE;
2496/** Pointer to a const PAE page directory. */
2497typedef const X86PDPAE *PCX86PDPAE;
2498
2499/** The page shift to get the PAE PD index. */
2500#define X86_PD_PAE_SHIFT 21
2501/** The PAE PD index mask (apply to a shifted page address). */
2502#define X86_PD_PAE_MASK 0x1ff
2503
2504
2505/** @name Page Directory Pointer Table Entry (PAE)
2506 * @{
2507 */
2508/** Bit 0 - P - Present bit. */
2509#define X86_PDPE_P RT_BIT_32(0)
2510/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2511#define X86_PDPE_RW RT_BIT_32(1)
2512/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2513#define X86_PDPE_US RT_BIT_32(2)
2514/** Bit 3 - PWT - Page level write thru bit. */
2515#define X86_PDPE_PWT RT_BIT_32(3)
2516/** Bit 4 - PCD - Page level cache disable bit. */
2517#define X86_PDPE_PCD RT_BIT_32(4)
2518/** Bit 5 - A - Access bit. Long Mode only. */
2519#define X86_PDPE_A RT_BIT_32(5)
2520/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2521#define X86_PDPE_LM_PS RT_BIT_32(7)
2522/** Bits 9-11 - - Available for use to system software. */
2523#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2524/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2525#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2526/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2527#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2528/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2529#define X86_PDPE_LM_NX RT_BIT_64(63)
2530/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2531#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2532/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2533#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2534/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2535#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2536/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2537#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2538
2539
2540/**
2541 * Page directory pointer table entry.
2542 */
2543typedef struct X86PDPEBITS
2544{
2545 /** Flags whether(=1) or not the page is present. */
2546 uint32_t u1Present : 1;
2547 /** Chunk of reserved bits. */
2548 uint32_t u2Reserved : 2;
2549 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2550 uint32_t u1WriteThru : 1;
2551 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2552 uint32_t u1CacheDisable : 1;
2553 /** Chunk of reserved bits. */
2554 uint32_t u4Reserved : 4;
2555 /** Available for use to system software. */
2556 uint32_t u3Available : 3;
2557 /** Physical Page number of the next level - Low Part. Don't use! */
2558 uint32_t u20PageNoLow : 20;
2559 /** Physical Page number of the next level - High Part. Don't use! */
2560 uint32_t u20PageNoHigh : 20;
2561 /** MBZ bits */
2562 uint32_t u12Reserved : 12;
2563} X86PDPEBITS;
2564#ifndef VBOX_FOR_DTRACE_LIB
2565AssertCompileSize(X86PDPEBITS, 8);
2566#endif
2567/** Pointer to a page directory pointer table entry. */
2568typedef X86PDPEBITS *PX86PTPEBITS;
2569/** Pointer to a const page directory pointer table entry. */
2570typedef const X86PDPEBITS *PCX86PTPEBITS;
2571
2572/**
2573 * Page directory pointer table entry. AMD64 version
2574 */
2575typedef struct X86PDPEAMD64BITS
2576{
2577 /** Flags whether(=1) or not the page is present. */
2578 uint32_t u1Present : 1;
2579 /** Read(=0) / Write(=1) flag. */
2580 uint32_t u1Write : 1;
2581 /** User(=1) / Supervisor (=0) flag. */
2582 uint32_t u1User : 1;
2583 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2584 uint32_t u1WriteThru : 1;
2585 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2586 uint32_t u1CacheDisable : 1;
2587 /** Accessed flag.
2588 * Indicates that the page have been read or written to. */
2589 uint32_t u1Accessed : 1;
2590 /** Chunk of reserved bits. */
2591 uint32_t u3Reserved : 3;
2592 /** Available for use to system software. */
2593 uint32_t u3Available : 3;
2594 /** Physical Page number of the next level - Low Part. Don't use! */
2595 uint32_t u20PageNoLow : 20;
2596 /** Physical Page number of the next level - High Part. Don't use! */
2597 uint32_t u20PageNoHigh : 20;
2598 /** MBZ bits */
2599 uint32_t u11Reserved : 11;
2600 /** No Execute flag. */
2601 uint32_t u1NoExecute : 1;
2602} X86PDPEAMD64BITS;
2603#ifndef VBOX_FOR_DTRACE_LIB
2604AssertCompileSize(X86PDPEAMD64BITS, 8);
2605#endif
2606/** Pointer to a page directory pointer table entry. */
2607typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2608/** Pointer to a const page directory pointer table entry. */
2609typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2610
2611/**
2612 * Page directory pointer table entry for 1GB page. (AMD64 only)
2613 */
2614typedef struct X86PDPE1GB
2615{
2616 /** 0: Flags whether(=1) or not the page is present. */
2617 uint32_t u1Present : 1;
2618 /** 1: Read(=0) / Write(=1) flag. */
2619 uint32_t u1Write : 1;
2620 /** 2: User(=1) / Supervisor (=0) flag. */
2621 uint32_t u1User : 1;
2622 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2623 uint32_t u1WriteThru : 1;
2624 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2625 uint32_t u1CacheDisable : 1;
2626 /** 5: Accessed flag.
2627 * Indicates that the page have been read or written to. */
2628 uint32_t u1Accessed : 1;
2629 /** 6: Dirty flag for 1GB pages. */
2630 uint32_t u1Dirty : 1;
2631 /** 7: Indicates 1GB page if set. */
2632 uint32_t u1Size : 1;
2633 /** 8: Global 1GB page. */
2634 uint32_t u1Global: 1;
2635 /** 9-11: Available for use to system software. */
2636 uint32_t u3Available : 3;
2637 /** 12: PAT bit for 1GB page. */
2638 uint32_t u1PAT : 1;
2639 /** 13-29: MBZ bits. */
2640 uint32_t u17Reserved : 17;
2641 /** 30-31: Physical page number - Low Part. Don't use! */
2642 uint32_t u2PageNoLow : 2;
2643 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2644 uint32_t u20PageNoHigh : 20;
2645 /** 52-62: MBZ bits */
2646 uint32_t u11Reserved : 11;
2647 /** 63: No Execute flag. */
2648 uint32_t u1NoExecute : 1;
2649} X86PDPE1GB;
2650#ifndef VBOX_FOR_DTRACE_LIB
2651AssertCompileSize(X86PDPE1GB, 8);
2652#endif
2653/** Pointer to a page directory pointer table entry for a 1GB page. */
2654typedef X86PDPE1GB *PX86PDPE1GB;
2655/** Pointer to a const page directory pointer table entry for a 1GB page. */
2656typedef const X86PDPE1GB *PCX86PDPE1GB;
2657
2658/**
2659 * Page directory pointer table entry.
2660 */
2661typedef union X86PDPE
2662{
2663 /** Unsigned integer view. */
2664 X86PGPAEUINT u;
2665 /** Normal view. */
2666 X86PDPEBITS n;
2667 /** AMD64 view. */
2668 X86PDPEAMD64BITS lm;
2669 /** AMD64 big view. */
2670 X86PDPE1GB b;
2671 /** 8 bit unsigned integer view. */
2672 uint8_t au8[8];
2673 /** 16 bit unsigned integer view. */
2674 uint16_t au16[4];
2675 /** 32 bit unsigned integer view. */
2676 uint32_t au32[2];
2677} X86PDPE;
2678#ifndef VBOX_FOR_DTRACE_LIB
2679AssertCompileSize(X86PDPE, 8);
2680#endif
2681/** Pointer to a page directory pointer table entry. */
2682typedef X86PDPE *PX86PDPE;
2683/** Pointer to a const page directory pointer table entry. */
2684typedef const X86PDPE *PCX86PDPE;
2685
2686
2687/**
2688 * Page directory pointer table.
2689 */
2690typedef struct X86PDPT
2691{
2692 /** PDE Array. */
2693 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2694} X86PDPT;
2695#ifndef VBOX_FOR_DTRACE_LIB
2696AssertCompileSize(X86PDPT, 4096);
2697#endif
2698/** Pointer to a page directory pointer table. */
2699typedef X86PDPT *PX86PDPT;
2700/** Pointer to a const page directory pointer table. */
2701typedef const X86PDPT *PCX86PDPT;
2702
2703/** The page shift to get the PDPT index. */
2704#define X86_PDPT_SHIFT 30
2705/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2706#define X86_PDPT_MASK_PAE 0x3
2707/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2708#define X86_PDPT_MASK_AMD64 0x1ff
2709
2710/** @} */
2711
2712
2713/** @name Page Map Level-4 Entry (Long Mode PAE)
2714 * @{
2715 */
2716/** Bit 0 - P - Present bit. */
2717#define X86_PML4E_P RT_BIT_32(0)
2718/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2719#define X86_PML4E_RW RT_BIT_32(1)
2720/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2721#define X86_PML4E_US RT_BIT_32(2)
2722/** Bit 3 - PWT - Page level write thru bit. */
2723#define X86_PML4E_PWT RT_BIT_32(3)
2724/** Bit 4 - PCD - Page level cache disable bit. */
2725#define X86_PML4E_PCD RT_BIT_32(4)
2726/** Bit 5 - A - Access bit. */
2727#define X86_PML4E_A RT_BIT_32(5)
2728/** Bits 9-11 - - Available for use to system software. */
2729#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2730/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2731#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2732/** Bits 8, 7 - - MBZ bits when NX is active. */
2733#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2734/** Bits 63, 7 - - MBZ bits when no NX. */
2735#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2736/** Bits 63 - NX - PAE - No execution flag. */
2737#define X86_PML4E_NX RT_BIT_64(63)
2738
2739/**
2740 * Page Map Level-4 Entry
2741 */
2742typedef struct X86PML4EBITS
2743{
2744 /** Flags whether(=1) or not the page is present. */
2745 uint32_t u1Present : 1;
2746 /** Read(=0) / Write(=1) flag. */
2747 uint32_t u1Write : 1;
2748 /** User(=1) / Supervisor (=0) flag. */
2749 uint32_t u1User : 1;
2750 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2751 uint32_t u1WriteThru : 1;
2752 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2753 uint32_t u1CacheDisable : 1;
2754 /** Accessed flag.
2755 * Indicates that the page have been read or written to. */
2756 uint32_t u1Accessed : 1;
2757 /** Chunk of reserved bits. */
2758 uint32_t u3Reserved : 3;
2759 /** Available for use to system software. */
2760 uint32_t u3Available : 3;
2761 /** Physical Page number of the next level - Low Part. Don't use! */
2762 uint32_t u20PageNoLow : 20;
2763 /** Physical Page number of the next level - High Part. Don't use! */
2764 uint32_t u20PageNoHigh : 20;
2765 /** MBZ bits */
2766 uint32_t u11Reserved : 11;
2767 /** No Execute flag. */
2768 uint32_t u1NoExecute : 1;
2769} X86PML4EBITS;
2770#ifndef VBOX_FOR_DTRACE_LIB
2771AssertCompileSize(X86PML4EBITS, 8);
2772#endif
2773/** Pointer to a page map level-4 entry. */
2774typedef X86PML4EBITS *PX86PML4EBITS;
2775/** Pointer to a const page map level-4 entry. */
2776typedef const X86PML4EBITS *PCX86PML4EBITS;
2777
2778/**
2779 * Page Map Level-4 Entry.
2780 */
2781typedef union X86PML4E
2782{
2783 /** Unsigned integer view. */
2784 X86PGPAEUINT u;
2785 /** Normal view. */
2786 X86PML4EBITS n;
2787 /** 8 bit unsigned integer view. */
2788 uint8_t au8[8];
2789 /** 16 bit unsigned integer view. */
2790 uint16_t au16[4];
2791 /** 32 bit unsigned integer view. */
2792 uint32_t au32[2];
2793} X86PML4E;
2794#ifndef VBOX_FOR_DTRACE_LIB
2795AssertCompileSize(X86PML4E, 8);
2796#endif
2797/** Pointer to a page map level-4 entry. */
2798typedef X86PML4E *PX86PML4E;
2799/** Pointer to a const page map level-4 entry. */
2800typedef const X86PML4E *PCX86PML4E;
2801
2802
2803/**
2804 * Page Map Level-4.
2805 */
2806typedef struct X86PML4
2807{
2808 /** PDE Array. */
2809 X86PML4E a[X86_PG_PAE_ENTRIES];
2810} X86PML4;
2811#ifndef VBOX_FOR_DTRACE_LIB
2812AssertCompileSize(X86PML4, 4096);
2813#endif
2814/** Pointer to a page map level-4. */
2815typedef X86PML4 *PX86PML4;
2816/** Pointer to a const page map level-4. */
2817typedef const X86PML4 *PCX86PML4;
2818
2819/** The page shift to get the PML4 index. */
2820#define X86_PML4_SHIFT 39
2821/** The PML4 index mask (apply to a shifted page address). */
2822#define X86_PML4_MASK 0x1ff
2823
2824/** @} */
2825
2826/** @} */
2827
2828/**
2829 * Intel PCID invalidation types.
2830 */
2831/** Individual address invalidation. */
2832#define X86_INVPCID_TYPE_INDV_ADDR 0
2833/** Single-context invalidation. */
2834#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2835/** All-context including globals invalidation. */
2836#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2837/** All-context excluding globals invalidation. */
2838#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2839/** The maximum valid invalidation type value. */
2840#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2841
2842/**
2843 * 32-bit protected mode FSTENV image.
2844 */
2845typedef struct X86FSTENV32P
2846{
2847 uint16_t FCW;
2848 uint16_t padding1;
2849 uint16_t FSW;
2850 uint16_t padding2;
2851 uint16_t FTW;
2852 uint16_t padding3;
2853 uint32_t FPUIP;
2854 uint16_t FPUCS;
2855 uint16_t FOP;
2856 uint32_t FPUDP;
2857 uint16_t FPUDS;
2858 uint16_t padding4;
2859} X86FSTENV32P;
2860/** Pointer to a 32-bit protected mode FSTENV image. */
2861typedef X86FSTENV32P *PX86FSTENV32P;
2862/** Pointer to a const 32-bit protected mode FSTENV image. */
2863typedef X86FSTENV32P const *PCX86FSTENV32P;
2864
2865
2866/**
2867 * 80-bit MMX/FPU register type.
2868 */
2869typedef struct X86FPUMMX
2870{
2871 uint8_t reg[10];
2872} X86FPUMMX;
2873#ifndef VBOX_FOR_DTRACE_LIB
2874AssertCompileSize(X86FPUMMX, 10);
2875#endif
2876/** Pointer to a 80-bit MMX/FPU register type. */
2877typedef X86FPUMMX *PX86FPUMMX;
2878/** Pointer to a const 80-bit MMX/FPU register type. */
2879typedef const X86FPUMMX *PCX86FPUMMX;
2880
2881/** FPU (x87) register. */
2882typedef union X86FPUREG
2883{
2884 /** MMX view. */
2885 uint64_t mmx;
2886 /** FPU view - todo. */
2887 X86FPUMMX fpu;
2888 /** Extended precision floating point view. */
2889 RTFLOAT80U r80;
2890 /** Extended precision floating point view v2 */
2891 RTFLOAT80U2 r80Ex;
2892 /** 8-bit view. */
2893 uint8_t au8[16];
2894 /** 16-bit view. */
2895 uint16_t au16[8];
2896 /** 32-bit view. */
2897 uint32_t au32[4];
2898 /** 64-bit view. */
2899 uint64_t au64[2];
2900 /** 128-bit view. (yeah, very helpful) */
2901 uint128_t au128[1];
2902} X86FPUREG;
2903#ifndef VBOX_FOR_DTRACE_LIB
2904AssertCompileSize(X86FPUREG, 16);
2905#endif
2906/** Pointer to a FPU register. */
2907typedef X86FPUREG *PX86FPUREG;
2908/** Pointer to a const FPU register. */
2909typedef X86FPUREG const *PCX86FPUREG;
2910
2911/**
2912 * XMM register union.
2913 */
2914typedef union X86XMMREG
2915{
2916 /** XMM Register view. */
2917 uint128_t xmm;
2918 /** 8-bit view. */
2919 uint8_t au8[16];
2920 /** 16-bit view. */
2921 uint16_t au16[8];
2922 /** 32-bit view. */
2923 uint32_t au32[4];
2924 /** 64-bit view. */
2925 uint64_t au64[2];
2926 /** 128-bit view. (yeah, very helpful) */
2927 uint128_t au128[1];
2928#ifndef VBOX_FOR_DTRACE_LIB
2929 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2930 RTUINT128U uXmm;
2931#endif
2932} X86XMMREG;
2933#ifndef VBOX_FOR_DTRACE_LIB
2934AssertCompileSize(X86XMMREG, 16);
2935#endif
2936/** Pointer to an XMM register state. */
2937typedef X86XMMREG *PX86XMMREG;
2938/** Pointer to a const XMM register state. */
2939typedef X86XMMREG const *PCX86XMMREG;
2940
2941/**
2942 * YMM register union.
2943 */
2944typedef union X86YMMREG
2945{
2946 /** 8-bit view. */
2947 uint8_t au8[32];
2948 /** 16-bit view. */
2949 uint16_t au16[16];
2950 /** 32-bit view. */
2951 uint32_t au32[8];
2952 /** 64-bit view. */
2953 uint64_t au64[4];
2954 /** 128-bit view. (yeah, very helpful) */
2955 uint128_t au128[2];
2956 /** XMM sub register view. */
2957 X86XMMREG aXmm[2];
2958} X86YMMREG;
2959#ifndef VBOX_FOR_DTRACE_LIB
2960AssertCompileSize(X86YMMREG, 32);
2961#endif
2962/** Pointer to an YMM register state. */
2963typedef X86YMMREG *PX86YMMREG;
2964/** Pointer to a const YMM register state. */
2965typedef X86YMMREG const *PCX86YMMREG;
2966
2967/**
2968 * ZMM register union.
2969 */
2970typedef union X86ZMMREG
2971{
2972 /** 8-bit view. */
2973 uint8_t au8[64];
2974 /** 16-bit view. */
2975 uint16_t au16[32];
2976 /** 32-bit view. */
2977 uint32_t au32[16];
2978 /** 64-bit view. */
2979 uint64_t au64[8];
2980 /** 128-bit view. (yeah, very helpful) */
2981 uint128_t au128[4];
2982 /** XMM sub register view. */
2983 X86XMMREG aXmm[4];
2984 /** YMM sub register view. */
2985 X86YMMREG aYmm[2];
2986} X86ZMMREG;
2987#ifndef VBOX_FOR_DTRACE_LIB
2988AssertCompileSize(X86ZMMREG, 64);
2989#endif
2990/** Pointer to an ZMM register state. */
2991typedef X86ZMMREG *PX86ZMMREG;
2992/** Pointer to a const ZMM register state. */
2993typedef X86ZMMREG const *PCX86ZMMREG;
2994
2995
2996/**
2997 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2998 * @todo verify this...
2999 */
3000#pragma pack(1)
3001typedef struct X86FPUSTATE
3002{
3003 /** 0x00 - Control word. */
3004 uint16_t FCW;
3005 /** 0x02 - Alignment word */
3006 uint16_t Dummy1;
3007 /** 0x04 - Status word. */
3008 uint16_t FSW;
3009 /** 0x06 - Alignment word */
3010 uint16_t Dummy2;
3011 /** 0x08 - Tag word */
3012 uint16_t FTW;
3013 /** 0x0a - Alignment word */
3014 uint16_t Dummy3;
3015
3016 /** 0x0c - Instruction pointer. */
3017 uint32_t FPUIP;
3018 /** 0x10 - Code selector. */
3019 uint16_t CS;
3020 /** 0x12 - Opcode. */
3021 uint16_t FOP;
3022 /** 0x14 - FOO. */
3023 uint32_t FPUOO;
3024 /** 0x18 - FOS. */
3025 uint32_t FPUOS;
3026 /** 0x1c - FPU register. */
3027 X86FPUREG regs[8];
3028} X86FPUSTATE;
3029#pragma pack()
3030/** Pointer to a FPU state. */
3031typedef X86FPUSTATE *PX86FPUSTATE;
3032/** Pointer to a const FPU state. */
3033typedef const X86FPUSTATE *PCX86FPUSTATE;
3034
3035/**
3036 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3037 */
3038#pragma pack(1)
3039typedef struct X86FXSTATE
3040{
3041 /** 0x00 - Control word. */
3042 uint16_t FCW;
3043 /** 0x02 - Status word. */
3044 uint16_t FSW;
3045 /** 0x04 - Tag word. (The upper byte is always zero.) */
3046 uint16_t FTW;
3047 /** 0x06 - Opcode. */
3048 uint16_t FOP;
3049 /** 0x08 - Instruction pointer. */
3050 uint32_t FPUIP;
3051 /** 0x0c - Code selector. */
3052 uint16_t CS;
3053 uint16_t Rsrvd1;
3054 /** 0x10 - Data pointer. */
3055 uint32_t FPUDP;
3056 /** 0x14 - Data segment */
3057 uint16_t DS;
3058 /** 0x16 */
3059 uint16_t Rsrvd2;
3060 /** 0x18 */
3061 uint32_t MXCSR;
3062 /** 0x1c */
3063 uint32_t MXCSR_MASK;
3064 /** 0x20 - FPU registers. */
3065 X86FPUREG aRegs[8];
3066 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3067 X86XMMREG aXMM[16];
3068 /* - offset 416 - */
3069 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3070 /* - offset 464 - Software usable reserved bits. */
3071 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3072} X86FXSTATE;
3073#pragma pack()
3074/** Pointer to a FPU Extended state. */
3075typedef X86FXSTATE *PX86FXSTATE;
3076/** Pointer to a const FPU Extended state. */
3077typedef const X86FXSTATE *PCX86FXSTATE;
3078
3079/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3080 * magic. Don't forget to update x86.mac if you change this! */
3081#define X86_OFF_FXSTATE_RSVD 0x1d0
3082/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3083 * forget to update x86.mac if you change this!
3084 * @todo r=bird: This has nothing what-so-ever to do here.... */
3085#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3086#ifndef VBOX_FOR_DTRACE_LIB
3087AssertCompileSize(X86FXSTATE, 512);
3088AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3089#endif
3090
3091/** @name FPU status word flags.
3092 * @{ */
3093/** Exception Flag: Invalid operation. */
3094#define X86_FSW_IE RT_BIT_32(0)
3095/** Exception Flag: Denormalized operand. */
3096#define X86_FSW_DE RT_BIT_32(1)
3097/** Exception Flag: Zero divide. */
3098#define X86_FSW_ZE RT_BIT_32(2)
3099/** Exception Flag: Overflow. */
3100#define X86_FSW_OE RT_BIT_32(3)
3101/** Exception Flag: Underflow. */
3102#define X86_FSW_UE RT_BIT_32(4)
3103/** Exception Flag: Precision. */
3104#define X86_FSW_PE RT_BIT_32(5)
3105/** Stack fault. */
3106#define X86_FSW_SF RT_BIT_32(6)
3107/** Error summary status. */
3108#define X86_FSW_ES RT_BIT_32(7)
3109/** Mask of exceptions flags, excluding the summary bit. */
3110#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3111/** Mask of exceptions flags, including the summary bit. */
3112#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3113/** Condition code 0. */
3114#define X86_FSW_C0 RT_BIT_32(8)
3115/** Condition code 1. */
3116#define X86_FSW_C1 RT_BIT_32(9)
3117/** Condition code 2. */
3118#define X86_FSW_C2 RT_BIT_32(10)
3119/** Top of the stack mask. */
3120#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3121/** TOP shift value. */
3122#define X86_FSW_TOP_SHIFT 11
3123/** Mask for getting TOP value after shifting it right. */
3124#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3125/** Get the TOP value. */
3126#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3127/** Condition code 3. */
3128#define X86_FSW_C3 RT_BIT_32(14)
3129/** Mask of exceptions flags, including the summary bit. */
3130#define X86_FSW_C_MASK UINT16_C(0x4700)
3131/** FPU busy. */
3132#define X86_FSW_B RT_BIT_32(15)
3133/** @} */
3134
3135
3136/** @name FPU control word flags.
3137 * @{ */
3138/** Exception Mask: Invalid operation. */
3139#define X86_FCW_IM RT_BIT_32(0)
3140/** Exception Mask: Denormalized operand. */
3141#define X86_FCW_DM RT_BIT_32(1)
3142/** Exception Mask: Zero divide. */
3143#define X86_FCW_ZM RT_BIT_32(2)
3144/** Exception Mask: Overflow. */
3145#define X86_FCW_OM RT_BIT_32(3)
3146/** Exception Mask: Underflow. */
3147#define X86_FCW_UM RT_BIT_32(4)
3148/** Exception Mask: Precision. */
3149#define X86_FCW_PM RT_BIT_32(5)
3150/** Mask all exceptions, the value typically loaded (by for instance fninit).
3151 * @remarks This includes reserved bit 6. */
3152#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3153/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3154#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3155/** Precision control mask. */
3156#define X86_FCW_PC_MASK UINT16_C(0x0300)
3157/** Precision control: 24-bit. */
3158#define X86_FCW_PC_24 UINT16_C(0x0000)
3159/** Precision control: Reserved. */
3160#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3161/** Precision control: 53-bit. */
3162#define X86_FCW_PC_53 UINT16_C(0x0200)
3163/** Precision control: 64-bit. */
3164#define X86_FCW_PC_64 UINT16_C(0x0300)
3165/** Rounding control mask. */
3166#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3167/** Rounding control: To nearest. */
3168#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3169/** Rounding control: Down. */
3170#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3171/** Rounding control: Up. */
3172#define X86_FCW_RC_UP UINT16_C(0x0800)
3173/** Rounding control: Towards zero. */
3174#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3175/** Bits which should be zero, apparently. */
3176#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3177/** @} */
3178
3179/** @name SSE MXCSR
3180 * @{ */
3181/** Exception Flag: Invalid operation. */
3182#define X86_MXCSR_IE RT_BIT_32(0)
3183/** Exception Flag: Denormalized operand. */
3184#define X86_MXCSR_DE RT_BIT_32(1)
3185/** Exception Flag: Zero divide. */
3186#define X86_MXCSR_ZE RT_BIT_32(2)
3187/** Exception Flag: Overflow. */
3188#define X86_MXCSR_OE RT_BIT_32(3)
3189/** Exception Flag: Underflow. */
3190#define X86_MXCSR_UE RT_BIT_32(4)
3191/** Exception Flag: Precision. */
3192#define X86_MXCSR_PE RT_BIT_32(5)
3193
3194/** Denormals are zero. */
3195#define X86_MXCSR_DAZ RT_BIT_32(6)
3196
3197/** Exception Mask: Invalid operation. */
3198#define X86_MXCSR_IM RT_BIT_32(7)
3199/** Exception Mask: Denormalized operand. */
3200#define X86_MXCSR_DM RT_BIT_32(8)
3201/** Exception Mask: Zero divide. */
3202#define X86_MXCSR_ZM RT_BIT_32(9)
3203/** Exception Mask: Overflow. */
3204#define X86_MXCSR_OM RT_BIT_32(10)
3205/** Exception Mask: Underflow. */
3206#define X86_MXCSR_UM RT_BIT_32(11)
3207/** Exception Mask: Precision. */
3208#define X86_MXCSR_PM RT_BIT_32(12)
3209
3210/** Rounding control mask. */
3211#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3212/** Rounding control: To nearest. */
3213#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3214/** Rounding control: Down. */
3215#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3216/** Rounding control: Up. */
3217#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3218/** Rounding control: Towards zero. */
3219#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3220
3221/** Flush-to-zero for masked underflow. */
3222#define X86_MXCSR_FZ RT_BIT_32(15)
3223
3224/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3225#define X86_MXCSR_MM RT_BIT_32(17)
3226/** @} */
3227
3228/**
3229 * XSAVE header.
3230 */
3231typedef struct X86XSAVEHDR
3232{
3233 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3234 uint64_t bmXState;
3235 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3236 uint64_t bmXComp;
3237 /** Reserved for furture extensions, probably MBZ. */
3238 uint64_t au64Reserved[6];
3239} X86XSAVEHDR;
3240#ifndef VBOX_FOR_DTRACE_LIB
3241AssertCompileSize(X86XSAVEHDR, 64);
3242#endif
3243/** Pointer to an XSAVE header. */
3244typedef X86XSAVEHDR *PX86XSAVEHDR;
3245/** Pointer to a const XSAVE header. */
3246typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3247
3248
3249/**
3250 * The high 128-bit YMM register state (XSAVE_C_YMM).
3251 * (The lower 128-bits being in X86FXSTATE.)
3252 */
3253typedef struct X86XSAVEYMMHI
3254{
3255 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3256 X86XMMREG aYmmHi[16];
3257} X86XSAVEYMMHI;
3258#ifndef VBOX_FOR_DTRACE_LIB
3259AssertCompileSize(X86XSAVEYMMHI, 256);
3260#endif
3261/** Pointer to a high 128-bit YMM register state. */
3262typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3263/** Pointer to a const high 128-bit YMM register state. */
3264typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3265
3266/**
3267 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3268 */
3269typedef struct X86XSAVEBNDREGS
3270{
3271 /** Array of registers (BND0...BND3). */
3272 struct
3273 {
3274 /** Lower bound. */
3275 uint64_t uLowerBound;
3276 /** Upper bound. */
3277 uint64_t uUpperBound;
3278 } aRegs[4];
3279} X86XSAVEBNDREGS;
3280#ifndef VBOX_FOR_DTRACE_LIB
3281AssertCompileSize(X86XSAVEBNDREGS, 64);
3282#endif
3283/** Pointer to a MPX bound register state. */
3284typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3285/** Pointer to a const MPX bound register state. */
3286typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3287
3288/**
3289 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3290 */
3291typedef struct X86XSAVEBNDCFG
3292{
3293 uint64_t fConfig;
3294 uint64_t fStatus;
3295} X86XSAVEBNDCFG;
3296#ifndef VBOX_FOR_DTRACE_LIB
3297AssertCompileSize(X86XSAVEBNDCFG, 16);
3298#endif
3299/** Pointer to a MPX bound config and status register state. */
3300typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3301/** Pointer to a const MPX bound config and status register state. */
3302typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3303
3304/**
3305 * AVX-512 opmask state (XSAVE_C_OPMASK).
3306 */
3307typedef struct X86XSAVEOPMASK
3308{
3309 /** The K0..K7 values. */
3310 uint64_t aKRegs[8];
3311} X86XSAVEOPMASK;
3312#ifndef VBOX_FOR_DTRACE_LIB
3313AssertCompileSize(X86XSAVEOPMASK, 64);
3314#endif
3315/** Pointer to a AVX-512 opmask state. */
3316typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3317/** Pointer to a const AVX-512 opmask state. */
3318typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3319
3320/**
3321 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3322 */
3323typedef struct X86XSAVEZMMHI256
3324{
3325 /** Upper 256-bits of ZMM0-15. */
3326 X86YMMREG aHi256Regs[16];
3327} X86XSAVEZMMHI256;
3328#ifndef VBOX_FOR_DTRACE_LIB
3329AssertCompileSize(X86XSAVEZMMHI256, 512);
3330#endif
3331/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3332typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3333/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3334typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3335
3336/**
3337 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3338 */
3339typedef struct X86XSAVEZMM16HI
3340{
3341 /** ZMM16 thru ZMM31. */
3342 X86ZMMREG aRegs[16];
3343} X86XSAVEZMM16HI;
3344#ifndef VBOX_FOR_DTRACE_LIB
3345AssertCompileSize(X86XSAVEZMM16HI, 1024);
3346#endif
3347/** Pointer to a state comprising ZMM16-32. */
3348typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3349/** Pointer to a const state comprising ZMM16-32. */
3350typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3351
3352/**
3353 * AMD Light weight profiling state (XSAVE_C_LWP).
3354 *
3355 * We probably won't play with this as AMD seems to be dropping from their "zen"
3356 * processor micro architecture.
3357 */
3358typedef struct X86XSAVELWP
3359{
3360 /** Details when needed. */
3361 uint64_t auLater[128/8];
3362} X86XSAVELWP;
3363#ifndef VBOX_FOR_DTRACE_LIB
3364AssertCompileSize(X86XSAVELWP, 128);
3365#endif
3366
3367
3368/**
3369 * x86 FPU/SSE/AVX/XXXX state.
3370 *
3371 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3372 * changes to this structure.
3373 */
3374typedef struct X86XSAVEAREA
3375{
3376 /** The x87 and SSE region (or legacy region if you like). */
3377 X86FXSTATE x87;
3378 /** The XSAVE header. */
3379 X86XSAVEHDR Hdr;
3380 /** Beyond the header, there isn't really a fixed layout, but we can
3381 generally assume the YMM (AVX) register extensions are present and
3382 follows immediately. */
3383 union
3384 {
3385 /** The high 128-bit AVX registers for easy access by IEM.
3386 * @note This ASSUMES they will always be here... */
3387 X86XSAVEYMMHI YmmHi;
3388
3389 /** This is a typical layout on intel CPUs (good for debuggers). */
3390 struct
3391 {
3392 X86XSAVEYMMHI YmmHi;
3393 X86XSAVEBNDREGS BndRegs;
3394 X86XSAVEBNDCFG BndCfg;
3395 uint8_t abFudgeToMatchDocs[0xB0];
3396 X86XSAVEOPMASK Opmask;
3397 X86XSAVEZMMHI256 ZmmHi256;
3398 X86XSAVEZMM16HI Zmm16Hi;
3399 } Intel;
3400
3401 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3402 struct
3403 {
3404 X86XSAVEYMMHI YmmHi;
3405 X86XSAVELWP Lwp;
3406 } AmdBd;
3407
3408 /** To enbling static deployments that have a reasonable chance of working for
3409 * the next 3-6 CPU generations without running short on space, we allocate a
3410 * lot of extra space here, making the structure a round 8KB in size. This
3411 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3412 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3413 uint8_t ab[8192 - 512 - 64];
3414 } u;
3415} X86XSAVEAREA;
3416#ifndef VBOX_FOR_DTRACE_LIB
3417AssertCompileSize(X86XSAVEAREA, 8192);
3418AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3419AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3420AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3421AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3422AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3423AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3424AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3425AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3426#endif
3427/** Pointer to a XSAVE area. */
3428typedef X86XSAVEAREA *PX86XSAVEAREA;
3429/** Pointer to a const XSAVE area. */
3430typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3431
3432
3433/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3434 * @{ */
3435/** Bit 0 - x87 - Legacy FPU state (bit number) */
3436#define XSAVE_C_X87_BIT 0
3437/** Bit 0 - x87 - Legacy FPU state. */
3438#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3439/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3440#define XSAVE_C_SSE_BIT 1
3441/** Bit 1 - SSE - 128-bit SSE state. */
3442#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3443/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3444#define XSAVE_C_YMM_BIT 2
3445/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3446#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3447/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3448#define XSAVE_C_BNDREGS_BIT 3
3449/** Bit 3 - BNDREGS - MPX bound register state. */
3450#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3451/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3452#define XSAVE_C_BNDCSR_BIT 4
3453/** Bit 4 - BNDCSR - MPX bound config and status state. */
3454#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3455/** Bit 5 - Opmask - opmask state (bit number). */
3456#define XSAVE_C_OPMASK_BIT 5
3457/** Bit 5 - Opmask - opmask state. */
3458#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3459/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3460#define XSAVE_C_ZMM_HI256_BIT 6
3461/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3462#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3463/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3464#define XSAVE_C_ZMM_16HI_BIT 7
3465/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3466#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3467/** Bit 9 - PKRU - Protection-key state (bit number). */
3468#define XSAVE_C_PKRU_BIT 9
3469/** Bit 9 - PKRU - Protection-key state. */
3470#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3471/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3472#define XSAVE_C_LWP_BIT 62
3473/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3474#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3475/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3476#define XSAVE_C_X_BIT 63
3477/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3478#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3479/** @} */
3480
3481
3482
3483/** @name Selector Descriptor
3484 * @{
3485 */
3486
3487#ifndef VBOX_FOR_DTRACE_LIB
3488/**
3489 * Descriptor attributes (as seen by VT-x).
3490 */
3491typedef struct X86DESCATTRBITS
3492{
3493 /** 00 - Segment Type. */
3494 unsigned u4Type : 4;
3495 /** 04 - Descriptor Type. System(=0) or code/data selector */
3496 unsigned u1DescType : 1;
3497 /** 05 - Descriptor Privilege level. */
3498 unsigned u2Dpl : 2;
3499 /** 07 - Flags selector present(=1) or not. */
3500 unsigned u1Present : 1;
3501 /** 08 - Segment limit 16-19. */
3502 unsigned u4LimitHigh : 4;
3503 /** 0c - Available for system software. */
3504 unsigned u1Available : 1;
3505 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3506 unsigned u1Long : 1;
3507 /** 0e - This flags meaning depends on the segment type. Try make sense out
3508 * of the intel manual yourself. */
3509 unsigned u1DefBig : 1;
3510 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3511 * clear byte. */
3512 unsigned u1Granularity : 1;
3513 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3514 unsigned u1Unusable : 1;
3515} X86DESCATTRBITS;
3516#endif /* !VBOX_FOR_DTRACE_LIB */
3517
3518/** @name X86DESCATTR masks
3519 * @{ */
3520#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3521#define X86DESCATTR_DT UINT32_C(0x00000010)
3522#define X86DESCATTR_DPL UINT32_C(0x00000060)
3523#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3524#define X86DESCATTR_P UINT32_C(0x00000080)
3525#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3526#define X86DESCATTR_AVL UINT32_C(0x00001000)
3527#define X86DESCATTR_L UINT32_C(0x00002000)
3528#define X86DESCATTR_D UINT32_C(0x00004000)
3529#define X86DESCATTR_G UINT32_C(0x00008000)
3530#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3531/** @} */
3532
3533#pragma pack(1)
3534typedef union X86DESCATTR
3535{
3536 /** Unsigned integer view. */
3537 uint32_t u;
3538#ifndef VBOX_FOR_DTRACE_LIB
3539 /** Normal view. */
3540 X86DESCATTRBITS n;
3541#endif
3542} X86DESCATTR;
3543#pragma pack()
3544/** Pointer to descriptor attributes. */
3545typedef X86DESCATTR *PX86DESCATTR;
3546/** Pointer to const descriptor attributes. */
3547typedef const X86DESCATTR *PCX86DESCATTR;
3548
3549#ifndef VBOX_FOR_DTRACE_LIB
3550
3551/**
3552 * Generic descriptor table entry
3553 */
3554#pragma pack(1)
3555typedef struct X86DESCGENERIC
3556{
3557 /** 00 - Limit - Low word. */
3558 unsigned u16LimitLow : 16;
3559 /** 10 - Base address - low word.
3560 * Don't try set this to 24 because MSC is doing stupid things then. */
3561 unsigned u16BaseLow : 16;
3562 /** 20 - Base address - first 8 bits of high word. */
3563 unsigned u8BaseHigh1 : 8;
3564 /** 28 - Segment Type. */
3565 unsigned u4Type : 4;
3566 /** 2c - Descriptor Type. System(=0) or code/data selector */
3567 unsigned u1DescType : 1;
3568 /** 2d - Descriptor Privilege level. */
3569 unsigned u2Dpl : 2;
3570 /** 2f - Flags selector present(=1) or not. */
3571 unsigned u1Present : 1;
3572 /** 30 - Segment limit 16-19. */
3573 unsigned u4LimitHigh : 4;
3574 /** 34 - Available for system software. */
3575 unsigned u1Available : 1;
3576 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3577 unsigned u1Long : 1;
3578 /** 36 - This flags meaning depends on the segment type. Try make sense out
3579 * of the intel manual yourself. */
3580 unsigned u1DefBig : 1;
3581 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3582 * clear byte. */
3583 unsigned u1Granularity : 1;
3584 /** 38 - Base address - highest 8 bits. */
3585 unsigned u8BaseHigh2 : 8;
3586} X86DESCGENERIC;
3587#pragma pack()
3588/** Pointer to a generic descriptor entry. */
3589typedef X86DESCGENERIC *PX86DESCGENERIC;
3590/** Pointer to a const generic descriptor entry. */
3591typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3592
3593/** @name Bit offsets of X86DESCGENERIC members.
3594 * @{*/
3595#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3596#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3597#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3598#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3599#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3600#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3601#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3602#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3603#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3604#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3605#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3606#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3607#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3608/** @} */
3609
3610
3611/** @name LAR mask
3612 * @{ */
3613#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3614#define X86LAR_F_DT UINT16_C( 0x1000)
3615#define X86LAR_F_DPL UINT16_C( 0x6000)
3616#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3617#define X86LAR_F_P UINT16_C( 0x8000)
3618#define X86LAR_F_AVL UINT32_C(0x00100000)
3619#define X86LAR_F_L UINT32_C(0x00200000)
3620#define X86LAR_F_D UINT32_C(0x00400000)
3621#define X86LAR_F_G UINT32_C(0x00800000)
3622/** @} */
3623
3624
3625/**
3626 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3627 */
3628typedef struct X86DESCGATE
3629{
3630 /** 00 - Target code segment offset - Low word.
3631 * Ignored if task-gate. */
3632 unsigned u16OffsetLow : 16;
3633 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3634 * TSS selector if task-gate. */
3635 unsigned u16Sel : 16;
3636 /** 20 - Number of parameters for a call-gate.
3637 * Ignored if interrupt-, trap- or task-gate. */
3638 unsigned u5ParmCount : 5;
3639 /** 25 - Reserved / ignored. */
3640 unsigned u3Reserved : 3;
3641 /** 28 - Segment Type. */
3642 unsigned u4Type : 4;
3643 /** 2c - Descriptor Type (0 = system). */
3644 unsigned u1DescType : 1;
3645 /** 2d - Descriptor Privilege level. */
3646 unsigned u2Dpl : 2;
3647 /** 2f - Flags selector present(=1) or not. */
3648 unsigned u1Present : 1;
3649 /** 30 - Target code segment offset - High word.
3650 * Ignored if task-gate. */
3651 unsigned u16OffsetHigh : 16;
3652} X86DESCGATE;
3653/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3654typedef X86DESCGATE *PX86DESCGATE;
3655/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3656typedef const X86DESCGATE *PCX86DESCGATE;
3657
3658#endif /* VBOX_FOR_DTRACE_LIB */
3659
3660/**
3661 * Descriptor table entry.
3662 */
3663#pragma pack(1)
3664typedef union X86DESC
3665{
3666#ifndef VBOX_FOR_DTRACE_LIB
3667 /** Generic descriptor view. */
3668 X86DESCGENERIC Gen;
3669 /** Gate descriptor view. */
3670 X86DESCGATE Gate;
3671#endif
3672
3673 /** 8 bit unsigned integer view. */
3674 uint8_t au8[8];
3675 /** 16 bit unsigned integer view. */
3676 uint16_t au16[4];
3677 /** 32 bit unsigned integer view. */
3678 uint32_t au32[2];
3679 /** 64 bit unsigned integer view. */
3680 uint64_t au64[1];
3681 /** Unsigned integer view. */
3682 uint64_t u;
3683} X86DESC;
3684#ifndef VBOX_FOR_DTRACE_LIB
3685AssertCompileSize(X86DESC, 8);
3686#endif
3687#pragma pack()
3688/** Pointer to descriptor table entry. */
3689typedef X86DESC *PX86DESC;
3690/** Pointer to const descriptor table entry. */
3691typedef const X86DESC *PCX86DESC;
3692
3693/** @def X86DESC_BASE
3694 * Return the base address of a descriptor.
3695 */
3696#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3697 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3698 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3699 | ( (a_pDesc)->Gen.u16BaseLow ) )
3700
3701/** @def X86DESC_LIMIT
3702 * Return the limit of a descriptor.
3703 */
3704#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3705 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3706 | ( (a_pDesc)->Gen.u16LimitLow ) )
3707
3708/** @def X86DESC_LIMIT_G
3709 * Return the limit of a descriptor with the granularity bit taken into account.
3710 * @returns Selector limit (uint32_t).
3711 * @param a_pDesc Pointer to the descriptor.
3712 */
3713#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3714 ( (a_pDesc)->Gen.u1Granularity \
3715 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3716 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3717 )
3718
3719/** @def X86DESC_GET_HID_ATTR
3720 * Get the descriptor attributes for the hidden register.
3721 */
3722#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3723 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3724
3725#ifndef VBOX_FOR_DTRACE_LIB
3726
3727/**
3728 * 64 bits generic descriptor table entry
3729 * Note: most of these bits have no meaning in long mode.
3730 */
3731#pragma pack(1)
3732typedef struct X86DESC64GENERIC
3733{
3734 /** Limit - Low word - *IGNORED*. */
3735 uint32_t u16LimitLow : 16;
3736 /** Base address - low word. - *IGNORED*
3737 * Don't try set this to 24 because MSC is doing stupid things then. */
3738 uint32_t u16BaseLow : 16;
3739 /** Base address - first 8 bits of high word. - *IGNORED* */
3740 uint32_t u8BaseHigh1 : 8;
3741 /** Segment Type. */
3742 uint32_t u4Type : 4;
3743 /** Descriptor Type. System(=0) or code/data selector */
3744 uint32_t u1DescType : 1;
3745 /** Descriptor Privilege level. */
3746 uint32_t u2Dpl : 2;
3747 /** Flags selector present(=1) or not. */
3748 uint32_t u1Present : 1;
3749 /** Segment limit 16-19. - *IGNORED* */
3750 uint32_t u4LimitHigh : 4;
3751 /** Available for system software. - *IGNORED* */
3752 uint32_t u1Available : 1;
3753 /** Long mode flag. */
3754 uint32_t u1Long : 1;
3755 /** This flags meaning depends on the segment type. Try make sense out
3756 * of the intel manual yourself. */
3757 uint32_t u1DefBig : 1;
3758 /** Granularity of the limit. If set 4KB granularity is used, if
3759 * clear byte. - *IGNORED* */
3760 uint32_t u1Granularity : 1;
3761 /** Base address - highest 8 bits. - *IGNORED* */
3762 uint32_t u8BaseHigh2 : 8;
3763 /** Base address - bits 63-32. */
3764 uint32_t u32BaseHigh3 : 32;
3765 uint32_t u8Reserved : 8;
3766 uint32_t u5Zeros : 5;
3767 uint32_t u19Reserved : 19;
3768} X86DESC64GENERIC;
3769#pragma pack()
3770/** Pointer to a generic descriptor entry. */
3771typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3772/** Pointer to a const generic descriptor entry. */
3773typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3774
3775/**
3776 * System descriptor table entry (64 bits)
3777 *
3778 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3779 */
3780#pragma pack(1)
3781typedef struct X86DESC64SYSTEM
3782{
3783 /** Limit - Low word. */
3784 uint32_t u16LimitLow : 16;
3785 /** Base address - low word.
3786 * Don't try set this to 24 because MSC is doing stupid things then. */
3787 uint32_t u16BaseLow : 16;
3788 /** Base address - first 8 bits of high word. */
3789 uint32_t u8BaseHigh1 : 8;
3790 /** Segment Type. */
3791 uint32_t u4Type : 4;
3792 /** Descriptor Type. System(=0) or code/data selector */
3793 uint32_t u1DescType : 1;
3794 /** Descriptor Privilege level. */
3795 uint32_t u2Dpl : 2;
3796 /** Flags selector present(=1) or not. */
3797 uint32_t u1Present : 1;
3798 /** Segment limit 16-19. */
3799 uint32_t u4LimitHigh : 4;
3800 /** Available for system software. */
3801 uint32_t u1Available : 1;
3802 /** Reserved - 0. */
3803 uint32_t u1Reserved : 1;
3804 /** This flags meaning depends on the segment type. Try make sense out
3805 * of the intel manual yourself. */
3806 uint32_t u1DefBig : 1;
3807 /** Granularity of the limit. If set 4KB granularity is used, if
3808 * clear byte. */
3809 uint32_t u1Granularity : 1;
3810 /** Base address - bits 31-24. */
3811 uint32_t u8BaseHigh2 : 8;
3812 /** Base address - bits 63-32. */
3813 uint32_t u32BaseHigh3 : 32;
3814 uint32_t u8Reserved : 8;
3815 uint32_t u5Zeros : 5;
3816 uint32_t u19Reserved : 19;
3817} X86DESC64SYSTEM;
3818#pragma pack()
3819/** Pointer to a system descriptor entry. */
3820typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3821/** Pointer to a const system descriptor entry. */
3822typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3823
3824/**
3825 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3826 */
3827typedef struct X86DESC64GATE
3828{
3829 /** Target code segment offset - Low word. */
3830 uint32_t u16OffsetLow : 16;
3831 /** Target code segment selector. */
3832 uint32_t u16Sel : 16;
3833 /** Interrupt stack table for interrupt- and trap-gates.
3834 * Ignored by call-gates. */
3835 uint32_t u3IST : 3;
3836 /** Reserved / ignored. */
3837 uint32_t u5Reserved : 5;
3838 /** Segment Type. */
3839 uint32_t u4Type : 4;
3840 /** Descriptor Type (0 = system). */
3841 uint32_t u1DescType : 1;
3842 /** Descriptor Privilege level. */
3843 uint32_t u2Dpl : 2;
3844 /** Flags selector present(=1) or not. */
3845 uint32_t u1Present : 1;
3846 /** Target code segment offset - High word.
3847 * Ignored if task-gate. */
3848 uint32_t u16OffsetHigh : 16;
3849 /** Target code segment offset - Top dword.
3850 * Ignored if task-gate. */
3851 uint32_t u32OffsetTop : 32;
3852 /** Reserved / ignored / must be zero.
3853 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3854 uint32_t u32Reserved : 32;
3855} X86DESC64GATE;
3856AssertCompileSize(X86DESC64GATE, 16);
3857/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3858typedef X86DESC64GATE *PX86DESC64GATE;
3859/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3860typedef const X86DESC64GATE *PCX86DESC64GATE;
3861
3862#endif /* VBOX_FOR_DTRACE_LIB */
3863
3864/**
3865 * Descriptor table entry.
3866 */
3867#pragma pack(1)
3868typedef union X86DESC64
3869{
3870#ifndef VBOX_FOR_DTRACE_LIB
3871 /** Generic descriptor view. */
3872 X86DESC64GENERIC Gen;
3873 /** System descriptor view. */
3874 X86DESC64SYSTEM System;
3875 /** Gate descriptor view. */
3876 X86DESC64GATE Gate;
3877#endif
3878
3879 /** 8 bit unsigned integer view. */
3880 uint8_t au8[16];
3881 /** 16 bit unsigned integer view. */
3882 uint16_t au16[8];
3883 /** 32 bit unsigned integer view. */
3884 uint32_t au32[4];
3885 /** 64 bit unsigned integer view. */
3886 uint64_t au64[2];
3887} X86DESC64;
3888#ifndef VBOX_FOR_DTRACE_LIB
3889AssertCompileSize(X86DESC64, 16);
3890#endif
3891#pragma pack()
3892/** Pointer to descriptor table entry. */
3893typedef X86DESC64 *PX86DESC64;
3894/** Pointer to const descriptor table entry. */
3895typedef const X86DESC64 *PCX86DESC64;
3896
3897/** @def X86DESC64_BASE
3898 * Return the base of a 64-bit descriptor.
3899 */
3900#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3901 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3902 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3903 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3904 | ( (a_pDesc)->Gen.u16BaseLow ) )
3905
3906
3907
3908/** @name Host system descriptor table entry - Use with care!
3909 * @{ */
3910/** Host system descriptor table entry. */
3911#if HC_ARCH_BITS == 64
3912typedef X86DESC64 X86DESCHC;
3913#else
3914typedef X86DESC X86DESCHC;
3915#endif
3916/** Pointer to a host system descriptor table entry. */
3917#if HC_ARCH_BITS == 64
3918typedef PX86DESC64 PX86DESCHC;
3919#else
3920typedef PX86DESC PX86DESCHC;
3921#endif
3922/** Pointer to a const host system descriptor table entry. */
3923#if HC_ARCH_BITS == 64
3924typedef PCX86DESC64 PCX86DESCHC;
3925#else
3926typedef PCX86DESC PCX86DESCHC;
3927#endif
3928/** @} */
3929
3930
3931/** @name Selector Descriptor Types.
3932 * @{
3933 */
3934
3935/** @name Non-System Selector Types.
3936 * @{ */
3937/** Code(=set)/Data(=clear) bit. */
3938#define X86_SEL_TYPE_CODE 8
3939/** Memory(=set)/System(=clear) bit. */
3940#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3941/** Accessed bit. */
3942#define X86_SEL_TYPE_ACCESSED 1
3943/** Expand down bit (for data selectors only). */
3944#define X86_SEL_TYPE_DOWN 4
3945/** Conforming bit (for code selectors only). */
3946#define X86_SEL_TYPE_CONF 4
3947/** Write bit (for data selectors only). */
3948#define X86_SEL_TYPE_WRITE 2
3949/** Read bit (for code selectors only). */
3950#define X86_SEL_TYPE_READ 2
3951/** The bit number of the code segment read bit (relative to u4Type). */
3952#define X86_SEL_TYPE_READ_BIT 1
3953
3954/** Read only selector type. */
3955#define X86_SEL_TYPE_RO 0
3956/** Accessed read only selector type. */
3957#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3958/** Read write selector type. */
3959#define X86_SEL_TYPE_RW 2
3960/** Accessed read write selector type. */
3961#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3962/** Expand down read only selector type. */
3963#define X86_SEL_TYPE_RO_DOWN 4
3964/** Accessed expand down read only selector type. */
3965#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3966/** Expand down read write selector type. */
3967#define X86_SEL_TYPE_RW_DOWN 6
3968/** Accessed expand down read write selector type. */
3969#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3970/** Execute only selector type. */
3971#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3972/** Accessed execute only selector type. */
3973#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3974/** Execute and read selector type. */
3975#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3976/** Accessed execute and read selector type. */
3977#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3978/** Conforming execute only selector type. */
3979#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3980/** Accessed Conforming execute only selector type. */
3981#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3982/** Conforming execute and write selector type. */
3983#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3984/** Accessed Conforming execute and write selector type. */
3985#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3986/** @} */
3987
3988
3989/** @name System Selector Types.
3990 * @{ */
3991/** The TSS busy bit mask. */
3992#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3993
3994/** Undefined system selector type. */
3995#define X86_SEL_TYPE_SYS_UNDEFINED 0
3996/** 286 TSS selector. */
3997#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3998/** LDT selector. */
3999#define X86_SEL_TYPE_SYS_LDT 2
4000/** 286 TSS selector - Busy. */
4001#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4002/** 286 Callgate selector. */
4003#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4004/** Taskgate selector. */
4005#define X86_SEL_TYPE_SYS_TASK_GATE 5
4006/** 286 Interrupt gate selector. */
4007#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4008/** 286 Trapgate selector. */
4009#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4010/** Undefined system selector. */
4011#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4012/** 386 TSS selector. */
4013#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4014/** Undefined system selector. */
4015#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4016/** 386 TSS selector - Busy. */
4017#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4018/** 386 Callgate selector. */
4019#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4020/** Undefined system selector. */
4021#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4022/** 386 Interruptgate selector. */
4023#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4024/** 386 Trapgate selector. */
4025#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4026/** @} */
4027
4028/** @name AMD64 System Selector Types.
4029 * @{ */
4030/** LDT selector. */
4031#define AMD64_SEL_TYPE_SYS_LDT 2
4032/** TSS selector - Busy. */
4033#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4034/** TSS selector - Busy. */
4035#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4036/** Callgate selector. */
4037#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4038/** Interruptgate selector. */
4039#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4040/** Trapgate selector. */
4041#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4042/** @} */
4043
4044/** @} */
4045
4046
4047/** @name Descriptor Table Entry Flag Masks.
4048 * These are for the 2nd 32-bit word of a descriptor.
4049 * @{ */
4050/** Bits 8-11 - TYPE - Descriptor type mask. */
4051#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
4052/** Bit 12 - S - System (=0) or Code/Data (=1). */
4053#define X86_DESC_S RT_BIT_32(12)
4054/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4055#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
4056/** Bit 15 - P - Present. */
4057#define X86_DESC_P RT_BIT_32(15)
4058/** Bit 20 - AVL - Available for system software. */
4059#define X86_DESC_AVL RT_BIT_32(20)
4060/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4061#define X86_DESC_DB RT_BIT_32(22)
4062/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4063 * used, if clear byte. */
4064#define X86_DESC_G RT_BIT_32(23)
4065/** @} */
4066
4067/** @} */
4068
4069
4070/** @name Task Segments.
4071 * @{
4072 */
4073
4074/**
4075 * The minimum TSS descriptor limit for 286 tasks.
4076 */
4077#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4078
4079/**
4080 * The minimum TSS descriptor segment limit for 386 tasks.
4081 */
4082#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4083
4084/**
4085 * 16-bit Task Segment (TSS).
4086 */
4087#pragma pack(1)
4088typedef struct X86TSS16
4089{
4090 /** Back link to previous task. (static) */
4091 RTSEL selPrev;
4092 /** Ring-0 stack pointer. (static) */
4093 uint16_t sp0;
4094 /** Ring-0 stack segment. (static) */
4095 RTSEL ss0;
4096 /** Ring-1 stack pointer. (static) */
4097 uint16_t sp1;
4098 /** Ring-1 stack segment. (static) */
4099 RTSEL ss1;
4100 /** Ring-2 stack pointer. (static) */
4101 uint16_t sp2;
4102 /** Ring-2 stack segment. (static) */
4103 RTSEL ss2;
4104 /** IP before task switch. */
4105 uint16_t ip;
4106 /** FLAGS before task switch. */
4107 uint16_t flags;
4108 /** AX before task switch. */
4109 uint16_t ax;
4110 /** CX before task switch. */
4111 uint16_t cx;
4112 /** DX before task switch. */
4113 uint16_t dx;
4114 /** BX before task switch. */
4115 uint16_t bx;
4116 /** SP before task switch. */
4117 uint16_t sp;
4118 /** BP before task switch. */
4119 uint16_t bp;
4120 /** SI before task switch. */
4121 uint16_t si;
4122 /** DI before task switch. */
4123 uint16_t di;
4124 /** ES before task switch. */
4125 RTSEL es;
4126 /** CS before task switch. */
4127 RTSEL cs;
4128 /** SS before task switch. */
4129 RTSEL ss;
4130 /** DS before task switch. */
4131 RTSEL ds;
4132 /** LDTR before task switch. */
4133 RTSEL selLdt;
4134} X86TSS16;
4135#ifndef VBOX_FOR_DTRACE_LIB
4136AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4137#endif
4138#pragma pack()
4139/** Pointer to a 16-bit task segment. */
4140typedef X86TSS16 *PX86TSS16;
4141/** Pointer to a const 16-bit task segment. */
4142typedef const X86TSS16 *PCX86TSS16;
4143
4144
4145/**
4146 * 32-bit Task Segment (TSS).
4147 */
4148#pragma pack(1)
4149typedef struct X86TSS32
4150{
4151 /** Back link to previous task. (static) */
4152 RTSEL selPrev;
4153 uint16_t padding1;
4154 /** Ring-0 stack pointer. (static) */
4155 uint32_t esp0;
4156 /** Ring-0 stack segment. (static) */
4157 RTSEL ss0;
4158 uint16_t padding_ss0;
4159 /** Ring-1 stack pointer. (static) */
4160 uint32_t esp1;
4161 /** Ring-1 stack segment. (static) */
4162 RTSEL ss1;
4163 uint16_t padding_ss1;
4164 /** Ring-2 stack pointer. (static) */
4165 uint32_t esp2;
4166 /** Ring-2 stack segment. (static) */
4167 RTSEL ss2;
4168 uint16_t padding_ss2;
4169 /** Page directory for the task. (static) */
4170 uint32_t cr3;
4171 /** EIP before task switch. */
4172 uint32_t eip;
4173 /** EFLAGS before task switch. */
4174 uint32_t eflags;
4175 /** EAX before task switch. */
4176 uint32_t eax;
4177 /** ECX before task switch. */
4178 uint32_t ecx;
4179 /** EDX before task switch. */
4180 uint32_t edx;
4181 /** EBX before task switch. */
4182 uint32_t ebx;
4183 /** ESP before task switch. */
4184 uint32_t esp;
4185 /** EBP before task switch. */
4186 uint32_t ebp;
4187 /** ESI before task switch. */
4188 uint32_t esi;
4189 /** EDI before task switch. */
4190 uint32_t edi;
4191 /** ES before task switch. */
4192 RTSEL es;
4193 uint16_t padding_es;
4194 /** CS before task switch. */
4195 RTSEL cs;
4196 uint16_t padding_cs;
4197 /** SS before task switch. */
4198 RTSEL ss;
4199 uint16_t padding_ss;
4200 /** DS before task switch. */
4201 RTSEL ds;
4202 uint16_t padding_ds;
4203 /** FS before task switch. */
4204 RTSEL fs;
4205 uint16_t padding_fs;
4206 /** GS before task switch. */
4207 RTSEL gs;
4208 uint16_t padding_gs;
4209 /** LDTR before task switch. */
4210 RTSEL selLdt;
4211 uint16_t padding_ldt;
4212 /** Debug trap flag */
4213 uint16_t fDebugTrap;
4214 /** Offset relative to the TSS of the start of the I/O Bitmap
4215 * and the end of the interrupt redirection bitmap. */
4216 uint16_t offIoBitmap;
4217} X86TSS32;
4218#pragma pack()
4219/** Pointer to task segment. */
4220typedef X86TSS32 *PX86TSS32;
4221/** Pointer to const task segment. */
4222typedef const X86TSS32 *PCX86TSS32;
4223#ifndef VBOX_FOR_DTRACE_LIB
4224AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4225AssertCompileMemberOffset(X86TSS32, cr3, 28);
4226AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4227#endif
4228
4229/**
4230 * 64-bit Task segment.
4231 */
4232#pragma pack(1)
4233typedef struct X86TSS64
4234{
4235 /** Reserved. */
4236 uint32_t u32Reserved;
4237 /** Ring-0 stack pointer. (static) */
4238 uint64_t rsp0;
4239 /** Ring-1 stack pointer. (static) */
4240 uint64_t rsp1;
4241 /** Ring-2 stack pointer. (static) */
4242 uint64_t rsp2;
4243 /** Reserved. */
4244 uint32_t u32Reserved2[2];
4245 /* IST */
4246 uint64_t ist1;
4247 uint64_t ist2;
4248 uint64_t ist3;
4249 uint64_t ist4;
4250 uint64_t ist5;
4251 uint64_t ist6;
4252 uint64_t ist7;
4253 /* Reserved. */
4254 uint16_t u16Reserved[5];
4255 /** Offset relative to the TSS of the start of the I/O Bitmap
4256 * and the end of the interrupt redirection bitmap. */
4257 uint16_t offIoBitmap;
4258} X86TSS64;
4259#pragma pack()
4260/** Pointer to a 64-bit task segment. */
4261typedef X86TSS64 *PX86TSS64;
4262/** Pointer to a const 64-bit task segment. */
4263typedef const X86TSS64 *PCX86TSS64;
4264#ifndef VBOX_FOR_DTRACE_LIB
4265AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4266#endif
4267
4268/** @} */
4269
4270
4271/** @name Selectors.
4272 * @{
4273 */
4274
4275/**
4276 * The shift used to convert a selector from and to index an index (C).
4277 */
4278#define X86_SEL_SHIFT 3
4279
4280/**
4281 * The mask used to mask off the table indicator and RPL of an selector.
4282 */
4283#define X86_SEL_MASK 0xfff8U
4284
4285/**
4286 * The mask used to mask off the RPL of an selector.
4287 * This is suitable for checking for NULL selectors.
4288 */
4289#define X86_SEL_MASK_OFF_RPL 0xfffcU
4290
4291/**
4292 * The bit indicating that a selector is in the LDT and not in the GDT.
4293 */
4294#define X86_SEL_LDT 0x0004U
4295
4296/**
4297 * The bit mask for getting the RPL of a selector.
4298 */
4299#define X86_SEL_RPL 0x0003U
4300
4301/**
4302 * The mask covering both RPL and LDT.
4303 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4304 * checks.
4305 */
4306#define X86_SEL_RPL_LDT 0x0007U
4307
4308/** @} */
4309
4310
4311/**
4312 * x86 Exceptions/Faults/Traps.
4313 */
4314typedef enum X86XCPT
4315{
4316 /** \#DE - Divide error. */
4317 X86_XCPT_DE = 0x00,
4318 /** \#DB - Debug event (single step, DRx, ..) */
4319 X86_XCPT_DB = 0x01,
4320 /** NMI - Non-Maskable Interrupt */
4321 X86_XCPT_NMI = 0x02,
4322 /** \#BP - Breakpoint (INT3). */
4323 X86_XCPT_BP = 0x03,
4324 /** \#OF - Overflow (INTO). */
4325 X86_XCPT_OF = 0x04,
4326 /** \#BR - Bound range exceeded (BOUND). */
4327 X86_XCPT_BR = 0x05,
4328 /** \#UD - Undefined opcode. */
4329 X86_XCPT_UD = 0x06,
4330 /** \#NM - Device not available (math coprocessor device). */
4331 X86_XCPT_NM = 0x07,
4332 /** \#DF - Double fault. */
4333 X86_XCPT_DF = 0x08,
4334 /** ??? - Coprocessor segment overrun (obsolete). */
4335 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4336 /** \#TS - Taskswitch (TSS). */
4337 X86_XCPT_TS = 0x0a,
4338 /** \#NP - Segment no present. */
4339 X86_XCPT_NP = 0x0b,
4340 /** \#SS - Stack segment fault. */
4341 X86_XCPT_SS = 0x0c,
4342 /** \#GP - General protection fault. */
4343 X86_XCPT_GP = 0x0d,
4344 /** \#PF - Page fault. */
4345 X86_XCPT_PF = 0x0e,
4346 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4347 /** \#MF - Math fault (FPU). */
4348 X86_XCPT_MF = 0x10,
4349 /** \#AC - Alignment check. */
4350 X86_XCPT_AC = 0x11,
4351 /** \#MC - Machine check. */
4352 X86_XCPT_MC = 0x12,
4353 /** \#XF - SIMD Floating-Pointer Exception. */
4354 X86_XCPT_XF = 0x13,
4355 /** \#VE - Virtualization Exception. */
4356 X86_XCPT_VE = 0x14,
4357 /** \#SX - Security Exception. */
4358 X86_XCPT_SX = 0x1e
4359} X86XCPT;
4360/** Pointer to a x86 exception code. */
4361typedef X86XCPT *PX86XCPT;
4362/** Pointer to a const x86 exception code. */
4363typedef const X86XCPT *PCX86XCPT;
4364/** The last valid (currently reserved) exception value. */
4365#define X86_XCPT_LAST 0x1f
4366
4367
4368/** @name Trap Error Codes
4369 * @{
4370 */
4371/** External indicator. */
4372#define X86_TRAP_ERR_EXTERNAL 1
4373/** IDT indicator. */
4374#define X86_TRAP_ERR_IDT 2
4375/** Descriptor table indicator - If set LDT, if clear GDT. */
4376#define X86_TRAP_ERR_TI 4
4377/** Mask for getting the selector. */
4378#define X86_TRAP_ERR_SEL_MASK 0xfff8
4379/** Shift for getting the selector table index (C type index). */
4380#define X86_TRAP_ERR_SEL_SHIFT 3
4381/** @} */
4382
4383
4384/** @name \#PF Trap Error Codes
4385 * @{
4386 */
4387/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4388#define X86_TRAP_PF_P RT_BIT_32(0)
4389/** Bit 1 - R/W - Read (clear) or write (set) access. */
4390#define X86_TRAP_PF_RW RT_BIT_32(1)
4391/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4392#define X86_TRAP_PF_US RT_BIT_32(2)
4393/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4394#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4395/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4396#define X86_TRAP_PF_ID RT_BIT_32(4)
4397/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4398#define X86_TRAP_PF_PK RT_BIT_32(5)
4399/** @} */
4400
4401#pragma pack(1)
4402/**
4403 * 16-bit IDTR.
4404 */
4405typedef struct X86IDTR16
4406{
4407 /** Offset. */
4408 uint16_t offSel;
4409 /** Selector. */
4410 uint16_t uSel;
4411} X86IDTR16, *PX86IDTR16;
4412#pragma pack()
4413
4414#pragma pack(1)
4415/**
4416 * 32-bit IDTR/GDTR.
4417 */
4418typedef struct X86XDTR32
4419{
4420 /** Size of the descriptor table. */
4421 uint16_t cb;
4422 /** Address of the descriptor table. */
4423#ifndef VBOX_FOR_DTRACE_LIB
4424 uint32_t uAddr;
4425#else
4426 uint16_t au16Addr[2];
4427#endif
4428} X86XDTR32, *PX86XDTR32;
4429#pragma pack()
4430
4431#pragma pack(1)
4432/**
4433 * 64-bit IDTR/GDTR.
4434 */
4435typedef struct X86XDTR64
4436{
4437 /** Size of the descriptor table. */
4438 uint16_t cb;
4439 /** Address of the descriptor table. */
4440#ifndef VBOX_FOR_DTRACE_LIB
4441 uint64_t uAddr;
4442#else
4443 uint16_t au16Addr[4];
4444#endif
4445} X86XDTR64, *PX86XDTR64;
4446#pragma pack()
4447
4448
4449/** @name ModR/M
4450 * @{ */
4451#define X86_MODRM_RM_MASK UINT8_C(0x07)
4452#define X86_MODRM_REG_MASK UINT8_C(0x38)
4453#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4454#define X86_MODRM_REG_SHIFT 3
4455#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4456#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4457#define X86_MODRM_MOD_SHIFT 6
4458#ifndef VBOX_FOR_DTRACE_LIB
4459AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4460AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4461AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4462/** @def X86_MODRM_MAKE
4463 * @param a_Mod The mod value (0..3).
4464 * @param a_Reg The register value (0..7).
4465 * @param a_RegMem The register or memory value (0..7). */
4466# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4467#endif
4468/** @} */
4469
4470/** @name SIB
4471 * @{ */
4472#define X86_SIB_BASE_MASK UINT8_C(0x07)
4473#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4474#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4475#define X86_SIB_INDEX_SHIFT 3
4476#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4477#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4478#define X86_SIB_SCALE_SHIFT 6
4479#ifndef VBOX_FOR_DTRACE_LIB
4480AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4481AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4482AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4483#endif
4484/** @} */
4485
4486/** @name General register indexes.
4487 * @{ */
4488#define X86_GREG_xAX 0
4489#define X86_GREG_xCX 1
4490#define X86_GREG_xDX 2
4491#define X86_GREG_xBX 3
4492#define X86_GREG_xSP 4
4493#define X86_GREG_xBP 5
4494#define X86_GREG_xSI 6
4495#define X86_GREG_xDI 7
4496#define X86_GREG_x8 8
4497#define X86_GREG_x9 9
4498#define X86_GREG_x10 10
4499#define X86_GREG_x11 11
4500#define X86_GREG_x12 12
4501#define X86_GREG_x13 13
4502#define X86_GREG_x14 14
4503#define X86_GREG_x15 15
4504/** @} */
4505/** General register count. */
4506#define X86_GREG_COUNT 16
4507
4508/** @name X86_SREG_XXX - Segment register indexes.
4509 * @{ */
4510#define X86_SREG_ES 0
4511#define X86_SREG_CS 1
4512#define X86_SREG_SS 2
4513#define X86_SREG_DS 3
4514#define X86_SREG_FS 4
4515#define X86_SREG_GS 5
4516/** @} */
4517/** Segment register count. */
4518#define X86_SREG_COUNT 6
4519
4520
4521/** @name X86_OP_XXX - Prefixes
4522 * @{ */
4523#define X86_OP_PRF_CS UINT8_C(0x2e)
4524#define X86_OP_PRF_SS UINT8_C(0x36)
4525#define X86_OP_PRF_DS UINT8_C(0x3e)
4526#define X86_OP_PRF_ES UINT8_C(0x26)
4527#define X86_OP_PRF_FS UINT8_C(0x64)
4528#define X86_OP_PRF_GS UINT8_C(0x65)
4529#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4530#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4531#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4532#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4533#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4534#define X86_OP_REX_B UINT8_C(0x41)
4535#define X86_OP_REX_X UINT8_C(0x42)
4536#define X86_OP_REX_R UINT8_C(0x44)
4537#define X86_OP_REX_W UINT8_C(0x48)
4538/** @} */
4539
4540
4541/** @} */
4542
4543#endif /* !IPRT_INCLUDED_x86_h */
4544
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